ohci.c revision 1.254.2.28
1 /* $NetBSD: ohci.c,v 1.254.2.28 2015/11/15 13:59:52 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * USB Open Host Controller driver. 38 * 39 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 40 * USB spec: http://www.usb.org/developers/docs/ 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.254.2.28 2015/11/15 13:59:52 skrll Exp $"); 45 46 #include "opt_usb.h" 47 48 #include <sys/param.h> 49 50 #include <sys/cpu.h> 51 #include <sys/device.h> 52 #include <sys/kernel.h> 53 #include <sys/kmem.h> 54 #include <sys/proc.h> 55 #include <sys/queue.h> 56 #include <sys/select.h> 57 #include <sys/sysctl.h> 58 #include <sys/systm.h> 59 60 #include <machine/endian.h> 61 62 #include <dev/usb/usb.h> 63 #include <dev/usb/usbdi.h> 64 #include <dev/usb/usbdivar.h> 65 #include <dev/usb/usb_mem.h> 66 #include <dev/usb/usb_quirks.h> 67 68 #include <dev/usb/ohcireg.h> 69 #include <dev/usb/ohcivar.h> 70 #include <dev/usb/usbroothub.h> 71 #include <dev/usb/usbhist.h> 72 73 #ifdef USB_DEBUG 74 #ifndef OHCI_DEBUG 75 #define ohcidebug 0 76 #else 77 static int ohcidebug = 0; 78 79 SYSCTL_SETUP(sysctl_hw_ohci_setup, "sysctl hw.ohci setup") 80 { 81 int err; 82 const struct sysctlnode *rnode; 83 const struct sysctlnode *cnode; 84 85 err = sysctl_createv(clog, 0, NULL, &rnode, 86 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ohci", 87 SYSCTL_DESCR("ohci global controls"), 88 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 89 90 if (err) 91 goto fail; 92 93 /* control debugging printfs */ 94 err = sysctl_createv(clog, 0, &rnode, &cnode, 95 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 96 "debug", SYSCTL_DESCR("Enable debugging output"), 97 NULL, 0, &ohcidebug, sizeof(ohcidebug), CTL_CREATE, CTL_EOL); 98 if (err) 99 goto fail; 100 101 return; 102 fail: 103 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 104 } 105 106 #endif /* OHCI_DEBUG */ 107 #endif /* USB_DEBUG */ 108 109 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ohcidebug,FMT,A,B,C,D) 110 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ohcidebug,N,FMT,A,B,C,D) 111 #define OHCIHIST_FUNC() USBHIST_FUNC() 112 #define OHCIHIST_CALLED(name) USBHIST_CALLED(ohcidebug) 113 114 #if BYTE_ORDER == BIG_ENDIAN 115 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 116 #else 117 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 118 #endif 119 120 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 121 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 122 #define HTOO16(val) O16TOH(val) 123 #define HTOO32(val) O32TOH(val) 124 125 struct ohci_pipe; 126 127 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 128 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 129 130 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 131 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 132 133 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 134 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 135 136 Static void ohci_free_std_chain(ohci_softc_t *, ohci_soft_td_t *, 137 ohci_soft_td_t *); 138 Static usbd_status ohci_alloc_std_chain(struct ohci_pipe *, 139 ohci_softc_t *, int, int, struct usbd_xfer *, 140 ohci_soft_td_t *, ohci_soft_td_t **); 141 142 Static usbd_status ohci_open(struct usbd_pipe *); 143 Static void ohci_poll(struct usbd_bus *); 144 Static void ohci_softintr(void *); 145 Static void ohci_waitintr(ohci_softc_t *, struct usbd_xfer *); 146 Static void ohci_rhsc(ohci_softc_t *, struct usbd_xfer *); 147 Static void ohci_rhsc_softint(void *); 148 149 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 150 ohci_soft_ed_t *); 151 152 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 153 ohci_soft_ed_t *); 154 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 155 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 156 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 157 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 158 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 159 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 160 161 Static usbd_status ohci_setup_isoc(struct usbd_pipe *); 162 Static void ohci_device_isoc_enter(struct usbd_xfer *); 163 164 Static struct usbd_xfer * 165 ohci_allocx(struct usbd_bus *, unsigned int); 166 Static void ohci_freex(struct usbd_bus *, struct usbd_xfer *); 167 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 168 Static int ohci_roothub_ctrl(struct usbd_bus *, 169 usb_device_request_t *, void *, int); 170 171 Static usbd_status ohci_root_intr_transfer(struct usbd_xfer *); 172 Static usbd_status ohci_root_intr_start(struct usbd_xfer *); 173 Static void ohci_root_intr_abort(struct usbd_xfer *); 174 Static void ohci_root_intr_close(struct usbd_pipe *); 175 Static void ohci_root_intr_done(struct usbd_xfer *); 176 177 Static usbd_status ohci_device_ctrl_transfer(struct usbd_xfer *); 178 Static usbd_status ohci_device_ctrl_start(struct usbd_xfer *); 179 Static void ohci_device_ctrl_abort(struct usbd_xfer *); 180 Static void ohci_device_ctrl_close(struct usbd_pipe *); 181 Static void ohci_device_ctrl_done(struct usbd_xfer *); 182 183 Static usbd_status ohci_device_bulk_transfer(struct usbd_xfer *); 184 Static usbd_status ohci_device_bulk_start(struct usbd_xfer *); 185 Static void ohci_device_bulk_abort(struct usbd_xfer *); 186 Static void ohci_device_bulk_close(struct usbd_pipe *); 187 Static void ohci_device_bulk_done(struct usbd_xfer *); 188 189 Static usbd_status ohci_device_intr_transfer(struct usbd_xfer *); 190 Static usbd_status ohci_device_intr_start(struct usbd_xfer *); 191 Static void ohci_device_intr_abort(struct usbd_xfer *); 192 Static void ohci_device_intr_close(struct usbd_pipe *); 193 Static void ohci_device_intr_done(struct usbd_xfer *); 194 195 Static usbd_status ohci_device_isoc_transfer(struct usbd_xfer *); 196 Static usbd_status ohci_device_isoc_start(struct usbd_xfer *); 197 Static void ohci_device_isoc_abort(struct usbd_xfer *); 198 Static void ohci_device_isoc_close(struct usbd_pipe *); 199 Static void ohci_device_isoc_done(struct usbd_xfer *); 200 201 Static usbd_status ohci_device_setintr(ohci_softc_t *, 202 struct ohci_pipe *, int); 203 204 Static void ohci_timeout(void *); 205 Static void ohci_timeout_task(void *); 206 Static void ohci_rhsc_enable(void *); 207 208 Static void ohci_close_pipe(struct usbd_pipe *, ohci_soft_ed_t *); 209 Static void ohci_abort_xfer(struct usbd_xfer *, usbd_status); 210 211 Static void ohci_device_clear_toggle(struct usbd_pipe *); 212 Static void ohci_noop(struct usbd_pipe *); 213 214 #ifdef OHCI_DEBUG 215 Static void ohci_dumpregs(ohci_softc_t *); 216 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 217 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 218 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 219 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 220 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 221 #endif 222 223 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 224 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 225 #define OWRITE1(sc, r, x) \ 226 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 227 #define OWRITE2(sc, r, x) \ 228 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 229 #define OWRITE4(sc, r, x) \ 230 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 231 232 static __inline uint32_t 233 OREAD4(ohci_softc_t *sc, bus_size_t r) 234 { 235 236 OBARR(sc); 237 return bus_space_read_4(sc->iot, sc->ioh, r); 238 } 239 240 /* Reverse the bits in a value 0 .. 31 */ 241 Static uint8_t revbits[OHCI_NO_INTRS] = 242 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 243 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 244 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 245 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 246 247 struct ohci_pipe { 248 struct usbd_pipe pipe; 249 ohci_soft_ed_t *sed; 250 union { 251 ohci_soft_td_t *td; 252 ohci_soft_itd_t *itd; 253 } tail; 254 /* Info needed for different pipe kinds. */ 255 union { 256 /* Control pipe */ 257 struct { 258 usb_dma_t reqdma; 259 } ctrl; 260 /* Interrupt pipe */ 261 struct { 262 int nslots; 263 int pos; 264 } intr; 265 /* Isochronous pipe */ 266 struct isoc { 267 int next, inuse; 268 } isoc; 269 }; 270 }; 271 272 Static const struct usbd_bus_methods ohci_bus_methods = { 273 .ubm_open = ohci_open, 274 .ubm_softint = ohci_softintr, 275 .ubm_dopoll = ohci_poll, 276 .ubm_allocx = ohci_allocx, 277 .ubm_freex = ohci_freex, 278 .ubm_getlock = ohci_get_lock, 279 .ubm_rhctrl = ohci_roothub_ctrl, 280 }; 281 282 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 283 .upm_transfer = ohci_root_intr_transfer, 284 .upm_start = ohci_root_intr_start, 285 .upm_abort = ohci_root_intr_abort, 286 .upm_close = ohci_root_intr_close, 287 .upm_cleartoggle = ohci_noop, 288 .upm_done = ohci_root_intr_done, 289 }; 290 291 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 292 .upm_transfer = ohci_device_ctrl_transfer, 293 .upm_start = ohci_device_ctrl_start, 294 .upm_abort = ohci_device_ctrl_abort, 295 .upm_close = ohci_device_ctrl_close, 296 .upm_cleartoggle = ohci_noop, 297 .upm_done = ohci_device_ctrl_done, 298 }; 299 300 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 301 .upm_transfer = ohci_device_intr_transfer, 302 .upm_start = ohci_device_intr_start, 303 .upm_abort = ohci_device_intr_abort, 304 .upm_close = ohci_device_intr_close, 305 .upm_cleartoggle = ohci_device_clear_toggle, 306 .upm_done = ohci_device_intr_done, 307 }; 308 309 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 310 .upm_transfer = ohci_device_bulk_transfer, 311 .upm_start = ohci_device_bulk_start, 312 .upm_abort = ohci_device_bulk_abort, 313 .upm_close = ohci_device_bulk_close, 314 .upm_cleartoggle = ohci_device_clear_toggle, 315 .upm_done = ohci_device_bulk_done, 316 }; 317 318 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 319 .upm_transfer = ohci_device_isoc_transfer, 320 .upm_start = ohci_device_isoc_start, 321 .upm_abort = ohci_device_isoc_abort, 322 .upm_close = ohci_device_isoc_close, 323 .upm_cleartoggle = ohci_noop, 324 .upm_done = ohci_device_isoc_done, 325 }; 326 327 int 328 ohci_activate(device_t self, enum devact act) 329 { 330 struct ohci_softc *sc = device_private(self); 331 332 switch (act) { 333 case DVACT_DEACTIVATE: 334 sc->sc_dying = 1; 335 return 0; 336 default: 337 return EOPNOTSUPP; 338 } 339 } 340 341 void 342 ohci_childdet(device_t self, device_t child) 343 { 344 struct ohci_softc *sc = device_private(self); 345 346 KASSERT(sc->sc_child == child); 347 sc->sc_child = NULL; 348 } 349 350 int 351 ohci_detach(struct ohci_softc *sc, int flags) 352 { 353 int rv = 0; 354 355 if (sc->sc_child != NULL) 356 rv = config_detach(sc->sc_child, flags); 357 358 if (rv != 0) 359 return rv; 360 361 callout_halt(&sc->sc_tmo_rhsc, &sc->sc_lock); 362 363 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 364 callout_destroy(&sc->sc_tmo_rhsc); 365 366 softint_disestablish(sc->sc_rhsc_si); 367 368 cv_destroy(&sc->sc_softwake_cv); 369 370 mutex_destroy(&sc->sc_lock); 371 mutex_destroy(&sc->sc_intr_lock); 372 373 if (sc->sc_hcca != NULL) 374 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 375 pool_cache_destroy(sc->sc_xferpool); 376 377 return rv; 378 } 379 380 ohci_soft_ed_t * 381 ohci_alloc_sed(ohci_softc_t *sc) 382 { 383 ohci_soft_ed_t *sed; 384 usbd_status err; 385 int i, offs; 386 usb_dma_t dma; 387 388 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 389 390 if (sc->sc_freeeds == NULL) { 391 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 392 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 393 OHCI_ED_ALIGN, &dma); 394 if (err) 395 return 0; 396 for (i = 0; i < OHCI_SED_CHUNK; i++) { 397 offs = i * OHCI_SED_SIZE; 398 sed = KERNADDR(&dma, offs); 399 sed->physaddr = DMAADDR(&dma, offs); 400 sed->dma = dma; 401 sed->offs = offs; 402 sed->next = sc->sc_freeeds; 403 sc->sc_freeeds = sed; 404 } 405 } 406 sed = sc->sc_freeeds; 407 sc->sc_freeeds = sed->next; 408 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 409 sed->next = 0; 410 return sed; 411 } 412 413 void 414 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 415 { 416 sed->next = sc->sc_freeeds; 417 sc->sc_freeeds = sed; 418 } 419 420 ohci_soft_td_t * 421 ohci_alloc_std(ohci_softc_t *sc) 422 { 423 ohci_soft_td_t *std; 424 usbd_status err; 425 int i, offs; 426 usb_dma_t dma; 427 428 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 429 430 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 431 432 if (sc->sc_freetds == NULL) { 433 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 434 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 435 OHCI_TD_ALIGN, &dma); 436 if (err) 437 return NULL; 438 for(i = 0; i < OHCI_STD_CHUNK; i++) { 439 offs = i * OHCI_STD_SIZE; 440 std = KERNADDR(&dma, offs); 441 std->physaddr = DMAADDR(&dma, offs); 442 std->dma = dma; 443 std->offs = offs; 444 std->nexttd = sc->sc_freetds; 445 sc->sc_freetds = std; 446 } 447 } 448 449 std = sc->sc_freetds; 450 sc->sc_freetds = std->nexttd; 451 memset(&std->td, 0, sizeof(ohci_td_t)); 452 std->nexttd = NULL; 453 std->xfer = NULL; 454 ohci_hash_add_td(sc, std); 455 456 return std; 457 } 458 459 void 460 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 461 { 462 463 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 464 465 ohci_hash_rem_td(sc, std); 466 std->nexttd = sc->sc_freetds; 467 sc->sc_freetds = std; 468 } 469 470 usbd_status 471 ohci_alloc_std_chain(struct ohci_pipe *opipe, ohci_softc_t *sc, 472 int alen, int rd, struct usbd_xfer *xfer, 473 ohci_soft_td_t *sp, ohci_soft_td_t **ep) 474 { 475 ohci_soft_td_t *next, *cur; 476 ohci_physaddr_t dataphys, dataphysend; 477 uint32_t tdflags; 478 int len, curlen; 479 usb_dma_t *dma = &xfer->ux_dmabuf; 480 uint16_t flags = xfer->ux_flags; 481 482 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 483 DPRINTF("start len=%d", alen, 0, 0, 0); 484 485 KASSERT(mutex_owned(&sc->sc_lock)); 486 487 DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d", 488 opipe->pipe.up_dev->ud_addr, 489 UE_GET_ADDR(opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress), 490 alen, opipe->pipe.up_dev->ud_speed); 491 492 len = alen; 493 cur = sp; 494 dataphys = DMAADDR(dma, 0); 495 dataphysend = OHCI_PAGE(dataphys + len - 1); 496 usb_syncmem(dma, 0, len, 497 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 498 tdflags = HTOO32( 499 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 500 (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) | 501 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 502 503 for (;;) { 504 next = ohci_alloc_std(sc); 505 if (next == NULL) 506 goto nomem; 507 508 /* The OHCI hardware can handle at most one page crossing. */ 509 if (OHCI_PAGE(dataphys) == dataphysend || 510 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 511 /* we can handle it in this TD */ 512 curlen = len; 513 } else { 514 /* must use multiple TDs, fill as much as possible. */ 515 curlen = 2 * OHCI_PAGE_SIZE - 516 (dataphys & (OHCI_PAGE_SIZE-1)); 517 /* the length must be a multiple of the max size */ 518 curlen -= curlen % UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 519 KASSERT(curlen != 0); 520 } 521 DPRINTFN(4, "dataphys=0x%08x dataphysend=0x%08x " 522 "len=%d curlen=%d", dataphys, dataphysend, len, curlen); 523 len -= curlen; 524 525 cur->td.td_flags = tdflags; 526 cur->td.td_cbp = HTOO32(dataphys); 527 cur->nexttd = next; 528 cur->td.td_nexttd = HTOO32(next->physaddr); 529 cur->td.td_be = HTOO32(dataphys + curlen - 1); 530 cur->len = curlen; 531 cur->flags = OHCI_ADD_LEN; 532 cur->xfer = xfer; 533 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 534 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 535 DPRINTFN(10, "cbp=0x%08x be=0x%08x", dataphys, 536 dataphys + curlen - 1, 0, 0); 537 if (len == 0) 538 break; 539 DPRINTFN(10, "extend chain", 0, 0, 0, 0); 540 dataphys += curlen; 541 cur = next; 542 } 543 if (!rd && (flags & USBD_FORCE_SHORT_XFER) && 544 alen % UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize) == 0) { 545 /* Force a 0 length transfer at the end. */ 546 547 cur = next; 548 next = ohci_alloc_std(sc); 549 if (next == NULL) 550 goto nomem; 551 552 cur->td.td_flags = tdflags; 553 cur->td.td_cbp = 0; /* indicate 0 length packet */ 554 cur->nexttd = next; 555 cur->td.td_nexttd = HTOO32(next->physaddr); 556 cur->td.td_be = ~0; 557 cur->len = 0; 558 cur->flags = 0; 559 cur->xfer = xfer; 560 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 561 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 562 DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0); 563 } 564 *ep = cur; 565 566 return USBD_NORMAL_COMPLETION; 567 568 nomem: 569 570 /* Don't free sp - let the caller do that */ 571 ohci_free_std_chain(sc, sp->nexttd, NULL); 572 573 return USBD_NOMEM; 574 } 575 576 Static void 577 ohci_free_std_chain(ohci_softc_t *sc, ohci_soft_td_t *std, 578 ohci_soft_td_t *stdend) 579 { 580 ohci_soft_td_t *p; 581 582 for (; std != stdend; std = p) { 583 p = std->nexttd; 584 ohci_free_std(sc, std); 585 } 586 } 587 588 ohci_soft_itd_t * 589 ohci_alloc_sitd(ohci_softc_t *sc) 590 { 591 ohci_soft_itd_t *sitd; 592 usbd_status err; 593 int i, offs; 594 usb_dma_t dma; 595 596 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 597 598 if (sc->sc_freeitds == NULL) { 599 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 600 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 601 OHCI_ITD_ALIGN, &dma); 602 if (err) 603 return NULL; 604 for(i = 0; i < OHCI_SITD_CHUNK; i++) { 605 offs = i * OHCI_SITD_SIZE; 606 sitd = KERNADDR(&dma, offs); 607 sitd->physaddr = DMAADDR(&dma, offs); 608 sitd->dma = dma; 609 sitd->offs = offs; 610 sitd->nextitd = sc->sc_freeitds; 611 sc->sc_freeitds = sitd; 612 } 613 } 614 615 sitd = sc->sc_freeitds; 616 sc->sc_freeitds = sitd->nextitd; 617 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 618 sitd->nextitd = NULL; 619 sitd->xfer = NULL; 620 ohci_hash_add_itd(sc, sitd); 621 622 #ifdef DIAGNOSTIC 623 sitd->isdone = 0; 624 #endif 625 626 return sitd; 627 } 628 629 void 630 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 631 { 632 633 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 634 DPRINTFN(10, "sitd=%p", sitd, 0, 0, 0); 635 636 KASSERT(sitd->isdone); 637 #ifdef DIAGNOSTIC 638 /* Warn double free */ 639 sitd->isdone = 0; 640 #endif 641 642 ohci_hash_rem_itd(sc, sitd); 643 sitd->nextitd = sc->sc_freeitds; 644 sc->sc_freeitds = sitd; 645 } 646 647 int 648 ohci_init(ohci_softc_t *sc) 649 { 650 ohci_soft_ed_t *sed, *psed; 651 usbd_status err; 652 int i; 653 uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */; 654 655 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 656 657 aprint_normal_dev(sc->sc_dev, ""); 658 659 sc->sc_hcca = NULL; 660 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 661 662 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 663 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 664 cv_init(&sc->sc_softwake_cv, "ohciab"); 665 666 sc->sc_rhsc_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 667 ohci_rhsc_softint, sc); 668 669 for (i = 0; i < OHCI_HASH_SIZE; i++) 670 LIST_INIT(&sc->sc_hash_tds[i]); 671 for (i = 0; i < OHCI_HASH_SIZE; i++) 672 LIST_INIT(&sc->sc_hash_itds[i]); 673 674 sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0, 675 "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL); 676 677 rev = OREAD4(sc, OHCI_REVISION); 678 aprint_normal("OHCI version %d.%d%s\n", 679 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 680 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 681 682 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 683 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 684 sc->sc_bus.ub_revision = USBREV_UNKNOWN; 685 return -1; 686 } 687 sc->sc_bus.ub_revision = USBREV_1_0; 688 sc->sc_bus.ub_usedma = true; 689 690 /* XXX determine alignment by R/W */ 691 /* Allocate the HCCA area. */ 692 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 693 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 694 if (err) { 695 sc->sc_hcca = NULL; 696 return err; 697 } 698 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 699 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 700 701 sc->sc_eintrs = OHCI_NORMAL_INTRS; 702 703 /* Allocate dummy ED that starts the control list. */ 704 sc->sc_ctrl_head = ohci_alloc_sed(sc); 705 if (sc->sc_ctrl_head == NULL) { 706 err = ENOMEM; 707 goto bad1; 708 } 709 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 710 711 /* Allocate dummy ED that starts the bulk list. */ 712 sc->sc_bulk_head = ohci_alloc_sed(sc); 713 if (sc->sc_bulk_head == NULL) { 714 err = ENOMEM; 715 goto bad2; 716 } 717 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 718 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 719 sizeof(sc->sc_bulk_head->ed), 720 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 721 722 /* Allocate dummy ED that starts the isochronous list. */ 723 sc->sc_isoc_head = ohci_alloc_sed(sc); 724 if (sc->sc_isoc_head == NULL) { 725 err = ENOMEM; 726 goto bad3; 727 } 728 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 729 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 730 sizeof(sc->sc_isoc_head->ed), 731 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 732 733 /* Allocate all the dummy EDs that make up the interrupt tree. */ 734 for (i = 0; i < OHCI_NO_EDS; i++) { 735 sed = ohci_alloc_sed(sc); 736 if (sed == NULL) { 737 while (--i >= 0) 738 ohci_free_sed(sc, sc->sc_eds[i]); 739 err = ENOMEM; 740 goto bad4; 741 } 742 /* All ED fields are set to 0. */ 743 sc->sc_eds[i] = sed; 744 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 745 if (i != 0) 746 psed = sc->sc_eds[(i-1) / 2]; 747 else 748 psed= sc->sc_isoc_head; 749 sed->next = psed; 750 sed->ed.ed_nexted = HTOO32(psed->physaddr); 751 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 752 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 753 } 754 /* 755 * Fill HCCA interrupt table. The bit reversal is to get 756 * the tree set up properly to spread the interrupts. 757 */ 758 for (i = 0; i < OHCI_NO_INTRS; i++) 759 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 760 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 761 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 762 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 763 764 #ifdef OHCI_DEBUG 765 DPRINTFN(15, "--- dump start ---", 0, 0, 0 ,0); 766 if (ohcidebug > 15) { 767 for (i = 0; i < OHCI_NO_EDS; i++) { 768 DPRINTFN(15, "ed#%d ", i, 0, 0, 0); 769 ohci_dump_ed(sc, sc->sc_eds[i]); 770 } 771 DPRINTFN(15, "iso", 0, 0, 0 ,0); 772 ohci_dump_ed(sc, sc->sc_isoc_head); 773 } 774 DPRINTFN(15, "--- dump end ---", 0, 0, 0 ,0); 775 #endif 776 777 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 778 ctl = OREAD4(sc, OHCI_CONTROL); 779 rwc = ctl & OHCI_RWC; 780 fm = OREAD4(sc, OHCI_FM_INTERVAL); 781 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 782 /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */ 783 784 /* Determine in what context we are running. */ 785 if (ctl & OHCI_IR) { 786 /* SMM active, request change */ 787 DPRINTF("SMM active, request owner change", 0, 0, 0, 0); 788 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 789 (OHCI_OC | OHCI_MIE)) 790 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 791 s = OREAD4(sc, OHCI_COMMAND_STATUS); 792 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 793 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 794 usb_delay_ms(&sc->sc_bus, 1); 795 ctl = OREAD4(sc, OHCI_CONTROL); 796 } 797 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 798 if ((ctl & OHCI_IR) == 0) { 799 aprint_error_dev(sc->sc_dev, 800 "SMM does not respond, resetting\n"); 801 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 802 goto reset; 803 } 804 #if 0 805 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 806 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 807 /* BIOS started controller. */ 808 DPRINTF("BIOS active", 0, 0, 0, 0); 809 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 810 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 811 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 812 } 813 #endif 814 } else { 815 DPRINTF("cold started", 0 ,0 ,0 ,0); 816 reset: 817 /* Controller was cold started. */ 818 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 819 } 820 821 /* 822 * This reset should not be necessary according to the OHCI spec, but 823 * without it some controllers do not start. 824 */ 825 DPRINTF("sc %p: resetting", sc, 0, 0, 0); 826 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 827 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 828 829 /* We now own the host controller and the bus has been reset. */ 830 831 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 832 /* Nominal time for a reset is 10 us. */ 833 for (i = 0; i < 10; i++) { 834 delay(10); 835 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 836 if (!hcr) 837 break; 838 } 839 if (hcr) { 840 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 841 err = EIO; 842 goto bad5; 843 } 844 #ifdef OHCI_DEBUG 845 if (ohcidebug > 15) 846 ohci_dumpregs(sc); 847 #endif 848 849 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 850 851 /* Set up HC registers. */ 852 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 853 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 854 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 855 /* disable all interrupts and then switch on all desired interrupts */ 856 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 857 /* switch on desired functional features */ 858 ctl = OREAD4(sc, OHCI_CONTROL); 859 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 860 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 861 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 862 /* And finally start it! */ 863 OWRITE4(sc, OHCI_CONTROL, ctl); 864 865 /* 866 * The controller is now OPERATIONAL. Set a some final 867 * registers that should be set earlier, but that the 868 * controller ignores when in the SUSPEND state. 869 */ 870 ival = OHCI_GET_IVAL(fm); 871 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 872 fm |= OHCI_FSMPS(ival) | ival; 873 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 874 per = OHCI_PERIODIC(ival); /* 90% periodic */ 875 OWRITE4(sc, OHCI_PERIODIC_START, per); 876 877 if (sc->sc_flags & OHCIF_SUPERIO) { 878 /* no overcurrent protection */ 879 desca |= OHCI_NOCP; 880 /* 881 * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning 882 * that 883 * - ports are always power switched 884 * - don't wait for powered root hub port 885 */ 886 desca &= ~(__SHIFTIN(0xff, OHCI_POTPGT_MASK) | OHCI_NPS); 887 } 888 889 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 890 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 891 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 892 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 893 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 894 895 /* 896 * The AMD756 requires a delay before re-reading the register, 897 * otherwise it will occasionally report 0 ports. 898 */ 899 sc->sc_noport = 0; 900 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 901 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 902 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 903 } 904 905 #ifdef OHCI_DEBUG 906 if (ohcidebug > 5) 907 ohci_dumpregs(sc); 908 #endif 909 910 /* Set up the bus struct. */ 911 sc->sc_bus.ub_methods = &ohci_bus_methods; 912 sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe); 913 914 sc->sc_control = sc->sc_intre = 0; 915 916 /* Finally, turn on interrupts. */ 917 DPRINTF("enabling %#x", sc->sc_eintrs | OHCI_MIE, 0, 0, 0); 918 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 919 920 return 0; 921 922 bad5: 923 for (i = 0; i < OHCI_NO_EDS; i++) 924 ohci_free_sed(sc, sc->sc_eds[i]); 925 bad4: 926 ohci_free_sed(sc, sc->sc_isoc_head); 927 bad3: 928 ohci_free_sed(sc, sc->sc_bulk_head); 929 bad2: 930 ohci_free_sed(sc, sc->sc_ctrl_head); 931 bad1: 932 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 933 sc->sc_hcca = NULL; 934 return err; 935 } 936 937 struct usbd_xfer * 938 ohci_allocx(struct usbd_bus *bus, unsigned int nframes) 939 { 940 ohci_softc_t *sc = OHCI_BUS2SC(bus); 941 struct usbd_xfer *xfer; 942 943 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 944 if (xfer != NULL) { 945 memset(xfer, 0, sizeof(struct ohci_xfer)); 946 #ifdef DIAGNOSTIC 947 xfer->ux_state = XFER_BUSY; 948 #endif 949 } 950 return xfer; 951 } 952 953 void 954 ohci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 955 { 956 ohci_softc_t *sc = OHCI_BUS2SC(bus); 957 958 KASSERTMSG(xfer->ux_state == XFER_BUSY, 959 "xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state); 960 #ifdef DIAGNOSTIC 961 xfer->ux_state = XFER_FREE; 962 #endif 963 pool_cache_put(sc->sc_xferpool, xfer); 964 } 965 966 Static void 967 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 968 { 969 ohci_softc_t *sc = OHCI_BUS2SC(bus); 970 971 *lock = &sc->sc_lock; 972 } 973 974 /* 975 * Shut down the controller when the system is going down. 976 */ 977 bool 978 ohci_shutdown(device_t self, int flags) 979 { 980 ohci_softc_t *sc = device_private(self); 981 982 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 983 984 DPRINTF("stopping the HC", 0, 0, 0, 0); 985 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 986 return true; 987 } 988 989 bool 990 ohci_resume(device_t dv, const pmf_qual_t *qual) 991 { 992 ohci_softc_t *sc = device_private(dv); 993 uint32_t ctl; 994 995 mutex_spin_enter(&sc->sc_intr_lock); 996 sc->sc_bus.ub_usepolling++; 997 mutex_spin_exit(&sc->sc_intr_lock); 998 999 /* Some broken BIOSes do not recover these values */ 1000 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1001 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1002 sc->sc_ctrl_head->physaddr); 1003 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1004 sc->sc_bulk_head->physaddr); 1005 if (sc->sc_intre) 1006 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1007 (OHCI_ALL_INTRS | OHCI_MIE)); 1008 if (sc->sc_control) 1009 ctl = sc->sc_control; 1010 else 1011 ctl = OREAD4(sc, OHCI_CONTROL); 1012 ctl |= OHCI_HCFS_RESUME; 1013 OWRITE4(sc, OHCI_CONTROL, ctl); 1014 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1015 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1016 OWRITE4(sc, OHCI_CONTROL, ctl); 1017 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1018 sc->sc_control = sc->sc_intre = 0; 1019 1020 mutex_spin_enter(&sc->sc_intr_lock); 1021 sc->sc_bus.ub_usepolling--; 1022 mutex_spin_exit(&sc->sc_intr_lock); 1023 1024 return true; 1025 } 1026 1027 bool 1028 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1029 { 1030 ohci_softc_t *sc = device_private(dv); 1031 uint32_t ctl; 1032 1033 mutex_spin_enter(&sc->sc_intr_lock); 1034 sc->sc_bus.ub_usepolling++; 1035 mutex_spin_exit(&sc->sc_intr_lock); 1036 1037 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1038 if (sc->sc_control == 0) { 1039 /* 1040 * Preserve register values, in case that BIOS 1041 * does not recover them. 1042 */ 1043 sc->sc_control = ctl; 1044 sc->sc_intre = OREAD4(sc, 1045 OHCI_INTERRUPT_ENABLE); 1046 } 1047 ctl |= OHCI_HCFS_SUSPEND; 1048 OWRITE4(sc, OHCI_CONTROL, ctl); 1049 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1050 1051 mutex_spin_enter(&sc->sc_intr_lock); 1052 sc->sc_bus.ub_usepolling--; 1053 mutex_spin_exit(&sc->sc_intr_lock); 1054 1055 return true; 1056 } 1057 1058 #ifdef OHCI_DEBUG 1059 void 1060 ohci_dumpregs(ohci_softc_t *sc) 1061 { 1062 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1063 1064 DPRINTF("rev=0x%08x control=0x%08x command=0x%08x", 1065 OREAD4(sc, OHCI_REVISION), 1066 OREAD4(sc, OHCI_CONTROL), 1067 OREAD4(sc, OHCI_COMMAND_STATUS), 0); 1068 DPRINTF(" intrstat=0x%08x intre=0x%08x intrd=0x%08x", 1069 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1070 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1071 OREAD4(sc, OHCI_INTERRUPT_DISABLE), 0); 1072 DPRINTF(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x", 1073 OREAD4(sc, OHCI_HCCA), 1074 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1075 OREAD4(sc, OHCI_CONTROL_HEAD_ED), 0); 1076 DPRINTF(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x", 1077 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1078 OREAD4(sc, OHCI_BULK_HEAD_ED), 1079 OREAD4(sc, OHCI_BULK_CURRENT_ED) ,0); 1080 DPRINTF(" done=0x%08x fmival=0x%08x fmrem=0x%08x", 1081 OREAD4(sc, OHCI_DONE_HEAD), 1082 OREAD4(sc, OHCI_FM_INTERVAL), 1083 OREAD4(sc, OHCI_FM_REMAINING), 0); 1084 DPRINTF(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x", 1085 OREAD4(sc, OHCI_FM_NUMBER), 1086 OREAD4(sc, OHCI_PERIODIC_START), 1087 OREAD4(sc, OHCI_LS_THRESHOLD), 0); 1088 DPRINTF(" desca=0x%08x descb=0x%08x stat=0x%08x", 1089 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1090 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1091 OREAD4(sc, OHCI_RH_STATUS), 0); 1092 DPRINTF(" port1=0x%08x port2=0x%08x", 1093 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1094 OREAD4(sc, OHCI_RH_PORT_STATUS(2)), 0, 0); 1095 DPRINTF(" HCCA: frame_number=0x%04x done_head=0x%08x", 1096 O32TOH(sc->sc_hcca->hcca_frame_number), 1097 O32TOH(sc->sc_hcca->hcca_done_head), 0, 0); 1098 } 1099 #endif 1100 1101 Static int ohci_intr1(ohci_softc_t *); 1102 1103 int 1104 ohci_intr(void *p) 1105 { 1106 ohci_softc_t *sc = p; 1107 int ret = 0; 1108 1109 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1110 1111 if (sc == NULL) 1112 return 0; 1113 1114 mutex_spin_enter(&sc->sc_intr_lock); 1115 1116 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1117 goto done; 1118 1119 /* If we get an interrupt while polling, then just ignore it. */ 1120 if (sc->sc_bus.ub_usepolling) { 1121 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1122 /* for level triggered intrs, should do something to ack */ 1123 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1124 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1125 1126 goto done; 1127 } 1128 1129 ret = ohci_intr1(sc); 1130 1131 done: 1132 mutex_spin_exit(&sc->sc_intr_lock); 1133 return ret; 1134 } 1135 1136 Static int 1137 ohci_intr1(ohci_softc_t *sc) 1138 { 1139 uint32_t intrs, eintrs; 1140 1141 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1142 1143 /* In case the interrupt occurs before initialization has completed. */ 1144 if (sc == NULL || sc->sc_hcca == NULL) { 1145 #ifdef DIAGNOSTIC 1146 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1147 #endif 1148 return 0; 1149 } 1150 1151 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1152 1153 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1154 if (!intrs) 1155 return 0; 1156 1157 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); /* Acknowledge */ 1158 eintrs = intrs & sc->sc_eintrs; 1159 DPRINTFN(7, "sc=%p", sc, 0, 0, 0); 1160 DPRINTFN(7, "intrs=%#x(%#x) eintrs=%#x(%#x)", 1161 intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), eintrs, 1162 sc->sc_eintrs); 1163 1164 if (!eintrs) { 1165 return 0; 1166 } 1167 1168 if (eintrs & OHCI_SO) { 1169 sc->sc_overrun_cnt++; 1170 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1171 printf("%s: %u scheduling overruns\n", 1172 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1173 sc->sc_overrun_cnt = 0; 1174 } 1175 /* XXX do what */ 1176 eintrs &= ~OHCI_SO; 1177 } 1178 if (eintrs & OHCI_WDH) { 1179 /* 1180 * We block the interrupt below, and reenable it later from 1181 * ohci_softintr(). 1182 */ 1183 usb_schedsoftintr(&sc->sc_bus); 1184 } 1185 if (eintrs & OHCI_RD) { 1186 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1187 /* XXX process resume detect */ 1188 } 1189 if (eintrs & OHCI_UE) { 1190 printf("%s: unrecoverable error, controller halted\n", 1191 device_xname(sc->sc_dev)); 1192 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1193 /* XXX what else */ 1194 } 1195 if (eintrs & OHCI_RHSC) { 1196 /* 1197 * We block the interrupt below, and reenable it later from 1198 * a timeout. 1199 */ 1200 softint_schedule(sc->sc_rhsc_si); 1201 } 1202 1203 if (eintrs != 0) { 1204 /* Block unprocessed interrupts. */ 1205 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1206 sc->sc_eintrs &= ~eintrs; 1207 DPRINTF("sc %p blocking intrs 0x%x", sc, eintrs, 0, 0); 1208 } 1209 1210 return 1; 1211 } 1212 1213 void 1214 ohci_rhsc_enable(void *v_sc) 1215 { 1216 ohci_softc_t *sc = v_sc; 1217 1218 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1219 DPRINTF("sc %p", sc, 0, 0, 0); 1220 mutex_spin_enter(&sc->sc_intr_lock); 1221 sc->sc_eintrs |= OHCI_RHSC; 1222 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1223 mutex_spin_exit(&sc->sc_intr_lock); 1224 } 1225 1226 #ifdef OHCI_DEBUG 1227 const char *ohci_cc_strs[] = { 1228 "NO_ERROR", 1229 "CRC", 1230 "BIT_STUFFING", 1231 "DATA_TOGGLE_MISMATCH", 1232 "STALL", 1233 "DEVICE_NOT_RESPONDING", 1234 "PID_CHECK_FAILURE", 1235 "UNEXPECTED_PID", 1236 "DATA_OVERRUN", 1237 "DATA_UNDERRUN", 1238 "BUFFER_OVERRUN", 1239 "BUFFER_UNDERRUN", 1240 "reserved", 1241 "reserved", 1242 "NOT_ACCESSED", 1243 "NOT_ACCESSED", 1244 }; 1245 #endif 1246 1247 void 1248 ohci_softintr(void *v) 1249 { 1250 struct usbd_bus *bus = v; 1251 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1252 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1253 ohci_soft_td_t *std, *sdone, *stdnext; 1254 struct usbd_xfer *xfer; 1255 struct ohci_pipe *opipe; 1256 int len, cc; 1257 int i, j, actlen, iframes, uedir; 1258 ohci_physaddr_t done; 1259 1260 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1261 1262 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1263 1264 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1265 sizeof(sc->sc_hcca->hcca_done_head), 1266 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1267 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1268 sc->sc_hcca->hcca_done_head = 0; 1269 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1270 sizeof(sc->sc_hcca->hcca_done_head), 1271 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1272 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1273 sc->sc_eintrs |= OHCI_WDH; 1274 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1275 1276 /* Reverse the done list. */ 1277 for (sdone = NULL, sidone = NULL; done != 0; ) { 1278 std = ohci_hash_find_td(sc, done); 1279 if (std != NULL) { 1280 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1281 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1282 std->dnext = sdone; 1283 done = O32TOH(std->td.td_nexttd); 1284 sdone = std; 1285 DPRINTFN(10, "add TD %p", std, 0, 0, 0); 1286 continue; 1287 } 1288 sitd = ohci_hash_find_itd(sc, done); 1289 if (sitd != NULL) { 1290 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1291 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1292 sitd->dnext = sidone; 1293 done = O32TOH(sitd->itd.itd_nextitd); 1294 sidone = sitd; 1295 DPRINTFN(5, "add ITD %p", sitd, 0, 0, 0); 1296 continue; 1297 } 1298 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1299 (u_long)done); 1300 break; 1301 } 1302 1303 DPRINTFN(10, "sdone=%p sidone=%p", sdone, sidone, 0, 0); 1304 DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0); 1305 #ifdef OHCI_DEBUG 1306 if (ohcidebug > 10) { 1307 for (std = sdone; std; std = std->dnext) 1308 ohci_dump_td(sc, std); 1309 } 1310 #endif 1311 DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0); 1312 1313 for (std = sdone; std; std = stdnext) { 1314 xfer = std->xfer; 1315 stdnext = std->dnext; 1316 DPRINTFN(10, "std=%p xfer=%p hcpriv=%p", std, xfer, 1317 xfer ? xfer->ux_hcpriv : 0, 0); 1318 if (xfer == NULL) { 1319 /* 1320 * xfer == NULL: There seems to be no xfer associated 1321 * with this TD. It is tailp that happened to end up on 1322 * the done queue. 1323 * Shouldn't happen, but some chips are broken(?). 1324 */ 1325 continue; 1326 } 1327 if (xfer->ux_status == USBD_CANCELLED || 1328 xfer->ux_status == USBD_TIMEOUT) { 1329 DPRINTF("cancel/timeout %p", xfer, 0, 0, 0); 1330 /* Handled by abort routine. */ 1331 continue; 1332 } 1333 callout_stop(&xfer->ux_callout); 1334 1335 len = std->len; 1336 if (std->td.td_cbp != 0) 1337 len -= O32TOH(std->td.td_be) - 1338 O32TOH(std->td.td_cbp) + 1; 1339 DPRINTFN(10, "len=%d, flags=0x%x", len, std->flags, 0, 0); 1340 if (std->flags & OHCI_ADD_LEN) 1341 xfer->ux_actlen += len; 1342 1343 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1344 if (cc == OHCI_CC_NO_ERROR) { 1345 if (std->flags & OHCI_CALL_DONE) { 1346 xfer->ux_status = USBD_NORMAL_COMPLETION; 1347 usb_transfer_complete(xfer); 1348 } 1349 ohci_free_std(sc, std); 1350 } else { 1351 /* 1352 * Endpoint is halted. First unlink all the TDs 1353 * belonging to the failed transfer, and then restart 1354 * the endpoint. 1355 */ 1356 ohci_soft_td_t *p, *n; 1357 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1358 1359 DPRINTFN(15, "error cc=%d", 1360 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 0, 0, 0); 1361 1362 /* remove TDs */ 1363 for (p = std; p->xfer == xfer; p = n) { 1364 n = p->nexttd; 1365 ohci_free_std(sc, p); 1366 } 1367 1368 /* clear halt */ 1369 opipe->sed->ed.ed_headp = HTOO32(p->physaddr); 1370 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1371 1372 if (cc == OHCI_CC_STALL) 1373 xfer->ux_status = USBD_STALLED; 1374 else 1375 xfer->ux_status = USBD_IOERROR; 1376 usb_transfer_complete(xfer); 1377 } 1378 } 1379 DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0); 1380 #ifdef OHCI_DEBUG 1381 if (ohcidebug > 10) { 1382 DPRINTFN(10, "ITD done", 0, 0, 0, 0); 1383 for (sitd = sidone; sitd; sitd = sitd->dnext) 1384 ohci_dump_itd(sc, sitd); 1385 } 1386 #endif 1387 DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0); 1388 1389 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1390 xfer = sitd->xfer; 1391 sitdnext = sitd->dnext; 1392 DPRINTFN(1, "sitd=%p xfer=%p hcpriv=%p", sitd, xfer, 1393 xfer ? xfer->ux_hcpriv : 0, 0); 1394 if (xfer == NULL) 1395 continue; 1396 if (xfer->ux_status == USBD_CANCELLED || 1397 xfer->ux_status == USBD_TIMEOUT) { 1398 DPRINTF("cancel/timeout %p", xfer, 0, 0, 0); 1399 /* Handled by abort routine. */ 1400 continue; 1401 } 1402 KASSERT(!sitd->isdone); 1403 #ifdef DIAGNOSTIC 1404 sitd->isdone = 1; 1405 #endif 1406 if (sitd->flags & OHCI_CALL_DONE) { 1407 ohci_soft_itd_t *next; 1408 1409 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1410 opipe->isoc.inuse -= xfer->ux_nframes; 1411 uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc-> 1412 bEndpointAddress); 1413 xfer->ux_status = USBD_NORMAL_COMPLETION; 1414 actlen = 0; 1415 for (i = 0, sitd = xfer->ux_hcpriv;; 1416 sitd = next) { 1417 next = sitd->nextitd; 1418 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1419 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1420 xfer->ux_status = USBD_IOERROR; 1421 /* For input, update frlengths with actual */ 1422 /* XXX anything necessary for output? */ 1423 if (uedir == UE_DIR_IN && 1424 xfer->ux_status == USBD_NORMAL_COMPLETION) { 1425 iframes = OHCI_ITD_GET_FC(O32TOH( 1426 sitd->itd.itd_flags)); 1427 for (j = 0; j < iframes; i++, j++) { 1428 len = O16TOH(sitd-> 1429 itd.itd_offset[j]); 1430 if ((OHCI_ITD_PSW_GET_CC(len) & 1431 OHCI_CC_NOT_ACCESSED_MASK) 1432 == OHCI_CC_NOT_ACCESSED) 1433 len = 0; 1434 else 1435 len = OHCI_ITD_PSW_LENGTH(len); 1436 xfer->ux_frlengths[i] = len; 1437 actlen += len; 1438 } 1439 } 1440 if (sitd->flags & OHCI_CALL_DONE) 1441 break; 1442 ohci_free_sitd(sc, sitd); 1443 } 1444 ohci_free_sitd(sc, sitd); 1445 if (uedir == UE_DIR_IN && 1446 xfer->ux_status == USBD_NORMAL_COMPLETION) 1447 xfer->ux_actlen = actlen; 1448 xfer->ux_hcpriv = NULL; 1449 1450 usb_transfer_complete(xfer); 1451 } 1452 } 1453 1454 if (sc->sc_softwake) { 1455 sc->sc_softwake = 0; 1456 cv_broadcast(&sc->sc_softwake_cv); 1457 } 1458 1459 DPRINTFN(10, "done", 0, 0, 0, 0); 1460 } 1461 1462 void 1463 ohci_device_ctrl_done(struct usbd_xfer *xfer) 1464 { 1465 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1466 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1467 int len = UGETW(xfer->ux_request.wLength); 1468 int isread = (xfer->ux_request.bmRequestType & UT_READ); 1469 1470 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1471 DPRINTFN(10, "xfer=%p", xfer, 0, 0, 0); 1472 1473 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1474 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 1475 1476 if (len) 1477 usb_syncmem(&xfer->ux_dmabuf, 0, len, 1478 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1479 usb_syncmem(&opipe->ctrl.reqdma, 0, 1480 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1481 } 1482 1483 void 1484 ohci_device_intr_done(struct usbd_xfer *xfer) 1485 { 1486 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1487 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1488 ohci_soft_ed_t *sed = opipe->sed; 1489 ohci_soft_td_t *data, *tail; 1490 int isread = 1491 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1492 1493 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1494 DPRINTFN(10, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0); 1495 1496 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1497 1498 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1499 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1500 if (xfer->ux_pipe->up_repeat) { 1501 data = opipe->tail.td; 1502 tail = ohci_alloc_std(sc); /* XXX should reuse TD */ 1503 if (tail == NULL) { 1504 xfer->ux_status = USBD_NOMEM; 1505 return; 1506 } 1507 tail->xfer = NULL; 1508 1509 data->td.td_flags = HTOO32( 1510 OHCI_TD_IN | OHCI_TD_NOCC | 1511 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 1512 if (xfer->ux_flags & USBD_SHORT_XFER_OK) 1513 data->td.td_flags |= HTOO32(OHCI_TD_R); 1514 data->td.td_cbp = HTOO32(DMAADDR(&xfer->ux_dmabuf, 0)); 1515 data->nexttd = tail; 1516 data->td.td_nexttd = HTOO32(tail->physaddr); 1517 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + 1518 xfer->ux_length - 1); 1519 data->len = xfer->ux_length; 1520 data->xfer = xfer; 1521 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 1522 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 1523 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1524 xfer->ux_hcpriv = data; 1525 xfer->ux_actlen = 0; 1526 1527 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1528 usb_syncmem(&sed->dma, 1529 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1530 sizeof(sed->ed.ed_tailp), 1531 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1532 opipe->tail.td = tail; 1533 } 1534 } 1535 1536 void 1537 ohci_device_bulk_done(struct usbd_xfer *xfer) 1538 { 1539 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1540 1541 int isread = 1542 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1543 1544 KASSERT(mutex_owned(&sc->sc_lock)); 1545 1546 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1547 DPRINTFN(10, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0); 1548 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1549 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1550 } 1551 1552 Static void 1553 ohci_rhsc_softint(void *arg) 1554 { 1555 ohci_softc_t *sc = arg; 1556 1557 mutex_enter(&sc->sc_lock); 1558 1559 ohci_rhsc(sc, sc->sc_intrxfer); 1560 1561 /* Do not allow RHSC interrupts > 1 per second */ 1562 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1563 1564 mutex_exit(&sc->sc_lock); 1565 } 1566 1567 void 1568 ohci_rhsc(ohci_softc_t *sc, struct usbd_xfer *xfer) 1569 { 1570 u_char *p; 1571 int i, m; 1572 int hstatus __unused; 1573 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1574 1575 KASSERT(mutex_owned(&sc->sc_lock)); 1576 1577 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1578 DPRINTF("sc=%p xfer=%p hstatus=0x%08x", sc, xfer, hstatus, 0); 1579 1580 if (xfer == NULL) { 1581 /* Just ignore the change. */ 1582 return; 1583 } 1584 1585 p = xfer->ux_buf; 1586 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 1587 memset(p, 0, xfer->ux_length); 1588 for (i = 1; i <= m; i++) { 1589 /* Pick out CHANGE bits from the status reg. */ 1590 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1591 p[i/8] |= 1 << (i%8); 1592 } 1593 DPRINTF("change=0x%02x", *p, 0, 0, 0); 1594 xfer->ux_actlen = xfer->ux_length; 1595 xfer->ux_status = USBD_NORMAL_COMPLETION; 1596 1597 usb_transfer_complete(xfer); 1598 } 1599 1600 void 1601 ohci_root_intr_done(struct usbd_xfer *xfer) 1602 { 1603 } 1604 1605 /* 1606 * Wait here until controller claims to have an interrupt. 1607 * Then call ohci_intr and return. Use timeout to avoid waiting 1608 * too long. 1609 */ 1610 void 1611 ohci_waitintr(ohci_softc_t *sc, struct usbd_xfer *xfer) 1612 { 1613 int timo; 1614 uint32_t intrs; 1615 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1616 1617 mutex_enter(&sc->sc_lock); 1618 1619 xfer->ux_status = USBD_IN_PROGRESS; 1620 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1621 usb_delay_ms(&sc->sc_bus, 1); 1622 if (sc->sc_dying) 1623 break; 1624 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 1625 DPRINTFN(15, "intrs 0x%04x", intrs, 0, 0, 0); 1626 #ifdef OHCI_DEBUG 1627 if (ohcidebug > 15) 1628 ohci_dumpregs(sc); 1629 #endif 1630 if (intrs) { 1631 mutex_spin_enter(&sc->sc_intr_lock); 1632 ohci_intr1(sc); 1633 mutex_spin_exit(&sc->sc_intr_lock); 1634 if (xfer->ux_status != USBD_IN_PROGRESS) 1635 goto done; 1636 } 1637 } 1638 1639 /* Timeout */ 1640 DPRINTF("timeout", 0, 0, 0, 0); 1641 xfer->ux_status = USBD_TIMEOUT; 1642 usb_transfer_complete(xfer); 1643 1644 /* XXX should free TD */ 1645 1646 done: 1647 mutex_exit(&sc->sc_lock); 1648 } 1649 1650 void 1651 ohci_poll(struct usbd_bus *bus) 1652 { 1653 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1654 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1655 1656 #ifdef OHCI_DEBUG 1657 static int last; 1658 int new; 1659 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1660 if (new != last) { 1661 DPRINTFN(10, "intrs=0x%04x", new, 0, 0, 0); 1662 last = new; 1663 } 1664 #endif 1665 sc->sc_eintrs |= OHCI_WDH; 1666 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1667 mutex_spin_enter(&sc->sc_intr_lock); 1668 ohci_intr1(sc); 1669 mutex_spin_exit(&sc->sc_intr_lock); 1670 } 1671 } 1672 1673 /* 1674 * Add an ED to the schedule. Called with USB lock held. 1675 */ 1676 Static void 1677 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1678 { 1679 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1680 DPRINTFN(8, "sed=%p head=%p", sed, head, 0, 0); 1681 1682 KASSERT(mutex_owned(&sc->sc_lock)); 1683 1684 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1685 sizeof(head->ed.ed_nexted), 1686 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1687 sed->next = head->next; 1688 sed->ed.ed_nexted = head->ed.ed_nexted; 1689 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1690 sizeof(sed->ed.ed_nexted), 1691 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1692 head->next = sed; 1693 head->ed.ed_nexted = HTOO32(sed->physaddr); 1694 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1695 sizeof(head->ed.ed_nexted), 1696 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1697 } 1698 1699 /* 1700 * Remove an ED from the schedule. Called with USB lock held. 1701 */ 1702 Static void 1703 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1704 { 1705 ohci_soft_ed_t *p; 1706 1707 KASSERT(mutex_owned(&sc->sc_lock)); 1708 1709 /* XXX */ 1710 for (p = head; p != NULL && p->next != sed; p = p->next) 1711 ; 1712 KASSERT(p != NULL); 1713 1714 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1715 sizeof(sed->ed.ed_nexted), 1716 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1717 p->next = sed->next; 1718 p->ed.ed_nexted = sed->ed.ed_nexted; 1719 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1720 sizeof(p->ed.ed_nexted), 1721 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1722 } 1723 1724 /* 1725 * When a transfer is completed the TD is added to the done queue by 1726 * the host controller. This queue is the processed by software. 1727 * Unfortunately the queue contains the physical address of the TD 1728 * and we have no simple way to translate this back to a kernel address. 1729 * To make the translation possible (and fast) we use a hash table of 1730 * TDs currently in the schedule. The physical address is used as the 1731 * hash value. 1732 */ 1733 1734 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1735 /* Called with USB lock held. */ 1736 void 1737 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1738 { 1739 int h = HASH(std->physaddr); 1740 1741 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1742 1743 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1744 } 1745 1746 /* Called with USB lock held. */ 1747 void 1748 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1749 { 1750 1751 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1752 1753 LIST_REMOVE(std, hnext); 1754 } 1755 1756 ohci_soft_td_t * 1757 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1758 { 1759 int h = HASH(a); 1760 ohci_soft_td_t *std; 1761 1762 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1763 std != NULL; 1764 std = LIST_NEXT(std, hnext)) 1765 if (std->physaddr == a) 1766 return std; 1767 return NULL; 1768 } 1769 1770 /* Called with USB lock held. */ 1771 void 1772 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1773 { 1774 int h = HASH(sitd->physaddr); 1775 1776 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1777 1778 KASSERT(mutex_owned(&sc->sc_lock)); 1779 1780 DPRINTFN(10, "sitd=%p physaddr=0x%08lx", sitd, (u_long)sitd->physaddr, 1781 0, 0); 1782 1783 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1784 } 1785 1786 /* Called with USB lock held. */ 1787 void 1788 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1789 { 1790 1791 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1792 1793 KASSERT(mutex_owned(&sc->sc_lock)); 1794 1795 DPRINTFN(10, "sitd=%p physaddr=0x%08lx", sitd, (u_long)sitd->physaddr, 1796 0, 0); 1797 1798 LIST_REMOVE(sitd, hnext); 1799 } 1800 1801 ohci_soft_itd_t * 1802 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1803 { 1804 int h = HASH(a); 1805 ohci_soft_itd_t *sitd; 1806 1807 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1808 sitd != NULL; 1809 sitd = LIST_NEXT(sitd, hnext)) 1810 if (sitd->physaddr == a) 1811 return sitd; 1812 return NULL; 1813 } 1814 1815 void 1816 ohci_timeout(void *addr) 1817 { 1818 struct usbd_xfer *xfer = addr; 1819 struct ohci_xfer *oxfer = OHCI_XFER2OXFER(xfer); 1820 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1821 1822 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1823 DPRINTF("oxfer=%p", oxfer, 0, 0, 0); 1824 1825 if (sc->sc_dying) { 1826 mutex_enter(&sc->sc_lock); 1827 ohci_abort_xfer(xfer, USBD_TIMEOUT); 1828 mutex_exit(&sc->sc_lock); 1829 return; 1830 } 1831 1832 /* Execute the abort in a process context. */ 1833 usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr, 1834 USB_TASKQ_MPSAFE); 1835 usb_add_task(xfer->ux_pipe->up_dev, &oxfer->abort_task, 1836 USB_TASKQ_HC); 1837 } 1838 1839 void 1840 ohci_timeout_task(void *addr) 1841 { 1842 struct usbd_xfer *xfer = addr; 1843 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1844 1845 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1846 1847 DPRINTF("xfer=%p", xfer, 0, 0, 0); 1848 1849 mutex_enter(&sc->sc_lock); 1850 ohci_abort_xfer(xfer, USBD_TIMEOUT); 1851 mutex_exit(&sc->sc_lock); 1852 } 1853 1854 #ifdef OHCI_DEBUG 1855 void 1856 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 1857 { 1858 for (; std; std = std->nexttd) 1859 ohci_dump_td(sc, std); 1860 } 1861 1862 void 1863 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1864 { 1865 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1866 1867 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1868 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1869 1870 uint32_t flags = O32TOH(std->td.td_flags); 1871 DPRINTF("TD(%p) at %08lx:", std, (u_long)std->physaddr, 0, 0); 1872 DPRINTF(" round=%d DP=%x DI=%x T=%x", 1873 !!(flags & OHCI_TD_R), 1874 __SHIFTOUT(flags, OHCI_TD_DP_MASK), 1875 OHCI_TD_GET_DI(flags), 1876 __SHIFTOUT(flags, OHCI_TD_TOGGLE_MASK)); 1877 DPRINTF(" EC=%d CC=%d", OHCI_TD_GET_EC(flags), OHCI_TD_GET_CC(flags), 1878 0, 0); 1879 DPRINTF(" cbp=0x%08lx nexttd=0x%08lx be=0x%08lx", 1880 (u_long)O32TOH(std->td.td_cbp), 1881 (u_long)O32TOH(std->td.td_nexttd), 1882 (u_long)O32TOH(std->td.td_be), 0); 1883 } 1884 1885 void 1886 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1887 { 1888 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1889 1890 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1891 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1892 1893 uint32_t flags = O32TOH(sitd->itd.itd_flags); 1894 DPRINTF("ITD(%p) at %08lx", sitd, (u_long)sitd->physaddr, 0, 0); 1895 DPRINTF(" sf=%d di=%d fc=%d cc=%d", 1896 OHCI_ITD_GET_SF(flags), OHCI_ITD_GET_DI(flags), 1897 OHCI_ITD_GET_FC(flags), OHCI_ITD_GET_CC(flags)); 1898 DPRINTF(" bp0=0x%08x next=0x%08x be=0x%08x", 1899 O32TOH(sitd->itd.itd_bp0), 1900 O32TOH(sitd->itd.itd_nextitd), 1901 O32TOH(sitd->itd.itd_be), 0); 1902 CTASSERT(OHCI_ITD_NOFFSET == 8); 1903 DPRINTF(" offs[0] = 0x%04x offs[1] = 0x%04x " 1904 "offs[2] = 0x%04x offs[3] = 0x%04x", 1905 O16TOH(sitd->itd.itd_offset[0]), 1906 O16TOH(sitd->itd.itd_offset[1]), 1907 O16TOH(sitd->itd.itd_offset[2]), 1908 O16TOH(sitd->itd.itd_offset[3])); 1909 DPRINTF(" offs[4] = 0x%04x offs[5] = 0x%04x " 1910 "offs[6] = 0x%04x offs[7] = 0x%04x", 1911 O16TOH(sitd->itd.itd_offset[4]), 1912 O16TOH(sitd->itd.itd_offset[5]), 1913 O16TOH(sitd->itd.itd_offset[6]), 1914 O16TOH(sitd->itd.itd_offset[7])); 1915 } 1916 1917 void 1918 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1919 { 1920 for (; sitd; sitd = sitd->nextitd) 1921 ohci_dump_itd(sc, sitd); 1922 } 1923 1924 void 1925 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 1926 { 1927 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1928 1929 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 1930 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1931 1932 uint32_t flags = O32TOH(sed->ed.ed_flags); 1933 DPRINTF("ED(%p) at 0x%08lx:", sed, sed->physaddr, 0, 0); 1934 DPRINTF(" addr=%d endpt=%d maxp=%d", 1935 OHCI_ED_GET_FA(flags), 1936 OHCI_ED_GET_EN(flags), 1937 OHCI_ED_GET_MAXP(flags), 1938 0); 1939 DPRINTF(" dir=%d speed=%d skip=%d iso=%d", 1940 __SHIFTOUT(flags, OHCI_ED_DIR_MASK), 1941 !!(flags & OHCI_ED_SPEED), 1942 !!(flags & OHCI_ED_SKIP), 1943 !!(flags & OHCI_ED_FORMAT_ISO)); 1944 DPRINTF(" tailp=0x%08lx", (u_long)O32TOH(sed->ed.ed_tailp), 1945 0, 0, 0); 1946 DPRINTF(" headp=0x%08lx nexted=0x%08lx halted=%d carry=%d", 1947 O32TOH(sed->ed.ed_headp), O32TOH(sed->ed.ed_nexted), 1948 !!(O32TOH(sed->ed.ed_headp) & OHCI_HALTED), 1949 !!(O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 1950 } 1951 #endif 1952 1953 usbd_status 1954 ohci_open(struct usbd_pipe *pipe) 1955 { 1956 struct usbd_device *dev = pipe->up_dev; 1957 struct usbd_bus *bus = dev->ud_bus; 1958 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 1959 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1960 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 1961 uint8_t addr = dev->ud_addr; 1962 uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1963 ohci_soft_ed_t *sed; 1964 ohci_soft_td_t *std; 1965 ohci_soft_itd_t *sitd; 1966 ohci_physaddr_t tdphys; 1967 uint32_t fmt; 1968 usbd_status err = USBD_NOMEM; 1969 int ival; 1970 1971 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1972 DPRINTFN(1, "pipe=%p, addr=%d, endpt=%d (%d)", pipe, addr, 1973 ed->bEndpointAddress, bus->ub_rhaddr); 1974 1975 if (sc->sc_dying) { 1976 return USBD_IOERROR; 1977 } 1978 1979 std = NULL; 1980 sed = NULL; 1981 1982 if (addr == bus->ub_rhaddr) { 1983 switch (ed->bEndpointAddress) { 1984 case USB_CONTROL_ENDPOINT: 1985 pipe->up_methods = &roothub_ctrl_methods; 1986 break; 1987 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1988 pipe->up_methods = &ohci_root_intr_methods; 1989 break; 1990 default: 1991 err = USBD_INVAL; 1992 goto bad; 1993 } 1994 } else { 1995 sed = ohci_alloc_sed(sc); 1996 if (sed == NULL) 1997 goto bad; 1998 opipe->sed = sed; 1999 if (xfertype == UE_ISOCHRONOUS) { 2000 mutex_enter(&sc->sc_lock); 2001 sitd = ohci_alloc_sitd(sc); 2002 mutex_exit(&sc->sc_lock); 2003 if (sitd == NULL) 2004 goto bad; 2005 2006 opipe->tail.itd = sitd; 2007 tdphys = sitd->physaddr; 2008 fmt = OHCI_ED_FORMAT_ISO; 2009 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2010 fmt |= OHCI_ED_DIR_IN; 2011 else 2012 fmt |= OHCI_ED_DIR_OUT; 2013 } else { 2014 mutex_enter(&sc->sc_lock); 2015 std = ohci_alloc_std(sc); 2016 mutex_exit(&sc->sc_lock); 2017 if (std == NULL) 2018 goto bad; 2019 2020 opipe->tail.td = std; 2021 tdphys = std->physaddr; 2022 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2023 } 2024 sed->ed.ed_flags = HTOO32( 2025 OHCI_ED_SET_FA(addr) | 2026 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2027 (dev->ud_speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2028 fmt | 2029 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2030 sed->ed.ed_headp = HTOO32(tdphys | 2031 (pipe->up_endpoint->ue_toggle ? OHCI_TOGGLECARRY : 0)); 2032 sed->ed.ed_tailp = HTOO32(tdphys); 2033 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2034 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2035 2036 switch (xfertype) { 2037 case UE_CONTROL: 2038 pipe->up_methods = &ohci_device_ctrl_methods; 2039 err = usb_allocmem(&sc->sc_bus, 2040 sizeof(usb_device_request_t), 2041 0, &opipe->ctrl.reqdma); 2042 if (err) 2043 goto bad; 2044 mutex_enter(&sc->sc_lock); 2045 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2046 mutex_exit(&sc->sc_lock); 2047 break; 2048 case UE_INTERRUPT: 2049 pipe->up_methods = &ohci_device_intr_methods; 2050 ival = pipe->up_interval; 2051 if (ival == USBD_DEFAULT_INTERVAL) 2052 ival = ed->bInterval; 2053 err = ohci_device_setintr(sc, opipe, ival); 2054 if (err) 2055 goto bad; 2056 break; 2057 case UE_ISOCHRONOUS: 2058 pipe->up_methods = &ohci_device_isoc_methods; 2059 return ohci_setup_isoc(pipe); 2060 case UE_BULK: 2061 pipe->up_methods = &ohci_device_bulk_methods; 2062 mutex_enter(&sc->sc_lock); 2063 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2064 mutex_exit(&sc->sc_lock); 2065 break; 2066 } 2067 } 2068 2069 return USBD_NORMAL_COMPLETION; 2070 2071 bad: 2072 if (std != NULL) { 2073 mutex_enter(&sc->sc_lock); 2074 ohci_free_std(sc, std); 2075 mutex_exit(&sc->sc_lock); 2076 } 2077 if (sed != NULL) 2078 ohci_free_sed(sc, sed); 2079 return err; 2080 2081 } 2082 2083 /* 2084 * Close a reqular pipe. 2085 * Assumes that there are no pending transactions. 2086 */ 2087 void 2088 ohci_close_pipe(struct usbd_pipe *pipe, ohci_soft_ed_t *head) 2089 { 2090 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2091 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2092 ohci_soft_ed_t *sed = opipe->sed; 2093 2094 KASSERT(mutex_owned(&sc->sc_lock)); 2095 2096 #ifdef DIAGNOSTIC 2097 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2098 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2099 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2100 ohci_soft_td_t *std; 2101 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2102 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2103 "tl=0x%x pipe=%p, std=%p\n", sed, 2104 (int)O32TOH(sed->ed.ed_headp), 2105 (int)O32TOH(sed->ed.ed_tailp), 2106 pipe, std); 2107 #ifdef OHCI_DEBUG 2108 usbd_dump_pipe(&opipe->pipe); 2109 ohci_dump_ed(sc, sed); 2110 if (std) 2111 ohci_dump_td(sc, std); 2112 #endif 2113 usb_delay_ms(&sc->sc_bus, 2); 2114 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2115 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2116 printf("ohci_close_pipe: pipe still not empty\n"); 2117 } 2118 #endif 2119 ohci_rem_ed(sc, sed, head); 2120 /* Make sure the host controller is not touching this ED */ 2121 usb_delay_ms(&sc->sc_bus, 1); 2122 pipe->up_endpoint->ue_toggle = 2123 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2124 ohci_free_sed(sc, opipe->sed); 2125 } 2126 2127 /* 2128 * Abort a device request. 2129 * If this routine is called at splusb() it guarantees that the request 2130 * will be removed from the hardware scheduling and that the callback 2131 * for it will be called with USBD_CANCELLED status. 2132 * It's impossible to guarantee that the requested transfer will not 2133 * have happened since the hardware runs concurrently. 2134 * If the transaction has already happened we rely on the ordinary 2135 * interrupt processing to process it. 2136 * XXX This is most probably wrong. 2137 * XXXMRG this doesn't make sense anymore. 2138 */ 2139 void 2140 ohci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2141 { 2142 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2143 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2144 ohci_soft_ed_t *sed = opipe->sed; 2145 ohci_soft_td_t *p, *n; 2146 ohci_physaddr_t headp; 2147 int hit; 2148 int wake; 2149 2150 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2151 DPRINTF("xfer=%p pipe=%p sed=%p", xfer, opipe,sed, 0); 2152 2153 KASSERT(mutex_owned(&sc->sc_lock)); 2154 ASSERT_SLEEPABLE(); 2155 2156 if (sc->sc_dying) { 2157 /* If we're dying, just do the software part. */ 2158 xfer->ux_status = status; /* make software ignore it */ 2159 callout_halt(&xfer->ux_callout, &sc->sc_lock); 2160 usb_transfer_complete(xfer); 2161 return; 2162 } 2163 2164 /* 2165 * If an abort is already in progress then just wait for it to 2166 * complete and return. 2167 */ 2168 if (xfer->ux_hcflags & UXFER_ABORTING) { 2169 DPRINTFN(2, "already aborting", 0, 0, 0, 0); 2170 #ifdef DIAGNOSTIC 2171 if (status == USBD_TIMEOUT) 2172 printf("%s: TIMEOUT while aborting\n", __func__); 2173 #endif 2174 /* Override the status which might be USBD_TIMEOUT. */ 2175 xfer->ux_status = status; 2176 DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0); 2177 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2178 while (xfer->ux_hcflags & UXFER_ABORTING) 2179 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2180 goto done; 2181 } 2182 xfer->ux_hcflags |= UXFER_ABORTING; 2183 2184 /* 2185 * Step 1: Make interrupt routine and hardware ignore xfer. 2186 */ 2187 xfer->ux_status = status; /* make software ignore it */ 2188 callout_stop(&xfer->ux_callout); 2189 DPRINTFN(1, "stop ed=%p", sed, 0, 0, 0); 2190 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2191 sizeof(sed->ed.ed_flags), 2192 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2193 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2194 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2195 sizeof(sed->ed.ed_flags), 2196 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2197 2198 /* 2199 * Step 2: Wait until we know hardware has finished any possible 2200 * use of the xfer. Also make sure the soft interrupt routine 2201 * has run. 2202 */ 2203 /* Hardware finishes in 1ms */ 2204 usb_delay_ms_locked(opipe->pipe.up_dev->ud_bus, 20, &sc->sc_lock); 2205 sc->sc_softwake = 1; 2206 usb_schedsoftintr(&sc->sc_bus); 2207 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2208 2209 /* 2210 * Step 3: Remove any vestiges of the xfer from the hardware. 2211 * The complication here is that the hardware may have executed 2212 * beyond the xfer we're trying to abort. So as we're scanning 2213 * the TDs of this xfer we check if the hardware points to 2214 * any of them. 2215 */ 2216 p = xfer->ux_hcpriv; 2217 KASSERT(p); 2218 2219 #ifdef OHCI_DEBUG 2220 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2221 2222 if (ohcidebug > 1) { 2223 DPRINTF("sed:", 0, 0, 0, 0); 2224 ohci_dump_ed(sc, sed); 2225 ohci_dump_tds(sc, p); 2226 } 2227 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2228 #endif 2229 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2230 hit = 0; 2231 for (; p->xfer == xfer; p = n) { 2232 hit |= headp == p->physaddr; 2233 n = p->nexttd; 2234 ohci_free_std(sc, p); 2235 } 2236 /* Zap headp register if hardware pointed inside the xfer. */ 2237 if (hit) { 2238 DPRINTFN(1, "set hd=0x%08x, tl=0x%08x", (int)p->physaddr, 2239 (int)O32TOH(sed->ed.ed_tailp), 0, 0); 2240 sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */ 2241 usb_syncmem(&sed->dma, 2242 sed->offs + offsetof(ohci_ed_t, ed_headp), 2243 sizeof(sed->ed.ed_headp), 2244 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2245 } else { 2246 DPRINTFN(1, "no hit", 0, 0, 0, 0); 2247 } 2248 2249 /* 2250 * Step 4: Turn on hardware again. 2251 */ 2252 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2253 sizeof(sed->ed.ed_flags), 2254 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2255 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2256 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2257 sizeof(sed->ed.ed_flags), 2258 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2259 2260 /* 2261 * Step 5: Execute callback. 2262 */ 2263 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2264 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2265 usb_transfer_complete(xfer); 2266 if (wake) 2267 cv_broadcast(&xfer->ux_hccv); 2268 2269 done: 2270 KASSERT(mutex_owned(&sc->sc_lock)); 2271 } 2272 2273 /* 2274 * Data structures and routines to emulate the root hub. 2275 */ 2276 Static int 2277 ohci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2278 void *buf, int buflen) 2279 { 2280 ohci_softc_t *sc = OHCI_BUS2SC(bus); 2281 usb_port_status_t ps; 2282 uint16_t len, value, index; 2283 int l, totlen = 0; 2284 int port, i; 2285 uint32_t v; 2286 2287 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2288 2289 if (sc->sc_dying) 2290 return -1; 2291 2292 DPRINTFN(4, "type=0x%02x request=%02x", req->bmRequestType, 2293 req->bRequest, 0, 0); 2294 2295 len = UGETW(req->wLength); 2296 value = UGETW(req->wValue); 2297 index = UGETW(req->wIndex); 2298 2299 #define C(x,y) ((x) | ((y) << 8)) 2300 switch (C(req->bRequest, req->bmRequestType)) { 2301 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2302 DPRINTFN(8, "wValue=0x%04x", value, 0, 0, 0); 2303 if (len == 0) 2304 break; 2305 switch (value) { 2306 case C(0, UDESC_DEVICE): { 2307 usb_device_descriptor_t devd; 2308 2309 totlen = min(buflen, sizeof(devd)); 2310 memcpy(&devd, buf, totlen); 2311 USETW(devd.idVendor, sc->sc_id_vendor); 2312 memcpy(buf, &devd, totlen); 2313 break; 2314 } 2315 case C(1, UDESC_STRING): 2316 #define sd ((usb_string_descriptor_t *)buf) 2317 /* Vendor */ 2318 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2319 break; 2320 case C(2, UDESC_STRING): 2321 /* Product */ 2322 totlen = usb_makestrdesc(sd, len, "OHCI root hub"); 2323 break; 2324 #undef sd 2325 default: 2326 /* default from usbroothub */ 2327 return buflen; 2328 } 2329 break; 2330 2331 /* Hub requests */ 2332 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2333 break; 2334 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2335 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 2336 index, value, 0, 0); 2337 if (index < 1 || index > sc->sc_noport) { 2338 return -1; 2339 } 2340 port = OHCI_RH_PORT_STATUS(index); 2341 switch(value) { 2342 case UHF_PORT_ENABLE: 2343 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2344 break; 2345 case UHF_PORT_SUSPEND: 2346 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2347 break; 2348 case UHF_PORT_POWER: 2349 /* Yes, writing to the LOW_SPEED bit clears power. */ 2350 OWRITE4(sc, port, UPS_LOW_SPEED); 2351 break; 2352 case UHF_C_PORT_CONNECTION: 2353 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2354 break; 2355 case UHF_C_PORT_ENABLE: 2356 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2357 break; 2358 case UHF_C_PORT_SUSPEND: 2359 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2360 break; 2361 case UHF_C_PORT_OVER_CURRENT: 2362 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2363 break; 2364 case UHF_C_PORT_RESET: 2365 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2366 break; 2367 default: 2368 return -1; 2369 } 2370 switch(value) { 2371 case UHF_C_PORT_CONNECTION: 2372 case UHF_C_PORT_ENABLE: 2373 case UHF_C_PORT_SUSPEND: 2374 case UHF_C_PORT_OVER_CURRENT: 2375 case UHF_C_PORT_RESET: 2376 /* Enable RHSC interrupt if condition is cleared. */ 2377 if ((OREAD4(sc, port) >> 16) == 0) 2378 ohci_rhsc_enable(sc); 2379 break; 2380 default: 2381 break; 2382 } 2383 break; 2384 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2385 if (len == 0) 2386 break; 2387 if ((value & 0xff) != 0) { 2388 return -1; 2389 } 2390 usb_hub_descriptor_t hubd; 2391 2392 totlen = min(buflen, sizeof(hubd)); 2393 memcpy(&hubd, buf, totlen); 2394 2395 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2396 hubd.bNbrPorts = sc->sc_noport; 2397 USETW(hubd.wHubCharacteristics, 2398 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2399 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2400 /* XXX overcurrent */ 2401 ); 2402 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2403 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2404 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2405 hubd.DeviceRemovable[i++] = (uint8_t)v; 2406 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2407 totlen = min(totlen, hubd.bDescLength); 2408 memcpy(buf, &hubd, totlen); 2409 break; 2410 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2411 if (len != 4) { 2412 return -1; 2413 } 2414 memset(buf, 0, len); /* ? XXX */ 2415 totlen = len; 2416 break; 2417 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2418 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 2419 if (index < 1 || index > sc->sc_noport) { 2420 return -1; 2421 } 2422 if (len != 4) { 2423 return -1; 2424 } 2425 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2426 DPRINTFN(8, "port status=0x%04x", v, 0, 0, 0); 2427 USETW(ps.wPortStatus, v); 2428 USETW(ps.wPortChange, v >> 16); 2429 totlen = min(len, sizeof(ps)); 2430 memcpy(buf, &ps, totlen); 2431 break; 2432 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2433 return -1; 2434 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2435 break; 2436 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2437 if (index < 1 || index > sc->sc_noport) { 2438 return -1; 2439 } 2440 port = OHCI_RH_PORT_STATUS(index); 2441 switch(value) { 2442 case UHF_PORT_ENABLE: 2443 OWRITE4(sc, port, UPS_PORT_ENABLED); 2444 break; 2445 case UHF_PORT_SUSPEND: 2446 OWRITE4(sc, port, UPS_SUSPEND); 2447 break; 2448 case UHF_PORT_RESET: 2449 DPRINTFN(5, "reset port %d", index, 0, 0, 0); 2450 OWRITE4(sc, port, UPS_RESET); 2451 for (i = 0; i < 5; i++) { 2452 usb_delay_ms(&sc->sc_bus, 2453 USB_PORT_ROOT_RESET_DELAY); 2454 if (sc->sc_dying) { 2455 return -1; 2456 } 2457 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2458 break; 2459 } 2460 DPRINTFN(8, "port %d reset, status = 0x%04x", index, 2461 OREAD4(sc, port), 0, 0); 2462 break; 2463 case UHF_PORT_POWER: 2464 DPRINTFN(2, "set port power %d", index, 0, 0, 0); 2465 OWRITE4(sc, port, UPS_PORT_POWER); 2466 break; 2467 default: 2468 return -1; 2469 } 2470 break; 2471 default: 2472 /* default from usbroothub */ 2473 return buflen; 2474 } 2475 2476 return totlen; 2477 } 2478 2479 Static usbd_status 2480 ohci_root_intr_transfer(struct usbd_xfer *xfer) 2481 { 2482 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2483 usbd_status err; 2484 2485 /* Insert last in queue. */ 2486 mutex_enter(&sc->sc_lock); 2487 err = usb_insert_transfer(xfer); 2488 mutex_exit(&sc->sc_lock); 2489 if (err) 2490 return err; 2491 2492 /* Pipe isn't running, start first */ 2493 return ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2494 } 2495 2496 Static usbd_status 2497 ohci_root_intr_start(struct usbd_xfer *xfer) 2498 { 2499 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2500 2501 if (sc->sc_dying) 2502 return USBD_IOERROR; 2503 2504 mutex_enter(&sc->sc_lock); 2505 KASSERT(sc->sc_intrxfer == NULL); 2506 sc->sc_intrxfer = xfer; 2507 mutex_exit(&sc->sc_lock); 2508 2509 return USBD_IN_PROGRESS; 2510 } 2511 2512 /* Abort a root interrupt request. */ 2513 Static void 2514 ohci_root_intr_abort(struct usbd_xfer *xfer) 2515 { 2516 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2517 2518 KASSERT(mutex_owned(&sc->sc_lock)); 2519 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2520 2521 sc->sc_intrxfer = NULL; 2522 2523 xfer->ux_status = USBD_CANCELLED; 2524 usb_transfer_complete(xfer); 2525 } 2526 2527 /* Close the root pipe. */ 2528 Static void 2529 ohci_root_intr_close(struct usbd_pipe *pipe) 2530 { 2531 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2532 2533 KASSERT(mutex_owned(&sc->sc_lock)); 2534 2535 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2536 2537 sc->sc_intrxfer = NULL; 2538 } 2539 2540 /************************/ 2541 2542 Static usbd_status 2543 ohci_device_ctrl_transfer(struct usbd_xfer *xfer) 2544 { 2545 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2546 usbd_status err; 2547 2548 /* Insert last in queue. */ 2549 mutex_enter(&sc->sc_lock); 2550 err = usb_insert_transfer(xfer); 2551 mutex_exit(&sc->sc_lock); 2552 if (err) 2553 return err; 2554 2555 /* Pipe isn't running, start first */ 2556 return ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2557 } 2558 2559 Static usbd_status 2560 ohci_device_ctrl_start(struct usbd_xfer *xfer) 2561 { 2562 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2563 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2564 usb_device_request_t *req = &xfer->ux_request; 2565 struct usbd_device *dev __diagused = opipe->pipe.up_dev; 2566 ohci_soft_td_t *setup, *stat, *next, *tail; 2567 ohci_soft_ed_t *sed; 2568 int isread; 2569 int len; 2570 usbd_status err; 2571 2572 2573 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2574 2575 if (sc->sc_dying) 2576 return USBD_IOERROR; 2577 2578 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2579 2580 mutex_enter(&sc->sc_lock); 2581 2582 isread = req->bmRequestType & UT_READ; 2583 len = UGETW(req->wLength); 2584 2585 DPRINTF("type=0x%02x, request=0x%02x, " 2586 "wValue=0x%04x, wIndex=0x%04x", 2587 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2588 UGETW(req->wIndex)); 2589 DPRINTF("len=%d, addr=%d, endpt=%d", 2590 len, dev->ud_addr, 2591 opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 2592 2593 setup = opipe->tail.td; 2594 stat = ohci_alloc_std(sc); 2595 if (stat == NULL) { 2596 err = USBD_NOMEM; 2597 goto bad1; 2598 } 2599 tail = ohci_alloc_std(sc); 2600 if (tail == NULL) { 2601 err = USBD_NOMEM; 2602 goto bad2; 2603 } 2604 tail->xfer = NULL; 2605 2606 sed = opipe->sed; 2607 2608 KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->ud_addr, 2609 "address ED %d pipe %d\n", 2610 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->ud_addr); 2611 KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) == 2612 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 2613 "MPL ED %d pipe %d\n", 2614 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), 2615 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 2616 2617 next = stat; 2618 2619 /* Set up data transaction */ 2620 if (len != 0) { 2621 ohci_soft_td_t *std = stat; 2622 2623 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 2624 std, &stat); 2625 if (err) { 2626 /* stat is unchanged if error */ 2627 goto bad3; 2628 } 2629 stat = stat->nexttd; /* point at free TD */ 2630 2631 /* Start toggle at 1 and then use the carried toggle. */ 2632 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 2633 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 2634 usb_syncmem(&std->dma, 2635 std->offs + offsetof(ohci_td_t, td_flags), 2636 sizeof(std->td.td_flags), 2637 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2638 } 2639 2640 memcpy(KERNADDR(&opipe->ctrl.reqdma, 0), req, sizeof(*req)); 2641 usb_syncmem(&opipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2642 2643 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 2644 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 2645 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->ctrl.reqdma, 0)); 2646 setup->nexttd = next; 2647 setup->td.td_nexttd = HTOO32(next->physaddr); 2648 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof(*req) - 1); 2649 setup->len = 0; 2650 setup->xfer = xfer; 2651 setup->flags = 0; 2652 xfer->ux_hcpriv = setup; 2653 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2654 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2655 2656 stat->td.td_flags = HTOO32( 2657 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 2658 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 2659 stat->td.td_cbp = 0; 2660 stat->nexttd = tail; 2661 stat->td.td_nexttd = HTOO32(tail->physaddr); 2662 stat->td.td_be = 0; 2663 stat->flags = OHCI_CALL_DONE; 2664 stat->len = 0; 2665 stat->xfer = xfer; 2666 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2667 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2668 2669 #ifdef OHCI_DEBUG 2670 USBHIST_LOGN(ohcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2671 if (ohcidebug > 5) { 2672 ohci_dump_ed(sc, sed); 2673 ohci_dump_tds(sc, setup); 2674 } 2675 USBHIST_LOGN(ohcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2676 #endif 2677 2678 /* Insert ED in schedule */ 2679 sed->ed.ed_tailp = HTOO32(tail->physaddr); 2680 usb_syncmem(&sed->dma, 2681 sed->offs + offsetof(ohci_ed_t, ed_tailp), 2682 sizeof(sed->ed.ed_tailp), 2683 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2684 opipe->tail.td = tail; 2685 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2686 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2687 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2688 ohci_timeout, xfer); 2689 } 2690 2691 #ifdef OHCI_DEBUG 2692 DPRINTFN(20, "--- dump start ---", 0, 0, 0, 0); 2693 if (ohcidebug > 20) { 2694 delay(10000); 2695 DPRINTFN(20, "status=%x", OREAD4(sc, OHCI_COMMAND_STATUS), 2696 0, 0, 0); 2697 ohci_dumpregs(sc); 2698 DPRINTFN(20, "ctrl head:", 0, 0, 0, 0); 2699 ohci_dump_ed(sc, sc->sc_ctrl_head); 2700 DPRINTF("sed:", 0, 0, 0, 0); 2701 ohci_dump_ed(sc, sed); 2702 ohci_dump_tds(sc, setup); 2703 } 2704 DPRINTFN(20, "--- dump start ---", 0, 0, 0, 0); 2705 #endif 2706 2707 mutex_exit(&sc->sc_lock); 2708 2709 if (sc->sc_bus.ub_usepolling) 2710 ohci_waitintr(sc, xfer); 2711 2712 return USBD_IN_PROGRESS; 2713 2714 bad3: 2715 ohci_free_std(sc, tail); 2716 bad2: 2717 ohci_free_std(sc, stat); 2718 bad1: 2719 mutex_exit(&sc->sc_lock); 2720 2721 return err; 2722 } 2723 2724 /* Abort a device control request. */ 2725 Static void 2726 ohci_device_ctrl_abort(struct usbd_xfer *xfer) 2727 { 2728 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 2729 2730 KASSERT(mutex_owned(&sc->sc_lock)); 2731 2732 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2733 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2734 ohci_abort_xfer(xfer, USBD_CANCELLED); 2735 } 2736 2737 /* Close a device control pipe. */ 2738 Static void 2739 ohci_device_ctrl_close(struct usbd_pipe *pipe) 2740 { 2741 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2742 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2743 2744 KASSERT(mutex_owned(&sc->sc_lock)); 2745 2746 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2747 DPRINTF("pipe=%p", pipe, 0, 0, 0); 2748 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2749 ohci_free_std(sc, opipe->tail.td); 2750 } 2751 2752 /************************/ 2753 2754 Static void 2755 ohci_device_clear_toggle(struct usbd_pipe *pipe) 2756 { 2757 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2758 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2759 2760 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2761 } 2762 2763 Static void 2764 ohci_noop(struct usbd_pipe *pipe) 2765 { 2766 } 2767 2768 Static usbd_status 2769 ohci_device_bulk_transfer(struct usbd_xfer *xfer) 2770 { 2771 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2772 usbd_status err; 2773 2774 /* Insert last in queue. */ 2775 mutex_enter(&sc->sc_lock); 2776 err = usb_insert_transfer(xfer); 2777 mutex_exit(&sc->sc_lock); 2778 if (err) 2779 return err; 2780 2781 /* Pipe isn't running, start first */ 2782 return ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2783 } 2784 2785 Static usbd_status 2786 ohci_device_bulk_start(struct usbd_xfer *xfer) 2787 { 2788 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2789 struct usbd_device *dev = opipe->pipe.up_dev; 2790 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2791 int addr = dev->ud_addr; 2792 ohci_soft_td_t *data, *tail, *tdp; 2793 ohci_soft_ed_t *sed; 2794 int len, isread, endpt; 2795 usbd_status err; 2796 2797 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2798 2799 if (sc->sc_dying) 2800 return USBD_IOERROR; 2801 2802 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2803 2804 mutex_enter(&sc->sc_lock); 2805 2806 len = xfer->ux_length; 2807 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2808 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2809 sed = opipe->sed; 2810 2811 DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread, 2812 xfer->ux_flags); 2813 DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0); 2814 2815 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2816 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2817 /* Update device address */ 2818 sed->ed.ed_flags = HTOO32( 2819 (O32TOH(sed->ed.ed_flags) & ~OHCI_ED_ADDRMASK) | 2820 OHCI_ED_SET_FA(addr)); 2821 2822 /* Allocate a chain of new TDs (including a new tail). */ 2823 data = opipe->tail.td; 2824 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 2825 data, &tail); 2826 if (err) 2827 return err; 2828 2829 /* We want interrupt at the end of the transfer. */ 2830 tail->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 2831 tail->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 2832 tail->flags |= OHCI_CALL_DONE; 2833 tail = tail->nexttd; /* point at sentinel */ 2834 usb_syncmem(&tail->dma, tail->offs + offsetof(ohci_td_t, td_flags), 2835 sizeof(tail->td.td_flags), 2836 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2837 if (err) { 2838 mutex_exit(&sc->sc_lock); 2839 return err; 2840 } 2841 2842 tail->xfer = NULL; 2843 xfer->ux_hcpriv = data; 2844 2845 DPRINTFN(4, "ed_flags=0x%08x td_flags=0x%08x " 2846 "td_cbp=0x%08x td_be=0x%08x", 2847 (int)O32TOH(sed->ed.ed_flags), 2848 (int)O32TOH(data->td.td_flags), 2849 (int)O32TOH(data->td.td_cbp), 2850 (int)O32TOH(data->td.td_be)); 2851 2852 #ifdef OHCI_DEBUG 2853 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2854 if (ohcidebug > 5) { 2855 ohci_dump_ed(sc, sed); 2856 ohci_dump_tds(sc, data); 2857 } 2858 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2859 #endif 2860 2861 /* Insert ED in schedule */ 2862 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 2863 tdp->xfer = xfer; 2864 } 2865 sed->ed.ed_tailp = HTOO32(tail->physaddr); 2866 opipe->tail.td = tail; 2867 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 2868 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2869 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2870 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 2871 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2872 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2873 ohci_timeout, xfer); 2874 } 2875 mutex_exit(&sc->sc_lock); 2876 2877 #if 0 2878 /* This goes wrong if we are too slow. */ 2879 if (ohcidebug > 10) { 2880 delay(10000); 2881 DPRINTF("status=%x", OREAD4(sc, OHCI_COMMAND_STATUS), 2882 0, 0, 0); 2883 ohci_dump_ed(sc, sed); 2884 ohci_dump_tds(sc, data); 2885 } 2886 #endif 2887 2888 return USBD_IN_PROGRESS; 2889 } 2890 2891 Static void 2892 ohci_device_bulk_abort(struct usbd_xfer *xfer) 2893 { 2894 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 2895 2896 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2897 2898 KASSERT(mutex_owned(&sc->sc_lock)); 2899 2900 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2901 ohci_abort_xfer(xfer, USBD_CANCELLED); 2902 } 2903 2904 /* 2905 * Close a device bulk pipe. 2906 */ 2907 Static void 2908 ohci_device_bulk_close(struct usbd_pipe *pipe) 2909 { 2910 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2911 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2912 2913 KASSERT(mutex_owned(&sc->sc_lock)); 2914 2915 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2916 2917 DPRINTF("pipe=%p", pipe, 0, 0, 0); 2918 ohci_close_pipe(pipe, sc->sc_bulk_head); 2919 ohci_free_std(sc, opipe->tail.td); 2920 } 2921 2922 /************************/ 2923 2924 Static usbd_status 2925 ohci_device_intr_transfer(struct usbd_xfer *xfer) 2926 { 2927 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2928 usbd_status err; 2929 2930 /* Insert last in queue. */ 2931 mutex_enter(&sc->sc_lock); 2932 err = usb_insert_transfer(xfer); 2933 mutex_exit(&sc->sc_lock); 2934 if (err) 2935 return err; 2936 2937 /* Pipe isn't running, start first */ 2938 return ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2939 } 2940 2941 Static usbd_status 2942 ohci_device_intr_start(struct usbd_xfer *xfer) 2943 { 2944 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2945 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2946 ohci_soft_ed_t *sed = opipe->sed; 2947 ohci_soft_td_t *data, *tail; 2948 int len, isread, endpt; 2949 2950 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2951 2952 if (sc->sc_dying) 2953 return USBD_IOERROR; 2954 2955 DPRINTFN(3, "xfer=%p len=%d flags=%d priv=%p", xfer, xfer->ux_length, 2956 xfer->ux_flags, xfer->ux_priv); 2957 2958 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2959 2960 len = xfer->ux_length; 2961 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2962 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2963 2964 data = opipe->tail.td; 2965 mutex_enter(&sc->sc_lock); 2966 tail = ohci_alloc_std(sc); 2967 mutex_exit(&sc->sc_lock); 2968 if (tail == NULL) 2969 return USBD_NOMEM; 2970 tail->xfer = NULL; 2971 2972 data->td.td_flags = HTOO32( 2973 isread ? OHCI_TD_IN : OHCI_TD_OUT | 2974 OHCI_TD_NOCC | 2975 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 2976 if (xfer->ux_flags & USBD_SHORT_XFER_OK) 2977 data->td.td_flags |= HTOO32(OHCI_TD_R); 2978 data->td.td_cbp = HTOO32(DMAADDR(&xfer->ux_dmabuf, 0)); 2979 data->nexttd = tail; 2980 data->td.td_nexttd = HTOO32(tail->physaddr); 2981 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + len - 1); 2982 data->len = len; 2983 data->xfer = xfer; 2984 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 2985 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 2986 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2987 xfer->ux_hcpriv = data; 2988 2989 #ifdef OHCI_DEBUG 2990 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2991 if (ohcidebug > 5) { 2992 ohci_dump_ed(sc, sed); 2993 ohci_dump_tds(sc, data); 2994 } 2995 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2996 #endif 2997 2998 /* Insert ED in schedule */ 2999 mutex_enter(&sc->sc_lock); 3000 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3001 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3002 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3003 opipe->tail.td = tail; 3004 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3005 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3006 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3007 3008 #if 0 3009 /* 3010 * This goes horribly wrong, printing thousands of descriptors, 3011 * because false references are followed due to the fact that the 3012 * TD is gone. 3013 */ 3014 if (ohcidebug > 5) { 3015 usb_delay_ms_locked(&sc->sc_bus, 5, &sc->sc_lock); 3016 DPRINTF("status=%x", OREAD4(sc, OHCI_COMMAND_STATUS), 3017 0, 0, 0); 3018 ohci_dump_ed(sc, sed); 3019 ohci_dump_tds(sc, data); 3020 } 3021 #endif 3022 mutex_exit(&sc->sc_lock); 3023 3024 return USBD_IN_PROGRESS; 3025 } 3026 3027 /* Abort a device interrupt request. */ 3028 Static void 3029 ohci_device_intr_abort(struct usbd_xfer *xfer) 3030 { 3031 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3032 3033 KASSERT(mutex_owned(&sc->sc_lock)); 3034 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3035 3036 ohci_abort_xfer(xfer, USBD_CANCELLED); 3037 } 3038 3039 /* Close a device interrupt pipe. */ 3040 Static void 3041 ohci_device_intr_close(struct usbd_pipe *pipe) 3042 { 3043 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3044 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3045 int nslots = opipe->intr.nslots; 3046 int pos = opipe->intr.pos; 3047 int j; 3048 ohci_soft_ed_t *p, *sed = opipe->sed; 3049 3050 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3051 3052 KASSERT(mutex_owned(&sc->sc_lock)); 3053 3054 DPRINTFN(1, "pipe=%p nslots=%d pos=%d", pipe, nslots, pos, 0); 3055 usb_syncmem(&sed->dma, sed->offs, 3056 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3057 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3058 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3059 sizeof(sed->ed.ed_flags), 3060 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3061 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3062 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3063 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3064 3065 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3066 continue; 3067 KASSERT(p); 3068 p->next = sed->next; 3069 p->ed.ed_nexted = sed->ed.ed_nexted; 3070 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3071 sizeof(p->ed.ed_nexted), 3072 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3073 3074 for (j = 0; j < nslots; j++) 3075 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3076 3077 ohci_free_std(sc, opipe->tail.td); 3078 ohci_free_sed(sc, opipe->sed); 3079 } 3080 3081 Static usbd_status 3082 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3083 { 3084 int i, j, best; 3085 u_int npoll, slow, shigh, nslots; 3086 u_int bestbw, bw; 3087 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3088 3089 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3090 3091 DPRINTFN(2, "pipe=%p", opipe, 0, 0, 0); 3092 if (ival == 0) { 3093 printf("ohci_setintr: 0 interval\n"); 3094 return USBD_INVAL; 3095 } 3096 3097 npoll = OHCI_NO_INTRS; 3098 while (npoll > ival) 3099 npoll /= 2; 3100 DPRINTFN(2, "ival=%d npoll=%d", ival, npoll, 0, 0); 3101 3102 /* 3103 * We now know which level in the tree the ED must go into. 3104 * Figure out which slot has most bandwidth left over. 3105 * Slots to examine: 3106 * npoll 3107 * 1 0 3108 * 2 1 2 3109 * 4 3 4 5 6 3110 * 8 7 8 9 10 11 12 13 14 3111 * N (N-1) .. (N-1+N-1) 3112 */ 3113 slow = npoll-1; 3114 shigh = slow + npoll; 3115 nslots = OHCI_NO_INTRS / npoll; 3116 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3117 bw = 0; 3118 for (j = 0; j < nslots; j++) 3119 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3120 if (bw < bestbw) { 3121 best = i; 3122 bestbw = bw; 3123 } 3124 } 3125 DPRINTFN(2, "best=%d(%d..%d) bestbw=%d", best, slow, shigh, bestbw); 3126 3127 mutex_enter(&sc->sc_lock); 3128 hsed = sc->sc_eds[best]; 3129 sed->next = hsed->next; 3130 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3131 sizeof(hsed->ed.ed_flags), 3132 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3133 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3134 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3135 sizeof(sed->ed.ed_flags), 3136 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3137 hsed->next = sed; 3138 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3139 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3140 sizeof(hsed->ed.ed_flags), 3141 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3142 mutex_exit(&sc->sc_lock); 3143 3144 for (j = 0; j < nslots; j++) 3145 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3146 opipe->intr.nslots = nslots; 3147 opipe->intr.pos = best; 3148 3149 DPRINTFN(5, "returns %p", opipe, 0, 0, 0); 3150 return USBD_NORMAL_COMPLETION; 3151 } 3152 3153 /***********************/ 3154 3155 usbd_status 3156 ohci_device_isoc_transfer(struct usbd_xfer *xfer) 3157 { 3158 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3159 usbd_status err; 3160 3161 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3162 3163 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 3164 3165 /* Put it on our queue, */ 3166 mutex_enter(&sc->sc_lock); 3167 err = usb_insert_transfer(xfer); 3168 mutex_exit(&sc->sc_lock); 3169 3170 /* bail out on error, */ 3171 if (err && err != USBD_IN_PROGRESS) 3172 return err; 3173 3174 /* XXX should check inuse here */ 3175 3176 /* insert into schedule, */ 3177 ohci_device_isoc_enter(xfer); 3178 3179 /* and start if the pipe wasn't running */ 3180 if (!err) 3181 ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3182 3183 return err; 3184 } 3185 3186 void 3187 ohci_device_isoc_enter(struct usbd_xfer *xfer) 3188 { 3189 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3190 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3191 ohci_soft_ed_t *sed = opipe->sed; 3192 struct isoc *isoc = &opipe->isoc; 3193 ohci_soft_itd_t *sitd, *nsitd; 3194 ohci_physaddr_t buf, offs, noffs, bp0; 3195 int i, ncur, nframes; 3196 3197 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3198 3199 DPRINTFN(1, "used=%d next=%d xfer=%p nframes=%d", 3200 isoc->inuse, isoc->next, xfer, xfer->ux_nframes); 3201 3202 if (sc->sc_dying) 3203 return; 3204 3205 if (isoc->next == -1) { 3206 /* Not in use yet, schedule it a few frames ahead. */ 3207 isoc->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3208 DPRINTFN(2,"start next=%d", isoc->next, 0, 0, 0); 3209 } 3210 3211 sitd = opipe->tail.itd; 3212 buf = DMAADDR(&xfer->ux_dmabuf, 0); 3213 bp0 = OHCI_PAGE(buf); 3214 offs = OHCI_PAGE_OFFSET(buf); 3215 nframes = xfer->ux_nframes; 3216 xfer->ux_hcpriv = sitd; 3217 for (i = ncur = 0; i < nframes; i++, ncur++) { 3218 noffs = offs + xfer->ux_frlengths[i]; 3219 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3220 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3221 3222 /* Allocate next ITD */ 3223 mutex_enter(&sc->sc_lock); 3224 nsitd = ohci_alloc_sitd(sc); 3225 mutex_exit(&sc->sc_lock); 3226 if (nsitd == NULL) { 3227 /* XXX what now? */ 3228 printf("%s: isoc TD alloc failed\n", 3229 device_xname(sc->sc_dev)); 3230 return; 3231 } 3232 3233 /* Fill current ITD */ 3234 sitd->itd.itd_flags = HTOO32( 3235 OHCI_ITD_NOCC | 3236 OHCI_ITD_SET_SF(isoc->next) | 3237 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3238 OHCI_ITD_SET_FC(ncur)); 3239 sitd->itd.itd_bp0 = HTOO32(bp0); 3240 sitd->nextitd = nsitd; 3241 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3242 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3243 sitd->xfer = xfer; 3244 sitd->flags = 0; 3245 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3246 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3247 3248 sitd = nsitd; 3249 isoc->next = isoc->next + ncur; 3250 bp0 = OHCI_PAGE(buf + offs); 3251 ncur = 0; 3252 } 3253 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3254 offs = noffs; 3255 } 3256 mutex_enter(&sc->sc_lock); 3257 nsitd = ohci_alloc_sitd(sc); 3258 mutex_exit(&sc->sc_lock); 3259 if (nsitd == NULL) { 3260 /* XXX what now? */ 3261 printf("%s: isoc TD alloc failed\n", 3262 device_xname(sc->sc_dev)); 3263 return; 3264 } 3265 /* Fixup last used ITD */ 3266 sitd->itd.itd_flags = HTOO32( 3267 OHCI_ITD_NOCC | 3268 OHCI_ITD_SET_SF(isoc->next) | 3269 OHCI_ITD_SET_DI(0) | 3270 OHCI_ITD_SET_FC(ncur)); 3271 sitd->itd.itd_bp0 = HTOO32(bp0); 3272 sitd->nextitd = nsitd; 3273 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3274 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3275 sitd->xfer = xfer; 3276 sitd->flags = OHCI_CALL_DONE; 3277 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3278 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3279 3280 isoc->next = isoc->next + ncur; 3281 isoc->inuse += nframes; 3282 3283 xfer->ux_actlen = offs; /* XXX pretend we did it all */ 3284 3285 xfer->ux_status = USBD_IN_PROGRESS; 3286 3287 #ifdef OHCI_DEBUG 3288 if (ohcidebug > 5) { 3289 DPRINTF("frame=%d", O32TOH(sc->sc_hcca->hcca_frame_number), 3290 0, 0, 0); 3291 ohci_dump_itds(sc, xfer->ux_hcpriv); 3292 ohci_dump_ed(sc, sed); 3293 } 3294 #endif 3295 3296 mutex_enter(&sc->sc_lock); 3297 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3298 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3299 sed->ed.ed_tailp = HTOO32(nsitd->physaddr); 3300 opipe->tail.itd = nsitd; 3301 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3302 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3303 sizeof(sed->ed.ed_flags), 3304 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3305 mutex_exit(&sc->sc_lock); 3306 3307 #ifdef OHCI_DEBUG 3308 if (ohcidebug > 5) { 3309 delay(150000); 3310 DPRINTF("after frame=%d", O32TOH(sc->sc_hcca->hcca_frame_number), 3311 0, 0, 0); 3312 ohci_dump_itds(sc, xfer->ux_hcpriv); 3313 ohci_dump_ed(sc, sed); 3314 } 3315 #endif 3316 } 3317 3318 usbd_status 3319 ohci_device_isoc_start(struct usbd_xfer *xfer) 3320 { 3321 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3322 3323 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3324 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 3325 3326 mutex_enter(&sc->sc_lock); 3327 3328 if (sc->sc_dying) { 3329 mutex_exit(&sc->sc_lock); 3330 return USBD_IOERROR; 3331 } 3332 3333 3334 #ifdef DIAGNOSTIC 3335 if (xfer->ux_status != USBD_IN_PROGRESS) 3336 printf("ohci_device_isoc_start: not in progress %p\n", xfer); 3337 #endif 3338 3339 /* XXX anything to do? */ 3340 3341 mutex_exit(&sc->sc_lock); 3342 3343 return USBD_IN_PROGRESS; 3344 } 3345 3346 void 3347 ohci_device_isoc_abort(struct usbd_xfer *xfer) 3348 { 3349 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3350 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3351 ohci_soft_ed_t *sed; 3352 ohci_soft_itd_t *sitd; 3353 3354 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3355 DPRINTFN(1, "xfer=%p", xfer, 0, 0, 0); 3356 3357 KASSERT(mutex_owned(&sc->sc_lock)); 3358 3359 /* Transfer is already done. */ 3360 if (xfer->ux_status != USBD_NOT_STARTED && 3361 xfer->ux_status != USBD_IN_PROGRESS) { 3362 printf("ohci_device_isoc_abort: early return\n"); 3363 goto done; 3364 } 3365 3366 /* Give xfer the requested abort code. */ 3367 xfer->ux_status = USBD_CANCELLED; 3368 3369 sed = opipe->sed; 3370 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3371 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3372 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3373 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3374 sizeof(sed->ed.ed_flags), 3375 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3376 3377 sitd = xfer->ux_hcpriv; 3378 KASSERT(sitd); 3379 3380 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3381 #ifdef DIAGNOSTIC 3382 DPRINTFN(1, "abort sets done sitd=%p", sitd, 0, 0, 0); 3383 sitd->isdone = 1; 3384 #endif 3385 } 3386 3387 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3388 3389 /* Run callback. */ 3390 usb_transfer_complete(xfer); 3391 3392 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3393 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3394 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3395 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3396 3397 done: 3398 KASSERT(mutex_owned(&sc->sc_lock)); 3399 } 3400 3401 void 3402 ohci_device_isoc_done(struct usbd_xfer *xfer) 3403 { 3404 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3405 DPRINTFN(1, "xfer=%p", xfer, 0, 0, 0); 3406 } 3407 3408 usbd_status 3409 ohci_setup_isoc(struct usbd_pipe *pipe) 3410 { 3411 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3412 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3413 struct isoc *isoc = &opipe->isoc; 3414 3415 isoc->next = -1; 3416 isoc->inuse = 0; 3417 3418 mutex_enter(&sc->sc_lock); 3419 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3420 mutex_exit(&sc->sc_lock); 3421 3422 return USBD_NORMAL_COMPLETION; 3423 } 3424 3425 void 3426 ohci_device_isoc_close(struct usbd_pipe *pipe) 3427 { 3428 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3429 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3430 3431 KASSERT(mutex_owned(&sc->sc_lock)); 3432 3433 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3434 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3435 ohci_close_pipe(pipe, sc->sc_isoc_head); 3436 #ifdef DIAGNOSTIC 3437 opipe->tail.itd->isdone = 1; 3438 #endif 3439 ohci_free_sitd(sc, opipe->tail.itd); 3440 } 3441
Indexes created Fri Oct 03 02:09:57 GMT 2025