ohci.c revision 1.254.2.34
1 /* $NetBSD: ohci.c,v 1.254.2.34 2015/12/02 20:36:50 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * USB Open Host Controller driver. 38 * 39 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 40 * USB spec: http://www.usb.org/developers/docs/ 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.254.2.34 2015/12/02 20:36:50 skrll Exp $"); 45 46 #include "opt_usb.h" 47 48 #include <sys/param.h> 49 50 #include <sys/cpu.h> 51 #include <sys/device.h> 52 #include <sys/kernel.h> 53 #include <sys/kmem.h> 54 #include <sys/proc.h> 55 #include <sys/queue.h> 56 #include <sys/select.h> 57 #include <sys/sysctl.h> 58 #include <sys/systm.h> 59 60 #include <machine/endian.h> 61 62 #include <dev/usb/usb.h> 63 #include <dev/usb/usbdi.h> 64 #include <dev/usb/usbdivar.h> 65 #include <dev/usb/usb_mem.h> 66 #include <dev/usb/usb_quirks.h> 67 68 #include <dev/usb/ohcireg.h> 69 #include <dev/usb/ohcivar.h> 70 #include <dev/usb/usbroothub.h> 71 #include <dev/usb/usbhist.h> 72 73 #ifdef USB_DEBUG 74 #ifndef OHCI_DEBUG 75 #define ohcidebug 0 76 #else 77 static int ohcidebug = 0; 78 79 SYSCTL_SETUP(sysctl_hw_ohci_setup, "sysctl hw.ohci setup") 80 { 81 int err; 82 const struct sysctlnode *rnode; 83 const struct sysctlnode *cnode; 84 85 err = sysctl_createv(clog, 0, NULL, &rnode, 86 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ohci", 87 SYSCTL_DESCR("ohci global controls"), 88 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 89 90 if (err) 91 goto fail; 92 93 /* control debugging printfs */ 94 err = sysctl_createv(clog, 0, &rnode, &cnode, 95 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 96 "debug", SYSCTL_DESCR("Enable debugging output"), 97 NULL, 0, &ohcidebug, sizeof(ohcidebug), CTL_CREATE, CTL_EOL); 98 if (err) 99 goto fail; 100 101 return; 102 fail: 103 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 104 } 105 106 #endif /* OHCI_DEBUG */ 107 #endif /* USB_DEBUG */ 108 109 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ohcidebug,FMT,A,B,C,D) 110 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ohcidebug,N,FMT,A,B,C,D) 111 #define OHCIHIST_FUNC() USBHIST_FUNC() 112 #define OHCIHIST_CALLED(name) USBHIST_CALLED(ohcidebug) 113 114 #if BYTE_ORDER == BIG_ENDIAN 115 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 116 #else 117 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 118 #endif 119 120 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 121 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 122 #define HTOO16(val) O16TOH(val) 123 #define HTOO32(val) O32TOH(val) 124 125 struct ohci_pipe; 126 127 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 128 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 129 130 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 131 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 132 133 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 134 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 135 136 Static void ohci_free_std_chain(ohci_softc_t *, ohci_soft_td_t *, 137 ohci_soft_td_t *); 138 Static usbd_status ohci_alloc_std_chain(struct ohci_pipe *, 139 ohci_softc_t *, int, int, struct usbd_xfer *, 140 ohci_soft_td_t *, ohci_soft_td_t **); 141 142 Static usbd_status ohci_open(struct usbd_pipe *); 143 Static void ohci_poll(struct usbd_bus *); 144 Static void ohci_softintr(void *); 145 Static void ohci_waitintr(ohci_softc_t *, struct usbd_xfer *); 146 Static void ohci_rhsc(ohci_softc_t *, struct usbd_xfer *); 147 Static void ohci_rhsc_softint(void *); 148 149 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 150 ohci_soft_ed_t *); 151 152 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 153 ohci_soft_ed_t *); 154 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 155 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 156 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 157 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 158 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 159 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 160 161 Static usbd_status ohci_setup_isoc(struct usbd_pipe *); 162 Static void ohci_device_isoc_enter(struct usbd_xfer *); 163 164 Static struct usbd_xfer * 165 ohci_allocx(struct usbd_bus *, unsigned int); 166 Static void ohci_freex(struct usbd_bus *, struct usbd_xfer *); 167 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 168 Static int ohci_roothub_ctrl(struct usbd_bus *, 169 usb_device_request_t *, void *, int); 170 171 Static usbd_status ohci_root_intr_transfer(struct usbd_xfer *); 172 Static usbd_status ohci_root_intr_start(struct usbd_xfer *); 173 Static void ohci_root_intr_abort(struct usbd_xfer *); 174 Static void ohci_root_intr_close(struct usbd_pipe *); 175 Static void ohci_root_intr_done(struct usbd_xfer *); 176 177 Static usbd_status ohci_device_ctrl_transfer(struct usbd_xfer *); 178 Static usbd_status ohci_device_ctrl_start(struct usbd_xfer *); 179 Static void ohci_device_ctrl_abort(struct usbd_xfer *); 180 Static void ohci_device_ctrl_close(struct usbd_pipe *); 181 Static void ohci_device_ctrl_done(struct usbd_xfer *); 182 183 Static usbd_status ohci_device_bulk_transfer(struct usbd_xfer *); 184 Static usbd_status ohci_device_bulk_start(struct usbd_xfer *); 185 Static void ohci_device_bulk_abort(struct usbd_xfer *); 186 Static void ohci_device_bulk_close(struct usbd_pipe *); 187 Static void ohci_device_bulk_done(struct usbd_xfer *); 188 189 Static usbd_status ohci_device_intr_transfer(struct usbd_xfer *); 190 Static usbd_status ohci_device_intr_start(struct usbd_xfer *); 191 Static void ohci_device_intr_abort(struct usbd_xfer *); 192 Static void ohci_device_intr_close(struct usbd_pipe *); 193 Static void ohci_device_intr_done(struct usbd_xfer *); 194 195 Static usbd_status ohci_device_isoc_transfer(struct usbd_xfer *); 196 Static usbd_status ohci_device_isoc_start(struct usbd_xfer *); 197 Static void ohci_device_isoc_abort(struct usbd_xfer *); 198 Static void ohci_device_isoc_close(struct usbd_pipe *); 199 Static void ohci_device_isoc_done(struct usbd_xfer *); 200 201 Static usbd_status ohci_device_setintr(ohci_softc_t *, 202 struct ohci_pipe *, int); 203 204 Static void ohci_timeout(void *); 205 Static void ohci_timeout_task(void *); 206 Static void ohci_rhsc_enable(void *); 207 208 Static void ohci_close_pipe(struct usbd_pipe *, ohci_soft_ed_t *); 209 Static void ohci_abort_xfer(struct usbd_xfer *, usbd_status); 210 211 Static void ohci_device_clear_toggle(struct usbd_pipe *); 212 Static void ohci_noop(struct usbd_pipe *); 213 214 #ifdef OHCI_DEBUG 215 Static void ohci_dumpregs(ohci_softc_t *); 216 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 217 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 218 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 219 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 220 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 221 #endif 222 223 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 224 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 225 #define OWRITE1(sc, r, x) \ 226 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 227 #define OWRITE2(sc, r, x) \ 228 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 229 #define OWRITE4(sc, r, x) \ 230 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 231 232 static __inline uint32_t 233 OREAD4(ohci_softc_t *sc, bus_size_t r) 234 { 235 236 OBARR(sc); 237 return bus_space_read_4(sc->iot, sc->ioh, r); 238 } 239 240 /* Reverse the bits in a value 0 .. 31 */ 241 Static uint8_t revbits[OHCI_NO_INTRS] = 242 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 243 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 244 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 245 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 246 247 struct ohci_pipe { 248 struct usbd_pipe pipe; 249 ohci_soft_ed_t *sed; 250 union { 251 ohci_soft_td_t *td; 252 ohci_soft_itd_t *itd; 253 } tail; 254 /* Info needed for different pipe kinds. */ 255 union { 256 /* Control pipe */ 257 struct { 258 usb_dma_t reqdma; 259 } ctrl; 260 /* Interrupt pipe */ 261 struct { 262 int nslots; 263 int pos; 264 } intr; 265 /* Isochronous pipe */ 266 struct isoc { 267 int next, inuse; 268 } isoc; 269 }; 270 }; 271 272 Static const struct usbd_bus_methods ohci_bus_methods = { 273 .ubm_open = ohci_open, 274 .ubm_softint = ohci_softintr, 275 .ubm_dopoll = ohci_poll, 276 .ubm_allocx = ohci_allocx, 277 .ubm_freex = ohci_freex, 278 .ubm_getlock = ohci_get_lock, 279 .ubm_rhctrl = ohci_roothub_ctrl, 280 }; 281 282 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 283 .upm_transfer = ohci_root_intr_transfer, 284 .upm_start = ohci_root_intr_start, 285 .upm_abort = ohci_root_intr_abort, 286 .upm_close = ohci_root_intr_close, 287 .upm_cleartoggle = ohci_noop, 288 .upm_done = ohci_root_intr_done, 289 }; 290 291 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 292 .upm_transfer = ohci_device_ctrl_transfer, 293 .upm_start = ohci_device_ctrl_start, 294 .upm_abort = ohci_device_ctrl_abort, 295 .upm_close = ohci_device_ctrl_close, 296 .upm_cleartoggle = ohci_noop, 297 .upm_done = ohci_device_ctrl_done, 298 }; 299 300 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 301 .upm_transfer = ohci_device_intr_transfer, 302 .upm_start = ohci_device_intr_start, 303 .upm_abort = ohci_device_intr_abort, 304 .upm_close = ohci_device_intr_close, 305 .upm_cleartoggle = ohci_device_clear_toggle, 306 .upm_done = ohci_device_intr_done, 307 }; 308 309 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 310 .upm_transfer = ohci_device_bulk_transfer, 311 .upm_start = ohci_device_bulk_start, 312 .upm_abort = ohci_device_bulk_abort, 313 .upm_close = ohci_device_bulk_close, 314 .upm_cleartoggle = ohci_device_clear_toggle, 315 .upm_done = ohci_device_bulk_done, 316 }; 317 318 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 319 .upm_transfer = ohci_device_isoc_transfer, 320 .upm_start = ohci_device_isoc_start, 321 .upm_abort = ohci_device_isoc_abort, 322 .upm_close = ohci_device_isoc_close, 323 .upm_cleartoggle = ohci_noop, 324 .upm_done = ohci_device_isoc_done, 325 }; 326 327 int 328 ohci_activate(device_t self, enum devact act) 329 { 330 struct ohci_softc *sc = device_private(self); 331 332 switch (act) { 333 case DVACT_DEACTIVATE: 334 sc->sc_dying = 1; 335 return 0; 336 default: 337 return EOPNOTSUPP; 338 } 339 } 340 341 void 342 ohci_childdet(device_t self, device_t child) 343 { 344 struct ohci_softc *sc = device_private(self); 345 346 KASSERT(sc->sc_child == child); 347 sc->sc_child = NULL; 348 } 349 350 int 351 ohci_detach(struct ohci_softc *sc, int flags) 352 { 353 int rv = 0; 354 355 if (sc->sc_child != NULL) 356 rv = config_detach(sc->sc_child, flags); 357 358 if (rv != 0) 359 return rv; 360 361 callout_halt(&sc->sc_tmo_rhsc, &sc->sc_lock); 362 363 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 364 callout_destroy(&sc->sc_tmo_rhsc); 365 366 softint_disestablish(sc->sc_rhsc_si); 367 368 cv_destroy(&sc->sc_softwake_cv); 369 370 mutex_destroy(&sc->sc_lock); 371 mutex_destroy(&sc->sc_intr_lock); 372 373 if (sc->sc_hcca != NULL) 374 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 375 pool_cache_destroy(sc->sc_xferpool); 376 377 return rv; 378 } 379 380 ohci_soft_ed_t * 381 ohci_alloc_sed(ohci_softc_t *sc) 382 { 383 ohci_soft_ed_t *sed; 384 usbd_status err; 385 int i, offs; 386 usb_dma_t dma; 387 388 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 389 390 if (sc->sc_freeeds == NULL) { 391 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 392 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 393 OHCI_ED_ALIGN, &dma); 394 if (err) 395 return 0; 396 for (i = 0; i < OHCI_SED_CHUNK; i++) { 397 offs = i * OHCI_SED_SIZE; 398 sed = KERNADDR(&dma, offs); 399 sed->physaddr = DMAADDR(&dma, offs); 400 sed->dma = dma; 401 sed->offs = offs; 402 sed->next = sc->sc_freeeds; 403 sc->sc_freeeds = sed; 404 } 405 } 406 sed = sc->sc_freeeds; 407 sc->sc_freeeds = sed->next; 408 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 409 sed->next = 0; 410 return sed; 411 } 412 413 void 414 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 415 { 416 sed->next = sc->sc_freeeds; 417 sc->sc_freeeds = sed; 418 } 419 420 ohci_soft_td_t * 421 ohci_alloc_std(ohci_softc_t *sc) 422 { 423 ohci_soft_td_t *std; 424 usbd_status err; 425 int i, offs; 426 usb_dma_t dma; 427 428 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 429 430 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 431 432 if (sc->sc_freetds == NULL) { 433 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 434 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 435 OHCI_TD_ALIGN, &dma); 436 if (err) 437 return NULL; 438 for(i = 0; i < OHCI_STD_CHUNK; i++) { 439 offs = i * OHCI_STD_SIZE; 440 std = KERNADDR(&dma, offs); 441 std->physaddr = DMAADDR(&dma, offs); 442 std->dma = dma; 443 std->offs = offs; 444 std->nexttd = sc->sc_freetds; 445 sc->sc_freetds = std; 446 } 447 } 448 449 std = sc->sc_freetds; 450 sc->sc_freetds = std->nexttd; 451 memset(&std->td, 0, sizeof(ohci_td_t)); 452 std->nexttd = NULL; 453 std->xfer = NULL; 454 ohci_hash_add_td(sc, std); 455 456 return std; 457 } 458 459 void 460 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 461 { 462 463 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 464 465 ohci_hash_rem_td(sc, std); 466 std->nexttd = sc->sc_freetds; 467 sc->sc_freetds = std; 468 } 469 470 usbd_status 471 ohci_alloc_std_chain(struct ohci_pipe *opipe, ohci_softc_t *sc, 472 int alen, int rd, struct usbd_xfer *xfer, 473 ohci_soft_td_t *sp, ohci_soft_td_t **ep) 474 { 475 ohci_soft_td_t *next, *cur; 476 ohci_physaddr_t dataphys, dataphysend; 477 uint32_t tdflags; 478 int len, curlen; 479 usb_dma_t *dma = &xfer->ux_dmabuf; 480 uint16_t flags = xfer->ux_flags; 481 482 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 483 DPRINTF("start len=%d", alen, 0, 0, 0); 484 485 KASSERT(mutex_owned(&sc->sc_lock)); 486 487 DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d", 488 opipe->pipe.up_dev->ud_addr, 489 UE_GET_ADDR(opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress), 490 alen, opipe->pipe.up_dev->ud_speed); 491 492 len = alen; 493 cur = sp; 494 dataphys = DMAADDR(dma, 0); 495 dataphysend = OHCI_PAGE(dataphys + len - 1); 496 usb_syncmem(dma, 0, len, 497 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 498 tdflags = HTOO32( 499 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 500 (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) | 501 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 502 503 for (;;) { 504 next = ohci_alloc_std(sc); 505 if (next == NULL) 506 goto nomem; 507 508 /* The OHCI hardware can handle at most one page crossing. */ 509 if (OHCI_PAGE(dataphys) == dataphysend || 510 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 511 /* we can handle it in this TD */ 512 curlen = len; 513 } else { 514 /* must use multiple TDs, fill as much as possible. */ 515 curlen = 2 * OHCI_PAGE_SIZE - 516 (dataphys & (OHCI_PAGE_SIZE-1)); 517 /* the length must be a multiple of the max size */ 518 curlen -= curlen % UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 519 KASSERT(curlen != 0); 520 } 521 DPRINTFN(4, "dataphys=0x%08x dataphysend=0x%08x " 522 "len=%d curlen=%d", dataphys, dataphysend, len, curlen); 523 len -= curlen; 524 525 cur->td.td_flags = tdflags; 526 cur->td.td_cbp = HTOO32(dataphys); 527 cur->td.td_nexttd = HTOO32(next->physaddr); 528 cur->td.td_be = HTOO32(dataphys + curlen - 1); 529 cur->nexttd = next; 530 cur->len = curlen; 531 cur->flags = OHCI_ADD_LEN; 532 cur->xfer = xfer; 533 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 534 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 535 DPRINTFN(10, "cbp=0x%08x be=0x%08x", dataphys, 536 dataphys + curlen - 1, 0, 0); 537 if (len == 0) 538 break; 539 DPRINTFN(10, "extend chain", 0, 0, 0, 0); 540 dataphys += curlen; 541 cur = next; 542 } 543 if (!rd && (flags & USBD_FORCE_SHORT_XFER) && 544 alen % UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize) == 0) { 545 /* Force a 0 length transfer at the end. */ 546 547 cur = next; 548 next = ohci_alloc_std(sc); 549 if (next == NULL) 550 goto nomem; 551 552 cur->td.td_flags = tdflags; 553 cur->td.td_cbp = 0; /* indicate 0 length packet */ 554 cur->td.td_nexttd = HTOO32(next->physaddr); 555 cur->td.td_be = ~0; 556 cur->nexttd = next; 557 cur->len = 0; 558 cur->flags = 0; 559 cur->xfer = xfer; 560 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 561 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 562 DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0); 563 } 564 *ep = cur; 565 566 return USBD_NORMAL_COMPLETION; 567 568 nomem: 569 570 /* Don't free sp - let the caller do that */ 571 ohci_free_std_chain(sc, sp->nexttd, NULL); 572 573 return USBD_NOMEM; 574 } 575 576 Static void 577 ohci_free_std_chain(ohci_softc_t *sc, ohci_soft_td_t *std, 578 ohci_soft_td_t *stdend) 579 { 580 ohci_soft_td_t *p; 581 582 for (; std != stdend; std = p) { 583 p = std->nexttd; 584 ohci_free_std(sc, std); 585 } 586 } 587 588 ohci_soft_itd_t * 589 ohci_alloc_sitd(ohci_softc_t *sc) 590 { 591 ohci_soft_itd_t *sitd; 592 usbd_status err; 593 int i, offs; 594 usb_dma_t dma; 595 596 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 597 598 if (sc->sc_freeitds == NULL) { 599 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 600 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 601 OHCI_ITD_ALIGN, &dma); 602 if (err) 603 return NULL; 604 for(i = 0; i < OHCI_SITD_CHUNK; i++) { 605 offs = i * OHCI_SITD_SIZE; 606 sitd = KERNADDR(&dma, offs); 607 sitd->physaddr = DMAADDR(&dma, offs); 608 sitd->dma = dma; 609 sitd->offs = offs; 610 sitd->nextitd = sc->sc_freeitds; 611 sc->sc_freeitds = sitd; 612 } 613 } 614 615 sitd = sc->sc_freeitds; 616 sc->sc_freeitds = sitd->nextitd; 617 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 618 sitd->nextitd = NULL; 619 sitd->xfer = NULL; 620 ohci_hash_add_itd(sc, sitd); 621 622 #ifdef DIAGNOSTIC 623 sitd->isdone = false; 624 #endif 625 626 return sitd; 627 } 628 629 void 630 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 631 { 632 633 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 634 DPRINTFN(10, "sitd=%p", sitd, 0, 0, 0); 635 636 KASSERT(sitd->isdone); 637 #ifdef DIAGNOSTIC 638 /* Warn double free */ 639 sitd->isdone = false; 640 #endif 641 642 ohci_hash_rem_itd(sc, sitd); 643 sitd->nextitd = sc->sc_freeitds; 644 sc->sc_freeitds = sitd; 645 } 646 647 int 648 ohci_init(ohci_softc_t *sc) 649 { 650 ohci_soft_ed_t *sed, *psed; 651 usbd_status err; 652 int i; 653 uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */; 654 655 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 656 657 aprint_normal_dev(sc->sc_dev, ""); 658 659 sc->sc_hcca = NULL; 660 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 661 662 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 663 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 664 cv_init(&sc->sc_softwake_cv, "ohciab"); 665 666 sc->sc_rhsc_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 667 ohci_rhsc_softint, sc); 668 669 for (i = 0; i < OHCI_HASH_SIZE; i++) 670 LIST_INIT(&sc->sc_hash_tds[i]); 671 for (i = 0; i < OHCI_HASH_SIZE; i++) 672 LIST_INIT(&sc->sc_hash_itds[i]); 673 674 sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0, 675 "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL); 676 677 rev = OREAD4(sc, OHCI_REVISION); 678 aprint_normal("OHCI version %d.%d%s\n", 679 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 680 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 681 682 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 683 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 684 sc->sc_bus.ub_revision = USBREV_UNKNOWN; 685 return -1; 686 } 687 sc->sc_bus.ub_revision = USBREV_1_0; 688 sc->sc_bus.ub_usedma = true; 689 690 /* XXX determine alignment by R/W */ 691 /* Allocate the HCCA area. */ 692 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 693 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 694 if (err) { 695 sc->sc_hcca = NULL; 696 return err; 697 } 698 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 699 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 700 701 sc->sc_eintrs = OHCI_NORMAL_INTRS; 702 703 /* Allocate dummy ED that starts the control list. */ 704 sc->sc_ctrl_head = ohci_alloc_sed(sc); 705 if (sc->sc_ctrl_head == NULL) { 706 err = ENOMEM; 707 goto bad1; 708 } 709 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 710 711 /* Allocate dummy ED that starts the bulk list. */ 712 sc->sc_bulk_head = ohci_alloc_sed(sc); 713 if (sc->sc_bulk_head == NULL) { 714 err = ENOMEM; 715 goto bad2; 716 } 717 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 718 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 719 sizeof(sc->sc_bulk_head->ed), 720 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 721 722 /* Allocate dummy ED that starts the isochronous list. */ 723 sc->sc_isoc_head = ohci_alloc_sed(sc); 724 if (sc->sc_isoc_head == NULL) { 725 err = ENOMEM; 726 goto bad3; 727 } 728 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 729 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 730 sizeof(sc->sc_isoc_head->ed), 731 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 732 733 /* Allocate all the dummy EDs that make up the interrupt tree. */ 734 for (i = 0; i < OHCI_NO_EDS; i++) { 735 sed = ohci_alloc_sed(sc); 736 if (sed == NULL) { 737 while (--i >= 0) 738 ohci_free_sed(sc, sc->sc_eds[i]); 739 err = ENOMEM; 740 goto bad4; 741 } 742 /* All ED fields are set to 0. */ 743 sc->sc_eds[i] = sed; 744 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 745 if (i != 0) 746 psed = sc->sc_eds[(i-1) / 2]; 747 else 748 psed= sc->sc_isoc_head; 749 sed->next = psed; 750 sed->ed.ed_nexted = HTOO32(psed->physaddr); 751 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 752 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 753 } 754 /* 755 * Fill HCCA interrupt table. The bit reversal is to get 756 * the tree set up properly to spread the interrupts. 757 */ 758 for (i = 0; i < OHCI_NO_INTRS; i++) 759 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 760 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 761 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 762 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 763 764 #ifdef OHCI_DEBUG 765 DPRINTFN(15, "--- dump start ---", 0, 0, 0 ,0); 766 if (ohcidebug > 15) { 767 for (i = 0; i < OHCI_NO_EDS; i++) { 768 DPRINTFN(15, "ed#%d ", i, 0, 0, 0); 769 ohci_dump_ed(sc, sc->sc_eds[i]); 770 } 771 DPRINTFN(15, "iso", 0, 0, 0 ,0); 772 ohci_dump_ed(sc, sc->sc_isoc_head); 773 } 774 DPRINTFN(15, "--- dump end ---", 0, 0, 0 ,0); 775 #endif 776 777 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 778 ctl = OREAD4(sc, OHCI_CONTROL); 779 rwc = ctl & OHCI_RWC; 780 fm = OREAD4(sc, OHCI_FM_INTERVAL); 781 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 782 /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */ 783 784 /* Determine in what context we are running. */ 785 if (ctl & OHCI_IR) { 786 /* SMM active, request change */ 787 DPRINTF("SMM active, request owner change", 0, 0, 0, 0); 788 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 789 (OHCI_OC | OHCI_MIE)) 790 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 791 s = OREAD4(sc, OHCI_COMMAND_STATUS); 792 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 793 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 794 usb_delay_ms(&sc->sc_bus, 1); 795 ctl = OREAD4(sc, OHCI_CONTROL); 796 } 797 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 798 if ((ctl & OHCI_IR) == 0) { 799 aprint_error_dev(sc->sc_dev, 800 "SMM does not respond, resetting\n"); 801 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 802 goto reset; 803 } 804 #if 0 805 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 806 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 807 /* BIOS started controller. */ 808 DPRINTF("BIOS active", 0, 0, 0, 0); 809 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 810 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 811 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 812 } 813 #endif 814 } else { 815 DPRINTF("cold started", 0 ,0 ,0 ,0); 816 reset: 817 /* Controller was cold started. */ 818 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 819 } 820 821 /* 822 * This reset should not be necessary according to the OHCI spec, but 823 * without it some controllers do not start. 824 */ 825 DPRINTF("sc %p: resetting", sc, 0, 0, 0); 826 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 827 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 828 829 /* We now own the host controller and the bus has been reset. */ 830 831 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 832 /* Nominal time for a reset is 10 us. */ 833 for (i = 0; i < 10; i++) { 834 delay(10); 835 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 836 if (!hcr) 837 break; 838 } 839 if (hcr) { 840 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 841 err = EIO; 842 goto bad5; 843 } 844 #ifdef OHCI_DEBUG 845 if (ohcidebug > 15) 846 ohci_dumpregs(sc); 847 #endif 848 849 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 850 851 /* Set up HC registers. */ 852 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 853 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 854 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 855 /* disable all interrupts and then switch on all desired interrupts */ 856 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 857 /* switch on desired functional features */ 858 ctl = OREAD4(sc, OHCI_CONTROL); 859 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 860 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 861 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 862 /* And finally start it! */ 863 OWRITE4(sc, OHCI_CONTROL, ctl); 864 865 /* 866 * The controller is now OPERATIONAL. Set a some final 867 * registers that should be set earlier, but that the 868 * controller ignores when in the SUSPEND state. 869 */ 870 ival = OHCI_GET_IVAL(fm); 871 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 872 fm |= OHCI_FSMPS(ival) | ival; 873 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 874 per = OHCI_PERIODIC(ival); /* 90% periodic */ 875 OWRITE4(sc, OHCI_PERIODIC_START, per); 876 877 if (sc->sc_flags & OHCIF_SUPERIO) { 878 /* no overcurrent protection */ 879 desca |= OHCI_NOCP; 880 /* 881 * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning 882 * that 883 * - ports are always power switched 884 * - don't wait for powered root hub port 885 */ 886 desca &= ~(__SHIFTIN(0xff, OHCI_POTPGT_MASK) | OHCI_NPS); 887 } 888 889 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 890 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 891 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 892 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 893 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 894 895 /* 896 * The AMD756 requires a delay before re-reading the register, 897 * otherwise it will occasionally report 0 ports. 898 */ 899 sc->sc_noport = 0; 900 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 901 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 902 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 903 } 904 905 #ifdef OHCI_DEBUG 906 if (ohcidebug > 5) 907 ohci_dumpregs(sc); 908 #endif 909 910 /* Set up the bus struct. */ 911 sc->sc_bus.ub_methods = &ohci_bus_methods; 912 sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe); 913 914 sc->sc_control = sc->sc_intre = 0; 915 916 /* Finally, turn on interrupts. */ 917 DPRINTF("enabling %#x", sc->sc_eintrs | OHCI_MIE, 0, 0, 0); 918 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 919 920 return 0; 921 922 bad5: 923 for (i = 0; i < OHCI_NO_EDS; i++) 924 ohci_free_sed(sc, sc->sc_eds[i]); 925 bad4: 926 ohci_free_sed(sc, sc->sc_isoc_head); 927 bad3: 928 ohci_free_sed(sc, sc->sc_bulk_head); 929 bad2: 930 ohci_free_sed(sc, sc->sc_ctrl_head); 931 bad1: 932 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 933 sc->sc_hcca = NULL; 934 return err; 935 } 936 937 struct usbd_xfer * 938 ohci_allocx(struct usbd_bus *bus, unsigned int nframes) 939 { 940 ohci_softc_t *sc = OHCI_BUS2SC(bus); 941 struct usbd_xfer *xfer; 942 943 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 944 if (xfer != NULL) { 945 memset(xfer, 0, sizeof(struct ohci_xfer)); 946 #ifdef DIAGNOSTIC 947 xfer->ux_state = XFER_BUSY; 948 #endif 949 } 950 return xfer; 951 } 952 953 void 954 ohci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 955 { 956 ohci_softc_t *sc = OHCI_BUS2SC(bus); 957 958 KASSERTMSG(xfer->ux_state == XFER_BUSY, 959 "xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state); 960 #ifdef DIAGNOSTIC 961 xfer->ux_state = XFER_FREE; 962 #endif 963 pool_cache_put(sc->sc_xferpool, xfer); 964 } 965 966 Static void 967 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 968 { 969 ohci_softc_t *sc = OHCI_BUS2SC(bus); 970 971 *lock = &sc->sc_lock; 972 } 973 974 /* 975 * Shut down the controller when the system is going down. 976 */ 977 bool 978 ohci_shutdown(device_t self, int flags) 979 { 980 ohci_softc_t *sc = device_private(self); 981 982 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 983 984 DPRINTF("stopping the HC", 0, 0, 0, 0); 985 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 986 return true; 987 } 988 989 bool 990 ohci_resume(device_t dv, const pmf_qual_t *qual) 991 { 992 ohci_softc_t *sc = device_private(dv); 993 uint32_t ctl; 994 995 mutex_spin_enter(&sc->sc_intr_lock); 996 sc->sc_bus.ub_usepolling++; 997 mutex_spin_exit(&sc->sc_intr_lock); 998 999 /* Some broken BIOSes do not recover these values */ 1000 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1001 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1002 sc->sc_ctrl_head->physaddr); 1003 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1004 sc->sc_bulk_head->physaddr); 1005 if (sc->sc_intre) 1006 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1007 (OHCI_ALL_INTRS | OHCI_MIE)); 1008 if (sc->sc_control) 1009 ctl = sc->sc_control; 1010 else 1011 ctl = OREAD4(sc, OHCI_CONTROL); 1012 ctl |= OHCI_HCFS_RESUME; 1013 OWRITE4(sc, OHCI_CONTROL, ctl); 1014 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1015 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1016 OWRITE4(sc, OHCI_CONTROL, ctl); 1017 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1018 sc->sc_control = sc->sc_intre = 0; 1019 1020 mutex_spin_enter(&sc->sc_intr_lock); 1021 sc->sc_bus.ub_usepolling--; 1022 mutex_spin_exit(&sc->sc_intr_lock); 1023 1024 return true; 1025 } 1026 1027 bool 1028 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1029 { 1030 ohci_softc_t *sc = device_private(dv); 1031 uint32_t ctl; 1032 1033 mutex_spin_enter(&sc->sc_intr_lock); 1034 sc->sc_bus.ub_usepolling++; 1035 mutex_spin_exit(&sc->sc_intr_lock); 1036 1037 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1038 if (sc->sc_control == 0) { 1039 /* 1040 * Preserve register values, in case that BIOS 1041 * does not recover them. 1042 */ 1043 sc->sc_control = ctl; 1044 sc->sc_intre = OREAD4(sc, 1045 OHCI_INTERRUPT_ENABLE); 1046 } 1047 ctl |= OHCI_HCFS_SUSPEND; 1048 OWRITE4(sc, OHCI_CONTROL, ctl); 1049 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1050 1051 mutex_spin_enter(&sc->sc_intr_lock); 1052 sc->sc_bus.ub_usepolling--; 1053 mutex_spin_exit(&sc->sc_intr_lock); 1054 1055 return true; 1056 } 1057 1058 #ifdef OHCI_DEBUG 1059 void 1060 ohci_dumpregs(ohci_softc_t *sc) 1061 { 1062 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1063 1064 DPRINTF("rev=0x%08x control=0x%08x command=0x%08x", 1065 OREAD4(sc, OHCI_REVISION), 1066 OREAD4(sc, OHCI_CONTROL), 1067 OREAD4(sc, OHCI_COMMAND_STATUS), 0); 1068 DPRINTF(" intrstat=0x%08x intre=0x%08x intrd=0x%08x", 1069 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1070 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1071 OREAD4(sc, OHCI_INTERRUPT_DISABLE), 0); 1072 DPRINTF(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x", 1073 OREAD4(sc, OHCI_HCCA), 1074 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1075 OREAD4(sc, OHCI_CONTROL_HEAD_ED), 0); 1076 DPRINTF(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x", 1077 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1078 OREAD4(sc, OHCI_BULK_HEAD_ED), 1079 OREAD4(sc, OHCI_BULK_CURRENT_ED) ,0); 1080 DPRINTF(" done=0x%08x fmival=0x%08x fmrem=0x%08x", 1081 OREAD4(sc, OHCI_DONE_HEAD), 1082 OREAD4(sc, OHCI_FM_INTERVAL), 1083 OREAD4(sc, OHCI_FM_REMAINING), 0); 1084 DPRINTF(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x", 1085 OREAD4(sc, OHCI_FM_NUMBER), 1086 OREAD4(sc, OHCI_PERIODIC_START), 1087 OREAD4(sc, OHCI_LS_THRESHOLD), 0); 1088 DPRINTF(" desca=0x%08x descb=0x%08x stat=0x%08x", 1089 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1090 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1091 OREAD4(sc, OHCI_RH_STATUS), 0); 1092 DPRINTF(" port1=0x%08x port2=0x%08x", 1093 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1094 OREAD4(sc, OHCI_RH_PORT_STATUS(2)), 0, 0); 1095 DPRINTF(" HCCA: frame_number=0x%04x done_head=0x%08x", 1096 O32TOH(sc->sc_hcca->hcca_frame_number), 1097 O32TOH(sc->sc_hcca->hcca_done_head), 0, 0); 1098 } 1099 #endif 1100 1101 Static int ohci_intr1(ohci_softc_t *); 1102 1103 int 1104 ohci_intr(void *p) 1105 { 1106 ohci_softc_t *sc = p; 1107 int ret = 0; 1108 1109 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1110 1111 if (sc == NULL) 1112 return 0; 1113 1114 mutex_spin_enter(&sc->sc_intr_lock); 1115 1116 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1117 goto done; 1118 1119 /* If we get an interrupt while polling, then just ignore it. */ 1120 if (sc->sc_bus.ub_usepolling) { 1121 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1122 /* for level triggered intrs, should do something to ack */ 1123 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1124 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1125 1126 goto done; 1127 } 1128 1129 ret = ohci_intr1(sc); 1130 1131 done: 1132 mutex_spin_exit(&sc->sc_intr_lock); 1133 return ret; 1134 } 1135 1136 Static int 1137 ohci_intr1(ohci_softc_t *sc) 1138 { 1139 uint32_t intrs, eintrs; 1140 1141 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1142 1143 /* In case the interrupt occurs before initialization has completed. */ 1144 if (sc == NULL || sc->sc_hcca == NULL) { 1145 #ifdef DIAGNOSTIC 1146 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1147 #endif 1148 return 0; 1149 } 1150 1151 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1152 1153 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1154 if (!intrs) 1155 return 0; 1156 1157 /* Acknowledge */ 1158 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); 1159 eintrs = intrs & sc->sc_eintrs; 1160 DPRINTFN(7, "sc=%p", sc, 0, 0, 0); 1161 DPRINTFN(7, "intrs=%#x(%#x) eintrs=%#x(%#x)", 1162 intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), eintrs, 1163 sc->sc_eintrs); 1164 1165 if (!eintrs) { 1166 return 0; 1167 } 1168 1169 if (eintrs & OHCI_SO) { 1170 sc->sc_overrun_cnt++; 1171 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1172 printf("%s: %u scheduling overruns\n", 1173 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1174 sc->sc_overrun_cnt = 0; 1175 } 1176 /* XXX do what */ 1177 eintrs &= ~OHCI_SO; 1178 } 1179 if (eintrs & OHCI_WDH) { 1180 /* 1181 * We block the interrupt below, and reenable it later from 1182 * ohci_softintr(). 1183 */ 1184 usb_schedsoftintr(&sc->sc_bus); 1185 } 1186 if (eintrs & OHCI_RD) { 1187 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1188 /* XXX process resume detect */ 1189 } 1190 if (eintrs & OHCI_UE) { 1191 printf("%s: unrecoverable error, controller halted\n", 1192 device_xname(sc->sc_dev)); 1193 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1194 /* XXX what else */ 1195 } 1196 if (eintrs & OHCI_RHSC) { 1197 /* 1198 * We block the interrupt below, and reenable it later from 1199 * a timeout. 1200 */ 1201 softint_schedule(sc->sc_rhsc_si); 1202 } 1203 1204 if (eintrs != 0) { 1205 /* Block unprocessed interrupts. */ 1206 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1207 sc->sc_eintrs &= ~eintrs; 1208 DPRINTF("sc %p blocking intrs 0x%x", sc, eintrs, 0, 0); 1209 } 1210 1211 return 1; 1212 } 1213 1214 void 1215 ohci_rhsc_enable(void *v_sc) 1216 { 1217 ohci_softc_t *sc = v_sc; 1218 1219 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1220 DPRINTF("sc %p", sc, 0, 0, 0); 1221 mutex_spin_enter(&sc->sc_intr_lock); 1222 sc->sc_eintrs |= OHCI_RHSC; 1223 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1224 mutex_spin_exit(&sc->sc_intr_lock); 1225 } 1226 1227 #ifdef OHCI_DEBUG 1228 const char *ohci_cc_strs[] = { 1229 "NO_ERROR", 1230 "CRC", 1231 "BIT_STUFFING", 1232 "DATA_TOGGLE_MISMATCH", 1233 "STALL", 1234 "DEVICE_NOT_RESPONDING", 1235 "PID_CHECK_FAILURE", 1236 "UNEXPECTED_PID", 1237 "DATA_OVERRUN", 1238 "DATA_UNDERRUN", 1239 "BUFFER_OVERRUN", 1240 "BUFFER_UNDERRUN", 1241 "reserved", 1242 "reserved", 1243 "NOT_ACCESSED", 1244 "NOT_ACCESSED", 1245 }; 1246 #endif 1247 1248 void 1249 ohci_softintr(void *v) 1250 { 1251 struct usbd_bus *bus = v; 1252 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1253 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1254 ohci_soft_td_t *std, *sdone, *stdnext; 1255 struct usbd_xfer *xfer; 1256 struct ohci_pipe *opipe; 1257 int len, cc; 1258 int i, j, actlen, iframes, uedir; 1259 ohci_physaddr_t done; 1260 1261 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1262 1263 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1264 1265 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1266 sizeof(sc->sc_hcca->hcca_done_head), 1267 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1268 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1269 sc->sc_hcca->hcca_done_head = 0; 1270 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1271 sizeof(sc->sc_hcca->hcca_done_head), 1272 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1273 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1274 sc->sc_eintrs |= OHCI_WDH; 1275 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1276 1277 /* Reverse the done list. */ 1278 for (sdone = NULL, sidone = NULL; done != 0; ) { 1279 std = ohci_hash_find_td(sc, done); 1280 if (std != NULL) { 1281 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1282 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1283 std->dnext = sdone; 1284 done = O32TOH(std->td.td_nexttd); 1285 sdone = std; 1286 DPRINTFN(10, "add TD %p", std, 0, 0, 0); 1287 continue; 1288 } 1289 sitd = ohci_hash_find_itd(sc, done); 1290 if (sitd != NULL) { 1291 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1292 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1293 sitd->dnext = sidone; 1294 done = O32TOH(sitd->itd.itd_nextitd); 1295 sidone = sitd; 1296 DPRINTFN(5, "add ITD %p", sitd, 0, 0, 0); 1297 continue; 1298 } 1299 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1300 (u_long)done); 1301 break; 1302 } 1303 1304 DPRINTFN(10, "sdone=%p sidone=%p", sdone, sidone, 0, 0); 1305 DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0); 1306 #ifdef OHCI_DEBUG 1307 if (ohcidebug > 10) { 1308 for (std = sdone; std; std = std->dnext) 1309 ohci_dump_td(sc, std); 1310 } 1311 #endif 1312 DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0); 1313 1314 for (std = sdone; std; std = stdnext) { 1315 xfer = std->xfer; 1316 stdnext = std->dnext; 1317 DPRINTFN(10, "std=%p xfer=%p hcpriv=%p", std, xfer, 1318 xfer ? xfer->ux_hcpriv : 0, 0); 1319 if (xfer == NULL) { 1320 /* 1321 * xfer == NULL: There seems to be no xfer associated 1322 * with this TD. It is tailp that happened to end up on 1323 * the done queue. 1324 * Shouldn't happen, but some chips are broken(?). 1325 */ 1326 continue; 1327 } 1328 if (xfer->ux_status == USBD_CANCELLED || 1329 xfer->ux_status == USBD_TIMEOUT) { 1330 DPRINTF("cancel/timeout %p", xfer, 0, 0, 0); 1331 /* Handled by abort routine. */ 1332 continue; 1333 } 1334 callout_stop(&xfer->ux_callout); 1335 1336 len = std->len; 1337 if (std->td.td_cbp != 0) 1338 len -= O32TOH(std->td.td_be) - 1339 O32TOH(std->td.td_cbp) + 1; 1340 DPRINTFN(10, "len=%d, flags=0x%x", len, std->flags, 0, 0); 1341 if (std->flags & OHCI_ADD_LEN) 1342 xfer->ux_actlen += len; 1343 1344 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1345 if (cc == OHCI_CC_NO_ERROR) { 1346 if (std->flags & OHCI_CALL_DONE) { 1347 xfer->ux_status = USBD_NORMAL_COMPLETION; 1348 usb_transfer_complete(xfer); 1349 } 1350 ohci_free_std(sc, std); 1351 } else { 1352 /* 1353 * Endpoint is halted. First unlink all the TDs 1354 * belonging to the failed transfer, and then restart 1355 * the endpoint. 1356 */ 1357 ohci_soft_td_t *p, *n; 1358 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1359 1360 DPRINTFN(15, "error cc=%d", 1361 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 0, 0, 0); 1362 1363 /* remove TDs */ 1364 for (p = std; p->xfer == xfer; p = n) { 1365 n = p->nexttd; 1366 ohci_free_std(sc, p); 1367 } 1368 1369 /* clear halt */ 1370 opipe->sed->ed.ed_headp = HTOO32(p->physaddr); 1371 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1372 1373 if (cc == OHCI_CC_STALL) 1374 xfer->ux_status = USBD_STALLED; 1375 else 1376 xfer->ux_status = USBD_IOERROR; 1377 usb_transfer_complete(xfer); 1378 } 1379 } 1380 DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0); 1381 #ifdef OHCI_DEBUG 1382 if (ohcidebug > 10) { 1383 DPRINTFN(10, "ITD done", 0, 0, 0, 0); 1384 for (sitd = sidone; sitd; sitd = sitd->dnext) 1385 ohci_dump_itd(sc, sitd); 1386 } 1387 #endif 1388 DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0); 1389 1390 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1391 xfer = sitd->xfer; 1392 sitdnext = sitd->dnext; 1393 DPRINTFN(1, "sitd=%p xfer=%p hcpriv=%p", sitd, xfer, 1394 xfer ? xfer->ux_hcpriv : 0, 0); 1395 if (xfer == NULL) 1396 continue; 1397 if (xfer->ux_status == USBD_CANCELLED || 1398 xfer->ux_status == USBD_TIMEOUT) { 1399 DPRINTF("cancel/timeout %p", xfer, 0, 0, 0); 1400 /* Handled by abort routine. */ 1401 continue; 1402 } 1403 KASSERT(!sitd->isdone); 1404 #ifdef DIAGNOSTIC 1405 sitd->isdone = true; 1406 #endif 1407 if (sitd->flags & OHCI_CALL_DONE) { 1408 ohci_soft_itd_t *next; 1409 1410 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1411 opipe->isoc.inuse -= xfer->ux_nframes; 1412 uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc-> 1413 bEndpointAddress); 1414 xfer->ux_status = USBD_NORMAL_COMPLETION; 1415 actlen = 0; 1416 for (i = 0, sitd = xfer->ux_hcpriv;; 1417 sitd = next) { 1418 next = sitd->nextitd; 1419 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1420 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1421 xfer->ux_status = USBD_IOERROR; 1422 /* For input, update frlengths with actual */ 1423 /* XXX anything necessary for output? */ 1424 if (uedir == UE_DIR_IN && 1425 xfer->ux_status == USBD_NORMAL_COMPLETION) { 1426 iframes = OHCI_ITD_GET_FC(O32TOH( 1427 sitd->itd.itd_flags)); 1428 for (j = 0; j < iframes; i++, j++) { 1429 len = O16TOH(sitd-> 1430 itd.itd_offset[j]); 1431 if ((OHCI_ITD_PSW_GET_CC(len) & 1432 OHCI_CC_NOT_ACCESSED_MASK) 1433 == OHCI_CC_NOT_ACCESSED) 1434 len = 0; 1435 else 1436 len = OHCI_ITD_PSW_LENGTH(len); 1437 xfer->ux_frlengths[i] = len; 1438 actlen += len; 1439 } 1440 } 1441 if (sitd->flags & OHCI_CALL_DONE) 1442 break; 1443 ohci_free_sitd(sc, sitd); 1444 } 1445 ohci_free_sitd(sc, sitd); 1446 if (uedir == UE_DIR_IN && 1447 xfer->ux_status == USBD_NORMAL_COMPLETION) 1448 xfer->ux_actlen = actlen; 1449 xfer->ux_hcpriv = NULL; 1450 1451 usb_transfer_complete(xfer); 1452 } 1453 } 1454 1455 if (sc->sc_softwake) { 1456 sc->sc_softwake = 0; 1457 cv_broadcast(&sc->sc_softwake_cv); 1458 } 1459 1460 DPRINTFN(10, "done", 0, 0, 0, 0); 1461 } 1462 1463 void 1464 ohci_device_ctrl_done(struct usbd_xfer *xfer) 1465 { 1466 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1467 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1468 int len = UGETW(xfer->ux_request.wLength); 1469 int isread = (xfer->ux_request.bmRequestType & UT_READ); 1470 1471 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1472 DPRINTFN(10, "xfer=%p", xfer, 0, 0, 0); 1473 1474 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1475 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 1476 1477 if (len) 1478 usb_syncmem(&xfer->ux_dmabuf, 0, len, 1479 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1480 usb_syncmem(&opipe->ctrl.reqdma, 0, 1481 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1482 } 1483 1484 void 1485 ohci_device_intr_done(struct usbd_xfer *xfer) 1486 { 1487 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1488 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1489 ohci_soft_ed_t *sed = opipe->sed; 1490 ohci_soft_td_t *data, *tail; 1491 int isread = 1492 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1493 1494 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1495 DPRINTFN(10, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0); 1496 1497 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1498 1499 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1500 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1501 if (xfer->ux_pipe->up_repeat) { 1502 data = opipe->tail.td; 1503 tail = ohci_alloc_std(sc); /* XXX should reuse TD */ 1504 if (tail == NULL) { 1505 xfer->ux_status = USBD_NOMEM; 1506 return; 1507 } 1508 tail->xfer = NULL; 1509 1510 data->td.td_flags = HTOO32( 1511 OHCI_TD_IN | OHCI_TD_NOCC | 1512 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 1513 if (xfer->ux_flags & USBD_SHORT_XFER_OK) 1514 data->td.td_flags |= HTOO32(OHCI_TD_R); 1515 data->td.td_cbp = HTOO32(DMAADDR(&xfer->ux_dmabuf, 0)); 1516 data->td.td_nexttd = HTOO32(tail->physaddr); 1517 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + 1518 xfer->ux_length - 1); 1519 data->nexttd = tail; 1520 data->len = xfer->ux_length; 1521 data->xfer = xfer; 1522 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 1523 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 1524 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1525 xfer->ux_hcpriv = data; 1526 xfer->ux_actlen = 0; 1527 1528 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1529 usb_syncmem(&sed->dma, 1530 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1531 sizeof(sed->ed.ed_tailp), 1532 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1533 opipe->tail.td = tail; 1534 } 1535 } 1536 1537 void 1538 ohci_device_bulk_done(struct usbd_xfer *xfer) 1539 { 1540 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1541 1542 int isread = 1543 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1544 1545 KASSERT(mutex_owned(&sc->sc_lock)); 1546 1547 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1548 DPRINTFN(10, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0); 1549 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1550 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1551 } 1552 1553 Static void 1554 ohci_rhsc_softint(void *arg) 1555 { 1556 ohci_softc_t *sc = arg; 1557 1558 mutex_enter(&sc->sc_lock); 1559 1560 ohci_rhsc(sc, sc->sc_intrxfer); 1561 1562 /* Do not allow RHSC interrupts > 1 per second */ 1563 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1564 1565 mutex_exit(&sc->sc_lock); 1566 } 1567 1568 void 1569 ohci_rhsc(ohci_softc_t *sc, struct usbd_xfer *xfer) 1570 { 1571 u_char *p; 1572 int i, m; 1573 int hstatus __unused; 1574 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1575 1576 KASSERT(mutex_owned(&sc->sc_lock)); 1577 1578 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1579 DPRINTF("sc=%p xfer=%p hstatus=0x%08x", sc, xfer, hstatus, 0); 1580 1581 if (xfer == NULL) { 1582 /* Just ignore the change. */ 1583 return; 1584 } 1585 1586 p = xfer->ux_buf; 1587 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 1588 memset(p, 0, xfer->ux_length); 1589 for (i = 1; i <= m; i++) { 1590 /* Pick out CHANGE bits from the status reg. */ 1591 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1592 p[i/8] |= 1 << (i%8); 1593 } 1594 DPRINTF("change=0x%02x", *p, 0, 0, 0); 1595 xfer->ux_actlen = xfer->ux_length; 1596 xfer->ux_status = USBD_NORMAL_COMPLETION; 1597 1598 usb_transfer_complete(xfer); 1599 } 1600 1601 void 1602 ohci_root_intr_done(struct usbd_xfer *xfer) 1603 { 1604 } 1605 1606 /* 1607 * Wait here until controller claims to have an interrupt. 1608 * Then call ohci_intr and return. Use timeout to avoid waiting 1609 * too long. 1610 */ 1611 void 1612 ohci_waitintr(ohci_softc_t *sc, struct usbd_xfer *xfer) 1613 { 1614 int timo; 1615 uint32_t intrs; 1616 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1617 1618 mutex_enter(&sc->sc_lock); 1619 1620 xfer->ux_status = USBD_IN_PROGRESS; 1621 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1622 usb_delay_ms(&sc->sc_bus, 1); 1623 if (sc->sc_dying) 1624 break; 1625 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 1626 DPRINTFN(15, "intrs 0x%04x", intrs, 0, 0, 0); 1627 #ifdef OHCI_DEBUG 1628 if (ohcidebug > 15) 1629 ohci_dumpregs(sc); 1630 #endif 1631 if (intrs) { 1632 mutex_spin_enter(&sc->sc_intr_lock); 1633 ohci_intr1(sc); 1634 mutex_spin_exit(&sc->sc_intr_lock); 1635 if (xfer->ux_status != USBD_IN_PROGRESS) 1636 goto done; 1637 } 1638 } 1639 1640 /* Timeout */ 1641 DPRINTF("timeout", 0, 0, 0, 0); 1642 xfer->ux_status = USBD_TIMEOUT; 1643 usb_transfer_complete(xfer); 1644 1645 /* XXX should free TD */ 1646 1647 done: 1648 mutex_exit(&sc->sc_lock); 1649 } 1650 1651 void 1652 ohci_poll(struct usbd_bus *bus) 1653 { 1654 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1655 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1656 1657 #ifdef OHCI_DEBUG 1658 static int last; 1659 int new; 1660 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1661 if (new != last) { 1662 DPRINTFN(10, "intrs=0x%04x", new, 0, 0, 0); 1663 last = new; 1664 } 1665 #endif 1666 sc->sc_eintrs |= OHCI_WDH; 1667 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1668 mutex_spin_enter(&sc->sc_intr_lock); 1669 ohci_intr1(sc); 1670 mutex_spin_exit(&sc->sc_intr_lock); 1671 } 1672 } 1673 1674 /* 1675 * Add an ED to the schedule. Called with USB lock held. 1676 */ 1677 Static void 1678 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1679 { 1680 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1681 DPRINTFN(8, "sed=%p head=%p", sed, head, 0, 0); 1682 1683 KASSERT(mutex_owned(&sc->sc_lock)); 1684 1685 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1686 sizeof(head->ed.ed_nexted), 1687 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1688 sed->next = head->next; 1689 sed->ed.ed_nexted = head->ed.ed_nexted; 1690 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1691 sizeof(sed->ed.ed_nexted), 1692 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1693 head->next = sed; 1694 head->ed.ed_nexted = HTOO32(sed->physaddr); 1695 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1696 sizeof(head->ed.ed_nexted), 1697 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1698 } 1699 1700 /* 1701 * Remove an ED from the schedule. Called with USB lock held. 1702 */ 1703 Static void 1704 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1705 { 1706 ohci_soft_ed_t *p; 1707 1708 KASSERT(mutex_owned(&sc->sc_lock)); 1709 1710 /* XXX */ 1711 for (p = head; p != NULL && p->next != sed; p = p->next) 1712 ; 1713 KASSERT(p != NULL); 1714 1715 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1716 sizeof(sed->ed.ed_nexted), 1717 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1718 p->next = sed->next; 1719 p->ed.ed_nexted = sed->ed.ed_nexted; 1720 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1721 sizeof(p->ed.ed_nexted), 1722 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1723 } 1724 1725 /* 1726 * When a transfer is completed the TD is added to the done queue by 1727 * the host controller. This queue is the processed by software. 1728 * Unfortunately the queue contains the physical address of the TD 1729 * and we have no simple way to translate this back to a kernel address. 1730 * To make the translation possible (and fast) we use a hash table of 1731 * TDs currently in the schedule. The physical address is used as the 1732 * hash value. 1733 */ 1734 1735 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1736 /* Called with USB lock held. */ 1737 void 1738 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1739 { 1740 int h = HASH(std->physaddr); 1741 1742 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1743 1744 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1745 } 1746 1747 /* Called with USB lock held. */ 1748 void 1749 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1750 { 1751 1752 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1753 1754 LIST_REMOVE(std, hnext); 1755 } 1756 1757 ohci_soft_td_t * 1758 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1759 { 1760 int h = HASH(a); 1761 ohci_soft_td_t *std; 1762 1763 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1764 std != NULL; 1765 std = LIST_NEXT(std, hnext)) 1766 if (std->physaddr == a) 1767 return std; 1768 return NULL; 1769 } 1770 1771 /* Called with USB lock held. */ 1772 void 1773 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1774 { 1775 int h = HASH(sitd->physaddr); 1776 1777 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1778 1779 KASSERT(mutex_owned(&sc->sc_lock)); 1780 1781 DPRINTFN(10, "sitd=%p physaddr=0x%08lx", sitd, (u_long)sitd->physaddr, 1782 0, 0); 1783 1784 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1785 } 1786 1787 /* Called with USB lock held. */ 1788 void 1789 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1790 { 1791 1792 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1793 1794 KASSERT(mutex_owned(&sc->sc_lock)); 1795 1796 DPRINTFN(10, "sitd=%p physaddr=0x%08lx", sitd, (u_long)sitd->physaddr, 1797 0, 0); 1798 1799 LIST_REMOVE(sitd, hnext); 1800 } 1801 1802 ohci_soft_itd_t * 1803 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1804 { 1805 int h = HASH(a); 1806 ohci_soft_itd_t *sitd; 1807 1808 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1809 sitd != NULL; 1810 sitd = LIST_NEXT(sitd, hnext)) 1811 if (sitd->physaddr == a) 1812 return sitd; 1813 return NULL; 1814 } 1815 1816 void 1817 ohci_timeout(void *addr) 1818 { 1819 struct usbd_xfer *xfer = addr; 1820 struct ohci_xfer *oxfer = OHCI_XFER2OXFER(xfer); 1821 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1822 1823 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1824 DPRINTF("oxfer=%p", oxfer, 0, 0, 0); 1825 1826 if (sc->sc_dying) { 1827 mutex_enter(&sc->sc_lock); 1828 ohci_abort_xfer(xfer, USBD_TIMEOUT); 1829 mutex_exit(&sc->sc_lock); 1830 return; 1831 } 1832 1833 /* Execute the abort in a process context. */ 1834 usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr, 1835 USB_TASKQ_MPSAFE); 1836 usb_add_task(xfer->ux_pipe->up_dev, &oxfer->abort_task, 1837 USB_TASKQ_HC); 1838 } 1839 1840 void 1841 ohci_timeout_task(void *addr) 1842 { 1843 struct usbd_xfer *xfer = addr; 1844 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1845 1846 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1847 1848 DPRINTF("xfer=%p", xfer, 0, 0, 0); 1849 1850 mutex_enter(&sc->sc_lock); 1851 ohci_abort_xfer(xfer, USBD_TIMEOUT); 1852 mutex_exit(&sc->sc_lock); 1853 } 1854 1855 #ifdef OHCI_DEBUG 1856 void 1857 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 1858 { 1859 for (; std; std = std->nexttd) { 1860 ohci_dump_td(sc, std); 1861 KASSERTMSG(std->nexttd == NULL || std != std->nexttd, 1862 "std %p next %p", std, std->nexttd); 1863 } 1864 } 1865 1866 void 1867 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1868 { 1869 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1870 1871 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1872 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1873 1874 uint32_t flags = O32TOH(std->td.td_flags); 1875 DPRINTF("TD(%p) at %08lx:", std, (u_long)std->physaddr, 0, 0); 1876 DPRINTF(" round=%d DP=%x DI=%x T=%x", 1877 !!(flags & OHCI_TD_R), 1878 __SHIFTOUT(flags, OHCI_TD_DP_MASK), 1879 OHCI_TD_GET_DI(flags), 1880 __SHIFTOUT(flags, OHCI_TD_TOGGLE_MASK)); 1881 DPRINTF(" EC=%d CC=%d", OHCI_TD_GET_EC(flags), OHCI_TD_GET_CC(flags), 1882 0, 0); 1883 DPRINTF(" cbp=0x%08lx nexttd=0x%08lx be=0x%08lx", 1884 (u_long)O32TOH(std->td.td_cbp), 1885 (u_long)O32TOH(std->td.td_nexttd), 1886 (u_long)O32TOH(std->td.td_be), 0); 1887 } 1888 1889 void 1890 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1891 { 1892 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1893 1894 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1895 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1896 1897 uint32_t flags = O32TOH(sitd->itd.itd_flags); 1898 DPRINTF("ITD(%p) at %08lx", sitd, (u_long)sitd->physaddr, 0, 0); 1899 DPRINTF(" sf=%d di=%d fc=%d cc=%d", 1900 OHCI_ITD_GET_SF(flags), OHCI_ITD_GET_DI(flags), 1901 OHCI_ITD_GET_FC(flags), OHCI_ITD_GET_CC(flags)); 1902 DPRINTF(" bp0=0x%08x next=0x%08x be=0x%08x", 1903 O32TOH(sitd->itd.itd_bp0), 1904 O32TOH(sitd->itd.itd_nextitd), 1905 O32TOH(sitd->itd.itd_be), 0); 1906 CTASSERT(OHCI_ITD_NOFFSET == 8); 1907 DPRINTF(" offs[0] = 0x%04x offs[1] = 0x%04x " 1908 "offs[2] = 0x%04x offs[3] = 0x%04x", 1909 O16TOH(sitd->itd.itd_offset[0]), 1910 O16TOH(sitd->itd.itd_offset[1]), 1911 O16TOH(sitd->itd.itd_offset[2]), 1912 O16TOH(sitd->itd.itd_offset[3])); 1913 DPRINTF(" offs[4] = 0x%04x offs[5] = 0x%04x " 1914 "offs[6] = 0x%04x offs[7] = 0x%04x", 1915 O16TOH(sitd->itd.itd_offset[4]), 1916 O16TOH(sitd->itd.itd_offset[5]), 1917 O16TOH(sitd->itd.itd_offset[6]), 1918 O16TOH(sitd->itd.itd_offset[7])); 1919 } 1920 1921 void 1922 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1923 { 1924 for (; sitd; sitd = sitd->nextitd) 1925 ohci_dump_itd(sc, sitd); 1926 } 1927 1928 void 1929 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 1930 { 1931 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1932 1933 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 1934 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1935 1936 uint32_t flags = O32TOH(sed->ed.ed_flags); 1937 DPRINTF("ED(%p) at 0x%08lx:", sed, sed->physaddr, 0, 0); 1938 DPRINTF(" addr=%d endpt=%d maxp=%d", 1939 OHCI_ED_GET_FA(flags), 1940 OHCI_ED_GET_EN(flags), 1941 OHCI_ED_GET_MAXP(flags), 1942 0); 1943 DPRINTF(" dir=%d speed=%d skip=%d iso=%d", 1944 __SHIFTOUT(flags, OHCI_ED_DIR_MASK), 1945 !!(flags & OHCI_ED_SPEED), 1946 !!(flags & OHCI_ED_SKIP), 1947 !!(flags & OHCI_ED_FORMAT_ISO)); 1948 DPRINTF(" tailp=0x%08lx", (u_long)O32TOH(sed->ed.ed_tailp), 1949 0, 0, 0); 1950 DPRINTF(" headp=0x%08lx nexted=0x%08lx halted=%d carry=%d", 1951 O32TOH(sed->ed.ed_headp), O32TOH(sed->ed.ed_nexted), 1952 !!(O32TOH(sed->ed.ed_headp) & OHCI_HALTED), 1953 !!(O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 1954 } 1955 #endif 1956 1957 usbd_status 1958 ohci_open(struct usbd_pipe *pipe) 1959 { 1960 struct usbd_device *dev = pipe->up_dev; 1961 struct usbd_bus *bus = dev->ud_bus; 1962 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 1963 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1964 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 1965 uint8_t addr = dev->ud_addr; 1966 uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1967 ohci_soft_ed_t *sed; 1968 ohci_soft_td_t *std; 1969 ohci_soft_itd_t *sitd; 1970 ohci_physaddr_t tdphys; 1971 uint32_t fmt; 1972 usbd_status err = USBD_NOMEM; 1973 int ival; 1974 1975 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1976 DPRINTFN(1, "pipe=%p, addr=%d, endpt=%d (%d)", pipe, addr, 1977 ed->bEndpointAddress, bus->ub_rhaddr); 1978 1979 if (sc->sc_dying) { 1980 return USBD_IOERROR; 1981 } 1982 1983 std = NULL; 1984 sed = NULL; 1985 1986 if (addr == bus->ub_rhaddr) { 1987 switch (ed->bEndpointAddress) { 1988 case USB_CONTROL_ENDPOINT: 1989 pipe->up_methods = &roothub_ctrl_methods; 1990 break; 1991 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1992 pipe->up_methods = &ohci_root_intr_methods; 1993 break; 1994 default: 1995 err = USBD_INVAL; 1996 goto bad; 1997 } 1998 } else { 1999 sed = ohci_alloc_sed(sc); 2000 if (sed == NULL) 2001 goto bad; 2002 opipe->sed = sed; 2003 if (xfertype == UE_ISOCHRONOUS) { 2004 mutex_enter(&sc->sc_lock); 2005 sitd = ohci_alloc_sitd(sc); 2006 mutex_exit(&sc->sc_lock); 2007 if (sitd == NULL) 2008 goto bad; 2009 2010 opipe->tail.itd = sitd; 2011 tdphys = sitd->physaddr; 2012 fmt = OHCI_ED_FORMAT_ISO; 2013 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2014 fmt |= OHCI_ED_DIR_IN; 2015 else 2016 fmt |= OHCI_ED_DIR_OUT; 2017 } else { 2018 mutex_enter(&sc->sc_lock); 2019 std = ohci_alloc_std(sc); 2020 mutex_exit(&sc->sc_lock); 2021 if (std == NULL) 2022 goto bad; 2023 2024 opipe->tail.td = std; 2025 tdphys = std->physaddr; 2026 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2027 } 2028 sed->ed.ed_flags = HTOO32( 2029 OHCI_ED_SET_FA(addr) | 2030 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2031 (dev->ud_speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2032 fmt | 2033 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2034 sed->ed.ed_headp = HTOO32(tdphys | 2035 (pipe->up_endpoint->ue_toggle ? OHCI_TOGGLECARRY : 0)); 2036 sed->ed.ed_tailp = HTOO32(tdphys); 2037 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2038 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2039 2040 switch (xfertype) { 2041 case UE_CONTROL: 2042 pipe->up_methods = &ohci_device_ctrl_methods; 2043 err = usb_allocmem(&sc->sc_bus, 2044 sizeof(usb_device_request_t), 2045 0, &opipe->ctrl.reqdma); 2046 if (err) 2047 goto bad; 2048 mutex_enter(&sc->sc_lock); 2049 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2050 mutex_exit(&sc->sc_lock); 2051 break; 2052 case UE_INTERRUPT: 2053 pipe->up_methods = &ohci_device_intr_methods; 2054 ival = pipe->up_interval; 2055 if (ival == USBD_DEFAULT_INTERVAL) 2056 ival = ed->bInterval; 2057 err = ohci_device_setintr(sc, opipe, ival); 2058 if (err) 2059 goto bad; 2060 break; 2061 case UE_ISOCHRONOUS: 2062 pipe->up_methods = &ohci_device_isoc_methods; 2063 return ohci_setup_isoc(pipe); 2064 case UE_BULK: 2065 pipe->up_methods = &ohci_device_bulk_methods; 2066 mutex_enter(&sc->sc_lock); 2067 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2068 mutex_exit(&sc->sc_lock); 2069 break; 2070 } 2071 } 2072 2073 return USBD_NORMAL_COMPLETION; 2074 2075 bad: 2076 if (std != NULL) { 2077 mutex_enter(&sc->sc_lock); 2078 ohci_free_std(sc, std); 2079 mutex_exit(&sc->sc_lock); 2080 } 2081 if (sed != NULL) 2082 ohci_free_sed(sc, sed); 2083 return err; 2084 2085 } 2086 2087 /* 2088 * Close a reqular pipe. 2089 * Assumes that there are no pending transactions. 2090 */ 2091 void 2092 ohci_close_pipe(struct usbd_pipe *pipe, ohci_soft_ed_t *head) 2093 { 2094 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2095 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2096 ohci_soft_ed_t *sed = opipe->sed; 2097 2098 KASSERT(mutex_owned(&sc->sc_lock)); 2099 2100 #ifdef DIAGNOSTIC 2101 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2102 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2103 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2104 ohci_soft_td_t *std; 2105 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2106 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2107 "tl=0x%x pipe=%p, std=%p\n", sed, 2108 (int)O32TOH(sed->ed.ed_headp), 2109 (int)O32TOH(sed->ed.ed_tailp), 2110 pipe, std); 2111 #ifdef OHCI_DEBUG 2112 usbd_dump_pipe(&opipe->pipe); 2113 ohci_dump_ed(sc, sed); 2114 if (std) 2115 ohci_dump_td(sc, std); 2116 #endif 2117 usb_delay_ms(&sc->sc_bus, 2); 2118 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2119 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2120 printf("ohci_close_pipe: pipe still not empty\n"); 2121 } 2122 #endif 2123 ohci_rem_ed(sc, sed, head); 2124 /* Make sure the host controller is not touching this ED */ 2125 usb_delay_ms(&sc->sc_bus, 1); 2126 pipe->up_endpoint->ue_toggle = 2127 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2128 ohci_free_sed(sc, opipe->sed); 2129 } 2130 2131 /* 2132 * Abort a device request. 2133 * If this routine is called at splusb() it guarantees that the request 2134 * will be removed from the hardware scheduling and that the callback 2135 * for it will be called with USBD_CANCELLED status. 2136 * It's impossible to guarantee that the requested transfer will not 2137 * have happened since the hardware runs concurrently. 2138 * If the transaction has already happened we rely on the ordinary 2139 * interrupt processing to process it. 2140 * XXX This is most probably wrong. 2141 * XXXMRG this doesn't make sense anymore. 2142 */ 2143 void 2144 ohci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2145 { 2146 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2147 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2148 ohci_soft_ed_t *sed = opipe->sed; 2149 ohci_soft_td_t *p, *n; 2150 ohci_physaddr_t headp; 2151 int hit; 2152 int wake; 2153 2154 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2155 DPRINTF("xfer=%p pipe=%p sed=%p", xfer, opipe,sed, 0); 2156 2157 KASSERT(mutex_owned(&sc->sc_lock)); 2158 ASSERT_SLEEPABLE(); 2159 2160 if (sc->sc_dying) { 2161 /* If we're dying, just do the software part. */ 2162 xfer->ux_status = status; /* make software ignore it */ 2163 callout_halt(&xfer->ux_callout, &sc->sc_lock); 2164 usb_transfer_complete(xfer); 2165 return; 2166 } 2167 2168 /* 2169 * If an abort is already in progress then just wait for it to 2170 * complete and return. 2171 */ 2172 if (xfer->ux_hcflags & UXFER_ABORTING) { 2173 DPRINTFN(2, "already aborting", 0, 0, 0, 0); 2174 #ifdef DIAGNOSTIC 2175 if (status == USBD_TIMEOUT) 2176 printf("%s: TIMEOUT while aborting\n", __func__); 2177 #endif 2178 /* Override the status which might be USBD_TIMEOUT. */ 2179 xfer->ux_status = status; 2180 DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0); 2181 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2182 while (xfer->ux_hcflags & UXFER_ABORTING) 2183 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2184 goto done; 2185 } 2186 xfer->ux_hcflags |= UXFER_ABORTING; 2187 2188 /* 2189 * Step 1: Make interrupt routine and hardware ignore xfer. 2190 */ 2191 xfer->ux_status = status; /* make software ignore it */ 2192 callout_stop(&xfer->ux_callout); 2193 DPRINTFN(1, "stop ed=%p", sed, 0, 0, 0); 2194 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2195 sizeof(sed->ed.ed_flags), 2196 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2197 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2198 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2199 sizeof(sed->ed.ed_flags), 2200 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2201 2202 /* 2203 * Step 2: Wait until we know hardware has finished any possible 2204 * use of the xfer. Also make sure the soft interrupt routine 2205 * has run. 2206 */ 2207 /* Hardware finishes in 1ms */ 2208 usb_delay_ms_locked(opipe->pipe.up_dev->ud_bus, 20, &sc->sc_lock); 2209 sc->sc_softwake = 1; 2210 usb_schedsoftintr(&sc->sc_bus); 2211 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2212 2213 /* 2214 * Step 3: Remove any vestiges of the xfer from the hardware. 2215 * The complication here is that the hardware may have executed 2216 * beyond the xfer we're trying to abort. So as we're scanning 2217 * the TDs of this xfer we check if the hardware points to 2218 * any of them. 2219 */ 2220 p = xfer->ux_hcpriv; 2221 KASSERT(p); 2222 2223 #ifdef OHCI_DEBUG 2224 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2225 2226 if (ohcidebug > 1) { 2227 DPRINTF("sed:", 0, 0, 0, 0); 2228 ohci_dump_ed(sc, sed); 2229 ohci_dump_tds(sc, p); 2230 } 2231 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2232 #endif 2233 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2234 hit = 0; 2235 for (; p->xfer == xfer; p = n) { 2236 hit |= headp == p->physaddr; 2237 n = p->nexttd; 2238 ohci_free_std(sc, p); 2239 } 2240 /* Zap headp register if hardware pointed inside the xfer. */ 2241 if (hit) { 2242 DPRINTFN(1, "set hd=0x%08x, tl=0x%08x", (int)p->physaddr, 2243 (int)O32TOH(sed->ed.ed_tailp), 0, 0); 2244 sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */ 2245 usb_syncmem(&sed->dma, 2246 sed->offs + offsetof(ohci_ed_t, ed_headp), 2247 sizeof(sed->ed.ed_headp), 2248 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2249 } else { 2250 DPRINTFN(1, "no hit", 0, 0, 0, 0); 2251 } 2252 2253 /* 2254 * Step 4: Turn on hardware again. 2255 */ 2256 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2257 sizeof(sed->ed.ed_flags), 2258 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2259 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2260 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2261 sizeof(sed->ed.ed_flags), 2262 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2263 2264 /* 2265 * Step 5: Execute callback. 2266 */ 2267 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2268 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2269 usb_transfer_complete(xfer); 2270 if (wake) 2271 cv_broadcast(&xfer->ux_hccv); 2272 2273 done: 2274 KASSERT(mutex_owned(&sc->sc_lock)); 2275 } 2276 2277 /* 2278 * Data structures and routines to emulate the root hub. 2279 */ 2280 Static int 2281 ohci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2282 void *buf, int buflen) 2283 { 2284 ohci_softc_t *sc = OHCI_BUS2SC(bus); 2285 usb_port_status_t ps; 2286 uint16_t len, value, index; 2287 int l, totlen = 0; 2288 int port, i; 2289 uint32_t v; 2290 2291 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2292 2293 if (sc->sc_dying) 2294 return -1; 2295 2296 DPRINTFN(4, "type=0x%02x request=%02x", req->bmRequestType, 2297 req->bRequest, 0, 0); 2298 2299 len = UGETW(req->wLength); 2300 value = UGETW(req->wValue); 2301 index = UGETW(req->wIndex); 2302 2303 #define C(x,y) ((x) | ((y) << 8)) 2304 switch (C(req->bRequest, req->bmRequestType)) { 2305 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2306 DPRINTFN(8, "wValue=0x%04x", value, 0, 0, 0); 2307 if (len == 0) 2308 break; 2309 switch (value) { 2310 case C(0, UDESC_DEVICE): { 2311 usb_device_descriptor_t devd; 2312 2313 totlen = min(buflen, sizeof(devd)); 2314 memcpy(&devd, buf, totlen); 2315 USETW(devd.idVendor, sc->sc_id_vendor); 2316 memcpy(buf, &devd, totlen); 2317 break; 2318 } 2319 case C(1, UDESC_STRING): 2320 #define sd ((usb_string_descriptor_t *)buf) 2321 /* Vendor */ 2322 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2323 break; 2324 case C(2, UDESC_STRING): 2325 /* Product */ 2326 totlen = usb_makestrdesc(sd, len, "OHCI root hub"); 2327 break; 2328 #undef sd 2329 default: 2330 /* default from usbroothub */ 2331 return buflen; 2332 } 2333 break; 2334 2335 /* Hub requests */ 2336 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2337 break; 2338 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2339 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 2340 index, value, 0, 0); 2341 if (index < 1 || index > sc->sc_noport) { 2342 return -1; 2343 } 2344 port = OHCI_RH_PORT_STATUS(index); 2345 switch(value) { 2346 case UHF_PORT_ENABLE: 2347 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2348 break; 2349 case UHF_PORT_SUSPEND: 2350 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2351 break; 2352 case UHF_PORT_POWER: 2353 /* Yes, writing to the LOW_SPEED bit clears power. */ 2354 OWRITE4(sc, port, UPS_LOW_SPEED); 2355 break; 2356 case UHF_C_PORT_CONNECTION: 2357 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2358 break; 2359 case UHF_C_PORT_ENABLE: 2360 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2361 break; 2362 case UHF_C_PORT_SUSPEND: 2363 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2364 break; 2365 case UHF_C_PORT_OVER_CURRENT: 2366 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2367 break; 2368 case UHF_C_PORT_RESET: 2369 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2370 break; 2371 default: 2372 return -1; 2373 } 2374 switch(value) { 2375 case UHF_C_PORT_CONNECTION: 2376 case UHF_C_PORT_ENABLE: 2377 case UHF_C_PORT_SUSPEND: 2378 case UHF_C_PORT_OVER_CURRENT: 2379 case UHF_C_PORT_RESET: 2380 /* Enable RHSC interrupt if condition is cleared. */ 2381 if ((OREAD4(sc, port) >> 16) == 0) 2382 ohci_rhsc_enable(sc); 2383 break; 2384 default: 2385 break; 2386 } 2387 break; 2388 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2389 if (len == 0) 2390 break; 2391 if ((value & 0xff) != 0) { 2392 return -1; 2393 } 2394 usb_hub_descriptor_t hubd; 2395 2396 totlen = min(buflen, sizeof(hubd)); 2397 memcpy(&hubd, buf, totlen); 2398 2399 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2400 hubd.bNbrPorts = sc->sc_noport; 2401 USETW(hubd.wHubCharacteristics, 2402 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2403 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2404 /* XXX overcurrent */ 2405 ); 2406 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2407 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2408 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2409 hubd.DeviceRemovable[i++] = (uint8_t)v; 2410 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2411 totlen = min(totlen, hubd.bDescLength); 2412 memcpy(buf, &hubd, totlen); 2413 break; 2414 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2415 if (len != 4) { 2416 return -1; 2417 } 2418 memset(buf, 0, len); /* ? XXX */ 2419 totlen = len; 2420 break; 2421 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2422 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 2423 if (index < 1 || index > sc->sc_noport) { 2424 return -1; 2425 } 2426 if (len != 4) { 2427 return -1; 2428 } 2429 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2430 DPRINTFN(8, "port status=0x%04x", v, 0, 0, 0); 2431 USETW(ps.wPortStatus, v); 2432 USETW(ps.wPortChange, v >> 16); 2433 totlen = min(len, sizeof(ps)); 2434 memcpy(buf, &ps, totlen); 2435 break; 2436 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2437 return -1; 2438 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2439 break; 2440 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2441 if (index < 1 || index > sc->sc_noport) { 2442 return -1; 2443 } 2444 port = OHCI_RH_PORT_STATUS(index); 2445 switch(value) { 2446 case UHF_PORT_ENABLE: 2447 OWRITE4(sc, port, UPS_PORT_ENABLED); 2448 break; 2449 case UHF_PORT_SUSPEND: 2450 OWRITE4(sc, port, UPS_SUSPEND); 2451 break; 2452 case UHF_PORT_RESET: 2453 DPRINTFN(5, "reset port %d", index, 0, 0, 0); 2454 OWRITE4(sc, port, UPS_RESET); 2455 for (i = 0; i < 5; i++) { 2456 usb_delay_ms(&sc->sc_bus, 2457 USB_PORT_ROOT_RESET_DELAY); 2458 if (sc->sc_dying) { 2459 return -1; 2460 } 2461 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2462 break; 2463 } 2464 DPRINTFN(8, "port %d reset, status = 0x%04x", index, 2465 OREAD4(sc, port), 0, 0); 2466 break; 2467 case UHF_PORT_POWER: 2468 DPRINTFN(2, "set port power %d", index, 0, 0, 0); 2469 OWRITE4(sc, port, UPS_PORT_POWER); 2470 break; 2471 default: 2472 return -1; 2473 } 2474 break; 2475 default: 2476 /* default from usbroothub */ 2477 return buflen; 2478 } 2479 2480 return totlen; 2481 } 2482 2483 Static usbd_status 2484 ohci_root_intr_transfer(struct usbd_xfer *xfer) 2485 { 2486 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2487 usbd_status err; 2488 2489 /* Insert last in queue. */ 2490 mutex_enter(&sc->sc_lock); 2491 err = usb_insert_transfer(xfer); 2492 mutex_exit(&sc->sc_lock); 2493 if (err) 2494 return err; 2495 2496 /* Pipe isn't running, start first */ 2497 return ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2498 } 2499 2500 Static usbd_status 2501 ohci_root_intr_start(struct usbd_xfer *xfer) 2502 { 2503 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2504 2505 if (sc->sc_dying) 2506 return USBD_IOERROR; 2507 2508 mutex_enter(&sc->sc_lock); 2509 KASSERT(sc->sc_intrxfer == NULL); 2510 sc->sc_intrxfer = xfer; 2511 mutex_exit(&sc->sc_lock); 2512 2513 return USBD_IN_PROGRESS; 2514 } 2515 2516 /* Abort a root interrupt request. */ 2517 Static void 2518 ohci_root_intr_abort(struct usbd_xfer *xfer) 2519 { 2520 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2521 2522 KASSERT(mutex_owned(&sc->sc_lock)); 2523 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2524 2525 sc->sc_intrxfer = NULL; 2526 2527 xfer->ux_status = USBD_CANCELLED; 2528 usb_transfer_complete(xfer); 2529 } 2530 2531 /* Close the root pipe. */ 2532 Static void 2533 ohci_root_intr_close(struct usbd_pipe *pipe) 2534 { 2535 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2536 2537 KASSERT(mutex_owned(&sc->sc_lock)); 2538 2539 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2540 2541 sc->sc_intrxfer = NULL; 2542 } 2543 2544 /************************/ 2545 2546 Static usbd_status 2547 ohci_device_ctrl_transfer(struct usbd_xfer *xfer) 2548 { 2549 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2550 usbd_status err; 2551 2552 /* Insert last in queue. */ 2553 mutex_enter(&sc->sc_lock); 2554 err = usb_insert_transfer(xfer); 2555 mutex_exit(&sc->sc_lock); 2556 if (err) 2557 return err; 2558 2559 /* Pipe isn't running, start first */ 2560 return ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2561 } 2562 2563 Static usbd_status 2564 ohci_device_ctrl_start(struct usbd_xfer *xfer) 2565 { 2566 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2567 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2568 usb_device_request_t *req = &xfer->ux_request; 2569 struct usbd_device *dev __diagused = opipe->pipe.up_dev; 2570 ohci_soft_td_t *setup, *stat, *next, *tail; 2571 ohci_soft_ed_t *sed; 2572 int isread; 2573 int len; 2574 usbd_status err; 2575 2576 2577 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2578 2579 if (sc->sc_dying) 2580 return USBD_IOERROR; 2581 2582 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2583 2584 mutex_enter(&sc->sc_lock); 2585 2586 isread = req->bmRequestType & UT_READ; 2587 len = UGETW(req->wLength); 2588 2589 DPRINTF("type=0x%02x, request=0x%02x, " 2590 "wValue=0x%04x, wIndex=0x%04x", 2591 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2592 UGETW(req->wIndex)); 2593 DPRINTF("len=%d, addr=%d, endpt=%d", 2594 len, dev->ud_addr, 2595 opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 2596 2597 setup = opipe->tail.td; 2598 stat = ohci_alloc_std(sc); 2599 if (stat == NULL) { 2600 err = USBD_NOMEM; 2601 goto bad1; 2602 } 2603 tail = ohci_alloc_std(sc); 2604 if (tail == NULL) { 2605 err = USBD_NOMEM; 2606 goto bad2; 2607 } 2608 tail->xfer = NULL; 2609 2610 sed = opipe->sed; 2611 2612 KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->ud_addr, 2613 "address ED %d pipe %d\n", 2614 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->ud_addr); 2615 KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) == 2616 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 2617 "MPL ED %d pipe %d\n", 2618 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), 2619 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 2620 2621 next = stat; 2622 2623 /* Set up data transaction */ 2624 if (len != 0) { 2625 ohci_soft_td_t *std = stat; 2626 2627 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 2628 std, &stat); 2629 if (err) { 2630 /* stat is unchanged if error */ 2631 goto bad3; 2632 } 2633 stat = stat->nexttd; /* point at free TD */ 2634 2635 /* Start toggle at 1 and then use the carried toggle. */ 2636 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 2637 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 2638 usb_syncmem(&std->dma, 2639 std->offs + offsetof(ohci_td_t, td_flags), 2640 sizeof(std->td.td_flags), 2641 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2642 } 2643 2644 memcpy(KERNADDR(&opipe->ctrl.reqdma, 0), req, sizeof(*req)); 2645 usb_syncmem(&opipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2646 2647 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 2648 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 2649 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->ctrl.reqdma, 0)); 2650 setup->td.td_nexttd = HTOO32(next->physaddr); 2651 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof(*req) - 1); 2652 setup->nexttd = next; 2653 setup->len = 0; 2654 setup->xfer = xfer; 2655 setup->flags = 0; 2656 xfer->ux_hcpriv = setup; 2657 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2658 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2659 2660 stat->td.td_flags = HTOO32( 2661 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 2662 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 2663 stat->td.td_cbp = 0; 2664 stat->td.td_nexttd = HTOO32(tail->physaddr); 2665 stat->td.td_be = 0; 2666 stat->nexttd = tail; 2667 stat->flags = OHCI_CALL_DONE; 2668 stat->len = 0; 2669 stat->xfer = xfer; 2670 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2671 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2672 2673 #ifdef OHCI_DEBUG 2674 USBHIST_LOGN(ohcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2675 if (ohcidebug > 5) { 2676 ohci_dump_ed(sc, sed); 2677 ohci_dump_tds(sc, setup); 2678 } 2679 USBHIST_LOGN(ohcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2680 #endif 2681 2682 /* Insert ED in schedule */ 2683 sed->ed.ed_tailp = HTOO32(tail->physaddr); 2684 usb_syncmem(&sed->dma, 2685 sed->offs + offsetof(ohci_ed_t, ed_tailp), 2686 sizeof(sed->ed.ed_tailp), 2687 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2688 opipe->tail.td = tail; 2689 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2690 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2691 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2692 ohci_timeout, xfer); 2693 } 2694 2695 #ifdef OHCI_DEBUG 2696 DPRINTFN(20, "--- dump start ---", 0, 0, 0, 0); 2697 if (ohcidebug > 20) { 2698 delay(10000); 2699 DPRINTFN(20, "status=%x", OREAD4(sc, OHCI_COMMAND_STATUS), 2700 0, 0, 0); 2701 ohci_dumpregs(sc); 2702 DPRINTFN(20, "ctrl head:", 0, 0, 0, 0); 2703 ohci_dump_ed(sc, sc->sc_ctrl_head); 2704 DPRINTF("sed:", 0, 0, 0, 0); 2705 ohci_dump_ed(sc, sed); 2706 ohci_dump_tds(sc, setup); 2707 } 2708 DPRINTFN(20, "--- dump start ---", 0, 0, 0, 0); 2709 #endif 2710 2711 mutex_exit(&sc->sc_lock); 2712 2713 if (sc->sc_bus.ub_usepolling) 2714 ohci_waitintr(sc, xfer); 2715 2716 return USBD_IN_PROGRESS; 2717 2718 bad3: 2719 ohci_free_std(sc, tail); 2720 bad2: 2721 ohci_free_std(sc, stat); 2722 bad1: 2723 mutex_exit(&sc->sc_lock); 2724 2725 return err; 2726 } 2727 2728 /* Abort a device control request. */ 2729 Static void 2730 ohci_device_ctrl_abort(struct usbd_xfer *xfer) 2731 { 2732 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 2733 2734 KASSERT(mutex_owned(&sc->sc_lock)); 2735 2736 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2737 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2738 ohci_abort_xfer(xfer, USBD_CANCELLED); 2739 } 2740 2741 /* Close a device control pipe. */ 2742 Static void 2743 ohci_device_ctrl_close(struct usbd_pipe *pipe) 2744 { 2745 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2746 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2747 2748 KASSERT(mutex_owned(&sc->sc_lock)); 2749 2750 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2751 DPRINTF("pipe=%p", pipe, 0, 0, 0); 2752 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2753 ohci_free_std(sc, opipe->tail.td); 2754 } 2755 2756 /************************/ 2757 2758 Static void 2759 ohci_device_clear_toggle(struct usbd_pipe *pipe) 2760 { 2761 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2762 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2763 2764 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2765 } 2766 2767 Static void 2768 ohci_noop(struct usbd_pipe *pipe) 2769 { 2770 } 2771 2772 Static usbd_status 2773 ohci_device_bulk_transfer(struct usbd_xfer *xfer) 2774 { 2775 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2776 usbd_status err; 2777 2778 /* Insert last in queue. */ 2779 mutex_enter(&sc->sc_lock); 2780 err = usb_insert_transfer(xfer); 2781 mutex_exit(&sc->sc_lock); 2782 if (err) 2783 return err; 2784 2785 /* Pipe isn't running, start first */ 2786 return ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2787 } 2788 2789 Static usbd_status 2790 ohci_device_bulk_start(struct usbd_xfer *xfer) 2791 { 2792 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2793 struct usbd_device *dev = opipe->pipe.up_dev; 2794 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2795 int addr = dev->ud_addr; 2796 ohci_soft_td_t *data, *tail, *tdp; 2797 ohci_soft_ed_t *sed; 2798 int len, isread, endpt; 2799 usbd_status err; 2800 2801 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2802 2803 if (sc->sc_dying) 2804 return USBD_IOERROR; 2805 2806 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2807 2808 mutex_enter(&sc->sc_lock); 2809 2810 len = xfer->ux_length; 2811 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2812 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2813 sed = opipe->sed; 2814 2815 DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread, 2816 xfer->ux_flags); 2817 DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0); 2818 2819 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2820 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2821 /* Update device address */ 2822 sed->ed.ed_flags = HTOO32( 2823 (O32TOH(sed->ed.ed_flags) & ~OHCI_ED_ADDRMASK) | 2824 OHCI_ED_SET_FA(addr)); 2825 2826 /* Allocate a chain of new TDs (including a new tail). */ 2827 data = opipe->tail.td; 2828 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 2829 data, &tail); 2830 if (err) 2831 return err; 2832 2833 /* We want interrupt at the end of the transfer. */ 2834 tail->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 2835 tail->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 2836 tail->flags |= OHCI_CALL_DONE; 2837 tail = tail->nexttd; /* point at sentinel */ 2838 usb_syncmem(&tail->dma, tail->offs + offsetof(ohci_td_t, td_flags), 2839 sizeof(tail->td.td_flags), 2840 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2841 if (err) { 2842 mutex_exit(&sc->sc_lock); 2843 return err; 2844 } 2845 2846 tail->xfer = NULL; 2847 xfer->ux_hcpriv = data; 2848 2849 DPRINTFN(4, "ed_flags=0x%08x td_flags=0x%08x " 2850 "td_cbp=0x%08x td_be=0x%08x", 2851 (int)O32TOH(sed->ed.ed_flags), 2852 (int)O32TOH(data->td.td_flags), 2853 (int)O32TOH(data->td.td_cbp), 2854 (int)O32TOH(data->td.td_be)); 2855 2856 #ifdef OHCI_DEBUG 2857 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2858 if (ohcidebug > 5) { 2859 ohci_dump_ed(sc, sed); 2860 ohci_dump_tds(sc, data); 2861 } 2862 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2863 #endif 2864 2865 /* Insert ED in schedule */ 2866 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 2867 tdp->xfer = xfer; 2868 } 2869 sed->ed.ed_tailp = HTOO32(tail->physaddr); 2870 opipe->tail.td = tail; 2871 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 2872 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2873 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2874 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 2875 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2876 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2877 ohci_timeout, xfer); 2878 } 2879 mutex_exit(&sc->sc_lock); 2880 2881 return USBD_IN_PROGRESS; 2882 } 2883 2884 Static void 2885 ohci_device_bulk_abort(struct usbd_xfer *xfer) 2886 { 2887 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 2888 2889 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2890 2891 KASSERT(mutex_owned(&sc->sc_lock)); 2892 2893 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2894 ohci_abort_xfer(xfer, USBD_CANCELLED); 2895 } 2896 2897 /* 2898 * Close a device bulk pipe. 2899 */ 2900 Static void 2901 ohci_device_bulk_close(struct usbd_pipe *pipe) 2902 { 2903 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2904 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2905 2906 KASSERT(mutex_owned(&sc->sc_lock)); 2907 2908 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2909 2910 DPRINTF("pipe=%p", pipe, 0, 0, 0); 2911 ohci_close_pipe(pipe, sc->sc_bulk_head); 2912 ohci_free_std(sc, opipe->tail.td); 2913 } 2914 2915 /************************/ 2916 2917 Static usbd_status 2918 ohci_device_intr_transfer(struct usbd_xfer *xfer) 2919 { 2920 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2921 usbd_status err; 2922 2923 /* Insert last in queue. */ 2924 mutex_enter(&sc->sc_lock); 2925 err = usb_insert_transfer(xfer); 2926 mutex_exit(&sc->sc_lock); 2927 if (err) 2928 return err; 2929 2930 /* Pipe isn't running, start first */ 2931 return ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2932 } 2933 2934 Static usbd_status 2935 ohci_device_intr_start(struct usbd_xfer *xfer) 2936 { 2937 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2938 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2939 ohci_soft_ed_t *sed = opipe->sed; 2940 ohci_soft_td_t *data, *tail; 2941 int len, isread, endpt; 2942 2943 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2944 2945 if (sc->sc_dying) 2946 return USBD_IOERROR; 2947 2948 DPRINTFN(3, "xfer=%p len=%d flags=%d priv=%p", xfer, xfer->ux_length, 2949 xfer->ux_flags, xfer->ux_priv); 2950 2951 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2952 2953 len = xfer->ux_length; 2954 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2955 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2956 2957 data = opipe->tail.td; 2958 mutex_enter(&sc->sc_lock); 2959 tail = ohci_alloc_std(sc); 2960 mutex_exit(&sc->sc_lock); 2961 if (tail == NULL) 2962 return USBD_NOMEM; 2963 tail->xfer = NULL; 2964 2965 data->td.td_flags = HTOO32( 2966 isread ? OHCI_TD_IN : OHCI_TD_OUT | 2967 OHCI_TD_NOCC | 2968 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 2969 if (xfer->ux_flags & USBD_SHORT_XFER_OK) 2970 data->td.td_flags |= HTOO32(OHCI_TD_R); 2971 data->td.td_cbp = HTOO32(DMAADDR(&xfer->ux_dmabuf, 0)); 2972 data->td.td_nexttd = HTOO32(tail->physaddr); 2973 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + len - 1); 2974 data->nexttd = tail; 2975 data->len = len; 2976 data->xfer = xfer; 2977 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 2978 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 2979 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2980 xfer->ux_hcpriv = data; 2981 2982 #ifdef OHCI_DEBUG 2983 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2984 if (ohcidebug > 5) { 2985 ohci_dump_ed(sc, sed); 2986 ohci_dump_tds(sc, data); 2987 } 2988 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2989 #endif 2990 2991 /* Insert ED in schedule */ 2992 mutex_enter(&sc->sc_lock); 2993 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2994 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2995 sed->ed.ed_tailp = HTOO32(tail->physaddr); 2996 opipe->tail.td = tail; 2997 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 2998 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2999 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3000 3001 mutex_exit(&sc->sc_lock); 3002 3003 return USBD_IN_PROGRESS; 3004 } 3005 3006 /* Abort a device interrupt request. */ 3007 Static void 3008 ohci_device_intr_abort(struct usbd_xfer *xfer) 3009 { 3010 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3011 3012 KASSERT(mutex_owned(&sc->sc_lock)); 3013 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3014 3015 ohci_abort_xfer(xfer, USBD_CANCELLED); 3016 } 3017 3018 /* Close a device interrupt pipe. */ 3019 Static void 3020 ohci_device_intr_close(struct usbd_pipe *pipe) 3021 { 3022 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3023 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3024 int nslots = opipe->intr.nslots; 3025 int pos = opipe->intr.pos; 3026 int j; 3027 ohci_soft_ed_t *p, *sed = opipe->sed; 3028 3029 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3030 3031 KASSERT(mutex_owned(&sc->sc_lock)); 3032 3033 DPRINTFN(1, "pipe=%p nslots=%d pos=%d", pipe, nslots, pos, 0); 3034 usb_syncmem(&sed->dma, sed->offs, 3035 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3036 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3037 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3038 sizeof(sed->ed.ed_flags), 3039 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3040 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3041 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3042 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3043 3044 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3045 continue; 3046 KASSERT(p); 3047 p->next = sed->next; 3048 p->ed.ed_nexted = sed->ed.ed_nexted; 3049 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3050 sizeof(p->ed.ed_nexted), 3051 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3052 3053 for (j = 0; j < nslots; j++) 3054 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3055 3056 ohci_free_std(sc, opipe->tail.td); 3057 ohci_free_sed(sc, opipe->sed); 3058 } 3059 3060 Static usbd_status 3061 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3062 { 3063 int i, j, best; 3064 u_int npoll, slow, shigh, nslots; 3065 u_int bestbw, bw; 3066 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3067 3068 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3069 3070 DPRINTFN(2, "pipe=%p", opipe, 0, 0, 0); 3071 if (ival == 0) { 3072 printf("ohci_setintr: 0 interval\n"); 3073 return USBD_INVAL; 3074 } 3075 3076 npoll = OHCI_NO_INTRS; 3077 while (npoll > ival) 3078 npoll /= 2; 3079 DPRINTFN(2, "ival=%d npoll=%d", ival, npoll, 0, 0); 3080 3081 /* 3082 * We now know which level in the tree the ED must go into. 3083 * Figure out which slot has most bandwidth left over. 3084 * Slots to examine: 3085 * npoll 3086 * 1 0 3087 * 2 1 2 3088 * 4 3 4 5 6 3089 * 8 7 8 9 10 11 12 13 14 3090 * N (N-1) .. (N-1+N-1) 3091 */ 3092 slow = npoll-1; 3093 shigh = slow + npoll; 3094 nslots = OHCI_NO_INTRS / npoll; 3095 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3096 bw = 0; 3097 for (j = 0; j < nslots; j++) 3098 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3099 if (bw < bestbw) { 3100 best = i; 3101 bestbw = bw; 3102 } 3103 } 3104 DPRINTFN(2, "best=%d(%d..%d) bestbw=%d", best, slow, shigh, bestbw); 3105 3106 mutex_enter(&sc->sc_lock); 3107 hsed = sc->sc_eds[best]; 3108 sed->next = hsed->next; 3109 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3110 sizeof(hsed->ed.ed_flags), 3111 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3112 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3113 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3114 sizeof(sed->ed.ed_flags), 3115 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3116 hsed->next = sed; 3117 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3118 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3119 sizeof(hsed->ed.ed_flags), 3120 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3121 mutex_exit(&sc->sc_lock); 3122 3123 for (j = 0; j < nslots; j++) 3124 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3125 opipe->intr.nslots = nslots; 3126 opipe->intr.pos = best; 3127 3128 DPRINTFN(5, "returns %p", opipe, 0, 0, 0); 3129 return USBD_NORMAL_COMPLETION; 3130 } 3131 3132 /***********************/ 3133 3134 usbd_status 3135 ohci_device_isoc_transfer(struct usbd_xfer *xfer) 3136 { 3137 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3138 usbd_status err; 3139 3140 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3141 3142 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 3143 3144 /* Put it on our queue, */ 3145 mutex_enter(&sc->sc_lock); 3146 err = usb_insert_transfer(xfer); 3147 mutex_exit(&sc->sc_lock); 3148 3149 /* bail out on error, */ 3150 if (err && err != USBD_IN_PROGRESS) 3151 return err; 3152 3153 /* XXX should check inuse here */ 3154 3155 /* insert into schedule, */ 3156 ohci_device_isoc_enter(xfer); 3157 3158 /* and start if the pipe wasn't running */ 3159 if (!err) 3160 ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3161 3162 return err; 3163 } 3164 3165 void 3166 ohci_device_isoc_enter(struct usbd_xfer *xfer) 3167 { 3168 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3169 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3170 ohci_soft_ed_t *sed = opipe->sed; 3171 struct isoc *isoc = &opipe->isoc; 3172 ohci_soft_itd_t *sitd, *nsitd; 3173 ohci_physaddr_t buf, offs, noffs, bp0; 3174 int i, ncur, nframes; 3175 3176 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3177 3178 DPRINTFN(1, "used=%d next=%d xfer=%p nframes=%d", 3179 isoc->inuse, isoc->next, xfer, xfer->ux_nframes); 3180 3181 if (sc->sc_dying) 3182 return; 3183 3184 if (isoc->next == -1) { 3185 /* Not in use yet, schedule it a few frames ahead. */ 3186 isoc->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3187 DPRINTFN(2,"start next=%d", isoc->next, 0, 0, 0); 3188 } 3189 3190 sitd = opipe->tail.itd; 3191 buf = DMAADDR(&xfer->ux_dmabuf, 0); 3192 bp0 = OHCI_PAGE(buf); 3193 offs = OHCI_PAGE_OFFSET(buf); 3194 nframes = xfer->ux_nframes; 3195 xfer->ux_hcpriv = sitd; 3196 for (i = ncur = 0; i < nframes; i++, ncur++) { 3197 noffs = offs + xfer->ux_frlengths[i]; 3198 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3199 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3200 3201 /* Allocate next ITD */ 3202 mutex_enter(&sc->sc_lock); 3203 nsitd = ohci_alloc_sitd(sc); 3204 mutex_exit(&sc->sc_lock); 3205 if (nsitd == NULL) { 3206 /* XXX what now? */ 3207 printf("%s: isoc TD alloc failed\n", 3208 device_xname(sc->sc_dev)); 3209 return; 3210 } 3211 3212 /* Fill current ITD */ 3213 sitd->itd.itd_flags = HTOO32( 3214 OHCI_ITD_NOCC | 3215 OHCI_ITD_SET_SF(isoc->next) | 3216 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3217 OHCI_ITD_SET_FC(ncur)); 3218 sitd->itd.itd_bp0 = HTOO32(bp0); 3219 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3220 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3221 sitd->nextitd = nsitd; 3222 sitd->xfer = xfer; 3223 sitd->flags = 0; 3224 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3225 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3226 3227 sitd = nsitd; 3228 isoc->next = isoc->next + ncur; 3229 bp0 = OHCI_PAGE(buf + offs); 3230 ncur = 0; 3231 } 3232 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3233 offs = noffs; 3234 } 3235 mutex_enter(&sc->sc_lock); 3236 nsitd = ohci_alloc_sitd(sc); 3237 mutex_exit(&sc->sc_lock); 3238 if (nsitd == NULL) { 3239 /* XXX what now? */ 3240 printf("%s: isoc TD alloc failed\n", 3241 device_xname(sc->sc_dev)); 3242 return; 3243 } 3244 /* Fixup last used ITD */ 3245 sitd->itd.itd_flags = HTOO32( 3246 OHCI_ITD_NOCC | 3247 OHCI_ITD_SET_SF(isoc->next) | 3248 OHCI_ITD_SET_DI(0) | 3249 OHCI_ITD_SET_FC(ncur)); 3250 sitd->itd.itd_bp0 = HTOO32(bp0); 3251 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3252 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3253 sitd->nextitd = nsitd; 3254 sitd->xfer = xfer; 3255 sitd->flags = OHCI_CALL_DONE; 3256 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3257 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3258 3259 isoc->next = isoc->next + ncur; 3260 isoc->inuse += nframes; 3261 3262 xfer->ux_actlen = offs; /* XXX pretend we did it all */ 3263 3264 xfer->ux_status = USBD_IN_PROGRESS; 3265 3266 #ifdef OHCI_DEBUG 3267 if (ohcidebug > 5) { 3268 DPRINTF("frame=%d", O32TOH(sc->sc_hcca->hcca_frame_number), 3269 0, 0, 0); 3270 ohci_dump_itds(sc, xfer->ux_hcpriv); 3271 ohci_dump_ed(sc, sed); 3272 } 3273 #endif 3274 3275 mutex_enter(&sc->sc_lock); 3276 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3277 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3278 sed->ed.ed_tailp = HTOO32(nsitd->physaddr); 3279 opipe->tail.itd = nsitd; 3280 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3281 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3282 sizeof(sed->ed.ed_flags), 3283 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3284 mutex_exit(&sc->sc_lock); 3285 3286 #ifdef OHCI_DEBUG 3287 if (ohcidebug > 5) { 3288 delay(150000); 3289 DPRINTF("after frame=%d", O32TOH(sc->sc_hcca->hcca_frame_number), 3290 0, 0, 0); 3291 ohci_dump_itds(sc, xfer->ux_hcpriv); 3292 ohci_dump_ed(sc, sed); 3293 } 3294 #endif 3295 } 3296 3297 usbd_status 3298 ohci_device_isoc_start(struct usbd_xfer *xfer) 3299 { 3300 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3301 3302 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3303 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 3304 3305 mutex_enter(&sc->sc_lock); 3306 3307 if (sc->sc_dying) { 3308 mutex_exit(&sc->sc_lock); 3309 return USBD_IOERROR; 3310 } 3311 3312 3313 #ifdef DIAGNOSTIC 3314 if (xfer->ux_status != USBD_IN_PROGRESS) 3315 printf("ohci_device_isoc_start: not in progress %p\n", xfer); 3316 #endif 3317 3318 /* XXX anything to do? */ 3319 3320 mutex_exit(&sc->sc_lock); 3321 3322 return USBD_IN_PROGRESS; 3323 } 3324 3325 void 3326 ohci_device_isoc_abort(struct usbd_xfer *xfer) 3327 { 3328 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3329 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3330 ohci_soft_ed_t *sed; 3331 ohci_soft_itd_t *sitd; 3332 3333 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3334 DPRINTFN(1, "xfer=%p", xfer, 0, 0, 0); 3335 3336 KASSERT(mutex_owned(&sc->sc_lock)); 3337 3338 /* Transfer is already done. */ 3339 if (xfer->ux_status != USBD_NOT_STARTED && 3340 xfer->ux_status != USBD_IN_PROGRESS) { 3341 printf("ohci_device_isoc_abort: early return\n"); 3342 goto done; 3343 } 3344 3345 /* Give xfer the requested abort code. */ 3346 xfer->ux_status = USBD_CANCELLED; 3347 3348 sed = opipe->sed; 3349 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3350 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3351 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3352 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3353 sizeof(sed->ed.ed_flags), 3354 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3355 3356 sitd = xfer->ux_hcpriv; 3357 KASSERT(sitd); 3358 3359 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3360 #ifdef DIAGNOSTIC 3361 DPRINTFN(1, "abort sets done sitd=%p", sitd, 0, 0, 0); 3362 sitd->isdone = true; 3363 #endif 3364 } 3365 3366 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3367 3368 /* Run callback. */ 3369 usb_transfer_complete(xfer); 3370 3371 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3372 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3373 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3374 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3375 3376 done: 3377 KASSERT(mutex_owned(&sc->sc_lock)); 3378 } 3379 3380 void 3381 ohci_device_isoc_done(struct usbd_xfer *xfer) 3382 { 3383 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3384 DPRINTFN(1, "xfer=%p", xfer, 0, 0, 0); 3385 } 3386 3387 usbd_status 3388 ohci_setup_isoc(struct usbd_pipe *pipe) 3389 { 3390 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3391 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3392 struct isoc *isoc = &opipe->isoc; 3393 3394 isoc->next = -1; 3395 isoc->inuse = 0; 3396 3397 mutex_enter(&sc->sc_lock); 3398 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3399 mutex_exit(&sc->sc_lock); 3400 3401 return USBD_NORMAL_COMPLETION; 3402 } 3403 3404 void 3405 ohci_device_isoc_close(struct usbd_pipe *pipe) 3406 { 3407 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3408 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3409 3410 KASSERT(mutex_owned(&sc->sc_lock)); 3411 3412 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3413 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3414 ohci_close_pipe(pipe, sc->sc_isoc_head); 3415 #ifdef DIAGNOSTIC 3416 opipe->tail.itd->isdone = true; 3417 #endif 3418 ohci_free_sitd(sc, opipe->tail.itd); 3419 } 3420
Indexes created Fri Oct 03 02:09:57 GMT 2025