ohci.c revision 1.254.2.35
1 /* $NetBSD: ohci.c,v 1.254.2.35 2015/12/06 15:39:35 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * USB Open Host Controller driver. 38 * 39 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 40 * USB spec: http://www.usb.org/developers/docs/ 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.254.2.35 2015/12/06 15:39:35 skrll Exp $"); 45 46 #include "opt_usb.h" 47 48 #include <sys/param.h> 49 50 #include <sys/cpu.h> 51 #include <sys/device.h> 52 #include <sys/kernel.h> 53 #include <sys/kmem.h> 54 #include <sys/proc.h> 55 #include <sys/queue.h> 56 #include <sys/select.h> 57 #include <sys/sysctl.h> 58 #include <sys/systm.h> 59 60 #include <machine/endian.h> 61 62 #include <dev/usb/usb.h> 63 #include <dev/usb/usbdi.h> 64 #include <dev/usb/usbdivar.h> 65 #include <dev/usb/usb_mem.h> 66 #include <dev/usb/usb_quirks.h> 67 68 #include <dev/usb/ohcireg.h> 69 #include <dev/usb/ohcivar.h> 70 #include <dev/usb/usbroothub.h> 71 #include <dev/usb/usbhist.h> 72 73 #ifdef USB_DEBUG 74 #ifndef OHCI_DEBUG 75 #define ohcidebug 0 76 #else 77 static int ohcidebug = 0; 78 79 SYSCTL_SETUP(sysctl_hw_ohci_setup, "sysctl hw.ohci setup") 80 { 81 int err; 82 const struct sysctlnode *rnode; 83 const struct sysctlnode *cnode; 84 85 err = sysctl_createv(clog, 0, NULL, &rnode, 86 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ohci", 87 SYSCTL_DESCR("ohci global controls"), 88 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 89 90 if (err) 91 goto fail; 92 93 /* control debugging printfs */ 94 err = sysctl_createv(clog, 0, &rnode, &cnode, 95 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 96 "debug", SYSCTL_DESCR("Enable debugging output"), 97 NULL, 0, &ohcidebug, sizeof(ohcidebug), CTL_CREATE, CTL_EOL); 98 if (err) 99 goto fail; 100 101 return; 102 fail: 103 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 104 } 105 106 #endif /* OHCI_DEBUG */ 107 #endif /* USB_DEBUG */ 108 109 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ohcidebug,FMT,A,B,C,D) 110 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ohcidebug,N,FMT,A,B,C,D) 111 #define OHCIHIST_FUNC() USBHIST_FUNC() 112 #define OHCIHIST_CALLED(name) USBHIST_CALLED(ohcidebug) 113 114 #if BYTE_ORDER == BIG_ENDIAN 115 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 116 #else 117 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 118 #endif 119 120 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 121 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 122 #define HTOO16(val) O16TOH(val) 123 #define HTOO32(val) O32TOH(val) 124 125 struct ohci_pipe; 126 127 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 128 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 129 130 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 131 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 132 Static void ohci_free_std_locked(ohci_softc_t *, ohci_soft_td_t *); 133 134 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 135 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 136 Static void ohci_free_sitd_locked(ohci_softc_t *, 137 ohci_soft_itd_t *); 138 139 Static usbd_status ohci_alloc_std_chain(ohci_softc_t *, struct usbd_xfer *, 140 int, int); 141 Static void ohci_free_stds(ohci_softc_t *, struct ohci_xfer *); 142 143 Static void ohci_reset_std_chain(ohci_softc_t *, struct usbd_xfer *, 144 int, int, ohci_soft_td_t *, ohci_soft_td_t **); 145 146 Static usbd_status ohci_open(struct usbd_pipe *); 147 Static void ohci_poll(struct usbd_bus *); 148 Static void ohci_softintr(void *); 149 Static void ohci_waitintr(ohci_softc_t *, struct usbd_xfer *); 150 Static void ohci_rhsc(ohci_softc_t *, struct usbd_xfer *); 151 Static void ohci_rhsc_softint(void *); 152 153 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 154 ohci_soft_ed_t *); 155 156 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 157 ohci_soft_ed_t *); 158 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 159 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 160 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 161 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 162 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 163 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 164 165 Static usbd_status ohci_setup_isoc(struct usbd_pipe *); 166 Static void ohci_device_isoc_enter(struct usbd_xfer *); 167 168 Static struct usbd_xfer * 169 ohci_allocx(struct usbd_bus *, unsigned int); 170 Static void ohci_freex(struct usbd_bus *, struct usbd_xfer *); 171 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 172 Static int ohci_roothub_ctrl(struct usbd_bus *, 173 usb_device_request_t *, void *, int); 174 175 Static usbd_status ohci_root_intr_transfer(struct usbd_xfer *); 176 Static usbd_status ohci_root_intr_start(struct usbd_xfer *); 177 Static void ohci_root_intr_abort(struct usbd_xfer *); 178 Static void ohci_root_intr_close(struct usbd_pipe *); 179 Static void ohci_root_intr_done(struct usbd_xfer *); 180 181 Static int ohci_device_ctrl_init(struct usbd_xfer *); 182 Static void ohci_device_ctrl_fini(struct usbd_xfer *); 183 Static usbd_status ohci_device_ctrl_transfer(struct usbd_xfer *); 184 Static usbd_status ohci_device_ctrl_start(struct usbd_xfer *); 185 Static void ohci_device_ctrl_abort(struct usbd_xfer *); 186 Static void ohci_device_ctrl_close(struct usbd_pipe *); 187 Static void ohci_device_ctrl_done(struct usbd_xfer *); 188 189 Static int ohci_device_bulk_init(struct usbd_xfer *); 190 Static void ohci_device_bulk_fini(struct usbd_xfer *); 191 Static usbd_status ohci_device_bulk_transfer(struct usbd_xfer *); 192 Static usbd_status ohci_device_bulk_start(struct usbd_xfer *); 193 Static void ohci_device_bulk_abort(struct usbd_xfer *); 194 Static void ohci_device_bulk_close(struct usbd_pipe *); 195 Static void ohci_device_bulk_done(struct usbd_xfer *); 196 197 Static int ohci_device_intr_init(struct usbd_xfer *); 198 Static void ohci_device_intr_fini(struct usbd_xfer *); 199 Static usbd_status ohci_device_intr_transfer(struct usbd_xfer *); 200 Static usbd_status ohci_device_intr_start(struct usbd_xfer *); 201 Static void ohci_device_intr_abort(struct usbd_xfer *); 202 Static void ohci_device_intr_close(struct usbd_pipe *); 203 Static void ohci_device_intr_done(struct usbd_xfer *); 204 205 Static int ohci_device_isoc_init(struct usbd_xfer *); 206 Static void ohci_device_isoc_fini(struct usbd_xfer *); 207 Static usbd_status ohci_device_isoc_transfer(struct usbd_xfer *); 208 Static usbd_status ohci_device_isoc_start(struct usbd_xfer *); 209 Static void ohci_device_isoc_abort(struct usbd_xfer *); 210 Static void ohci_device_isoc_close(struct usbd_pipe *); 211 Static void ohci_device_isoc_done(struct usbd_xfer *); 212 213 Static usbd_status ohci_device_setintr(ohci_softc_t *, 214 struct ohci_pipe *, int); 215 216 Static void ohci_timeout(void *); 217 Static void ohci_timeout_task(void *); 218 Static void ohci_rhsc_enable(void *); 219 220 Static void ohci_close_pipe(struct usbd_pipe *, ohci_soft_ed_t *); 221 Static void ohci_abort_xfer(struct usbd_xfer *, usbd_status); 222 223 Static void ohci_device_clear_toggle(struct usbd_pipe *); 224 Static void ohci_noop(struct usbd_pipe *); 225 226 #ifdef OHCI_DEBUG 227 Static void ohci_dumpregs(ohci_softc_t *); 228 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 229 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 230 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 231 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 232 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 233 #endif 234 235 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 236 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 237 #define OWRITE1(sc, r, x) \ 238 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 239 #define OWRITE2(sc, r, x) \ 240 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 241 #define OWRITE4(sc, r, x) \ 242 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 243 244 static __inline uint32_t 245 OREAD4(ohci_softc_t *sc, bus_size_t r) 246 { 247 248 OBARR(sc); 249 return bus_space_read_4(sc->iot, sc->ioh, r); 250 } 251 252 /* Reverse the bits in a value 0 .. 31 */ 253 Static uint8_t revbits[OHCI_NO_INTRS] = 254 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 255 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 256 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 257 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 258 259 struct ohci_pipe { 260 struct usbd_pipe pipe; 261 ohci_soft_ed_t *sed; 262 union { 263 ohci_soft_td_t *td; 264 ohci_soft_itd_t *itd; 265 } tail; 266 /* Info needed for different pipe kinds. */ 267 union { 268 /* Control pipe */ 269 struct { 270 usb_dma_t reqdma; 271 } ctrl; 272 /* Interrupt pipe */ 273 struct { 274 int nslots; 275 int pos; 276 } intr; 277 /* Isochronous pipe */ 278 struct isoc { 279 int next, inuse; 280 } isoc; 281 }; 282 }; 283 284 Static const struct usbd_bus_methods ohci_bus_methods = { 285 .ubm_open = ohci_open, 286 .ubm_softint = ohci_softintr, 287 .ubm_dopoll = ohci_poll, 288 .ubm_allocx = ohci_allocx, 289 .ubm_freex = ohci_freex, 290 .ubm_getlock = ohci_get_lock, 291 .ubm_rhctrl = ohci_roothub_ctrl, 292 }; 293 294 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 295 .upm_transfer = ohci_root_intr_transfer, 296 .upm_start = ohci_root_intr_start, 297 .upm_abort = ohci_root_intr_abort, 298 .upm_close = ohci_root_intr_close, 299 .upm_cleartoggle = ohci_noop, 300 .upm_done = ohci_root_intr_done, 301 }; 302 303 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 304 .upm_init = ohci_device_ctrl_init, 305 .upm_fini = ohci_device_ctrl_fini, 306 .upm_transfer = ohci_device_ctrl_transfer, 307 .upm_start = ohci_device_ctrl_start, 308 .upm_abort = ohci_device_ctrl_abort, 309 .upm_close = ohci_device_ctrl_close, 310 .upm_cleartoggle = ohci_noop, 311 .upm_done = ohci_device_ctrl_done, 312 }; 313 314 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 315 .upm_init = ohci_device_intr_init, 316 .upm_fini = ohci_device_intr_fini, 317 .upm_transfer = ohci_device_intr_transfer, 318 .upm_start = ohci_device_intr_start, 319 .upm_abort = ohci_device_intr_abort, 320 .upm_close = ohci_device_intr_close, 321 .upm_cleartoggle = ohci_device_clear_toggle, 322 .upm_done = ohci_device_intr_done, 323 }; 324 325 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 326 .upm_init = ohci_device_bulk_init, 327 .upm_fini = ohci_device_bulk_fini, 328 .upm_transfer = ohci_device_bulk_transfer, 329 .upm_start = ohci_device_bulk_start, 330 .upm_abort = ohci_device_bulk_abort, 331 .upm_close = ohci_device_bulk_close, 332 .upm_cleartoggle = ohci_device_clear_toggle, 333 .upm_done = ohci_device_bulk_done, 334 }; 335 336 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 337 .upm_init = ohci_device_isoc_init, 338 .upm_fini = ohci_device_isoc_fini, 339 .upm_transfer = ohci_device_isoc_transfer, 340 .upm_start = ohci_device_isoc_start, 341 .upm_abort = ohci_device_isoc_abort, 342 .upm_close = ohci_device_isoc_close, 343 .upm_cleartoggle = ohci_noop, 344 .upm_done = ohci_device_isoc_done, 345 }; 346 347 int 348 ohci_activate(device_t self, enum devact act) 349 { 350 struct ohci_softc *sc = device_private(self); 351 352 switch (act) { 353 case DVACT_DEACTIVATE: 354 sc->sc_dying = 1; 355 return 0; 356 default: 357 return EOPNOTSUPP; 358 } 359 } 360 361 void 362 ohci_childdet(device_t self, device_t child) 363 { 364 struct ohci_softc *sc = device_private(self); 365 366 KASSERT(sc->sc_child == child); 367 sc->sc_child = NULL; 368 } 369 370 int 371 ohci_detach(struct ohci_softc *sc, int flags) 372 { 373 int rv = 0; 374 375 if (sc->sc_child != NULL) 376 rv = config_detach(sc->sc_child, flags); 377 378 if (rv != 0) 379 return rv; 380 381 callout_halt(&sc->sc_tmo_rhsc, &sc->sc_lock); 382 383 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 384 callout_destroy(&sc->sc_tmo_rhsc); 385 386 softint_disestablish(sc->sc_rhsc_si); 387 388 cv_destroy(&sc->sc_softwake_cv); 389 390 mutex_destroy(&sc->sc_lock); 391 mutex_destroy(&sc->sc_intr_lock); 392 393 if (sc->sc_hcca != NULL) 394 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 395 pool_cache_destroy(sc->sc_xferpool); 396 397 return rv; 398 } 399 400 ohci_soft_ed_t * 401 ohci_alloc_sed(ohci_softc_t *sc) 402 { 403 ohci_soft_ed_t *sed; 404 usbd_status err; 405 int i, offs; 406 usb_dma_t dma; 407 408 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 409 410 mutex_enter(&sc->sc_lock); 411 if (sc->sc_freeeds == NULL) { 412 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 413 mutex_exit(&sc->sc_lock); 414 415 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 416 OHCI_ED_ALIGN, &dma); 417 if (err) 418 return 0; 419 420 mutex_enter(&sc->sc_lock); 421 for (i = 0; i < OHCI_SED_CHUNK; i++) { 422 offs = i * OHCI_SED_SIZE; 423 sed = KERNADDR(&dma, offs); 424 sed->physaddr = DMAADDR(&dma, offs); 425 sed->dma = dma; 426 sed->offs = offs; 427 sed->next = sc->sc_freeeds; 428 sc->sc_freeeds = sed; 429 } 430 } 431 sed = sc->sc_freeeds; 432 sc->sc_freeeds = sed->next; 433 mutex_exit(&sc->sc_lock); 434 435 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 436 sed->next = 0; 437 return sed; 438 } 439 440 static inline void 441 ohci_free_sed_locked(ohci_softc_t *sc, ohci_soft_ed_t *sed) 442 { 443 444 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 445 446 sed->next = sc->sc_freeeds; 447 sc->sc_freeeds = sed; 448 } 449 450 void 451 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 452 { 453 454 mutex_enter(&sc->sc_lock); 455 ohci_free_sed_locked(sc, sed); 456 mutex_exit(&sc->sc_lock); 457 } 458 459 ohci_soft_td_t * 460 ohci_alloc_std(ohci_softc_t *sc) 461 { 462 ohci_soft_td_t *std; 463 usbd_status err; 464 int i, offs; 465 usb_dma_t dma; 466 467 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 468 469 mutex_enter(&sc->sc_lock); 470 if (sc->sc_freetds == NULL) { 471 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 472 mutex_exit(&sc->sc_lock); 473 474 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 475 OHCI_TD_ALIGN, &dma); 476 if (err) 477 return NULL; 478 479 mutex_enter(&sc->sc_lock); 480 for(i = 0; i < OHCI_STD_CHUNK; i++) { 481 offs = i * OHCI_STD_SIZE; 482 std = KERNADDR(&dma, offs); 483 std->physaddr = DMAADDR(&dma, offs); 484 std->dma = dma; 485 std->offs = offs; 486 std->nexttd = sc->sc_freetds; 487 sc->sc_freetds = std; 488 } 489 } 490 491 std = sc->sc_freetds; 492 sc->sc_freetds = std->nexttd; 493 mutex_exit(&sc->sc_lock); 494 495 memset(&std->td, 0, sizeof(ohci_td_t)); 496 std->nexttd = NULL; 497 std->xfer = NULL; 498 499 return std; 500 } 501 502 void 503 ohci_free_std_locked(ohci_softc_t *sc, ohci_soft_td_t *std) 504 { 505 506 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 507 508 std->nexttd = sc->sc_freetds; 509 sc->sc_freetds = std; 510 } 511 512 void 513 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 514 { 515 516 mutex_enter(&sc->sc_lock); 517 ohci_free_std_locked(sc, std); 518 mutex_exit(&sc->sc_lock); 519 } 520 521 Static usbd_status 522 ohci_alloc_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, int alen, int rd) 523 { 524 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 525 struct usbd_pipe *pipe = xfer->ux_pipe; 526 ohci_soft_td_t *next, *cur; 527 ohci_physaddr_t dataphys, dataphysend; 528 uint32_t tdflags; 529 int len = alen; 530 int curlen; 531 usb_dma_t *dma = &xfer->ux_dmabuf; 532 uint16_t flags = xfer->ux_flags; 533 534 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 535 536 DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d", 537 pipe->up_dev->ud_addr, 538 UE_GET_ADDR(pipe->up_endpoint->ue_edesc->bEndpointAddress), 539 alen, pipe->up_dev->ud_speed); 540 541 ASSERT_SLEEPABLE(); 542 543 size_t nstd = (flags & USBD_FORCE_SHORT_XFER) ? 1 : 0; 544 nstd += ((len + OHCI_PAGE_SIZE - 1) / OHCI_PAGE_SIZE); 545 ox->ox_stds = kmem_zalloc(sizeof(ohci_soft_td_t *) * nstd, 546 KM_SLEEP); 547 ox->ox_nstd = nstd; 548 int mps = UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize); 549 550 DPRINTFN(8, "xfer %p nstd %d mps %d", xfer, nstd, mps, 0); 551 552 len = alen; 553 cur = ohci_alloc_std(sc); 554 if (cur == NULL) 555 goto nomem; 556 557 dataphys = DMAADDR(dma, 0); 558 dataphysend = OHCI_PAGE(dataphys + len - 1); 559 tdflags = HTOO32( 560 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 561 (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) | 562 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 563 564 for (size_t j = 0;;) { 565 ox->ox_stds[j++] = cur; 566 next = ohci_alloc_std(sc); 567 if (next == NULL) 568 goto nomem; 569 570 /* The OHCI hardware can handle at most one page crossing. */ 571 if (OHCI_PAGE(dataphys) == dataphysend || 572 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 573 /* we can handle it in this TD */ 574 curlen = len; 575 } else { 576 /* must use multiple TDs, fill as much as possible. */ 577 curlen = 2 * OHCI_PAGE_SIZE - 578 (dataphys & (OHCI_PAGE_SIZE-1)); 579 /* the length must be a multiple of the max size */ 580 curlen -= curlen % mps; 581 KASSERT(curlen != 0); 582 } 583 DPRINTFN(4, "dataphys=0x%08x dataphysend=0x%08x " 584 "len=%d curlen=%d", dataphys, dataphysend, len, curlen); 585 len -= curlen; 586 587 cur->td.td_flags = tdflags; 588 cur->td.td_cbp = HTOO32(dataphys); 589 cur->td.td_nexttd = HTOO32(next->physaddr); 590 cur->td.td_be = HTOO32(dataphys + curlen - 1); 591 cur->nexttd = next; 592 cur->len = curlen; 593 cur->flags = OHCI_ADD_LEN; 594 cur->xfer = xfer; 595 596 DPRINTFN(10, "cbp=0x%08x be=0x%08x", dataphys, 597 dataphys + curlen - 1, 0, 0); 598 if (len == 0) 599 break; 600 DPRINTFN(10, "extend chain", 0, 0, 0, 0); 601 dataphys += curlen; 602 cur = next; 603 } 604 if (!rd && (flags & USBD_FORCE_SHORT_XFER) && 605 alen % mps == 0) { 606 /* Force a 0 length transfer at the end. */ 607 608 cur = next; 609 next = ohci_alloc_std(sc); 610 if (next == NULL) 611 goto nomem; 612 613 cur->td.td_flags = tdflags; 614 cur->td.td_cbp = 0; /* indicate 0 length packet */ 615 cur->td.td_nexttd = HTOO32(next->physaddr); 616 cur->td.td_be = ~0; 617 cur->nexttd = next; 618 cur->len = 0; 619 cur->flags = 0; 620 cur->xfer = xfer; 621 622 DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0); 623 } 624 625 return USBD_NORMAL_COMPLETION; 626 627 nomem: 628 ohci_free_stds(sc, ox); 629 630 return USBD_NOMEM; 631 } 632 633 Static void 634 ohci_free_stds(ohci_softc_t *sc, struct ohci_xfer *ox) 635 { 636 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 637 DPRINTF("ox=%p", ox, 0, 0, 0); 638 639 mutex_enter(&sc->sc_lock); 640 for (size_t i = 0; i < ox->ox_nstd; i++) { 641 ohci_soft_td_t *std = ox->ox_stds[i]; 642 if (std == NULL) 643 break; 644 ohci_free_std_locked(sc, std); 645 } 646 mutex_exit(&sc->sc_lock); 647 } 648 649 void 650 ohci_reset_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, 651 int alen, int rd, ohci_soft_td_t *sp, ohci_soft_td_t **ep) 652 { 653 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 654 ohci_soft_td_t *next, *cur; 655 ohci_physaddr_t dataphys, dataphysend; 656 uint32_t tdflags; 657 int len, curlen; 658 usb_dma_t *dma = &xfer->ux_dmabuf; 659 uint16_t flags = xfer->ux_flags; 660 661 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 662 DPRINTF("start len=%d", alen, 0, 0, 0); 663 664 KASSERT(mutex_owned(&sc->sc_lock)); 665 666 DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d", 667 xfer->ux_pipe->up_dev->ud_addr, 668 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 669 alen, xfer->ux_pipe->up_dev->ud_speed); 670 671 ASSERT_SLEEPABLE(); 672 KASSERT(sp); 673 674 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 675 676 len = alen; 677 cur = sp; 678 679 dataphys = DMAADDR(dma, 0); 680 dataphysend = OHCI_PAGE(dataphys + len - 1); 681 usb_syncmem(dma, 0, len, 682 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 683 tdflags = HTOO32( 684 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 685 (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) | 686 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 687 688 for (size_t j = 1;;) { 689 if (j == ox->ox_nstd) 690 next = NULL; 691 else 692 next = ox->ox_stds[j++]; 693 KASSERT(next != cur); 694 695 /* The OHCI hardware can handle at most one page crossing. */ 696 if (OHCI_PAGE(dataphys) == dataphysend || 697 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 698 /* we can handle it in this TD */ 699 curlen = len; 700 } else { 701 /* must use multiple TDs, fill as much as possible. */ 702 curlen = 2 * OHCI_PAGE_SIZE - 703 (dataphys & (OHCI_PAGE_SIZE - 1)); 704 /* the length must be a multiple of the max size */ 705 curlen -= curlen % mps; 706 KASSERT(curlen != 0); 707 } 708 DPRINTFN(4, "dataphys=0x%08x dataphysend=0x%08x " 709 "len=%d curlen=%d", dataphys, dataphysend, len, curlen); 710 len -= curlen; 711 712 cur->td.td_flags = tdflags; 713 cur->td.td_cbp = HTOO32(dataphys); 714 cur->td.td_be = HTOO32(dataphys + curlen - 1); 715 cur->td.td_nexttd = (next != NULL) ? HTOO32(next->physaddr) : 0; 716 cur->nexttd = next; 717 cur->len = curlen; 718 cur->flags = OHCI_ADD_LEN; 719 cur->xfer = xfer; 720 ohci_hash_add_td(sc, cur); 721 722 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 723 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 724 DPRINTFN(10, "cbp=0x%08x be=0x%08x", dataphys, 725 dataphys + curlen - 1, 0, 0); 726 if (len == 0) 727 break; 728 KASSERT(next != NULL); 729 DPRINTFN(10, "extend chain", 0, 0, 0, 0); 730 dataphys += curlen; 731 cur = next; 732 } 733 if (!rd && 734 (flags & USBD_FORCE_SHORT_XFER) && 735 alen % mps == 0) { 736 /* Force a 0 length transfer at the end. */ 737 738 KASSERT(next != NULL); 739 cur = next; 740 741 cur->td.td_flags = tdflags; 742 cur->td.td_cbp = 0; /* indicate 0 length packet */ 743 cur->td.td_nexttd = HTOO32(next->physaddr); 744 cur->td.td_be = ~0; 745 cur->nexttd = NULL; 746 cur->len = 0; 747 cur->flags = 0; 748 cur->xfer = xfer; 749 ohci_hash_add_td(sc, cur); 750 751 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 752 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 753 DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0); 754 } 755 *ep = cur; 756 } 757 758 ohci_soft_itd_t * 759 ohci_alloc_sitd(ohci_softc_t *sc) 760 { 761 ohci_soft_itd_t *sitd; 762 usbd_status err; 763 int i, offs; 764 usb_dma_t dma; 765 766 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 767 768 mutex_enter(&sc->sc_lock); 769 if (sc->sc_freeitds == NULL) { 770 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 771 mutex_exit(&sc->sc_lock); 772 773 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 774 OHCI_ITD_ALIGN, &dma); 775 if (err) 776 return NULL; 777 mutex_enter(&sc->sc_lock); 778 for(i = 0; i < OHCI_SITD_CHUNK; i++) { 779 offs = i * OHCI_SITD_SIZE; 780 sitd = KERNADDR(&dma, offs); 781 sitd->physaddr = DMAADDR(&dma, offs); 782 sitd->dma = dma; 783 sitd->offs = offs; 784 sitd->nextitd = sc->sc_freeitds; 785 sc->sc_freeitds = sitd; 786 } 787 } 788 789 sitd = sc->sc_freeitds; 790 sc->sc_freeitds = sitd->nextitd; 791 mutex_exit(&sc->sc_lock); 792 793 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 794 sitd->nextitd = NULL; 795 sitd->xfer = NULL; 796 797 #ifdef DIAGNOSTIC 798 sitd->isdone = false; 799 #endif 800 801 return sitd; 802 } 803 804 Static void 805 ohci_free_sitd_locked(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 806 { 807 808 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 809 DPRINTFN(10, "sitd=%p", sitd, 0, 0, 0); 810 811 KASSERT(sitd->isdone); 812 #ifdef DIAGNOSTIC 813 /* Warn double free */ 814 sitd->isdone = false; 815 #endif 816 817 sitd->nextitd = sc->sc_freeitds; 818 sc->sc_freeitds = sitd; 819 } 820 821 void 822 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 823 { 824 825 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 826 827 mutex_enter(&sc->sc_lock); 828 ohci_free_sitd_locked(sc, sitd); 829 mutex_exit(&sc->sc_lock); 830 } 831 832 int 833 ohci_init(ohci_softc_t *sc) 834 { 835 ohci_soft_ed_t *sed, *psed; 836 usbd_status err; 837 int i; 838 uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */; 839 840 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 841 842 aprint_normal_dev(sc->sc_dev, ""); 843 844 sc->sc_hcca = NULL; 845 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 846 847 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 848 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 849 cv_init(&sc->sc_softwake_cv, "ohciab"); 850 851 sc->sc_rhsc_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 852 ohci_rhsc_softint, sc); 853 854 for (i = 0; i < OHCI_HASH_SIZE; i++) 855 LIST_INIT(&sc->sc_hash_tds[i]); 856 for (i = 0; i < OHCI_HASH_SIZE; i++) 857 LIST_INIT(&sc->sc_hash_itds[i]); 858 859 sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0, 860 "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL); 861 862 rev = OREAD4(sc, OHCI_REVISION); 863 aprint_normal("OHCI version %d.%d%s\n", 864 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 865 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 866 867 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 868 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 869 sc->sc_bus.ub_revision = USBREV_UNKNOWN; 870 return -1; 871 } 872 sc->sc_bus.ub_revision = USBREV_1_0; 873 sc->sc_bus.ub_usedma = true; 874 875 /* XXX determine alignment by R/W */ 876 /* Allocate the HCCA area. */ 877 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 878 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 879 if (err) { 880 sc->sc_hcca = NULL; 881 return err; 882 } 883 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 884 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 885 886 sc->sc_eintrs = OHCI_NORMAL_INTRS; 887 888 /* Allocate dummy ED that starts the control list. */ 889 sc->sc_ctrl_head = ohci_alloc_sed(sc); 890 if (sc->sc_ctrl_head == NULL) { 891 err = ENOMEM; 892 goto bad1; 893 } 894 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 895 896 /* Allocate dummy ED that starts the bulk list. */ 897 sc->sc_bulk_head = ohci_alloc_sed(sc); 898 if (sc->sc_bulk_head == NULL) { 899 err = ENOMEM; 900 goto bad2; 901 } 902 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 903 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 904 sizeof(sc->sc_bulk_head->ed), 905 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 906 907 /* Allocate dummy ED that starts the isochronous list. */ 908 sc->sc_isoc_head = ohci_alloc_sed(sc); 909 if (sc->sc_isoc_head == NULL) { 910 err = ENOMEM; 911 goto bad3; 912 } 913 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 914 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 915 sizeof(sc->sc_isoc_head->ed), 916 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 917 918 /* Allocate all the dummy EDs that make up the interrupt tree. */ 919 for (i = 0; i < OHCI_NO_EDS; i++) { 920 sed = ohci_alloc_sed(sc); 921 if (sed == NULL) { 922 while (--i >= 0) 923 ohci_free_sed(sc, sc->sc_eds[i]); 924 err = ENOMEM; 925 goto bad4; 926 } 927 /* All ED fields are set to 0. */ 928 sc->sc_eds[i] = sed; 929 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 930 if (i != 0) 931 psed = sc->sc_eds[(i-1) / 2]; 932 else 933 psed= sc->sc_isoc_head; 934 sed->next = psed; 935 sed->ed.ed_nexted = HTOO32(psed->physaddr); 936 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 937 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 938 } 939 /* 940 * Fill HCCA interrupt table. The bit reversal is to get 941 * the tree set up properly to spread the interrupts. 942 */ 943 for (i = 0; i < OHCI_NO_INTRS; i++) 944 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 945 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 946 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 947 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 948 949 #ifdef OHCI_DEBUG 950 DPRINTFN(15, "--- dump start ---", 0, 0, 0 ,0); 951 if (ohcidebug > 15) { 952 for (i = 0; i < OHCI_NO_EDS; i++) { 953 DPRINTFN(15, "ed#%d ", i, 0, 0, 0); 954 ohci_dump_ed(sc, sc->sc_eds[i]); 955 } 956 DPRINTFN(15, "iso", 0, 0, 0 ,0); 957 ohci_dump_ed(sc, sc->sc_isoc_head); 958 } 959 DPRINTFN(15, "--- dump end ---", 0, 0, 0 ,0); 960 #endif 961 962 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 963 ctl = OREAD4(sc, OHCI_CONTROL); 964 rwc = ctl & OHCI_RWC; 965 fm = OREAD4(sc, OHCI_FM_INTERVAL); 966 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 967 /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */ 968 969 /* Determine in what context we are running. */ 970 if (ctl & OHCI_IR) { 971 /* SMM active, request change */ 972 DPRINTF("SMM active, request owner change", 0, 0, 0, 0); 973 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 974 (OHCI_OC | OHCI_MIE)) 975 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 976 s = OREAD4(sc, OHCI_COMMAND_STATUS); 977 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 978 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 979 usb_delay_ms(&sc->sc_bus, 1); 980 ctl = OREAD4(sc, OHCI_CONTROL); 981 } 982 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 983 if ((ctl & OHCI_IR) == 0) { 984 aprint_error_dev(sc->sc_dev, 985 "SMM does not respond, resetting\n"); 986 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 987 goto reset; 988 } 989 #if 0 990 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 991 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 992 /* BIOS started controller. */ 993 DPRINTF("BIOS active", 0, 0, 0, 0); 994 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 995 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 996 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 997 } 998 #endif 999 } else { 1000 DPRINTF("cold started", 0 ,0 ,0 ,0); 1001 reset: 1002 /* Controller was cold started. */ 1003 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 1004 } 1005 1006 /* 1007 * This reset should not be necessary according to the OHCI spec, but 1008 * without it some controllers do not start. 1009 */ 1010 DPRINTF("sc %p: resetting", sc, 0, 0, 0); 1011 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 1012 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 1013 1014 /* We now own the host controller and the bus has been reset. */ 1015 1016 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 1017 /* Nominal time for a reset is 10 us. */ 1018 for (i = 0; i < 10; i++) { 1019 delay(10); 1020 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 1021 if (!hcr) 1022 break; 1023 } 1024 if (hcr) { 1025 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 1026 err = EIO; 1027 goto bad5; 1028 } 1029 #ifdef OHCI_DEBUG 1030 if (ohcidebug > 15) 1031 ohci_dumpregs(sc); 1032 #endif 1033 1034 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 1035 1036 /* Set up HC registers. */ 1037 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1038 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 1039 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 1040 /* disable all interrupts and then switch on all desired interrupts */ 1041 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 1042 /* switch on desired functional features */ 1043 ctl = OREAD4(sc, OHCI_CONTROL); 1044 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 1045 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 1046 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 1047 /* And finally start it! */ 1048 OWRITE4(sc, OHCI_CONTROL, ctl); 1049 1050 /* 1051 * The controller is now OPERATIONAL. Set a some final 1052 * registers that should be set earlier, but that the 1053 * controller ignores when in the SUSPEND state. 1054 */ 1055 ival = OHCI_GET_IVAL(fm); 1056 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 1057 fm |= OHCI_FSMPS(ival) | ival; 1058 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 1059 per = OHCI_PERIODIC(ival); /* 90% periodic */ 1060 OWRITE4(sc, OHCI_PERIODIC_START, per); 1061 1062 if (sc->sc_flags & OHCIF_SUPERIO) { 1063 /* no overcurrent protection */ 1064 desca |= OHCI_NOCP; 1065 /* 1066 * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning 1067 * that 1068 * - ports are always power switched 1069 * - don't wait for powered root hub port 1070 */ 1071 desca &= ~(__SHIFTIN(0xff, OHCI_POTPGT_MASK) | OHCI_NPS); 1072 } 1073 1074 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 1075 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 1076 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 1077 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 1078 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 1079 1080 /* 1081 * The AMD756 requires a delay before re-reading the register, 1082 * otherwise it will occasionally report 0 ports. 1083 */ 1084 sc->sc_noport = 0; 1085 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 1086 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 1087 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 1088 } 1089 1090 #ifdef OHCI_DEBUG 1091 if (ohcidebug > 5) 1092 ohci_dumpregs(sc); 1093 #endif 1094 1095 /* Set up the bus struct. */ 1096 sc->sc_bus.ub_methods = &ohci_bus_methods; 1097 sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe); 1098 1099 sc->sc_control = sc->sc_intre = 0; 1100 1101 /* Finally, turn on interrupts. */ 1102 DPRINTF("enabling %#x", sc->sc_eintrs | OHCI_MIE, 0, 0, 0); 1103 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 1104 1105 return 0; 1106 1107 bad5: 1108 for (i = 0; i < OHCI_NO_EDS; i++) 1109 ohci_free_sed(sc, sc->sc_eds[i]); 1110 bad4: 1111 ohci_free_sed(sc, sc->sc_isoc_head); 1112 bad3: 1113 ohci_free_sed(sc, sc->sc_bulk_head); 1114 bad2: 1115 ohci_free_sed(sc, sc->sc_ctrl_head); 1116 bad1: 1117 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 1118 sc->sc_hcca = NULL; 1119 return err; 1120 } 1121 1122 struct usbd_xfer * 1123 ohci_allocx(struct usbd_bus *bus, unsigned int nframes) 1124 { 1125 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1126 struct usbd_xfer *xfer; 1127 1128 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1129 if (xfer != NULL) { 1130 memset(xfer, 0, sizeof(struct ohci_xfer)); 1131 #ifdef DIAGNOSTIC 1132 xfer->ux_state = XFER_BUSY; 1133 #endif 1134 } 1135 return xfer; 1136 } 1137 1138 void 1139 ohci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1140 { 1141 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1142 1143 KASSERTMSG(xfer->ux_state == XFER_BUSY, 1144 "xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state); 1145 #ifdef DIAGNOSTIC 1146 xfer->ux_state = XFER_FREE; 1147 #endif 1148 pool_cache_put(sc->sc_xferpool, xfer); 1149 } 1150 1151 Static void 1152 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1153 { 1154 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1155 1156 *lock = &sc->sc_lock; 1157 } 1158 1159 /* 1160 * Shut down the controller when the system is going down. 1161 */ 1162 bool 1163 ohci_shutdown(device_t self, int flags) 1164 { 1165 ohci_softc_t *sc = device_private(self); 1166 1167 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1168 1169 DPRINTF("stopping the HC", 0, 0, 0, 0); 1170 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1171 return true; 1172 } 1173 1174 bool 1175 ohci_resume(device_t dv, const pmf_qual_t *qual) 1176 { 1177 ohci_softc_t *sc = device_private(dv); 1178 uint32_t ctl; 1179 1180 mutex_spin_enter(&sc->sc_intr_lock); 1181 sc->sc_bus.ub_usepolling++; 1182 mutex_spin_exit(&sc->sc_intr_lock); 1183 1184 /* Some broken BIOSes do not recover these values */ 1185 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1186 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1187 sc->sc_ctrl_head->physaddr); 1188 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1189 sc->sc_bulk_head->physaddr); 1190 if (sc->sc_intre) 1191 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1192 (OHCI_ALL_INTRS | OHCI_MIE)); 1193 if (sc->sc_control) 1194 ctl = sc->sc_control; 1195 else 1196 ctl = OREAD4(sc, OHCI_CONTROL); 1197 ctl |= OHCI_HCFS_RESUME; 1198 OWRITE4(sc, OHCI_CONTROL, ctl); 1199 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1200 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1201 OWRITE4(sc, OHCI_CONTROL, ctl); 1202 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1203 sc->sc_control = sc->sc_intre = 0; 1204 1205 mutex_spin_enter(&sc->sc_intr_lock); 1206 sc->sc_bus.ub_usepolling--; 1207 mutex_spin_exit(&sc->sc_intr_lock); 1208 1209 return true; 1210 } 1211 1212 bool 1213 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1214 { 1215 ohci_softc_t *sc = device_private(dv); 1216 uint32_t ctl; 1217 1218 mutex_spin_enter(&sc->sc_intr_lock); 1219 sc->sc_bus.ub_usepolling++; 1220 mutex_spin_exit(&sc->sc_intr_lock); 1221 1222 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1223 if (sc->sc_control == 0) { 1224 /* 1225 * Preserve register values, in case that BIOS 1226 * does not recover them. 1227 */ 1228 sc->sc_control = ctl; 1229 sc->sc_intre = OREAD4(sc, 1230 OHCI_INTERRUPT_ENABLE); 1231 } 1232 ctl |= OHCI_HCFS_SUSPEND; 1233 OWRITE4(sc, OHCI_CONTROL, ctl); 1234 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1235 1236 mutex_spin_enter(&sc->sc_intr_lock); 1237 sc->sc_bus.ub_usepolling--; 1238 mutex_spin_exit(&sc->sc_intr_lock); 1239 1240 return true; 1241 } 1242 1243 #ifdef OHCI_DEBUG 1244 void 1245 ohci_dumpregs(ohci_softc_t *sc) 1246 { 1247 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1248 1249 DPRINTF("rev=0x%08x control=0x%08x command=0x%08x", 1250 OREAD4(sc, OHCI_REVISION), 1251 OREAD4(sc, OHCI_CONTROL), 1252 OREAD4(sc, OHCI_COMMAND_STATUS), 0); 1253 DPRINTF(" intrstat=0x%08x intre=0x%08x intrd=0x%08x", 1254 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1255 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1256 OREAD4(sc, OHCI_INTERRUPT_DISABLE), 0); 1257 DPRINTF(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x", 1258 OREAD4(sc, OHCI_HCCA), 1259 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1260 OREAD4(sc, OHCI_CONTROL_HEAD_ED), 0); 1261 DPRINTF(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x", 1262 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1263 OREAD4(sc, OHCI_BULK_HEAD_ED), 1264 OREAD4(sc, OHCI_BULK_CURRENT_ED) ,0); 1265 DPRINTF(" done=0x%08x fmival=0x%08x fmrem=0x%08x", 1266 OREAD4(sc, OHCI_DONE_HEAD), 1267 OREAD4(sc, OHCI_FM_INTERVAL), 1268 OREAD4(sc, OHCI_FM_REMAINING), 0); 1269 DPRINTF(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x", 1270 OREAD4(sc, OHCI_FM_NUMBER), 1271 OREAD4(sc, OHCI_PERIODIC_START), 1272 OREAD4(sc, OHCI_LS_THRESHOLD), 0); 1273 DPRINTF(" desca=0x%08x descb=0x%08x stat=0x%08x", 1274 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1275 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1276 OREAD4(sc, OHCI_RH_STATUS), 0); 1277 DPRINTF(" port1=0x%08x port2=0x%08x", 1278 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1279 OREAD4(sc, OHCI_RH_PORT_STATUS(2)), 0, 0); 1280 DPRINTF(" HCCA: frame_number=0x%04x done_head=0x%08x", 1281 O32TOH(sc->sc_hcca->hcca_frame_number), 1282 O32TOH(sc->sc_hcca->hcca_done_head), 0, 0); 1283 } 1284 #endif 1285 1286 Static int ohci_intr1(ohci_softc_t *); 1287 1288 int 1289 ohci_intr(void *p) 1290 { 1291 ohci_softc_t *sc = p; 1292 int ret = 0; 1293 1294 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1295 1296 if (sc == NULL) 1297 return 0; 1298 1299 mutex_spin_enter(&sc->sc_intr_lock); 1300 1301 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1302 goto done; 1303 1304 /* If we get an interrupt while polling, then just ignore it. */ 1305 if (sc->sc_bus.ub_usepolling) { 1306 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1307 /* for level triggered intrs, should do something to ack */ 1308 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1309 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1310 1311 goto done; 1312 } 1313 1314 ret = ohci_intr1(sc); 1315 1316 done: 1317 mutex_spin_exit(&sc->sc_intr_lock); 1318 return ret; 1319 } 1320 1321 Static int 1322 ohci_intr1(ohci_softc_t *sc) 1323 { 1324 uint32_t intrs, eintrs; 1325 1326 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1327 1328 /* In case the interrupt occurs before initialization has completed. */ 1329 if (sc == NULL || sc->sc_hcca == NULL) { 1330 #ifdef DIAGNOSTIC 1331 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1332 #endif 1333 return 0; 1334 } 1335 1336 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1337 1338 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1339 if (!intrs) 1340 return 0; 1341 1342 /* Acknowledge */ 1343 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); 1344 eintrs = intrs & sc->sc_eintrs; 1345 DPRINTFN(7, "sc=%p", sc, 0, 0, 0); 1346 DPRINTFN(7, "intrs=%#x(%#x) eintrs=%#x(%#x)", 1347 intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), eintrs, 1348 sc->sc_eintrs); 1349 1350 if (!eintrs) { 1351 return 0; 1352 } 1353 1354 if (eintrs & OHCI_SO) { 1355 sc->sc_overrun_cnt++; 1356 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1357 printf("%s: %u scheduling overruns\n", 1358 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1359 sc->sc_overrun_cnt = 0; 1360 } 1361 /* XXX do what */ 1362 eintrs &= ~OHCI_SO; 1363 } 1364 if (eintrs & OHCI_WDH) { 1365 /* 1366 * We block the interrupt below, and reenable it later from 1367 * ohci_softintr(). 1368 */ 1369 usb_schedsoftintr(&sc->sc_bus); 1370 } 1371 if (eintrs & OHCI_RD) { 1372 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1373 /* XXX process resume detect */ 1374 } 1375 if (eintrs & OHCI_UE) { 1376 printf("%s: unrecoverable error, controller halted\n", 1377 device_xname(sc->sc_dev)); 1378 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1379 /* XXX what else */ 1380 } 1381 if (eintrs & OHCI_RHSC) { 1382 /* 1383 * We block the interrupt below, and reenable it later from 1384 * a timeout. 1385 */ 1386 softint_schedule(sc->sc_rhsc_si); 1387 } 1388 1389 if (eintrs != 0) { 1390 /* Block unprocessed interrupts. */ 1391 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1392 sc->sc_eintrs &= ~eintrs; 1393 DPRINTF("sc %p blocking intrs 0x%x", sc, eintrs, 0, 0); 1394 } 1395 1396 return 1; 1397 } 1398 1399 void 1400 ohci_rhsc_enable(void *v_sc) 1401 { 1402 ohci_softc_t *sc = v_sc; 1403 1404 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1405 DPRINTF("sc %p", sc, 0, 0, 0); 1406 mutex_spin_enter(&sc->sc_intr_lock); 1407 sc->sc_eintrs |= OHCI_RHSC; 1408 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1409 mutex_spin_exit(&sc->sc_intr_lock); 1410 } 1411 1412 #ifdef OHCI_DEBUG 1413 const char *ohci_cc_strs[] = { 1414 "NO_ERROR", 1415 "CRC", 1416 "BIT_STUFFING", 1417 "DATA_TOGGLE_MISMATCH", 1418 "STALL", 1419 "DEVICE_NOT_RESPONDING", 1420 "PID_CHECK_FAILURE", 1421 "UNEXPECTED_PID", 1422 "DATA_OVERRUN", 1423 "DATA_UNDERRUN", 1424 "BUFFER_OVERRUN", 1425 "BUFFER_UNDERRUN", 1426 "reserved", 1427 "reserved", 1428 "NOT_ACCESSED", 1429 "NOT_ACCESSED", 1430 }; 1431 #endif 1432 1433 void 1434 ohci_softintr(void *v) 1435 { 1436 struct usbd_bus *bus = v; 1437 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1438 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1439 ohci_soft_td_t *std, *sdone, *stdnext; 1440 struct usbd_xfer *xfer; 1441 struct ohci_pipe *opipe; 1442 int len, cc; 1443 int i, j, actlen, iframes, uedir; 1444 ohci_physaddr_t done; 1445 1446 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1447 1448 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1449 1450 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1451 sizeof(sc->sc_hcca->hcca_done_head), 1452 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1453 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1454 sc->sc_hcca->hcca_done_head = 0; 1455 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1456 sizeof(sc->sc_hcca->hcca_done_head), 1457 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1458 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1459 sc->sc_eintrs |= OHCI_WDH; 1460 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1461 1462 /* Reverse the done list. */ 1463 for (sdone = NULL, sidone = NULL; done != 0; ) { 1464 std = ohci_hash_find_td(sc, done); 1465 if (std != NULL) { 1466 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1467 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1468 std->dnext = sdone; 1469 done = O32TOH(std->td.td_nexttd); 1470 sdone = std; 1471 DPRINTFN(10, "add TD %p", std, 0, 0, 0); 1472 continue; 1473 } 1474 sitd = ohci_hash_find_itd(sc, done); 1475 if (sitd != NULL) { 1476 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1477 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1478 sitd->dnext = sidone; 1479 done = O32TOH(sitd->itd.itd_nextitd); 1480 sidone = sitd; 1481 DPRINTFN(5, "add ITD %p", sitd, 0, 0, 0); 1482 continue; 1483 } 1484 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1485 (u_long)done); 1486 break; 1487 } 1488 1489 DPRINTFN(10, "sdone=%p sidone=%p", sdone, sidone, 0, 0); 1490 DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0); 1491 #ifdef OHCI_DEBUG 1492 if (ohcidebug > 10) { 1493 for (std = sdone; std; std = std->dnext) 1494 ohci_dump_td(sc, std); 1495 } 1496 #endif 1497 DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0); 1498 1499 for (std = sdone; std; std = stdnext) { 1500 xfer = std->xfer; 1501 stdnext = std->dnext; 1502 DPRINTFN(10, "std=%p xfer=%p hcpriv=%p", std, xfer, 1503 xfer ? xfer->ux_hcpriv : 0, 0); 1504 if (xfer == NULL) { 1505 /* 1506 * xfer == NULL: There seems to be no xfer associated 1507 * with this TD. It is tailp that happened to end up on 1508 * the done queue. 1509 * Shouldn't happen, but some chips are broken(?). 1510 */ 1511 continue; 1512 } 1513 if (xfer->ux_status == USBD_CANCELLED || 1514 xfer->ux_status == USBD_TIMEOUT) { 1515 DPRINTF("cancel/timeout %p", xfer, 0, 0, 0); 1516 /* Handled by abort routine. */ 1517 continue; 1518 } 1519 callout_stop(&xfer->ux_callout); 1520 1521 len = std->len; 1522 if (std->td.td_cbp != 0) 1523 len -= O32TOH(std->td.td_be) - 1524 O32TOH(std->td.td_cbp) + 1; 1525 DPRINTFN(10, "len=%d, flags=0x%x", len, std->flags, 0, 0); 1526 if (std->flags & OHCI_ADD_LEN) 1527 xfer->ux_actlen += len; 1528 1529 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1530 if (cc == OHCI_CC_NO_ERROR) { 1531 if (std->flags & OHCI_CALL_DONE) { 1532 xfer->ux_status = USBD_NORMAL_COMPLETION; 1533 usb_transfer_complete(xfer); 1534 } 1535 ohci_hash_rem_td(sc, std); 1536 } else { 1537 /* 1538 * Endpoint is halted. First unlink all the TDs 1539 * belonging to the failed transfer, and then restart 1540 * the endpoint. 1541 */ 1542 ohci_soft_td_t *p, *n; 1543 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1544 1545 DPRINTFN(15, "error cc=%d", 1546 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 0, 0, 0); 1547 1548 /* remove xfer's TDs from the hash */ 1549 for (p = std; p->xfer == xfer; p = n) { 1550 n = p->nexttd; 1551 ohci_hash_rem_td(sc, p); 1552 } 1553 1554 /* clear halt */ 1555 opipe->sed->ed.ed_headp = HTOO32(p->physaddr); 1556 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1557 1558 if (cc == OHCI_CC_STALL) 1559 xfer->ux_status = USBD_STALLED; 1560 else 1561 xfer->ux_status = USBD_IOERROR; 1562 usb_transfer_complete(xfer); 1563 } 1564 } 1565 DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0); 1566 #ifdef OHCI_DEBUG 1567 if (ohcidebug > 10) { 1568 DPRINTFN(10, "ITD done", 0, 0, 0, 0); 1569 for (sitd = sidone; sitd; sitd = sitd->dnext) 1570 ohci_dump_itd(sc, sitd); 1571 } 1572 #endif 1573 DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0); 1574 1575 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1576 xfer = sitd->xfer; 1577 sitdnext = sitd->dnext; 1578 DPRINTFN(1, "sitd=%p xfer=%p hcpriv=%p", sitd, xfer, 1579 xfer ? xfer->ux_hcpriv : 0, 0); 1580 if (xfer == NULL) 1581 continue; 1582 if (xfer->ux_status == USBD_CANCELLED || 1583 xfer->ux_status == USBD_TIMEOUT) { 1584 DPRINTF("cancel/timeout %p", xfer, 0, 0, 0); 1585 /* Handled by abort routine. */ 1586 continue; 1587 } 1588 KASSERT(!sitd->isdone); 1589 #ifdef DIAGNOSTIC 1590 sitd->isdone = true; 1591 #endif 1592 if (sitd->flags & OHCI_CALL_DONE) { 1593 ohci_soft_itd_t *next; 1594 1595 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1596 opipe->isoc.inuse -= xfer->ux_nframes; 1597 uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc-> 1598 bEndpointAddress); 1599 xfer->ux_status = USBD_NORMAL_COMPLETION; 1600 actlen = 0; 1601 for (i = 0, sitd = xfer->ux_hcpriv;; 1602 sitd = next) { 1603 next = sitd->nextitd; 1604 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1605 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1606 xfer->ux_status = USBD_IOERROR; 1607 /* For input, update frlengths with actual */ 1608 /* XXX anything necessary for output? */ 1609 if (uedir == UE_DIR_IN && 1610 xfer->ux_status == USBD_NORMAL_COMPLETION) { 1611 iframes = OHCI_ITD_GET_FC(O32TOH( 1612 sitd->itd.itd_flags)); 1613 for (j = 0; j < iframes; i++, j++) { 1614 len = O16TOH(sitd-> 1615 itd.itd_offset[j]); 1616 if ((OHCI_ITD_PSW_GET_CC(len) & 1617 OHCI_CC_NOT_ACCESSED_MASK) 1618 == OHCI_CC_NOT_ACCESSED) 1619 len = 0; 1620 else 1621 len = OHCI_ITD_PSW_LENGTH(len); 1622 xfer->ux_frlengths[i] = len; 1623 actlen += len; 1624 } 1625 } 1626 if (sitd->flags & OHCI_CALL_DONE) 1627 break; 1628 ohci_hash_rem_itd(sc, sitd); 1629 1630 } 1631 ohci_hash_rem_itd(sc, sitd); 1632 if (uedir == UE_DIR_IN && 1633 xfer->ux_status == USBD_NORMAL_COMPLETION) 1634 xfer->ux_actlen = actlen; 1635 xfer->ux_hcpriv = NULL; 1636 1637 usb_transfer_complete(xfer); 1638 } 1639 } 1640 1641 if (sc->sc_softwake) { 1642 sc->sc_softwake = 0; 1643 cv_broadcast(&sc->sc_softwake_cv); 1644 } 1645 1646 DPRINTFN(10, "done", 0, 0, 0, 0); 1647 } 1648 1649 void 1650 ohci_device_ctrl_done(struct usbd_xfer *xfer) 1651 { 1652 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1653 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1654 int len = UGETW(xfer->ux_request.wLength); 1655 int isread = (xfer->ux_request.bmRequestType & UT_READ); 1656 1657 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1658 DPRINTFN(10, "xfer=%p", xfer, 0, 0, 0); 1659 1660 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1661 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 1662 1663 if (len) 1664 usb_syncmem(&xfer->ux_dmabuf, 0, len, 1665 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1666 usb_syncmem(&opipe->ctrl.reqdma, 0, 1667 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1668 } 1669 1670 void 1671 ohci_device_intr_done(struct usbd_xfer *xfer) 1672 { 1673 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 1674 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1675 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1676 ohci_soft_ed_t *sed = opipe->sed; 1677 int isread = 1678 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1679 1680 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1681 DPRINTFN(10, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0); 1682 1683 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1684 1685 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1686 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1687 if (xfer->ux_pipe->up_repeat) { 1688 ohci_soft_td_t *data, *last, *tail; 1689 int len = xfer->ux_length; 1690 1691 /* Use "tail" TD and loan our first TD to next transfer */ 1692 data = opipe->tail.td; 1693 opipe->tail.td = ox->ox_stds[0]; 1694 ox->ox_stds[0] = data; 1695 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 1696 1697 tail = opipe->tail.td; /* point at sentinel */ 1698 memset(&tail->td, 0, sizeof(tail->td)); 1699 tail->nexttd = NULL; 1700 tail->xfer = NULL; 1701 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 1702 BUS_DMASYNC_PREWRITE); 1703 1704 /* We want interrupt at the end of the transfer. */ 1705 last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 1706 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 1707 1708 last->td.td_nexttd = HTOO32(tail->physaddr); 1709 last->nexttd = tail; 1710 last->flags |= OHCI_CALL_DONE; 1711 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 1712 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1713 1714 xfer->ux_hcpriv = data; 1715 xfer->ux_actlen = 0; 1716 1717 /* Insert ED in schedule */ 1718 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1719 usb_syncmem(&sed->dma, 1720 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1721 sizeof(sed->ed.ed_tailp), 1722 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1723 } 1724 } 1725 1726 void 1727 ohci_device_bulk_done(struct usbd_xfer *xfer) 1728 { 1729 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1730 1731 int isread = 1732 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1733 1734 KASSERT(mutex_owned(&sc->sc_lock)); 1735 1736 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1737 DPRINTFN(10, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0); 1738 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1739 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1740 } 1741 1742 Static void 1743 ohci_rhsc_softint(void *arg) 1744 { 1745 ohci_softc_t *sc = arg; 1746 1747 mutex_enter(&sc->sc_lock); 1748 1749 ohci_rhsc(sc, sc->sc_intrxfer); 1750 1751 /* Do not allow RHSC interrupts > 1 per second */ 1752 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1753 1754 mutex_exit(&sc->sc_lock); 1755 } 1756 1757 void 1758 ohci_rhsc(ohci_softc_t *sc, struct usbd_xfer *xfer) 1759 { 1760 u_char *p; 1761 int i, m; 1762 int hstatus __unused; 1763 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1764 1765 KASSERT(mutex_owned(&sc->sc_lock)); 1766 1767 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1768 DPRINTF("sc=%p xfer=%p hstatus=0x%08x", sc, xfer, hstatus, 0); 1769 1770 if (xfer == NULL) { 1771 /* Just ignore the change. */ 1772 return; 1773 } 1774 1775 p = xfer->ux_buf; 1776 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 1777 memset(p, 0, xfer->ux_length); 1778 for (i = 1; i <= m; i++) { 1779 /* Pick out CHANGE bits from the status reg. */ 1780 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1781 p[i/8] |= 1 << (i%8); 1782 } 1783 DPRINTF("change=0x%02x", *p, 0, 0, 0); 1784 xfer->ux_actlen = xfer->ux_length; 1785 xfer->ux_status = USBD_NORMAL_COMPLETION; 1786 1787 usb_transfer_complete(xfer); 1788 } 1789 1790 void 1791 ohci_root_intr_done(struct usbd_xfer *xfer) 1792 { 1793 } 1794 1795 /* 1796 * Wait here until controller claims to have an interrupt. 1797 * Then call ohci_intr and return. Use timeout to avoid waiting 1798 * too long. 1799 */ 1800 void 1801 ohci_waitintr(ohci_softc_t *sc, struct usbd_xfer *xfer) 1802 { 1803 int timo; 1804 uint32_t intrs; 1805 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1806 1807 mutex_enter(&sc->sc_lock); 1808 1809 xfer->ux_status = USBD_IN_PROGRESS; 1810 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1811 usb_delay_ms(&sc->sc_bus, 1); 1812 if (sc->sc_dying) 1813 break; 1814 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 1815 DPRINTFN(15, "intrs 0x%04x", intrs, 0, 0, 0); 1816 #ifdef OHCI_DEBUG 1817 if (ohcidebug > 15) 1818 ohci_dumpregs(sc); 1819 #endif 1820 if (intrs) { 1821 mutex_spin_enter(&sc->sc_intr_lock); 1822 ohci_intr1(sc); 1823 mutex_spin_exit(&sc->sc_intr_lock); 1824 if (xfer->ux_status != USBD_IN_PROGRESS) 1825 goto done; 1826 } 1827 } 1828 1829 /* Timeout */ 1830 DPRINTF("timeout", 0, 0, 0, 0); 1831 xfer->ux_status = USBD_TIMEOUT; 1832 usb_transfer_complete(xfer); 1833 1834 done: 1835 mutex_exit(&sc->sc_lock); 1836 } 1837 1838 void 1839 ohci_poll(struct usbd_bus *bus) 1840 { 1841 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1842 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1843 1844 #ifdef OHCI_DEBUG 1845 static int last; 1846 int new; 1847 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1848 if (new != last) { 1849 DPRINTFN(10, "intrs=0x%04x", new, 0, 0, 0); 1850 last = new; 1851 } 1852 #endif 1853 sc->sc_eintrs |= OHCI_WDH; 1854 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1855 mutex_spin_enter(&sc->sc_intr_lock); 1856 ohci_intr1(sc); 1857 mutex_spin_exit(&sc->sc_intr_lock); 1858 } 1859 } 1860 1861 /* 1862 * Add an ED to the schedule. Called with USB lock held. 1863 */ 1864 Static void 1865 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1866 { 1867 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1868 DPRINTFN(8, "sed=%p head=%p", sed, head, 0, 0); 1869 1870 KASSERT(mutex_owned(&sc->sc_lock)); 1871 1872 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1873 sizeof(head->ed.ed_nexted), 1874 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1875 sed->next = head->next; 1876 sed->ed.ed_nexted = head->ed.ed_nexted; 1877 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1878 sizeof(sed->ed.ed_nexted), 1879 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1880 head->next = sed; 1881 head->ed.ed_nexted = HTOO32(sed->physaddr); 1882 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1883 sizeof(head->ed.ed_nexted), 1884 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1885 } 1886 1887 /* 1888 * Remove an ED from the schedule. Called with USB lock held. 1889 */ 1890 Static void 1891 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1892 { 1893 ohci_soft_ed_t *p; 1894 1895 KASSERT(mutex_owned(&sc->sc_lock)); 1896 1897 /* XXX */ 1898 for (p = head; p != NULL && p->next != sed; p = p->next) 1899 ; 1900 KASSERT(p != NULL); 1901 1902 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1903 sizeof(sed->ed.ed_nexted), 1904 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1905 p->next = sed->next; 1906 p->ed.ed_nexted = sed->ed.ed_nexted; 1907 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1908 sizeof(p->ed.ed_nexted), 1909 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1910 } 1911 1912 /* 1913 * When a transfer is completed the TD is added to the done queue by 1914 * the host controller. This queue is the processed by software. 1915 * Unfortunately the queue contains the physical address of the TD 1916 * and we have no simple way to translate this back to a kernel address. 1917 * To make the translation possible (and fast) we use a hash table of 1918 * TDs currently in the schedule. The physical address is used as the 1919 * hash value. 1920 */ 1921 1922 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1923 /* Called with USB lock held. */ 1924 void 1925 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1926 { 1927 int h = HASH(std->physaddr); 1928 1929 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1930 1931 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1932 } 1933 1934 /* Called with USB lock held. */ 1935 void 1936 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1937 { 1938 1939 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1940 1941 LIST_REMOVE(std, hnext); 1942 } 1943 1944 ohci_soft_td_t * 1945 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1946 { 1947 int h = HASH(a); 1948 ohci_soft_td_t *std; 1949 1950 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1951 std != NULL; 1952 std = LIST_NEXT(std, hnext)) 1953 if (std->physaddr == a) 1954 return std; 1955 return NULL; 1956 } 1957 1958 /* Called with USB lock held. */ 1959 void 1960 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1961 { 1962 int h = HASH(sitd->physaddr); 1963 1964 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1965 1966 KASSERT(mutex_owned(&sc->sc_lock)); 1967 1968 DPRINTFN(10, "sitd=%p physaddr=0x%08lx", sitd, (u_long)sitd->physaddr, 1969 0, 0); 1970 1971 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1972 } 1973 1974 /* Called with USB lock held. */ 1975 void 1976 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1977 { 1978 1979 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1980 1981 KASSERT(mutex_owned(&sc->sc_lock)); 1982 1983 DPRINTFN(10, "sitd=%p physaddr=0x%08lx", sitd, (u_long)sitd->physaddr, 1984 0, 0); 1985 1986 LIST_REMOVE(sitd, hnext); 1987 } 1988 1989 ohci_soft_itd_t * 1990 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1991 { 1992 int h = HASH(a); 1993 ohci_soft_itd_t *sitd; 1994 1995 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1996 sitd != NULL; 1997 sitd = LIST_NEXT(sitd, hnext)) 1998 if (sitd->physaddr == a) 1999 return sitd; 2000 return NULL; 2001 } 2002 2003 void 2004 ohci_timeout(void *addr) 2005 { 2006 struct usbd_xfer *xfer = addr; 2007 struct ohci_xfer *oxfer = OHCI_XFER2OXFER(xfer); 2008 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2009 2010 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2011 DPRINTF("oxfer=%p", oxfer, 0, 0, 0); 2012 2013 if (sc->sc_dying) { 2014 mutex_enter(&sc->sc_lock); 2015 ohci_abort_xfer(xfer, USBD_TIMEOUT); 2016 mutex_exit(&sc->sc_lock); 2017 return; 2018 } 2019 2020 /* Execute the abort in a process context. */ 2021 usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr, 2022 USB_TASKQ_MPSAFE); 2023 usb_add_task(xfer->ux_pipe->up_dev, &oxfer->abort_task, 2024 USB_TASKQ_HC); 2025 } 2026 2027 void 2028 ohci_timeout_task(void *addr) 2029 { 2030 struct usbd_xfer *xfer = addr; 2031 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2032 2033 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2034 2035 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2036 2037 mutex_enter(&sc->sc_lock); 2038 ohci_abort_xfer(xfer, USBD_TIMEOUT); 2039 mutex_exit(&sc->sc_lock); 2040 } 2041 2042 #ifdef OHCI_DEBUG 2043 void 2044 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 2045 { 2046 for (; std; std = std->nexttd) { 2047 ohci_dump_td(sc, std); 2048 KASSERTMSG(std->nexttd == NULL || std != std->nexttd, 2049 "std %p next %p", std, std->nexttd); 2050 } 2051 } 2052 2053 void 2054 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 2055 { 2056 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2057 2058 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2059 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2060 2061 uint32_t flags = O32TOH(std->td.td_flags); 2062 DPRINTF("TD(%p) at %08lx:", std, (u_long)std->physaddr, 0, 0); 2063 DPRINTF(" round=%d DP=%x DI=%x T=%x", 2064 !!(flags & OHCI_TD_R), 2065 __SHIFTOUT(flags, OHCI_TD_DP_MASK), 2066 OHCI_TD_GET_DI(flags), 2067 __SHIFTOUT(flags, OHCI_TD_TOGGLE_MASK)); 2068 DPRINTF(" EC=%d CC=%d", OHCI_TD_GET_EC(flags), OHCI_TD_GET_CC(flags), 2069 0, 0); 2070 DPRINTF(" cbp=0x%08lx nexttd=0x%08lx be=0x%08lx", 2071 (u_long)O32TOH(std->td.td_cbp), 2072 (u_long)O32TOH(std->td.td_nexttd), 2073 (u_long)O32TOH(std->td.td_be), 0); 2074 } 2075 2076 void 2077 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2078 { 2079 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2080 2081 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 2082 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2083 2084 uint32_t flags = O32TOH(sitd->itd.itd_flags); 2085 DPRINTF("ITD(%p) at %08lx", sitd, (u_long)sitd->physaddr, 0, 0); 2086 DPRINTF(" sf=%d di=%d fc=%d cc=%d", 2087 OHCI_ITD_GET_SF(flags), OHCI_ITD_GET_DI(flags), 2088 OHCI_ITD_GET_FC(flags), OHCI_ITD_GET_CC(flags)); 2089 DPRINTF(" bp0=0x%08x next=0x%08x be=0x%08x", 2090 O32TOH(sitd->itd.itd_bp0), 2091 O32TOH(sitd->itd.itd_nextitd), 2092 O32TOH(sitd->itd.itd_be), 0); 2093 CTASSERT(OHCI_ITD_NOFFSET == 8); 2094 DPRINTF(" offs[0] = 0x%04x offs[1] = 0x%04x " 2095 "offs[2] = 0x%04x offs[3] = 0x%04x", 2096 O16TOH(sitd->itd.itd_offset[0]), 2097 O16TOH(sitd->itd.itd_offset[1]), 2098 O16TOH(sitd->itd.itd_offset[2]), 2099 O16TOH(sitd->itd.itd_offset[3])); 2100 DPRINTF(" offs[4] = 0x%04x offs[5] = 0x%04x " 2101 "offs[6] = 0x%04x offs[7] = 0x%04x", 2102 O16TOH(sitd->itd.itd_offset[4]), 2103 O16TOH(sitd->itd.itd_offset[5]), 2104 O16TOH(sitd->itd.itd_offset[6]), 2105 O16TOH(sitd->itd.itd_offset[7])); 2106 } 2107 2108 void 2109 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2110 { 2111 for (; sitd; sitd = sitd->nextitd) 2112 ohci_dump_itd(sc, sitd); 2113 } 2114 2115 void 2116 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2117 { 2118 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2119 2120 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2121 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2122 2123 uint32_t flags = O32TOH(sed->ed.ed_flags); 2124 DPRINTF("ED(%p) at 0x%08lx:", sed, sed->physaddr, 0, 0); 2125 DPRINTF(" addr=%d endpt=%d maxp=%d", 2126 OHCI_ED_GET_FA(flags), 2127 OHCI_ED_GET_EN(flags), 2128 OHCI_ED_GET_MAXP(flags), 2129 0); 2130 DPRINTF(" dir=%d speed=%d skip=%d iso=%d", 2131 __SHIFTOUT(flags, OHCI_ED_DIR_MASK), 2132 !!(flags & OHCI_ED_SPEED), 2133 !!(flags & OHCI_ED_SKIP), 2134 !!(flags & OHCI_ED_FORMAT_ISO)); 2135 DPRINTF(" tailp=0x%08lx", (u_long)O32TOH(sed->ed.ed_tailp), 2136 0, 0, 0); 2137 DPRINTF(" headp=0x%08lx nexted=0x%08lx halted=%d carry=%d", 2138 O32TOH(sed->ed.ed_headp), O32TOH(sed->ed.ed_nexted), 2139 !!(O32TOH(sed->ed.ed_headp) & OHCI_HALTED), 2140 !!(O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 2141 } 2142 #endif 2143 2144 usbd_status 2145 ohci_open(struct usbd_pipe *pipe) 2146 { 2147 struct usbd_device *dev = pipe->up_dev; 2148 struct usbd_bus *bus = dev->ud_bus; 2149 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2150 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 2151 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2152 uint8_t addr = dev->ud_addr; 2153 uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2154 ohci_soft_ed_t *sed; 2155 ohci_soft_td_t *std; 2156 ohci_soft_itd_t *sitd; 2157 ohci_physaddr_t tdphys; 2158 uint32_t fmt; 2159 usbd_status err = USBD_NOMEM; 2160 int ival; 2161 2162 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2163 DPRINTFN(1, "pipe=%p, addr=%d, endpt=%d (%d)", pipe, addr, 2164 ed->bEndpointAddress, bus->ub_rhaddr); 2165 2166 if (sc->sc_dying) { 2167 return USBD_IOERROR; 2168 } 2169 2170 std = NULL; 2171 sed = NULL; 2172 2173 if (addr == bus->ub_rhaddr) { 2174 switch (ed->bEndpointAddress) { 2175 case USB_CONTROL_ENDPOINT: 2176 pipe->up_methods = &roothub_ctrl_methods; 2177 break; 2178 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 2179 pipe->up_methods = &ohci_root_intr_methods; 2180 break; 2181 default: 2182 err = USBD_INVAL; 2183 goto bad; 2184 } 2185 } else { 2186 sed = ohci_alloc_sed(sc); 2187 if (sed == NULL) 2188 goto bad; 2189 opipe->sed = sed; 2190 if (xfertype == UE_ISOCHRONOUS) { 2191 sitd = ohci_alloc_sitd(sc); 2192 if (sitd == NULL) 2193 goto bad; 2194 2195 opipe->tail.itd = sitd; 2196 tdphys = sitd->physaddr; 2197 fmt = OHCI_ED_FORMAT_ISO; 2198 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2199 fmt |= OHCI_ED_DIR_IN; 2200 else 2201 fmt |= OHCI_ED_DIR_OUT; 2202 } else { 2203 std = ohci_alloc_std(sc); 2204 if (std == NULL) 2205 goto bad; 2206 2207 opipe->tail.td = std; 2208 tdphys = std->physaddr; 2209 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2210 } 2211 sed->ed.ed_flags = HTOO32( 2212 OHCI_ED_SET_FA(addr) | 2213 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2214 (dev->ud_speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2215 fmt | 2216 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2217 sed->ed.ed_headp = HTOO32(tdphys | 2218 (pipe->up_endpoint->ue_toggle ? OHCI_TOGGLECARRY : 0)); 2219 sed->ed.ed_tailp = HTOO32(tdphys); 2220 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2221 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2222 2223 switch (xfertype) { 2224 case UE_CONTROL: 2225 pipe->up_methods = &ohci_device_ctrl_methods; 2226 err = usb_allocmem(&sc->sc_bus, 2227 sizeof(usb_device_request_t), 2228 0, &opipe->ctrl.reqdma); 2229 if (err) 2230 goto bad; 2231 mutex_enter(&sc->sc_lock); 2232 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2233 mutex_exit(&sc->sc_lock); 2234 break; 2235 case UE_INTERRUPT: 2236 pipe->up_methods = &ohci_device_intr_methods; 2237 ival = pipe->up_interval; 2238 if (ival == USBD_DEFAULT_INTERVAL) 2239 ival = ed->bInterval; 2240 err = ohci_device_setintr(sc, opipe, ival); 2241 if (err) 2242 goto bad; 2243 break; 2244 case UE_ISOCHRONOUS: 2245 pipe->up_methods = &ohci_device_isoc_methods; 2246 return ohci_setup_isoc(pipe); 2247 case UE_BULK: 2248 pipe->up_methods = &ohci_device_bulk_methods; 2249 mutex_enter(&sc->sc_lock); 2250 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2251 mutex_exit(&sc->sc_lock); 2252 break; 2253 } 2254 } 2255 2256 return USBD_NORMAL_COMPLETION; 2257 2258 bad: 2259 if (std != NULL) { 2260 ohci_free_std(sc, std); 2261 } 2262 if (sed != NULL) 2263 ohci_free_sed(sc, sed); 2264 return err; 2265 2266 } 2267 2268 /* 2269 * Close a reqular pipe. 2270 * Assumes that there are no pending transactions. 2271 */ 2272 void 2273 ohci_close_pipe(struct usbd_pipe *pipe, ohci_soft_ed_t *head) 2274 { 2275 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2276 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2277 ohci_soft_ed_t *sed = opipe->sed; 2278 2279 KASSERT(mutex_owned(&sc->sc_lock)); 2280 2281 #ifdef DIAGNOSTIC 2282 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2283 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2284 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2285 ohci_soft_td_t *std; 2286 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2287 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2288 "tl=0x%x pipe=%p, std=%p\n", sed, 2289 (int)O32TOH(sed->ed.ed_headp), 2290 (int)O32TOH(sed->ed.ed_tailp), 2291 pipe, std); 2292 #ifdef OHCI_DEBUG 2293 usbd_dump_pipe(&opipe->pipe); 2294 ohci_dump_ed(sc, sed); 2295 if (std) 2296 ohci_dump_td(sc, std); 2297 #endif 2298 usb_delay_ms(&sc->sc_bus, 2); 2299 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2300 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2301 printf("ohci_close_pipe: pipe still not empty\n"); 2302 } 2303 #endif 2304 ohci_rem_ed(sc, sed, head); 2305 /* Make sure the host controller is not touching this ED */ 2306 usb_delay_ms(&sc->sc_bus, 1); 2307 pipe->up_endpoint->ue_toggle = 2308 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2309 ohci_free_sed_locked(sc, opipe->sed); 2310 } 2311 2312 /* 2313 * Abort a device request. 2314 * If this routine is called at splusb() it guarantees that the request 2315 * will be removed from the hardware scheduling and that the callback 2316 * for it will be called with USBD_CANCELLED status. 2317 * It's impossible to guarantee that the requested transfer will not 2318 * have happened since the hardware runs concurrently. 2319 * If the transaction has already happened we rely on the ordinary 2320 * interrupt processing to process it. 2321 * XXX This is most probably wrong. 2322 * XXXMRG this doesn't make sense anymore. 2323 */ 2324 void 2325 ohci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2326 { 2327 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2328 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2329 ohci_soft_ed_t *sed = opipe->sed; 2330 ohci_soft_td_t *p, *n; 2331 ohci_physaddr_t headp; 2332 int hit; 2333 int wake; 2334 2335 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2336 DPRINTF("xfer=%p pipe=%p sed=%p", xfer, opipe,sed, 0); 2337 2338 KASSERT(mutex_owned(&sc->sc_lock)); 2339 ASSERT_SLEEPABLE(); 2340 2341 if (sc->sc_dying) { 2342 /* If we're dying, just do the software part. */ 2343 xfer->ux_status = status; /* make software ignore it */ 2344 callout_halt(&xfer->ux_callout, &sc->sc_lock); 2345 usb_transfer_complete(xfer); 2346 return; 2347 } 2348 2349 /* 2350 * If an abort is already in progress then just wait for it to 2351 * complete and return. 2352 */ 2353 if (xfer->ux_hcflags & UXFER_ABORTING) { 2354 DPRINTFN(2, "already aborting", 0, 0, 0, 0); 2355 #ifdef DIAGNOSTIC 2356 if (status == USBD_TIMEOUT) 2357 printf("%s: TIMEOUT while aborting\n", __func__); 2358 #endif 2359 /* Override the status which might be USBD_TIMEOUT. */ 2360 xfer->ux_status = status; 2361 DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0); 2362 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2363 while (xfer->ux_hcflags & UXFER_ABORTING) 2364 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2365 goto done; 2366 } 2367 xfer->ux_hcflags |= UXFER_ABORTING; 2368 2369 /* 2370 * Step 1: Make interrupt routine and hardware ignore xfer. 2371 */ 2372 xfer->ux_status = status; /* make software ignore it */ 2373 callout_stop(&xfer->ux_callout); 2374 DPRINTFN(1, "stop ed=%p", sed, 0, 0, 0); 2375 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2376 sizeof(sed->ed.ed_flags), 2377 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2378 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2379 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2380 sizeof(sed->ed.ed_flags), 2381 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2382 2383 /* 2384 * Step 2: Wait until we know hardware has finished any possible 2385 * use of the xfer. Also make sure the soft interrupt routine 2386 * has run. 2387 */ 2388 /* Hardware finishes in 1ms */ 2389 usb_delay_ms_locked(opipe->pipe.up_dev->ud_bus, 20, &sc->sc_lock); 2390 sc->sc_softwake = 1; 2391 usb_schedsoftintr(&sc->sc_bus); 2392 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2393 2394 /* 2395 * Step 3: Remove any vestiges of the xfer from the hardware. 2396 * The complication here is that the hardware may have executed 2397 * beyond the xfer we're trying to abort. So as we're scanning 2398 * the TDs of this xfer we check if the hardware points to 2399 * any of them. 2400 */ 2401 p = xfer->ux_hcpriv; 2402 KASSERT(p); 2403 2404 #ifdef OHCI_DEBUG 2405 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2406 2407 if (ohcidebug > 1) { 2408 DPRINTF("sed:", 0, 0, 0, 0); 2409 ohci_dump_ed(sc, sed); 2410 ohci_dump_tds(sc, p); 2411 } 2412 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2413 #endif 2414 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2415 hit = 0; 2416 for (; p->xfer == xfer; p = n) { 2417 hit |= headp == p->physaddr; 2418 n = p->nexttd; 2419 ohci_hash_rem_td(sc, p); 2420 } 2421 /* Zap headp register if hardware pointed inside the xfer. */ 2422 if (hit) { 2423 DPRINTFN(1, "set hd=0x%08x, tl=0x%08x", (int)p->physaddr, 2424 (int)O32TOH(sed->ed.ed_tailp), 0, 0); 2425 sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */ 2426 usb_syncmem(&sed->dma, 2427 sed->offs + offsetof(ohci_ed_t, ed_headp), 2428 sizeof(sed->ed.ed_headp), 2429 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2430 } else { 2431 DPRINTFN(1, "no hit", 0, 0, 0, 0); 2432 } 2433 2434 /* 2435 * Step 4: Turn on hardware again. 2436 */ 2437 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2438 sizeof(sed->ed.ed_flags), 2439 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2440 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2441 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2442 sizeof(sed->ed.ed_flags), 2443 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2444 2445 /* 2446 * Step 5: Execute callback. 2447 */ 2448 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2449 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2450 usb_transfer_complete(xfer); 2451 if (wake) 2452 cv_broadcast(&xfer->ux_hccv); 2453 2454 done: 2455 KASSERT(mutex_owned(&sc->sc_lock)); 2456 } 2457 2458 /* 2459 * Data structures and routines to emulate the root hub. 2460 */ 2461 Static int 2462 ohci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2463 void *buf, int buflen) 2464 { 2465 ohci_softc_t *sc = OHCI_BUS2SC(bus); 2466 usb_port_status_t ps; 2467 uint16_t len, value, index; 2468 int l, totlen = 0; 2469 int port, i; 2470 uint32_t v; 2471 2472 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2473 2474 if (sc->sc_dying) 2475 return -1; 2476 2477 DPRINTFN(4, "type=0x%02x request=%02x", req->bmRequestType, 2478 req->bRequest, 0, 0); 2479 2480 len = UGETW(req->wLength); 2481 value = UGETW(req->wValue); 2482 index = UGETW(req->wIndex); 2483 2484 #define C(x,y) ((x) | ((y) << 8)) 2485 switch (C(req->bRequest, req->bmRequestType)) { 2486 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2487 DPRINTFN(8, "wValue=0x%04x", value, 0, 0, 0); 2488 if (len == 0) 2489 break; 2490 switch (value) { 2491 case C(0, UDESC_DEVICE): { 2492 usb_device_descriptor_t devd; 2493 2494 totlen = min(buflen, sizeof(devd)); 2495 memcpy(&devd, buf, totlen); 2496 USETW(devd.idVendor, sc->sc_id_vendor); 2497 memcpy(buf, &devd, totlen); 2498 break; 2499 } 2500 case C(1, UDESC_STRING): 2501 #define sd ((usb_string_descriptor_t *)buf) 2502 /* Vendor */ 2503 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2504 break; 2505 case C(2, UDESC_STRING): 2506 /* Product */ 2507 totlen = usb_makestrdesc(sd, len, "OHCI root hub"); 2508 break; 2509 #undef sd 2510 default: 2511 /* default from usbroothub */ 2512 return buflen; 2513 } 2514 break; 2515 2516 /* Hub requests */ 2517 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2518 break; 2519 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2520 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 2521 index, value, 0, 0); 2522 if (index < 1 || index > sc->sc_noport) { 2523 return -1; 2524 } 2525 port = OHCI_RH_PORT_STATUS(index); 2526 switch(value) { 2527 case UHF_PORT_ENABLE: 2528 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2529 break; 2530 case UHF_PORT_SUSPEND: 2531 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2532 break; 2533 case UHF_PORT_POWER: 2534 /* Yes, writing to the LOW_SPEED bit clears power. */ 2535 OWRITE4(sc, port, UPS_LOW_SPEED); 2536 break; 2537 case UHF_C_PORT_CONNECTION: 2538 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2539 break; 2540 case UHF_C_PORT_ENABLE: 2541 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2542 break; 2543 case UHF_C_PORT_SUSPEND: 2544 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2545 break; 2546 case UHF_C_PORT_OVER_CURRENT: 2547 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2548 break; 2549 case UHF_C_PORT_RESET: 2550 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2551 break; 2552 default: 2553 return -1; 2554 } 2555 switch(value) { 2556 case UHF_C_PORT_CONNECTION: 2557 case UHF_C_PORT_ENABLE: 2558 case UHF_C_PORT_SUSPEND: 2559 case UHF_C_PORT_OVER_CURRENT: 2560 case UHF_C_PORT_RESET: 2561 /* Enable RHSC interrupt if condition is cleared. */ 2562 if ((OREAD4(sc, port) >> 16) == 0) 2563 ohci_rhsc_enable(sc); 2564 break; 2565 default: 2566 break; 2567 } 2568 break; 2569 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2570 if (len == 0) 2571 break; 2572 if ((value & 0xff) != 0) { 2573 return -1; 2574 } 2575 usb_hub_descriptor_t hubd; 2576 2577 totlen = min(buflen, sizeof(hubd)); 2578 memcpy(&hubd, buf, totlen); 2579 2580 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2581 hubd.bNbrPorts = sc->sc_noport; 2582 USETW(hubd.wHubCharacteristics, 2583 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2584 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2585 /* XXX overcurrent */ 2586 ); 2587 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2588 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2589 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2590 hubd.DeviceRemovable[i++] = (uint8_t)v; 2591 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2592 totlen = min(totlen, hubd.bDescLength); 2593 memcpy(buf, &hubd, totlen); 2594 break; 2595 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2596 if (len != 4) { 2597 return -1; 2598 } 2599 memset(buf, 0, len); /* ? XXX */ 2600 totlen = len; 2601 break; 2602 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2603 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 2604 if (index < 1 || index > sc->sc_noport) { 2605 return -1; 2606 } 2607 if (len != 4) { 2608 return -1; 2609 } 2610 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2611 DPRINTFN(8, "port status=0x%04x", v, 0, 0, 0); 2612 USETW(ps.wPortStatus, v); 2613 USETW(ps.wPortChange, v >> 16); 2614 totlen = min(len, sizeof(ps)); 2615 memcpy(buf, &ps, totlen); 2616 break; 2617 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2618 return -1; 2619 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2620 break; 2621 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2622 if (index < 1 || index > sc->sc_noport) { 2623 return -1; 2624 } 2625 port = OHCI_RH_PORT_STATUS(index); 2626 switch(value) { 2627 case UHF_PORT_ENABLE: 2628 OWRITE4(sc, port, UPS_PORT_ENABLED); 2629 break; 2630 case UHF_PORT_SUSPEND: 2631 OWRITE4(sc, port, UPS_SUSPEND); 2632 break; 2633 case UHF_PORT_RESET: 2634 DPRINTFN(5, "reset port %d", index, 0, 0, 0); 2635 OWRITE4(sc, port, UPS_RESET); 2636 for (i = 0; i < 5; i++) { 2637 usb_delay_ms(&sc->sc_bus, 2638 USB_PORT_ROOT_RESET_DELAY); 2639 if (sc->sc_dying) { 2640 return -1; 2641 } 2642 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2643 break; 2644 } 2645 DPRINTFN(8, "port %d reset, status = 0x%04x", index, 2646 OREAD4(sc, port), 0, 0); 2647 break; 2648 case UHF_PORT_POWER: 2649 DPRINTFN(2, "set port power %d", index, 0, 0, 0); 2650 OWRITE4(sc, port, UPS_PORT_POWER); 2651 break; 2652 default: 2653 return -1; 2654 } 2655 break; 2656 default: 2657 /* default from usbroothub */ 2658 return buflen; 2659 } 2660 2661 return totlen; 2662 } 2663 2664 Static usbd_status 2665 ohci_root_intr_transfer(struct usbd_xfer *xfer) 2666 { 2667 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2668 usbd_status err; 2669 2670 /* Insert last in queue. */ 2671 mutex_enter(&sc->sc_lock); 2672 err = usb_insert_transfer(xfer); 2673 mutex_exit(&sc->sc_lock); 2674 if (err) 2675 return err; 2676 2677 /* Pipe isn't running, start first */ 2678 return ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2679 } 2680 2681 Static usbd_status 2682 ohci_root_intr_start(struct usbd_xfer *xfer) 2683 { 2684 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2685 2686 if (sc->sc_dying) 2687 return USBD_IOERROR; 2688 2689 mutex_enter(&sc->sc_lock); 2690 KASSERT(sc->sc_intrxfer == NULL); 2691 sc->sc_intrxfer = xfer; 2692 mutex_exit(&sc->sc_lock); 2693 2694 return USBD_IN_PROGRESS; 2695 } 2696 2697 /* Abort a root interrupt request. */ 2698 Static void 2699 ohci_root_intr_abort(struct usbd_xfer *xfer) 2700 { 2701 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2702 2703 KASSERT(mutex_owned(&sc->sc_lock)); 2704 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2705 2706 sc->sc_intrxfer = NULL; 2707 2708 xfer->ux_status = USBD_CANCELLED; 2709 usb_transfer_complete(xfer); 2710 } 2711 2712 /* Close the root pipe. */ 2713 Static void 2714 ohci_root_intr_close(struct usbd_pipe *pipe) 2715 { 2716 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2717 2718 KASSERT(mutex_owned(&sc->sc_lock)); 2719 2720 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2721 2722 sc->sc_intrxfer = NULL; 2723 } 2724 2725 /************************/ 2726 2727 int 2728 ohci_device_ctrl_init(struct usbd_xfer *xfer) 2729 { 2730 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2731 usb_device_request_t *req = &xfer->ux_request; 2732 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2733 ohci_soft_td_t *stat, *tail; 2734 int isread = req->bmRequestType & UT_READ; 2735 int len = xfer->ux_bufsize; 2736 int err = ENOMEM; 2737 2738 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2739 2740 /* The TD for setup will be a 'tail' from elsewhere */ 2741 stat = ohci_alloc_std(sc); 2742 if (stat == NULL) { 2743 goto bad1; 2744 } 2745 tail = ohci_alloc_std(sc); 2746 if (tail == NULL) { 2747 goto bad2; 2748 } 2749 tail->xfer = NULL; 2750 2751 ox->ox_stat = stat; 2752 ox->ox_tdtail = tail; 2753 ox->ox_nstd = 0; 2754 2755 /* Set up data transaction */ 2756 if (len != 0) { 2757 err = ohci_alloc_std_chain(sc, xfer, len, isread); 2758 if (err) { 2759 goto bad3; 2760 } 2761 } 2762 return 0; 2763 2764 bad3: 2765 ohci_free_std(sc, tail); 2766 bad2: 2767 ohci_free_std(sc, stat); 2768 bad1: 2769 return err; 2770 } 2771 2772 void 2773 ohci_device_ctrl_fini(struct usbd_xfer *xfer) 2774 { 2775 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2776 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2777 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2778 2779 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2780 DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0); 2781 2782 mutex_enter(&sc->sc_lock); 2783 if (ox->ox_tdtail != opipe->tail.td) { 2784 ohci_free_std_locked(sc, ox->ox_tdtail); 2785 } 2786 for (size_t i = 0; i < ox->ox_nstd; i++) { 2787 ohci_soft_td_t *std = ox->ox_stds[i]; 2788 if (std == NULL) 2789 break; 2790 ohci_free_std_locked(sc, std); 2791 } 2792 ohci_free_std_locked(sc, ox->ox_stat); 2793 mutex_exit(&sc->sc_lock); 2794 2795 if (ox->ox_nstd) { 2796 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 2797 kmem_free(ox->ox_stds, sz); 2798 } 2799 } 2800 2801 Static usbd_status 2802 ohci_device_ctrl_transfer(struct usbd_xfer *xfer) 2803 { 2804 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2805 usbd_status err; 2806 2807 /* Insert last in queue. */ 2808 mutex_enter(&sc->sc_lock); 2809 err = usb_insert_transfer(xfer); 2810 mutex_exit(&sc->sc_lock); 2811 if (err) 2812 return err; 2813 2814 /* Pipe isn't running, start first */ 2815 return ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2816 } 2817 2818 Static usbd_status 2819 ohci_device_ctrl_start(struct usbd_xfer *xfer) 2820 { 2821 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2822 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2823 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2824 usb_device_request_t *req = &xfer->ux_request; 2825 struct usbd_device *dev __diagused = opipe->pipe.up_dev; 2826 ohci_soft_td_t *setup, *stat, *next, *tail; 2827 ohci_soft_ed_t *sed; 2828 int isread; 2829 int len; 2830 2831 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2832 2833 if (sc->sc_dying) 2834 return USBD_IOERROR; 2835 2836 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2837 2838 isread = req->bmRequestType & UT_READ; 2839 len = UGETW(req->wLength); 2840 2841 DPRINTF("type=0x%02x, request=0x%02x, " 2842 "wValue=0x%04x, wIndex=0x%04x", 2843 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2844 UGETW(req->wIndex)); 2845 DPRINTF("len=%d, addr=%d, endpt=%d", 2846 len, dev->ud_addr, 2847 opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 2848 2849 /* Need to take lock here for pipe->tail.td */ 2850 mutex_enter(&sc->sc_lock); 2851 2852 setup = opipe->tail.td; 2853 stat = ox->ox_stat; 2854 tail = ox->ox_tdtail; 2855 opipe->tail.td = tail; 2856 2857 sed = opipe->sed; 2858 2859 KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->ud_addr, 2860 "address ED %d pipe %d\n", 2861 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->ud_addr); 2862 KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) == 2863 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 2864 "MPL ED %d pipe %d\n", 2865 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), 2866 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 2867 2868 /* next will point to data if len != 0 */ 2869 next = stat; 2870 2871 /* Set up data transaction */ 2872 if (len != 0) { 2873 ohci_soft_td_t *std; 2874 ohci_soft_td_t *end; 2875 2876 next = ox->ox_stds[0]; 2877 ohci_reset_std_chain(sc, xfer, len, isread, next, &end); 2878 2879 end->td.td_nexttd = HTOO32(stat->physaddr); 2880 end->nexttd = stat; 2881 2882 usb_syncmem(&end->dma, 2883 end->offs + offsetof(ohci_td_t, td_nexttd), 2884 sizeof(end->td.td_nexttd), 2885 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2886 2887 usb_syncmem(&xfer->ux_dmabuf, 0, len, 2888 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2889 std = ox->ox_stds[0]; 2890 /* Start toggle at 1 and then use the carried toggle. */ 2891 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 2892 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 2893 usb_syncmem(&std->dma, 2894 std->offs + offsetof(ohci_td_t, td_flags), 2895 sizeof(std->td.td_flags), 2896 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2897 } 2898 2899 DPRINTFN(8, "setup %p data %p stat %p tail %p", setup, 2900 (len != 0 ? ox->ox_stds[0] : NULL), stat, tail); 2901 KASSERT(opipe->tail.td == tail); 2902 2903 memcpy(KERNADDR(&opipe->ctrl.reqdma, 0), req, sizeof(*req)); 2904 usb_syncmem(&opipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2905 2906 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 2907 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 2908 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->ctrl.reqdma, 0)); 2909 setup->td.td_nexttd = HTOO32(next->physaddr); 2910 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof(*req) - 1); 2911 setup->nexttd = next; 2912 setup->len = 0; 2913 setup->xfer = xfer; 2914 setup->flags = 0; 2915 ohci_hash_add_td(sc, setup); 2916 2917 xfer->ux_hcpriv = setup; 2918 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2919 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2920 2921 stat->td.td_flags = HTOO32( 2922 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 2923 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 2924 stat->td.td_cbp = 0; 2925 stat->td.td_nexttd = HTOO32(tail->physaddr); 2926 stat->td.td_be = 0; 2927 stat->nexttd = tail; 2928 stat->flags = OHCI_CALL_DONE; 2929 stat->len = 0; 2930 stat->xfer = xfer; 2931 ohci_hash_add_td(sc, stat); 2932 2933 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2934 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2935 2936 memset(&tail->td, 0, sizeof(tail->td)); 2937 tail->nexttd = NULL; 2938 tail->xfer = NULL; 2939 2940 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 2941 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2942 2943 2944 #ifdef OHCI_DEBUG 2945 USBHIST_LOGN(ohcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2946 if (ohcidebug > 5) { 2947 ohci_dump_ed(sc, sed); 2948 ohci_dump_tds(sc, setup); 2949 } 2950 USBHIST_LOGN(ohcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2951 #endif 2952 2953 /* Insert ED in schedule */ 2954 sed->ed.ed_tailp = HTOO32(tail->physaddr); 2955 usb_syncmem(&sed->dma, 2956 sed->offs + offsetof(ohci_ed_t, ed_tailp), 2957 sizeof(sed->ed.ed_tailp), 2958 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2959 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2960 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2961 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2962 ohci_timeout, xfer); 2963 } 2964 2965 #ifdef OHCI_DEBUG 2966 DPRINTFN(20, "--- dump start ---", 0, 0, 0, 0); 2967 if (ohcidebug > 20) { 2968 delay(10000); 2969 DPRINTFN(20, "status=%x", OREAD4(sc, OHCI_COMMAND_STATUS), 2970 0, 0, 0); 2971 ohci_dumpregs(sc); 2972 DPRINTFN(20, "ctrl head:", 0, 0, 0, 0); 2973 ohci_dump_ed(sc, sc->sc_ctrl_head); 2974 DPRINTF("sed:", 0, 0, 0, 0); 2975 ohci_dump_ed(sc, sed); 2976 ohci_dump_tds(sc, setup); 2977 } 2978 DPRINTFN(20, "--- dump start ---", 0, 0, 0, 0); 2979 #endif 2980 2981 mutex_exit(&sc->sc_lock); 2982 2983 if (sc->sc_bus.ub_usepolling) 2984 ohci_waitintr(sc, xfer); 2985 2986 return USBD_IN_PROGRESS; 2987 } 2988 2989 /* Abort a device control request. */ 2990 Static void 2991 ohci_device_ctrl_abort(struct usbd_xfer *xfer) 2992 { 2993 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 2994 2995 KASSERT(mutex_owned(&sc->sc_lock)); 2996 2997 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2998 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2999 ohci_abort_xfer(xfer, USBD_CANCELLED); 3000 } 3001 3002 /* Close a device control pipe. */ 3003 Static void 3004 ohci_device_ctrl_close(struct usbd_pipe *pipe) 3005 { 3006 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3007 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3008 3009 KASSERT(mutex_owned(&sc->sc_lock)); 3010 3011 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3012 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3013 ohci_close_pipe(pipe, sc->sc_ctrl_head); 3014 ohci_free_std_locked(sc, opipe->tail.td); 3015 } 3016 3017 /************************/ 3018 3019 Static void 3020 ohci_device_clear_toggle(struct usbd_pipe *pipe) 3021 { 3022 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3023 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3024 3025 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 3026 } 3027 3028 Static void 3029 ohci_noop(struct usbd_pipe *pipe) 3030 { 3031 } 3032 3033 Static int 3034 ohci_device_bulk_init(struct usbd_xfer *xfer) 3035 { 3036 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3037 int len = xfer->ux_bufsize; 3038 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;; 3039 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3040 int err; 3041 3042 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3043 3044 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3045 3046 DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread, 3047 xfer->ux_flags); 3048 DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0); 3049 3050 /* Allocate a chain of new TDs (including a new tail). */ 3051 err = ohci_alloc_std_chain(sc, xfer, len, isread); 3052 if (err) 3053 return err; 3054 3055 return 0; 3056 } 3057 3058 Static void 3059 ohci_device_bulk_fini(struct usbd_xfer *xfer) 3060 { 3061 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3062 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3063 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3064 3065 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3066 DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0); 3067 3068 mutex_enter(&sc->sc_lock); 3069 for (size_t i = 0; i < ox->ox_nstd; i++) { 3070 ohci_soft_td_t *std = ox->ox_stds[i]; 3071 if (std == NULL) 3072 break; 3073 if (std != opipe->tail.td) 3074 ohci_free_std_locked(sc, std); 3075 } 3076 mutex_exit(&sc->sc_lock); 3077 3078 if (ox->ox_nstd) { 3079 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 3080 kmem_free(ox->ox_stds, sz); 3081 } 3082 } 3083 3084 Static usbd_status 3085 ohci_device_bulk_transfer(struct usbd_xfer *xfer) 3086 { 3087 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3088 usbd_status err; 3089 3090 /* Insert last in queue. */ 3091 mutex_enter(&sc->sc_lock); 3092 err = usb_insert_transfer(xfer); 3093 mutex_exit(&sc->sc_lock); 3094 if (err) 3095 return err; 3096 3097 /* Pipe isn't running, start first */ 3098 return ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3099 } 3100 3101 Static usbd_status 3102 ohci_device_bulk_start(struct usbd_xfer *xfer) 3103 { 3104 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3105 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3106 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3107 ohci_soft_td_t *last; 3108 ohci_soft_td_t *data, *tail, *tdp; 3109 ohci_soft_ed_t *sed; 3110 int len, isread, endpt; 3111 3112 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3113 3114 if (sc->sc_dying) 3115 return USBD_IOERROR; 3116 3117 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3118 3119 len = xfer->ux_length; 3120 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3121 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3122 sed = opipe->sed; 3123 3124 DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread, 3125 xfer->ux_flags); 3126 DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0); 3127 3128 mutex_enter(&sc->sc_lock); 3129 3130 /* Use "tail" TD and loan our first TD to next transfer */ 3131 data = opipe->tail.td; 3132 opipe->tail.td = ox->ox_stds[0]; 3133 ox->ox_stds[0] = data; 3134 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3135 3136 tail = opipe->tail.td; /* point at sentinel */ 3137 memset(&tail->td, 0, sizeof(tail->td)); 3138 tail->nexttd = NULL; 3139 tail->xfer = NULL; 3140 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3141 BUS_DMASYNC_PREWRITE); 3142 xfer->ux_hcpriv = data; 3143 3144 DPRINTFN(8, "xfer %p data %p tail %p", xfer, ox->ox_stds[0], tail, 0); 3145 KASSERT(opipe->tail.td == tail); 3146 3147 /* We want interrupt at the end of the transfer. */ 3148 last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3149 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3150 3151 last->td.td_nexttd = HTOO32(tail->physaddr); 3152 last->nexttd = tail; 3153 last->flags |= OHCI_CALL_DONE; 3154 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3155 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3156 3157 DPRINTFN(4, "ed_flags=0x%08x td_flags=0x%08x " 3158 "td_cbp=0x%08x td_be=0x%08x", 3159 (int)O32TOH(sed->ed.ed_flags), 3160 (int)O32TOH(data->td.td_flags), 3161 (int)O32TOH(data->td.td_cbp), 3162 (int)O32TOH(data->td.td_be)); 3163 3164 #ifdef OHCI_DEBUG 3165 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3166 if (ohcidebug > 5) { 3167 ohci_dump_ed(sc, sed); 3168 ohci_dump_tds(sc, data); 3169 } 3170 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3171 #endif 3172 3173 /* Insert ED in schedule */ 3174 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3175 KASSERT(tdp->xfer == xfer); 3176 } 3177 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3178 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3179 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3180 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3181 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3182 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3183 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3184 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3185 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3186 ohci_timeout, xfer); 3187 } 3188 mutex_exit(&sc->sc_lock); 3189 3190 return USBD_IN_PROGRESS; 3191 } 3192 3193 Static void 3194 ohci_device_bulk_abort(struct usbd_xfer *xfer) 3195 { 3196 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3197 3198 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3199 3200 KASSERT(mutex_owned(&sc->sc_lock)); 3201 3202 DPRINTF("xfer=%p", xfer, 0, 0, 0); 3203 ohci_abort_xfer(xfer, USBD_CANCELLED); 3204 } 3205 3206 /* 3207 * Close a device bulk pipe. 3208 */ 3209 Static void 3210 ohci_device_bulk_close(struct usbd_pipe *pipe) 3211 { 3212 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3213 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3214 3215 KASSERT(mutex_owned(&sc->sc_lock)); 3216 3217 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3218 3219 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3220 ohci_close_pipe(pipe, sc->sc_bulk_head); 3221 ohci_free_std_locked(sc, opipe->tail.td); 3222 } 3223 3224 /************************/ 3225 3226 Static int 3227 ohci_device_intr_init(struct usbd_xfer *xfer) 3228 { 3229 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3230 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3231 int len = xfer->ux_bufsize; 3232 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;; 3233 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3234 int err; 3235 3236 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3237 3238 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3239 KASSERT(len != 0); 3240 3241 DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread, 3242 xfer->ux_flags); 3243 DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0); 3244 3245 ox->ox_nstd = 0; 3246 3247 err = ohci_alloc_std_chain(sc, xfer, len, isread); 3248 if (err) { 3249 return err; 3250 } 3251 3252 return 0; 3253 } 3254 3255 Static void 3256 ohci_device_intr_fini(struct usbd_xfer *xfer) 3257 { 3258 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3259 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3260 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3261 3262 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3263 DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0); 3264 3265 mutex_enter(&sc->sc_lock); 3266 for (size_t i = 0; i < ox->ox_nstd; i++) { 3267 ohci_soft_td_t *std = ox->ox_stds[i]; 3268 if (std != NULL) 3269 break; 3270 if (std != opipe->tail.td) 3271 ohci_free_std_locked(sc, std); 3272 } 3273 mutex_exit(&sc->sc_lock); 3274 3275 if (ox->ox_nstd) { 3276 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 3277 kmem_free(ox->ox_stds, sz); 3278 } 3279 } 3280 3281 Static usbd_status 3282 ohci_device_intr_transfer(struct usbd_xfer *xfer) 3283 { 3284 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3285 usbd_status err; 3286 3287 /* Insert last in queue. */ 3288 mutex_enter(&sc->sc_lock); 3289 err = usb_insert_transfer(xfer); 3290 mutex_exit(&sc->sc_lock); 3291 if (err) 3292 return err; 3293 3294 /* Pipe isn't running, start first */ 3295 return ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3296 } 3297 3298 Static usbd_status 3299 ohci_device_intr_start(struct usbd_xfer *xfer) 3300 { 3301 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3302 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3303 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3304 ohci_soft_ed_t *sed = opipe->sed; 3305 ohci_soft_td_t *data, *last, *tail; 3306 int len, isread, endpt; 3307 3308 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3309 3310 if (sc->sc_dying) 3311 return USBD_IOERROR; 3312 3313 DPRINTFN(3, "xfer=%p len=%d flags=%d priv=%p", xfer, xfer->ux_length, 3314 xfer->ux_flags, xfer->ux_priv); 3315 3316 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3317 3318 len = xfer->ux_length; 3319 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3320 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3321 3322 mutex_enter(&sc->sc_lock); 3323 3324 /* Use "tail" TD and loan our first TD to next transfer */ 3325 data = opipe->tail.td; 3326 opipe->tail.td = ox->ox_stds[0]; 3327 ox->ox_stds[0] = data; 3328 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3329 3330 tail = opipe->tail.td; /* point at sentinel */ 3331 memset(&tail->td, 0, sizeof(tail->td)); 3332 tail->nexttd = NULL; 3333 tail->xfer = NULL; 3334 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3335 BUS_DMASYNC_PREWRITE); 3336 xfer->ux_hcpriv = data; 3337 3338 DPRINTFN(8, "data %p tail %p", ox->ox_stds[0], tail, 0, 0); 3339 KASSERT(opipe->tail.td == tail); 3340 3341 /* We want interrupt at the end of the transfer. */ 3342 last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3343 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3344 3345 last->td.td_nexttd = HTOO32(tail->physaddr); 3346 last->nexttd = tail; 3347 last->flags |= OHCI_CALL_DONE; 3348 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3349 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3350 3351 #ifdef OHCI_DEBUG 3352 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3353 if (ohcidebug > 5) { 3354 ohci_dump_ed(sc, sed); 3355 ohci_dump_tds(sc, data); 3356 } 3357 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3358 #endif 3359 3360 /* Insert ED in schedule */ 3361 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3362 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3363 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3364 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3365 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3366 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3367 3368 mutex_exit(&sc->sc_lock); 3369 3370 return USBD_IN_PROGRESS; 3371 } 3372 3373 /* Abort a device interrupt request. */ 3374 Static void 3375 ohci_device_intr_abort(struct usbd_xfer *xfer) 3376 { 3377 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3378 3379 KASSERT(mutex_owned(&sc->sc_lock)); 3380 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3381 3382 ohci_abort_xfer(xfer, USBD_CANCELLED); 3383 } 3384 3385 /* Close a device interrupt pipe. */ 3386 Static void 3387 ohci_device_intr_close(struct usbd_pipe *pipe) 3388 { 3389 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3390 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3391 int nslots = opipe->intr.nslots; 3392 int pos = opipe->intr.pos; 3393 int j; 3394 ohci_soft_ed_t *p, *sed = opipe->sed; 3395 3396 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3397 3398 KASSERT(mutex_owned(&sc->sc_lock)); 3399 3400 DPRINTFN(1, "pipe=%p nslots=%d pos=%d", pipe, nslots, pos, 0); 3401 usb_syncmem(&sed->dma, sed->offs, 3402 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3403 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3404 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3405 sizeof(sed->ed.ed_flags), 3406 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3407 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3408 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3409 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3410 3411 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3412 continue; 3413 KASSERT(p); 3414 p->next = sed->next; 3415 p->ed.ed_nexted = sed->ed.ed_nexted; 3416 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3417 sizeof(p->ed.ed_nexted), 3418 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3419 3420 for (j = 0; j < nslots; j++) 3421 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3422 3423 ohci_free_std_locked(sc, opipe->tail.td); 3424 ohci_free_sed_locked(sc, opipe->sed); 3425 } 3426 3427 Static usbd_status 3428 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3429 { 3430 int i, j, best; 3431 u_int npoll, slow, shigh, nslots; 3432 u_int bestbw, bw; 3433 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3434 3435 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3436 3437 DPRINTFN(2, "pipe=%p", opipe, 0, 0, 0); 3438 if (ival == 0) { 3439 printf("ohci_setintr: 0 interval\n"); 3440 return USBD_INVAL; 3441 } 3442 3443 npoll = OHCI_NO_INTRS; 3444 while (npoll > ival) 3445 npoll /= 2; 3446 DPRINTFN(2, "ival=%d npoll=%d", ival, npoll, 0, 0); 3447 3448 /* 3449 * We now know which level in the tree the ED must go into. 3450 * Figure out which slot has most bandwidth left over. 3451 * Slots to examine: 3452 * npoll 3453 * 1 0 3454 * 2 1 2 3455 * 4 3 4 5 6 3456 * 8 7 8 9 10 11 12 13 14 3457 * N (N-1) .. (N-1+N-1) 3458 */ 3459 slow = npoll-1; 3460 shigh = slow + npoll; 3461 nslots = OHCI_NO_INTRS / npoll; 3462 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3463 bw = 0; 3464 for (j = 0; j < nslots; j++) 3465 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3466 if (bw < bestbw) { 3467 best = i; 3468 bestbw = bw; 3469 } 3470 } 3471 DPRINTFN(2, "best=%d(%d..%d) bestbw=%d", best, slow, shigh, bestbw); 3472 3473 mutex_enter(&sc->sc_lock); 3474 hsed = sc->sc_eds[best]; 3475 sed->next = hsed->next; 3476 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3477 sizeof(hsed->ed.ed_flags), 3478 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3479 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3480 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3481 sizeof(sed->ed.ed_flags), 3482 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3483 hsed->next = sed; 3484 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3485 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3486 sizeof(hsed->ed.ed_flags), 3487 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3488 mutex_exit(&sc->sc_lock); 3489 3490 for (j = 0; j < nslots; j++) 3491 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3492 opipe->intr.nslots = nslots; 3493 opipe->intr.pos = best; 3494 3495 DPRINTFN(5, "returns %p", opipe, 0, 0, 0); 3496 return USBD_NORMAL_COMPLETION; 3497 } 3498 3499 /***********************/ 3500 3501 Static int 3502 ohci_device_isoc_init(struct usbd_xfer *xfer) 3503 { 3504 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3505 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3506 ohci_soft_itd_t *sitd; 3507 size_t i; 3508 int err; 3509 3510 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3511 3512 DPRINTFN(1, "xfer %p len %d flags %d", xfer, xfer->ux_length, 3513 xfer->ux_flags, 0); 3514 3515 const size_t nfsitd = 3516 (xfer->ux_nframes + OHCI_ITD_NOFFSET - 1) / OHCI_ITD_NOFFSET; 3517 const size_t nbsitd = xfer->ux_bufsize / OHCI_PAGE_SIZE; 3518 const size_t nsitd = MAX(nfsitd, nbsitd) + 1; 3519 3520 ox->ox_sitds = kmem_zalloc(sizeof(ohci_soft_itd_t *) * nsitd, 3521 KM_SLEEP); 3522 ox->ox_nsitd = nsitd; 3523 3524 for (i = 0; i < nsitd; i++) { 3525 /* Allocate next ITD */ 3526 sitd = ohci_alloc_sitd(sc); 3527 if (sitd == NULL) { 3528 err = ENOMEM; 3529 goto fail; 3530 } 3531 ox->ox_sitds[i] = sitd; 3532 sitd->xfer = xfer; 3533 sitd->flags = 0; 3534 } 3535 3536 return 0; 3537 fail: 3538 for (; i > 0;) { 3539 ohci_free_sitd(sc, ox->ox_sitds[--i]); 3540 } 3541 return err; 3542 } 3543 3544 Static void 3545 ohci_device_isoc_fini(struct usbd_xfer *xfer) 3546 { 3547 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3548 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3549 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3550 3551 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3552 3553 mutex_enter(&sc->sc_lock); 3554 for (size_t i = 0; i < ox->ox_nsitd; i++) { 3555 if (ox->ox_sitds[i] != opipe->tail.itd) { 3556 ohci_free_sitd_locked(sc, ox->ox_sitds[i]); 3557 } 3558 } 3559 mutex_exit(&sc->sc_lock); 3560 3561 if (ox->ox_nsitd) { 3562 const size_t sz = sizeof(ohci_soft_itd_t *) * ox->ox_nsitd; 3563 kmem_free(ox->ox_sitds, sz); 3564 } 3565 } 3566 3567 3568 usbd_status 3569 ohci_device_isoc_transfer(struct usbd_xfer *xfer) 3570 { 3571 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3572 usbd_status err; 3573 3574 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3575 3576 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 3577 3578 /* Put it on our queue, */ 3579 mutex_enter(&sc->sc_lock); 3580 err = usb_insert_transfer(xfer); 3581 mutex_exit(&sc->sc_lock); 3582 3583 /* bail out on error, */ 3584 if (err && err != USBD_IN_PROGRESS) 3585 return err; 3586 3587 /* XXX should check inuse here */ 3588 3589 /* insert into schedule, */ 3590 ohci_device_isoc_enter(xfer); 3591 3592 /* and start if the pipe wasn't running */ 3593 if (!err) 3594 ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3595 3596 return err; 3597 } 3598 3599 void 3600 ohci_device_isoc_enter(struct usbd_xfer *xfer) 3601 { 3602 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3603 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3604 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3605 ohci_soft_ed_t *sed = opipe->sed; 3606 ohci_soft_itd_t *sitd, *nsitd; 3607 ohci_physaddr_t buf, offs, noffs, bp0; 3608 int i, ncur, nframes; 3609 3610 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3611 3612 mutex_enter(&sc->sc_lock); 3613 3614 if (sc->sc_dying) { 3615 mutex_exit(&sc->sc_lock); 3616 return; 3617 } 3618 3619 struct isoc *isoc = &opipe->isoc; 3620 3621 DPRINTFN(1, "used=%d next=%d xfer=%p nframes=%d", 3622 isoc->inuse, isoc->next, xfer, xfer->ux_nframes); 3623 3624 if (isoc->next == -1) { 3625 /* Not in use yet, schedule it a few frames ahead. */ 3626 isoc->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3627 DPRINTFN(2,"start next=%d", isoc->next, 0, 0, 0); 3628 } 3629 3630 sitd = opipe->tail.itd; 3631 opipe->tail.itd = ox->ox_sitds[0]; 3632 ox->ox_sitds[0] = sitd; 3633 3634 buf = DMAADDR(&xfer->ux_dmabuf, 0); 3635 bp0 = OHCI_PAGE(buf); 3636 offs = OHCI_PAGE_OFFSET(buf); 3637 nframes = xfer->ux_nframes; 3638 xfer->ux_hcpriv = sitd; 3639 size_t j = 1; 3640 for (i = ncur = 0; i < nframes; i++, ncur++) { 3641 noffs = offs + xfer->ux_frlengths[i]; 3642 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3643 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3644 3645 /* Allocate next ITD */ 3646 nsitd = ox->ox_sitds[j++]; 3647 KASSERT(nsitd != NULL); 3648 KASSERT(j < ox->ox_nsitd); 3649 3650 /* Fill current ITD */ 3651 sitd->itd.itd_flags = HTOO32( 3652 OHCI_ITD_NOCC | 3653 OHCI_ITD_SET_SF(isoc->next) | 3654 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3655 OHCI_ITD_SET_FC(ncur)); 3656 sitd->itd.itd_bp0 = HTOO32(bp0); 3657 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3658 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3659 sitd->nextitd = nsitd; 3660 sitd->xfer = xfer; 3661 sitd->flags = 0; 3662 #ifdef DIAGNOSTIC 3663 sitd->isdone = false; 3664 #endif 3665 ohci_hash_add_itd(sc, sitd); 3666 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3667 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3668 3669 sitd = nsitd; 3670 isoc->next = isoc->next + ncur; 3671 bp0 = OHCI_PAGE(buf + offs); 3672 ncur = 0; 3673 } 3674 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3675 offs = noffs; 3676 } 3677 nsitd = ox->ox_sitds[j++]; 3678 KASSERT(nsitd != NULL); 3679 KASSERT(j <= ox->ox_nsitd); 3680 3681 memset(&nsitd->itd, 0, sizeof(nsitd->itd)); 3682 nsitd->nextitd = NULL; 3683 nsitd->xfer = NULL; 3684 /* Fixup last used ITD */ 3685 sitd->itd.itd_flags = HTOO32( 3686 OHCI_ITD_NOCC | 3687 OHCI_ITD_SET_SF(isoc->next) | 3688 OHCI_ITD_SET_DI(0) | 3689 OHCI_ITD_SET_FC(ncur)); 3690 sitd->itd.itd_bp0 = HTOO32(bp0); 3691 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3692 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3693 sitd->nextitd = nsitd; 3694 sitd->xfer = xfer; 3695 sitd->flags = OHCI_CALL_DONE; 3696 #ifdef DIAGNOSTIC 3697 sitd->isdone = false; 3698 #endif 3699 ohci_hash_add_itd(sc, sitd); 3700 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3701 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3702 3703 isoc->next = isoc->next + ncur; 3704 isoc->inuse += nframes; 3705 3706 xfer->ux_actlen = offs; /* XXX pretend we did it all */ 3707 3708 xfer->ux_status = USBD_IN_PROGRESS; 3709 3710 #ifdef OHCI_DEBUG 3711 if (ohcidebug > 5) { 3712 DPRINTF("frame=%d", O32TOH(sc->sc_hcca->hcca_frame_number), 3713 0, 0, 0); 3714 ohci_dump_itds(sc, xfer->ux_hcpriv); 3715 ohci_dump_ed(sc, sed); 3716 } 3717 #endif 3718 3719 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3720 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3721 sed->ed.ed_tailp = HTOO32(nsitd->physaddr); 3722 opipe->tail.itd = nsitd; 3723 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3724 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3725 sizeof(sed->ed.ed_flags), 3726 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3727 mutex_exit(&sc->sc_lock); 3728 3729 #ifdef OHCI_DEBUG 3730 if (ohcidebug > 5) { 3731 delay(150000); 3732 DPRINTF("after frame=%d", O32TOH(sc->sc_hcca->hcca_frame_number), 3733 0, 0, 0); 3734 ohci_dump_itds(sc, xfer->ux_hcpriv); 3735 ohci_dump_ed(sc, sed); 3736 } 3737 #endif 3738 } 3739 3740 usbd_status 3741 ohci_device_isoc_start(struct usbd_xfer *xfer) 3742 { 3743 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3744 3745 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3746 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 3747 3748 mutex_enter(&sc->sc_lock); 3749 3750 if (sc->sc_dying) { 3751 mutex_exit(&sc->sc_lock); 3752 return USBD_IOERROR; 3753 } 3754 3755 3756 #ifdef DIAGNOSTIC 3757 if (xfer->ux_status != USBD_IN_PROGRESS) 3758 printf("ohci_device_isoc_start: not in progress %p\n", xfer); 3759 #endif 3760 3761 /* XXX anything to do? */ 3762 3763 mutex_exit(&sc->sc_lock); 3764 3765 return USBD_IN_PROGRESS; 3766 } 3767 3768 void 3769 ohci_device_isoc_abort(struct usbd_xfer *xfer) 3770 { 3771 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3772 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3773 ohci_soft_ed_t *sed; 3774 ohci_soft_itd_t *sitd; 3775 3776 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3777 DPRINTFN(1, "xfer=%p", xfer, 0, 0, 0); 3778 3779 KASSERT(mutex_owned(&sc->sc_lock)); 3780 3781 /* Transfer is already done. */ 3782 if (xfer->ux_status != USBD_NOT_STARTED && 3783 xfer->ux_status != USBD_IN_PROGRESS) { 3784 printf("ohci_device_isoc_abort: early return\n"); 3785 goto done; 3786 } 3787 3788 /* Give xfer the requested abort code. */ 3789 xfer->ux_status = USBD_CANCELLED; 3790 3791 sed = opipe->sed; 3792 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3793 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3794 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3795 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3796 sizeof(sed->ed.ed_flags), 3797 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3798 3799 sitd = xfer->ux_hcpriv; 3800 KASSERT(sitd); 3801 3802 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3803 #ifdef DIAGNOSTIC 3804 DPRINTFN(1, "abort sets done sitd=%p", sitd, 0, 0, 0); 3805 sitd->isdone = true; 3806 #endif 3807 } 3808 3809 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3810 3811 /* Run callback. */ 3812 usb_transfer_complete(xfer); 3813 3814 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3815 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3816 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3817 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3818 3819 done: 3820 KASSERT(mutex_owned(&sc->sc_lock)); 3821 } 3822 3823 void 3824 ohci_device_isoc_done(struct usbd_xfer *xfer) 3825 { 3826 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3827 DPRINTFN(1, "xfer=%p", xfer, 0, 0, 0); 3828 } 3829 3830 usbd_status 3831 ohci_setup_isoc(struct usbd_pipe *pipe) 3832 { 3833 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3834 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3835 struct isoc *isoc = &opipe->isoc; 3836 3837 isoc->next = -1; 3838 isoc->inuse = 0; 3839 3840 mutex_enter(&sc->sc_lock); 3841 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3842 mutex_exit(&sc->sc_lock); 3843 3844 return USBD_NORMAL_COMPLETION; 3845 } 3846 3847 void 3848 ohci_device_isoc_close(struct usbd_pipe *pipe) 3849 { 3850 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3851 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3852 3853 KASSERT(mutex_owned(&sc->sc_lock)); 3854 3855 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3856 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3857 ohci_close_pipe(pipe, sc->sc_isoc_head); 3858 #ifdef DIAGNOSTIC 3859 opipe->tail.itd->isdone = true; 3860 #endif 3861 ohci_free_sitd_locked(sc, opipe->tail.itd); 3862 } 3863
Indexes created Fri Oct 03 02:09:57 GMT 2025