ohci.c revision 1.254.2.38
1 /* $NetBSD: ohci.c,v 1.254.2.38 2015/12/28 15:46:28 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * USB Open Host Controller driver. 38 * 39 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 40 * USB spec: http://www.usb.org/developers/docs/ 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.254.2.38 2015/12/28 15:46:28 skrll Exp $"); 45 46 #include "opt_usb.h" 47 48 #include <sys/param.h> 49 50 #include <sys/cpu.h> 51 #include <sys/device.h> 52 #include <sys/kernel.h> 53 #include <sys/kmem.h> 54 #include <sys/proc.h> 55 #include <sys/queue.h> 56 #include <sys/select.h> 57 #include <sys/sysctl.h> 58 #include <sys/systm.h> 59 60 #include <machine/endian.h> 61 62 #include <dev/usb/usb.h> 63 #include <dev/usb/usbdi.h> 64 #include <dev/usb/usbdivar.h> 65 #include <dev/usb/usb_mem.h> 66 #include <dev/usb/usb_quirks.h> 67 68 #include <dev/usb/ohcireg.h> 69 #include <dev/usb/ohcivar.h> 70 #include <dev/usb/usbroothub.h> 71 #include <dev/usb/usbhist.h> 72 73 #ifdef USB_DEBUG 74 #ifndef OHCI_DEBUG 75 #define ohcidebug 0 76 #else 77 static int ohcidebug = 0; 78 79 SYSCTL_SETUP(sysctl_hw_ohci_setup, "sysctl hw.ohci setup") 80 { 81 int err; 82 const struct sysctlnode *rnode; 83 const struct sysctlnode *cnode; 84 85 err = sysctl_createv(clog, 0, NULL, &rnode, 86 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ohci", 87 SYSCTL_DESCR("ohci global controls"), 88 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 89 90 if (err) 91 goto fail; 92 93 /* control debugging printfs */ 94 err = sysctl_createv(clog, 0, &rnode, &cnode, 95 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 96 "debug", SYSCTL_DESCR("Enable debugging output"), 97 NULL, 0, &ohcidebug, sizeof(ohcidebug), CTL_CREATE, CTL_EOL); 98 if (err) 99 goto fail; 100 101 return; 102 fail: 103 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 104 } 105 106 #endif /* OHCI_DEBUG */ 107 #endif /* USB_DEBUG */ 108 109 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ohcidebug,FMT,A,B,C,D) 110 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ohcidebug,N,FMT,A,B,C,D) 111 #define OHCIHIST_FUNC() USBHIST_FUNC() 112 #define OHCIHIST_CALLED(name) USBHIST_CALLED(ohcidebug) 113 114 #if BYTE_ORDER == BIG_ENDIAN 115 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 116 #else 117 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 118 #endif 119 120 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 121 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 122 #define HTOO16(val) O16TOH(val) 123 #define HTOO32(val) O32TOH(val) 124 125 struct ohci_pipe; 126 127 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 128 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 129 130 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 131 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 132 Static void ohci_free_std_locked(ohci_softc_t *, ohci_soft_td_t *); 133 134 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 135 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 136 Static void ohci_free_sitd_locked(ohci_softc_t *, 137 ohci_soft_itd_t *); 138 139 Static usbd_status ohci_alloc_std_chain(ohci_softc_t *, struct usbd_xfer *, 140 int, int); 141 Static void ohci_free_stds(ohci_softc_t *, struct ohci_xfer *); 142 143 Static void ohci_reset_std_chain(ohci_softc_t *, struct usbd_xfer *, 144 int, int, ohci_soft_td_t *, ohci_soft_td_t **); 145 146 Static usbd_status ohci_open(struct usbd_pipe *); 147 Static void ohci_poll(struct usbd_bus *); 148 Static void ohci_softintr(void *); 149 Static void ohci_waitintr(ohci_softc_t *, struct usbd_xfer *); 150 Static void ohci_rhsc(ohci_softc_t *, struct usbd_xfer *); 151 Static void ohci_rhsc_softint(void *); 152 153 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 154 ohci_soft_ed_t *); 155 156 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 157 ohci_soft_ed_t *); 158 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 159 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 160 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 161 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 162 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 163 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 164 165 Static usbd_status ohci_setup_isoc(struct usbd_pipe *); 166 Static void ohci_device_isoc_enter(struct usbd_xfer *); 167 168 Static struct usbd_xfer * 169 ohci_allocx(struct usbd_bus *, unsigned int); 170 Static void ohci_freex(struct usbd_bus *, struct usbd_xfer *); 171 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 172 Static int ohci_roothub_ctrl(struct usbd_bus *, 173 usb_device_request_t *, void *, int); 174 175 Static usbd_status ohci_root_intr_transfer(struct usbd_xfer *); 176 Static usbd_status ohci_root_intr_start(struct usbd_xfer *); 177 Static void ohci_root_intr_abort(struct usbd_xfer *); 178 Static void ohci_root_intr_close(struct usbd_pipe *); 179 Static void ohci_root_intr_done(struct usbd_xfer *); 180 181 Static int ohci_device_ctrl_init(struct usbd_xfer *); 182 Static void ohci_device_ctrl_fini(struct usbd_xfer *); 183 Static usbd_status ohci_device_ctrl_transfer(struct usbd_xfer *); 184 Static usbd_status ohci_device_ctrl_start(struct usbd_xfer *); 185 Static void ohci_device_ctrl_abort(struct usbd_xfer *); 186 Static void ohci_device_ctrl_close(struct usbd_pipe *); 187 Static void ohci_device_ctrl_done(struct usbd_xfer *); 188 189 Static int ohci_device_bulk_init(struct usbd_xfer *); 190 Static void ohci_device_bulk_fini(struct usbd_xfer *); 191 Static usbd_status ohci_device_bulk_transfer(struct usbd_xfer *); 192 Static usbd_status ohci_device_bulk_start(struct usbd_xfer *); 193 Static void ohci_device_bulk_abort(struct usbd_xfer *); 194 Static void ohci_device_bulk_close(struct usbd_pipe *); 195 Static void ohci_device_bulk_done(struct usbd_xfer *); 196 197 Static int ohci_device_intr_init(struct usbd_xfer *); 198 Static void ohci_device_intr_fini(struct usbd_xfer *); 199 Static usbd_status ohci_device_intr_transfer(struct usbd_xfer *); 200 Static usbd_status ohci_device_intr_start(struct usbd_xfer *); 201 Static void ohci_device_intr_abort(struct usbd_xfer *); 202 Static void ohci_device_intr_close(struct usbd_pipe *); 203 Static void ohci_device_intr_done(struct usbd_xfer *); 204 205 Static int ohci_device_isoc_init(struct usbd_xfer *); 206 Static void ohci_device_isoc_fini(struct usbd_xfer *); 207 Static usbd_status ohci_device_isoc_transfer(struct usbd_xfer *); 208 Static usbd_status ohci_device_isoc_start(struct usbd_xfer *); 209 Static void ohci_device_isoc_abort(struct usbd_xfer *); 210 Static void ohci_device_isoc_close(struct usbd_pipe *); 211 Static void ohci_device_isoc_done(struct usbd_xfer *); 212 213 Static usbd_status ohci_device_setintr(ohci_softc_t *, 214 struct ohci_pipe *, int); 215 216 Static void ohci_timeout(void *); 217 Static void ohci_timeout_task(void *); 218 Static void ohci_rhsc_enable(void *); 219 220 Static void ohci_close_pipe(struct usbd_pipe *, ohci_soft_ed_t *); 221 Static void ohci_abort_xfer(struct usbd_xfer *, usbd_status); 222 223 Static void ohci_device_clear_toggle(struct usbd_pipe *); 224 Static void ohci_noop(struct usbd_pipe *); 225 226 #ifdef OHCI_DEBUG 227 Static void ohci_dumpregs(ohci_softc_t *); 228 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 229 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 230 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 231 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 232 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 233 #endif 234 235 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 236 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 237 #define OWRITE1(sc, r, x) \ 238 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 239 #define OWRITE2(sc, r, x) \ 240 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 241 #define OWRITE4(sc, r, x) \ 242 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 243 244 static __inline uint32_t 245 OREAD4(ohci_softc_t *sc, bus_size_t r) 246 { 247 248 OBARR(sc); 249 return bus_space_read_4(sc->iot, sc->ioh, r); 250 } 251 252 /* Reverse the bits in a value 0 .. 31 */ 253 Static uint8_t revbits[OHCI_NO_INTRS] = 254 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 255 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 256 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 257 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 258 259 struct ohci_pipe { 260 struct usbd_pipe pipe; 261 ohci_soft_ed_t *sed; 262 union { 263 ohci_soft_td_t *td; 264 ohci_soft_itd_t *itd; 265 } tail; 266 /* Info needed for different pipe kinds. */ 267 union { 268 /* Control pipe */ 269 struct { 270 usb_dma_t reqdma; 271 } ctrl; 272 /* Interrupt pipe */ 273 struct { 274 int nslots; 275 int pos; 276 } intr; 277 /* Isochronous pipe */ 278 struct isoc { 279 int next, inuse; 280 } isoc; 281 }; 282 }; 283 284 Static const struct usbd_bus_methods ohci_bus_methods = { 285 .ubm_open = ohci_open, 286 .ubm_softint = ohci_softintr, 287 .ubm_dopoll = ohci_poll, 288 .ubm_allocx = ohci_allocx, 289 .ubm_freex = ohci_freex, 290 .ubm_getlock = ohci_get_lock, 291 .ubm_rhctrl = ohci_roothub_ctrl, 292 }; 293 294 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 295 .upm_transfer = ohci_root_intr_transfer, 296 .upm_start = ohci_root_intr_start, 297 .upm_abort = ohci_root_intr_abort, 298 .upm_close = ohci_root_intr_close, 299 .upm_cleartoggle = ohci_noop, 300 .upm_done = ohci_root_intr_done, 301 }; 302 303 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 304 .upm_init = ohci_device_ctrl_init, 305 .upm_fini = ohci_device_ctrl_fini, 306 .upm_transfer = ohci_device_ctrl_transfer, 307 .upm_start = ohci_device_ctrl_start, 308 .upm_abort = ohci_device_ctrl_abort, 309 .upm_close = ohci_device_ctrl_close, 310 .upm_cleartoggle = ohci_noop, 311 .upm_done = ohci_device_ctrl_done, 312 }; 313 314 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 315 .upm_init = ohci_device_intr_init, 316 .upm_fini = ohci_device_intr_fini, 317 .upm_transfer = ohci_device_intr_transfer, 318 .upm_start = ohci_device_intr_start, 319 .upm_abort = ohci_device_intr_abort, 320 .upm_close = ohci_device_intr_close, 321 .upm_cleartoggle = ohci_device_clear_toggle, 322 .upm_done = ohci_device_intr_done, 323 }; 324 325 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 326 .upm_init = ohci_device_bulk_init, 327 .upm_fini = ohci_device_bulk_fini, 328 .upm_transfer = ohci_device_bulk_transfer, 329 .upm_start = ohci_device_bulk_start, 330 .upm_abort = ohci_device_bulk_abort, 331 .upm_close = ohci_device_bulk_close, 332 .upm_cleartoggle = ohci_device_clear_toggle, 333 .upm_done = ohci_device_bulk_done, 334 }; 335 336 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 337 .upm_init = ohci_device_isoc_init, 338 .upm_fini = ohci_device_isoc_fini, 339 .upm_transfer = ohci_device_isoc_transfer, 340 .upm_start = ohci_device_isoc_start, 341 .upm_abort = ohci_device_isoc_abort, 342 .upm_close = ohci_device_isoc_close, 343 .upm_cleartoggle = ohci_noop, 344 .upm_done = ohci_device_isoc_done, 345 }; 346 347 int 348 ohci_activate(device_t self, enum devact act) 349 { 350 struct ohci_softc *sc = device_private(self); 351 352 switch (act) { 353 case DVACT_DEACTIVATE: 354 sc->sc_dying = 1; 355 return 0; 356 default: 357 return EOPNOTSUPP; 358 } 359 } 360 361 void 362 ohci_childdet(device_t self, device_t child) 363 { 364 struct ohci_softc *sc = device_private(self); 365 366 KASSERT(sc->sc_child == child); 367 sc->sc_child = NULL; 368 } 369 370 int 371 ohci_detach(struct ohci_softc *sc, int flags) 372 { 373 int rv = 0; 374 375 if (sc->sc_child != NULL) 376 rv = config_detach(sc->sc_child, flags); 377 378 if (rv != 0) 379 return rv; 380 381 callout_halt(&sc->sc_tmo_rhsc, &sc->sc_lock); 382 383 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 384 callout_destroy(&sc->sc_tmo_rhsc); 385 386 softint_disestablish(sc->sc_rhsc_si); 387 388 cv_destroy(&sc->sc_softwake_cv); 389 390 mutex_destroy(&sc->sc_lock); 391 mutex_destroy(&sc->sc_intr_lock); 392 393 if (sc->sc_hcca != NULL) 394 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 395 pool_cache_destroy(sc->sc_xferpool); 396 397 return rv; 398 } 399 400 ohci_soft_ed_t * 401 ohci_alloc_sed(ohci_softc_t *sc) 402 { 403 ohci_soft_ed_t *sed; 404 usbd_status err; 405 int i, offs; 406 usb_dma_t dma; 407 408 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 409 410 mutex_enter(&sc->sc_lock); 411 if (sc->sc_freeeds == NULL) { 412 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 413 mutex_exit(&sc->sc_lock); 414 415 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 416 OHCI_ED_ALIGN, &dma); 417 if (err) 418 return 0; 419 420 mutex_enter(&sc->sc_lock); 421 for (i = 0; i < OHCI_SED_CHUNK; i++) { 422 offs = i * OHCI_SED_SIZE; 423 sed = KERNADDR(&dma, offs); 424 sed->physaddr = DMAADDR(&dma, offs); 425 sed->dma = dma; 426 sed->offs = offs; 427 sed->next = sc->sc_freeeds; 428 sc->sc_freeeds = sed; 429 } 430 } 431 sed = sc->sc_freeeds; 432 sc->sc_freeeds = sed->next; 433 mutex_exit(&sc->sc_lock); 434 435 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 436 sed->next = 0; 437 return sed; 438 } 439 440 static inline void 441 ohci_free_sed_locked(ohci_softc_t *sc, ohci_soft_ed_t *sed) 442 { 443 444 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 445 446 sed->next = sc->sc_freeeds; 447 sc->sc_freeeds = sed; 448 } 449 450 void 451 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 452 { 453 454 mutex_enter(&sc->sc_lock); 455 ohci_free_sed_locked(sc, sed); 456 mutex_exit(&sc->sc_lock); 457 } 458 459 ohci_soft_td_t * 460 ohci_alloc_std(ohci_softc_t *sc) 461 { 462 ohci_soft_td_t *std; 463 usbd_status err; 464 int i, offs; 465 usb_dma_t dma; 466 467 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 468 469 mutex_enter(&sc->sc_lock); 470 if (sc->sc_freetds == NULL) { 471 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 472 mutex_exit(&sc->sc_lock); 473 474 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 475 OHCI_TD_ALIGN, &dma); 476 if (err) 477 return NULL; 478 479 mutex_enter(&sc->sc_lock); 480 for(i = 0; i < OHCI_STD_CHUNK; i++) { 481 offs = i * OHCI_STD_SIZE; 482 std = KERNADDR(&dma, offs); 483 std->physaddr = DMAADDR(&dma, offs); 484 std->dma = dma; 485 std->offs = offs; 486 std->nexttd = sc->sc_freetds; 487 sc->sc_freetds = std; 488 } 489 } 490 491 std = sc->sc_freetds; 492 sc->sc_freetds = std->nexttd; 493 mutex_exit(&sc->sc_lock); 494 495 memset(&std->td, 0, sizeof(ohci_td_t)); 496 std->nexttd = NULL; 497 std->xfer = NULL; 498 499 return std; 500 } 501 502 void 503 ohci_free_std_locked(ohci_softc_t *sc, ohci_soft_td_t *std) 504 { 505 506 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 507 508 std->nexttd = sc->sc_freetds; 509 sc->sc_freetds = std; 510 } 511 512 void 513 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 514 { 515 516 mutex_enter(&sc->sc_lock); 517 ohci_free_std_locked(sc, std); 518 mutex_exit(&sc->sc_lock); 519 } 520 521 Static usbd_status 522 ohci_alloc_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, int alen, int rd) 523 { 524 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 525 struct usbd_pipe *pipe = xfer->ux_pipe; 526 ohci_soft_td_t *next, *cur; 527 ohci_physaddr_t dataphys, dataphysend; 528 uint32_t tdflags; 529 int len = alen; 530 int curlen; 531 usb_dma_t *dma = &xfer->ux_dmabuf; 532 uint16_t flags = xfer->ux_flags; 533 534 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 535 536 DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d", 537 pipe->up_dev->ud_addr, 538 UE_GET_ADDR(pipe->up_endpoint->ue_edesc->bEndpointAddress), 539 alen, pipe->up_dev->ud_speed); 540 541 ASSERT_SLEEPABLE(); 542 543 size_t nstd = (flags & USBD_FORCE_SHORT_XFER) ? 1 : 0; 544 nstd += ((len + OHCI_PAGE_SIZE - 1) / OHCI_PAGE_SIZE); 545 ox->ox_stds = kmem_zalloc(sizeof(ohci_soft_td_t *) * nstd, 546 KM_SLEEP); 547 ox->ox_nstd = nstd; 548 int mps = UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize); 549 550 DPRINTFN(8, "xfer %p nstd %d mps %d", xfer, nstd, mps, 0); 551 552 len = alen; 553 cur = ohci_alloc_std(sc); 554 if (cur == NULL) 555 goto nomem; 556 557 dataphys = DMAADDR(dma, 0); 558 dataphysend = OHCI_PAGE(dataphys + len - 1); 559 tdflags = HTOO32( 560 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 561 (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) | 562 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 563 564 for (size_t j = 0;;) { 565 ox->ox_stds[j++] = cur; 566 next = ohci_alloc_std(sc); 567 if (next == NULL) 568 goto nomem; 569 570 /* The OHCI hardware can handle at most one page crossing. */ 571 if (OHCI_PAGE(dataphys) == dataphysend || 572 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 573 /* we can handle it in this TD */ 574 curlen = len; 575 } else { 576 /* must use multiple TDs, fill as much as possible. */ 577 curlen = 2 * OHCI_PAGE_SIZE - 578 (dataphys & (OHCI_PAGE_SIZE-1)); 579 /* the length must be a multiple of the max size */ 580 curlen -= curlen % mps; 581 KASSERT(curlen != 0); 582 } 583 DPRINTFN(4, "dataphys=0x%08x dataphysend=0x%08x " 584 "len=%d curlen=%d", dataphys, dataphysend, len, curlen); 585 len -= curlen; 586 587 cur->td.td_flags = tdflags; 588 cur->td.td_cbp = HTOO32(dataphys); 589 cur->td.td_nexttd = HTOO32(next->physaddr); 590 cur->td.td_be = HTOO32(dataphys + curlen - 1); 591 cur->nexttd = next; 592 cur->len = curlen; 593 cur->flags = OHCI_ADD_LEN; 594 cur->xfer = xfer; 595 596 DPRINTFN(10, "cbp=0x%08x be=0x%08x", dataphys, 597 dataphys + curlen - 1, 0, 0); 598 if (len == 0) 599 break; 600 DPRINTFN(10, "extend chain", 0, 0, 0, 0); 601 dataphys += curlen; 602 cur = next; 603 } 604 if (!rd && (flags & USBD_FORCE_SHORT_XFER) && 605 alen % mps == 0) { 606 /* Force a 0 length transfer at the end. */ 607 608 cur = next; 609 next = ohci_alloc_std(sc); 610 if (next == NULL) 611 goto nomem; 612 613 cur->td.td_flags = tdflags; 614 cur->td.td_cbp = 0; /* indicate 0 length packet */ 615 cur->td.td_nexttd = HTOO32(next->physaddr); 616 cur->td.td_be = ~0; 617 cur->nexttd = next; 618 cur->len = 0; 619 cur->flags = 0; 620 cur->xfer = xfer; 621 622 DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0); 623 } 624 625 return USBD_NORMAL_COMPLETION; 626 627 nomem: 628 ohci_free_stds(sc, ox); 629 630 return USBD_NOMEM; 631 } 632 633 Static void 634 ohci_free_stds(ohci_softc_t *sc, struct ohci_xfer *ox) 635 { 636 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 637 DPRINTF("ox=%p", ox, 0, 0, 0); 638 639 mutex_enter(&sc->sc_lock); 640 for (size_t i = 0; i < ox->ox_nstd; i++) { 641 ohci_soft_td_t *std = ox->ox_stds[i]; 642 if (std == NULL) 643 break; 644 ohci_free_std_locked(sc, std); 645 } 646 mutex_exit(&sc->sc_lock); 647 } 648 649 void 650 ohci_reset_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, 651 int alen, int rd, ohci_soft_td_t *sp, ohci_soft_td_t **ep) 652 { 653 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 654 ohci_soft_td_t *next, *cur; 655 ohci_physaddr_t dataphys, dataphysend; 656 uint32_t tdflags; 657 int len, curlen; 658 usb_dma_t *dma = &xfer->ux_dmabuf; 659 uint16_t flags = xfer->ux_flags; 660 661 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 662 DPRINTF("start len=%d", alen, 0, 0, 0); 663 664 KASSERT(mutex_owned(&sc->sc_lock)); 665 666 DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d", 667 xfer->ux_pipe->up_dev->ud_addr, 668 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 669 alen, xfer->ux_pipe->up_dev->ud_speed); 670 671 KASSERT(sp); 672 673 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 674 675 len = alen; 676 cur = sp; 677 678 dataphys = DMAADDR(dma, 0); 679 dataphysend = OHCI_PAGE(dataphys + len - 1); 680 usb_syncmem(dma, 0, len, 681 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 682 tdflags = HTOO32( 683 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 684 (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) | 685 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 686 687 for (size_t j = 1;;) { 688 if (j == ox->ox_nstd) 689 next = NULL; 690 else 691 next = ox->ox_stds[j++]; 692 KASSERT(next != cur); 693 694 /* The OHCI hardware can handle at most one page crossing. */ 695 if (OHCI_PAGE(dataphys) == dataphysend || 696 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 697 /* we can handle it in this TD */ 698 curlen = len; 699 } else { 700 /* must use multiple TDs, fill as much as possible. */ 701 curlen = 2 * OHCI_PAGE_SIZE - 702 (dataphys & (OHCI_PAGE_SIZE - 1)); 703 /* the length must be a multiple of the max size */ 704 curlen -= curlen % mps; 705 KASSERT(curlen != 0); 706 } 707 DPRINTFN(4, "dataphys=0x%08x dataphysend=0x%08x " 708 "len=%d curlen=%d", dataphys, dataphysend, len, curlen); 709 len -= curlen; 710 711 cur->td.td_flags = tdflags; 712 cur->td.td_cbp = HTOO32(dataphys); 713 cur->td.td_be = HTOO32(dataphys + curlen - 1); 714 cur->td.td_nexttd = (next != NULL) ? HTOO32(next->physaddr) : 0; 715 cur->nexttd = next; 716 cur->len = curlen; 717 cur->flags = OHCI_ADD_LEN; 718 cur->xfer = xfer; 719 ohci_hash_add_td(sc, cur); 720 721 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 722 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 723 DPRINTFN(10, "cbp=0x%08x be=0x%08x", dataphys, 724 dataphys + curlen - 1, 0, 0); 725 if (len == 0) 726 break; 727 KASSERT(next != NULL); 728 DPRINTFN(10, "extend chain", 0, 0, 0, 0); 729 dataphys += curlen; 730 cur = next; 731 } 732 if (!rd && 733 (flags & USBD_FORCE_SHORT_XFER) && 734 alen % mps == 0) { 735 /* Force a 0 length transfer at the end. */ 736 737 KASSERT(next != NULL); 738 cur = next; 739 740 cur->td.td_flags = tdflags; 741 cur->td.td_cbp = 0; /* indicate 0 length packet */ 742 cur->td.td_nexttd = HTOO32(next->physaddr); 743 cur->td.td_be = ~0; 744 cur->nexttd = NULL; 745 cur->len = 0; 746 cur->flags = 0; 747 cur->xfer = xfer; 748 ohci_hash_add_td(sc, cur); 749 750 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 751 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 752 DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0); 753 } 754 *ep = cur; 755 } 756 757 ohci_soft_itd_t * 758 ohci_alloc_sitd(ohci_softc_t *sc) 759 { 760 ohci_soft_itd_t *sitd; 761 usbd_status err; 762 int i, offs; 763 usb_dma_t dma; 764 765 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 766 767 mutex_enter(&sc->sc_lock); 768 if (sc->sc_freeitds == NULL) { 769 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 770 mutex_exit(&sc->sc_lock); 771 772 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 773 OHCI_ITD_ALIGN, &dma); 774 if (err) 775 return NULL; 776 mutex_enter(&sc->sc_lock); 777 for(i = 0; i < OHCI_SITD_CHUNK; i++) { 778 offs = i * OHCI_SITD_SIZE; 779 sitd = KERNADDR(&dma, offs); 780 sitd->physaddr = DMAADDR(&dma, offs); 781 sitd->dma = dma; 782 sitd->offs = offs; 783 sitd->nextitd = sc->sc_freeitds; 784 sc->sc_freeitds = sitd; 785 } 786 } 787 788 sitd = sc->sc_freeitds; 789 sc->sc_freeitds = sitd->nextitd; 790 mutex_exit(&sc->sc_lock); 791 792 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 793 sitd->nextitd = NULL; 794 sitd->xfer = NULL; 795 796 #ifdef DIAGNOSTIC 797 sitd->isdone = false; 798 #endif 799 800 return sitd; 801 } 802 803 Static void 804 ohci_free_sitd_locked(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 805 { 806 807 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 808 DPRINTFN(10, "sitd=%p", sitd, 0, 0, 0); 809 810 KASSERT(sitd->isdone); 811 #ifdef DIAGNOSTIC 812 /* Warn double free */ 813 sitd->isdone = false; 814 #endif 815 816 sitd->nextitd = sc->sc_freeitds; 817 sc->sc_freeitds = sitd; 818 } 819 820 void 821 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 822 { 823 824 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 825 826 mutex_enter(&sc->sc_lock); 827 ohci_free_sitd_locked(sc, sitd); 828 mutex_exit(&sc->sc_lock); 829 } 830 831 int 832 ohci_init(ohci_softc_t *sc) 833 { 834 ohci_soft_ed_t *sed, *psed; 835 usbd_status err; 836 int i; 837 uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */; 838 839 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 840 841 aprint_normal_dev(sc->sc_dev, ""); 842 843 sc->sc_hcca = NULL; 844 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 845 846 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 847 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 848 cv_init(&sc->sc_softwake_cv, "ohciab"); 849 850 sc->sc_rhsc_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 851 ohci_rhsc_softint, sc); 852 853 for (i = 0; i < OHCI_HASH_SIZE; i++) 854 LIST_INIT(&sc->sc_hash_tds[i]); 855 for (i = 0; i < OHCI_HASH_SIZE; i++) 856 LIST_INIT(&sc->sc_hash_itds[i]); 857 858 sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0, 859 "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL); 860 861 rev = OREAD4(sc, OHCI_REVISION); 862 aprint_normal("OHCI version %d.%d%s\n", 863 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 864 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 865 866 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 867 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 868 sc->sc_bus.ub_revision = USBREV_UNKNOWN; 869 return -1; 870 } 871 sc->sc_bus.ub_revision = USBREV_1_0; 872 sc->sc_bus.ub_usedma = true; 873 874 /* XXX determine alignment by R/W */ 875 /* Allocate the HCCA area. */ 876 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 877 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 878 if (err) { 879 sc->sc_hcca = NULL; 880 return err; 881 } 882 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 883 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 884 885 sc->sc_eintrs = OHCI_NORMAL_INTRS; 886 887 /* Allocate dummy ED that starts the control list. */ 888 sc->sc_ctrl_head = ohci_alloc_sed(sc); 889 if (sc->sc_ctrl_head == NULL) { 890 err = ENOMEM; 891 goto bad1; 892 } 893 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 894 895 /* Allocate dummy ED that starts the bulk list. */ 896 sc->sc_bulk_head = ohci_alloc_sed(sc); 897 if (sc->sc_bulk_head == NULL) { 898 err = ENOMEM; 899 goto bad2; 900 } 901 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 902 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 903 sizeof(sc->sc_bulk_head->ed), 904 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 905 906 /* Allocate dummy ED that starts the isochronous list. */ 907 sc->sc_isoc_head = ohci_alloc_sed(sc); 908 if (sc->sc_isoc_head == NULL) { 909 err = ENOMEM; 910 goto bad3; 911 } 912 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 913 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 914 sizeof(sc->sc_isoc_head->ed), 915 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 916 917 /* Allocate all the dummy EDs that make up the interrupt tree. */ 918 for (i = 0; i < OHCI_NO_EDS; i++) { 919 sed = ohci_alloc_sed(sc); 920 if (sed == NULL) { 921 while (--i >= 0) 922 ohci_free_sed(sc, sc->sc_eds[i]); 923 err = ENOMEM; 924 goto bad4; 925 } 926 /* All ED fields are set to 0. */ 927 sc->sc_eds[i] = sed; 928 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 929 if (i != 0) 930 psed = sc->sc_eds[(i-1) / 2]; 931 else 932 psed= sc->sc_isoc_head; 933 sed->next = psed; 934 sed->ed.ed_nexted = HTOO32(psed->physaddr); 935 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 936 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 937 } 938 /* 939 * Fill HCCA interrupt table. The bit reversal is to get 940 * the tree set up properly to spread the interrupts. 941 */ 942 for (i = 0; i < OHCI_NO_INTRS; i++) 943 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 944 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 945 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 946 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 947 948 #ifdef OHCI_DEBUG 949 DPRINTFN(15, "--- dump start ---", 0, 0, 0 ,0); 950 if (ohcidebug > 15) { 951 for (i = 0; i < OHCI_NO_EDS; i++) { 952 DPRINTFN(15, "ed#%d ", i, 0, 0, 0); 953 ohci_dump_ed(sc, sc->sc_eds[i]); 954 } 955 DPRINTFN(15, "iso", 0, 0, 0 ,0); 956 ohci_dump_ed(sc, sc->sc_isoc_head); 957 } 958 DPRINTFN(15, "--- dump end ---", 0, 0, 0 ,0); 959 #endif 960 961 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 962 ctl = OREAD4(sc, OHCI_CONTROL); 963 rwc = ctl & OHCI_RWC; 964 fm = OREAD4(sc, OHCI_FM_INTERVAL); 965 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 966 /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */ 967 968 /* Determine in what context we are running. */ 969 if (ctl & OHCI_IR) { 970 /* SMM active, request change */ 971 DPRINTF("SMM active, request owner change", 0, 0, 0, 0); 972 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 973 (OHCI_OC | OHCI_MIE)) 974 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 975 s = OREAD4(sc, OHCI_COMMAND_STATUS); 976 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 977 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 978 usb_delay_ms(&sc->sc_bus, 1); 979 ctl = OREAD4(sc, OHCI_CONTROL); 980 } 981 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 982 if ((ctl & OHCI_IR) == 0) { 983 aprint_error_dev(sc->sc_dev, 984 "SMM does not respond, resetting\n"); 985 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 986 goto reset; 987 } 988 #if 0 989 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 990 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 991 /* BIOS started controller. */ 992 DPRINTF("BIOS active", 0, 0, 0, 0); 993 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 994 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 995 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 996 } 997 #endif 998 } else { 999 DPRINTF("cold started", 0 ,0 ,0 ,0); 1000 reset: 1001 /* Controller was cold started. */ 1002 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 1003 } 1004 1005 /* 1006 * This reset should not be necessary according to the OHCI spec, but 1007 * without it some controllers do not start. 1008 */ 1009 DPRINTF("sc %p: resetting", sc, 0, 0, 0); 1010 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 1011 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 1012 1013 /* We now own the host controller and the bus has been reset. */ 1014 1015 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 1016 /* Nominal time for a reset is 10 us. */ 1017 for (i = 0; i < 10; i++) { 1018 delay(10); 1019 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 1020 if (!hcr) 1021 break; 1022 } 1023 if (hcr) { 1024 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 1025 err = EIO; 1026 goto bad5; 1027 } 1028 #ifdef OHCI_DEBUG 1029 if (ohcidebug > 15) 1030 ohci_dumpregs(sc); 1031 #endif 1032 1033 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 1034 1035 /* Set up HC registers. */ 1036 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1037 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 1038 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 1039 /* disable all interrupts and then switch on all desired interrupts */ 1040 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 1041 /* switch on desired functional features */ 1042 ctl = OREAD4(sc, OHCI_CONTROL); 1043 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 1044 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 1045 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 1046 /* And finally start it! */ 1047 OWRITE4(sc, OHCI_CONTROL, ctl); 1048 1049 /* 1050 * The controller is now OPERATIONAL. Set a some final 1051 * registers that should be set earlier, but that the 1052 * controller ignores when in the SUSPEND state. 1053 */ 1054 ival = OHCI_GET_IVAL(fm); 1055 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 1056 fm |= OHCI_FSMPS(ival) | ival; 1057 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 1058 per = OHCI_PERIODIC(ival); /* 90% periodic */ 1059 OWRITE4(sc, OHCI_PERIODIC_START, per); 1060 1061 if (sc->sc_flags & OHCIF_SUPERIO) { 1062 /* no overcurrent protection */ 1063 desca |= OHCI_NOCP; 1064 /* 1065 * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning 1066 * that 1067 * - ports are always power switched 1068 * - don't wait for powered root hub port 1069 */ 1070 desca &= ~(__SHIFTIN(0xff, OHCI_POTPGT_MASK) | OHCI_NPS); 1071 } 1072 1073 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 1074 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 1075 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 1076 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 1077 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 1078 1079 /* 1080 * The AMD756 requires a delay before re-reading the register, 1081 * otherwise it will occasionally report 0 ports. 1082 */ 1083 sc->sc_noport = 0; 1084 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 1085 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 1086 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 1087 } 1088 1089 #ifdef OHCI_DEBUG 1090 if (ohcidebug > 5) 1091 ohci_dumpregs(sc); 1092 #endif 1093 1094 /* Set up the bus struct. */ 1095 sc->sc_bus.ub_methods = &ohci_bus_methods; 1096 sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe); 1097 1098 sc->sc_control = sc->sc_intre = 0; 1099 1100 /* Finally, turn on interrupts. */ 1101 DPRINTF("enabling %#x", sc->sc_eintrs | OHCI_MIE, 0, 0, 0); 1102 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 1103 1104 return 0; 1105 1106 bad5: 1107 for (i = 0; i < OHCI_NO_EDS; i++) 1108 ohci_free_sed(sc, sc->sc_eds[i]); 1109 bad4: 1110 ohci_free_sed(sc, sc->sc_isoc_head); 1111 bad3: 1112 ohci_free_sed(sc, sc->sc_bulk_head); 1113 bad2: 1114 ohci_free_sed(sc, sc->sc_ctrl_head); 1115 bad1: 1116 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 1117 sc->sc_hcca = NULL; 1118 return err; 1119 } 1120 1121 struct usbd_xfer * 1122 ohci_allocx(struct usbd_bus *bus, unsigned int nframes) 1123 { 1124 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1125 struct usbd_xfer *xfer; 1126 1127 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1128 if (xfer != NULL) { 1129 memset(xfer, 0, sizeof(struct ohci_xfer)); 1130 #ifdef DIAGNOSTIC 1131 xfer->ux_state = XFER_BUSY; 1132 #endif 1133 } 1134 return xfer; 1135 } 1136 1137 void 1138 ohci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1139 { 1140 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1141 1142 KASSERTMSG(xfer->ux_state == XFER_BUSY, 1143 "xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state); 1144 #ifdef DIAGNOSTIC 1145 xfer->ux_state = XFER_FREE; 1146 #endif 1147 pool_cache_put(sc->sc_xferpool, xfer); 1148 } 1149 1150 Static void 1151 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1152 { 1153 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1154 1155 *lock = &sc->sc_lock; 1156 } 1157 1158 /* 1159 * Shut down the controller when the system is going down. 1160 */ 1161 bool 1162 ohci_shutdown(device_t self, int flags) 1163 { 1164 ohci_softc_t *sc = device_private(self); 1165 1166 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1167 1168 DPRINTF("stopping the HC", 0, 0, 0, 0); 1169 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1170 return true; 1171 } 1172 1173 bool 1174 ohci_resume(device_t dv, const pmf_qual_t *qual) 1175 { 1176 ohci_softc_t *sc = device_private(dv); 1177 uint32_t ctl; 1178 1179 mutex_spin_enter(&sc->sc_intr_lock); 1180 sc->sc_bus.ub_usepolling++; 1181 mutex_spin_exit(&sc->sc_intr_lock); 1182 1183 /* Some broken BIOSes do not recover these values */ 1184 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1185 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1186 sc->sc_ctrl_head->physaddr); 1187 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1188 sc->sc_bulk_head->physaddr); 1189 if (sc->sc_intre) 1190 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1191 (OHCI_ALL_INTRS | OHCI_MIE)); 1192 if (sc->sc_control) 1193 ctl = sc->sc_control; 1194 else 1195 ctl = OREAD4(sc, OHCI_CONTROL); 1196 ctl |= OHCI_HCFS_RESUME; 1197 OWRITE4(sc, OHCI_CONTROL, ctl); 1198 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1199 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1200 OWRITE4(sc, OHCI_CONTROL, ctl); 1201 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1202 sc->sc_control = sc->sc_intre = 0; 1203 1204 mutex_spin_enter(&sc->sc_intr_lock); 1205 sc->sc_bus.ub_usepolling--; 1206 mutex_spin_exit(&sc->sc_intr_lock); 1207 1208 return true; 1209 } 1210 1211 bool 1212 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1213 { 1214 ohci_softc_t *sc = device_private(dv); 1215 uint32_t ctl; 1216 1217 mutex_spin_enter(&sc->sc_intr_lock); 1218 sc->sc_bus.ub_usepolling++; 1219 mutex_spin_exit(&sc->sc_intr_lock); 1220 1221 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1222 if (sc->sc_control == 0) { 1223 /* 1224 * Preserve register values, in case that BIOS 1225 * does not recover them. 1226 */ 1227 sc->sc_control = ctl; 1228 sc->sc_intre = OREAD4(sc, 1229 OHCI_INTERRUPT_ENABLE); 1230 } 1231 ctl |= OHCI_HCFS_SUSPEND; 1232 OWRITE4(sc, OHCI_CONTROL, ctl); 1233 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1234 1235 mutex_spin_enter(&sc->sc_intr_lock); 1236 sc->sc_bus.ub_usepolling--; 1237 mutex_spin_exit(&sc->sc_intr_lock); 1238 1239 return true; 1240 } 1241 1242 #ifdef OHCI_DEBUG 1243 void 1244 ohci_dumpregs(ohci_softc_t *sc) 1245 { 1246 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1247 1248 DPRINTF("rev=0x%08x control=0x%08x command=0x%08x", 1249 OREAD4(sc, OHCI_REVISION), 1250 OREAD4(sc, OHCI_CONTROL), 1251 OREAD4(sc, OHCI_COMMAND_STATUS), 0); 1252 DPRINTF(" intrstat=0x%08x intre=0x%08x intrd=0x%08x", 1253 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1254 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1255 OREAD4(sc, OHCI_INTERRUPT_DISABLE), 0); 1256 DPRINTF(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x", 1257 OREAD4(sc, OHCI_HCCA), 1258 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1259 OREAD4(sc, OHCI_CONTROL_HEAD_ED), 0); 1260 DPRINTF(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x", 1261 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1262 OREAD4(sc, OHCI_BULK_HEAD_ED), 1263 OREAD4(sc, OHCI_BULK_CURRENT_ED) ,0); 1264 DPRINTF(" done=0x%08x fmival=0x%08x fmrem=0x%08x", 1265 OREAD4(sc, OHCI_DONE_HEAD), 1266 OREAD4(sc, OHCI_FM_INTERVAL), 1267 OREAD4(sc, OHCI_FM_REMAINING), 0); 1268 DPRINTF(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x", 1269 OREAD4(sc, OHCI_FM_NUMBER), 1270 OREAD4(sc, OHCI_PERIODIC_START), 1271 OREAD4(sc, OHCI_LS_THRESHOLD), 0); 1272 DPRINTF(" desca=0x%08x descb=0x%08x stat=0x%08x", 1273 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1274 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1275 OREAD4(sc, OHCI_RH_STATUS), 0); 1276 DPRINTF(" port1=0x%08x port2=0x%08x", 1277 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1278 OREAD4(sc, OHCI_RH_PORT_STATUS(2)), 0, 0); 1279 DPRINTF(" HCCA: frame_number=0x%04x done_head=0x%08x", 1280 O32TOH(sc->sc_hcca->hcca_frame_number), 1281 O32TOH(sc->sc_hcca->hcca_done_head), 0, 0); 1282 } 1283 #endif 1284 1285 Static int ohci_intr1(ohci_softc_t *); 1286 1287 int 1288 ohci_intr(void *p) 1289 { 1290 ohci_softc_t *sc = p; 1291 int ret = 0; 1292 1293 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1294 1295 if (sc == NULL) 1296 return 0; 1297 1298 mutex_spin_enter(&sc->sc_intr_lock); 1299 1300 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1301 goto done; 1302 1303 /* If we get an interrupt while polling, then just ignore it. */ 1304 if (sc->sc_bus.ub_usepolling) { 1305 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1306 /* for level triggered intrs, should do something to ack */ 1307 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1308 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1309 1310 goto done; 1311 } 1312 1313 ret = ohci_intr1(sc); 1314 1315 done: 1316 mutex_spin_exit(&sc->sc_intr_lock); 1317 return ret; 1318 } 1319 1320 Static int 1321 ohci_intr1(ohci_softc_t *sc) 1322 { 1323 uint32_t intrs, eintrs; 1324 1325 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1326 1327 /* In case the interrupt occurs before initialization has completed. */ 1328 if (sc == NULL || sc->sc_hcca == NULL) { 1329 #ifdef DIAGNOSTIC 1330 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1331 #endif 1332 return 0; 1333 } 1334 1335 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1336 1337 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1338 if (!intrs) 1339 return 0; 1340 1341 /* Acknowledge */ 1342 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); 1343 eintrs = intrs & sc->sc_eintrs; 1344 DPRINTFN(7, "sc=%p", sc, 0, 0, 0); 1345 DPRINTFN(7, "intrs=%#x(%#x) eintrs=%#x(%#x)", 1346 intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), eintrs, 1347 sc->sc_eintrs); 1348 1349 if (!eintrs) { 1350 return 0; 1351 } 1352 1353 if (eintrs & OHCI_SO) { 1354 sc->sc_overrun_cnt++; 1355 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1356 printf("%s: %u scheduling overruns\n", 1357 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1358 sc->sc_overrun_cnt = 0; 1359 } 1360 /* XXX do what */ 1361 eintrs &= ~OHCI_SO; 1362 } 1363 if (eintrs & OHCI_WDH) { 1364 /* 1365 * We block the interrupt below, and reenable it later from 1366 * ohci_softintr(). 1367 */ 1368 usb_schedsoftintr(&sc->sc_bus); 1369 } 1370 if (eintrs & OHCI_RD) { 1371 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1372 /* XXX process resume detect */ 1373 } 1374 if (eintrs & OHCI_UE) { 1375 printf("%s: unrecoverable error, controller halted\n", 1376 device_xname(sc->sc_dev)); 1377 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1378 /* XXX what else */ 1379 } 1380 if (eintrs & OHCI_RHSC) { 1381 /* 1382 * We block the interrupt below, and reenable it later from 1383 * a timeout. 1384 */ 1385 softint_schedule(sc->sc_rhsc_si); 1386 } 1387 1388 if (eintrs != 0) { 1389 /* Block unprocessed interrupts. */ 1390 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1391 sc->sc_eintrs &= ~eintrs; 1392 DPRINTF("sc %p blocking intrs 0x%x", sc, eintrs, 0, 0); 1393 } 1394 1395 return 1; 1396 } 1397 1398 void 1399 ohci_rhsc_enable(void *v_sc) 1400 { 1401 ohci_softc_t *sc = v_sc; 1402 1403 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1404 DPRINTF("sc %p", sc, 0, 0, 0); 1405 mutex_spin_enter(&sc->sc_intr_lock); 1406 sc->sc_eintrs |= OHCI_RHSC; 1407 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1408 mutex_spin_exit(&sc->sc_intr_lock); 1409 } 1410 1411 #ifdef OHCI_DEBUG 1412 const char *ohci_cc_strs[] = { 1413 "NO_ERROR", 1414 "CRC", 1415 "BIT_STUFFING", 1416 "DATA_TOGGLE_MISMATCH", 1417 "STALL", 1418 "DEVICE_NOT_RESPONDING", 1419 "PID_CHECK_FAILURE", 1420 "UNEXPECTED_PID", 1421 "DATA_OVERRUN", 1422 "DATA_UNDERRUN", 1423 "BUFFER_OVERRUN", 1424 "BUFFER_UNDERRUN", 1425 "reserved", 1426 "reserved", 1427 "NOT_ACCESSED", 1428 "NOT_ACCESSED", 1429 }; 1430 #endif 1431 1432 void 1433 ohci_softintr(void *v) 1434 { 1435 struct usbd_bus *bus = v; 1436 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1437 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1438 ohci_soft_td_t *std, *sdone, *stdnext; 1439 struct usbd_xfer *xfer; 1440 struct ohci_pipe *opipe; 1441 int len, cc; 1442 int i, j, actlen, iframes, uedir; 1443 ohci_physaddr_t done; 1444 1445 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1446 1447 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1448 1449 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1450 sizeof(sc->sc_hcca->hcca_done_head), 1451 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1452 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1453 sc->sc_hcca->hcca_done_head = 0; 1454 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1455 sizeof(sc->sc_hcca->hcca_done_head), 1456 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1457 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1458 sc->sc_eintrs |= OHCI_WDH; 1459 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1460 1461 /* Reverse the done list. */ 1462 for (sdone = NULL, sidone = NULL; done != 0; ) { 1463 std = ohci_hash_find_td(sc, done); 1464 if (std != NULL) { 1465 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1466 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1467 std->dnext = sdone; 1468 done = O32TOH(std->td.td_nexttd); 1469 sdone = std; 1470 DPRINTFN(10, "add TD %p", std, 0, 0, 0); 1471 continue; 1472 } 1473 sitd = ohci_hash_find_itd(sc, done); 1474 if (sitd != NULL) { 1475 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1476 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1477 sitd->dnext = sidone; 1478 done = O32TOH(sitd->itd.itd_nextitd); 1479 sidone = sitd; 1480 DPRINTFN(5, "add ITD %p", sitd, 0, 0, 0); 1481 continue; 1482 } 1483 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1484 (u_long)done); 1485 break; 1486 } 1487 1488 DPRINTFN(10, "sdone=%p sidone=%p", sdone, sidone, 0, 0); 1489 DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0); 1490 #ifdef OHCI_DEBUG 1491 if (ohcidebug > 10) { 1492 for (std = sdone; std; std = std->dnext) 1493 ohci_dump_td(sc, std); 1494 } 1495 #endif 1496 DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0); 1497 1498 for (std = sdone; std; std = stdnext) { 1499 xfer = std->xfer; 1500 stdnext = std->dnext; 1501 DPRINTFN(10, "std=%p xfer=%p hcpriv=%p", std, xfer, 1502 xfer ? xfer->ux_hcpriv : 0, 0); 1503 if (xfer == NULL) { 1504 /* 1505 * xfer == NULL: There seems to be no xfer associated 1506 * with this TD. It is tailp that happened to end up on 1507 * the done queue. 1508 * Shouldn't happen, but some chips are broken(?). 1509 */ 1510 continue; 1511 } 1512 if (xfer->ux_status == USBD_CANCELLED || 1513 xfer->ux_status == USBD_TIMEOUT) { 1514 DPRINTF("cancel/timeout %p", xfer, 0, 0, 0); 1515 /* Handled by abort routine. */ 1516 continue; 1517 } 1518 callout_stop(&xfer->ux_callout); 1519 1520 len = std->len; 1521 if (std->td.td_cbp != 0) 1522 len -= O32TOH(std->td.td_be) - 1523 O32TOH(std->td.td_cbp) + 1; 1524 DPRINTFN(10, "len=%d, flags=0x%x", len, std->flags, 0, 0); 1525 if (std->flags & OHCI_ADD_LEN) 1526 xfer->ux_actlen += len; 1527 1528 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1529 if (cc == OHCI_CC_NO_ERROR) { 1530 if (std->flags & OHCI_CALL_DONE) { 1531 xfer->ux_status = USBD_NORMAL_COMPLETION; 1532 usb_transfer_complete(xfer); 1533 } 1534 ohci_hash_rem_td(sc, std); 1535 } else { 1536 /* 1537 * Endpoint is halted. First unlink all the TDs 1538 * belonging to the failed transfer, and then restart 1539 * the endpoint. 1540 */ 1541 ohci_soft_td_t *p, *n; 1542 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1543 1544 DPRINTFN(15, "error cc=%d", 1545 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 0, 0, 0); 1546 1547 /* remove xfer's TDs from the hash */ 1548 for (p = std; p->xfer == xfer; p = n) { 1549 n = p->nexttd; 1550 ohci_hash_rem_td(sc, p); 1551 } 1552 1553 /* clear halt */ 1554 opipe->sed->ed.ed_headp = HTOO32(p->physaddr); 1555 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1556 1557 if (cc == OHCI_CC_STALL) 1558 xfer->ux_status = USBD_STALLED; 1559 else 1560 xfer->ux_status = USBD_IOERROR; 1561 usb_transfer_complete(xfer); 1562 } 1563 } 1564 DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0); 1565 #ifdef OHCI_DEBUG 1566 if (ohcidebug > 10) { 1567 DPRINTFN(10, "ITD done", 0, 0, 0, 0); 1568 for (sitd = sidone; sitd; sitd = sitd->dnext) 1569 ohci_dump_itd(sc, sitd); 1570 } 1571 #endif 1572 DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0); 1573 1574 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1575 xfer = sitd->xfer; 1576 sitdnext = sitd->dnext; 1577 DPRINTFN(1, "sitd=%p xfer=%p hcpriv=%p", sitd, xfer, 1578 xfer ? xfer->ux_hcpriv : 0, 0); 1579 if (xfer == NULL) 1580 continue; 1581 if (xfer->ux_status == USBD_CANCELLED || 1582 xfer->ux_status == USBD_TIMEOUT) { 1583 DPRINTF("cancel/timeout %p", xfer, 0, 0, 0); 1584 /* Handled by abort routine. */ 1585 continue; 1586 } 1587 KASSERT(!sitd->isdone); 1588 #ifdef DIAGNOSTIC 1589 sitd->isdone = true; 1590 #endif 1591 if (sitd->flags & OHCI_CALL_DONE) { 1592 ohci_soft_itd_t *next; 1593 1594 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1595 opipe->isoc.inuse -= xfer->ux_nframes; 1596 uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc-> 1597 bEndpointAddress); 1598 xfer->ux_status = USBD_NORMAL_COMPLETION; 1599 actlen = 0; 1600 for (i = 0, sitd = xfer->ux_hcpriv;; 1601 sitd = next) { 1602 next = sitd->nextitd; 1603 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1604 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1605 xfer->ux_status = USBD_IOERROR; 1606 /* For input, update frlengths with actual */ 1607 /* XXX anything necessary for output? */ 1608 if (uedir == UE_DIR_IN && 1609 xfer->ux_status == USBD_NORMAL_COMPLETION) { 1610 iframes = OHCI_ITD_GET_FC(O32TOH( 1611 sitd->itd.itd_flags)); 1612 for (j = 0; j < iframes; i++, j++) { 1613 len = O16TOH(sitd-> 1614 itd.itd_offset[j]); 1615 if ((OHCI_ITD_PSW_GET_CC(len) & 1616 OHCI_CC_NOT_ACCESSED_MASK) 1617 == OHCI_CC_NOT_ACCESSED) 1618 len = 0; 1619 else 1620 len = OHCI_ITD_PSW_LENGTH(len); 1621 xfer->ux_frlengths[i] = len; 1622 actlen += len; 1623 } 1624 } 1625 if (sitd->flags & OHCI_CALL_DONE) 1626 break; 1627 ohci_hash_rem_itd(sc, sitd); 1628 1629 } 1630 ohci_hash_rem_itd(sc, sitd); 1631 if (uedir == UE_DIR_IN && 1632 xfer->ux_status == USBD_NORMAL_COMPLETION) 1633 xfer->ux_actlen = actlen; 1634 xfer->ux_hcpriv = NULL; 1635 1636 usb_transfer_complete(xfer); 1637 } 1638 } 1639 1640 if (sc->sc_softwake) { 1641 sc->sc_softwake = 0; 1642 cv_broadcast(&sc->sc_softwake_cv); 1643 } 1644 1645 DPRINTFN(10, "done", 0, 0, 0, 0); 1646 } 1647 1648 void 1649 ohci_device_ctrl_done(struct usbd_xfer *xfer) 1650 { 1651 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1652 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1653 int len = UGETW(xfer->ux_request.wLength); 1654 int isread = (xfer->ux_request.bmRequestType & UT_READ); 1655 1656 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1657 DPRINTFN(10, "xfer=%p", xfer, 0, 0, 0); 1658 1659 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1660 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 1661 1662 if (len) 1663 usb_syncmem(&xfer->ux_dmabuf, 0, len, 1664 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1665 usb_syncmem(&opipe->ctrl.reqdma, 0, 1666 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1667 } 1668 1669 void 1670 ohci_device_intr_done(struct usbd_xfer *xfer) 1671 { 1672 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 1673 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1674 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1675 ohci_soft_ed_t *sed = opipe->sed; 1676 int isread = 1677 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1678 1679 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1680 DPRINTFN(10, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0); 1681 1682 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1683 1684 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1685 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1686 if (xfer->ux_pipe->up_repeat) { 1687 ohci_soft_td_t *data, *last, *tail; 1688 int len = xfer->ux_length; 1689 1690 /* Use "tail" TD and loan our first TD to next transfer */ 1691 data = opipe->tail.td; 1692 opipe->tail.td = ox->ox_stds[0]; 1693 ox->ox_stds[0] = data; 1694 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 1695 1696 tail = opipe->tail.td; /* point at sentinel */ 1697 memset(&tail->td, 0, sizeof(tail->td)); 1698 tail->nexttd = NULL; 1699 tail->xfer = NULL; 1700 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 1701 BUS_DMASYNC_PREWRITE); 1702 1703 /* We want interrupt at the end of the transfer. */ 1704 last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 1705 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 1706 1707 last->td.td_nexttd = HTOO32(tail->physaddr); 1708 last->nexttd = tail; 1709 last->flags |= OHCI_CALL_DONE; 1710 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 1711 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1712 1713 xfer->ux_hcpriv = data; 1714 xfer->ux_actlen = 0; 1715 1716 /* Insert ED in schedule */ 1717 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1718 usb_syncmem(&sed->dma, 1719 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1720 sizeof(sed->ed.ed_tailp), 1721 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1722 } 1723 } 1724 1725 void 1726 ohci_device_bulk_done(struct usbd_xfer *xfer) 1727 { 1728 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1729 1730 int isread = 1731 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1732 1733 KASSERT(mutex_owned(&sc->sc_lock)); 1734 1735 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1736 DPRINTFN(10, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0); 1737 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1738 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1739 } 1740 1741 Static void 1742 ohci_rhsc_softint(void *arg) 1743 { 1744 ohci_softc_t *sc = arg; 1745 1746 mutex_enter(&sc->sc_lock); 1747 1748 ohci_rhsc(sc, sc->sc_intrxfer); 1749 1750 /* Do not allow RHSC interrupts > 1 per second */ 1751 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1752 1753 mutex_exit(&sc->sc_lock); 1754 } 1755 1756 void 1757 ohci_rhsc(ohci_softc_t *sc, struct usbd_xfer *xfer) 1758 { 1759 u_char *p; 1760 int i, m; 1761 int hstatus __unused; 1762 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1763 1764 KASSERT(mutex_owned(&sc->sc_lock)); 1765 1766 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1767 DPRINTF("sc=%p xfer=%p hstatus=0x%08x", sc, xfer, hstatus, 0); 1768 1769 if (xfer == NULL) { 1770 /* Just ignore the change. */ 1771 return; 1772 } 1773 1774 p = xfer->ux_buf; 1775 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 1776 memset(p, 0, xfer->ux_length); 1777 for (i = 1; i <= m; i++) { 1778 /* Pick out CHANGE bits from the status reg. */ 1779 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1780 p[i/8] |= 1 << (i%8); 1781 } 1782 DPRINTF("change=0x%02x", *p, 0, 0, 0); 1783 xfer->ux_actlen = xfer->ux_length; 1784 xfer->ux_status = USBD_NORMAL_COMPLETION; 1785 1786 usb_transfer_complete(xfer); 1787 } 1788 1789 void 1790 ohci_root_intr_done(struct usbd_xfer *xfer) 1791 { 1792 } 1793 1794 /* 1795 * Wait here until controller claims to have an interrupt. 1796 * Then call ohci_intr and return. Use timeout to avoid waiting 1797 * too long. 1798 */ 1799 void 1800 ohci_waitintr(ohci_softc_t *sc, struct usbd_xfer *xfer) 1801 { 1802 int timo; 1803 uint32_t intrs; 1804 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1805 1806 mutex_enter(&sc->sc_lock); 1807 1808 xfer->ux_status = USBD_IN_PROGRESS; 1809 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1810 usb_delay_ms(&sc->sc_bus, 1); 1811 if (sc->sc_dying) 1812 break; 1813 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 1814 DPRINTFN(15, "intrs 0x%04x", intrs, 0, 0, 0); 1815 #ifdef OHCI_DEBUG 1816 if (ohcidebug > 15) 1817 ohci_dumpregs(sc); 1818 #endif 1819 if (intrs) { 1820 mutex_spin_enter(&sc->sc_intr_lock); 1821 ohci_intr1(sc); 1822 mutex_spin_exit(&sc->sc_intr_lock); 1823 if (xfer->ux_status != USBD_IN_PROGRESS) 1824 goto done; 1825 } 1826 } 1827 1828 /* Timeout */ 1829 DPRINTF("timeout", 0, 0, 0, 0); 1830 xfer->ux_status = USBD_TIMEOUT; 1831 usb_transfer_complete(xfer); 1832 1833 done: 1834 mutex_exit(&sc->sc_lock); 1835 } 1836 1837 void 1838 ohci_poll(struct usbd_bus *bus) 1839 { 1840 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1841 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1842 1843 #ifdef OHCI_DEBUG 1844 static int last; 1845 int new; 1846 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1847 if (new != last) { 1848 DPRINTFN(10, "intrs=0x%04x", new, 0, 0, 0); 1849 last = new; 1850 } 1851 #endif 1852 sc->sc_eintrs |= OHCI_WDH; 1853 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1854 mutex_spin_enter(&sc->sc_intr_lock); 1855 ohci_intr1(sc); 1856 mutex_spin_exit(&sc->sc_intr_lock); 1857 } 1858 } 1859 1860 /* 1861 * Add an ED to the schedule. Called with USB lock held. 1862 */ 1863 Static void 1864 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1865 { 1866 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1867 DPRINTFN(8, "sed=%p head=%p", sed, head, 0, 0); 1868 1869 KASSERT(mutex_owned(&sc->sc_lock)); 1870 1871 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1872 sizeof(head->ed.ed_nexted), 1873 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1874 sed->next = head->next; 1875 sed->ed.ed_nexted = head->ed.ed_nexted; 1876 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1877 sizeof(sed->ed.ed_nexted), 1878 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1879 head->next = sed; 1880 head->ed.ed_nexted = HTOO32(sed->physaddr); 1881 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1882 sizeof(head->ed.ed_nexted), 1883 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1884 } 1885 1886 /* 1887 * Remove an ED from the schedule. Called with USB lock held. 1888 */ 1889 Static void 1890 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1891 { 1892 ohci_soft_ed_t *p; 1893 1894 KASSERT(mutex_owned(&sc->sc_lock)); 1895 1896 /* XXX */ 1897 for (p = head; p != NULL && p->next != sed; p = p->next) 1898 ; 1899 KASSERT(p != NULL); 1900 1901 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1902 sizeof(sed->ed.ed_nexted), 1903 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1904 p->next = sed->next; 1905 p->ed.ed_nexted = sed->ed.ed_nexted; 1906 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1907 sizeof(p->ed.ed_nexted), 1908 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1909 } 1910 1911 /* 1912 * When a transfer is completed the TD is added to the done queue by 1913 * the host controller. This queue is the processed by software. 1914 * Unfortunately the queue contains the physical address of the TD 1915 * and we have no simple way to translate this back to a kernel address. 1916 * To make the translation possible (and fast) we use a hash table of 1917 * TDs currently in the schedule. The physical address is used as the 1918 * hash value. 1919 */ 1920 1921 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1922 /* Called with USB lock held. */ 1923 void 1924 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1925 { 1926 int h = HASH(std->physaddr); 1927 1928 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1929 1930 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1931 } 1932 1933 /* Called with USB lock held. */ 1934 void 1935 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1936 { 1937 1938 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1939 1940 LIST_REMOVE(std, hnext); 1941 } 1942 1943 ohci_soft_td_t * 1944 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1945 { 1946 int h = HASH(a); 1947 ohci_soft_td_t *std; 1948 1949 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1950 std != NULL; 1951 std = LIST_NEXT(std, hnext)) 1952 if (std->physaddr == a) 1953 return std; 1954 return NULL; 1955 } 1956 1957 /* Called with USB lock held. */ 1958 void 1959 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1960 { 1961 int h = HASH(sitd->physaddr); 1962 1963 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1964 1965 KASSERT(mutex_owned(&sc->sc_lock)); 1966 1967 DPRINTFN(10, "sitd=%p physaddr=0x%08lx", sitd, (u_long)sitd->physaddr, 1968 0, 0); 1969 1970 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1971 } 1972 1973 /* Called with USB lock held. */ 1974 void 1975 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1976 { 1977 1978 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1979 1980 KASSERT(mutex_owned(&sc->sc_lock)); 1981 1982 DPRINTFN(10, "sitd=%p physaddr=0x%08lx", sitd, (u_long)sitd->physaddr, 1983 0, 0); 1984 1985 LIST_REMOVE(sitd, hnext); 1986 } 1987 1988 ohci_soft_itd_t * 1989 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1990 { 1991 int h = HASH(a); 1992 ohci_soft_itd_t *sitd; 1993 1994 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1995 sitd != NULL; 1996 sitd = LIST_NEXT(sitd, hnext)) 1997 if (sitd->physaddr == a) 1998 return sitd; 1999 return NULL; 2000 } 2001 2002 void 2003 ohci_timeout(void *addr) 2004 { 2005 struct usbd_xfer *xfer = addr; 2006 struct ohci_xfer *oxfer = OHCI_XFER2OXFER(xfer); 2007 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2008 2009 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2010 DPRINTF("oxfer=%p", oxfer, 0, 0, 0); 2011 2012 if (sc->sc_dying) { 2013 mutex_enter(&sc->sc_lock); 2014 ohci_abort_xfer(xfer, USBD_TIMEOUT); 2015 mutex_exit(&sc->sc_lock); 2016 return; 2017 } 2018 2019 /* Execute the abort in a process context. */ 2020 usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr, 2021 USB_TASKQ_MPSAFE); 2022 usb_add_task(xfer->ux_pipe->up_dev, &oxfer->abort_task, 2023 USB_TASKQ_HC); 2024 } 2025 2026 void 2027 ohci_timeout_task(void *addr) 2028 { 2029 struct usbd_xfer *xfer = addr; 2030 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2031 2032 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2033 2034 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2035 2036 mutex_enter(&sc->sc_lock); 2037 ohci_abort_xfer(xfer, USBD_TIMEOUT); 2038 mutex_exit(&sc->sc_lock); 2039 } 2040 2041 #ifdef OHCI_DEBUG 2042 void 2043 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 2044 { 2045 for (; std; std = std->nexttd) { 2046 ohci_dump_td(sc, std); 2047 KASSERTMSG(std->nexttd == NULL || std != std->nexttd, 2048 "std %p next %p", std, std->nexttd); 2049 } 2050 } 2051 2052 void 2053 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 2054 { 2055 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2056 2057 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2058 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2059 2060 uint32_t flags = O32TOH(std->td.td_flags); 2061 DPRINTF("TD(%p) at %08lx:", std, (u_long)std->physaddr, 0, 0); 2062 DPRINTF(" round=%d DP=%x DI=%x T=%x", 2063 !!(flags & OHCI_TD_R), 2064 __SHIFTOUT(flags, OHCI_TD_DP_MASK), 2065 OHCI_TD_GET_DI(flags), 2066 __SHIFTOUT(flags, OHCI_TD_TOGGLE_MASK)); 2067 DPRINTF(" EC=%d CC=%d", OHCI_TD_GET_EC(flags), OHCI_TD_GET_CC(flags), 2068 0, 0); 2069 DPRINTF(" cbp=0x%08lx nexttd=0x%08lx be=0x%08lx", 2070 (u_long)O32TOH(std->td.td_cbp), 2071 (u_long)O32TOH(std->td.td_nexttd), 2072 (u_long)O32TOH(std->td.td_be), 0); 2073 } 2074 2075 void 2076 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2077 { 2078 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2079 2080 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 2081 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2082 2083 uint32_t flags = O32TOH(sitd->itd.itd_flags); 2084 DPRINTF("ITD(%p) at %08lx", sitd, (u_long)sitd->physaddr, 0, 0); 2085 DPRINTF(" sf=%d di=%d fc=%d cc=%d", 2086 OHCI_ITD_GET_SF(flags), OHCI_ITD_GET_DI(flags), 2087 OHCI_ITD_GET_FC(flags), OHCI_ITD_GET_CC(flags)); 2088 DPRINTF(" bp0=0x%08x next=0x%08x be=0x%08x", 2089 O32TOH(sitd->itd.itd_bp0), 2090 O32TOH(sitd->itd.itd_nextitd), 2091 O32TOH(sitd->itd.itd_be), 0); 2092 CTASSERT(OHCI_ITD_NOFFSET == 8); 2093 DPRINTF(" offs[0] = 0x%04x offs[1] = 0x%04x " 2094 "offs[2] = 0x%04x offs[3] = 0x%04x", 2095 O16TOH(sitd->itd.itd_offset[0]), 2096 O16TOH(sitd->itd.itd_offset[1]), 2097 O16TOH(sitd->itd.itd_offset[2]), 2098 O16TOH(sitd->itd.itd_offset[3])); 2099 DPRINTF(" offs[4] = 0x%04x offs[5] = 0x%04x " 2100 "offs[6] = 0x%04x offs[7] = 0x%04x", 2101 O16TOH(sitd->itd.itd_offset[4]), 2102 O16TOH(sitd->itd.itd_offset[5]), 2103 O16TOH(sitd->itd.itd_offset[6]), 2104 O16TOH(sitd->itd.itd_offset[7])); 2105 } 2106 2107 void 2108 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2109 { 2110 for (; sitd; sitd = sitd->nextitd) 2111 ohci_dump_itd(sc, sitd); 2112 } 2113 2114 void 2115 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2116 { 2117 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2118 2119 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2120 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2121 2122 uint32_t flags = O32TOH(sed->ed.ed_flags); 2123 DPRINTF("ED(%p) at 0x%08lx:", sed, sed->physaddr, 0, 0); 2124 DPRINTF(" addr=%d endpt=%d maxp=%d", 2125 OHCI_ED_GET_FA(flags), 2126 OHCI_ED_GET_EN(flags), 2127 OHCI_ED_GET_MAXP(flags), 2128 0); 2129 DPRINTF(" dir=%d speed=%d skip=%d iso=%d", 2130 __SHIFTOUT(flags, OHCI_ED_DIR_MASK), 2131 !!(flags & OHCI_ED_SPEED), 2132 !!(flags & OHCI_ED_SKIP), 2133 !!(flags & OHCI_ED_FORMAT_ISO)); 2134 DPRINTF(" tailp=0x%08lx", (u_long)O32TOH(sed->ed.ed_tailp), 2135 0, 0, 0); 2136 DPRINTF(" headp=0x%08lx nexted=0x%08lx halted=%d carry=%d", 2137 O32TOH(sed->ed.ed_headp), O32TOH(sed->ed.ed_nexted), 2138 !!(O32TOH(sed->ed.ed_headp) & OHCI_HALTED), 2139 !!(O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 2140 } 2141 #endif 2142 2143 usbd_status 2144 ohci_open(struct usbd_pipe *pipe) 2145 { 2146 struct usbd_device *dev = pipe->up_dev; 2147 struct usbd_bus *bus = dev->ud_bus; 2148 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2149 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 2150 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2151 uint8_t addr = dev->ud_addr; 2152 uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2153 ohci_soft_ed_t *sed; 2154 ohci_soft_td_t *std; 2155 ohci_soft_itd_t *sitd; 2156 ohci_physaddr_t tdphys; 2157 uint32_t fmt; 2158 usbd_status err = USBD_NOMEM; 2159 int ival; 2160 2161 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2162 DPRINTFN(1, "pipe=%p, addr=%d, endpt=%d (%d)", pipe, addr, 2163 ed->bEndpointAddress, bus->ub_rhaddr); 2164 2165 if (sc->sc_dying) { 2166 return USBD_IOERROR; 2167 } 2168 2169 std = NULL; 2170 sed = NULL; 2171 2172 if (addr == bus->ub_rhaddr) { 2173 switch (ed->bEndpointAddress) { 2174 case USB_CONTROL_ENDPOINT: 2175 pipe->up_methods = &roothub_ctrl_methods; 2176 break; 2177 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 2178 pipe->up_methods = &ohci_root_intr_methods; 2179 break; 2180 default: 2181 err = USBD_INVAL; 2182 goto bad; 2183 } 2184 } else { 2185 sed = ohci_alloc_sed(sc); 2186 if (sed == NULL) 2187 goto bad; 2188 opipe->sed = sed; 2189 if (xfertype == UE_ISOCHRONOUS) { 2190 sitd = ohci_alloc_sitd(sc); 2191 if (sitd == NULL) 2192 goto bad; 2193 2194 opipe->tail.itd = sitd; 2195 tdphys = sitd->physaddr; 2196 fmt = OHCI_ED_FORMAT_ISO; 2197 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2198 fmt |= OHCI_ED_DIR_IN; 2199 else 2200 fmt |= OHCI_ED_DIR_OUT; 2201 } else { 2202 std = ohci_alloc_std(sc); 2203 if (std == NULL) 2204 goto bad; 2205 2206 opipe->tail.td = std; 2207 tdphys = std->physaddr; 2208 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2209 } 2210 sed->ed.ed_flags = HTOO32( 2211 OHCI_ED_SET_FA(addr) | 2212 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2213 (dev->ud_speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2214 fmt | 2215 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2216 sed->ed.ed_headp = HTOO32(tdphys | 2217 (pipe->up_endpoint->ue_toggle ? OHCI_TOGGLECARRY : 0)); 2218 sed->ed.ed_tailp = HTOO32(tdphys); 2219 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2220 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2221 2222 switch (xfertype) { 2223 case UE_CONTROL: 2224 pipe->up_methods = &ohci_device_ctrl_methods; 2225 err = usb_allocmem(&sc->sc_bus, 2226 sizeof(usb_device_request_t), 2227 0, &opipe->ctrl.reqdma); 2228 if (err) 2229 goto bad; 2230 mutex_enter(&sc->sc_lock); 2231 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2232 mutex_exit(&sc->sc_lock); 2233 break; 2234 case UE_INTERRUPT: 2235 pipe->up_methods = &ohci_device_intr_methods; 2236 ival = pipe->up_interval; 2237 if (ival == USBD_DEFAULT_INTERVAL) 2238 ival = ed->bInterval; 2239 err = ohci_device_setintr(sc, opipe, ival); 2240 if (err) 2241 goto bad; 2242 break; 2243 case UE_ISOCHRONOUS: 2244 pipe->up_methods = &ohci_device_isoc_methods; 2245 return ohci_setup_isoc(pipe); 2246 case UE_BULK: 2247 pipe->up_methods = &ohci_device_bulk_methods; 2248 mutex_enter(&sc->sc_lock); 2249 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2250 mutex_exit(&sc->sc_lock); 2251 break; 2252 } 2253 } 2254 2255 return USBD_NORMAL_COMPLETION; 2256 2257 bad: 2258 if (std != NULL) { 2259 ohci_free_std(sc, std); 2260 } 2261 if (sed != NULL) 2262 ohci_free_sed(sc, sed); 2263 return err; 2264 2265 } 2266 2267 /* 2268 * Close a reqular pipe. 2269 * Assumes that there are no pending transactions. 2270 */ 2271 void 2272 ohci_close_pipe(struct usbd_pipe *pipe, ohci_soft_ed_t *head) 2273 { 2274 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2275 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2276 ohci_soft_ed_t *sed = opipe->sed; 2277 2278 KASSERT(mutex_owned(&sc->sc_lock)); 2279 2280 #ifdef DIAGNOSTIC 2281 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2282 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2283 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2284 ohci_soft_td_t *std; 2285 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2286 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2287 "tl=0x%x pipe=%p, std=%p\n", sed, 2288 (int)O32TOH(sed->ed.ed_headp), 2289 (int)O32TOH(sed->ed.ed_tailp), 2290 pipe, std); 2291 #ifdef OHCI_DEBUG 2292 usbd_dump_pipe(&opipe->pipe); 2293 ohci_dump_ed(sc, sed); 2294 if (std) 2295 ohci_dump_td(sc, std); 2296 #endif 2297 usb_delay_ms(&sc->sc_bus, 2); 2298 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2299 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2300 printf("ohci_close_pipe: pipe still not empty\n"); 2301 } 2302 #endif 2303 ohci_rem_ed(sc, sed, head); 2304 /* Make sure the host controller is not touching this ED */ 2305 usb_delay_ms(&sc->sc_bus, 1); 2306 pipe->up_endpoint->ue_toggle = 2307 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2308 ohci_free_sed_locked(sc, opipe->sed); 2309 } 2310 2311 /* 2312 * Abort a device request. 2313 * If this routine is called at splusb() it guarantees that the request 2314 * will be removed from the hardware scheduling and that the callback 2315 * for it will be called with USBD_CANCELLED status. 2316 * It's impossible to guarantee that the requested transfer will not 2317 * have happened since the hardware runs concurrently. 2318 * If the transaction has already happened we rely on the ordinary 2319 * interrupt processing to process it. 2320 * XXX This is most probably wrong. 2321 * XXXMRG this doesn't make sense anymore. 2322 */ 2323 void 2324 ohci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2325 { 2326 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2327 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2328 ohci_soft_ed_t *sed = opipe->sed; 2329 ohci_soft_td_t *p, *n; 2330 ohci_physaddr_t headp; 2331 int hit; 2332 int wake; 2333 2334 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2335 DPRINTF("xfer=%p pipe=%p sed=%p", xfer, opipe,sed, 0); 2336 2337 KASSERT(mutex_owned(&sc->sc_lock)); 2338 ASSERT_SLEEPABLE(); 2339 2340 if (sc->sc_dying) { 2341 /* If we're dying, just do the software part. */ 2342 xfer->ux_status = status; /* make software ignore it */ 2343 callout_halt(&xfer->ux_callout, &sc->sc_lock); 2344 usb_transfer_complete(xfer); 2345 return; 2346 } 2347 2348 /* 2349 * If an abort is already in progress then just wait for it to 2350 * complete and return. 2351 */ 2352 if (xfer->ux_hcflags & UXFER_ABORTING) { 2353 DPRINTFN(2, "already aborting", 0, 0, 0, 0); 2354 #ifdef DIAGNOSTIC 2355 if (status == USBD_TIMEOUT) 2356 printf("%s: TIMEOUT while aborting\n", __func__); 2357 #endif 2358 /* Override the status which might be USBD_TIMEOUT. */ 2359 xfer->ux_status = status; 2360 DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0); 2361 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2362 while (xfer->ux_hcflags & UXFER_ABORTING) 2363 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2364 goto done; 2365 } 2366 xfer->ux_hcflags |= UXFER_ABORTING; 2367 2368 /* 2369 * Step 1: Make interrupt routine and hardware ignore xfer. 2370 */ 2371 xfer->ux_status = status; /* make software ignore it */ 2372 callout_stop(&xfer->ux_callout); 2373 DPRINTFN(1, "stop ed=%p", sed, 0, 0, 0); 2374 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2375 sizeof(sed->ed.ed_flags), 2376 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2377 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2378 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2379 sizeof(sed->ed.ed_flags), 2380 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2381 2382 /* 2383 * Step 2: Wait until we know hardware has finished any possible 2384 * use of the xfer. Also make sure the soft interrupt routine 2385 * has run. 2386 */ 2387 /* Hardware finishes in 1ms */ 2388 usb_delay_ms_locked(opipe->pipe.up_dev->ud_bus, 20, &sc->sc_lock); 2389 sc->sc_softwake = 1; 2390 usb_schedsoftintr(&sc->sc_bus); 2391 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2392 2393 /* 2394 * Step 3: Remove any vestiges of the xfer from the hardware. 2395 * The complication here is that the hardware may have executed 2396 * beyond the xfer we're trying to abort. So as we're scanning 2397 * the TDs of this xfer we check if the hardware points to 2398 * any of them. 2399 */ 2400 p = xfer->ux_hcpriv; 2401 KASSERT(p); 2402 2403 #ifdef OHCI_DEBUG 2404 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2405 2406 if (ohcidebug > 1) { 2407 DPRINTF("sed:", 0, 0, 0, 0); 2408 ohci_dump_ed(sc, sed); 2409 ohci_dump_tds(sc, p); 2410 } 2411 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2412 #endif 2413 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2414 hit = 0; 2415 for (; p->xfer == xfer; p = n) { 2416 hit |= headp == p->physaddr; 2417 n = p->nexttd; 2418 ohci_hash_rem_td(sc, p); 2419 } 2420 /* Zap headp register if hardware pointed inside the xfer. */ 2421 if (hit) { 2422 DPRINTFN(1, "set hd=0x%08x, tl=0x%08x", (int)p->physaddr, 2423 (int)O32TOH(sed->ed.ed_tailp), 0, 0); 2424 sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */ 2425 usb_syncmem(&sed->dma, 2426 sed->offs + offsetof(ohci_ed_t, ed_headp), 2427 sizeof(sed->ed.ed_headp), 2428 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2429 } else { 2430 DPRINTFN(1, "no hit", 0, 0, 0, 0); 2431 } 2432 2433 /* 2434 * Step 4: Turn on hardware again. 2435 */ 2436 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2437 sizeof(sed->ed.ed_flags), 2438 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2439 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2440 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2441 sizeof(sed->ed.ed_flags), 2442 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2443 2444 /* 2445 * Step 5: Execute callback. 2446 */ 2447 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2448 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2449 usb_transfer_complete(xfer); 2450 if (wake) 2451 cv_broadcast(&xfer->ux_hccv); 2452 2453 done: 2454 KASSERT(mutex_owned(&sc->sc_lock)); 2455 } 2456 2457 /* 2458 * Data structures and routines to emulate the root hub. 2459 */ 2460 Static int 2461 ohci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2462 void *buf, int buflen) 2463 { 2464 ohci_softc_t *sc = OHCI_BUS2SC(bus); 2465 usb_port_status_t ps; 2466 uint16_t len, value, index; 2467 int l, totlen = 0; 2468 int port, i; 2469 uint32_t v; 2470 2471 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2472 2473 if (sc->sc_dying) 2474 return -1; 2475 2476 DPRINTFN(4, "type=0x%02x request=%02x", req->bmRequestType, 2477 req->bRequest, 0, 0); 2478 2479 len = UGETW(req->wLength); 2480 value = UGETW(req->wValue); 2481 index = UGETW(req->wIndex); 2482 2483 #define C(x,y) ((x) | ((y) << 8)) 2484 switch (C(req->bRequest, req->bmRequestType)) { 2485 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2486 DPRINTFN(8, "wValue=0x%04x", value, 0, 0, 0); 2487 if (len == 0) 2488 break; 2489 switch (value) { 2490 case C(0, UDESC_DEVICE): { 2491 usb_device_descriptor_t devd; 2492 2493 totlen = min(buflen, sizeof(devd)); 2494 memcpy(&devd, buf, totlen); 2495 USETW(devd.idVendor, sc->sc_id_vendor); 2496 memcpy(buf, &devd, totlen); 2497 break; 2498 } 2499 case C(1, UDESC_STRING): 2500 #define sd ((usb_string_descriptor_t *)buf) 2501 /* Vendor */ 2502 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2503 break; 2504 case C(2, UDESC_STRING): 2505 /* Product */ 2506 totlen = usb_makestrdesc(sd, len, "OHCI root hub"); 2507 break; 2508 #undef sd 2509 default: 2510 /* default from usbroothub */ 2511 return buflen; 2512 } 2513 break; 2514 2515 /* Hub requests */ 2516 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2517 break; 2518 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2519 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 2520 index, value, 0, 0); 2521 if (index < 1 || index > sc->sc_noport) { 2522 return -1; 2523 } 2524 port = OHCI_RH_PORT_STATUS(index); 2525 switch(value) { 2526 case UHF_PORT_ENABLE: 2527 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2528 break; 2529 case UHF_PORT_SUSPEND: 2530 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2531 break; 2532 case UHF_PORT_POWER: 2533 /* Yes, writing to the LOW_SPEED bit clears power. */ 2534 OWRITE4(sc, port, UPS_LOW_SPEED); 2535 break; 2536 case UHF_C_PORT_CONNECTION: 2537 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2538 break; 2539 case UHF_C_PORT_ENABLE: 2540 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2541 break; 2542 case UHF_C_PORT_SUSPEND: 2543 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2544 break; 2545 case UHF_C_PORT_OVER_CURRENT: 2546 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2547 break; 2548 case UHF_C_PORT_RESET: 2549 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2550 break; 2551 default: 2552 return -1; 2553 } 2554 switch(value) { 2555 case UHF_C_PORT_CONNECTION: 2556 case UHF_C_PORT_ENABLE: 2557 case UHF_C_PORT_SUSPEND: 2558 case UHF_C_PORT_OVER_CURRENT: 2559 case UHF_C_PORT_RESET: 2560 /* Enable RHSC interrupt if condition is cleared. */ 2561 if ((OREAD4(sc, port) >> 16) == 0) 2562 ohci_rhsc_enable(sc); 2563 break; 2564 default: 2565 break; 2566 } 2567 break; 2568 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2569 if (len == 0) 2570 break; 2571 if ((value & 0xff) != 0) { 2572 return -1; 2573 } 2574 usb_hub_descriptor_t hubd; 2575 2576 totlen = min(buflen, sizeof(hubd)); 2577 memcpy(&hubd, buf, totlen); 2578 2579 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2580 hubd.bNbrPorts = sc->sc_noport; 2581 USETW(hubd.wHubCharacteristics, 2582 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2583 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2584 /* XXX overcurrent */ 2585 ); 2586 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2587 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2588 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2589 hubd.DeviceRemovable[i++] = (uint8_t)v; 2590 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2591 totlen = min(totlen, hubd.bDescLength); 2592 memcpy(buf, &hubd, totlen); 2593 break; 2594 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2595 if (len != 4) { 2596 return -1; 2597 } 2598 memset(buf, 0, len); /* ? XXX */ 2599 totlen = len; 2600 break; 2601 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2602 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 2603 if (index < 1 || index > sc->sc_noport) { 2604 return -1; 2605 } 2606 if (len != 4) { 2607 return -1; 2608 } 2609 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2610 DPRINTFN(8, "port status=0x%04x", v, 0, 0, 0); 2611 USETW(ps.wPortStatus, v); 2612 USETW(ps.wPortChange, v >> 16); 2613 totlen = min(len, sizeof(ps)); 2614 memcpy(buf, &ps, totlen); 2615 break; 2616 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2617 return -1; 2618 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2619 break; 2620 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2621 if (index < 1 || index > sc->sc_noport) { 2622 return -1; 2623 } 2624 port = OHCI_RH_PORT_STATUS(index); 2625 switch(value) { 2626 case UHF_PORT_ENABLE: 2627 OWRITE4(sc, port, UPS_PORT_ENABLED); 2628 break; 2629 case UHF_PORT_SUSPEND: 2630 OWRITE4(sc, port, UPS_SUSPEND); 2631 break; 2632 case UHF_PORT_RESET: 2633 DPRINTFN(5, "reset port %d", index, 0, 0, 0); 2634 OWRITE4(sc, port, UPS_RESET); 2635 for (i = 0; i < 5; i++) { 2636 usb_delay_ms(&sc->sc_bus, 2637 USB_PORT_ROOT_RESET_DELAY); 2638 if (sc->sc_dying) { 2639 return -1; 2640 } 2641 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2642 break; 2643 } 2644 DPRINTFN(8, "port %d reset, status = 0x%04x", index, 2645 OREAD4(sc, port), 0, 0); 2646 break; 2647 case UHF_PORT_POWER: 2648 DPRINTFN(2, "set port power %d", index, 0, 0, 0); 2649 OWRITE4(sc, port, UPS_PORT_POWER); 2650 break; 2651 default: 2652 return -1; 2653 } 2654 break; 2655 default: 2656 /* default from usbroothub */ 2657 return buflen; 2658 } 2659 2660 return totlen; 2661 } 2662 2663 Static usbd_status 2664 ohci_root_intr_transfer(struct usbd_xfer *xfer) 2665 { 2666 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2667 usbd_status err; 2668 2669 /* Insert last in queue. */ 2670 mutex_enter(&sc->sc_lock); 2671 err = usb_insert_transfer(xfer); 2672 mutex_exit(&sc->sc_lock); 2673 if (err) 2674 return err; 2675 2676 /* Pipe isn't running, start first */ 2677 return ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2678 } 2679 2680 Static usbd_status 2681 ohci_root_intr_start(struct usbd_xfer *xfer) 2682 { 2683 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2684 2685 if (sc->sc_dying) 2686 return USBD_IOERROR; 2687 2688 mutex_enter(&sc->sc_lock); 2689 KASSERT(sc->sc_intrxfer == NULL); 2690 sc->sc_intrxfer = xfer; 2691 mutex_exit(&sc->sc_lock); 2692 2693 return USBD_IN_PROGRESS; 2694 } 2695 2696 /* Abort a root interrupt request. */ 2697 Static void 2698 ohci_root_intr_abort(struct usbd_xfer *xfer) 2699 { 2700 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2701 2702 KASSERT(mutex_owned(&sc->sc_lock)); 2703 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2704 2705 sc->sc_intrxfer = NULL; 2706 2707 xfer->ux_status = USBD_CANCELLED; 2708 usb_transfer_complete(xfer); 2709 } 2710 2711 /* Close the root pipe. */ 2712 Static void 2713 ohci_root_intr_close(struct usbd_pipe *pipe) 2714 { 2715 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2716 2717 KASSERT(mutex_owned(&sc->sc_lock)); 2718 2719 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2720 2721 sc->sc_intrxfer = NULL; 2722 } 2723 2724 /************************/ 2725 2726 int 2727 ohci_device_ctrl_init(struct usbd_xfer *xfer) 2728 { 2729 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2730 usb_device_request_t *req = &xfer->ux_request; 2731 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2732 ohci_soft_td_t *stat, *tail; 2733 int isread = req->bmRequestType & UT_READ; 2734 int len = xfer->ux_bufsize; 2735 int err = ENOMEM; 2736 2737 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2738 2739 /* The TD for setup will be a 'tail' from elsewhere */ 2740 stat = ohci_alloc_std(sc); 2741 if (stat == NULL) { 2742 goto bad1; 2743 } 2744 tail = ohci_alloc_std(sc); 2745 if (tail == NULL) { 2746 goto bad2; 2747 } 2748 tail->xfer = NULL; 2749 2750 ox->ox_stat = stat; 2751 ox->ox_tdtail = tail; 2752 ox->ox_nstd = 0; 2753 2754 /* Set up data transaction */ 2755 if (len != 0) { 2756 err = ohci_alloc_std_chain(sc, xfer, len, isread); 2757 if (err) { 2758 goto bad3; 2759 } 2760 } 2761 return 0; 2762 2763 bad3: 2764 ohci_free_std(sc, tail); 2765 bad2: 2766 ohci_free_std(sc, stat); 2767 bad1: 2768 return err; 2769 } 2770 2771 void 2772 ohci_device_ctrl_fini(struct usbd_xfer *xfer) 2773 { 2774 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2775 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2776 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2777 2778 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2779 DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0); 2780 2781 mutex_enter(&sc->sc_lock); 2782 if (ox->ox_tdtail != opipe->tail.td) { 2783 ohci_free_std_locked(sc, ox->ox_tdtail); 2784 } 2785 for (size_t i = 0; i < ox->ox_nstd; i++) { 2786 ohci_soft_td_t *std = ox->ox_stds[i]; 2787 if (std == NULL) 2788 break; 2789 ohci_free_std_locked(sc, std); 2790 } 2791 ohci_free_std_locked(sc, ox->ox_stat); 2792 mutex_exit(&sc->sc_lock); 2793 2794 if (ox->ox_nstd) { 2795 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 2796 kmem_free(ox->ox_stds, sz); 2797 } 2798 } 2799 2800 Static usbd_status 2801 ohci_device_ctrl_transfer(struct usbd_xfer *xfer) 2802 { 2803 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2804 usbd_status err; 2805 2806 /* Insert last in queue. */ 2807 mutex_enter(&sc->sc_lock); 2808 err = usb_insert_transfer(xfer); 2809 mutex_exit(&sc->sc_lock); 2810 if (err) 2811 return err; 2812 2813 /* Pipe isn't running, start first */ 2814 return ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2815 } 2816 2817 Static usbd_status 2818 ohci_device_ctrl_start(struct usbd_xfer *xfer) 2819 { 2820 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2821 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2822 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2823 usb_device_request_t *req = &xfer->ux_request; 2824 struct usbd_device *dev __diagused = opipe->pipe.up_dev; 2825 ohci_soft_td_t *setup, *stat, *next, *tail; 2826 ohci_soft_ed_t *sed; 2827 int isread; 2828 int len; 2829 2830 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2831 2832 if (sc->sc_dying) 2833 return USBD_IOERROR; 2834 2835 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2836 2837 isread = req->bmRequestType & UT_READ; 2838 len = UGETW(req->wLength); 2839 2840 DPRINTF("type=0x%02x, request=0x%02x, " 2841 "wValue=0x%04x, wIndex=0x%04x", 2842 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2843 UGETW(req->wIndex)); 2844 DPRINTF("len=%d, addr=%d, endpt=%d", 2845 len, dev->ud_addr, 2846 opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 2847 2848 /* Need to take lock here for pipe->tail.td */ 2849 mutex_enter(&sc->sc_lock); 2850 2851 setup = opipe->tail.td; 2852 stat = ox->ox_stat; 2853 tail = ox->ox_tdtail; 2854 opipe->tail.td = tail; 2855 2856 sed = opipe->sed; 2857 2858 KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->ud_addr, 2859 "address ED %d pipe %d\n", 2860 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->ud_addr); 2861 KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) == 2862 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 2863 "MPL ED %d pipe %d\n", 2864 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), 2865 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 2866 2867 /* next will point to data if len != 0 */ 2868 next = stat; 2869 2870 /* Set up data transaction */ 2871 if (len != 0) { 2872 ohci_soft_td_t *std; 2873 ohci_soft_td_t *end; 2874 2875 next = ox->ox_stds[0]; 2876 ohci_reset_std_chain(sc, xfer, len, isread, next, &end); 2877 2878 end->td.td_nexttd = HTOO32(stat->physaddr); 2879 end->nexttd = stat; 2880 2881 usb_syncmem(&end->dma, 2882 end->offs + offsetof(ohci_td_t, td_nexttd), 2883 sizeof(end->td.td_nexttd), 2884 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2885 2886 usb_syncmem(&xfer->ux_dmabuf, 0, len, 2887 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2888 std = ox->ox_stds[0]; 2889 /* Start toggle at 1 and then use the carried toggle. */ 2890 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 2891 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 2892 usb_syncmem(&std->dma, 2893 std->offs + offsetof(ohci_td_t, td_flags), 2894 sizeof(std->td.td_flags), 2895 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2896 } 2897 2898 DPRINTFN(8, "setup %p data %p stat %p tail %p", setup, 2899 (len != 0 ? ox->ox_stds[0] : NULL), stat, tail); 2900 KASSERT(opipe->tail.td == tail); 2901 2902 memcpy(KERNADDR(&opipe->ctrl.reqdma, 0), req, sizeof(*req)); 2903 usb_syncmem(&opipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2904 2905 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 2906 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 2907 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->ctrl.reqdma, 0)); 2908 setup->td.td_nexttd = HTOO32(next->physaddr); 2909 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof(*req) - 1); 2910 setup->nexttd = next; 2911 setup->len = 0; 2912 setup->xfer = xfer; 2913 setup->flags = 0; 2914 ohci_hash_add_td(sc, setup); 2915 2916 xfer->ux_hcpriv = setup; 2917 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2918 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2919 2920 stat->td.td_flags = HTOO32( 2921 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 2922 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 2923 stat->td.td_cbp = 0; 2924 stat->td.td_nexttd = HTOO32(tail->physaddr); 2925 stat->td.td_be = 0; 2926 stat->nexttd = tail; 2927 stat->flags = OHCI_CALL_DONE; 2928 stat->len = 0; 2929 stat->xfer = xfer; 2930 ohci_hash_add_td(sc, stat); 2931 2932 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2933 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2934 2935 memset(&tail->td, 0, sizeof(tail->td)); 2936 tail->nexttd = NULL; 2937 tail->xfer = NULL; 2938 2939 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 2940 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2941 2942 2943 #ifdef OHCI_DEBUG 2944 USBHIST_LOGN(ohcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2945 if (ohcidebug > 5) { 2946 ohci_dump_ed(sc, sed); 2947 ohci_dump_tds(sc, setup); 2948 } 2949 USBHIST_LOGN(ohcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2950 #endif 2951 2952 /* Insert ED in schedule */ 2953 sed->ed.ed_tailp = HTOO32(tail->physaddr); 2954 usb_syncmem(&sed->dma, 2955 sed->offs + offsetof(ohci_ed_t, ed_tailp), 2956 sizeof(sed->ed.ed_tailp), 2957 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2958 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2959 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2960 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2961 ohci_timeout, xfer); 2962 } 2963 2964 #ifdef OHCI_DEBUG 2965 DPRINTFN(20, "--- dump start ---", 0, 0, 0, 0); 2966 if (ohcidebug > 20) { 2967 delay(10000); 2968 DPRINTFN(20, "status=%x", OREAD4(sc, OHCI_COMMAND_STATUS), 2969 0, 0, 0); 2970 ohci_dumpregs(sc); 2971 DPRINTFN(20, "ctrl head:", 0, 0, 0, 0); 2972 ohci_dump_ed(sc, sc->sc_ctrl_head); 2973 DPRINTF("sed:", 0, 0, 0, 0); 2974 ohci_dump_ed(sc, sed); 2975 ohci_dump_tds(sc, setup); 2976 } 2977 DPRINTFN(20, "--- dump start ---", 0, 0, 0, 0); 2978 #endif 2979 2980 mutex_exit(&sc->sc_lock); 2981 2982 if (sc->sc_bus.ub_usepolling) 2983 ohci_waitintr(sc, xfer); 2984 2985 return USBD_IN_PROGRESS; 2986 } 2987 2988 /* Abort a device control request. */ 2989 Static void 2990 ohci_device_ctrl_abort(struct usbd_xfer *xfer) 2991 { 2992 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 2993 2994 KASSERT(mutex_owned(&sc->sc_lock)); 2995 2996 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2997 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2998 ohci_abort_xfer(xfer, USBD_CANCELLED); 2999 } 3000 3001 /* Close a device control pipe. */ 3002 Static void 3003 ohci_device_ctrl_close(struct usbd_pipe *pipe) 3004 { 3005 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3006 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3007 3008 KASSERT(mutex_owned(&sc->sc_lock)); 3009 3010 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3011 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3012 ohci_close_pipe(pipe, sc->sc_ctrl_head); 3013 ohci_free_std_locked(sc, opipe->tail.td); 3014 } 3015 3016 /************************/ 3017 3018 Static void 3019 ohci_device_clear_toggle(struct usbd_pipe *pipe) 3020 { 3021 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3022 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3023 3024 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 3025 } 3026 3027 Static void 3028 ohci_noop(struct usbd_pipe *pipe) 3029 { 3030 } 3031 3032 Static int 3033 ohci_device_bulk_init(struct usbd_xfer *xfer) 3034 { 3035 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3036 int len = xfer->ux_bufsize; 3037 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;; 3038 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3039 int err; 3040 3041 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3042 3043 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3044 3045 DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread, 3046 xfer->ux_flags); 3047 DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0); 3048 3049 /* Allocate a chain of new TDs (including a new tail). */ 3050 err = ohci_alloc_std_chain(sc, xfer, len, isread); 3051 if (err) 3052 return err; 3053 3054 return 0; 3055 } 3056 3057 Static void 3058 ohci_device_bulk_fini(struct usbd_xfer *xfer) 3059 { 3060 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3061 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3062 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3063 3064 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3065 DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0); 3066 3067 mutex_enter(&sc->sc_lock); 3068 for (size_t i = 0; i < ox->ox_nstd; i++) { 3069 ohci_soft_td_t *std = ox->ox_stds[i]; 3070 if (std == NULL) 3071 break; 3072 if (std != opipe->tail.td) 3073 ohci_free_std_locked(sc, std); 3074 } 3075 mutex_exit(&sc->sc_lock); 3076 3077 if (ox->ox_nstd) { 3078 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 3079 kmem_free(ox->ox_stds, sz); 3080 } 3081 } 3082 3083 Static usbd_status 3084 ohci_device_bulk_transfer(struct usbd_xfer *xfer) 3085 { 3086 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3087 usbd_status err; 3088 3089 /* Insert last in queue. */ 3090 mutex_enter(&sc->sc_lock); 3091 err = usb_insert_transfer(xfer); 3092 mutex_exit(&sc->sc_lock); 3093 if (err) 3094 return err; 3095 3096 /* Pipe isn't running, start first */ 3097 return ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3098 } 3099 3100 Static usbd_status 3101 ohci_device_bulk_start(struct usbd_xfer *xfer) 3102 { 3103 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3104 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3105 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3106 ohci_soft_td_t *last; 3107 ohci_soft_td_t *data, *tail, *tdp; 3108 ohci_soft_ed_t *sed; 3109 int len, isread, endpt; 3110 3111 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3112 3113 if (sc->sc_dying) 3114 return USBD_IOERROR; 3115 3116 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3117 3118 len = xfer->ux_length; 3119 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3120 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3121 sed = opipe->sed; 3122 3123 DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread, 3124 xfer->ux_flags); 3125 DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0); 3126 3127 mutex_enter(&sc->sc_lock); 3128 3129 /* Use "tail" TD and loan our first TD to next transfer */ 3130 data = opipe->tail.td; 3131 opipe->tail.td = ox->ox_stds[0]; 3132 ox->ox_stds[0] = data; 3133 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3134 3135 tail = opipe->tail.td; /* point at sentinel */ 3136 memset(&tail->td, 0, sizeof(tail->td)); 3137 tail->nexttd = NULL; 3138 tail->xfer = NULL; 3139 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3140 BUS_DMASYNC_PREWRITE); 3141 xfer->ux_hcpriv = data; 3142 3143 DPRINTFN(8, "xfer %p data %p tail %p", xfer, ox->ox_stds[0], tail, 0); 3144 KASSERT(opipe->tail.td == tail); 3145 3146 /* We want interrupt at the end of the transfer. */ 3147 last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3148 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3149 3150 last->td.td_nexttd = HTOO32(tail->physaddr); 3151 last->nexttd = tail; 3152 last->flags |= OHCI_CALL_DONE; 3153 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3154 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3155 3156 DPRINTFN(4, "ed_flags=0x%08x td_flags=0x%08x " 3157 "td_cbp=0x%08x td_be=0x%08x", 3158 (int)O32TOH(sed->ed.ed_flags), 3159 (int)O32TOH(data->td.td_flags), 3160 (int)O32TOH(data->td.td_cbp), 3161 (int)O32TOH(data->td.td_be)); 3162 3163 #ifdef OHCI_DEBUG 3164 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3165 if (ohcidebug > 5) { 3166 ohci_dump_ed(sc, sed); 3167 ohci_dump_tds(sc, data); 3168 } 3169 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3170 #endif 3171 3172 /* Insert ED in schedule */ 3173 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3174 KASSERT(tdp->xfer == xfer); 3175 } 3176 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3177 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3178 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3179 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3180 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3181 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3182 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3183 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3184 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3185 ohci_timeout, xfer); 3186 } 3187 mutex_exit(&sc->sc_lock); 3188 3189 return USBD_IN_PROGRESS; 3190 } 3191 3192 Static void 3193 ohci_device_bulk_abort(struct usbd_xfer *xfer) 3194 { 3195 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3196 3197 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3198 3199 KASSERT(mutex_owned(&sc->sc_lock)); 3200 3201 DPRINTF("xfer=%p", xfer, 0, 0, 0); 3202 ohci_abort_xfer(xfer, USBD_CANCELLED); 3203 } 3204 3205 /* 3206 * Close a device bulk pipe. 3207 */ 3208 Static void 3209 ohci_device_bulk_close(struct usbd_pipe *pipe) 3210 { 3211 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3212 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3213 3214 KASSERT(mutex_owned(&sc->sc_lock)); 3215 3216 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3217 3218 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3219 ohci_close_pipe(pipe, sc->sc_bulk_head); 3220 ohci_free_std_locked(sc, opipe->tail.td); 3221 } 3222 3223 /************************/ 3224 3225 Static int 3226 ohci_device_intr_init(struct usbd_xfer *xfer) 3227 { 3228 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3229 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3230 int len = xfer->ux_bufsize; 3231 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;; 3232 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3233 int err; 3234 3235 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3236 3237 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3238 KASSERT(len != 0); 3239 3240 DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread, 3241 xfer->ux_flags); 3242 DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0); 3243 3244 ox->ox_nstd = 0; 3245 3246 err = ohci_alloc_std_chain(sc, xfer, len, isread); 3247 if (err) { 3248 return err; 3249 } 3250 3251 return 0; 3252 } 3253 3254 Static void 3255 ohci_device_intr_fini(struct usbd_xfer *xfer) 3256 { 3257 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3258 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3259 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3260 3261 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3262 DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0); 3263 3264 mutex_enter(&sc->sc_lock); 3265 for (size_t i = 0; i < ox->ox_nstd; i++) { 3266 ohci_soft_td_t *std = ox->ox_stds[i]; 3267 if (std != NULL) 3268 break; 3269 if (std != opipe->tail.td) 3270 ohci_free_std_locked(sc, std); 3271 } 3272 mutex_exit(&sc->sc_lock); 3273 3274 if (ox->ox_nstd) { 3275 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 3276 kmem_free(ox->ox_stds, sz); 3277 } 3278 } 3279 3280 Static usbd_status 3281 ohci_device_intr_transfer(struct usbd_xfer *xfer) 3282 { 3283 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3284 usbd_status err; 3285 3286 /* Insert last in queue. */ 3287 mutex_enter(&sc->sc_lock); 3288 err = usb_insert_transfer(xfer); 3289 mutex_exit(&sc->sc_lock); 3290 if (err) 3291 return err; 3292 3293 /* Pipe isn't running, start first */ 3294 return ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3295 } 3296 3297 Static usbd_status 3298 ohci_device_intr_start(struct usbd_xfer *xfer) 3299 { 3300 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3301 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3302 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3303 ohci_soft_ed_t *sed = opipe->sed; 3304 ohci_soft_td_t *data, *last, *tail; 3305 int len, isread, endpt; 3306 3307 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3308 3309 if (sc->sc_dying) 3310 return USBD_IOERROR; 3311 3312 DPRINTFN(3, "xfer=%p len=%d flags=%d priv=%p", xfer, xfer->ux_length, 3313 xfer->ux_flags, xfer->ux_priv); 3314 3315 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3316 3317 len = xfer->ux_length; 3318 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3319 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3320 3321 mutex_enter(&sc->sc_lock); 3322 3323 /* Use "tail" TD and loan our first TD to next transfer */ 3324 data = opipe->tail.td; 3325 opipe->tail.td = ox->ox_stds[0]; 3326 ox->ox_stds[0] = data; 3327 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3328 3329 tail = opipe->tail.td; /* point at sentinel */ 3330 memset(&tail->td, 0, sizeof(tail->td)); 3331 tail->nexttd = NULL; 3332 tail->xfer = NULL; 3333 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3334 BUS_DMASYNC_PREWRITE); 3335 xfer->ux_hcpriv = data; 3336 3337 DPRINTFN(8, "data %p tail %p", ox->ox_stds[0], tail, 0, 0); 3338 KASSERT(opipe->tail.td == tail); 3339 3340 /* We want interrupt at the end of the transfer. */ 3341 last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3342 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3343 3344 last->td.td_nexttd = HTOO32(tail->physaddr); 3345 last->nexttd = tail; 3346 last->flags |= OHCI_CALL_DONE; 3347 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3348 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3349 3350 #ifdef OHCI_DEBUG 3351 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3352 if (ohcidebug > 5) { 3353 ohci_dump_ed(sc, sed); 3354 ohci_dump_tds(sc, data); 3355 } 3356 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3357 #endif 3358 3359 /* Insert ED in schedule */ 3360 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3361 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3362 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3363 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3364 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3365 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3366 3367 mutex_exit(&sc->sc_lock); 3368 3369 return USBD_IN_PROGRESS; 3370 } 3371 3372 /* Abort a device interrupt request. */ 3373 Static void 3374 ohci_device_intr_abort(struct usbd_xfer *xfer) 3375 { 3376 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3377 3378 KASSERT(mutex_owned(&sc->sc_lock)); 3379 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3380 3381 ohci_abort_xfer(xfer, USBD_CANCELLED); 3382 } 3383 3384 /* Close a device interrupt pipe. */ 3385 Static void 3386 ohci_device_intr_close(struct usbd_pipe *pipe) 3387 { 3388 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3389 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3390 int nslots = opipe->intr.nslots; 3391 int pos = opipe->intr.pos; 3392 int j; 3393 ohci_soft_ed_t *p, *sed = opipe->sed; 3394 3395 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3396 3397 KASSERT(mutex_owned(&sc->sc_lock)); 3398 3399 DPRINTFN(1, "pipe=%p nslots=%d pos=%d", pipe, nslots, pos, 0); 3400 usb_syncmem(&sed->dma, sed->offs, 3401 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3402 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3403 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3404 sizeof(sed->ed.ed_flags), 3405 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3406 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3407 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3408 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3409 3410 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3411 continue; 3412 KASSERT(p); 3413 p->next = sed->next; 3414 p->ed.ed_nexted = sed->ed.ed_nexted; 3415 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3416 sizeof(p->ed.ed_nexted), 3417 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3418 3419 for (j = 0; j < nslots; j++) 3420 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3421 3422 ohci_free_std_locked(sc, opipe->tail.td); 3423 ohci_free_sed_locked(sc, opipe->sed); 3424 } 3425 3426 Static usbd_status 3427 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3428 { 3429 int i, j, best; 3430 u_int npoll, slow, shigh, nslots; 3431 u_int bestbw, bw; 3432 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3433 3434 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3435 3436 DPRINTFN(2, "pipe=%p", opipe, 0, 0, 0); 3437 if (ival == 0) { 3438 printf("ohci_setintr: 0 interval\n"); 3439 return USBD_INVAL; 3440 } 3441 3442 npoll = OHCI_NO_INTRS; 3443 while (npoll > ival) 3444 npoll /= 2; 3445 DPRINTFN(2, "ival=%d npoll=%d", ival, npoll, 0, 0); 3446 3447 /* 3448 * We now know which level in the tree the ED must go into. 3449 * Figure out which slot has most bandwidth left over. 3450 * Slots to examine: 3451 * npoll 3452 * 1 0 3453 * 2 1 2 3454 * 4 3 4 5 6 3455 * 8 7 8 9 10 11 12 13 14 3456 * N (N-1) .. (N-1+N-1) 3457 */ 3458 slow = npoll-1; 3459 shigh = slow + npoll; 3460 nslots = OHCI_NO_INTRS / npoll; 3461 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3462 bw = 0; 3463 for (j = 0; j < nslots; j++) 3464 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3465 if (bw < bestbw) { 3466 best = i; 3467 bestbw = bw; 3468 } 3469 } 3470 DPRINTFN(2, "best=%d(%d..%d) bestbw=%d", best, slow, shigh, bestbw); 3471 3472 mutex_enter(&sc->sc_lock); 3473 hsed = sc->sc_eds[best]; 3474 sed->next = hsed->next; 3475 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3476 sizeof(hsed->ed.ed_flags), 3477 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3478 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3479 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3480 sizeof(sed->ed.ed_flags), 3481 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3482 hsed->next = sed; 3483 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3484 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3485 sizeof(hsed->ed.ed_flags), 3486 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3487 mutex_exit(&sc->sc_lock); 3488 3489 for (j = 0; j < nslots; j++) 3490 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3491 opipe->intr.nslots = nslots; 3492 opipe->intr.pos = best; 3493 3494 DPRINTFN(5, "returns %p", opipe, 0, 0, 0); 3495 return USBD_NORMAL_COMPLETION; 3496 } 3497 3498 /***********************/ 3499 3500 Static int 3501 ohci_device_isoc_init(struct usbd_xfer *xfer) 3502 { 3503 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3504 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3505 ohci_soft_itd_t *sitd; 3506 size_t i; 3507 int err; 3508 3509 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3510 3511 DPRINTFN(1, "xfer %p len %d flags %d", xfer, xfer->ux_length, 3512 xfer->ux_flags, 0); 3513 3514 const size_t nfsitd = 3515 (xfer->ux_nframes + OHCI_ITD_NOFFSET - 1) / OHCI_ITD_NOFFSET; 3516 const size_t nbsitd = xfer->ux_bufsize / OHCI_PAGE_SIZE; 3517 const size_t nsitd = MAX(nfsitd, nbsitd) + 1; 3518 3519 ox->ox_sitds = kmem_zalloc(sizeof(ohci_soft_itd_t *) * nsitd, 3520 KM_SLEEP); 3521 ox->ox_nsitd = nsitd; 3522 3523 for (i = 0; i < nsitd; i++) { 3524 /* Allocate next ITD */ 3525 sitd = ohci_alloc_sitd(sc); 3526 if (sitd == NULL) { 3527 err = ENOMEM; 3528 goto fail; 3529 } 3530 ox->ox_sitds[i] = sitd; 3531 sitd->xfer = xfer; 3532 sitd->flags = 0; 3533 } 3534 3535 return 0; 3536 fail: 3537 for (; i > 0;) { 3538 ohci_free_sitd(sc, ox->ox_sitds[--i]); 3539 } 3540 return err; 3541 } 3542 3543 Static void 3544 ohci_device_isoc_fini(struct usbd_xfer *xfer) 3545 { 3546 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3547 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3548 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3549 3550 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3551 3552 mutex_enter(&sc->sc_lock); 3553 for (size_t i = 0; i < ox->ox_nsitd; i++) { 3554 if (ox->ox_sitds[i] != opipe->tail.itd) { 3555 ohci_free_sitd_locked(sc, ox->ox_sitds[i]); 3556 } 3557 } 3558 mutex_exit(&sc->sc_lock); 3559 3560 if (ox->ox_nsitd) { 3561 const size_t sz = sizeof(ohci_soft_itd_t *) * ox->ox_nsitd; 3562 kmem_free(ox->ox_sitds, sz); 3563 } 3564 } 3565 3566 3567 usbd_status 3568 ohci_device_isoc_transfer(struct usbd_xfer *xfer) 3569 { 3570 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3571 usbd_status err; 3572 3573 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3574 3575 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 3576 3577 /* Put it on our queue, */ 3578 mutex_enter(&sc->sc_lock); 3579 err = usb_insert_transfer(xfer); 3580 mutex_exit(&sc->sc_lock); 3581 3582 /* bail out on error, */ 3583 if (err && err != USBD_IN_PROGRESS) 3584 return err; 3585 3586 /* XXX should check inuse here */ 3587 3588 /* insert into schedule, */ 3589 ohci_device_isoc_enter(xfer); 3590 3591 /* and start if the pipe wasn't running */ 3592 if (!err) 3593 ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3594 3595 return err; 3596 } 3597 3598 void 3599 ohci_device_isoc_enter(struct usbd_xfer *xfer) 3600 { 3601 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3602 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3603 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3604 ohci_soft_ed_t *sed = opipe->sed; 3605 ohci_soft_itd_t *sitd, *nsitd; 3606 ohci_physaddr_t buf, offs, noffs, bp0; 3607 int i, ncur, nframes; 3608 3609 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3610 3611 mutex_enter(&sc->sc_lock); 3612 3613 if (sc->sc_dying) { 3614 mutex_exit(&sc->sc_lock); 3615 return; 3616 } 3617 3618 struct isoc *isoc = &opipe->isoc; 3619 3620 DPRINTFN(1, "used=%d next=%d xfer=%p nframes=%d", 3621 isoc->inuse, isoc->next, xfer, xfer->ux_nframes); 3622 3623 if (isoc->next == -1) { 3624 /* Not in use yet, schedule it a few frames ahead. */ 3625 isoc->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3626 DPRINTFN(2,"start next=%d", isoc->next, 0, 0, 0); 3627 } 3628 3629 sitd = opipe->tail.itd; 3630 opipe->tail.itd = ox->ox_sitds[0]; 3631 ox->ox_sitds[0] = sitd; 3632 3633 buf = DMAADDR(&xfer->ux_dmabuf, 0); 3634 bp0 = OHCI_PAGE(buf); 3635 offs = OHCI_PAGE_OFFSET(buf); 3636 nframes = xfer->ux_nframes; 3637 xfer->ux_hcpriv = sitd; 3638 size_t j = 1; 3639 for (i = ncur = 0; i < nframes; i++, ncur++) { 3640 noffs = offs + xfer->ux_frlengths[i]; 3641 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3642 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3643 3644 /* Allocate next ITD */ 3645 nsitd = ox->ox_sitds[j++]; 3646 KASSERT(nsitd != NULL); 3647 KASSERT(j < ox->ox_nsitd); 3648 3649 /* Fill current ITD */ 3650 sitd->itd.itd_flags = HTOO32( 3651 OHCI_ITD_NOCC | 3652 OHCI_ITD_SET_SF(isoc->next) | 3653 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3654 OHCI_ITD_SET_FC(ncur)); 3655 sitd->itd.itd_bp0 = HTOO32(bp0); 3656 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3657 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3658 sitd->nextitd = nsitd; 3659 sitd->xfer = xfer; 3660 sitd->flags = 0; 3661 #ifdef DIAGNOSTIC 3662 sitd->isdone = false; 3663 #endif 3664 ohci_hash_add_itd(sc, sitd); 3665 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3666 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3667 3668 sitd = nsitd; 3669 isoc->next = isoc->next + ncur; 3670 bp0 = OHCI_PAGE(buf + offs); 3671 ncur = 0; 3672 } 3673 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3674 offs = noffs; 3675 } 3676 nsitd = ox->ox_sitds[j++]; 3677 KASSERT(nsitd != NULL); 3678 KASSERT(j <= ox->ox_nsitd); 3679 3680 memset(&nsitd->itd, 0, sizeof(nsitd->itd)); 3681 nsitd->nextitd = NULL; 3682 nsitd->xfer = NULL; 3683 /* Fixup last used ITD */ 3684 sitd->itd.itd_flags = HTOO32( 3685 OHCI_ITD_NOCC | 3686 OHCI_ITD_SET_SF(isoc->next) | 3687 OHCI_ITD_SET_DI(0) | 3688 OHCI_ITD_SET_FC(ncur)); 3689 sitd->itd.itd_bp0 = HTOO32(bp0); 3690 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3691 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3692 sitd->nextitd = nsitd; 3693 sitd->xfer = xfer; 3694 sitd->flags = OHCI_CALL_DONE; 3695 #ifdef DIAGNOSTIC 3696 sitd->isdone = false; 3697 #endif 3698 ohci_hash_add_itd(sc, sitd); 3699 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3700 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3701 3702 isoc->next = isoc->next + ncur; 3703 isoc->inuse += nframes; 3704 3705 xfer->ux_actlen = offs; /* XXX pretend we did it all */ 3706 3707 xfer->ux_status = USBD_IN_PROGRESS; 3708 3709 #ifdef OHCI_DEBUG 3710 if (ohcidebug > 5) { 3711 DPRINTF("frame=%d", O32TOH(sc->sc_hcca->hcca_frame_number), 3712 0, 0, 0); 3713 ohci_dump_itds(sc, xfer->ux_hcpriv); 3714 ohci_dump_ed(sc, sed); 3715 } 3716 #endif 3717 3718 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3719 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3720 sed->ed.ed_tailp = HTOO32(nsitd->physaddr); 3721 opipe->tail.itd = nsitd; 3722 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3723 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3724 sizeof(sed->ed.ed_flags), 3725 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3726 mutex_exit(&sc->sc_lock); 3727 3728 #ifdef OHCI_DEBUG 3729 if (ohcidebug > 5) { 3730 delay(150000); 3731 DPRINTF("after frame=%d", O32TOH(sc->sc_hcca->hcca_frame_number), 3732 0, 0, 0); 3733 ohci_dump_itds(sc, xfer->ux_hcpriv); 3734 ohci_dump_ed(sc, sed); 3735 } 3736 #endif 3737 } 3738 3739 usbd_status 3740 ohci_device_isoc_start(struct usbd_xfer *xfer) 3741 { 3742 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3743 3744 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3745 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 3746 3747 mutex_enter(&sc->sc_lock); 3748 3749 if (sc->sc_dying) { 3750 mutex_exit(&sc->sc_lock); 3751 return USBD_IOERROR; 3752 } 3753 3754 3755 #ifdef DIAGNOSTIC 3756 if (xfer->ux_status != USBD_IN_PROGRESS) 3757 printf("ohci_device_isoc_start: not in progress %p\n", xfer); 3758 #endif 3759 3760 /* XXX anything to do? */ 3761 3762 mutex_exit(&sc->sc_lock); 3763 3764 return USBD_IN_PROGRESS; 3765 } 3766 3767 void 3768 ohci_device_isoc_abort(struct usbd_xfer *xfer) 3769 { 3770 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3771 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3772 ohci_soft_ed_t *sed; 3773 ohci_soft_itd_t *sitd; 3774 3775 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3776 DPRINTFN(1, "xfer=%p", xfer, 0, 0, 0); 3777 3778 KASSERT(mutex_owned(&sc->sc_lock)); 3779 3780 /* Transfer is already done. */ 3781 if (xfer->ux_status != USBD_NOT_STARTED && 3782 xfer->ux_status != USBD_IN_PROGRESS) { 3783 printf("ohci_device_isoc_abort: early return\n"); 3784 goto done; 3785 } 3786 3787 /* Give xfer the requested abort code. */ 3788 xfer->ux_status = USBD_CANCELLED; 3789 3790 sed = opipe->sed; 3791 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3792 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3793 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3794 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3795 sizeof(sed->ed.ed_flags), 3796 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3797 3798 sitd = xfer->ux_hcpriv; 3799 KASSERT(sitd); 3800 3801 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3802 #ifdef DIAGNOSTIC 3803 DPRINTFN(1, "abort sets done sitd=%p", sitd, 0, 0, 0); 3804 sitd->isdone = true; 3805 #endif 3806 } 3807 3808 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3809 3810 /* Run callback. */ 3811 usb_transfer_complete(xfer); 3812 3813 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3814 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3815 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3816 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3817 3818 done: 3819 KASSERT(mutex_owned(&sc->sc_lock)); 3820 } 3821 3822 void 3823 ohci_device_isoc_done(struct usbd_xfer *xfer) 3824 { 3825 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3826 DPRINTFN(1, "xfer=%p", xfer, 0, 0, 0); 3827 } 3828 3829 usbd_status 3830 ohci_setup_isoc(struct usbd_pipe *pipe) 3831 { 3832 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3833 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3834 struct isoc *isoc = &opipe->isoc; 3835 3836 isoc->next = -1; 3837 isoc->inuse = 0; 3838 3839 mutex_enter(&sc->sc_lock); 3840 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3841 mutex_exit(&sc->sc_lock); 3842 3843 return USBD_NORMAL_COMPLETION; 3844 } 3845 3846 void 3847 ohci_device_isoc_close(struct usbd_pipe *pipe) 3848 { 3849 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3850 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3851 3852 KASSERT(mutex_owned(&sc->sc_lock)); 3853 3854 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3855 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3856 ohci_close_pipe(pipe, sc->sc_isoc_head); 3857 #ifdef DIAGNOSTIC 3858 opipe->tail.itd->isdone = true; 3859 #endif 3860 ohci_free_sitd_locked(sc, opipe->tail.itd); 3861 } 3862
Indexes created Fri Oct 03 02:09:57 GMT 2025