ohci.c revision 1.254.2.41
1 /* $NetBSD: ohci.c,v 1.254.2.41 2016/01/09 21:45:20 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * USB Open Host Controller driver. 38 * 39 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 40 * USB spec: http://www.usb.org/developers/docs/ 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.254.2.41 2016/01/09 21:45:20 skrll Exp $"); 45 46 #include "opt_usb.h" 47 48 #include <sys/param.h> 49 50 #include <sys/cpu.h> 51 #include <sys/device.h> 52 #include <sys/kernel.h> 53 #include <sys/kmem.h> 54 #include <sys/proc.h> 55 #include <sys/queue.h> 56 #include <sys/select.h> 57 #include <sys/sysctl.h> 58 #include <sys/systm.h> 59 60 #include <machine/endian.h> 61 62 #include <dev/usb/usb.h> 63 #include <dev/usb/usbdi.h> 64 #include <dev/usb/usbdivar.h> 65 #include <dev/usb/usb_mem.h> 66 #include <dev/usb/usb_quirks.h> 67 68 #include <dev/usb/ohcireg.h> 69 #include <dev/usb/ohcivar.h> 70 #include <dev/usb/usbroothub.h> 71 #include <dev/usb/usbhist.h> 72 73 #ifdef USB_DEBUG 74 #ifndef OHCI_DEBUG 75 #define ohcidebug 0 76 #else 77 static int ohcidebug = 0; 78 79 SYSCTL_SETUP(sysctl_hw_ohci_setup, "sysctl hw.ohci setup") 80 { 81 int err; 82 const struct sysctlnode *rnode; 83 const struct sysctlnode *cnode; 84 85 err = sysctl_createv(clog, 0, NULL, &rnode, 86 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ohci", 87 SYSCTL_DESCR("ohci global controls"), 88 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 89 90 if (err) 91 goto fail; 92 93 /* control debugging printfs */ 94 err = sysctl_createv(clog, 0, &rnode, &cnode, 95 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 96 "debug", SYSCTL_DESCR("Enable debugging output"), 97 NULL, 0, &ohcidebug, sizeof(ohcidebug), CTL_CREATE, CTL_EOL); 98 if (err) 99 goto fail; 100 101 return; 102 fail: 103 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 104 } 105 106 #endif /* OHCI_DEBUG */ 107 #endif /* USB_DEBUG */ 108 109 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ohcidebug,FMT,A,B,C,D) 110 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ohcidebug,N,FMT,A,B,C,D) 111 #define OHCIHIST_FUNC() USBHIST_FUNC() 112 #define OHCIHIST_CALLED(name) USBHIST_CALLED(ohcidebug) 113 114 #if BYTE_ORDER == BIG_ENDIAN 115 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 116 #else 117 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 118 #endif 119 120 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 121 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 122 #define HTOO16(val) O16TOH(val) 123 #define HTOO32(val) O32TOH(val) 124 125 struct ohci_pipe; 126 127 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 128 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 129 130 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 131 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 132 Static void ohci_free_std_locked(ohci_softc_t *, ohci_soft_td_t *); 133 134 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 135 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 136 Static void ohci_free_sitd_locked(ohci_softc_t *, 137 ohci_soft_itd_t *); 138 139 Static usbd_status ohci_alloc_std_chain(ohci_softc_t *, struct usbd_xfer *, 140 int, int); 141 Static void ohci_free_stds(ohci_softc_t *, struct ohci_xfer *); 142 143 Static void ohci_reset_std_chain(ohci_softc_t *, struct usbd_xfer *, 144 int, int, ohci_soft_td_t *, ohci_soft_td_t **); 145 146 Static usbd_status ohci_open(struct usbd_pipe *); 147 Static void ohci_poll(struct usbd_bus *); 148 Static void ohci_softintr(void *); 149 Static void ohci_waitintr(ohci_softc_t *, struct usbd_xfer *); 150 Static void ohci_rhsc(ohci_softc_t *, struct usbd_xfer *); 151 Static void ohci_rhsc_softint(void *); 152 153 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 154 ohci_soft_ed_t *); 155 156 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 157 ohci_soft_ed_t *); 158 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 159 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 160 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 161 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 162 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 163 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 164 165 Static usbd_status ohci_setup_isoc(struct usbd_pipe *); 166 Static void ohci_device_isoc_enter(struct usbd_xfer *); 167 168 Static struct usbd_xfer * 169 ohci_allocx(struct usbd_bus *, unsigned int); 170 Static void ohci_freex(struct usbd_bus *, struct usbd_xfer *); 171 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 172 Static int ohci_roothub_ctrl(struct usbd_bus *, 173 usb_device_request_t *, void *, int); 174 175 Static usbd_status ohci_root_intr_transfer(struct usbd_xfer *); 176 Static usbd_status ohci_root_intr_start(struct usbd_xfer *); 177 Static void ohci_root_intr_abort(struct usbd_xfer *); 178 Static void ohci_root_intr_close(struct usbd_pipe *); 179 Static void ohci_root_intr_done(struct usbd_xfer *); 180 181 Static int ohci_device_ctrl_init(struct usbd_xfer *); 182 Static void ohci_device_ctrl_fini(struct usbd_xfer *); 183 Static usbd_status ohci_device_ctrl_transfer(struct usbd_xfer *); 184 Static usbd_status ohci_device_ctrl_start(struct usbd_xfer *); 185 Static void ohci_device_ctrl_abort(struct usbd_xfer *); 186 Static void ohci_device_ctrl_close(struct usbd_pipe *); 187 Static void ohci_device_ctrl_done(struct usbd_xfer *); 188 189 Static int ohci_device_bulk_init(struct usbd_xfer *); 190 Static void ohci_device_bulk_fini(struct usbd_xfer *); 191 Static usbd_status ohci_device_bulk_transfer(struct usbd_xfer *); 192 Static usbd_status ohci_device_bulk_start(struct usbd_xfer *); 193 Static void ohci_device_bulk_abort(struct usbd_xfer *); 194 Static void ohci_device_bulk_close(struct usbd_pipe *); 195 Static void ohci_device_bulk_done(struct usbd_xfer *); 196 197 Static int ohci_device_intr_init(struct usbd_xfer *); 198 Static void ohci_device_intr_fini(struct usbd_xfer *); 199 Static usbd_status ohci_device_intr_transfer(struct usbd_xfer *); 200 Static usbd_status ohci_device_intr_start(struct usbd_xfer *); 201 Static void ohci_device_intr_abort(struct usbd_xfer *); 202 Static void ohci_device_intr_close(struct usbd_pipe *); 203 Static void ohci_device_intr_done(struct usbd_xfer *); 204 205 Static int ohci_device_isoc_init(struct usbd_xfer *); 206 Static void ohci_device_isoc_fini(struct usbd_xfer *); 207 Static usbd_status ohci_device_isoc_transfer(struct usbd_xfer *); 208 Static usbd_status ohci_device_isoc_start(struct usbd_xfer *); 209 Static void ohci_device_isoc_abort(struct usbd_xfer *); 210 Static void ohci_device_isoc_close(struct usbd_pipe *); 211 Static void ohci_device_isoc_done(struct usbd_xfer *); 212 213 Static usbd_status ohci_device_setintr(ohci_softc_t *, 214 struct ohci_pipe *, int); 215 216 Static void ohci_timeout(void *); 217 Static void ohci_timeout_task(void *); 218 Static void ohci_rhsc_enable(void *); 219 220 Static void ohci_close_pipe(struct usbd_pipe *, ohci_soft_ed_t *); 221 Static void ohci_abort_xfer(struct usbd_xfer *, usbd_status); 222 223 Static void ohci_device_clear_toggle(struct usbd_pipe *); 224 Static void ohci_noop(struct usbd_pipe *); 225 226 #ifdef OHCI_DEBUG 227 Static void ohci_dumpregs(ohci_softc_t *); 228 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 229 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 230 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 231 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 232 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 233 #endif 234 235 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 236 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 237 #define OWRITE1(sc, r, x) \ 238 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 239 #define OWRITE2(sc, r, x) \ 240 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 241 #define OWRITE4(sc, r, x) \ 242 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 243 244 static __inline uint32_t 245 OREAD4(ohci_softc_t *sc, bus_size_t r) 246 { 247 248 OBARR(sc); 249 return bus_space_read_4(sc->iot, sc->ioh, r); 250 } 251 252 /* Reverse the bits in a value 0 .. 31 */ 253 Static uint8_t revbits[OHCI_NO_INTRS] = 254 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 255 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 256 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 257 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 258 259 struct ohci_pipe { 260 struct usbd_pipe pipe; 261 ohci_soft_ed_t *sed; 262 union { 263 ohci_soft_td_t *td; 264 ohci_soft_itd_t *itd; 265 } tail; 266 /* Info needed for different pipe kinds. */ 267 union { 268 /* Control pipe */ 269 struct { 270 usb_dma_t reqdma; 271 } ctrl; 272 /* Interrupt pipe */ 273 struct { 274 int nslots; 275 int pos; 276 } intr; 277 /* Isochronous pipe */ 278 struct isoc { 279 int next, inuse; 280 } isoc; 281 }; 282 }; 283 284 Static const struct usbd_bus_methods ohci_bus_methods = { 285 .ubm_open = ohci_open, 286 .ubm_softint = ohci_softintr, 287 .ubm_dopoll = ohci_poll, 288 .ubm_allocx = ohci_allocx, 289 .ubm_freex = ohci_freex, 290 .ubm_getlock = ohci_get_lock, 291 .ubm_rhctrl = ohci_roothub_ctrl, 292 }; 293 294 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 295 .upm_transfer = ohci_root_intr_transfer, 296 .upm_start = ohci_root_intr_start, 297 .upm_abort = ohci_root_intr_abort, 298 .upm_close = ohci_root_intr_close, 299 .upm_cleartoggle = ohci_noop, 300 .upm_done = ohci_root_intr_done, 301 }; 302 303 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 304 .upm_init = ohci_device_ctrl_init, 305 .upm_fini = ohci_device_ctrl_fini, 306 .upm_transfer = ohci_device_ctrl_transfer, 307 .upm_start = ohci_device_ctrl_start, 308 .upm_abort = ohci_device_ctrl_abort, 309 .upm_close = ohci_device_ctrl_close, 310 .upm_cleartoggle = ohci_noop, 311 .upm_done = ohci_device_ctrl_done, 312 }; 313 314 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 315 .upm_init = ohci_device_intr_init, 316 .upm_fini = ohci_device_intr_fini, 317 .upm_transfer = ohci_device_intr_transfer, 318 .upm_start = ohci_device_intr_start, 319 .upm_abort = ohci_device_intr_abort, 320 .upm_close = ohci_device_intr_close, 321 .upm_cleartoggle = ohci_device_clear_toggle, 322 .upm_done = ohci_device_intr_done, 323 }; 324 325 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 326 .upm_init = ohci_device_bulk_init, 327 .upm_fini = ohci_device_bulk_fini, 328 .upm_transfer = ohci_device_bulk_transfer, 329 .upm_start = ohci_device_bulk_start, 330 .upm_abort = ohci_device_bulk_abort, 331 .upm_close = ohci_device_bulk_close, 332 .upm_cleartoggle = ohci_device_clear_toggle, 333 .upm_done = ohci_device_bulk_done, 334 }; 335 336 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 337 .upm_init = ohci_device_isoc_init, 338 .upm_fini = ohci_device_isoc_fini, 339 .upm_transfer = ohci_device_isoc_transfer, 340 .upm_start = ohci_device_isoc_start, 341 .upm_abort = ohci_device_isoc_abort, 342 .upm_close = ohci_device_isoc_close, 343 .upm_cleartoggle = ohci_noop, 344 .upm_done = ohci_device_isoc_done, 345 }; 346 347 int 348 ohci_activate(device_t self, enum devact act) 349 { 350 struct ohci_softc *sc = device_private(self); 351 352 switch (act) { 353 case DVACT_DEACTIVATE: 354 sc->sc_dying = 1; 355 return 0; 356 default: 357 return EOPNOTSUPP; 358 } 359 } 360 361 void 362 ohci_childdet(device_t self, device_t child) 363 { 364 struct ohci_softc *sc = device_private(self); 365 366 KASSERT(sc->sc_child == child); 367 sc->sc_child = NULL; 368 } 369 370 int 371 ohci_detach(struct ohci_softc *sc, int flags) 372 { 373 int rv = 0; 374 375 if (sc->sc_child != NULL) 376 rv = config_detach(sc->sc_child, flags); 377 378 if (rv != 0) 379 return rv; 380 381 callout_halt(&sc->sc_tmo_rhsc, &sc->sc_lock); 382 383 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 384 callout_destroy(&sc->sc_tmo_rhsc); 385 386 softint_disestablish(sc->sc_rhsc_si); 387 388 cv_destroy(&sc->sc_softwake_cv); 389 390 mutex_destroy(&sc->sc_lock); 391 mutex_destroy(&sc->sc_intr_lock); 392 393 if (sc->sc_hcca != NULL) 394 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 395 pool_cache_destroy(sc->sc_xferpool); 396 397 return rv; 398 } 399 400 ohci_soft_ed_t * 401 ohci_alloc_sed(ohci_softc_t *sc) 402 { 403 ohci_soft_ed_t *sed; 404 usbd_status err; 405 int i, offs; 406 usb_dma_t dma; 407 408 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 409 410 mutex_enter(&sc->sc_lock); 411 if (sc->sc_freeeds == NULL) { 412 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 413 mutex_exit(&sc->sc_lock); 414 415 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 416 OHCI_ED_ALIGN, &dma); 417 if (err) 418 return 0; 419 420 mutex_enter(&sc->sc_lock); 421 for (i = 0; i < OHCI_SED_CHUNK; i++) { 422 offs = i * OHCI_SED_SIZE; 423 sed = KERNADDR(&dma, offs); 424 sed->physaddr = DMAADDR(&dma, offs); 425 sed->dma = dma; 426 sed->offs = offs; 427 sed->next = sc->sc_freeeds; 428 sc->sc_freeeds = sed; 429 } 430 } 431 sed = sc->sc_freeeds; 432 sc->sc_freeeds = sed->next; 433 mutex_exit(&sc->sc_lock); 434 435 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 436 sed->next = 0; 437 return sed; 438 } 439 440 static inline void 441 ohci_free_sed_locked(ohci_softc_t *sc, ohci_soft_ed_t *sed) 442 { 443 444 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 445 446 sed->next = sc->sc_freeeds; 447 sc->sc_freeeds = sed; 448 } 449 450 void 451 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 452 { 453 454 mutex_enter(&sc->sc_lock); 455 ohci_free_sed_locked(sc, sed); 456 mutex_exit(&sc->sc_lock); 457 } 458 459 ohci_soft_td_t * 460 ohci_alloc_std(ohci_softc_t *sc) 461 { 462 ohci_soft_td_t *std; 463 usbd_status err; 464 int i, offs; 465 usb_dma_t dma; 466 467 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 468 469 mutex_enter(&sc->sc_lock); 470 if (sc->sc_freetds == NULL) { 471 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 472 mutex_exit(&sc->sc_lock); 473 474 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 475 OHCI_TD_ALIGN, &dma); 476 if (err) 477 return NULL; 478 479 mutex_enter(&sc->sc_lock); 480 for(i = 0; i < OHCI_STD_CHUNK; i++) { 481 offs = i * OHCI_STD_SIZE; 482 std = KERNADDR(&dma, offs); 483 std->physaddr = DMAADDR(&dma, offs); 484 std->dma = dma; 485 std->offs = offs; 486 std->nexttd = sc->sc_freetds; 487 sc->sc_freetds = std; 488 } 489 } 490 491 std = sc->sc_freetds; 492 sc->sc_freetds = std->nexttd; 493 mutex_exit(&sc->sc_lock); 494 495 memset(&std->td, 0, sizeof(ohci_td_t)); 496 std->nexttd = NULL; 497 std->xfer = NULL; 498 499 return std; 500 } 501 502 void 503 ohci_free_std_locked(ohci_softc_t *sc, ohci_soft_td_t *std) 504 { 505 506 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 507 508 std->nexttd = sc->sc_freetds; 509 sc->sc_freetds = std; 510 } 511 512 void 513 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 514 { 515 516 mutex_enter(&sc->sc_lock); 517 ohci_free_std_locked(sc, std); 518 mutex_exit(&sc->sc_lock); 519 } 520 521 Static usbd_status 522 ohci_alloc_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, int alen, int rd) 523 { 524 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 525 struct usbd_pipe *pipe = xfer->ux_pipe; 526 ohci_soft_td_t *next, *cur; 527 ohci_physaddr_t dataphys, dataphysend; 528 uint32_t tdflags; 529 int len = alen; 530 int curlen; 531 usb_dma_t *dma = &xfer->ux_dmabuf; 532 uint16_t flags = xfer->ux_flags; 533 534 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 535 536 DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d", 537 pipe->up_dev->ud_addr, 538 UE_GET_ADDR(pipe->up_endpoint->ue_edesc->bEndpointAddress), 539 alen, pipe->up_dev->ud_speed); 540 541 ASSERT_SLEEPABLE(); 542 543 size_t nstd = (flags & USBD_FORCE_SHORT_XFER) ? 1 : 0; 544 nstd += ((len + OHCI_PAGE_SIZE - 1) / OHCI_PAGE_SIZE); 545 ox->ox_stds = kmem_zalloc(sizeof(ohci_soft_td_t *) * nstd, 546 KM_SLEEP); 547 ox->ox_nstd = nstd; 548 int mps = UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize); 549 550 DPRINTFN(8, "xfer %p nstd %d mps %d", xfer, nstd, mps, 0); 551 552 len = alen; 553 cur = ohci_alloc_std(sc); 554 if (cur == NULL) 555 goto nomem; 556 557 dataphys = DMAADDR(dma, 0); 558 dataphysend = OHCI_PAGE(dataphys + len - 1); 559 tdflags = HTOO32( 560 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 561 (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) | 562 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 563 564 for (size_t j = 0;;) { 565 ox->ox_stds[j++] = cur; 566 next = ohci_alloc_std(sc); 567 if (next == NULL) 568 goto nomem; 569 570 /* The OHCI hardware can handle at most one page crossing. */ 571 if (OHCI_PAGE(dataphys) == dataphysend || 572 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 573 /* we can handle it in this TD */ 574 curlen = len; 575 } else { 576 /* must use multiple TDs, fill as much as possible. */ 577 curlen = 2 * OHCI_PAGE_SIZE - 578 (dataphys & (OHCI_PAGE_SIZE-1)); 579 /* the length must be a multiple of the max size */ 580 curlen -= curlen % mps; 581 KASSERT(curlen != 0); 582 } 583 DPRINTFN(4, "dataphys=0x%08x dataphysend=0x%08x " 584 "len=%d curlen=%d", dataphys, dataphysend, len, curlen); 585 len -= curlen; 586 587 cur->td.td_flags = tdflags; 588 cur->td.td_cbp = HTOO32(dataphys); 589 cur->td.td_nexttd = HTOO32(next->physaddr); 590 cur->td.td_be = HTOO32(dataphys + curlen - 1); 591 cur->nexttd = next; 592 cur->len = curlen; 593 cur->flags = OHCI_ADD_LEN; 594 cur->xfer = xfer; 595 596 DPRINTFN(10, "cbp=0x%08x be=0x%08x", dataphys, 597 dataphys + curlen - 1, 0, 0); 598 if (len == 0) 599 break; 600 DPRINTFN(10, "extend chain", 0, 0, 0, 0); 601 dataphys += curlen; 602 cur = next; 603 } 604 if (!rd && (flags & USBD_FORCE_SHORT_XFER) && 605 alen % mps == 0) { 606 /* Force a 0 length transfer at the end. */ 607 608 cur = next; 609 next = ohci_alloc_std(sc); 610 if (next == NULL) 611 goto nomem; 612 613 cur->td.td_flags = tdflags; 614 cur->td.td_cbp = 0; /* indicate 0 length packet */ 615 cur->td.td_nexttd = HTOO32(next->physaddr); 616 cur->td.td_be = ~0; 617 cur->nexttd = next; 618 cur->len = 0; 619 cur->flags = 0; 620 cur->xfer = xfer; 621 622 DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0); 623 } 624 625 return USBD_NORMAL_COMPLETION; 626 627 nomem: 628 ohci_free_stds(sc, ox); 629 630 return USBD_NOMEM; 631 } 632 633 Static void 634 ohci_free_stds(ohci_softc_t *sc, struct ohci_xfer *ox) 635 { 636 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 637 DPRINTF("ox=%p", ox, 0, 0, 0); 638 639 mutex_enter(&sc->sc_lock); 640 for (size_t i = 0; i < ox->ox_nstd; i++) { 641 ohci_soft_td_t *std = ox->ox_stds[i]; 642 if (std == NULL) 643 break; 644 ohci_free_std_locked(sc, std); 645 } 646 mutex_exit(&sc->sc_lock); 647 } 648 649 void 650 ohci_reset_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, 651 int alen, int rd, ohci_soft_td_t *sp, ohci_soft_td_t **ep) 652 { 653 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 654 ohci_soft_td_t *next, *cur; 655 ohci_physaddr_t dataphys, dataphysend; 656 uint32_t tdflags; 657 int len, curlen; 658 usb_dma_t *dma = &xfer->ux_dmabuf; 659 uint16_t flags = xfer->ux_flags; 660 661 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 662 DPRINTF("start len=%d", alen, 0, 0, 0); 663 664 KASSERT(mutex_owned(&sc->sc_lock)); 665 666 DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d", 667 xfer->ux_pipe->up_dev->ud_addr, 668 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 669 alen, xfer->ux_pipe->up_dev->ud_speed); 670 671 KASSERT(sp); 672 673 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 674 675 len = alen; 676 cur = sp; 677 678 dataphys = DMAADDR(dma, 0); 679 dataphysend = OHCI_PAGE(dataphys + len - 1); 680 usb_syncmem(dma, 0, len, 681 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 682 tdflags = HTOO32( 683 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 684 (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) | 685 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 686 687 for (size_t j = 1;;) { 688 if (j == ox->ox_nstd) 689 next = NULL; 690 else 691 next = ox->ox_stds[j++]; 692 KASSERT(next != cur); 693 694 /* The OHCI hardware can handle at most one page crossing. */ 695 if (OHCI_PAGE(dataphys) == dataphysend || 696 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 697 /* we can handle it in this TD */ 698 curlen = len; 699 } else { 700 /* must use multiple TDs, fill as much as possible. */ 701 curlen = 2 * OHCI_PAGE_SIZE - 702 (dataphys & (OHCI_PAGE_SIZE - 1)); 703 /* the length must be a multiple of the max size */ 704 curlen -= curlen % mps; 705 KASSERT(curlen != 0); 706 } 707 DPRINTFN(4, "dataphys=0x%08x dataphysend=0x%08x " 708 "len=%d curlen=%d", dataphys, dataphysend, len, curlen); 709 len -= curlen; 710 711 cur->td.td_flags = tdflags; 712 cur->td.td_cbp = HTOO32(dataphys); 713 cur->td.td_be = HTOO32(dataphys + curlen - 1); 714 cur->td.td_nexttd = (next != NULL) ? HTOO32(next->physaddr) : 0; 715 cur->nexttd = next; 716 cur->len = curlen; 717 cur->flags = OHCI_ADD_LEN; 718 cur->xfer = xfer; 719 ohci_hash_add_td(sc, cur); 720 721 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 722 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 723 DPRINTFN(10, "cbp=0x%08x be=0x%08x", dataphys, 724 dataphys + curlen - 1, 0, 0); 725 if (len == 0) 726 break; 727 KASSERT(next != NULL); 728 DPRINTFN(10, "extend chain", 0, 0, 0, 0); 729 dataphys += curlen; 730 cur = next; 731 } 732 if (!rd && 733 (flags & USBD_FORCE_SHORT_XFER) && 734 alen % mps == 0) { 735 /* Force a 0 length transfer at the end. */ 736 737 KASSERT(next != NULL); 738 cur = next; 739 740 cur->td.td_flags = tdflags; 741 cur->td.td_cbp = 0; /* indicate 0 length packet */ 742 cur->td.td_nexttd = HTOO32(next->physaddr); 743 cur->td.td_be = ~0; 744 cur->nexttd = NULL; 745 cur->len = 0; 746 cur->flags = 0; 747 cur->xfer = xfer; 748 ohci_hash_add_td(sc, cur); 749 750 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 751 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 752 DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0); 753 } 754 *ep = cur; 755 } 756 757 ohci_soft_itd_t * 758 ohci_alloc_sitd(ohci_softc_t *sc) 759 { 760 ohci_soft_itd_t *sitd; 761 usbd_status err; 762 int i, offs; 763 usb_dma_t dma; 764 765 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 766 767 mutex_enter(&sc->sc_lock); 768 if (sc->sc_freeitds == NULL) { 769 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 770 mutex_exit(&sc->sc_lock); 771 772 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 773 OHCI_ITD_ALIGN, &dma); 774 if (err) 775 return NULL; 776 mutex_enter(&sc->sc_lock); 777 for(i = 0; i < OHCI_SITD_CHUNK; i++) { 778 offs = i * OHCI_SITD_SIZE; 779 sitd = KERNADDR(&dma, offs); 780 sitd->physaddr = DMAADDR(&dma, offs); 781 sitd->dma = dma; 782 sitd->offs = offs; 783 sitd->nextitd = sc->sc_freeitds; 784 sc->sc_freeitds = sitd; 785 } 786 } 787 788 sitd = sc->sc_freeitds; 789 sc->sc_freeitds = sitd->nextitd; 790 mutex_exit(&sc->sc_lock); 791 792 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 793 sitd->nextitd = NULL; 794 sitd->xfer = NULL; 795 796 #ifdef DIAGNOSTIC 797 sitd->isdone = false; 798 #endif 799 800 return sitd; 801 } 802 803 Static void 804 ohci_free_sitd_locked(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 805 { 806 807 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 808 DPRINTFN(10, "sitd=%p", sitd, 0, 0, 0); 809 810 KASSERT(sitd->isdone); 811 #ifdef DIAGNOSTIC 812 /* Warn double free */ 813 sitd->isdone = false; 814 #endif 815 816 sitd->nextitd = sc->sc_freeitds; 817 sc->sc_freeitds = sitd; 818 } 819 820 void 821 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 822 { 823 824 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 825 826 mutex_enter(&sc->sc_lock); 827 ohci_free_sitd_locked(sc, sitd); 828 mutex_exit(&sc->sc_lock); 829 } 830 831 int 832 ohci_init(ohci_softc_t *sc) 833 { 834 ohci_soft_ed_t *sed, *psed; 835 usbd_status err; 836 int i; 837 uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */; 838 839 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 840 841 aprint_normal_dev(sc->sc_dev, ""); 842 843 sc->sc_hcca = NULL; 844 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 845 846 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 847 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 848 cv_init(&sc->sc_softwake_cv, "ohciab"); 849 850 sc->sc_rhsc_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 851 ohci_rhsc_softint, sc); 852 853 for (i = 0; i < OHCI_HASH_SIZE; i++) 854 LIST_INIT(&sc->sc_hash_tds[i]); 855 for (i = 0; i < OHCI_HASH_SIZE; i++) 856 LIST_INIT(&sc->sc_hash_itds[i]); 857 858 sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0, 859 "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL); 860 861 rev = OREAD4(sc, OHCI_REVISION); 862 aprint_normal("OHCI version %d.%d%s\n", 863 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 864 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 865 866 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 867 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 868 sc->sc_bus.ub_revision = USBREV_UNKNOWN; 869 return -1; 870 } 871 sc->sc_bus.ub_revision = USBREV_1_0; 872 sc->sc_bus.ub_usedma = true; 873 874 /* XXX determine alignment by R/W */ 875 /* Allocate the HCCA area. */ 876 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 877 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 878 if (err) { 879 sc->sc_hcca = NULL; 880 return err; 881 } 882 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 883 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 884 885 sc->sc_eintrs = OHCI_NORMAL_INTRS; 886 887 /* Allocate dummy ED that starts the control list. */ 888 sc->sc_ctrl_head = ohci_alloc_sed(sc); 889 if (sc->sc_ctrl_head == NULL) { 890 err = ENOMEM; 891 goto bad1; 892 } 893 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 894 895 /* Allocate dummy ED that starts the bulk list. */ 896 sc->sc_bulk_head = ohci_alloc_sed(sc); 897 if (sc->sc_bulk_head == NULL) { 898 err = ENOMEM; 899 goto bad2; 900 } 901 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 902 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 903 sizeof(sc->sc_bulk_head->ed), 904 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 905 906 /* Allocate dummy ED that starts the isochronous list. */ 907 sc->sc_isoc_head = ohci_alloc_sed(sc); 908 if (sc->sc_isoc_head == NULL) { 909 err = ENOMEM; 910 goto bad3; 911 } 912 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 913 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 914 sizeof(sc->sc_isoc_head->ed), 915 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 916 917 /* Allocate all the dummy EDs that make up the interrupt tree. */ 918 for (i = 0; i < OHCI_NO_EDS; i++) { 919 sed = ohci_alloc_sed(sc); 920 if (sed == NULL) { 921 while (--i >= 0) 922 ohci_free_sed(sc, sc->sc_eds[i]); 923 err = ENOMEM; 924 goto bad4; 925 } 926 /* All ED fields are set to 0. */ 927 sc->sc_eds[i] = sed; 928 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 929 if (i != 0) 930 psed = sc->sc_eds[(i-1) / 2]; 931 else 932 psed= sc->sc_isoc_head; 933 sed->next = psed; 934 sed->ed.ed_nexted = HTOO32(psed->physaddr); 935 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 936 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 937 } 938 /* 939 * Fill HCCA interrupt table. The bit reversal is to get 940 * the tree set up properly to spread the interrupts. 941 */ 942 for (i = 0; i < OHCI_NO_INTRS; i++) 943 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 944 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 945 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 946 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 947 948 #ifdef OHCI_DEBUG 949 DPRINTFN(15, "--- dump start ---", 0, 0, 0 ,0); 950 if (ohcidebug >= 15) { 951 for (i = 0; i < OHCI_NO_EDS; i++) { 952 DPRINTFN(15, "ed#%d ", i, 0, 0, 0); 953 ohci_dump_ed(sc, sc->sc_eds[i]); 954 } 955 DPRINTFN(15, "iso", 0, 0, 0 ,0); 956 ohci_dump_ed(sc, sc->sc_isoc_head); 957 } 958 DPRINTFN(15, "--- dump end ---", 0, 0, 0 ,0); 959 #endif 960 961 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 962 ctl = OREAD4(sc, OHCI_CONTROL); 963 rwc = ctl & OHCI_RWC; 964 fm = OREAD4(sc, OHCI_FM_INTERVAL); 965 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 966 /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */ 967 968 /* Determine in what context we are running. */ 969 if (ctl & OHCI_IR) { 970 /* SMM active, request change */ 971 DPRINTF("SMM active, request owner change", 0, 0, 0, 0); 972 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 973 (OHCI_OC | OHCI_MIE)) 974 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 975 s = OREAD4(sc, OHCI_COMMAND_STATUS); 976 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 977 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 978 usb_delay_ms(&sc->sc_bus, 1); 979 ctl = OREAD4(sc, OHCI_CONTROL); 980 } 981 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 982 if ((ctl & OHCI_IR) == 0) { 983 aprint_error_dev(sc->sc_dev, 984 "SMM does not respond, resetting\n"); 985 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 986 goto reset; 987 } 988 #if 0 989 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 990 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 991 /* BIOS started controller. */ 992 DPRINTF("BIOS active", 0, 0, 0, 0); 993 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 994 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 995 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 996 } 997 #endif 998 } else { 999 DPRINTF("cold started", 0 ,0 ,0 ,0); 1000 reset: 1001 /* Controller was cold started. */ 1002 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 1003 } 1004 1005 /* 1006 * This reset should not be necessary according to the OHCI spec, but 1007 * without it some controllers do not start. 1008 */ 1009 DPRINTF("sc %p: resetting", sc, 0, 0, 0); 1010 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 1011 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 1012 1013 /* We now own the host controller and the bus has been reset. */ 1014 1015 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 1016 /* Nominal time for a reset is 10 us. */ 1017 for (i = 0; i < 10; i++) { 1018 delay(10); 1019 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 1020 if (!hcr) 1021 break; 1022 } 1023 if (hcr) { 1024 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 1025 err = EIO; 1026 goto bad5; 1027 } 1028 #ifdef OHCI_DEBUG 1029 if (ohcidebug >= 15) 1030 ohci_dumpregs(sc); 1031 #endif 1032 1033 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 1034 1035 /* Set up HC registers. */ 1036 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1037 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 1038 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 1039 /* disable all interrupts and then switch on all desired interrupts */ 1040 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 1041 /* switch on desired functional features */ 1042 ctl = OREAD4(sc, OHCI_CONTROL); 1043 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 1044 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 1045 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 1046 /* And finally start it! */ 1047 OWRITE4(sc, OHCI_CONTROL, ctl); 1048 1049 /* 1050 * The controller is now OPERATIONAL. Set a some final 1051 * registers that should be set earlier, but that the 1052 * controller ignores when in the SUSPEND state. 1053 */ 1054 ival = OHCI_GET_IVAL(fm); 1055 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 1056 fm |= OHCI_FSMPS(ival) | ival; 1057 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 1058 per = OHCI_PERIODIC(ival); /* 90% periodic */ 1059 OWRITE4(sc, OHCI_PERIODIC_START, per); 1060 1061 if (sc->sc_flags & OHCIF_SUPERIO) { 1062 /* no overcurrent protection */ 1063 desca |= OHCI_NOCP; 1064 /* 1065 * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning 1066 * that 1067 * - ports are always power switched 1068 * - don't wait for powered root hub port 1069 */ 1070 desca &= ~(__SHIFTIN(0xff, OHCI_POTPGT_MASK) | OHCI_NPS); 1071 } 1072 1073 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 1074 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 1075 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 1076 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 1077 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 1078 1079 /* 1080 * The AMD756 requires a delay before re-reading the register, 1081 * otherwise it will occasionally report 0 ports. 1082 */ 1083 sc->sc_noport = 0; 1084 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 1085 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 1086 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 1087 } 1088 1089 #ifdef OHCI_DEBUG 1090 if (ohcidebug >= 5) 1091 ohci_dumpregs(sc); 1092 #endif 1093 1094 /* Set up the bus struct. */ 1095 sc->sc_bus.ub_methods = &ohci_bus_methods; 1096 sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe); 1097 1098 sc->sc_control = sc->sc_intre = 0; 1099 1100 /* Finally, turn on interrupts. */ 1101 DPRINTF("enabling %#x", sc->sc_eintrs | OHCI_MIE, 0, 0, 0); 1102 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 1103 1104 return 0; 1105 1106 bad5: 1107 for (i = 0; i < OHCI_NO_EDS; i++) 1108 ohci_free_sed(sc, sc->sc_eds[i]); 1109 bad4: 1110 ohci_free_sed(sc, sc->sc_isoc_head); 1111 bad3: 1112 ohci_free_sed(sc, sc->sc_bulk_head); 1113 bad2: 1114 ohci_free_sed(sc, sc->sc_ctrl_head); 1115 bad1: 1116 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 1117 sc->sc_hcca = NULL; 1118 return err; 1119 } 1120 1121 struct usbd_xfer * 1122 ohci_allocx(struct usbd_bus *bus, unsigned int nframes) 1123 { 1124 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1125 struct usbd_xfer *xfer; 1126 1127 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1128 if (xfer != NULL) { 1129 memset(xfer, 0, sizeof(struct ohci_xfer)); 1130 #ifdef DIAGNOSTIC 1131 xfer->ux_state = XFER_BUSY; 1132 #endif 1133 } 1134 return xfer; 1135 } 1136 1137 void 1138 ohci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1139 { 1140 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1141 1142 KASSERTMSG(xfer->ux_state == XFER_BUSY, 1143 "xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state); 1144 #ifdef DIAGNOSTIC 1145 xfer->ux_state = XFER_FREE; 1146 #endif 1147 pool_cache_put(sc->sc_xferpool, xfer); 1148 } 1149 1150 Static void 1151 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1152 { 1153 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1154 1155 *lock = &sc->sc_lock; 1156 } 1157 1158 /* 1159 * Shut down the controller when the system is going down. 1160 */ 1161 bool 1162 ohci_shutdown(device_t self, int flags) 1163 { 1164 ohci_softc_t *sc = device_private(self); 1165 1166 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1167 1168 DPRINTF("stopping the HC", 0, 0, 0, 0); 1169 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1170 return true; 1171 } 1172 1173 bool 1174 ohci_resume(device_t dv, const pmf_qual_t *qual) 1175 { 1176 ohci_softc_t *sc = device_private(dv); 1177 uint32_t ctl; 1178 1179 mutex_spin_enter(&sc->sc_intr_lock); 1180 sc->sc_bus.ub_usepolling++; 1181 mutex_spin_exit(&sc->sc_intr_lock); 1182 1183 /* Some broken BIOSes do not recover these values */ 1184 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1185 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1186 sc->sc_ctrl_head->physaddr); 1187 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1188 sc->sc_bulk_head->physaddr); 1189 if (sc->sc_intre) 1190 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1191 (OHCI_ALL_INTRS | OHCI_MIE)); 1192 if (sc->sc_control) 1193 ctl = sc->sc_control; 1194 else 1195 ctl = OREAD4(sc, OHCI_CONTROL); 1196 ctl |= OHCI_HCFS_RESUME; 1197 OWRITE4(sc, OHCI_CONTROL, ctl); 1198 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1199 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1200 OWRITE4(sc, OHCI_CONTROL, ctl); 1201 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1202 sc->sc_control = sc->sc_intre = 0; 1203 1204 mutex_spin_enter(&sc->sc_intr_lock); 1205 sc->sc_bus.ub_usepolling--; 1206 mutex_spin_exit(&sc->sc_intr_lock); 1207 1208 return true; 1209 } 1210 1211 bool 1212 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1213 { 1214 ohci_softc_t *sc = device_private(dv); 1215 uint32_t ctl; 1216 1217 mutex_spin_enter(&sc->sc_intr_lock); 1218 sc->sc_bus.ub_usepolling++; 1219 mutex_spin_exit(&sc->sc_intr_lock); 1220 1221 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1222 if (sc->sc_control == 0) { 1223 /* 1224 * Preserve register values, in case that BIOS 1225 * does not recover them. 1226 */ 1227 sc->sc_control = ctl; 1228 sc->sc_intre = OREAD4(sc, 1229 OHCI_INTERRUPT_ENABLE); 1230 } 1231 ctl |= OHCI_HCFS_SUSPEND; 1232 OWRITE4(sc, OHCI_CONTROL, ctl); 1233 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1234 1235 mutex_spin_enter(&sc->sc_intr_lock); 1236 sc->sc_bus.ub_usepolling--; 1237 mutex_spin_exit(&sc->sc_intr_lock); 1238 1239 return true; 1240 } 1241 1242 #ifdef OHCI_DEBUG 1243 void 1244 ohci_dumpregs(ohci_softc_t *sc) 1245 { 1246 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1247 1248 DPRINTF("rev=0x%08x control=0x%08x command=0x%08x", 1249 OREAD4(sc, OHCI_REVISION), 1250 OREAD4(sc, OHCI_CONTROL), 1251 OREAD4(sc, OHCI_COMMAND_STATUS), 0); 1252 DPRINTF(" intrstat=0x%08x intre=0x%08x intrd=0x%08x", 1253 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1254 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1255 OREAD4(sc, OHCI_INTERRUPT_DISABLE), 0); 1256 DPRINTF(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x", 1257 OREAD4(sc, OHCI_HCCA), 1258 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1259 OREAD4(sc, OHCI_CONTROL_HEAD_ED), 0); 1260 DPRINTF(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x", 1261 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1262 OREAD4(sc, OHCI_BULK_HEAD_ED), 1263 OREAD4(sc, OHCI_BULK_CURRENT_ED) ,0); 1264 DPRINTF(" done=0x%08x fmival=0x%08x fmrem=0x%08x", 1265 OREAD4(sc, OHCI_DONE_HEAD), 1266 OREAD4(sc, OHCI_FM_INTERVAL), 1267 OREAD4(sc, OHCI_FM_REMAINING), 0); 1268 DPRINTF(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x", 1269 OREAD4(sc, OHCI_FM_NUMBER), 1270 OREAD4(sc, OHCI_PERIODIC_START), 1271 OREAD4(sc, OHCI_LS_THRESHOLD), 0); 1272 DPRINTF(" desca=0x%08x descb=0x%08x stat=0x%08x", 1273 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1274 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1275 OREAD4(sc, OHCI_RH_STATUS), 0); 1276 DPRINTF(" port1=0x%08x port2=0x%08x", 1277 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1278 OREAD4(sc, OHCI_RH_PORT_STATUS(2)), 0, 0); 1279 DPRINTF(" HCCA: frame_number=0x%04x done_head=0x%08x", 1280 O32TOH(sc->sc_hcca->hcca_frame_number), 1281 O32TOH(sc->sc_hcca->hcca_done_head), 0, 0); 1282 } 1283 #endif 1284 1285 Static int ohci_intr1(ohci_softc_t *); 1286 1287 int 1288 ohci_intr(void *p) 1289 { 1290 ohci_softc_t *sc = p; 1291 int ret = 0; 1292 1293 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1294 1295 if (sc == NULL) 1296 return 0; 1297 1298 mutex_spin_enter(&sc->sc_intr_lock); 1299 1300 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1301 goto done; 1302 1303 /* If we get an interrupt while polling, then just ignore it. */ 1304 if (sc->sc_bus.ub_usepolling) { 1305 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1306 /* for level triggered intrs, should do something to ack */ 1307 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1308 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1309 1310 goto done; 1311 } 1312 1313 ret = ohci_intr1(sc); 1314 1315 done: 1316 mutex_spin_exit(&sc->sc_intr_lock); 1317 return ret; 1318 } 1319 1320 Static int 1321 ohci_intr1(ohci_softc_t *sc) 1322 { 1323 uint32_t intrs, eintrs; 1324 1325 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1326 1327 /* In case the interrupt occurs before initialization has completed. */ 1328 if (sc == NULL || sc->sc_hcca == NULL) { 1329 #ifdef DIAGNOSTIC 1330 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1331 #endif 1332 return 0; 1333 } 1334 1335 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1336 1337 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1338 if (!intrs) 1339 return 0; 1340 1341 /* Acknowledge */ 1342 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); 1343 eintrs = intrs & sc->sc_eintrs; 1344 DPRINTFN(7, "sc=%p", sc, 0, 0, 0); 1345 DPRINTFN(7, "intrs=%#x(%#x) eintrs=%#x(%#x)", 1346 intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), eintrs, 1347 sc->sc_eintrs); 1348 1349 if (!eintrs) { 1350 return 0; 1351 } 1352 1353 if (eintrs & OHCI_SO) { 1354 sc->sc_overrun_cnt++; 1355 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1356 printf("%s: %u scheduling overruns\n", 1357 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1358 sc->sc_overrun_cnt = 0; 1359 } 1360 /* XXX do what */ 1361 eintrs &= ~OHCI_SO; 1362 } 1363 if (eintrs & OHCI_WDH) { 1364 /* 1365 * We block the interrupt below, and reenable it later from 1366 * ohci_softintr(). 1367 */ 1368 usb_schedsoftintr(&sc->sc_bus); 1369 } 1370 if (eintrs & OHCI_RD) { 1371 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1372 /* XXX process resume detect */ 1373 } 1374 if (eintrs & OHCI_UE) { 1375 printf("%s: unrecoverable error, controller halted\n", 1376 device_xname(sc->sc_dev)); 1377 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1378 /* XXX what else */ 1379 } 1380 if (eintrs & OHCI_RHSC) { 1381 /* 1382 * We block the interrupt below, and reenable it later from 1383 * a timeout. 1384 */ 1385 softint_schedule(sc->sc_rhsc_si); 1386 } 1387 1388 if (eintrs != 0) { 1389 /* Block unprocessed interrupts. */ 1390 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1391 sc->sc_eintrs &= ~eintrs; 1392 DPRINTF("sc %p blocking intrs 0x%x", sc, eintrs, 0, 0); 1393 } 1394 1395 return 1; 1396 } 1397 1398 void 1399 ohci_rhsc_enable(void *v_sc) 1400 { 1401 ohci_softc_t *sc = v_sc; 1402 1403 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1404 DPRINTF("sc %p", sc, 0, 0, 0); 1405 mutex_spin_enter(&sc->sc_intr_lock); 1406 sc->sc_eintrs |= OHCI_RHSC; 1407 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1408 mutex_spin_exit(&sc->sc_intr_lock); 1409 } 1410 1411 #ifdef OHCI_DEBUG 1412 const char *ohci_cc_strs[] = { 1413 "NO_ERROR", 1414 "CRC", 1415 "BIT_STUFFING", 1416 "DATA_TOGGLE_MISMATCH", 1417 "STALL", 1418 "DEVICE_NOT_RESPONDING", 1419 "PID_CHECK_FAILURE", 1420 "UNEXPECTED_PID", 1421 "DATA_OVERRUN", 1422 "DATA_UNDERRUN", 1423 "BUFFER_OVERRUN", 1424 "BUFFER_UNDERRUN", 1425 "reserved", 1426 "reserved", 1427 "NOT_ACCESSED", 1428 "NOT_ACCESSED", 1429 }; 1430 #endif 1431 1432 void 1433 ohci_softintr(void *v) 1434 { 1435 struct usbd_bus *bus = v; 1436 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1437 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1438 ohci_soft_td_t *std, *sdone, *stdnext; 1439 struct usbd_xfer *xfer; 1440 struct ohci_pipe *opipe; 1441 int len, cc; 1442 int i, j, actlen, iframes, uedir; 1443 ohci_physaddr_t done; 1444 1445 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1446 1447 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1448 1449 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1450 sizeof(sc->sc_hcca->hcca_done_head), 1451 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1452 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1453 sc->sc_hcca->hcca_done_head = 0; 1454 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1455 sizeof(sc->sc_hcca->hcca_done_head), 1456 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1457 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1458 sc->sc_eintrs |= OHCI_WDH; 1459 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1460 1461 /* Reverse the done list. */ 1462 for (sdone = NULL, sidone = NULL; done != 0; ) { 1463 std = ohci_hash_find_td(sc, done); 1464 if (std != NULL) { 1465 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1466 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1467 std->dnext = sdone; 1468 done = O32TOH(std->td.td_nexttd); 1469 sdone = std; 1470 DPRINTFN(10, "add TD %p", std, 0, 0, 0); 1471 continue; 1472 } 1473 sitd = ohci_hash_find_itd(sc, done); 1474 if (sitd != NULL) { 1475 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1476 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1477 sitd->dnext = sidone; 1478 done = O32TOH(sitd->itd.itd_nextitd); 1479 sidone = sitd; 1480 DPRINTFN(5, "add ITD %p", sitd, 0, 0, 0); 1481 continue; 1482 } 1483 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1484 (u_long)done); 1485 break; 1486 } 1487 1488 DPRINTFN(10, "sdone=%p sidone=%p", sdone, sidone, 0, 0); 1489 DPRINTFN(10, "--- TD dump start ---", 0, 0, 0, 0); 1490 #ifdef OHCI_DEBUG 1491 if (ohcidebug >= 10) { 1492 for (std = sdone; std; std = std->dnext) 1493 ohci_dump_td(sc, std); 1494 } 1495 #endif 1496 DPRINTFN(10, "--- TD dump end ---", 0, 0, 0, 0); 1497 1498 for (std = sdone; std; std = stdnext) { 1499 xfer = std->xfer; 1500 stdnext = std->dnext; 1501 DPRINTFN(10, "std=%p xfer=%p hcpriv=%p", std, xfer, 1502 xfer ? xfer->ux_hcpriv : 0, 0); 1503 if (xfer == NULL) { 1504 /* 1505 * xfer == NULL: There seems to be no xfer associated 1506 * with this TD. It is tailp that happened to end up on 1507 * the done queue. 1508 * Shouldn't happen, but some chips are broken(?). 1509 */ 1510 continue; 1511 } 1512 if (xfer->ux_status == USBD_CANCELLED || 1513 xfer->ux_status == USBD_TIMEOUT) { 1514 DPRINTF("cancel/timeout %p", xfer, 0, 0, 0); 1515 /* Handled by abort routine. */ 1516 continue; 1517 } 1518 callout_stop(&xfer->ux_callout); 1519 1520 len = std->len; 1521 if (std->td.td_cbp != 0) 1522 len -= O32TOH(std->td.td_be) - 1523 O32TOH(std->td.td_cbp) + 1; 1524 DPRINTFN(10, "len=%d, flags=0x%x", len, std->flags, 0, 0); 1525 if (std->flags & OHCI_ADD_LEN) 1526 xfer->ux_actlen += len; 1527 1528 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1529 if (cc == OHCI_CC_NO_ERROR) { 1530 if (std->flags & OHCI_CALL_DONE) { 1531 xfer->ux_status = USBD_NORMAL_COMPLETION; 1532 usb_transfer_complete(xfer); 1533 } 1534 ohci_hash_rem_td(sc, std); 1535 } else { 1536 /* 1537 * Endpoint is halted. First unlink all the TDs 1538 * belonging to the failed transfer, and then restart 1539 * the endpoint. 1540 */ 1541 ohci_soft_td_t *p, *n; 1542 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1543 1544 DPRINTFN(15, "error cc=%d", 1545 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 0, 0, 0); 1546 1547 /* remove xfer's TDs from the hash */ 1548 for (p = std; p->xfer == xfer; p = n) { 1549 n = p->nexttd; 1550 ohci_hash_rem_td(sc, p); 1551 } 1552 1553 /* clear halt */ 1554 opipe->sed->ed.ed_headp = HTOO32(p->physaddr); 1555 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1556 1557 if (cc == OHCI_CC_STALL) 1558 xfer->ux_status = USBD_STALLED; 1559 else 1560 xfer->ux_status = USBD_IOERROR; 1561 usb_transfer_complete(xfer); 1562 } 1563 } 1564 DPRINTFN(10, "--- ITD dump start ---", 0, 0, 0, 0); 1565 #ifdef OHCI_DEBUG 1566 if (ohcidebug >= 10) { 1567 for (sitd = sidone; sitd; sitd = sitd->dnext) 1568 ohci_dump_itd(sc, sitd); 1569 } 1570 #endif 1571 DPRINTFN(10, "--- ITD dump end ---", 0, 0, 0, 0); 1572 1573 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1574 xfer = sitd->xfer; 1575 sitdnext = sitd->dnext; 1576 DPRINTFN(1, "sitd=%p xfer=%p hcpriv=%p", sitd, xfer, 1577 xfer ? xfer->ux_hcpriv : 0, 0); 1578 if (xfer == NULL) 1579 continue; 1580 if (xfer->ux_status == USBD_CANCELLED || 1581 xfer->ux_status == USBD_TIMEOUT) { 1582 DPRINTF("cancel/timeout %p", xfer, 0, 0, 0); 1583 /* Handled by abort routine. */ 1584 continue; 1585 } 1586 KASSERT(!sitd->isdone); 1587 #ifdef DIAGNOSTIC 1588 sitd->isdone = true; 1589 #endif 1590 if (sitd->flags & OHCI_CALL_DONE) { 1591 ohci_soft_itd_t *next; 1592 1593 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1594 opipe->isoc.inuse -= xfer->ux_nframes; 1595 uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc-> 1596 bEndpointAddress); 1597 xfer->ux_status = USBD_NORMAL_COMPLETION; 1598 actlen = 0; 1599 for (i = 0, sitd = xfer->ux_hcpriv;; 1600 sitd = next) { 1601 next = sitd->nextitd; 1602 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1603 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1604 xfer->ux_status = USBD_IOERROR; 1605 /* For input, update frlengths with actual */ 1606 /* XXX anything necessary for output? */ 1607 if (uedir == UE_DIR_IN && 1608 xfer->ux_status == USBD_NORMAL_COMPLETION) { 1609 iframes = OHCI_ITD_GET_FC(O32TOH( 1610 sitd->itd.itd_flags)); 1611 for (j = 0; j < iframes; i++, j++) { 1612 len = O16TOH(sitd-> 1613 itd.itd_offset[j]); 1614 if ((OHCI_ITD_PSW_GET_CC(len) & 1615 OHCI_CC_NOT_ACCESSED_MASK) 1616 == OHCI_CC_NOT_ACCESSED) 1617 len = 0; 1618 else 1619 len = OHCI_ITD_PSW_LENGTH(len); 1620 xfer->ux_frlengths[i] = len; 1621 actlen += len; 1622 } 1623 } 1624 if (sitd->flags & OHCI_CALL_DONE) 1625 break; 1626 ohci_hash_rem_itd(sc, sitd); 1627 1628 } 1629 ohci_hash_rem_itd(sc, sitd); 1630 if (uedir == UE_DIR_IN && 1631 xfer->ux_status == USBD_NORMAL_COMPLETION) 1632 xfer->ux_actlen = actlen; 1633 xfer->ux_hcpriv = NULL; 1634 1635 usb_transfer_complete(xfer); 1636 } 1637 } 1638 1639 if (sc->sc_softwake) { 1640 sc->sc_softwake = 0; 1641 cv_broadcast(&sc->sc_softwake_cv); 1642 } 1643 1644 DPRINTFN(10, "done", 0, 0, 0, 0); 1645 } 1646 1647 void 1648 ohci_device_ctrl_done(struct usbd_xfer *xfer) 1649 { 1650 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1651 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1652 int len = UGETW(xfer->ux_request.wLength); 1653 int isread = (xfer->ux_request.bmRequestType & UT_READ); 1654 1655 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1656 DPRINTFN(10, "xfer=%p", xfer, 0, 0, 0); 1657 1658 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1659 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 1660 1661 if (len) 1662 usb_syncmem(&xfer->ux_dmabuf, 0, len, 1663 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1664 usb_syncmem(&opipe->ctrl.reqdma, 0, 1665 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1666 } 1667 1668 void 1669 ohci_device_intr_done(struct usbd_xfer *xfer) 1670 { 1671 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 1672 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1673 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1674 ohci_soft_ed_t *sed = opipe->sed; 1675 int isread = 1676 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1677 1678 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1679 DPRINTFN(10, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0); 1680 1681 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1682 1683 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1684 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1685 if (xfer->ux_pipe->up_repeat) { 1686 ohci_soft_td_t *data, *last, *tail; 1687 int len = xfer->ux_length; 1688 1689 /* Use "tail" TD and loan our first TD to next transfer */ 1690 data = opipe->tail.td; 1691 opipe->tail.td = ox->ox_stds[0]; 1692 ox->ox_stds[0] = data; 1693 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 1694 1695 tail = opipe->tail.td; /* point at sentinel */ 1696 memset(&tail->td, 0, sizeof(tail->td)); 1697 tail->nexttd = NULL; 1698 tail->xfer = NULL; 1699 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 1700 BUS_DMASYNC_PREWRITE); 1701 1702 /* We want interrupt at the end of the transfer. */ 1703 last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 1704 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 1705 1706 last->td.td_nexttd = HTOO32(tail->physaddr); 1707 last->nexttd = tail; 1708 last->flags |= OHCI_CALL_DONE; 1709 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 1710 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1711 1712 xfer->ux_hcpriv = data; 1713 xfer->ux_actlen = 0; 1714 1715 /* Insert ED in schedule */ 1716 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1717 usb_syncmem(&sed->dma, 1718 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1719 sizeof(sed->ed.ed_tailp), 1720 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1721 } 1722 } 1723 1724 void 1725 ohci_device_bulk_done(struct usbd_xfer *xfer) 1726 { 1727 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1728 1729 int isread = 1730 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1731 1732 KASSERT(mutex_owned(&sc->sc_lock)); 1733 1734 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1735 DPRINTFN(10, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0); 1736 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1737 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1738 } 1739 1740 Static void 1741 ohci_rhsc_softint(void *arg) 1742 { 1743 ohci_softc_t *sc = arg; 1744 1745 mutex_enter(&sc->sc_lock); 1746 1747 ohci_rhsc(sc, sc->sc_intrxfer); 1748 1749 /* Do not allow RHSC interrupts > 1 per second */ 1750 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1751 1752 mutex_exit(&sc->sc_lock); 1753 } 1754 1755 void 1756 ohci_rhsc(ohci_softc_t *sc, struct usbd_xfer *xfer) 1757 { 1758 u_char *p; 1759 int i, m; 1760 int hstatus __unused; 1761 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1762 1763 KASSERT(mutex_owned(&sc->sc_lock)); 1764 1765 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1766 DPRINTF("sc=%p xfer=%p hstatus=0x%08x", sc, xfer, hstatus, 0); 1767 1768 if (xfer == NULL) { 1769 /* Just ignore the change. */ 1770 return; 1771 } 1772 1773 p = xfer->ux_buf; 1774 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 1775 memset(p, 0, xfer->ux_length); 1776 for (i = 1; i <= m; i++) { 1777 /* Pick out CHANGE bits from the status reg. */ 1778 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1779 p[i/8] |= 1 << (i%8); 1780 } 1781 DPRINTF("change=0x%02x", *p, 0, 0, 0); 1782 xfer->ux_actlen = xfer->ux_length; 1783 xfer->ux_status = USBD_NORMAL_COMPLETION; 1784 1785 usb_transfer_complete(xfer); 1786 } 1787 1788 void 1789 ohci_root_intr_done(struct usbd_xfer *xfer) 1790 { 1791 } 1792 1793 /* 1794 * Wait here until controller claims to have an interrupt. 1795 * Then call ohci_intr and return. Use timeout to avoid waiting 1796 * too long. 1797 */ 1798 void 1799 ohci_waitintr(ohci_softc_t *sc, struct usbd_xfer *xfer) 1800 { 1801 int timo; 1802 uint32_t intrs; 1803 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1804 1805 mutex_enter(&sc->sc_lock); 1806 1807 xfer->ux_status = USBD_IN_PROGRESS; 1808 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1809 usb_delay_ms(&sc->sc_bus, 1); 1810 if (sc->sc_dying) 1811 break; 1812 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 1813 DPRINTFN(15, "intrs 0x%04x", intrs, 0, 0, 0); 1814 #ifdef OHCI_DEBUG 1815 if (ohcidebug > 15) 1816 ohci_dumpregs(sc); 1817 #endif 1818 if (intrs) { 1819 mutex_spin_enter(&sc->sc_intr_lock); 1820 ohci_intr1(sc); 1821 mutex_spin_exit(&sc->sc_intr_lock); 1822 if (xfer->ux_status != USBD_IN_PROGRESS) 1823 goto done; 1824 } 1825 } 1826 1827 /* Timeout */ 1828 DPRINTF("timeout", 0, 0, 0, 0); 1829 xfer->ux_status = USBD_TIMEOUT; 1830 usb_transfer_complete(xfer); 1831 1832 done: 1833 mutex_exit(&sc->sc_lock); 1834 } 1835 1836 void 1837 ohci_poll(struct usbd_bus *bus) 1838 { 1839 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1840 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1841 1842 #ifdef OHCI_DEBUG 1843 static int last; 1844 int new; 1845 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1846 if (new != last) { 1847 DPRINTFN(10, "intrs=0x%04x", new, 0, 0, 0); 1848 last = new; 1849 } 1850 #endif 1851 sc->sc_eintrs |= OHCI_WDH; 1852 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1853 mutex_spin_enter(&sc->sc_intr_lock); 1854 ohci_intr1(sc); 1855 mutex_spin_exit(&sc->sc_intr_lock); 1856 } 1857 } 1858 1859 /* 1860 * Add an ED to the schedule. Called with USB lock held. 1861 */ 1862 Static void 1863 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1864 { 1865 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1866 DPRINTFN(8, "sed=%p head=%p", sed, head, 0, 0); 1867 1868 KASSERT(mutex_owned(&sc->sc_lock)); 1869 1870 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1871 sizeof(head->ed.ed_nexted), 1872 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1873 sed->next = head->next; 1874 sed->ed.ed_nexted = head->ed.ed_nexted; 1875 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1876 sizeof(sed->ed.ed_nexted), 1877 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1878 head->next = sed; 1879 head->ed.ed_nexted = HTOO32(sed->physaddr); 1880 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1881 sizeof(head->ed.ed_nexted), 1882 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1883 } 1884 1885 /* 1886 * Remove an ED from the schedule. Called with USB lock held. 1887 */ 1888 Static void 1889 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1890 { 1891 ohci_soft_ed_t *p; 1892 1893 KASSERT(mutex_owned(&sc->sc_lock)); 1894 1895 /* XXX */ 1896 for (p = head; p != NULL && p->next != sed; p = p->next) 1897 ; 1898 KASSERT(p != NULL); 1899 1900 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1901 sizeof(sed->ed.ed_nexted), 1902 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1903 p->next = sed->next; 1904 p->ed.ed_nexted = sed->ed.ed_nexted; 1905 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1906 sizeof(p->ed.ed_nexted), 1907 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1908 } 1909 1910 /* 1911 * When a transfer is completed the TD is added to the done queue by 1912 * the host controller. This queue is the processed by software. 1913 * Unfortunately the queue contains the physical address of the TD 1914 * and we have no simple way to translate this back to a kernel address. 1915 * To make the translation possible (and fast) we use a hash table of 1916 * TDs currently in the schedule. The physical address is used as the 1917 * hash value. 1918 */ 1919 1920 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1921 /* Called with USB lock held. */ 1922 void 1923 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1924 { 1925 int h = HASH(std->physaddr); 1926 1927 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1928 1929 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1930 } 1931 1932 /* Called with USB lock held. */ 1933 void 1934 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1935 { 1936 1937 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1938 1939 LIST_REMOVE(std, hnext); 1940 } 1941 1942 ohci_soft_td_t * 1943 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1944 { 1945 int h = HASH(a); 1946 ohci_soft_td_t *std; 1947 1948 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1949 std != NULL; 1950 std = LIST_NEXT(std, hnext)) 1951 if (std->physaddr == a) 1952 return std; 1953 return NULL; 1954 } 1955 1956 /* Called with USB lock held. */ 1957 void 1958 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1959 { 1960 int h = HASH(sitd->physaddr); 1961 1962 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1963 1964 KASSERT(mutex_owned(&sc->sc_lock)); 1965 1966 DPRINTFN(10, "sitd=%p physaddr=0x%08lx", sitd, (u_long)sitd->physaddr, 1967 0, 0); 1968 1969 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1970 } 1971 1972 /* Called with USB lock held. */ 1973 void 1974 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1975 { 1976 1977 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1978 1979 KASSERT(mutex_owned(&sc->sc_lock)); 1980 1981 DPRINTFN(10, "sitd=%p physaddr=0x%08lx", sitd, (u_long)sitd->physaddr, 1982 0, 0); 1983 1984 LIST_REMOVE(sitd, hnext); 1985 } 1986 1987 ohci_soft_itd_t * 1988 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1989 { 1990 int h = HASH(a); 1991 ohci_soft_itd_t *sitd; 1992 1993 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1994 sitd != NULL; 1995 sitd = LIST_NEXT(sitd, hnext)) 1996 if (sitd->physaddr == a) 1997 return sitd; 1998 return NULL; 1999 } 2000 2001 void 2002 ohci_timeout(void *addr) 2003 { 2004 struct usbd_xfer *xfer = addr; 2005 struct ohci_xfer *oxfer = OHCI_XFER2OXFER(xfer); 2006 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2007 2008 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2009 DPRINTF("oxfer=%p", oxfer, 0, 0, 0); 2010 2011 if (sc->sc_dying) { 2012 mutex_enter(&sc->sc_lock); 2013 ohci_abort_xfer(xfer, USBD_TIMEOUT); 2014 mutex_exit(&sc->sc_lock); 2015 return; 2016 } 2017 2018 /* Execute the abort in a process context. */ 2019 usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr, 2020 USB_TASKQ_MPSAFE); 2021 usb_add_task(xfer->ux_pipe->up_dev, &oxfer->abort_task, 2022 USB_TASKQ_HC); 2023 } 2024 2025 void 2026 ohci_timeout_task(void *addr) 2027 { 2028 struct usbd_xfer *xfer = addr; 2029 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2030 2031 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2032 2033 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2034 2035 mutex_enter(&sc->sc_lock); 2036 ohci_abort_xfer(xfer, USBD_TIMEOUT); 2037 mutex_exit(&sc->sc_lock); 2038 } 2039 2040 #ifdef OHCI_DEBUG 2041 void 2042 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 2043 { 2044 for (; std; std = std->nexttd) { 2045 ohci_dump_td(sc, std); 2046 KASSERTMSG(std->nexttd == NULL || std != std->nexttd, 2047 "std %p next %p", std, std->nexttd); 2048 } 2049 } 2050 2051 void 2052 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 2053 { 2054 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2055 2056 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2057 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2058 2059 uint32_t flags = O32TOH(std->td.td_flags); 2060 DPRINTF("TD(%p) at 0x%08lx:", std, (u_long)std->physaddr, 0, 0); 2061 DPRINTF(" round=%d DP=%x DI=%x T=%x", 2062 !!(flags & OHCI_TD_R), 2063 __SHIFTOUT(flags, OHCI_TD_DP_MASK), 2064 OHCI_TD_GET_DI(flags), 2065 __SHIFTOUT(flags, OHCI_TD_TOGGLE_MASK)); 2066 DPRINTF(" EC=%d CC=%d", OHCI_TD_GET_EC(flags), OHCI_TD_GET_CC(flags), 2067 0, 0); 2068 DPRINTF(" cbp=0x%08lx nexttd=0x%08lx be=0x%08lx", 2069 (u_long)O32TOH(std->td.td_cbp), 2070 (u_long)O32TOH(std->td.td_nexttd), 2071 (u_long)O32TOH(std->td.td_be), 0); 2072 } 2073 2074 void 2075 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2076 { 2077 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2078 2079 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 2080 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2081 2082 uint32_t flags = O32TOH(sitd->itd.itd_flags); 2083 DPRINTF("ITD(%p) at 0x%08lx", sitd, (u_long)sitd->physaddr, 0, 0); 2084 DPRINTF(" sf=%d di=%d fc=%d cc=%d", 2085 OHCI_ITD_GET_SF(flags), OHCI_ITD_GET_DI(flags), 2086 OHCI_ITD_GET_FC(flags), OHCI_ITD_GET_CC(flags)); 2087 DPRINTF(" bp0=0x%08x next=0x%08x be=0x%08x", 2088 O32TOH(sitd->itd.itd_bp0), 2089 O32TOH(sitd->itd.itd_nextitd), 2090 O32TOH(sitd->itd.itd_be), 0); 2091 CTASSERT(OHCI_ITD_NOFFSET == 8); 2092 DPRINTF(" offs[0] = 0x%04x offs[1] = 0x%04x " 2093 "offs[2] = 0x%04x offs[3] = 0x%04x", 2094 O16TOH(sitd->itd.itd_offset[0]), 2095 O16TOH(sitd->itd.itd_offset[1]), 2096 O16TOH(sitd->itd.itd_offset[2]), 2097 O16TOH(sitd->itd.itd_offset[3])); 2098 DPRINTF(" offs[4] = 0x%04x offs[5] = 0x%04x " 2099 "offs[6] = 0x%04x offs[7] = 0x%04x", 2100 O16TOH(sitd->itd.itd_offset[4]), 2101 O16TOH(sitd->itd.itd_offset[5]), 2102 O16TOH(sitd->itd.itd_offset[6]), 2103 O16TOH(sitd->itd.itd_offset[7])); 2104 } 2105 2106 void 2107 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2108 { 2109 for (; sitd; sitd = sitd->nextitd) 2110 ohci_dump_itd(sc, sitd); 2111 } 2112 2113 void 2114 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2115 { 2116 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2117 2118 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2119 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2120 2121 uint32_t flags = O32TOH(sed->ed.ed_flags); 2122 DPRINTF("ED(%p) at 0x%08lx:", sed, sed->physaddr, 0, 0); 2123 DPRINTF(" addr=%d endpt=%d maxp=%d", 2124 OHCI_ED_GET_FA(flags), 2125 OHCI_ED_GET_EN(flags), 2126 OHCI_ED_GET_MAXP(flags), 2127 0); 2128 DPRINTF(" dir=%d speed=%d skip=%d iso=%d", 2129 __SHIFTOUT(flags, OHCI_ED_DIR_MASK), 2130 !!(flags & OHCI_ED_SPEED), 2131 !!(flags & OHCI_ED_SKIP), 2132 !!(flags & OHCI_ED_FORMAT_ISO)); 2133 DPRINTF(" tailp=0x%08lx", (u_long)O32TOH(sed->ed.ed_tailp), 2134 0, 0, 0); 2135 DPRINTF(" headp=0x%08lx nexted=0x%08lx halted=%d carry=%d", 2136 O32TOH(sed->ed.ed_headp), O32TOH(sed->ed.ed_nexted), 2137 !!(O32TOH(sed->ed.ed_headp) & OHCI_HALTED), 2138 !!(O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 2139 } 2140 #endif 2141 2142 usbd_status 2143 ohci_open(struct usbd_pipe *pipe) 2144 { 2145 struct usbd_device *dev = pipe->up_dev; 2146 struct usbd_bus *bus = dev->ud_bus; 2147 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2148 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 2149 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2150 uint8_t addr = dev->ud_addr; 2151 uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2152 ohci_soft_ed_t *sed; 2153 ohci_soft_td_t *std; 2154 ohci_soft_itd_t *sitd; 2155 ohci_physaddr_t tdphys; 2156 uint32_t fmt; 2157 usbd_status err = USBD_NOMEM; 2158 int ival; 2159 2160 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2161 DPRINTFN(1, "pipe=%p, addr=%d, endpt=%d (%d)", pipe, addr, 2162 ed->bEndpointAddress, bus->ub_rhaddr); 2163 2164 if (sc->sc_dying) { 2165 return USBD_IOERROR; 2166 } 2167 2168 std = NULL; 2169 sed = NULL; 2170 2171 if (addr == bus->ub_rhaddr) { 2172 switch (ed->bEndpointAddress) { 2173 case USB_CONTROL_ENDPOINT: 2174 pipe->up_methods = &roothub_ctrl_methods; 2175 break; 2176 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 2177 pipe->up_methods = &ohci_root_intr_methods; 2178 break; 2179 default: 2180 err = USBD_INVAL; 2181 goto bad; 2182 } 2183 } else { 2184 sed = ohci_alloc_sed(sc); 2185 if (sed == NULL) 2186 goto bad; 2187 opipe->sed = sed; 2188 if (xfertype == UE_ISOCHRONOUS) { 2189 sitd = ohci_alloc_sitd(sc); 2190 if (sitd == NULL) 2191 goto bad; 2192 2193 opipe->tail.itd = sitd; 2194 tdphys = sitd->physaddr; 2195 fmt = OHCI_ED_FORMAT_ISO; 2196 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2197 fmt |= OHCI_ED_DIR_IN; 2198 else 2199 fmt |= OHCI_ED_DIR_OUT; 2200 } else { 2201 std = ohci_alloc_std(sc); 2202 if (std == NULL) 2203 goto bad; 2204 2205 opipe->tail.td = std; 2206 tdphys = std->physaddr; 2207 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2208 } 2209 sed->ed.ed_flags = HTOO32( 2210 OHCI_ED_SET_FA(addr) | 2211 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2212 (dev->ud_speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2213 fmt | 2214 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2215 sed->ed.ed_headp = HTOO32(tdphys | 2216 (pipe->up_endpoint->ue_toggle ? OHCI_TOGGLECARRY : 0)); 2217 sed->ed.ed_tailp = HTOO32(tdphys); 2218 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2219 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2220 2221 switch (xfertype) { 2222 case UE_CONTROL: 2223 pipe->up_methods = &ohci_device_ctrl_methods; 2224 err = usb_allocmem(&sc->sc_bus, 2225 sizeof(usb_device_request_t), 2226 0, &opipe->ctrl.reqdma); 2227 if (err) 2228 goto bad; 2229 mutex_enter(&sc->sc_lock); 2230 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2231 mutex_exit(&sc->sc_lock); 2232 break; 2233 case UE_INTERRUPT: 2234 pipe->up_methods = &ohci_device_intr_methods; 2235 ival = pipe->up_interval; 2236 if (ival == USBD_DEFAULT_INTERVAL) 2237 ival = ed->bInterval; 2238 err = ohci_device_setintr(sc, opipe, ival); 2239 if (err) 2240 goto bad; 2241 break; 2242 case UE_ISOCHRONOUS: 2243 pipe->up_methods = &ohci_device_isoc_methods; 2244 return ohci_setup_isoc(pipe); 2245 case UE_BULK: 2246 pipe->up_methods = &ohci_device_bulk_methods; 2247 mutex_enter(&sc->sc_lock); 2248 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2249 mutex_exit(&sc->sc_lock); 2250 break; 2251 } 2252 } 2253 2254 return USBD_NORMAL_COMPLETION; 2255 2256 bad: 2257 if (std != NULL) { 2258 ohci_free_std(sc, std); 2259 } 2260 if (sed != NULL) 2261 ohci_free_sed(sc, sed); 2262 return err; 2263 2264 } 2265 2266 /* 2267 * Close a reqular pipe. 2268 * Assumes that there are no pending transactions. 2269 */ 2270 void 2271 ohci_close_pipe(struct usbd_pipe *pipe, ohci_soft_ed_t *head) 2272 { 2273 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2274 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2275 ohci_soft_ed_t *sed = opipe->sed; 2276 2277 KASSERT(mutex_owned(&sc->sc_lock)); 2278 2279 #ifdef DIAGNOSTIC 2280 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2281 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2282 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2283 ohci_soft_td_t *std; 2284 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2285 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2286 "tl=0x%x pipe=%p, std=%p\n", sed, 2287 (int)O32TOH(sed->ed.ed_headp), 2288 (int)O32TOH(sed->ed.ed_tailp), 2289 pipe, std); 2290 #ifdef OHCI_DEBUG 2291 usbd_dump_pipe(&opipe->pipe); 2292 ohci_dump_ed(sc, sed); 2293 if (std) 2294 ohci_dump_td(sc, std); 2295 #endif 2296 usb_delay_ms(&sc->sc_bus, 2); 2297 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2298 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2299 printf("ohci_close_pipe: pipe still not empty\n"); 2300 } 2301 #endif 2302 ohci_rem_ed(sc, sed, head); 2303 /* Make sure the host controller is not touching this ED */ 2304 usb_delay_ms(&sc->sc_bus, 1); 2305 pipe->up_endpoint->ue_toggle = 2306 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2307 ohci_free_sed_locked(sc, opipe->sed); 2308 } 2309 2310 /* 2311 * Abort a device request. 2312 * If this routine is called at splusb() it guarantees that the request 2313 * will be removed from the hardware scheduling and that the callback 2314 * for it will be called with USBD_CANCELLED status. 2315 * It's impossible to guarantee that the requested transfer will not 2316 * have happened since the hardware runs concurrently. 2317 * If the transaction has already happened we rely on the ordinary 2318 * interrupt processing to process it. 2319 * XXX This is most probably wrong. 2320 * XXXMRG this doesn't make sense anymore. 2321 */ 2322 void 2323 ohci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2324 { 2325 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2326 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2327 ohci_soft_ed_t *sed = opipe->sed; 2328 ohci_soft_td_t *p, *n; 2329 ohci_physaddr_t headp; 2330 int hit; 2331 int wake; 2332 2333 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2334 DPRINTF("xfer=%p pipe=%p sed=%p", xfer, opipe,sed, 0); 2335 2336 KASSERT(mutex_owned(&sc->sc_lock)); 2337 ASSERT_SLEEPABLE(); 2338 2339 if (sc->sc_dying) { 2340 /* If we're dying, just do the software part. */ 2341 xfer->ux_status = status; /* make software ignore it */ 2342 callout_halt(&xfer->ux_callout, &sc->sc_lock); 2343 usb_transfer_complete(xfer); 2344 return; 2345 } 2346 2347 /* 2348 * If an abort is already in progress then just wait for it to 2349 * complete and return. 2350 */ 2351 if (xfer->ux_hcflags & UXFER_ABORTING) { 2352 DPRINTFN(2, "already aborting", 0, 0, 0, 0); 2353 #ifdef DIAGNOSTIC 2354 if (status == USBD_TIMEOUT) 2355 printf("%s: TIMEOUT while aborting\n", __func__); 2356 #endif 2357 /* Override the status which might be USBD_TIMEOUT. */ 2358 xfer->ux_status = status; 2359 DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0); 2360 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2361 while (xfer->ux_hcflags & UXFER_ABORTING) 2362 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2363 goto done; 2364 } 2365 xfer->ux_hcflags |= UXFER_ABORTING; 2366 2367 /* 2368 * Step 1: Make interrupt routine and hardware ignore xfer. 2369 */ 2370 xfer->ux_status = status; /* make software ignore it */ 2371 callout_stop(&xfer->ux_callout); 2372 DPRINTFN(1, "stop ed=%p", sed, 0, 0, 0); 2373 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2374 sizeof(sed->ed.ed_flags), 2375 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2376 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2377 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2378 sizeof(sed->ed.ed_flags), 2379 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2380 2381 /* 2382 * Step 2: Wait until we know hardware has finished any possible 2383 * use of the xfer. Also make sure the soft interrupt routine 2384 * has run. 2385 */ 2386 /* Hardware finishes in 1ms */ 2387 usb_delay_ms_locked(opipe->pipe.up_dev->ud_bus, 20, &sc->sc_lock); 2388 sc->sc_softwake = 1; 2389 usb_schedsoftintr(&sc->sc_bus); 2390 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2391 2392 /* 2393 * Step 3: Remove any vestiges of the xfer from the hardware. 2394 * The complication here is that the hardware may have executed 2395 * beyond the xfer we're trying to abort. So as we're scanning 2396 * the TDs of this xfer we check if the hardware points to 2397 * any of them. 2398 */ 2399 p = xfer->ux_hcpriv; 2400 KASSERT(p); 2401 2402 #ifdef OHCI_DEBUG 2403 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2404 2405 if (ohcidebug >= 2) { 2406 DPRINTF("sed:", 0, 0, 0, 0); 2407 ohci_dump_ed(sc, sed); 2408 ohci_dump_tds(sc, p); 2409 } 2410 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2411 #endif 2412 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2413 hit = 0; 2414 for (; p->xfer == xfer; p = n) { 2415 hit |= headp == p->physaddr; 2416 n = p->nexttd; 2417 ohci_hash_rem_td(sc, p); 2418 } 2419 /* Zap headp register if hardware pointed inside the xfer. */ 2420 if (hit) { 2421 DPRINTFN(1, "set hd=0x%08x, tl=0x%08x", (int)p->physaddr, 2422 (int)O32TOH(sed->ed.ed_tailp), 0, 0); 2423 sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */ 2424 usb_syncmem(&sed->dma, 2425 sed->offs + offsetof(ohci_ed_t, ed_headp), 2426 sizeof(sed->ed.ed_headp), 2427 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2428 } else { 2429 DPRINTFN(1, "no hit", 0, 0, 0, 0); 2430 } 2431 2432 /* 2433 * Step 4: Turn on hardware again. 2434 */ 2435 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2436 sizeof(sed->ed.ed_flags), 2437 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2438 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2439 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2440 sizeof(sed->ed.ed_flags), 2441 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2442 2443 /* 2444 * Step 5: Execute callback. 2445 */ 2446 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2447 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2448 usb_transfer_complete(xfer); 2449 if (wake) 2450 cv_broadcast(&xfer->ux_hccv); 2451 2452 done: 2453 KASSERT(mutex_owned(&sc->sc_lock)); 2454 } 2455 2456 /* 2457 * Data structures and routines to emulate the root hub. 2458 */ 2459 Static int 2460 ohci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2461 void *buf, int buflen) 2462 { 2463 ohci_softc_t *sc = OHCI_BUS2SC(bus); 2464 usb_port_status_t ps; 2465 uint16_t len, value, index; 2466 int l, totlen = 0; 2467 int port, i; 2468 uint32_t v; 2469 2470 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2471 2472 if (sc->sc_dying) 2473 return -1; 2474 2475 DPRINTFN(4, "type=0x%02x request=%02x", req->bmRequestType, 2476 req->bRequest, 0, 0); 2477 2478 len = UGETW(req->wLength); 2479 value = UGETW(req->wValue); 2480 index = UGETW(req->wIndex); 2481 2482 #define C(x,y) ((x) | ((y) << 8)) 2483 switch (C(req->bRequest, req->bmRequestType)) { 2484 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2485 DPRINTFN(8, "wValue=0x%04x", value, 0, 0, 0); 2486 if (len == 0) 2487 break; 2488 switch (value) { 2489 case C(0, UDESC_DEVICE): { 2490 usb_device_descriptor_t devd; 2491 2492 totlen = min(buflen, sizeof(devd)); 2493 memcpy(&devd, buf, totlen); 2494 USETW(devd.idVendor, sc->sc_id_vendor); 2495 memcpy(buf, &devd, totlen); 2496 break; 2497 } 2498 case C(1, UDESC_STRING): 2499 #define sd ((usb_string_descriptor_t *)buf) 2500 /* Vendor */ 2501 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2502 break; 2503 case C(2, UDESC_STRING): 2504 /* Product */ 2505 totlen = usb_makestrdesc(sd, len, "OHCI root hub"); 2506 break; 2507 #undef sd 2508 default: 2509 /* default from usbroothub */ 2510 return buflen; 2511 } 2512 break; 2513 2514 /* Hub requests */ 2515 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2516 break; 2517 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2518 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 2519 index, value, 0, 0); 2520 if (index < 1 || index > sc->sc_noport) { 2521 return -1; 2522 } 2523 port = OHCI_RH_PORT_STATUS(index); 2524 switch(value) { 2525 case UHF_PORT_ENABLE: 2526 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2527 break; 2528 case UHF_PORT_SUSPEND: 2529 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2530 break; 2531 case UHF_PORT_POWER: 2532 /* Yes, writing to the LOW_SPEED bit clears power. */ 2533 OWRITE4(sc, port, UPS_LOW_SPEED); 2534 break; 2535 case UHF_C_PORT_CONNECTION: 2536 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2537 break; 2538 case UHF_C_PORT_ENABLE: 2539 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2540 break; 2541 case UHF_C_PORT_SUSPEND: 2542 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2543 break; 2544 case UHF_C_PORT_OVER_CURRENT: 2545 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2546 break; 2547 case UHF_C_PORT_RESET: 2548 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2549 break; 2550 default: 2551 return -1; 2552 } 2553 switch(value) { 2554 case UHF_C_PORT_CONNECTION: 2555 case UHF_C_PORT_ENABLE: 2556 case UHF_C_PORT_SUSPEND: 2557 case UHF_C_PORT_OVER_CURRENT: 2558 case UHF_C_PORT_RESET: 2559 /* Enable RHSC interrupt if condition is cleared. */ 2560 if ((OREAD4(sc, port) >> 16) == 0) 2561 ohci_rhsc_enable(sc); 2562 break; 2563 default: 2564 break; 2565 } 2566 break; 2567 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2568 if (len == 0) 2569 break; 2570 if ((value & 0xff) != 0) { 2571 return -1; 2572 } 2573 usb_hub_descriptor_t hubd; 2574 2575 totlen = min(buflen, sizeof(hubd)); 2576 memcpy(&hubd, buf, totlen); 2577 2578 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2579 hubd.bNbrPorts = sc->sc_noport; 2580 USETW(hubd.wHubCharacteristics, 2581 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2582 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2583 /* XXX overcurrent */ 2584 ); 2585 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2586 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2587 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2588 hubd.DeviceRemovable[i++] = (uint8_t)v; 2589 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2590 totlen = min(totlen, hubd.bDescLength); 2591 memcpy(buf, &hubd, totlen); 2592 break; 2593 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2594 if (len != 4) { 2595 return -1; 2596 } 2597 memset(buf, 0, len); /* ? XXX */ 2598 totlen = len; 2599 break; 2600 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2601 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 2602 if (index < 1 || index > sc->sc_noport) { 2603 return -1; 2604 } 2605 if (len != 4) { 2606 return -1; 2607 } 2608 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2609 DPRINTFN(8, "port status=0x%04x", v, 0, 0, 0); 2610 USETW(ps.wPortStatus, v); 2611 USETW(ps.wPortChange, v >> 16); 2612 totlen = min(len, sizeof(ps)); 2613 memcpy(buf, &ps, totlen); 2614 break; 2615 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2616 return -1; 2617 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2618 break; 2619 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2620 if (index < 1 || index > sc->sc_noport) { 2621 return -1; 2622 } 2623 port = OHCI_RH_PORT_STATUS(index); 2624 switch(value) { 2625 case UHF_PORT_ENABLE: 2626 OWRITE4(sc, port, UPS_PORT_ENABLED); 2627 break; 2628 case UHF_PORT_SUSPEND: 2629 OWRITE4(sc, port, UPS_SUSPEND); 2630 break; 2631 case UHF_PORT_RESET: 2632 DPRINTFN(5, "reset port %d", index, 0, 0, 0); 2633 OWRITE4(sc, port, UPS_RESET); 2634 for (i = 0; i < 5; i++) { 2635 usb_delay_ms(&sc->sc_bus, 2636 USB_PORT_ROOT_RESET_DELAY); 2637 if (sc->sc_dying) { 2638 return -1; 2639 } 2640 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2641 break; 2642 } 2643 DPRINTFN(8, "port %d reset, status = 0x%04x", index, 2644 OREAD4(sc, port), 0, 0); 2645 break; 2646 case UHF_PORT_POWER: 2647 DPRINTFN(2, "set port power %d", index, 0, 0, 0); 2648 OWRITE4(sc, port, UPS_PORT_POWER); 2649 break; 2650 default: 2651 return -1; 2652 } 2653 break; 2654 default: 2655 /* default from usbroothub */ 2656 return buflen; 2657 } 2658 2659 return totlen; 2660 } 2661 2662 Static usbd_status 2663 ohci_root_intr_transfer(struct usbd_xfer *xfer) 2664 { 2665 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2666 usbd_status err; 2667 2668 /* Insert last in queue. */ 2669 mutex_enter(&sc->sc_lock); 2670 err = usb_insert_transfer(xfer); 2671 mutex_exit(&sc->sc_lock); 2672 if (err) 2673 return err; 2674 2675 /* Pipe isn't running, start first */ 2676 return ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2677 } 2678 2679 Static usbd_status 2680 ohci_root_intr_start(struct usbd_xfer *xfer) 2681 { 2682 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2683 2684 if (sc->sc_dying) 2685 return USBD_IOERROR; 2686 2687 mutex_enter(&sc->sc_lock); 2688 KASSERT(sc->sc_intrxfer == NULL); 2689 sc->sc_intrxfer = xfer; 2690 mutex_exit(&sc->sc_lock); 2691 2692 return USBD_IN_PROGRESS; 2693 } 2694 2695 /* Abort a root interrupt request. */ 2696 Static void 2697 ohci_root_intr_abort(struct usbd_xfer *xfer) 2698 { 2699 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2700 2701 KASSERT(mutex_owned(&sc->sc_lock)); 2702 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2703 2704 sc->sc_intrxfer = NULL; 2705 2706 xfer->ux_status = USBD_CANCELLED; 2707 usb_transfer_complete(xfer); 2708 } 2709 2710 /* Close the root pipe. */ 2711 Static void 2712 ohci_root_intr_close(struct usbd_pipe *pipe) 2713 { 2714 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2715 2716 KASSERT(mutex_owned(&sc->sc_lock)); 2717 2718 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2719 2720 sc->sc_intrxfer = NULL; 2721 } 2722 2723 /************************/ 2724 2725 int 2726 ohci_device_ctrl_init(struct usbd_xfer *xfer) 2727 { 2728 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2729 usb_device_request_t *req = &xfer->ux_request; 2730 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2731 ohci_soft_td_t *stat, *tail; 2732 int isread = req->bmRequestType & UT_READ; 2733 int len = xfer->ux_bufsize; 2734 int err = ENOMEM; 2735 2736 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2737 2738 /* The TD for setup will be a 'tail' from elsewhere */ 2739 stat = ohci_alloc_std(sc); 2740 if (stat == NULL) { 2741 goto bad1; 2742 } 2743 tail = ohci_alloc_std(sc); 2744 if (tail == NULL) { 2745 goto bad2; 2746 } 2747 tail->xfer = NULL; 2748 2749 ox->ox_stat = stat; 2750 ox->ox_tdtail = tail; 2751 ox->ox_nstd = 0; 2752 2753 /* Set up data transaction */ 2754 if (len != 0) { 2755 err = ohci_alloc_std_chain(sc, xfer, len, isread); 2756 if (err) { 2757 goto bad3; 2758 } 2759 } 2760 return 0; 2761 2762 bad3: 2763 ohci_free_std(sc, tail); 2764 bad2: 2765 ohci_free_std(sc, stat); 2766 bad1: 2767 return err; 2768 } 2769 2770 void 2771 ohci_device_ctrl_fini(struct usbd_xfer *xfer) 2772 { 2773 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2774 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2775 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2776 2777 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2778 DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0); 2779 2780 mutex_enter(&sc->sc_lock); 2781 if (ox->ox_tdtail != opipe->tail.td) { 2782 ohci_free_std_locked(sc, ox->ox_tdtail); 2783 } 2784 for (size_t i = 0; i < ox->ox_nstd; i++) { 2785 ohci_soft_td_t *std = ox->ox_stds[i]; 2786 if (std == NULL) 2787 break; 2788 ohci_free_std_locked(sc, std); 2789 } 2790 ohci_free_std_locked(sc, ox->ox_stat); 2791 mutex_exit(&sc->sc_lock); 2792 2793 if (ox->ox_nstd) { 2794 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 2795 kmem_free(ox->ox_stds, sz); 2796 } 2797 } 2798 2799 Static usbd_status 2800 ohci_device_ctrl_transfer(struct usbd_xfer *xfer) 2801 { 2802 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2803 usbd_status err; 2804 2805 /* Insert last in queue. */ 2806 mutex_enter(&sc->sc_lock); 2807 err = usb_insert_transfer(xfer); 2808 mutex_exit(&sc->sc_lock); 2809 if (err) 2810 return err; 2811 2812 /* Pipe isn't running, start first */ 2813 return ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2814 } 2815 2816 Static usbd_status 2817 ohci_device_ctrl_start(struct usbd_xfer *xfer) 2818 { 2819 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2820 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2821 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2822 usb_device_request_t *req = &xfer->ux_request; 2823 struct usbd_device *dev __diagused = opipe->pipe.up_dev; 2824 ohci_soft_td_t *setup, *stat, *next, *tail; 2825 ohci_soft_ed_t *sed; 2826 int isread; 2827 int len; 2828 2829 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2830 2831 if (sc->sc_dying) 2832 return USBD_IOERROR; 2833 2834 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2835 2836 isread = req->bmRequestType & UT_READ; 2837 len = UGETW(req->wLength); 2838 2839 DPRINTF("xfer=%p len=%d, addr=%d, endpt=%d", xfer, len, dev->ud_addr, 2840 opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress); 2841 DPRINTF("type=0x%02x, request=0x%02x, wValue=0x%04x, wIndex=0x%04x", 2842 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2843 UGETW(req->wIndex)); 2844 2845 /* Need to take lock here for pipe->tail.td */ 2846 mutex_enter(&sc->sc_lock); 2847 2848 setup = opipe->tail.td; 2849 stat = ox->ox_stat; 2850 tail = ox->ox_tdtail; 2851 opipe->tail.td = tail; 2852 2853 sed = opipe->sed; 2854 2855 KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->ud_addr, 2856 "address ED %d pipe %d\n", 2857 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->ud_addr); 2858 KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) == 2859 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 2860 "MPL ED %d pipe %d\n", 2861 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), 2862 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 2863 2864 /* next will point to data if len != 0 */ 2865 next = stat; 2866 2867 /* Set up data transaction */ 2868 if (len != 0) { 2869 ohci_soft_td_t *std; 2870 ohci_soft_td_t *end; 2871 2872 next = ox->ox_stds[0]; 2873 ohci_reset_std_chain(sc, xfer, len, isread, next, &end); 2874 2875 end->td.td_nexttd = HTOO32(stat->physaddr); 2876 end->nexttd = stat; 2877 2878 usb_syncmem(&end->dma, 2879 end->offs + offsetof(ohci_td_t, td_nexttd), 2880 sizeof(end->td.td_nexttd), 2881 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2882 2883 usb_syncmem(&xfer->ux_dmabuf, 0, len, 2884 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2885 std = ox->ox_stds[0]; 2886 /* Start toggle at 1 and then use the carried toggle. */ 2887 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 2888 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 2889 usb_syncmem(&std->dma, 2890 std->offs + offsetof(ohci_td_t, td_flags), 2891 sizeof(std->td.td_flags), 2892 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2893 } 2894 2895 DPRINTFN(8, "setup %p data %p stat %p tail %p", setup, 2896 (len != 0 ? ox->ox_stds[0] : NULL), stat, tail); 2897 KASSERT(opipe->tail.td == tail); 2898 2899 memcpy(KERNADDR(&opipe->ctrl.reqdma, 0), req, sizeof(*req)); 2900 usb_syncmem(&opipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2901 2902 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 2903 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 2904 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->ctrl.reqdma, 0)); 2905 setup->td.td_nexttd = HTOO32(next->physaddr); 2906 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof(*req) - 1); 2907 setup->nexttd = next; 2908 setup->len = 0; 2909 setup->xfer = xfer; 2910 setup->flags = 0; 2911 ohci_hash_add_td(sc, setup); 2912 2913 xfer->ux_hcpriv = setup; 2914 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2915 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2916 2917 stat->td.td_flags = HTOO32( 2918 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 2919 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 2920 stat->td.td_cbp = 0; 2921 stat->td.td_nexttd = HTOO32(tail->physaddr); 2922 stat->td.td_be = 0; 2923 stat->nexttd = tail; 2924 stat->flags = OHCI_CALL_DONE; 2925 stat->len = 0; 2926 stat->xfer = xfer; 2927 ohci_hash_add_td(sc, stat); 2928 2929 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2930 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2931 2932 memset(&tail->td, 0, sizeof(tail->td)); 2933 tail->nexttd = NULL; 2934 tail->xfer = NULL; 2935 2936 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 2937 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2938 2939 2940 #ifdef OHCI_DEBUG 2941 USBHIST_LOGN(ohcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2942 if (ohcidebug >= 5) { 2943 ohci_dump_ed(sc, sed); 2944 ohci_dump_tds(sc, setup); 2945 } 2946 USBHIST_LOGN(ohcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2947 #endif 2948 2949 /* Insert ED in schedule */ 2950 sed->ed.ed_tailp = HTOO32(tail->physaddr); 2951 usb_syncmem(&sed->dma, 2952 sed->offs + offsetof(ohci_ed_t, ed_tailp), 2953 sizeof(sed->ed.ed_tailp), 2954 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2955 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2956 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2957 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2958 ohci_timeout, xfer); 2959 } 2960 2961 #ifdef OHCI_DEBUG 2962 DPRINTFN(20, "--- dump start ---", 0, 0, 0, 0); 2963 if (ohcidebug >= 20) { 2964 delay(10000); 2965 DPRINTFN(20, "status=%x", OREAD4(sc, OHCI_COMMAND_STATUS), 2966 0, 0, 0); 2967 ohci_dumpregs(sc); 2968 DPRINTFN(20, "ctrl head:", 0, 0, 0, 0); 2969 ohci_dump_ed(sc, sc->sc_ctrl_head); 2970 DPRINTF("sed:", 0, 0, 0, 0); 2971 ohci_dump_ed(sc, sed); 2972 ohci_dump_tds(sc, setup); 2973 } 2974 DPRINTFN(20, "--- dump start ---", 0, 0, 0, 0); 2975 #endif 2976 2977 DPRINTF("done", 0, 0, 0, 0); 2978 2979 mutex_exit(&sc->sc_lock); 2980 2981 if (sc->sc_bus.ub_usepolling) 2982 ohci_waitintr(sc, xfer); 2983 2984 return USBD_IN_PROGRESS; 2985 } 2986 2987 /* Abort a device control request. */ 2988 Static void 2989 ohci_device_ctrl_abort(struct usbd_xfer *xfer) 2990 { 2991 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 2992 2993 KASSERT(mutex_owned(&sc->sc_lock)); 2994 2995 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2996 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2997 ohci_abort_xfer(xfer, USBD_CANCELLED); 2998 } 2999 3000 /* Close a device control pipe. */ 3001 Static void 3002 ohci_device_ctrl_close(struct usbd_pipe *pipe) 3003 { 3004 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3005 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3006 3007 KASSERT(mutex_owned(&sc->sc_lock)); 3008 3009 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3010 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3011 ohci_close_pipe(pipe, sc->sc_ctrl_head); 3012 ohci_free_std_locked(sc, opipe->tail.td); 3013 } 3014 3015 /************************/ 3016 3017 Static void 3018 ohci_device_clear_toggle(struct usbd_pipe *pipe) 3019 { 3020 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3021 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3022 3023 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 3024 } 3025 3026 Static void 3027 ohci_noop(struct usbd_pipe *pipe) 3028 { 3029 } 3030 3031 Static int 3032 ohci_device_bulk_init(struct usbd_xfer *xfer) 3033 { 3034 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3035 int len = xfer->ux_bufsize; 3036 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;; 3037 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3038 int err; 3039 3040 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3041 3042 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3043 3044 DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread, 3045 xfer->ux_flags); 3046 DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0); 3047 3048 /* Allocate a chain of new TDs (including a new tail). */ 3049 err = ohci_alloc_std_chain(sc, xfer, len, isread); 3050 if (err) 3051 return err; 3052 3053 return 0; 3054 } 3055 3056 Static void 3057 ohci_device_bulk_fini(struct usbd_xfer *xfer) 3058 { 3059 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3060 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3061 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3062 3063 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3064 DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0); 3065 3066 mutex_enter(&sc->sc_lock); 3067 for (size_t i = 0; i < ox->ox_nstd; i++) { 3068 ohci_soft_td_t *std = ox->ox_stds[i]; 3069 if (std == NULL) 3070 break; 3071 if (std != opipe->tail.td) 3072 ohci_free_std_locked(sc, std); 3073 } 3074 mutex_exit(&sc->sc_lock); 3075 3076 if (ox->ox_nstd) { 3077 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 3078 kmem_free(ox->ox_stds, sz); 3079 } 3080 } 3081 3082 Static usbd_status 3083 ohci_device_bulk_transfer(struct usbd_xfer *xfer) 3084 { 3085 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3086 usbd_status err; 3087 3088 /* Insert last in queue. */ 3089 mutex_enter(&sc->sc_lock); 3090 err = usb_insert_transfer(xfer); 3091 mutex_exit(&sc->sc_lock); 3092 if (err) 3093 return err; 3094 3095 /* Pipe isn't running, start first */ 3096 return ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3097 } 3098 3099 Static usbd_status 3100 ohci_device_bulk_start(struct usbd_xfer *xfer) 3101 { 3102 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3103 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3104 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3105 ohci_soft_td_t *last; 3106 ohci_soft_td_t *data, *tail, *tdp; 3107 ohci_soft_ed_t *sed; 3108 int len, isread, endpt; 3109 3110 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3111 3112 if (sc->sc_dying) 3113 return USBD_IOERROR; 3114 3115 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3116 3117 len = xfer->ux_length; 3118 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3119 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3120 sed = opipe->sed; 3121 3122 DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread, 3123 xfer->ux_flags); 3124 DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0); 3125 3126 mutex_enter(&sc->sc_lock); 3127 3128 /* Use "tail" TD and loan our first TD to next transfer */ 3129 data = opipe->tail.td; 3130 opipe->tail.td = ox->ox_stds[0]; 3131 ox->ox_stds[0] = data; 3132 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3133 3134 tail = opipe->tail.td; /* point at sentinel */ 3135 memset(&tail->td, 0, sizeof(tail->td)); 3136 tail->nexttd = NULL; 3137 tail->xfer = NULL; 3138 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3139 BUS_DMASYNC_PREWRITE); 3140 xfer->ux_hcpriv = data; 3141 3142 DPRINTFN(8, "xfer %p data %p tail %p", xfer, ox->ox_stds[0], tail, 0); 3143 KASSERT(opipe->tail.td == tail); 3144 3145 /* We want interrupt at the end of the transfer. */ 3146 last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3147 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3148 3149 last->td.td_nexttd = HTOO32(tail->physaddr); 3150 last->nexttd = tail; 3151 last->flags |= OHCI_CALL_DONE; 3152 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3153 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3154 3155 DPRINTFN(4, "ed_flags=0x%08x td_flags=0x%08x " 3156 "td_cbp=0x%08x td_be=0x%08x", 3157 (int)O32TOH(sed->ed.ed_flags), 3158 (int)O32TOH(data->td.td_flags), 3159 (int)O32TOH(data->td.td_cbp), 3160 (int)O32TOH(data->td.td_be)); 3161 3162 #ifdef OHCI_DEBUG 3163 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3164 if (ohcidebug >= 5) { 3165 ohci_dump_ed(sc, sed); 3166 ohci_dump_tds(sc, data); 3167 } 3168 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3169 #endif 3170 3171 /* Insert ED in schedule */ 3172 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3173 KASSERT(tdp->xfer == xfer); 3174 } 3175 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3176 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3177 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3178 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3179 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3180 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3181 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3182 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3183 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3184 ohci_timeout, xfer); 3185 } 3186 mutex_exit(&sc->sc_lock); 3187 3188 return USBD_IN_PROGRESS; 3189 } 3190 3191 Static void 3192 ohci_device_bulk_abort(struct usbd_xfer *xfer) 3193 { 3194 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3195 3196 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3197 3198 KASSERT(mutex_owned(&sc->sc_lock)); 3199 3200 DPRINTF("xfer=%p", xfer, 0, 0, 0); 3201 ohci_abort_xfer(xfer, USBD_CANCELLED); 3202 } 3203 3204 /* 3205 * Close a device bulk pipe. 3206 */ 3207 Static void 3208 ohci_device_bulk_close(struct usbd_pipe *pipe) 3209 { 3210 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3211 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3212 3213 KASSERT(mutex_owned(&sc->sc_lock)); 3214 3215 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3216 3217 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3218 ohci_close_pipe(pipe, sc->sc_bulk_head); 3219 ohci_free_std_locked(sc, opipe->tail.td); 3220 } 3221 3222 /************************/ 3223 3224 Static int 3225 ohci_device_intr_init(struct usbd_xfer *xfer) 3226 { 3227 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3228 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3229 int len = xfer->ux_bufsize; 3230 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;; 3231 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3232 int err; 3233 3234 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3235 3236 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3237 KASSERT(len != 0); 3238 3239 DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread, 3240 xfer->ux_flags); 3241 DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0); 3242 3243 ox->ox_nstd = 0; 3244 3245 err = ohci_alloc_std_chain(sc, xfer, len, isread); 3246 if (err) { 3247 return err; 3248 } 3249 3250 return 0; 3251 } 3252 3253 Static void 3254 ohci_device_intr_fini(struct usbd_xfer *xfer) 3255 { 3256 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3257 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3258 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3259 3260 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3261 DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0); 3262 3263 mutex_enter(&sc->sc_lock); 3264 for (size_t i = 0; i < ox->ox_nstd; i++) { 3265 ohci_soft_td_t *std = ox->ox_stds[i]; 3266 if (std != NULL) 3267 break; 3268 if (std != opipe->tail.td) 3269 ohci_free_std_locked(sc, std); 3270 } 3271 mutex_exit(&sc->sc_lock); 3272 3273 if (ox->ox_nstd) { 3274 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 3275 kmem_free(ox->ox_stds, sz); 3276 } 3277 } 3278 3279 Static usbd_status 3280 ohci_device_intr_transfer(struct usbd_xfer *xfer) 3281 { 3282 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3283 usbd_status err; 3284 3285 /* Insert last in queue. */ 3286 mutex_enter(&sc->sc_lock); 3287 err = usb_insert_transfer(xfer); 3288 mutex_exit(&sc->sc_lock); 3289 if (err) 3290 return err; 3291 3292 /* Pipe isn't running, start first */ 3293 return ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3294 } 3295 3296 Static usbd_status 3297 ohci_device_intr_start(struct usbd_xfer *xfer) 3298 { 3299 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3300 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3301 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3302 ohci_soft_ed_t *sed = opipe->sed; 3303 ohci_soft_td_t *data, *last, *tail; 3304 int len, isread, endpt; 3305 3306 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3307 3308 if (sc->sc_dying) 3309 return USBD_IOERROR; 3310 3311 DPRINTFN(3, "xfer=%p len=%d flags=%d priv=%p", xfer, xfer->ux_length, 3312 xfer->ux_flags, xfer->ux_priv); 3313 3314 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3315 3316 len = xfer->ux_length; 3317 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3318 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3319 3320 mutex_enter(&sc->sc_lock); 3321 3322 /* Use "tail" TD and loan our first TD to next transfer */ 3323 data = opipe->tail.td; 3324 opipe->tail.td = ox->ox_stds[0]; 3325 ox->ox_stds[0] = data; 3326 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3327 3328 tail = opipe->tail.td; /* point at sentinel */ 3329 memset(&tail->td, 0, sizeof(tail->td)); 3330 tail->nexttd = NULL; 3331 tail->xfer = NULL; 3332 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3333 BUS_DMASYNC_PREWRITE); 3334 xfer->ux_hcpriv = data; 3335 3336 DPRINTFN(8, "data %p tail %p", ox->ox_stds[0], tail, 0, 0); 3337 KASSERT(opipe->tail.td == tail); 3338 3339 /* We want interrupt at the end of the transfer. */ 3340 last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3341 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3342 3343 last->td.td_nexttd = HTOO32(tail->physaddr); 3344 last->nexttd = tail; 3345 last->flags |= OHCI_CALL_DONE; 3346 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3347 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3348 3349 #ifdef OHCI_DEBUG 3350 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3351 if (ohcidebug >= 5) { 3352 ohci_dump_ed(sc, sed); 3353 ohci_dump_tds(sc, data); 3354 } 3355 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3356 #endif 3357 3358 /* Insert ED in schedule */ 3359 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3360 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3361 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3362 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3363 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3364 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3365 3366 mutex_exit(&sc->sc_lock); 3367 3368 return USBD_IN_PROGRESS; 3369 } 3370 3371 /* Abort a device interrupt request. */ 3372 Static void 3373 ohci_device_intr_abort(struct usbd_xfer *xfer) 3374 { 3375 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3376 3377 KASSERT(mutex_owned(&sc->sc_lock)); 3378 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3379 3380 ohci_abort_xfer(xfer, USBD_CANCELLED); 3381 } 3382 3383 /* Close a device interrupt pipe. */ 3384 Static void 3385 ohci_device_intr_close(struct usbd_pipe *pipe) 3386 { 3387 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3388 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3389 int nslots = opipe->intr.nslots; 3390 int pos = opipe->intr.pos; 3391 int j; 3392 ohci_soft_ed_t *p, *sed = opipe->sed; 3393 3394 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3395 3396 KASSERT(mutex_owned(&sc->sc_lock)); 3397 3398 DPRINTFN(1, "pipe=%p nslots=%d pos=%d", pipe, nslots, pos, 0); 3399 usb_syncmem(&sed->dma, sed->offs, 3400 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3401 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3402 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3403 sizeof(sed->ed.ed_flags), 3404 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3405 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3406 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3407 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3408 3409 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3410 continue; 3411 KASSERT(p); 3412 p->next = sed->next; 3413 p->ed.ed_nexted = sed->ed.ed_nexted; 3414 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3415 sizeof(p->ed.ed_nexted), 3416 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3417 3418 for (j = 0; j < nslots; j++) 3419 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3420 3421 ohci_free_std_locked(sc, opipe->tail.td); 3422 ohci_free_sed_locked(sc, opipe->sed); 3423 } 3424 3425 Static usbd_status 3426 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3427 { 3428 int i, j, best; 3429 u_int npoll, slow, shigh, nslots; 3430 u_int bestbw, bw; 3431 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3432 3433 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3434 3435 DPRINTFN(2, "pipe=%p", opipe, 0, 0, 0); 3436 if (ival == 0) { 3437 printf("ohci_setintr: 0 interval\n"); 3438 return USBD_INVAL; 3439 } 3440 3441 npoll = OHCI_NO_INTRS; 3442 while (npoll > ival) 3443 npoll /= 2; 3444 DPRINTFN(2, "ival=%d npoll=%d", ival, npoll, 0, 0); 3445 3446 /* 3447 * We now know which level in the tree the ED must go into. 3448 * Figure out which slot has most bandwidth left over. 3449 * Slots to examine: 3450 * npoll 3451 * 1 0 3452 * 2 1 2 3453 * 4 3 4 5 6 3454 * 8 7 8 9 10 11 12 13 14 3455 * N (N-1) .. (N-1+N-1) 3456 */ 3457 slow = npoll-1; 3458 shigh = slow + npoll; 3459 nslots = OHCI_NO_INTRS / npoll; 3460 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3461 bw = 0; 3462 for (j = 0; j < nslots; j++) 3463 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3464 if (bw < bestbw) { 3465 best = i; 3466 bestbw = bw; 3467 } 3468 } 3469 DPRINTFN(2, "best=%d(%d..%d) bestbw=%d", best, slow, shigh, bestbw); 3470 3471 mutex_enter(&sc->sc_lock); 3472 hsed = sc->sc_eds[best]; 3473 sed->next = hsed->next; 3474 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3475 sizeof(hsed->ed.ed_flags), 3476 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3477 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3478 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3479 sizeof(sed->ed.ed_flags), 3480 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3481 hsed->next = sed; 3482 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3483 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3484 sizeof(hsed->ed.ed_flags), 3485 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3486 mutex_exit(&sc->sc_lock); 3487 3488 for (j = 0; j < nslots; j++) 3489 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3490 opipe->intr.nslots = nslots; 3491 opipe->intr.pos = best; 3492 3493 DPRINTFN(5, "returns %p", opipe, 0, 0, 0); 3494 return USBD_NORMAL_COMPLETION; 3495 } 3496 3497 /***********************/ 3498 3499 Static int 3500 ohci_device_isoc_init(struct usbd_xfer *xfer) 3501 { 3502 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3503 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3504 ohci_soft_itd_t *sitd; 3505 size_t i; 3506 int err; 3507 3508 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3509 3510 DPRINTFN(1, "xfer %p len %d flags %d", xfer, xfer->ux_length, 3511 xfer->ux_flags, 0); 3512 3513 const size_t nfsitd = 3514 (xfer->ux_nframes + OHCI_ITD_NOFFSET - 1) / OHCI_ITD_NOFFSET; 3515 const size_t nbsitd = xfer->ux_bufsize / OHCI_PAGE_SIZE; 3516 const size_t nsitd = MAX(nfsitd, nbsitd) + 1; 3517 3518 ox->ox_sitds = kmem_zalloc(sizeof(ohci_soft_itd_t *) * nsitd, 3519 KM_SLEEP); 3520 ox->ox_nsitd = nsitd; 3521 3522 for (i = 0; i < nsitd; i++) { 3523 /* Allocate next ITD */ 3524 sitd = ohci_alloc_sitd(sc); 3525 if (sitd == NULL) { 3526 err = ENOMEM; 3527 goto fail; 3528 } 3529 ox->ox_sitds[i] = sitd; 3530 sitd->xfer = xfer; 3531 sitd->flags = 0; 3532 } 3533 3534 return 0; 3535 fail: 3536 for (; i > 0;) { 3537 ohci_free_sitd(sc, ox->ox_sitds[--i]); 3538 } 3539 return err; 3540 } 3541 3542 Static void 3543 ohci_device_isoc_fini(struct usbd_xfer *xfer) 3544 { 3545 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3546 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3547 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3548 3549 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3550 3551 mutex_enter(&sc->sc_lock); 3552 for (size_t i = 0; i < ox->ox_nsitd; i++) { 3553 if (ox->ox_sitds[i] != opipe->tail.itd) { 3554 ohci_free_sitd_locked(sc, ox->ox_sitds[i]); 3555 } 3556 } 3557 mutex_exit(&sc->sc_lock); 3558 3559 if (ox->ox_nsitd) { 3560 const size_t sz = sizeof(ohci_soft_itd_t *) * ox->ox_nsitd; 3561 kmem_free(ox->ox_sitds, sz); 3562 } 3563 } 3564 3565 3566 usbd_status 3567 ohci_device_isoc_transfer(struct usbd_xfer *xfer) 3568 { 3569 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3570 usbd_status err; 3571 3572 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3573 3574 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 3575 3576 /* Put it on our queue, */ 3577 mutex_enter(&sc->sc_lock); 3578 err = usb_insert_transfer(xfer); 3579 mutex_exit(&sc->sc_lock); 3580 3581 /* bail out on error, */ 3582 if (err && err != USBD_IN_PROGRESS) 3583 return err; 3584 3585 /* XXX should check inuse here */ 3586 3587 /* insert into schedule, */ 3588 ohci_device_isoc_enter(xfer); 3589 3590 /* and start if the pipe wasn't running */ 3591 if (!err) 3592 ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3593 3594 return err; 3595 } 3596 3597 void 3598 ohci_device_isoc_enter(struct usbd_xfer *xfer) 3599 { 3600 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3601 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3602 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3603 ohci_soft_ed_t *sed = opipe->sed; 3604 ohci_soft_itd_t *sitd, *nsitd; 3605 ohci_physaddr_t buf, offs, noffs, bp0; 3606 int i, ncur, nframes; 3607 3608 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3609 3610 mutex_enter(&sc->sc_lock); 3611 3612 if (sc->sc_dying) { 3613 mutex_exit(&sc->sc_lock); 3614 return; 3615 } 3616 3617 struct isoc *isoc = &opipe->isoc; 3618 3619 DPRINTFN(1, "used=%d next=%d xfer=%p nframes=%d", 3620 isoc->inuse, isoc->next, xfer, xfer->ux_nframes); 3621 3622 if (isoc->next == -1) { 3623 /* Not in use yet, schedule it a few frames ahead. */ 3624 isoc->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3625 DPRINTFN(2,"start next=%d", isoc->next, 0, 0, 0); 3626 } 3627 3628 sitd = opipe->tail.itd; 3629 opipe->tail.itd = ox->ox_sitds[0]; 3630 ox->ox_sitds[0] = sitd; 3631 3632 buf = DMAADDR(&xfer->ux_dmabuf, 0); 3633 bp0 = OHCI_PAGE(buf); 3634 offs = OHCI_PAGE_OFFSET(buf); 3635 nframes = xfer->ux_nframes; 3636 xfer->ux_hcpriv = sitd; 3637 size_t j = 1; 3638 for (i = ncur = 0; i < nframes; i++, ncur++) { 3639 noffs = offs + xfer->ux_frlengths[i]; 3640 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3641 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3642 3643 /* Allocate next ITD */ 3644 nsitd = ox->ox_sitds[j++]; 3645 KASSERT(nsitd != NULL); 3646 KASSERT(j < ox->ox_nsitd); 3647 3648 /* Fill current ITD */ 3649 sitd->itd.itd_flags = HTOO32( 3650 OHCI_ITD_NOCC | 3651 OHCI_ITD_SET_SF(isoc->next) | 3652 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3653 OHCI_ITD_SET_FC(ncur)); 3654 sitd->itd.itd_bp0 = HTOO32(bp0); 3655 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3656 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3657 sitd->nextitd = nsitd; 3658 sitd->xfer = xfer; 3659 sitd->flags = 0; 3660 #ifdef DIAGNOSTIC 3661 sitd->isdone = false; 3662 #endif 3663 ohci_hash_add_itd(sc, sitd); 3664 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3665 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3666 3667 sitd = nsitd; 3668 isoc->next = isoc->next + ncur; 3669 bp0 = OHCI_PAGE(buf + offs); 3670 ncur = 0; 3671 } 3672 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3673 offs = noffs; 3674 } 3675 nsitd = ox->ox_sitds[j++]; 3676 KASSERT(nsitd != NULL); 3677 KASSERT(j <= ox->ox_nsitd); 3678 3679 memset(&nsitd->itd, 0, sizeof(nsitd->itd)); 3680 nsitd->nextitd = NULL; 3681 nsitd->xfer = NULL; 3682 /* Fixup last used ITD */ 3683 sitd->itd.itd_flags = HTOO32( 3684 OHCI_ITD_NOCC | 3685 OHCI_ITD_SET_SF(isoc->next) | 3686 OHCI_ITD_SET_DI(0) | 3687 OHCI_ITD_SET_FC(ncur)); 3688 sitd->itd.itd_bp0 = HTOO32(bp0); 3689 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3690 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3691 sitd->nextitd = nsitd; 3692 sitd->xfer = xfer; 3693 sitd->flags = OHCI_CALL_DONE; 3694 #ifdef DIAGNOSTIC 3695 sitd->isdone = false; 3696 #endif 3697 ohci_hash_add_itd(sc, sitd); 3698 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3699 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3700 3701 isoc->next = isoc->next + ncur; 3702 isoc->inuse += nframes; 3703 3704 xfer->ux_actlen = offs; /* XXX pretend we did it all */ 3705 3706 xfer->ux_status = USBD_IN_PROGRESS; 3707 3708 #ifdef OHCI_DEBUG 3709 if (ohcidebug >= 5) { 3710 DPRINTF("frame=%d", O32TOH(sc->sc_hcca->hcca_frame_number), 3711 0, 0, 0); 3712 ohci_dump_itds(sc, xfer->ux_hcpriv); 3713 ohci_dump_ed(sc, sed); 3714 } 3715 #endif 3716 3717 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3718 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3719 sed->ed.ed_tailp = HTOO32(nsitd->physaddr); 3720 opipe->tail.itd = nsitd; 3721 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3722 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3723 sizeof(sed->ed.ed_flags), 3724 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3725 mutex_exit(&sc->sc_lock); 3726 3727 #ifdef OHCI_DEBUG 3728 if (ohcidebug >= 5) { 3729 delay(150000); 3730 DPRINTF("after frame=%d", O32TOH(sc->sc_hcca->hcca_frame_number), 3731 0, 0, 0); 3732 ohci_dump_itds(sc, xfer->ux_hcpriv); 3733 ohci_dump_ed(sc, sed); 3734 } 3735 #endif 3736 } 3737 3738 usbd_status 3739 ohci_device_isoc_start(struct usbd_xfer *xfer) 3740 { 3741 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3742 3743 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3744 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 3745 3746 mutex_enter(&sc->sc_lock); 3747 3748 if (sc->sc_dying) { 3749 mutex_exit(&sc->sc_lock); 3750 return USBD_IOERROR; 3751 } 3752 3753 3754 #ifdef DIAGNOSTIC 3755 if (xfer->ux_status != USBD_IN_PROGRESS) 3756 printf("ohci_device_isoc_start: not in progress %p\n", xfer); 3757 #endif 3758 3759 /* XXX anything to do? */ 3760 3761 mutex_exit(&sc->sc_lock); 3762 3763 return USBD_IN_PROGRESS; 3764 } 3765 3766 void 3767 ohci_device_isoc_abort(struct usbd_xfer *xfer) 3768 { 3769 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3770 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3771 ohci_soft_ed_t *sed; 3772 ohci_soft_itd_t *sitd; 3773 3774 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3775 DPRINTFN(1, "xfer=%p", xfer, 0, 0, 0); 3776 3777 KASSERT(mutex_owned(&sc->sc_lock)); 3778 3779 /* Transfer is already done. */ 3780 if (xfer->ux_status != USBD_NOT_STARTED && 3781 xfer->ux_status != USBD_IN_PROGRESS) { 3782 printf("ohci_device_isoc_abort: early return\n"); 3783 goto done; 3784 } 3785 3786 /* Give xfer the requested abort code. */ 3787 xfer->ux_status = USBD_CANCELLED; 3788 3789 sed = opipe->sed; 3790 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3791 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3792 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3793 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3794 sizeof(sed->ed.ed_flags), 3795 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3796 3797 sitd = xfer->ux_hcpriv; 3798 KASSERT(sitd); 3799 3800 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3801 #ifdef DIAGNOSTIC 3802 DPRINTFN(1, "abort sets done sitd=%p", sitd, 0, 0, 0); 3803 sitd->isdone = true; 3804 #endif 3805 } 3806 3807 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3808 3809 /* Run callback. */ 3810 usb_transfer_complete(xfer); 3811 3812 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3813 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3814 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3815 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3816 3817 done: 3818 KASSERT(mutex_owned(&sc->sc_lock)); 3819 } 3820 3821 void 3822 ohci_device_isoc_done(struct usbd_xfer *xfer) 3823 { 3824 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3825 DPRINTFN(1, "xfer=%p", xfer, 0, 0, 0); 3826 } 3827 3828 usbd_status 3829 ohci_setup_isoc(struct usbd_pipe *pipe) 3830 { 3831 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3832 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3833 struct isoc *isoc = &opipe->isoc; 3834 3835 isoc->next = -1; 3836 isoc->inuse = 0; 3837 3838 mutex_enter(&sc->sc_lock); 3839 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3840 mutex_exit(&sc->sc_lock); 3841 3842 return USBD_NORMAL_COMPLETION; 3843 } 3844 3845 void 3846 ohci_device_isoc_close(struct usbd_pipe *pipe) 3847 { 3848 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3849 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3850 3851 KASSERT(mutex_owned(&sc->sc_lock)); 3852 3853 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3854 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3855 ohci_close_pipe(pipe, sc->sc_isoc_head); 3856 #ifdef DIAGNOSTIC 3857 opipe->tail.itd->isdone = true; 3858 #endif 3859 ohci_free_sitd_locked(sc, opipe->tail.itd); 3860 } 3861
Indexes created Fri Oct 03 02:09:57 GMT 2025