ohci.c revision 1.254.2.49
1 /* $NetBSD: ohci.c,v 1.254.2.49 2016/02/25 12:52:09 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * USB Open Host Controller driver. 38 * 39 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 40 * USB spec: http://www.usb.org/developers/docs/ 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.254.2.49 2016/02/25 12:52:09 skrll Exp $"); 45 46 #include "opt_usb.h" 47 48 #include <sys/param.h> 49 50 #include <sys/cpu.h> 51 #include <sys/device.h> 52 #include <sys/kernel.h> 53 #include <sys/kmem.h> 54 #include <sys/proc.h> 55 #include <sys/queue.h> 56 #include <sys/select.h> 57 #include <sys/sysctl.h> 58 #include <sys/systm.h> 59 60 #include <machine/endian.h> 61 62 #include <dev/usb/usb.h> 63 #include <dev/usb/usbdi.h> 64 #include <dev/usb/usbdivar.h> 65 #include <dev/usb/usb_mem.h> 66 #include <dev/usb/usb_quirks.h> 67 68 #include <dev/usb/ohcireg.h> 69 #include <dev/usb/ohcivar.h> 70 #include <dev/usb/usbroothub.h> 71 #include <dev/usb/usbhist.h> 72 73 #ifdef USB_DEBUG 74 #ifndef OHCI_DEBUG 75 #define ohcidebug 0 76 #else 77 static int ohcidebug = 0; 78 79 SYSCTL_SETUP(sysctl_hw_ohci_setup, "sysctl hw.ohci setup") 80 { 81 int err; 82 const struct sysctlnode *rnode; 83 const struct sysctlnode *cnode; 84 85 err = sysctl_createv(clog, 0, NULL, &rnode, 86 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ohci", 87 SYSCTL_DESCR("ohci global controls"), 88 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 89 90 if (err) 91 goto fail; 92 93 /* control debugging printfs */ 94 err = sysctl_createv(clog, 0, &rnode, &cnode, 95 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 96 "debug", SYSCTL_DESCR("Enable debugging output"), 97 NULL, 0, &ohcidebug, sizeof(ohcidebug), CTL_CREATE, CTL_EOL); 98 if (err) 99 goto fail; 100 101 return; 102 fail: 103 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 104 } 105 106 #endif /* OHCI_DEBUG */ 107 #endif /* USB_DEBUG */ 108 109 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ohcidebug,FMT,A,B,C,D) 110 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ohcidebug,N,FMT,A,B,C,D) 111 #define OHCIHIST_FUNC() USBHIST_FUNC() 112 #define OHCIHIST_CALLED(name) USBHIST_CALLED(ohcidebug) 113 114 #if BYTE_ORDER == BIG_ENDIAN 115 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 116 #else 117 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 118 #endif 119 120 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 121 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 122 #define HTOO16(val) O16TOH(val) 123 #define HTOO32(val) O32TOH(val) 124 125 struct ohci_pipe; 126 127 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 128 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 129 130 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 131 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 132 Static void ohci_free_std_locked(ohci_softc_t *, ohci_soft_td_t *); 133 134 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 135 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 136 Static void ohci_free_sitd_locked(ohci_softc_t *, 137 ohci_soft_itd_t *); 138 139 Static usbd_status ohci_alloc_std_chain(ohci_softc_t *, struct usbd_xfer *, 140 int, int); 141 Static void ohci_free_stds(ohci_softc_t *, struct ohci_xfer *); 142 143 Static void ohci_reset_std_chain(ohci_softc_t *, struct usbd_xfer *, 144 int, int, ohci_soft_td_t *, ohci_soft_td_t **); 145 146 Static usbd_status ohci_open(struct usbd_pipe *); 147 Static void ohci_poll(struct usbd_bus *); 148 Static void ohci_softintr(void *); 149 Static void ohci_waitintr(ohci_softc_t *, struct usbd_xfer *); 150 Static void ohci_rhsc(ohci_softc_t *, struct usbd_xfer *); 151 Static void ohci_rhsc_softint(void *); 152 153 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 154 ohci_soft_ed_t *); 155 156 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 157 ohci_soft_ed_t *); 158 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 159 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 160 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 161 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 162 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 163 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 164 165 Static usbd_status ohci_setup_isoc(struct usbd_pipe *); 166 Static void ohci_device_isoc_enter(struct usbd_xfer *); 167 168 Static struct usbd_xfer * 169 ohci_allocx(struct usbd_bus *, unsigned int); 170 Static void ohci_freex(struct usbd_bus *, struct usbd_xfer *); 171 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 172 Static int ohci_roothub_ctrl(struct usbd_bus *, 173 usb_device_request_t *, void *, int); 174 175 Static usbd_status ohci_root_intr_transfer(struct usbd_xfer *); 176 Static usbd_status ohci_root_intr_start(struct usbd_xfer *); 177 Static void ohci_root_intr_abort(struct usbd_xfer *); 178 Static void ohci_root_intr_close(struct usbd_pipe *); 179 Static void ohci_root_intr_done(struct usbd_xfer *); 180 181 Static int ohci_device_ctrl_init(struct usbd_xfer *); 182 Static void ohci_device_ctrl_fini(struct usbd_xfer *); 183 Static usbd_status ohci_device_ctrl_transfer(struct usbd_xfer *); 184 Static usbd_status ohci_device_ctrl_start(struct usbd_xfer *); 185 Static void ohci_device_ctrl_abort(struct usbd_xfer *); 186 Static void ohci_device_ctrl_close(struct usbd_pipe *); 187 Static void ohci_device_ctrl_done(struct usbd_xfer *); 188 189 Static int ohci_device_bulk_init(struct usbd_xfer *); 190 Static void ohci_device_bulk_fini(struct usbd_xfer *); 191 Static usbd_status ohci_device_bulk_transfer(struct usbd_xfer *); 192 Static usbd_status ohci_device_bulk_start(struct usbd_xfer *); 193 Static void ohci_device_bulk_abort(struct usbd_xfer *); 194 Static void ohci_device_bulk_close(struct usbd_pipe *); 195 Static void ohci_device_bulk_done(struct usbd_xfer *); 196 197 Static int ohci_device_intr_init(struct usbd_xfer *); 198 Static void ohci_device_intr_fini(struct usbd_xfer *); 199 Static usbd_status ohci_device_intr_transfer(struct usbd_xfer *); 200 Static usbd_status ohci_device_intr_start(struct usbd_xfer *); 201 Static void ohci_device_intr_abort(struct usbd_xfer *); 202 Static void ohci_device_intr_close(struct usbd_pipe *); 203 Static void ohci_device_intr_done(struct usbd_xfer *); 204 205 Static int ohci_device_isoc_init(struct usbd_xfer *); 206 Static void ohci_device_isoc_fini(struct usbd_xfer *); 207 Static usbd_status ohci_device_isoc_transfer(struct usbd_xfer *); 208 Static usbd_status ohci_device_isoc_start(struct usbd_xfer *); 209 Static void ohci_device_isoc_abort(struct usbd_xfer *); 210 Static void ohci_device_isoc_close(struct usbd_pipe *); 211 Static void ohci_device_isoc_done(struct usbd_xfer *); 212 213 Static usbd_status ohci_device_setintr(ohci_softc_t *, 214 struct ohci_pipe *, int); 215 216 Static void ohci_timeout(void *); 217 Static void ohci_timeout_task(void *); 218 Static void ohci_rhsc_enable(void *); 219 220 Static void ohci_close_pipe(struct usbd_pipe *, ohci_soft_ed_t *); 221 Static void ohci_abort_xfer(struct usbd_xfer *, usbd_status); 222 223 Static void ohci_device_clear_toggle(struct usbd_pipe *); 224 Static void ohci_noop(struct usbd_pipe *); 225 226 #ifdef OHCI_DEBUG 227 Static void ohci_dumpregs(ohci_softc_t *); 228 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 229 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 230 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 231 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 232 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 233 #endif 234 235 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 236 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 237 #define OWRITE1(sc, r, x) \ 238 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 239 #define OWRITE2(sc, r, x) \ 240 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 241 #define OWRITE4(sc, r, x) \ 242 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 243 244 static __inline uint32_t 245 OREAD4(ohci_softc_t *sc, bus_size_t r) 246 { 247 248 OBARR(sc); 249 return bus_space_read_4(sc->iot, sc->ioh, r); 250 } 251 252 /* Reverse the bits in a value 0 .. 31 */ 253 Static uint8_t revbits[OHCI_NO_INTRS] = 254 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 255 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 256 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 257 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 258 259 struct ohci_pipe { 260 struct usbd_pipe pipe; 261 ohci_soft_ed_t *sed; 262 union { 263 ohci_soft_td_t *td; 264 ohci_soft_itd_t *itd; 265 } tail; 266 /* Info needed for different pipe kinds. */ 267 union { 268 /* Control pipe */ 269 struct { 270 usb_dma_t reqdma; 271 } ctrl; 272 /* Interrupt pipe */ 273 struct { 274 int nslots; 275 int pos; 276 } intr; 277 /* Isochronous pipe */ 278 struct isoc { 279 int next, inuse; 280 } isoc; 281 }; 282 }; 283 284 Static const struct usbd_bus_methods ohci_bus_methods = { 285 .ubm_open = ohci_open, 286 .ubm_softint = ohci_softintr, 287 .ubm_dopoll = ohci_poll, 288 .ubm_allocx = ohci_allocx, 289 .ubm_freex = ohci_freex, 290 .ubm_getlock = ohci_get_lock, 291 .ubm_rhctrl = ohci_roothub_ctrl, 292 }; 293 294 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 295 .upm_transfer = ohci_root_intr_transfer, 296 .upm_start = ohci_root_intr_start, 297 .upm_abort = ohci_root_intr_abort, 298 .upm_close = ohci_root_intr_close, 299 .upm_cleartoggle = ohci_noop, 300 .upm_done = ohci_root_intr_done, 301 }; 302 303 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 304 .upm_init = ohci_device_ctrl_init, 305 .upm_fini = ohci_device_ctrl_fini, 306 .upm_transfer = ohci_device_ctrl_transfer, 307 .upm_start = ohci_device_ctrl_start, 308 .upm_abort = ohci_device_ctrl_abort, 309 .upm_close = ohci_device_ctrl_close, 310 .upm_cleartoggle = ohci_noop, 311 .upm_done = ohci_device_ctrl_done, 312 }; 313 314 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 315 .upm_init = ohci_device_intr_init, 316 .upm_fini = ohci_device_intr_fini, 317 .upm_transfer = ohci_device_intr_transfer, 318 .upm_start = ohci_device_intr_start, 319 .upm_abort = ohci_device_intr_abort, 320 .upm_close = ohci_device_intr_close, 321 .upm_cleartoggle = ohci_device_clear_toggle, 322 .upm_done = ohci_device_intr_done, 323 }; 324 325 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 326 .upm_init = ohci_device_bulk_init, 327 .upm_fini = ohci_device_bulk_fini, 328 .upm_transfer = ohci_device_bulk_transfer, 329 .upm_start = ohci_device_bulk_start, 330 .upm_abort = ohci_device_bulk_abort, 331 .upm_close = ohci_device_bulk_close, 332 .upm_cleartoggle = ohci_device_clear_toggle, 333 .upm_done = ohci_device_bulk_done, 334 }; 335 336 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 337 .upm_init = ohci_device_isoc_init, 338 .upm_fini = ohci_device_isoc_fini, 339 .upm_transfer = ohci_device_isoc_transfer, 340 .upm_start = ohci_device_isoc_start, 341 .upm_abort = ohci_device_isoc_abort, 342 .upm_close = ohci_device_isoc_close, 343 .upm_cleartoggle = ohci_noop, 344 .upm_done = ohci_device_isoc_done, 345 }; 346 347 int 348 ohci_activate(device_t self, enum devact act) 349 { 350 struct ohci_softc *sc = device_private(self); 351 352 switch (act) { 353 case DVACT_DEACTIVATE: 354 sc->sc_dying = 1; 355 return 0; 356 default: 357 return EOPNOTSUPP; 358 } 359 } 360 361 void 362 ohci_childdet(device_t self, device_t child) 363 { 364 struct ohci_softc *sc = device_private(self); 365 366 KASSERT(sc->sc_child == child); 367 sc->sc_child = NULL; 368 } 369 370 int 371 ohci_detach(struct ohci_softc *sc, int flags) 372 { 373 int rv = 0; 374 375 if (sc->sc_child != NULL) 376 rv = config_detach(sc->sc_child, flags); 377 378 if (rv != 0) 379 return rv; 380 381 callout_halt(&sc->sc_tmo_rhsc, &sc->sc_lock); 382 383 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 384 callout_destroy(&sc->sc_tmo_rhsc); 385 386 softint_disestablish(sc->sc_rhsc_si); 387 388 cv_destroy(&sc->sc_softwake_cv); 389 390 mutex_destroy(&sc->sc_lock); 391 mutex_destroy(&sc->sc_intr_lock); 392 393 if (sc->sc_hcca != NULL) 394 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 395 pool_cache_destroy(sc->sc_xferpool); 396 397 return rv; 398 } 399 400 ohci_soft_ed_t * 401 ohci_alloc_sed(ohci_softc_t *sc) 402 { 403 ohci_soft_ed_t *sed; 404 usbd_status err; 405 int i, offs; 406 usb_dma_t dma; 407 408 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 409 410 mutex_enter(&sc->sc_lock); 411 if (sc->sc_freeeds == NULL) { 412 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 413 mutex_exit(&sc->sc_lock); 414 415 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 416 OHCI_ED_ALIGN, &dma); 417 if (err) 418 return 0; 419 420 mutex_enter(&sc->sc_lock); 421 for (i = 0; i < OHCI_SED_CHUNK; i++) { 422 offs = i * OHCI_SED_SIZE; 423 sed = KERNADDR(&dma, offs); 424 sed->physaddr = DMAADDR(&dma, offs); 425 sed->dma = dma; 426 sed->offs = offs; 427 sed->next = sc->sc_freeeds; 428 sc->sc_freeeds = sed; 429 } 430 } 431 sed = sc->sc_freeeds; 432 sc->sc_freeeds = sed->next; 433 mutex_exit(&sc->sc_lock); 434 435 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 436 sed->next = 0; 437 return sed; 438 } 439 440 static inline void 441 ohci_free_sed_locked(ohci_softc_t *sc, ohci_soft_ed_t *sed) 442 { 443 444 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 445 446 sed->next = sc->sc_freeeds; 447 sc->sc_freeeds = sed; 448 } 449 450 void 451 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 452 { 453 454 mutex_enter(&sc->sc_lock); 455 ohci_free_sed_locked(sc, sed); 456 mutex_exit(&sc->sc_lock); 457 } 458 459 ohci_soft_td_t * 460 ohci_alloc_std(ohci_softc_t *sc) 461 { 462 ohci_soft_td_t *std; 463 usbd_status err; 464 int i, offs; 465 usb_dma_t dma; 466 467 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 468 469 mutex_enter(&sc->sc_lock); 470 if (sc->sc_freetds == NULL) { 471 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 472 mutex_exit(&sc->sc_lock); 473 474 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 475 OHCI_TD_ALIGN, &dma); 476 if (err) 477 return NULL; 478 479 mutex_enter(&sc->sc_lock); 480 for(i = 0; i < OHCI_STD_CHUNK; i++) { 481 offs = i * OHCI_STD_SIZE; 482 std = KERNADDR(&dma, offs); 483 std->physaddr = DMAADDR(&dma, offs); 484 std->dma = dma; 485 std->offs = offs; 486 std->nexttd = sc->sc_freetds; 487 sc->sc_freetds = std; 488 } 489 } 490 491 std = sc->sc_freetds; 492 sc->sc_freetds = std->nexttd; 493 mutex_exit(&sc->sc_lock); 494 495 memset(&std->td, 0, sizeof(ohci_td_t)); 496 std->nexttd = NULL; 497 std->xfer = NULL; 498 499 return std; 500 } 501 502 void 503 ohci_free_std_locked(ohci_softc_t *sc, ohci_soft_td_t *std) 504 { 505 506 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 507 508 std->nexttd = sc->sc_freetds; 509 sc->sc_freetds = std; 510 } 511 512 void 513 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 514 { 515 516 mutex_enter(&sc->sc_lock); 517 ohci_free_std_locked(sc, std); 518 mutex_exit(&sc->sc_lock); 519 } 520 521 Static usbd_status 522 ohci_alloc_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, int alen, int rd) 523 { 524 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 525 struct usbd_pipe *pipe = xfer->ux_pipe; 526 ohci_soft_td_t *next, *cur; 527 ohci_physaddr_t dataphys, dataphysend; 528 uint32_t tdflags; 529 int len = alen; 530 int curlen; 531 usb_dma_t *dma = &xfer->ux_dmabuf; 532 uint16_t flags = xfer->ux_flags; 533 534 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 535 536 DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d", 537 pipe->up_dev->ud_addr, 538 UE_GET_ADDR(pipe->up_endpoint->ue_edesc->bEndpointAddress), 539 alen, pipe->up_dev->ud_speed); 540 541 ASSERT_SLEEPABLE(); 542 543 size_t nstd = (flags & USBD_FORCE_SHORT_XFER) ? 1 : 0; 544 nstd += ((len + OHCI_PAGE_SIZE - 1) / OHCI_PAGE_SIZE); 545 ox->ox_stds = kmem_zalloc(sizeof(ohci_soft_td_t *) * nstd, 546 KM_SLEEP); 547 ox->ox_nstd = nstd; 548 int mps = UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize); 549 550 DPRINTFN(8, "xfer %p nstd %d mps %d", xfer, nstd, mps, 0); 551 552 len = alen; 553 cur = ohci_alloc_std(sc); 554 if (cur == NULL) 555 goto nomem; 556 557 dataphys = DMAADDR(dma, 0); 558 dataphysend = OHCI_PAGE(dataphys + len - 1); 559 tdflags = HTOO32( 560 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 561 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 562 563 for (size_t j = 0;;) { 564 ox->ox_stds[j++] = cur; 565 next = ohci_alloc_std(sc); 566 if (next == NULL) 567 goto nomem; 568 569 /* The OHCI hardware can handle at most one page crossing. */ 570 if (OHCI_PAGE(dataphys) == dataphysend || 571 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 572 /* we can handle it in this TD */ 573 curlen = len; 574 } else { 575 /* must use multiple TDs, fill as much as possible. */ 576 curlen = 2 * OHCI_PAGE_SIZE - 577 (dataphys & (OHCI_PAGE_SIZE-1)); 578 /* the length must be a multiple of the max size */ 579 curlen -= curlen % mps; 580 KASSERT(curlen != 0); 581 } 582 DPRINTFN(4, "dataphys=0x%08x dataphysend=0x%08x " 583 "len=%d curlen=%d", dataphys, dataphysend, len, curlen); 584 len -= curlen; 585 586 cur->td.td_flags = tdflags; 587 cur->td.td_cbp = HTOO32(dataphys); 588 cur->td.td_nexttd = HTOO32(next->physaddr); 589 cur->td.td_be = HTOO32(dataphys + curlen - 1); 590 cur->nexttd = next; 591 cur->len = curlen; 592 cur->flags = OHCI_ADD_LEN; 593 cur->xfer = xfer; 594 595 DPRINTFN(10, "cbp=0x%08x be=0x%08x", dataphys, 596 dataphys + curlen - 1, 0, 0); 597 if (len == 0) 598 break; 599 DPRINTFN(10, "extend chain", 0, 0, 0, 0); 600 dataphys += curlen; 601 cur = next; 602 } 603 if (!rd && (flags & USBD_FORCE_SHORT_XFER) && 604 alen % mps == 0) { 605 /* Force a 0 length transfer at the end. */ 606 607 cur = next; 608 next = ohci_alloc_std(sc); 609 if (next == NULL) 610 goto nomem; 611 612 cur->td.td_flags = tdflags; 613 cur->td.td_cbp = 0; /* indicate 0 length packet */ 614 cur->td.td_nexttd = HTOO32(next->physaddr); 615 cur->td.td_be = ~0; 616 cur->nexttd = next; 617 cur->len = 0; 618 cur->flags = 0; 619 cur->xfer = xfer; 620 621 DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0); 622 } 623 624 return USBD_NORMAL_COMPLETION; 625 626 nomem: 627 ohci_free_stds(sc, ox); 628 629 return USBD_NOMEM; 630 } 631 632 Static void 633 ohci_free_stds(ohci_softc_t *sc, struct ohci_xfer *ox) 634 { 635 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 636 DPRINTF("ox=%p", ox, 0, 0, 0); 637 638 mutex_enter(&sc->sc_lock); 639 for (size_t i = 0; i < ox->ox_nstd; i++) { 640 ohci_soft_td_t *std = ox->ox_stds[i]; 641 if (std == NULL) 642 break; 643 ohci_free_std_locked(sc, std); 644 } 645 mutex_exit(&sc->sc_lock); 646 } 647 648 void 649 ohci_reset_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, 650 int alen, int rd, ohci_soft_td_t *sp, ohci_soft_td_t **ep) 651 { 652 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 653 ohci_soft_td_t *next, *cur; 654 ohci_physaddr_t dataphys, dataphysend; 655 uint32_t tdflags; 656 int len, curlen; 657 usb_dma_t *dma = &xfer->ux_dmabuf; 658 uint16_t flags = xfer->ux_flags; 659 660 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 661 DPRINTF("start len=%d", alen, 0, 0, 0); 662 663 KASSERT(mutex_owned(&sc->sc_lock)); 664 665 DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d", 666 xfer->ux_pipe->up_dev->ud_addr, 667 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 668 alen, xfer->ux_pipe->up_dev->ud_speed); 669 670 KASSERT(sp); 671 672 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 673 674 len = alen; 675 cur = sp; 676 677 dataphys = DMAADDR(dma, 0); 678 dataphysend = OHCI_PAGE(dataphys + len - 1); 679 usb_syncmem(dma, 0, len, 680 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 681 tdflags = HTOO32( 682 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 683 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 684 685 for (size_t j = 1;;) { 686 if (j == ox->ox_nstd) 687 next = NULL; 688 else 689 next = ox->ox_stds[j++]; 690 KASSERT(next != cur); 691 692 /* The OHCI hardware can handle at most one page crossing. */ 693 if (OHCI_PAGE(dataphys) == dataphysend || 694 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 695 /* we can handle it in this TD */ 696 curlen = len; 697 } else { 698 /* must use multiple TDs, fill as much as possible. */ 699 curlen = 2 * OHCI_PAGE_SIZE - 700 (dataphys & (OHCI_PAGE_SIZE - 1)); 701 /* the length must be a multiple of the max size */ 702 curlen -= curlen % mps; 703 KASSERT(curlen != 0); 704 } 705 DPRINTFN(4, "dataphys=0x%08x dataphysend=0x%08x " 706 "len=%d curlen=%d", dataphys, dataphysend, len, curlen); 707 len -= curlen; 708 709 cur->td.td_flags = tdflags; 710 cur->td.td_cbp = HTOO32(dataphys); 711 cur->td.td_be = HTOO32(dataphys + curlen - 1); 712 cur->td.td_nexttd = (next != NULL) ? HTOO32(next->physaddr) : 0; 713 cur->nexttd = next; 714 cur->len = curlen; 715 cur->flags = OHCI_ADD_LEN; 716 cur->xfer = xfer; 717 ohci_hash_add_td(sc, cur); 718 719 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 720 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 721 DPRINTFN(10, "cbp=0x%08x be=0x%08x", dataphys, 722 dataphys + curlen - 1, 0, 0); 723 if (len == 0) 724 break; 725 KASSERT(next != NULL); 726 DPRINTFN(10, "extend chain", 0, 0, 0, 0); 727 dataphys += curlen; 728 cur = next; 729 } 730 cur->td.td_flags |= 731 (xfer->ux_flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0); 732 733 if (!rd && 734 (flags & USBD_FORCE_SHORT_XFER) && 735 alen % mps == 0) { 736 /* Force a 0 length transfer at the end. */ 737 738 KASSERT(next != NULL); 739 cur = next; 740 741 cur->td.td_flags = tdflags; 742 cur->td.td_cbp = 0; /* indicate 0 length packet */ 743 cur->td.td_nexttd = HTOO32(next->physaddr); 744 cur->td.td_be = ~0; 745 cur->nexttd = NULL; 746 cur->len = 0; 747 cur->flags = 0; 748 cur->xfer = xfer; 749 ohci_hash_add_td(sc, cur); 750 751 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 752 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 753 DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0); 754 } 755 *ep = cur; 756 } 757 758 ohci_soft_itd_t * 759 ohci_alloc_sitd(ohci_softc_t *sc) 760 { 761 ohci_soft_itd_t *sitd; 762 usbd_status err; 763 int i, offs; 764 usb_dma_t dma; 765 766 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 767 768 mutex_enter(&sc->sc_lock); 769 if (sc->sc_freeitds == NULL) { 770 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 771 mutex_exit(&sc->sc_lock); 772 773 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 774 OHCI_ITD_ALIGN, &dma); 775 if (err) 776 return NULL; 777 mutex_enter(&sc->sc_lock); 778 for(i = 0; i < OHCI_SITD_CHUNK; i++) { 779 offs = i * OHCI_SITD_SIZE; 780 sitd = KERNADDR(&dma, offs); 781 sitd->physaddr = DMAADDR(&dma, offs); 782 sitd->dma = dma; 783 sitd->offs = offs; 784 sitd->nextitd = sc->sc_freeitds; 785 sc->sc_freeitds = sitd; 786 } 787 } 788 789 sitd = sc->sc_freeitds; 790 sc->sc_freeitds = sitd->nextitd; 791 mutex_exit(&sc->sc_lock); 792 793 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 794 sitd->nextitd = NULL; 795 sitd->xfer = NULL; 796 797 #ifdef DIAGNOSTIC 798 sitd->isdone = false; 799 #endif 800 801 return sitd; 802 } 803 804 Static void 805 ohci_free_sitd_locked(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 806 { 807 808 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 809 DPRINTFN(10, "sitd=%p", sitd, 0, 0, 0); 810 811 KASSERT(sitd->isdone); 812 #ifdef DIAGNOSTIC 813 /* Warn double free */ 814 sitd->isdone = false; 815 #endif 816 817 sitd->nextitd = sc->sc_freeitds; 818 sc->sc_freeitds = sitd; 819 } 820 821 void 822 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 823 { 824 825 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 826 827 mutex_enter(&sc->sc_lock); 828 ohci_free_sitd_locked(sc, sitd); 829 mutex_exit(&sc->sc_lock); 830 } 831 832 int 833 ohci_init(ohci_softc_t *sc) 834 { 835 ohci_soft_ed_t *sed, *psed; 836 usbd_status err; 837 int i; 838 uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */; 839 840 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 841 842 aprint_normal_dev(sc->sc_dev, ""); 843 844 sc->sc_hcca = NULL; 845 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 846 847 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 848 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 849 cv_init(&sc->sc_softwake_cv, "ohciab"); 850 851 sc->sc_rhsc_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 852 ohci_rhsc_softint, sc); 853 854 for (i = 0; i < OHCI_HASH_SIZE; i++) 855 LIST_INIT(&sc->sc_hash_tds[i]); 856 for (i = 0; i < OHCI_HASH_SIZE; i++) 857 LIST_INIT(&sc->sc_hash_itds[i]); 858 859 sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0, 860 "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL); 861 862 rev = OREAD4(sc, OHCI_REVISION); 863 aprint_normal("OHCI version %d.%d%s\n", 864 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 865 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 866 867 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 868 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 869 sc->sc_bus.ub_revision = USBREV_UNKNOWN; 870 return -1; 871 } 872 sc->sc_bus.ub_revision = USBREV_1_0; 873 sc->sc_bus.ub_usedma = true; 874 875 /* XXX determine alignment by R/W */ 876 /* Allocate the HCCA area. */ 877 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 878 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 879 if (err) { 880 sc->sc_hcca = NULL; 881 return err; 882 } 883 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 884 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 885 886 sc->sc_eintrs = OHCI_NORMAL_INTRS; 887 888 /* Allocate dummy ED that starts the control list. */ 889 sc->sc_ctrl_head = ohci_alloc_sed(sc); 890 if (sc->sc_ctrl_head == NULL) { 891 err = ENOMEM; 892 goto bad1; 893 } 894 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 895 896 /* Allocate dummy ED that starts the bulk list. */ 897 sc->sc_bulk_head = ohci_alloc_sed(sc); 898 if (sc->sc_bulk_head == NULL) { 899 err = ENOMEM; 900 goto bad2; 901 } 902 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 903 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 904 sizeof(sc->sc_bulk_head->ed), 905 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 906 907 /* Allocate dummy ED that starts the isochronous list. */ 908 sc->sc_isoc_head = ohci_alloc_sed(sc); 909 if (sc->sc_isoc_head == NULL) { 910 err = ENOMEM; 911 goto bad3; 912 } 913 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 914 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 915 sizeof(sc->sc_isoc_head->ed), 916 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 917 918 /* Allocate all the dummy EDs that make up the interrupt tree. */ 919 for (i = 0; i < OHCI_NO_EDS; i++) { 920 sed = ohci_alloc_sed(sc); 921 if (sed == NULL) { 922 while (--i >= 0) 923 ohci_free_sed(sc, sc->sc_eds[i]); 924 err = ENOMEM; 925 goto bad4; 926 } 927 /* All ED fields are set to 0. */ 928 sc->sc_eds[i] = sed; 929 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 930 if (i != 0) 931 psed = sc->sc_eds[(i-1) / 2]; 932 else 933 psed= sc->sc_isoc_head; 934 sed->next = psed; 935 sed->ed.ed_nexted = HTOO32(psed->physaddr); 936 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 937 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 938 } 939 /* 940 * Fill HCCA interrupt table. The bit reversal is to get 941 * the tree set up properly to spread the interrupts. 942 */ 943 for (i = 0; i < OHCI_NO_INTRS; i++) 944 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 945 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 946 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 947 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 948 949 #ifdef OHCI_DEBUG 950 DPRINTFN(15, "--- dump start ---", 0, 0, 0 ,0); 951 if (ohcidebug >= 15) { 952 for (i = 0; i < OHCI_NO_EDS; i++) { 953 DPRINTFN(15, "ed#%d ", i, 0, 0, 0); 954 ohci_dump_ed(sc, sc->sc_eds[i]); 955 } 956 DPRINTFN(15, "iso", 0, 0, 0 ,0); 957 ohci_dump_ed(sc, sc->sc_isoc_head); 958 } 959 DPRINTFN(15, "--- dump end ---", 0, 0, 0 ,0); 960 #endif 961 962 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 963 ctl = OREAD4(sc, OHCI_CONTROL); 964 rwc = ctl & OHCI_RWC; 965 fm = OREAD4(sc, OHCI_FM_INTERVAL); 966 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 967 /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */ 968 969 /* Determine in what context we are running. */ 970 if (ctl & OHCI_IR) { 971 /* SMM active, request change */ 972 DPRINTF("SMM active, request owner change", 0, 0, 0, 0); 973 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 974 (OHCI_OC | OHCI_MIE)) 975 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 976 s = OREAD4(sc, OHCI_COMMAND_STATUS); 977 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 978 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 979 usb_delay_ms(&sc->sc_bus, 1); 980 ctl = OREAD4(sc, OHCI_CONTROL); 981 } 982 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 983 if ((ctl & OHCI_IR) == 0) { 984 aprint_error_dev(sc->sc_dev, 985 "SMM does not respond, resetting\n"); 986 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 987 goto reset; 988 } 989 #if 0 990 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 991 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 992 /* BIOS started controller. */ 993 DPRINTF("BIOS active", 0, 0, 0, 0); 994 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 995 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 996 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 997 } 998 #endif 999 } else { 1000 DPRINTF("cold started", 0 ,0 ,0 ,0); 1001 reset: 1002 /* Controller was cold started. */ 1003 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 1004 } 1005 1006 /* 1007 * This reset should not be necessary according to the OHCI spec, but 1008 * without it some controllers do not start. 1009 */ 1010 DPRINTF("sc %p: resetting", sc, 0, 0, 0); 1011 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 1012 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 1013 1014 /* We now own the host controller and the bus has been reset. */ 1015 1016 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 1017 /* Nominal time for a reset is 10 us. */ 1018 for (i = 0; i < 10; i++) { 1019 delay(10); 1020 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 1021 if (!hcr) 1022 break; 1023 } 1024 if (hcr) { 1025 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 1026 err = EIO; 1027 goto bad5; 1028 } 1029 #ifdef OHCI_DEBUG 1030 if (ohcidebug >= 15) 1031 ohci_dumpregs(sc); 1032 #endif 1033 1034 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 1035 1036 /* Set up HC registers. */ 1037 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1038 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 1039 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 1040 /* disable all interrupts and then switch on all desired interrupts */ 1041 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 1042 /* switch on desired functional features */ 1043 ctl = OREAD4(sc, OHCI_CONTROL); 1044 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 1045 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 1046 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 1047 /* And finally start it! */ 1048 OWRITE4(sc, OHCI_CONTROL, ctl); 1049 1050 /* 1051 * The controller is now OPERATIONAL. Set a some final 1052 * registers that should be set earlier, but that the 1053 * controller ignores when in the SUSPEND state. 1054 */ 1055 ival = OHCI_GET_IVAL(fm); 1056 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 1057 fm |= OHCI_FSMPS(ival) | ival; 1058 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 1059 per = OHCI_PERIODIC(ival); /* 90% periodic */ 1060 OWRITE4(sc, OHCI_PERIODIC_START, per); 1061 1062 if (sc->sc_flags & OHCIF_SUPERIO) { 1063 /* no overcurrent protection */ 1064 desca |= OHCI_NOCP; 1065 /* 1066 * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning 1067 * that 1068 * - ports are always power switched 1069 * - don't wait for powered root hub port 1070 */ 1071 desca &= ~(__SHIFTIN(0xff, OHCI_POTPGT_MASK) | OHCI_NPS); 1072 } 1073 1074 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 1075 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 1076 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 1077 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 1078 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 1079 1080 /* 1081 * The AMD756 requires a delay before re-reading the register, 1082 * otherwise it will occasionally report 0 ports. 1083 */ 1084 sc->sc_noport = 0; 1085 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 1086 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 1087 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 1088 } 1089 1090 #ifdef OHCI_DEBUG 1091 if (ohcidebug >= 5) 1092 ohci_dumpregs(sc); 1093 #endif 1094 1095 /* Set up the bus struct. */ 1096 sc->sc_bus.ub_methods = &ohci_bus_methods; 1097 sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe); 1098 1099 sc->sc_control = sc->sc_intre = 0; 1100 1101 /* Finally, turn on interrupts. */ 1102 DPRINTF("enabling %#x", sc->sc_eintrs | OHCI_MIE, 0, 0, 0); 1103 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 1104 1105 return 0; 1106 1107 bad5: 1108 for (i = 0; i < OHCI_NO_EDS; i++) 1109 ohci_free_sed(sc, sc->sc_eds[i]); 1110 bad4: 1111 ohci_free_sed(sc, sc->sc_isoc_head); 1112 bad3: 1113 ohci_free_sed(sc, sc->sc_bulk_head); 1114 bad2: 1115 ohci_free_sed(sc, sc->sc_ctrl_head); 1116 bad1: 1117 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 1118 sc->sc_hcca = NULL; 1119 return err; 1120 } 1121 1122 struct usbd_xfer * 1123 ohci_allocx(struct usbd_bus *bus, unsigned int nframes) 1124 { 1125 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1126 struct usbd_xfer *xfer; 1127 1128 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1129 if (xfer != NULL) { 1130 memset(xfer, 0, sizeof(struct ohci_xfer)); 1131 #ifdef DIAGNOSTIC 1132 xfer->ux_state = XFER_BUSY; 1133 #endif 1134 } 1135 return xfer; 1136 } 1137 1138 void 1139 ohci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1140 { 1141 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1142 1143 KASSERTMSG(xfer->ux_state == XFER_BUSY, 1144 "xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state); 1145 #ifdef DIAGNOSTIC 1146 xfer->ux_state = XFER_FREE; 1147 #endif 1148 pool_cache_put(sc->sc_xferpool, xfer); 1149 } 1150 1151 Static void 1152 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1153 { 1154 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1155 1156 *lock = &sc->sc_lock; 1157 } 1158 1159 /* 1160 * Shut down the controller when the system is going down. 1161 */ 1162 bool 1163 ohci_shutdown(device_t self, int flags) 1164 { 1165 ohci_softc_t *sc = device_private(self); 1166 1167 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1168 1169 DPRINTF("stopping the HC", 0, 0, 0, 0); 1170 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1171 return true; 1172 } 1173 1174 bool 1175 ohci_resume(device_t dv, const pmf_qual_t *qual) 1176 { 1177 ohci_softc_t *sc = device_private(dv); 1178 uint32_t ctl; 1179 1180 mutex_spin_enter(&sc->sc_intr_lock); 1181 sc->sc_bus.ub_usepolling++; 1182 mutex_spin_exit(&sc->sc_intr_lock); 1183 1184 /* Some broken BIOSes do not recover these values */ 1185 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1186 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1187 sc->sc_ctrl_head->physaddr); 1188 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1189 sc->sc_bulk_head->physaddr); 1190 if (sc->sc_intre) 1191 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1192 (OHCI_ALL_INTRS | OHCI_MIE)); 1193 if (sc->sc_control) 1194 ctl = sc->sc_control; 1195 else 1196 ctl = OREAD4(sc, OHCI_CONTROL); 1197 ctl |= OHCI_HCFS_RESUME; 1198 OWRITE4(sc, OHCI_CONTROL, ctl); 1199 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1200 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1201 OWRITE4(sc, OHCI_CONTROL, ctl); 1202 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1203 sc->sc_control = sc->sc_intre = 0; 1204 1205 mutex_spin_enter(&sc->sc_intr_lock); 1206 sc->sc_bus.ub_usepolling--; 1207 mutex_spin_exit(&sc->sc_intr_lock); 1208 1209 return true; 1210 } 1211 1212 bool 1213 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1214 { 1215 ohci_softc_t *sc = device_private(dv); 1216 uint32_t ctl; 1217 1218 mutex_spin_enter(&sc->sc_intr_lock); 1219 sc->sc_bus.ub_usepolling++; 1220 mutex_spin_exit(&sc->sc_intr_lock); 1221 1222 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1223 if (sc->sc_control == 0) { 1224 /* 1225 * Preserve register values, in case that BIOS 1226 * does not recover them. 1227 */ 1228 sc->sc_control = ctl; 1229 sc->sc_intre = OREAD4(sc, 1230 OHCI_INTERRUPT_ENABLE); 1231 } 1232 ctl |= OHCI_HCFS_SUSPEND; 1233 OWRITE4(sc, OHCI_CONTROL, ctl); 1234 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1235 1236 mutex_spin_enter(&sc->sc_intr_lock); 1237 sc->sc_bus.ub_usepolling--; 1238 mutex_spin_exit(&sc->sc_intr_lock); 1239 1240 return true; 1241 } 1242 1243 #ifdef OHCI_DEBUG 1244 void 1245 ohci_dumpregs(ohci_softc_t *sc) 1246 { 1247 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1248 1249 DPRINTF("rev=0x%08x control=0x%08x command=0x%08x", 1250 OREAD4(sc, OHCI_REVISION), 1251 OREAD4(sc, OHCI_CONTROL), 1252 OREAD4(sc, OHCI_COMMAND_STATUS), 0); 1253 DPRINTF(" intrstat=0x%08x intre=0x%08x intrd=0x%08x", 1254 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1255 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1256 OREAD4(sc, OHCI_INTERRUPT_DISABLE), 0); 1257 DPRINTF(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x", 1258 OREAD4(sc, OHCI_HCCA), 1259 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1260 OREAD4(sc, OHCI_CONTROL_HEAD_ED), 0); 1261 DPRINTF(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x", 1262 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1263 OREAD4(sc, OHCI_BULK_HEAD_ED), 1264 OREAD4(sc, OHCI_BULK_CURRENT_ED) ,0); 1265 DPRINTF(" done=0x%08x fmival=0x%08x fmrem=0x%08x", 1266 OREAD4(sc, OHCI_DONE_HEAD), 1267 OREAD4(sc, OHCI_FM_INTERVAL), 1268 OREAD4(sc, OHCI_FM_REMAINING), 0); 1269 DPRINTF(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x", 1270 OREAD4(sc, OHCI_FM_NUMBER), 1271 OREAD4(sc, OHCI_PERIODIC_START), 1272 OREAD4(sc, OHCI_LS_THRESHOLD), 0); 1273 DPRINTF(" desca=0x%08x descb=0x%08x stat=0x%08x", 1274 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1275 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1276 OREAD4(sc, OHCI_RH_STATUS), 0); 1277 DPRINTF(" port1=0x%08x port2=0x%08x", 1278 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1279 OREAD4(sc, OHCI_RH_PORT_STATUS(2)), 0, 0); 1280 DPRINTF(" HCCA: frame_number=0x%04x done_head=0x%08x", 1281 O32TOH(sc->sc_hcca->hcca_frame_number), 1282 O32TOH(sc->sc_hcca->hcca_done_head), 0, 0); 1283 } 1284 #endif 1285 1286 Static int ohci_intr1(ohci_softc_t *); 1287 1288 int 1289 ohci_intr(void *p) 1290 { 1291 ohci_softc_t *sc = p; 1292 int ret = 0; 1293 1294 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1295 1296 if (sc == NULL) 1297 return 0; 1298 1299 mutex_spin_enter(&sc->sc_intr_lock); 1300 1301 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1302 goto done; 1303 1304 /* If we get an interrupt while polling, then just ignore it. */ 1305 if (sc->sc_bus.ub_usepolling) { 1306 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1307 /* for level triggered intrs, should do something to ack */ 1308 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1309 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1310 1311 goto done; 1312 } 1313 1314 ret = ohci_intr1(sc); 1315 1316 done: 1317 mutex_spin_exit(&sc->sc_intr_lock); 1318 return ret; 1319 } 1320 1321 Static int 1322 ohci_intr1(ohci_softc_t *sc) 1323 { 1324 uint32_t intrs, eintrs; 1325 1326 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1327 1328 /* In case the interrupt occurs before initialization has completed. */ 1329 if (sc == NULL || sc->sc_hcca == NULL) { 1330 #ifdef DIAGNOSTIC 1331 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1332 #endif 1333 return 0; 1334 } 1335 1336 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1337 1338 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1339 if (!intrs) 1340 return 0; 1341 1342 /* Acknowledge */ 1343 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); 1344 eintrs = intrs & sc->sc_eintrs; 1345 DPRINTFN(7, "sc=%p", sc, 0, 0, 0); 1346 DPRINTFN(7, "intrs=%#x(%#x) eintrs=%#x(%#x)", 1347 intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), eintrs, 1348 sc->sc_eintrs); 1349 1350 if (!eintrs) { 1351 return 0; 1352 } 1353 1354 if (eintrs & OHCI_SO) { 1355 sc->sc_overrun_cnt++; 1356 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1357 printf("%s: %u scheduling overruns\n", 1358 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1359 sc->sc_overrun_cnt = 0; 1360 } 1361 /* XXX do what */ 1362 eintrs &= ~OHCI_SO; 1363 } 1364 if (eintrs & OHCI_WDH) { 1365 /* 1366 * We block the interrupt below, and reenable it later from 1367 * ohci_softintr(). 1368 */ 1369 usb_schedsoftintr(&sc->sc_bus); 1370 } 1371 if (eintrs & OHCI_RD) { 1372 DPRINTFN(5, "resume detect", sc, 0, 0, 0); 1373 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1374 /* XXX process resume detect */ 1375 } 1376 if (eintrs & OHCI_UE) { 1377 DPRINTFN(5, "unrecoverable error", sc, 0, 0, 0); 1378 printf("%s: unrecoverable error, controller halted\n", 1379 device_xname(sc->sc_dev)); 1380 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1381 /* XXX what else */ 1382 } 1383 if (eintrs & OHCI_RHSC) { 1384 /* 1385 * We block the interrupt below, and reenable it later from 1386 * a timeout. 1387 */ 1388 softint_schedule(sc->sc_rhsc_si); 1389 } 1390 1391 if (eintrs != 0) { 1392 /* Block unprocessed interrupts. */ 1393 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1394 sc->sc_eintrs &= ~eintrs; 1395 DPRINTF("sc %p blocking intrs 0x%x", sc, eintrs, 0, 0); 1396 } 1397 1398 return 1; 1399 } 1400 1401 void 1402 ohci_rhsc_enable(void *v_sc) 1403 { 1404 ohci_softc_t *sc = v_sc; 1405 1406 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1407 DPRINTF("sc %p", sc, 0, 0, 0); 1408 mutex_spin_enter(&sc->sc_intr_lock); 1409 sc->sc_eintrs |= OHCI_RHSC; 1410 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1411 mutex_spin_exit(&sc->sc_intr_lock); 1412 } 1413 1414 #ifdef OHCI_DEBUG 1415 const char *ohci_cc_strs[] = { 1416 "NO_ERROR", 1417 "CRC", 1418 "BIT_STUFFING", 1419 "DATA_TOGGLE_MISMATCH", 1420 "STALL", 1421 "DEVICE_NOT_RESPONDING", 1422 "PID_CHECK_FAILURE", 1423 "UNEXPECTED_PID", 1424 "DATA_OVERRUN", 1425 "DATA_UNDERRUN", 1426 "BUFFER_OVERRUN", 1427 "BUFFER_UNDERRUN", 1428 "reserved", 1429 "reserved", 1430 "NOT_ACCESSED", 1431 "NOT_ACCESSED", 1432 }; 1433 #endif 1434 1435 void 1436 ohci_softintr(void *v) 1437 { 1438 struct usbd_bus *bus = v; 1439 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1440 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1441 ohci_soft_td_t *std, *sdone, *stdnext; 1442 struct usbd_xfer *xfer; 1443 struct ohci_pipe *opipe; 1444 int len, cc; 1445 int i, j, actlen, iframes, uedir; 1446 ohci_physaddr_t done; 1447 1448 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1449 1450 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1451 1452 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1453 sizeof(sc->sc_hcca->hcca_done_head), 1454 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1455 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1456 sc->sc_hcca->hcca_done_head = 0; 1457 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1458 sizeof(sc->sc_hcca->hcca_done_head), 1459 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1460 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1461 sc->sc_eintrs |= OHCI_WDH; 1462 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1463 1464 /* Reverse the done list. */ 1465 for (sdone = NULL, sidone = NULL; done != 0; ) { 1466 std = ohci_hash_find_td(sc, done); 1467 if (std != NULL) { 1468 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1469 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1470 std->dnext = sdone; 1471 done = O32TOH(std->td.td_nexttd); 1472 sdone = std; 1473 DPRINTFN(10, "add TD %p", std, 0, 0, 0); 1474 continue; 1475 } 1476 sitd = ohci_hash_find_itd(sc, done); 1477 if (sitd != NULL) { 1478 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1479 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1480 sitd->dnext = sidone; 1481 done = O32TOH(sitd->itd.itd_nextitd); 1482 sidone = sitd; 1483 DPRINTFN(5, "add ITD %p", sitd, 0, 0, 0); 1484 continue; 1485 } 1486 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1487 (u_long)done); 1488 break; 1489 } 1490 1491 DPRINTFN(10, "sdone=%p sidone=%p", sdone, sidone, 0, 0); 1492 DPRINTFN(10, "--- TD dump start ---", 0, 0, 0, 0); 1493 #ifdef OHCI_DEBUG 1494 if (ohcidebug >= 10) { 1495 for (std = sdone; std; std = std->dnext) 1496 ohci_dump_td(sc, std); 1497 } 1498 #endif 1499 DPRINTFN(10, "--- TD dump end ---", 0, 0, 0, 0); 1500 1501 for (std = sdone; std; std = stdnext) { 1502 xfer = std->xfer; 1503 stdnext = std->dnext; 1504 DPRINTFN(10, "std=%p xfer=%p hcpriv=%p", std, xfer, 1505 xfer ? xfer->ux_hcpriv : 0, 0); 1506 if (xfer == NULL) { 1507 /* 1508 * xfer == NULL: There seems to be no xfer associated 1509 * with this TD. It is tailp that happened to end up on 1510 * the done queue. 1511 * Shouldn't happen, but some chips are broken(?). 1512 */ 1513 continue; 1514 } 1515 if (xfer->ux_status == USBD_CANCELLED || 1516 xfer->ux_status == USBD_TIMEOUT) { 1517 DPRINTF("cancel/timeout %p", xfer, 0, 0, 0); 1518 /* Handled by abort routine. */ 1519 continue; 1520 } 1521 callout_stop(&xfer->ux_callout); 1522 1523 len = std->len; 1524 if (std->td.td_cbp != 0) 1525 len -= O32TOH(std->td.td_be) - 1526 O32TOH(std->td.td_cbp) + 1; 1527 DPRINTFN(10, "len=%d, flags=0x%x", len, std->flags, 0, 0); 1528 if (std->flags & OHCI_ADD_LEN) 1529 xfer->ux_actlen += len; 1530 1531 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1532 if (cc == OHCI_CC_NO_ERROR) { 1533 ohci_hash_rem_td(sc, std); 1534 if (std->flags & OHCI_CALL_DONE) { 1535 xfer->ux_status = USBD_NORMAL_COMPLETION; 1536 usb_transfer_complete(xfer); 1537 } 1538 } else { 1539 /* 1540 * Endpoint is halted. First unlink all the TDs 1541 * belonging to the failed transfer, and then restart 1542 * the endpoint. 1543 */ 1544 ohci_soft_td_t *p, *n; 1545 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1546 1547 DPRINTFN(10, "error cc=%d", cc, 0, 0, 0); 1548 1549 /* remove xfer's TDs from the hash */ 1550 for (p = std; p->xfer == xfer; p = n) { 1551 n = p->nexttd; 1552 ohci_hash_rem_td(sc, p); 1553 } 1554 1555 ohci_soft_ed_t *sed = opipe->sed; 1556 1557 /* clear halt and TD chain */ 1558 sed->ed.ed_headp = HTOO32(p->physaddr); 1559 usb_syncmem(&sed->dma, 1560 sed->offs + offsetof(ohci_ed_t, ed_headp), 1561 sizeof(sed->ed.ed_headp), 1562 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1563 1564 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1565 1566 if (cc == OHCI_CC_DATA_UNDERRUN) 1567 xfer->ux_status = USBD_NORMAL_COMPLETION; 1568 else if (cc == OHCI_CC_STALL) 1569 xfer->ux_status = USBD_STALLED; 1570 else 1571 xfer->ux_status = USBD_IOERROR; 1572 usb_transfer_complete(xfer); 1573 } 1574 } 1575 DPRINTFN(10, "--- ITD dump start ---", 0, 0, 0, 0); 1576 #ifdef OHCI_DEBUG 1577 if (ohcidebug >= 10) { 1578 for (sitd = sidone; sitd; sitd = sitd->dnext) 1579 ohci_dump_itd(sc, sitd); 1580 } 1581 #endif 1582 DPRINTFN(10, "--- ITD dump end ---", 0, 0, 0, 0); 1583 1584 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1585 xfer = sitd->xfer; 1586 sitdnext = sitd->dnext; 1587 DPRINTFN(1, "sitd=%p xfer=%p hcpriv=%p", sitd, xfer, 1588 xfer ? xfer->ux_hcpriv : 0, 0); 1589 if (xfer == NULL) 1590 continue; 1591 if (xfer->ux_status == USBD_CANCELLED || 1592 xfer->ux_status == USBD_TIMEOUT) { 1593 DPRINTF("cancel/timeout %p", xfer, 0, 0, 0); 1594 /* Handled by abort routine. */ 1595 continue; 1596 } 1597 KASSERT(!sitd->isdone); 1598 #ifdef DIAGNOSTIC 1599 sitd->isdone = true; 1600 #endif 1601 if (sitd->flags & OHCI_CALL_DONE) { 1602 ohci_soft_itd_t *next; 1603 1604 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1605 opipe->isoc.inuse -= xfer->ux_nframes; 1606 uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc-> 1607 bEndpointAddress); 1608 xfer->ux_status = USBD_NORMAL_COMPLETION; 1609 actlen = 0; 1610 for (i = 0, sitd = xfer->ux_hcpriv;; 1611 sitd = next) { 1612 next = sitd->nextitd; 1613 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1614 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1615 xfer->ux_status = USBD_IOERROR; 1616 /* For input, update frlengths with actual */ 1617 /* XXX anything necessary for output? */ 1618 if (uedir == UE_DIR_IN && 1619 xfer->ux_status == USBD_NORMAL_COMPLETION) { 1620 iframes = OHCI_ITD_GET_FC(O32TOH( 1621 sitd->itd.itd_flags)); 1622 for (j = 0; j < iframes; i++, j++) { 1623 len = O16TOH(sitd-> 1624 itd.itd_offset[j]); 1625 if ((OHCI_ITD_PSW_GET_CC(len) & 1626 OHCI_CC_NOT_ACCESSED_MASK) 1627 == OHCI_CC_NOT_ACCESSED) 1628 len = 0; 1629 else 1630 len = OHCI_ITD_PSW_LENGTH(len); 1631 xfer->ux_frlengths[i] = len; 1632 actlen += len; 1633 } 1634 } 1635 if (sitd->flags & OHCI_CALL_DONE) 1636 break; 1637 ohci_hash_rem_itd(sc, sitd); 1638 1639 } 1640 ohci_hash_rem_itd(sc, sitd); 1641 if (uedir == UE_DIR_IN && 1642 xfer->ux_status == USBD_NORMAL_COMPLETION) 1643 xfer->ux_actlen = actlen; 1644 xfer->ux_hcpriv = NULL; 1645 1646 usb_transfer_complete(xfer); 1647 } 1648 } 1649 1650 if (sc->sc_softwake) { 1651 sc->sc_softwake = 0; 1652 cv_broadcast(&sc->sc_softwake_cv); 1653 } 1654 1655 DPRINTFN(10, "done", 0, 0, 0, 0); 1656 } 1657 1658 void 1659 ohci_device_ctrl_done(struct usbd_xfer *xfer) 1660 { 1661 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1662 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1663 int len = UGETW(xfer->ux_request.wLength); 1664 int isread = (xfer->ux_request.bmRequestType & UT_READ); 1665 1666 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1667 DPRINTFN(10, "xfer=%p", xfer, 0, 0, 0); 1668 1669 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1670 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 1671 1672 if (len) 1673 usb_syncmem(&xfer->ux_dmabuf, 0, len, 1674 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1675 usb_syncmem(&opipe->ctrl.reqdma, 0, 1676 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1677 } 1678 1679 void 1680 ohci_device_intr_done(struct usbd_xfer *xfer) 1681 { 1682 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 1683 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1684 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1685 ohci_soft_ed_t *sed = opipe->sed; 1686 int isread = 1687 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1688 1689 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1690 DPRINTFN(10, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0); 1691 1692 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1693 1694 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1695 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1696 if (xfer->ux_pipe->up_repeat) { 1697 ohci_soft_td_t *data, *last, *tail; 1698 int len = xfer->ux_length; 1699 1700 /* 1701 * Use the pipe "tail" TD as our first and loan our first TD 1702 * to the next transfer. 1703 */ 1704 data = opipe->tail.td; 1705 opipe->tail.td = ox->ox_stds[0]; 1706 ox->ox_stds[0] = data; 1707 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 1708 1709 tail = opipe->tail.td; /* point at sentinel */ 1710 memset(&tail->td, 0, sizeof(tail->td)); 1711 tail->nexttd = NULL; 1712 tail->xfer = NULL; 1713 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 1714 BUS_DMASYNC_PREWRITE); 1715 1716 /* We want interrupt at the end of the transfer. */ 1717 last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 1718 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 1719 1720 last->td.td_nexttd = HTOO32(tail->physaddr); 1721 last->nexttd = tail; 1722 last->flags |= OHCI_CALL_DONE; 1723 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 1724 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1725 1726 xfer->ux_hcpriv = data; 1727 xfer->ux_actlen = 0; 1728 1729 /* Insert ED in schedule */ 1730 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1731 usb_syncmem(&sed->dma, 1732 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1733 sizeof(sed->ed.ed_tailp), 1734 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1735 } 1736 } 1737 1738 void 1739 ohci_device_bulk_done(struct usbd_xfer *xfer) 1740 { 1741 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1742 1743 int isread = 1744 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1745 1746 KASSERT(mutex_owned(&sc->sc_lock)); 1747 1748 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1749 DPRINTFN(10, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0); 1750 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1751 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1752 } 1753 1754 Static void 1755 ohci_rhsc_softint(void *arg) 1756 { 1757 ohci_softc_t *sc = arg; 1758 1759 mutex_enter(&sc->sc_lock); 1760 1761 ohci_rhsc(sc, sc->sc_intrxfer); 1762 1763 /* Do not allow RHSC interrupts > 1 per second */ 1764 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1765 1766 mutex_exit(&sc->sc_lock); 1767 } 1768 1769 void 1770 ohci_rhsc(ohci_softc_t *sc, struct usbd_xfer *xfer) 1771 { 1772 u_char *p; 1773 int i, m; 1774 int hstatus __unused; 1775 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1776 1777 KASSERT(mutex_owned(&sc->sc_lock)); 1778 1779 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1780 DPRINTF("sc=%p xfer=%p hstatus=0x%08x", sc, xfer, hstatus, 0); 1781 1782 if (xfer == NULL) { 1783 /* Just ignore the change. */ 1784 return; 1785 } 1786 1787 p = xfer->ux_buf; 1788 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 1789 memset(p, 0, xfer->ux_length); 1790 for (i = 1; i <= m; i++) { 1791 /* Pick out CHANGE bits from the status reg. */ 1792 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1793 p[i/8] |= 1 << (i%8); 1794 } 1795 DPRINTF("change=0x%02x", *p, 0, 0, 0); 1796 xfer->ux_actlen = xfer->ux_length; 1797 xfer->ux_status = USBD_NORMAL_COMPLETION; 1798 1799 usb_transfer_complete(xfer); 1800 } 1801 1802 void 1803 ohci_root_intr_done(struct usbd_xfer *xfer) 1804 { 1805 } 1806 1807 /* 1808 * Wait here until controller claims to have an interrupt. 1809 * Then call ohci_intr and return. Use timeout to avoid waiting 1810 * too long. 1811 */ 1812 void 1813 ohci_waitintr(ohci_softc_t *sc, struct usbd_xfer *xfer) 1814 { 1815 int timo; 1816 uint32_t intrs; 1817 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1818 1819 mutex_enter(&sc->sc_lock); 1820 1821 xfer->ux_status = USBD_IN_PROGRESS; 1822 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1823 usb_delay_ms(&sc->sc_bus, 1); 1824 if (sc->sc_dying) 1825 break; 1826 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 1827 DPRINTFN(15, "intrs 0x%04x", intrs, 0, 0, 0); 1828 #ifdef OHCI_DEBUG 1829 if (ohcidebug > 15) 1830 ohci_dumpregs(sc); 1831 #endif 1832 if (intrs) { 1833 mutex_spin_enter(&sc->sc_intr_lock); 1834 ohci_intr1(sc); 1835 mutex_spin_exit(&sc->sc_intr_lock); 1836 if (xfer->ux_status != USBD_IN_PROGRESS) 1837 goto done; 1838 } 1839 } 1840 1841 /* Timeout */ 1842 DPRINTF("timeout", 0, 0, 0, 0); 1843 xfer->ux_status = USBD_TIMEOUT; 1844 usb_transfer_complete(xfer); 1845 1846 done: 1847 mutex_exit(&sc->sc_lock); 1848 } 1849 1850 void 1851 ohci_poll(struct usbd_bus *bus) 1852 { 1853 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1854 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1855 1856 #ifdef OHCI_DEBUG 1857 static int last; 1858 int new; 1859 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1860 if (new != last) { 1861 DPRINTFN(10, "intrs=0x%04x", new, 0, 0, 0); 1862 last = new; 1863 } 1864 #endif 1865 sc->sc_eintrs |= OHCI_WDH; 1866 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1867 mutex_spin_enter(&sc->sc_intr_lock); 1868 ohci_intr1(sc); 1869 mutex_spin_exit(&sc->sc_intr_lock); 1870 } 1871 } 1872 1873 /* 1874 * Add an ED to the schedule. Called with USB lock held. 1875 */ 1876 Static void 1877 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1878 { 1879 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1880 DPRINTFN(8, "sed=%p head=%p", sed, head, 0, 0); 1881 1882 KASSERT(mutex_owned(&sc->sc_lock)); 1883 1884 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1885 sizeof(head->ed.ed_nexted), 1886 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1887 sed->next = head->next; 1888 sed->ed.ed_nexted = head->ed.ed_nexted; 1889 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1890 sizeof(sed->ed.ed_nexted), 1891 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1892 head->next = sed; 1893 head->ed.ed_nexted = HTOO32(sed->physaddr); 1894 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1895 sizeof(head->ed.ed_nexted), 1896 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1897 } 1898 1899 /* 1900 * Remove an ED from the schedule. Called with USB lock held. 1901 */ 1902 Static void 1903 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1904 { 1905 ohci_soft_ed_t *p; 1906 1907 KASSERT(mutex_owned(&sc->sc_lock)); 1908 1909 /* XXX */ 1910 for (p = head; p != NULL && p->next != sed; p = p->next) 1911 ; 1912 KASSERT(p != NULL); 1913 1914 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1915 sizeof(sed->ed.ed_nexted), 1916 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1917 p->next = sed->next; 1918 p->ed.ed_nexted = sed->ed.ed_nexted; 1919 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1920 sizeof(p->ed.ed_nexted), 1921 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1922 } 1923 1924 /* 1925 * When a transfer is completed the TD is added to the done queue by 1926 * the host controller. This queue is the processed by software. 1927 * Unfortunately the queue contains the physical address of the TD 1928 * and we have no simple way to translate this back to a kernel address. 1929 * To make the translation possible (and fast) we use a hash table of 1930 * TDs currently in the schedule. The physical address is used as the 1931 * hash value. 1932 */ 1933 1934 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1935 /* Called with USB lock held. */ 1936 void 1937 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1938 { 1939 int h = HASH(std->physaddr); 1940 1941 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1942 1943 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1944 } 1945 1946 /* Called with USB lock held. */ 1947 void 1948 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1949 { 1950 1951 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1952 1953 LIST_REMOVE(std, hnext); 1954 } 1955 1956 ohci_soft_td_t * 1957 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1958 { 1959 int h = HASH(a); 1960 ohci_soft_td_t *std; 1961 1962 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1963 std != NULL; 1964 std = LIST_NEXT(std, hnext)) 1965 if (std->physaddr == a) 1966 return std; 1967 return NULL; 1968 } 1969 1970 /* Called with USB lock held. */ 1971 void 1972 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1973 { 1974 int h = HASH(sitd->physaddr); 1975 1976 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1977 1978 KASSERT(mutex_owned(&sc->sc_lock)); 1979 1980 DPRINTFN(10, "sitd=%p physaddr=0x%08lx", sitd, (u_long)sitd->physaddr, 1981 0, 0); 1982 1983 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1984 } 1985 1986 /* Called with USB lock held. */ 1987 void 1988 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1989 { 1990 1991 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1992 1993 KASSERT(mutex_owned(&sc->sc_lock)); 1994 1995 DPRINTFN(10, "sitd=%p physaddr=0x%08lx", sitd, (u_long)sitd->physaddr, 1996 0, 0); 1997 1998 LIST_REMOVE(sitd, hnext); 1999 } 2000 2001 ohci_soft_itd_t * 2002 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 2003 { 2004 int h = HASH(a); 2005 ohci_soft_itd_t *sitd; 2006 2007 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 2008 sitd != NULL; 2009 sitd = LIST_NEXT(sitd, hnext)) 2010 if (sitd->physaddr == a) 2011 return sitd; 2012 return NULL; 2013 } 2014 2015 void 2016 ohci_timeout(void *addr) 2017 { 2018 struct usbd_xfer *xfer = addr; 2019 struct ohci_xfer *oxfer = OHCI_XFER2OXFER(xfer); 2020 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2021 2022 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2023 DPRINTF("oxfer=%p", oxfer, 0, 0, 0); 2024 2025 if (sc->sc_dying) { 2026 mutex_enter(&sc->sc_lock); 2027 ohci_abort_xfer(xfer, USBD_TIMEOUT); 2028 mutex_exit(&sc->sc_lock); 2029 return; 2030 } 2031 2032 /* Execute the abort in a process context. */ 2033 usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr, 2034 USB_TASKQ_MPSAFE); 2035 usb_add_task(xfer->ux_pipe->up_dev, &oxfer->abort_task, 2036 USB_TASKQ_HC); 2037 } 2038 2039 void 2040 ohci_timeout_task(void *addr) 2041 { 2042 struct usbd_xfer *xfer = addr; 2043 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2044 2045 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2046 2047 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2048 2049 mutex_enter(&sc->sc_lock); 2050 ohci_abort_xfer(xfer, USBD_TIMEOUT); 2051 mutex_exit(&sc->sc_lock); 2052 } 2053 2054 #ifdef OHCI_DEBUG 2055 void 2056 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 2057 { 2058 for (; std; std = std->nexttd) { 2059 ohci_dump_td(sc, std); 2060 KASSERTMSG(std->nexttd == NULL || std != std->nexttd, 2061 "std %p next %p", std, std->nexttd); 2062 } 2063 } 2064 2065 void 2066 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 2067 { 2068 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2069 2070 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2071 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2072 2073 uint32_t flags = O32TOH(std->td.td_flags); 2074 DPRINTF("TD(%p) at 0x%08lx:", std, (u_long)std->physaddr, 0, 0); 2075 DPRINTF(" round=%d DP=%x DI=%x T=%x", 2076 !!(flags & OHCI_TD_R), 2077 __SHIFTOUT(flags, OHCI_TD_DP_MASK), 2078 OHCI_TD_GET_DI(flags), 2079 __SHIFTOUT(flags, OHCI_TD_TOGGLE_MASK)); 2080 DPRINTF(" EC=%d CC=%d", OHCI_TD_GET_EC(flags), OHCI_TD_GET_CC(flags), 2081 0, 0); 2082 DPRINTF(" td_cbp=0x%08lx td_nexttd=0x%08lx td_be=0x%08lx", 2083 (u_long)O32TOH(std->td.td_cbp), 2084 (u_long)O32TOH(std->td.td_nexttd), 2085 (u_long)O32TOH(std->td.td_be), 0); 2086 } 2087 2088 void 2089 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2090 { 2091 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2092 2093 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 2094 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2095 2096 uint32_t flags = O32TOH(sitd->itd.itd_flags); 2097 DPRINTF("ITD(%p) at 0x%08lx", sitd, (u_long)sitd->physaddr, 0, 0); 2098 DPRINTF(" sf=%d di=%d fc=%d cc=%d", 2099 OHCI_ITD_GET_SF(flags), OHCI_ITD_GET_DI(flags), 2100 OHCI_ITD_GET_FC(flags), OHCI_ITD_GET_CC(flags)); 2101 DPRINTF(" bp0=0x%08x next=0x%08x be=0x%08x", 2102 O32TOH(sitd->itd.itd_bp0), 2103 O32TOH(sitd->itd.itd_nextitd), 2104 O32TOH(sitd->itd.itd_be), 0); 2105 CTASSERT(OHCI_ITD_NOFFSET == 8); 2106 DPRINTF(" offs[0] = 0x%04x offs[1] = 0x%04x " 2107 "offs[2] = 0x%04x offs[3] = 0x%04x", 2108 O16TOH(sitd->itd.itd_offset[0]), 2109 O16TOH(sitd->itd.itd_offset[1]), 2110 O16TOH(sitd->itd.itd_offset[2]), 2111 O16TOH(sitd->itd.itd_offset[3])); 2112 DPRINTF(" offs[4] = 0x%04x offs[5] = 0x%04x " 2113 "offs[6] = 0x%04x offs[7] = 0x%04x", 2114 O16TOH(sitd->itd.itd_offset[4]), 2115 O16TOH(sitd->itd.itd_offset[5]), 2116 O16TOH(sitd->itd.itd_offset[6]), 2117 O16TOH(sitd->itd.itd_offset[7])); 2118 } 2119 2120 void 2121 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2122 { 2123 for (; sitd; sitd = sitd->nextitd) 2124 ohci_dump_itd(sc, sitd); 2125 } 2126 2127 void 2128 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2129 { 2130 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2131 2132 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2133 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2134 2135 uint32_t flags = O32TOH(sed->ed.ed_flags); 2136 DPRINTF("ED(%p) at 0x%08lx:", sed, sed->physaddr, 0, 0); 2137 DPRINTF(" addr=%d endpt=%d maxp=%d", 2138 OHCI_ED_GET_FA(flags), 2139 OHCI_ED_GET_EN(flags), 2140 OHCI_ED_GET_MAXP(flags), 2141 0); 2142 DPRINTF(" dir=%d speed=%d skip=%d iso=%d", 2143 __SHIFTOUT(flags, OHCI_ED_DIR_MASK), 2144 !!(flags & OHCI_ED_SPEED), 2145 !!(flags & OHCI_ED_SKIP), 2146 !!(flags & OHCI_ED_FORMAT_ISO)); 2147 DPRINTF(" tailp=0x%08lx", (u_long)O32TOH(sed->ed.ed_tailp), 2148 0, 0, 0); 2149 DPRINTF(" headp=0x%08lx nexted=0x%08lx halted=%d carry=%d", 2150 O32TOH(sed->ed.ed_headp), O32TOH(sed->ed.ed_nexted), 2151 !!(O32TOH(sed->ed.ed_headp) & OHCI_HALTED), 2152 !!(O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 2153 } 2154 #endif 2155 2156 usbd_status 2157 ohci_open(struct usbd_pipe *pipe) 2158 { 2159 struct usbd_device *dev = pipe->up_dev; 2160 struct usbd_bus *bus = dev->ud_bus; 2161 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2162 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 2163 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2164 uint8_t addr = dev->ud_addr; 2165 uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2166 ohci_soft_ed_t *sed; 2167 ohci_soft_td_t *std; 2168 ohci_soft_itd_t *sitd; 2169 ohci_physaddr_t tdphys; 2170 uint32_t fmt; 2171 usbd_status err = USBD_NOMEM; 2172 int ival; 2173 2174 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2175 DPRINTFN(1, "pipe=%p, addr=%d, endpt=%d (%d)", pipe, addr, 2176 ed->bEndpointAddress, bus->ub_rhaddr); 2177 2178 if (sc->sc_dying) { 2179 return USBD_IOERROR; 2180 } 2181 2182 std = NULL; 2183 sed = NULL; 2184 2185 if (addr == bus->ub_rhaddr) { 2186 switch (ed->bEndpointAddress) { 2187 case USB_CONTROL_ENDPOINT: 2188 pipe->up_methods = &roothub_ctrl_methods; 2189 break; 2190 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 2191 pipe->up_methods = &ohci_root_intr_methods; 2192 break; 2193 default: 2194 err = USBD_INVAL; 2195 goto bad; 2196 } 2197 } else { 2198 sed = ohci_alloc_sed(sc); 2199 if (sed == NULL) 2200 goto bad; 2201 opipe->sed = sed; 2202 if (xfertype == UE_ISOCHRONOUS) { 2203 sitd = ohci_alloc_sitd(sc); 2204 if (sitd == NULL) 2205 goto bad; 2206 2207 opipe->tail.itd = sitd; 2208 tdphys = sitd->physaddr; 2209 fmt = OHCI_ED_FORMAT_ISO; 2210 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2211 fmt |= OHCI_ED_DIR_IN; 2212 else 2213 fmt |= OHCI_ED_DIR_OUT; 2214 } else { 2215 std = ohci_alloc_std(sc); 2216 if (std == NULL) 2217 goto bad; 2218 2219 opipe->tail.td = std; 2220 tdphys = std->physaddr; 2221 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2222 } 2223 sed->ed.ed_flags = HTOO32( 2224 OHCI_ED_SET_FA(addr) | 2225 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2226 (dev->ud_speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2227 fmt | 2228 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2229 sed->ed.ed_headp = HTOO32(tdphys | 2230 (pipe->up_endpoint->ue_toggle ? OHCI_TOGGLECARRY : 0)); 2231 sed->ed.ed_tailp = HTOO32(tdphys); 2232 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2233 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2234 2235 switch (xfertype) { 2236 case UE_CONTROL: 2237 pipe->up_methods = &ohci_device_ctrl_methods; 2238 err = usb_allocmem(&sc->sc_bus, 2239 sizeof(usb_device_request_t), 2240 0, &opipe->ctrl.reqdma); 2241 if (err) 2242 goto bad; 2243 mutex_enter(&sc->sc_lock); 2244 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2245 mutex_exit(&sc->sc_lock); 2246 break; 2247 case UE_INTERRUPT: 2248 pipe->up_methods = &ohci_device_intr_methods; 2249 ival = pipe->up_interval; 2250 if (ival == USBD_DEFAULT_INTERVAL) 2251 ival = ed->bInterval; 2252 err = ohci_device_setintr(sc, opipe, ival); 2253 if (err) 2254 goto bad; 2255 break; 2256 case UE_ISOCHRONOUS: 2257 pipe->up_methods = &ohci_device_isoc_methods; 2258 return ohci_setup_isoc(pipe); 2259 case UE_BULK: 2260 pipe->up_methods = &ohci_device_bulk_methods; 2261 mutex_enter(&sc->sc_lock); 2262 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2263 mutex_exit(&sc->sc_lock); 2264 break; 2265 } 2266 } 2267 2268 return USBD_NORMAL_COMPLETION; 2269 2270 bad: 2271 if (std != NULL) { 2272 ohci_free_std(sc, std); 2273 } 2274 if (sed != NULL) 2275 ohci_free_sed(sc, sed); 2276 return err; 2277 2278 } 2279 2280 /* 2281 * Close a reqular pipe. 2282 * Assumes that there are no pending transactions. 2283 */ 2284 void 2285 ohci_close_pipe(struct usbd_pipe *pipe, ohci_soft_ed_t *head) 2286 { 2287 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2288 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2289 ohci_soft_ed_t *sed = opipe->sed; 2290 2291 KASSERT(mutex_owned(&sc->sc_lock)); 2292 2293 #ifdef DIAGNOSTIC 2294 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2295 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2296 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2297 ohci_soft_td_t *std; 2298 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2299 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2300 "tl=0x%x pipe=%p, std=%p\n", sed, 2301 (int)O32TOH(sed->ed.ed_headp), 2302 (int)O32TOH(sed->ed.ed_tailp), 2303 pipe, std); 2304 #ifdef OHCI_DEBUG 2305 usbd_dump_pipe(&opipe->pipe); 2306 ohci_dump_ed(sc, sed); 2307 if (std) 2308 ohci_dump_td(sc, std); 2309 #endif 2310 usb_delay_ms(&sc->sc_bus, 2); 2311 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2312 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2313 printf("ohci_close_pipe: pipe still not empty\n"); 2314 } 2315 #endif 2316 ohci_rem_ed(sc, sed, head); 2317 /* Make sure the host controller is not touching this ED */ 2318 usb_delay_ms(&sc->sc_bus, 1); 2319 pipe->up_endpoint->ue_toggle = 2320 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2321 ohci_free_sed_locked(sc, opipe->sed); 2322 } 2323 2324 /* 2325 * Abort a device request. 2326 * If this routine is called at splusb() it guarantees that the request 2327 * will be removed from the hardware scheduling and that the callback 2328 * for it will be called with USBD_CANCELLED status. 2329 * It's impossible to guarantee that the requested transfer will not 2330 * have happened since the hardware runs concurrently. 2331 * If the transaction has already happened we rely on the ordinary 2332 * interrupt processing to process it. 2333 * XXX This is most probably wrong. 2334 * XXXMRG this doesn't make sense anymore. 2335 */ 2336 void 2337 ohci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2338 { 2339 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2340 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2341 ohci_soft_ed_t *sed = opipe->sed; 2342 ohci_soft_td_t *p, *n; 2343 ohci_physaddr_t headp; 2344 int hit; 2345 int wake; 2346 2347 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2348 DPRINTF("xfer=%p pipe=%p sed=%p", xfer, opipe,sed, 0); 2349 2350 KASSERT(mutex_owned(&sc->sc_lock)); 2351 ASSERT_SLEEPABLE(); 2352 2353 if (sc->sc_dying) { 2354 /* If we're dying, just do the software part. */ 2355 xfer->ux_status = status; /* make software ignore it */ 2356 callout_halt(&xfer->ux_callout, &sc->sc_lock); 2357 usb_transfer_complete(xfer); 2358 return; 2359 } 2360 2361 /* 2362 * If an abort is already in progress then just wait for it to 2363 * complete and return. 2364 */ 2365 if (xfer->ux_hcflags & UXFER_ABORTING) { 2366 DPRINTFN(2, "already aborting", 0, 0, 0, 0); 2367 #ifdef DIAGNOSTIC 2368 if (status == USBD_TIMEOUT) 2369 printf("%s: TIMEOUT while aborting\n", __func__); 2370 #endif 2371 /* Override the status which might be USBD_TIMEOUT. */ 2372 xfer->ux_status = status; 2373 DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0); 2374 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2375 while (xfer->ux_hcflags & UXFER_ABORTING) 2376 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2377 goto done; 2378 } 2379 xfer->ux_hcflags |= UXFER_ABORTING; 2380 2381 /* 2382 * Step 1: Make interrupt routine and hardware ignore xfer. 2383 */ 2384 xfer->ux_status = status; /* make software ignore it */ 2385 callout_stop(&xfer->ux_callout); 2386 DPRINTFN(1, "stop ed=%p", sed, 0, 0, 0); 2387 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2388 sizeof(sed->ed.ed_flags), 2389 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2390 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2391 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2392 sizeof(sed->ed.ed_flags), 2393 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2394 2395 /* 2396 * Step 2: Wait until we know hardware has finished any possible 2397 * use of the xfer. Also make sure the soft interrupt routine 2398 * has run. 2399 */ 2400 /* Hardware finishes in 1ms */ 2401 usb_delay_ms_locked(opipe->pipe.up_dev->ud_bus, 20, &sc->sc_lock); 2402 sc->sc_softwake = 1; 2403 usb_schedsoftintr(&sc->sc_bus); 2404 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2405 2406 /* 2407 * Step 3: Remove any vestiges of the xfer from the hardware. 2408 * The complication here is that the hardware may have executed 2409 * beyond the xfer we're trying to abort. So as we're scanning 2410 * the TDs of this xfer we check if the hardware points to 2411 * any of them. 2412 */ 2413 p = xfer->ux_hcpriv; 2414 KASSERT(p); 2415 2416 #ifdef OHCI_DEBUG 2417 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2418 2419 if (ohcidebug >= 2) { 2420 DPRINTF("sed:", 0, 0, 0, 0); 2421 ohci_dump_ed(sc, sed); 2422 ohci_dump_tds(sc, p); 2423 } 2424 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2425 #endif 2426 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2427 hit = 0; 2428 for (; p->xfer == xfer; p = n) { 2429 hit |= headp == p->physaddr; 2430 n = p->nexttd; 2431 ohci_hash_rem_td(sc, p); 2432 } 2433 /* Zap headp register if hardware pointed inside the xfer. */ 2434 if (hit) { 2435 DPRINTFN(1, "set hd=0x%08x, tl=0x%08x", (int)p->physaddr, 2436 (int)O32TOH(sed->ed.ed_tailp), 0, 0); 2437 sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */ 2438 usb_syncmem(&sed->dma, 2439 sed->offs + offsetof(ohci_ed_t, ed_headp), 2440 sizeof(sed->ed.ed_headp), 2441 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2442 } else { 2443 DPRINTFN(1, "no hit", 0, 0, 0, 0); 2444 } 2445 2446 /* 2447 * Step 4: Turn on hardware again. 2448 */ 2449 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2450 sizeof(sed->ed.ed_flags), 2451 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2452 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2453 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2454 sizeof(sed->ed.ed_flags), 2455 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2456 2457 /* 2458 * Step 5: Execute callback. 2459 */ 2460 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2461 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2462 usb_transfer_complete(xfer); 2463 if (wake) 2464 cv_broadcast(&xfer->ux_hccv); 2465 2466 done: 2467 KASSERT(mutex_owned(&sc->sc_lock)); 2468 } 2469 2470 /* 2471 * Data structures and routines to emulate the root hub. 2472 */ 2473 Static int 2474 ohci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2475 void *buf, int buflen) 2476 { 2477 ohci_softc_t *sc = OHCI_BUS2SC(bus); 2478 usb_port_status_t ps; 2479 uint16_t len, value, index; 2480 int l, totlen = 0; 2481 int port, i; 2482 uint32_t v; 2483 2484 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2485 2486 if (sc->sc_dying) 2487 return -1; 2488 2489 DPRINTFN(4, "type=0x%02x request=%02x", req->bmRequestType, 2490 req->bRequest, 0, 0); 2491 2492 len = UGETW(req->wLength); 2493 value = UGETW(req->wValue); 2494 index = UGETW(req->wIndex); 2495 2496 #define C(x,y) ((x) | ((y) << 8)) 2497 switch (C(req->bRequest, req->bmRequestType)) { 2498 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2499 DPRINTFN(8, "wValue=0x%04x", value, 0, 0, 0); 2500 if (len == 0) 2501 break; 2502 switch (value) { 2503 case C(0, UDESC_DEVICE): { 2504 usb_device_descriptor_t devd; 2505 2506 totlen = min(buflen, sizeof(devd)); 2507 memcpy(&devd, buf, totlen); 2508 USETW(devd.idVendor, sc->sc_id_vendor); 2509 memcpy(buf, &devd, totlen); 2510 break; 2511 } 2512 case C(1, UDESC_STRING): 2513 #define sd ((usb_string_descriptor_t *)buf) 2514 /* Vendor */ 2515 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2516 break; 2517 case C(2, UDESC_STRING): 2518 /* Product */ 2519 totlen = usb_makestrdesc(sd, len, "OHCI root hub"); 2520 break; 2521 #undef sd 2522 default: 2523 /* default from usbroothub */ 2524 return buflen; 2525 } 2526 break; 2527 2528 /* Hub requests */ 2529 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2530 break; 2531 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2532 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 2533 index, value, 0, 0); 2534 if (index < 1 || index > sc->sc_noport) { 2535 return -1; 2536 } 2537 port = OHCI_RH_PORT_STATUS(index); 2538 switch(value) { 2539 case UHF_PORT_ENABLE: 2540 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2541 break; 2542 case UHF_PORT_SUSPEND: 2543 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2544 break; 2545 case UHF_PORT_POWER: 2546 /* Yes, writing to the LOW_SPEED bit clears power. */ 2547 OWRITE4(sc, port, UPS_LOW_SPEED); 2548 break; 2549 case UHF_C_PORT_CONNECTION: 2550 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2551 break; 2552 case UHF_C_PORT_ENABLE: 2553 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2554 break; 2555 case UHF_C_PORT_SUSPEND: 2556 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2557 break; 2558 case UHF_C_PORT_OVER_CURRENT: 2559 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2560 break; 2561 case UHF_C_PORT_RESET: 2562 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2563 break; 2564 default: 2565 return -1; 2566 } 2567 switch(value) { 2568 case UHF_C_PORT_CONNECTION: 2569 case UHF_C_PORT_ENABLE: 2570 case UHF_C_PORT_SUSPEND: 2571 case UHF_C_PORT_OVER_CURRENT: 2572 case UHF_C_PORT_RESET: 2573 /* Enable RHSC interrupt if condition is cleared. */ 2574 if ((OREAD4(sc, port) >> 16) == 0) 2575 ohci_rhsc_enable(sc); 2576 break; 2577 default: 2578 break; 2579 } 2580 break; 2581 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2582 if (len == 0) 2583 break; 2584 if ((value & 0xff) != 0) { 2585 return -1; 2586 } 2587 usb_hub_descriptor_t hubd; 2588 2589 totlen = min(buflen, sizeof(hubd)); 2590 memcpy(&hubd, buf, totlen); 2591 2592 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2593 hubd.bNbrPorts = sc->sc_noport; 2594 USETW(hubd.wHubCharacteristics, 2595 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2596 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2597 /* XXX overcurrent */ 2598 ); 2599 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2600 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2601 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2602 hubd.DeviceRemovable[i++] = (uint8_t)v; 2603 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2604 totlen = min(totlen, hubd.bDescLength); 2605 memcpy(buf, &hubd, totlen); 2606 break; 2607 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2608 if (len != 4) { 2609 return -1; 2610 } 2611 memset(buf, 0, len); /* ? XXX */ 2612 totlen = len; 2613 break; 2614 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2615 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 2616 if (index < 1 || index > sc->sc_noport) { 2617 return -1; 2618 } 2619 if (len != 4) { 2620 return -1; 2621 } 2622 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2623 DPRINTFN(8, "port status=0x%04x", v, 0, 0, 0); 2624 USETW(ps.wPortStatus, v); 2625 USETW(ps.wPortChange, v >> 16); 2626 totlen = min(len, sizeof(ps)); 2627 memcpy(buf, &ps, totlen); 2628 break; 2629 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2630 return -1; 2631 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2632 break; 2633 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2634 if (index < 1 || index > sc->sc_noport) { 2635 return -1; 2636 } 2637 port = OHCI_RH_PORT_STATUS(index); 2638 switch(value) { 2639 case UHF_PORT_ENABLE: 2640 OWRITE4(sc, port, UPS_PORT_ENABLED); 2641 break; 2642 case UHF_PORT_SUSPEND: 2643 OWRITE4(sc, port, UPS_SUSPEND); 2644 break; 2645 case UHF_PORT_RESET: 2646 DPRINTFN(5, "reset port %d", index, 0, 0, 0); 2647 OWRITE4(sc, port, UPS_RESET); 2648 for (i = 0; i < 5; i++) { 2649 usb_delay_ms(&sc->sc_bus, 2650 USB_PORT_ROOT_RESET_DELAY); 2651 if (sc->sc_dying) { 2652 return -1; 2653 } 2654 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2655 break; 2656 } 2657 DPRINTFN(8, "port %d reset, status = 0x%04x", index, 2658 OREAD4(sc, port), 0, 0); 2659 break; 2660 case UHF_PORT_POWER: 2661 DPRINTFN(2, "set port power %d", index, 0, 0, 0); 2662 OWRITE4(sc, port, UPS_PORT_POWER); 2663 break; 2664 default: 2665 return -1; 2666 } 2667 break; 2668 default: 2669 /* default from usbroothub */ 2670 return buflen; 2671 } 2672 2673 return totlen; 2674 } 2675 2676 Static usbd_status 2677 ohci_root_intr_transfer(struct usbd_xfer *xfer) 2678 { 2679 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2680 usbd_status err; 2681 2682 /* Insert last in queue. */ 2683 mutex_enter(&sc->sc_lock); 2684 err = usb_insert_transfer(xfer); 2685 mutex_exit(&sc->sc_lock); 2686 if (err) 2687 return err; 2688 2689 /* Pipe isn't running, start first */ 2690 return ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2691 } 2692 2693 Static usbd_status 2694 ohci_root_intr_start(struct usbd_xfer *xfer) 2695 { 2696 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2697 2698 if (sc->sc_dying) 2699 return USBD_IOERROR; 2700 2701 mutex_enter(&sc->sc_lock); 2702 KASSERT(sc->sc_intrxfer == NULL); 2703 sc->sc_intrxfer = xfer; 2704 mutex_exit(&sc->sc_lock); 2705 2706 return USBD_IN_PROGRESS; 2707 } 2708 2709 /* Abort a root interrupt request. */ 2710 Static void 2711 ohci_root_intr_abort(struct usbd_xfer *xfer) 2712 { 2713 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2714 2715 KASSERT(mutex_owned(&sc->sc_lock)); 2716 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2717 2718 sc->sc_intrxfer = NULL; 2719 2720 xfer->ux_status = USBD_CANCELLED; 2721 usb_transfer_complete(xfer); 2722 } 2723 2724 /* Close the root pipe. */ 2725 Static void 2726 ohci_root_intr_close(struct usbd_pipe *pipe) 2727 { 2728 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2729 2730 KASSERT(mutex_owned(&sc->sc_lock)); 2731 2732 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2733 2734 sc->sc_intrxfer = NULL; 2735 } 2736 2737 /************************/ 2738 2739 int 2740 ohci_device_ctrl_init(struct usbd_xfer *xfer) 2741 { 2742 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2743 usb_device_request_t *req = &xfer->ux_request; 2744 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2745 ohci_soft_td_t *stat, *setup; 2746 int isread = req->bmRequestType & UT_READ; 2747 int len = xfer->ux_bufsize; 2748 int err = ENOMEM; 2749 2750 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2751 2752 setup = ohci_alloc_std(sc); 2753 if (setup == NULL) { 2754 goto bad1; 2755 } 2756 stat = ohci_alloc_std(sc); 2757 if (stat == NULL) { 2758 goto bad2; 2759 } 2760 2761 ox->ox_setup = setup; 2762 ox->ox_stat = stat; 2763 ox->ox_nstd = 0; 2764 2765 /* Set up data transaction */ 2766 if (len != 0) { 2767 err = ohci_alloc_std_chain(sc, xfer, len, isread); 2768 if (err) { 2769 goto bad3; 2770 } 2771 } 2772 return 0; 2773 2774 bad3: 2775 ohci_free_std(sc, stat); 2776 bad2: 2777 ohci_free_std(sc, setup); 2778 bad1: 2779 return err; 2780 } 2781 2782 void 2783 ohci_device_ctrl_fini(struct usbd_xfer *xfer) 2784 { 2785 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2786 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2787 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2788 2789 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2790 DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0); 2791 2792 mutex_enter(&sc->sc_lock); 2793 if (ox->ox_setup != opipe->tail.td) { 2794 ohci_free_std_locked(sc, ox->ox_setup); 2795 } 2796 for (size_t i = 0; i < ox->ox_nstd; i++) { 2797 ohci_soft_td_t *std = ox->ox_stds[i]; 2798 if (std == NULL) 2799 break; 2800 ohci_free_std_locked(sc, std); 2801 } 2802 ohci_free_std_locked(sc, ox->ox_stat); 2803 mutex_exit(&sc->sc_lock); 2804 2805 if (ox->ox_nstd) { 2806 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 2807 kmem_free(ox->ox_stds, sz); 2808 } 2809 } 2810 2811 Static usbd_status 2812 ohci_device_ctrl_transfer(struct usbd_xfer *xfer) 2813 { 2814 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2815 usbd_status err; 2816 2817 /* Insert last in queue. */ 2818 mutex_enter(&sc->sc_lock); 2819 err = usb_insert_transfer(xfer); 2820 mutex_exit(&sc->sc_lock); 2821 if (err) 2822 return err; 2823 2824 /* Pipe isn't running, start first */ 2825 return ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2826 } 2827 2828 Static usbd_status 2829 ohci_device_ctrl_start(struct usbd_xfer *xfer) 2830 { 2831 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2832 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2833 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2834 usb_device_request_t *req = &xfer->ux_request; 2835 struct usbd_device *dev __diagused = opipe->pipe.up_dev; 2836 ohci_soft_td_t *setup, *stat, *next, *tail; 2837 ohci_soft_ed_t *sed; 2838 int isread; 2839 int len; 2840 2841 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2842 2843 if (sc->sc_dying) 2844 return USBD_IOERROR; 2845 2846 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2847 2848 isread = req->bmRequestType & UT_READ; 2849 len = UGETW(req->wLength); 2850 2851 DPRINTF("xfer=%p len=%d, addr=%d, endpt=%d", xfer, len, dev->ud_addr, 2852 opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress); 2853 DPRINTF("type=0x%02x, request=0x%02x, wValue=0x%04x, wIndex=0x%04x", 2854 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2855 UGETW(req->wIndex)); 2856 2857 /* Need to take lock here for pipe->tail.td */ 2858 mutex_enter(&sc->sc_lock); 2859 2860 /* 2861 * Use the pipe "tail" TD as our first and loan our first TD to the 2862 * next transfer 2863 */ 2864 setup = opipe->tail.td; 2865 opipe->tail.td = ox->ox_setup; 2866 ox->ox_setup = setup; 2867 2868 stat = ox->ox_stat; 2869 tail = opipe->tail.td; /* point at sentinel */ 2870 2871 sed = opipe->sed; 2872 2873 KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->ud_addr, 2874 "address ED %d pipe %d\n", 2875 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->ud_addr); 2876 KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) == 2877 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 2878 "MPL ED %d pipe %d\n", 2879 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), 2880 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 2881 2882 /* next will point to data if len != 0 */ 2883 next = stat; 2884 2885 /* Set up data transaction */ 2886 if (len != 0) { 2887 ohci_soft_td_t *std; 2888 ohci_soft_td_t *end; 2889 2890 next = ox->ox_stds[0]; 2891 ohci_reset_std_chain(sc, xfer, len, isread, next, &end); 2892 2893 end->td.td_nexttd = HTOO32(stat->physaddr); 2894 end->nexttd = stat; 2895 2896 usb_syncmem(&end->dma, 2897 end->offs + offsetof(ohci_td_t, td_nexttd), 2898 sizeof(end->td.td_nexttd), 2899 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2900 2901 usb_syncmem(&xfer->ux_dmabuf, 0, len, 2902 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2903 std = ox->ox_stds[0]; 2904 /* Start toggle at 1 and then use the carried toggle. */ 2905 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 2906 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 2907 usb_syncmem(&std->dma, 2908 std->offs + offsetof(ohci_td_t, td_flags), 2909 sizeof(std->td.td_flags), 2910 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2911 } 2912 2913 DPRINTFN(8, "setup %p data %p stat %p tail %p", setup, 2914 (len != 0 ? ox->ox_stds[0] : NULL), stat, tail); 2915 KASSERT(opipe->tail.td == tail); 2916 2917 memcpy(KERNADDR(&opipe->ctrl.reqdma, 0), req, sizeof(*req)); 2918 usb_syncmem(&opipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2919 2920 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 2921 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 2922 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->ctrl.reqdma, 0)); 2923 setup->td.td_nexttd = HTOO32(next->physaddr); 2924 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof(*req) - 1); 2925 setup->nexttd = next; 2926 setup->len = 0; 2927 setup->xfer = xfer; 2928 setup->flags = 0; 2929 ohci_hash_add_td(sc, setup); 2930 2931 xfer->ux_hcpriv = setup; 2932 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2933 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2934 2935 stat->td.td_flags = HTOO32( 2936 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 2937 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 2938 stat->td.td_cbp = 0; 2939 stat->td.td_nexttd = HTOO32(tail->physaddr); 2940 stat->td.td_be = 0; 2941 stat->nexttd = tail; 2942 stat->flags = OHCI_CALL_DONE; 2943 stat->len = 0; 2944 stat->xfer = xfer; 2945 ohci_hash_add_td(sc, stat); 2946 2947 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2948 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2949 2950 memset(&tail->td, 0, sizeof(tail->td)); 2951 tail->nexttd = NULL; 2952 tail->xfer = NULL; 2953 2954 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 2955 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2956 2957 2958 #ifdef OHCI_DEBUG 2959 USBHIST_LOGN(ohcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2960 if (ohcidebug >= 5) { 2961 ohci_dump_ed(sc, sed); 2962 ohci_dump_tds(sc, setup); 2963 } 2964 USBHIST_LOGN(ohcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2965 #endif 2966 2967 /* Insert ED in schedule */ 2968 sed->ed.ed_tailp = HTOO32(tail->physaddr); 2969 usb_syncmem(&sed->dma, 2970 sed->offs + offsetof(ohci_ed_t, ed_tailp), 2971 sizeof(sed->ed.ed_tailp), 2972 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2973 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2974 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2975 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2976 ohci_timeout, xfer); 2977 } 2978 2979 DPRINTF("done", 0, 0, 0, 0); 2980 2981 mutex_exit(&sc->sc_lock); 2982 2983 if (sc->sc_bus.ub_usepolling) 2984 ohci_waitintr(sc, xfer); 2985 2986 return USBD_IN_PROGRESS; 2987 } 2988 2989 /* Abort a device control request. */ 2990 Static void 2991 ohci_device_ctrl_abort(struct usbd_xfer *xfer) 2992 { 2993 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 2994 2995 KASSERT(mutex_owned(&sc->sc_lock)); 2996 2997 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2998 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2999 ohci_abort_xfer(xfer, USBD_CANCELLED); 3000 } 3001 3002 /* Close a device control pipe. */ 3003 Static void 3004 ohci_device_ctrl_close(struct usbd_pipe *pipe) 3005 { 3006 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3007 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3008 3009 KASSERT(mutex_owned(&sc->sc_lock)); 3010 3011 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3012 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3013 ohci_close_pipe(pipe, sc->sc_ctrl_head); 3014 ohci_free_std_locked(sc, opipe->tail.td); 3015 } 3016 3017 /************************/ 3018 3019 Static void 3020 ohci_device_clear_toggle(struct usbd_pipe *pipe) 3021 { 3022 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3023 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3024 3025 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 3026 } 3027 3028 Static void 3029 ohci_noop(struct usbd_pipe *pipe) 3030 { 3031 } 3032 3033 Static int 3034 ohci_device_bulk_init(struct usbd_xfer *xfer) 3035 { 3036 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3037 int len = xfer->ux_bufsize; 3038 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;; 3039 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3040 int err; 3041 3042 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3043 3044 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3045 3046 DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread, 3047 xfer->ux_flags); 3048 DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0); 3049 3050 /* Allocate a chain of new TDs (including a new tail). */ 3051 err = ohci_alloc_std_chain(sc, xfer, len, isread); 3052 if (err) 3053 return err; 3054 3055 return 0; 3056 } 3057 3058 Static void 3059 ohci_device_bulk_fini(struct usbd_xfer *xfer) 3060 { 3061 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3062 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3063 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3064 3065 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3066 DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0); 3067 3068 mutex_enter(&sc->sc_lock); 3069 for (size_t i = 0; i < ox->ox_nstd; i++) { 3070 ohci_soft_td_t *std = ox->ox_stds[i]; 3071 if (std == NULL) 3072 break; 3073 if (std != opipe->tail.td) 3074 ohci_free_std_locked(sc, std); 3075 } 3076 mutex_exit(&sc->sc_lock); 3077 3078 if (ox->ox_nstd) { 3079 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 3080 kmem_free(ox->ox_stds, sz); 3081 } 3082 } 3083 3084 Static usbd_status 3085 ohci_device_bulk_transfer(struct usbd_xfer *xfer) 3086 { 3087 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3088 usbd_status err; 3089 3090 /* Insert last in queue. */ 3091 mutex_enter(&sc->sc_lock); 3092 err = usb_insert_transfer(xfer); 3093 mutex_exit(&sc->sc_lock); 3094 if (err) 3095 return err; 3096 3097 /* Pipe isn't running, start first */ 3098 return ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3099 } 3100 3101 Static usbd_status 3102 ohci_device_bulk_start(struct usbd_xfer *xfer) 3103 { 3104 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3105 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3106 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3107 ohci_soft_td_t *last; 3108 ohci_soft_td_t *data, *tail, *tdp; 3109 ohci_soft_ed_t *sed; 3110 int len, isread, endpt; 3111 3112 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3113 3114 if (sc->sc_dying) 3115 return USBD_IOERROR; 3116 3117 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3118 3119 len = xfer->ux_length; 3120 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3121 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3122 sed = opipe->sed; 3123 3124 DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread, 3125 xfer->ux_flags); 3126 DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0); 3127 3128 mutex_enter(&sc->sc_lock); 3129 3130 /* 3131 * Use the pipe "tail" TD as our first and loan our first TD to the 3132 * next transfer 3133 */ 3134 data = opipe->tail.td; 3135 opipe->tail.td = ox->ox_stds[0]; 3136 ox->ox_stds[0] = data; 3137 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3138 3139 tail = opipe->tail.td; /* point at sentinel */ 3140 memset(&tail->td, 0, sizeof(tail->td)); 3141 tail->nexttd = NULL; 3142 tail->xfer = NULL; 3143 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3144 BUS_DMASYNC_PREWRITE); 3145 xfer->ux_hcpriv = data; 3146 3147 DPRINTFN(8, "xfer %p data %p tail %p", xfer, ox->ox_stds[0], tail, 0); 3148 KASSERT(opipe->tail.td == tail); 3149 3150 /* We want interrupt at the end of the transfer. */ 3151 last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3152 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3153 3154 last->td.td_nexttd = HTOO32(tail->physaddr); 3155 last->nexttd = tail; 3156 last->flags |= OHCI_CALL_DONE; 3157 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3158 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3159 3160 DPRINTFN(4, "ed_flags=0x%08x td_flags=0x%08x " 3161 "td_cbp=0x%08x td_be=0x%08x", 3162 (int)O32TOH(sed->ed.ed_flags), 3163 (int)O32TOH(data->td.td_flags), 3164 (int)O32TOH(data->td.td_cbp), 3165 (int)O32TOH(data->td.td_be)); 3166 3167 #ifdef OHCI_DEBUG 3168 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3169 if (ohcidebug >= 5) { 3170 ohci_dump_ed(sc, sed); 3171 ohci_dump_tds(sc, data); 3172 } 3173 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3174 #endif 3175 3176 /* Insert ED in schedule */ 3177 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3178 KASSERT(tdp->xfer == xfer); 3179 } 3180 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3181 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3182 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3183 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3184 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3185 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3186 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3187 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3188 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3189 ohci_timeout, xfer); 3190 } 3191 mutex_exit(&sc->sc_lock); 3192 3193 return USBD_IN_PROGRESS; 3194 } 3195 3196 Static void 3197 ohci_device_bulk_abort(struct usbd_xfer *xfer) 3198 { 3199 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3200 3201 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3202 3203 KASSERT(mutex_owned(&sc->sc_lock)); 3204 3205 DPRINTF("xfer=%p", xfer, 0, 0, 0); 3206 ohci_abort_xfer(xfer, USBD_CANCELLED); 3207 } 3208 3209 /* 3210 * Close a device bulk pipe. 3211 */ 3212 Static void 3213 ohci_device_bulk_close(struct usbd_pipe *pipe) 3214 { 3215 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3216 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3217 3218 KASSERT(mutex_owned(&sc->sc_lock)); 3219 3220 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3221 3222 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3223 ohci_close_pipe(pipe, sc->sc_bulk_head); 3224 ohci_free_std_locked(sc, opipe->tail.td); 3225 } 3226 3227 /************************/ 3228 3229 Static int 3230 ohci_device_intr_init(struct usbd_xfer *xfer) 3231 { 3232 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3233 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3234 int len = xfer->ux_bufsize; 3235 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;; 3236 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3237 int err; 3238 3239 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3240 3241 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3242 KASSERT(len != 0); 3243 3244 DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread, 3245 xfer->ux_flags); 3246 DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0); 3247 3248 ox->ox_nstd = 0; 3249 3250 err = ohci_alloc_std_chain(sc, xfer, len, isread); 3251 if (err) { 3252 return err; 3253 } 3254 3255 return 0; 3256 } 3257 3258 Static void 3259 ohci_device_intr_fini(struct usbd_xfer *xfer) 3260 { 3261 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3262 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3263 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3264 3265 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3266 DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0); 3267 3268 mutex_enter(&sc->sc_lock); 3269 for (size_t i = 0; i < ox->ox_nstd; i++) { 3270 ohci_soft_td_t *std = ox->ox_stds[i]; 3271 if (std != NULL) 3272 break; 3273 if (std != opipe->tail.td) 3274 ohci_free_std_locked(sc, std); 3275 } 3276 mutex_exit(&sc->sc_lock); 3277 3278 if (ox->ox_nstd) { 3279 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 3280 kmem_free(ox->ox_stds, sz); 3281 } 3282 } 3283 3284 Static usbd_status 3285 ohci_device_intr_transfer(struct usbd_xfer *xfer) 3286 { 3287 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3288 usbd_status err; 3289 3290 /* Insert last in queue. */ 3291 mutex_enter(&sc->sc_lock); 3292 err = usb_insert_transfer(xfer); 3293 mutex_exit(&sc->sc_lock); 3294 if (err) 3295 return err; 3296 3297 /* Pipe isn't running, start first */ 3298 return ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3299 } 3300 3301 Static usbd_status 3302 ohci_device_intr_start(struct usbd_xfer *xfer) 3303 { 3304 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3305 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3306 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3307 ohci_soft_ed_t *sed = opipe->sed; 3308 ohci_soft_td_t *data, *last, *tail; 3309 int len, isread, endpt; 3310 3311 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3312 3313 if (sc->sc_dying) 3314 return USBD_IOERROR; 3315 3316 DPRINTFN(3, "xfer=%p len=%d flags=%d priv=%p", xfer, xfer->ux_length, 3317 xfer->ux_flags, xfer->ux_priv); 3318 3319 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3320 3321 len = xfer->ux_length; 3322 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3323 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3324 3325 mutex_enter(&sc->sc_lock); 3326 3327 /* 3328 * Use the pipe "tail" TD as our first and loan our first TD to the 3329 * next transfer. 3330 */ 3331 data = opipe->tail.td; 3332 opipe->tail.td = ox->ox_stds[0]; 3333 ox->ox_stds[0] = data; 3334 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3335 3336 tail = opipe->tail.td; /* point at sentinel */ 3337 memset(&tail->td, 0, sizeof(tail->td)); 3338 tail->nexttd = NULL; 3339 tail->xfer = NULL; 3340 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3341 BUS_DMASYNC_PREWRITE); 3342 xfer->ux_hcpriv = data; 3343 3344 DPRINTFN(8, "data %p tail %p", ox->ox_stds[0], tail, 0, 0); 3345 KASSERT(opipe->tail.td == tail); 3346 3347 /* We want interrupt at the end of the transfer. */ 3348 last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3349 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3350 3351 last->td.td_nexttd = HTOO32(tail->physaddr); 3352 last->nexttd = tail; 3353 last->flags |= OHCI_CALL_DONE; 3354 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3355 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3356 3357 #ifdef OHCI_DEBUG 3358 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3359 if (ohcidebug >= 5) { 3360 ohci_dump_ed(sc, sed); 3361 ohci_dump_tds(sc, data); 3362 } 3363 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3364 #endif 3365 3366 /* Insert ED in schedule */ 3367 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3368 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3369 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3370 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3371 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3372 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3373 3374 mutex_exit(&sc->sc_lock); 3375 3376 return USBD_IN_PROGRESS; 3377 } 3378 3379 /* Abort a device interrupt request. */ 3380 Static void 3381 ohci_device_intr_abort(struct usbd_xfer *xfer) 3382 { 3383 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3384 3385 KASSERT(mutex_owned(&sc->sc_lock)); 3386 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3387 3388 ohci_abort_xfer(xfer, USBD_CANCELLED); 3389 } 3390 3391 /* Close a device interrupt pipe. */ 3392 Static void 3393 ohci_device_intr_close(struct usbd_pipe *pipe) 3394 { 3395 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3396 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3397 int nslots = opipe->intr.nslots; 3398 int pos = opipe->intr.pos; 3399 int j; 3400 ohci_soft_ed_t *p, *sed = opipe->sed; 3401 3402 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3403 3404 KASSERT(mutex_owned(&sc->sc_lock)); 3405 3406 DPRINTFN(1, "pipe=%p nslots=%d pos=%d", pipe, nslots, pos, 0); 3407 usb_syncmem(&sed->dma, sed->offs, 3408 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3409 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3410 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3411 sizeof(sed->ed.ed_flags), 3412 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3413 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3414 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3415 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3416 3417 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3418 continue; 3419 KASSERT(p); 3420 p->next = sed->next; 3421 p->ed.ed_nexted = sed->ed.ed_nexted; 3422 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3423 sizeof(p->ed.ed_nexted), 3424 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3425 3426 for (j = 0; j < nslots; j++) 3427 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3428 3429 ohci_free_std_locked(sc, opipe->tail.td); 3430 ohci_free_sed_locked(sc, opipe->sed); 3431 } 3432 3433 Static usbd_status 3434 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3435 { 3436 int i, j, best; 3437 u_int npoll, slow, shigh, nslots; 3438 u_int bestbw, bw; 3439 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3440 3441 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3442 3443 DPRINTFN(2, "pipe=%p", opipe, 0, 0, 0); 3444 if (ival == 0) { 3445 printf("ohci_setintr: 0 interval\n"); 3446 return USBD_INVAL; 3447 } 3448 3449 npoll = OHCI_NO_INTRS; 3450 while (npoll > ival) 3451 npoll /= 2; 3452 DPRINTFN(2, "ival=%d npoll=%d", ival, npoll, 0, 0); 3453 3454 /* 3455 * We now know which level in the tree the ED must go into. 3456 * Figure out which slot has most bandwidth left over. 3457 * Slots to examine: 3458 * npoll 3459 * 1 0 3460 * 2 1 2 3461 * 4 3 4 5 6 3462 * 8 7 8 9 10 11 12 13 14 3463 * N (N-1) .. (N-1+N-1) 3464 */ 3465 slow = npoll-1; 3466 shigh = slow + npoll; 3467 nslots = OHCI_NO_INTRS / npoll; 3468 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3469 bw = 0; 3470 for (j = 0; j < nslots; j++) 3471 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3472 if (bw < bestbw) { 3473 best = i; 3474 bestbw = bw; 3475 } 3476 } 3477 DPRINTFN(2, "best=%d(%d..%d) bestbw=%d", best, slow, shigh, bestbw); 3478 3479 mutex_enter(&sc->sc_lock); 3480 hsed = sc->sc_eds[best]; 3481 sed->next = hsed->next; 3482 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3483 sizeof(hsed->ed.ed_flags), 3484 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3485 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3486 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3487 sizeof(sed->ed.ed_flags), 3488 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3489 hsed->next = sed; 3490 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3491 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3492 sizeof(hsed->ed.ed_flags), 3493 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3494 mutex_exit(&sc->sc_lock); 3495 3496 for (j = 0; j < nslots; j++) 3497 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3498 opipe->intr.nslots = nslots; 3499 opipe->intr.pos = best; 3500 3501 DPRINTFN(5, "returns %p", opipe, 0, 0, 0); 3502 return USBD_NORMAL_COMPLETION; 3503 } 3504 3505 /***********************/ 3506 3507 Static int 3508 ohci_device_isoc_init(struct usbd_xfer *xfer) 3509 { 3510 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3511 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3512 ohci_soft_itd_t *sitd; 3513 size_t i; 3514 int err; 3515 3516 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3517 3518 DPRINTFN(1, "xfer %p len %d flags %d", xfer, xfer->ux_length, 3519 xfer->ux_flags, 0); 3520 3521 const size_t nfsitd = 3522 (xfer->ux_nframes + OHCI_ITD_NOFFSET - 1) / OHCI_ITD_NOFFSET; 3523 const size_t nbsitd = xfer->ux_bufsize / OHCI_PAGE_SIZE; 3524 const size_t nsitd = MAX(nfsitd, nbsitd) + 1; 3525 3526 ox->ox_sitds = kmem_zalloc(sizeof(ohci_soft_itd_t *) * nsitd, 3527 KM_SLEEP); 3528 ox->ox_nsitd = nsitd; 3529 3530 for (i = 0; i < nsitd; i++) { 3531 /* Allocate next ITD */ 3532 sitd = ohci_alloc_sitd(sc); 3533 if (sitd == NULL) { 3534 err = ENOMEM; 3535 goto fail; 3536 } 3537 ox->ox_sitds[i] = sitd; 3538 sitd->xfer = xfer; 3539 sitd->flags = 0; 3540 } 3541 3542 return 0; 3543 fail: 3544 for (; i > 0;) { 3545 ohci_free_sitd(sc, ox->ox_sitds[--i]); 3546 } 3547 return err; 3548 } 3549 3550 Static void 3551 ohci_device_isoc_fini(struct usbd_xfer *xfer) 3552 { 3553 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3554 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3555 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3556 3557 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3558 3559 mutex_enter(&sc->sc_lock); 3560 for (size_t i = 0; i < ox->ox_nsitd; i++) { 3561 if (ox->ox_sitds[i] != opipe->tail.itd) { 3562 ohci_free_sitd_locked(sc, ox->ox_sitds[i]); 3563 } 3564 } 3565 mutex_exit(&sc->sc_lock); 3566 3567 if (ox->ox_nsitd) { 3568 const size_t sz = sizeof(ohci_soft_itd_t *) * ox->ox_nsitd; 3569 kmem_free(ox->ox_sitds, sz); 3570 } 3571 } 3572 3573 3574 usbd_status 3575 ohci_device_isoc_transfer(struct usbd_xfer *xfer) 3576 { 3577 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3578 usbd_status err; 3579 3580 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3581 3582 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 3583 3584 /* Put it on our queue, */ 3585 mutex_enter(&sc->sc_lock); 3586 err = usb_insert_transfer(xfer); 3587 mutex_exit(&sc->sc_lock); 3588 3589 /* bail out on error, */ 3590 if (err && err != USBD_IN_PROGRESS) 3591 return err; 3592 3593 /* XXX should check inuse here */ 3594 3595 /* insert into schedule, */ 3596 ohci_device_isoc_enter(xfer); 3597 3598 /* and start if the pipe wasn't running */ 3599 if (!err) 3600 ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3601 3602 return err; 3603 } 3604 3605 void 3606 ohci_device_isoc_enter(struct usbd_xfer *xfer) 3607 { 3608 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3609 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3610 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3611 ohci_soft_ed_t *sed = opipe->sed; 3612 ohci_soft_itd_t *sitd, *nsitd; 3613 ohci_physaddr_t buf, offs, noffs, bp0; 3614 int i, ncur, nframes; 3615 3616 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3617 3618 mutex_enter(&sc->sc_lock); 3619 3620 if (sc->sc_dying) { 3621 mutex_exit(&sc->sc_lock); 3622 return; 3623 } 3624 3625 struct isoc *isoc = &opipe->isoc; 3626 3627 DPRINTFN(1, "used=%d next=%d xfer=%p nframes=%d", 3628 isoc->inuse, isoc->next, xfer, xfer->ux_nframes); 3629 3630 if (isoc->next == -1) { 3631 /* Not in use yet, schedule it a few frames ahead. */ 3632 isoc->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3633 DPRINTFN(2,"start next=%d", isoc->next, 0, 0, 0); 3634 } 3635 3636 sitd = opipe->tail.itd; 3637 opipe->tail.itd = ox->ox_sitds[0]; 3638 ox->ox_sitds[0] = sitd; 3639 3640 buf = DMAADDR(&xfer->ux_dmabuf, 0); 3641 bp0 = OHCI_PAGE(buf); 3642 offs = OHCI_PAGE_OFFSET(buf); 3643 nframes = xfer->ux_nframes; 3644 xfer->ux_hcpriv = sitd; 3645 size_t j = 1; 3646 for (i = ncur = 0; i < nframes; i++, ncur++) { 3647 noffs = offs + xfer->ux_frlengths[i]; 3648 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3649 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3650 3651 /* Allocate next ITD */ 3652 nsitd = ox->ox_sitds[j++]; 3653 KASSERT(nsitd != NULL); 3654 KASSERT(j < ox->ox_nsitd); 3655 3656 /* Fill current ITD */ 3657 sitd->itd.itd_flags = HTOO32( 3658 OHCI_ITD_NOCC | 3659 OHCI_ITD_SET_SF(isoc->next) | 3660 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3661 OHCI_ITD_SET_FC(ncur)); 3662 sitd->itd.itd_bp0 = HTOO32(bp0); 3663 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3664 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3665 sitd->nextitd = nsitd; 3666 sitd->xfer = xfer; 3667 sitd->flags = 0; 3668 #ifdef DIAGNOSTIC 3669 sitd->isdone = false; 3670 #endif 3671 ohci_hash_add_itd(sc, sitd); 3672 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3673 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3674 3675 sitd = nsitd; 3676 isoc->next = isoc->next + ncur; 3677 bp0 = OHCI_PAGE(buf + offs); 3678 ncur = 0; 3679 } 3680 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3681 offs = noffs; 3682 } 3683 nsitd = ox->ox_sitds[j++]; 3684 KASSERT(nsitd != NULL); 3685 KASSERT(j <= ox->ox_nsitd); 3686 3687 memset(&nsitd->itd, 0, sizeof(nsitd->itd)); 3688 nsitd->nextitd = NULL; 3689 nsitd->xfer = NULL; 3690 /* Fixup last used ITD */ 3691 sitd->itd.itd_flags = HTOO32( 3692 OHCI_ITD_NOCC | 3693 OHCI_ITD_SET_SF(isoc->next) | 3694 OHCI_ITD_SET_DI(0) | 3695 OHCI_ITD_SET_FC(ncur)); 3696 sitd->itd.itd_bp0 = HTOO32(bp0); 3697 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3698 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3699 sitd->nextitd = nsitd; 3700 sitd->xfer = xfer; 3701 sitd->flags = OHCI_CALL_DONE; 3702 #ifdef DIAGNOSTIC 3703 sitd->isdone = false; 3704 #endif 3705 ohci_hash_add_itd(sc, sitd); 3706 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3707 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3708 3709 isoc->next = isoc->next + ncur; 3710 isoc->inuse += nframes; 3711 3712 /* XXX pretend we did it all */ 3713 xfer->ux_actlen = offs; 3714 3715 xfer->ux_status = USBD_IN_PROGRESS; 3716 3717 #ifdef OHCI_DEBUG 3718 if (ohcidebug >= 5) { 3719 DPRINTF("frame=%d", O32TOH(sc->sc_hcca->hcca_frame_number), 3720 0, 0, 0); 3721 ohci_dump_itds(sc, xfer->ux_hcpriv); 3722 ohci_dump_ed(sc, sed); 3723 } 3724 #endif 3725 3726 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3727 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3728 sed->ed.ed_tailp = HTOO32(nsitd->physaddr); 3729 opipe->tail.itd = nsitd; 3730 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3731 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3732 sizeof(sed->ed.ed_flags), 3733 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3734 mutex_exit(&sc->sc_lock); 3735 } 3736 3737 usbd_status 3738 ohci_device_isoc_start(struct usbd_xfer *xfer) 3739 { 3740 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3741 3742 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3743 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 3744 3745 mutex_enter(&sc->sc_lock); 3746 3747 if (sc->sc_dying) { 3748 mutex_exit(&sc->sc_lock); 3749 return USBD_IOERROR; 3750 } 3751 3752 3753 #ifdef DIAGNOSTIC 3754 if (xfer->ux_status != USBD_IN_PROGRESS) 3755 printf("ohci_device_isoc_start: not in progress %p\n", xfer); 3756 #endif 3757 3758 /* XXX anything to do? */ 3759 3760 mutex_exit(&sc->sc_lock); 3761 3762 return USBD_IN_PROGRESS; 3763 } 3764 3765 void 3766 ohci_device_isoc_abort(struct usbd_xfer *xfer) 3767 { 3768 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3769 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3770 ohci_soft_ed_t *sed; 3771 ohci_soft_itd_t *sitd; 3772 3773 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3774 DPRINTFN(1, "xfer=%p", xfer, 0, 0, 0); 3775 3776 KASSERT(mutex_owned(&sc->sc_lock)); 3777 3778 /* Transfer is already done. */ 3779 if (xfer->ux_status != USBD_NOT_STARTED && 3780 xfer->ux_status != USBD_IN_PROGRESS) { 3781 printf("ohci_device_isoc_abort: early return\n"); 3782 goto done; 3783 } 3784 3785 /* Give xfer the requested abort code. */ 3786 xfer->ux_status = USBD_CANCELLED; 3787 3788 sed = opipe->sed; 3789 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3790 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3791 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3792 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3793 sizeof(sed->ed.ed_flags), 3794 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3795 3796 sitd = xfer->ux_hcpriv; 3797 KASSERT(sitd); 3798 3799 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3800 #ifdef DIAGNOSTIC 3801 DPRINTFN(1, "abort sets done sitd=%p", sitd, 0, 0, 0); 3802 sitd->isdone = true; 3803 #endif 3804 } 3805 3806 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3807 3808 /* Run callback. */ 3809 usb_transfer_complete(xfer); 3810 3811 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3812 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3813 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3814 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3815 3816 done: 3817 KASSERT(mutex_owned(&sc->sc_lock)); 3818 } 3819 3820 void 3821 ohci_device_isoc_done(struct usbd_xfer *xfer) 3822 { 3823 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3824 DPRINTFN(1, "xfer=%p", xfer, 0, 0, 0); 3825 } 3826 3827 usbd_status 3828 ohci_setup_isoc(struct usbd_pipe *pipe) 3829 { 3830 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3831 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3832 struct isoc *isoc = &opipe->isoc; 3833 3834 isoc->next = -1; 3835 isoc->inuse = 0; 3836 3837 mutex_enter(&sc->sc_lock); 3838 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3839 mutex_exit(&sc->sc_lock); 3840 3841 return USBD_NORMAL_COMPLETION; 3842 } 3843 3844 void 3845 ohci_device_isoc_close(struct usbd_pipe *pipe) 3846 { 3847 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3848 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3849 3850 KASSERT(mutex_owned(&sc->sc_lock)); 3851 3852 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3853 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3854 ohci_close_pipe(pipe, sc->sc_isoc_head); 3855 #ifdef DIAGNOSTIC 3856 opipe->tail.itd->isdone = true; 3857 #endif 3858 ohci_free_sitd_locked(sc, opipe->tail.itd); 3859 } 3860
Indexes created Fri Oct 03 02:09:57 GMT 2025