ohci.c revision 1.254.2.54
1 /* $NetBSD: ohci.c,v 1.254.2.54 2016/02/28 09:16:20 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * USB Open Host Controller driver. 38 * 39 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 40 * USB spec: http://www.usb.org/developers/docs/ 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.254.2.54 2016/02/28 09:16:20 skrll Exp $"); 45 46 #include "opt_usb.h" 47 48 #include <sys/param.h> 49 50 #include <sys/cpu.h> 51 #include <sys/device.h> 52 #include <sys/kernel.h> 53 #include <sys/kmem.h> 54 #include <sys/proc.h> 55 #include <sys/queue.h> 56 #include <sys/select.h> 57 #include <sys/sysctl.h> 58 #include <sys/systm.h> 59 60 #include <machine/endian.h> 61 62 #include <dev/usb/usb.h> 63 #include <dev/usb/usbdi.h> 64 #include <dev/usb/usbdivar.h> 65 #include <dev/usb/usb_mem.h> 66 #include <dev/usb/usb_quirks.h> 67 68 #include <dev/usb/ohcireg.h> 69 #include <dev/usb/ohcivar.h> 70 #include <dev/usb/usbroothub.h> 71 #include <dev/usb/usbhist.h> 72 73 #ifdef USB_DEBUG 74 #ifndef OHCI_DEBUG 75 #define ohcidebug 0 76 #else 77 static int ohcidebug = 0; 78 79 SYSCTL_SETUP(sysctl_hw_ohci_setup, "sysctl hw.ohci setup") 80 { 81 int err; 82 const struct sysctlnode *rnode; 83 const struct sysctlnode *cnode; 84 85 err = sysctl_createv(clog, 0, NULL, &rnode, 86 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ohci", 87 SYSCTL_DESCR("ohci global controls"), 88 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 89 90 if (err) 91 goto fail; 92 93 /* control debugging printfs */ 94 err = sysctl_createv(clog, 0, &rnode, &cnode, 95 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 96 "debug", SYSCTL_DESCR("Enable debugging output"), 97 NULL, 0, &ohcidebug, sizeof(ohcidebug), CTL_CREATE, CTL_EOL); 98 if (err) 99 goto fail; 100 101 return; 102 fail: 103 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 104 } 105 106 #endif /* OHCI_DEBUG */ 107 #endif /* USB_DEBUG */ 108 109 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ohcidebug,FMT,A,B,C,D) 110 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ohcidebug,N,FMT,A,B,C,D) 111 #define OHCIHIST_FUNC() USBHIST_FUNC() 112 #define OHCIHIST_CALLED(name) USBHIST_CALLED(ohcidebug) 113 114 #if BYTE_ORDER == BIG_ENDIAN 115 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 116 #else 117 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 118 #endif 119 120 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 121 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 122 #define HTOO16(val) O16TOH(val) 123 #define HTOO32(val) O32TOH(val) 124 125 struct ohci_pipe; 126 127 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 128 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 129 130 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 131 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 132 Static void ohci_free_std_locked(ohci_softc_t *, ohci_soft_td_t *); 133 134 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 135 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 136 Static void ohci_free_sitd_locked(ohci_softc_t *, 137 ohci_soft_itd_t *); 138 139 Static usbd_status ohci_alloc_std_chain(ohci_softc_t *, struct usbd_xfer *, 140 int, int); 141 Static void ohci_free_stds(ohci_softc_t *, struct ohci_xfer *); 142 143 Static void ohci_reset_std_chain(ohci_softc_t *, struct usbd_xfer *, 144 int, int, ohci_soft_td_t *, ohci_soft_td_t **); 145 146 Static usbd_status ohci_open(struct usbd_pipe *); 147 Static void ohci_poll(struct usbd_bus *); 148 Static void ohci_softintr(void *); 149 Static void ohci_waitintr(ohci_softc_t *, struct usbd_xfer *); 150 Static void ohci_rhsc(ohci_softc_t *, struct usbd_xfer *); 151 Static void ohci_rhsc_softint(void *); 152 153 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 154 ohci_soft_ed_t *); 155 156 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 157 ohci_soft_ed_t *); 158 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 159 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 160 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 161 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 162 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 163 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 164 165 Static usbd_status ohci_setup_isoc(struct usbd_pipe *); 166 Static void ohci_device_isoc_enter(struct usbd_xfer *); 167 168 Static struct usbd_xfer * 169 ohci_allocx(struct usbd_bus *, unsigned int); 170 Static void ohci_freex(struct usbd_bus *, struct usbd_xfer *); 171 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 172 Static int ohci_roothub_ctrl(struct usbd_bus *, 173 usb_device_request_t *, void *, int); 174 175 Static usbd_status ohci_root_intr_transfer(struct usbd_xfer *); 176 Static usbd_status ohci_root_intr_start(struct usbd_xfer *); 177 Static void ohci_root_intr_abort(struct usbd_xfer *); 178 Static void ohci_root_intr_close(struct usbd_pipe *); 179 Static void ohci_root_intr_done(struct usbd_xfer *); 180 181 Static int ohci_device_ctrl_init(struct usbd_xfer *); 182 Static void ohci_device_ctrl_fini(struct usbd_xfer *); 183 Static usbd_status ohci_device_ctrl_transfer(struct usbd_xfer *); 184 Static usbd_status ohci_device_ctrl_start(struct usbd_xfer *); 185 Static void ohci_device_ctrl_abort(struct usbd_xfer *); 186 Static void ohci_device_ctrl_close(struct usbd_pipe *); 187 Static void ohci_device_ctrl_done(struct usbd_xfer *); 188 189 Static int ohci_device_bulk_init(struct usbd_xfer *); 190 Static void ohci_device_bulk_fini(struct usbd_xfer *); 191 Static usbd_status ohci_device_bulk_transfer(struct usbd_xfer *); 192 Static usbd_status ohci_device_bulk_start(struct usbd_xfer *); 193 Static void ohci_device_bulk_abort(struct usbd_xfer *); 194 Static void ohci_device_bulk_close(struct usbd_pipe *); 195 Static void ohci_device_bulk_done(struct usbd_xfer *); 196 197 Static int ohci_device_intr_init(struct usbd_xfer *); 198 Static void ohci_device_intr_fini(struct usbd_xfer *); 199 Static usbd_status ohci_device_intr_transfer(struct usbd_xfer *); 200 Static usbd_status ohci_device_intr_start(struct usbd_xfer *); 201 Static void ohci_device_intr_abort(struct usbd_xfer *); 202 Static void ohci_device_intr_close(struct usbd_pipe *); 203 Static void ohci_device_intr_done(struct usbd_xfer *); 204 205 Static int ohci_device_isoc_init(struct usbd_xfer *); 206 Static void ohci_device_isoc_fini(struct usbd_xfer *); 207 Static usbd_status ohci_device_isoc_transfer(struct usbd_xfer *); 208 Static usbd_status ohci_device_isoc_start(struct usbd_xfer *); 209 Static void ohci_device_isoc_abort(struct usbd_xfer *); 210 Static void ohci_device_isoc_close(struct usbd_pipe *); 211 Static void ohci_device_isoc_done(struct usbd_xfer *); 212 213 Static usbd_status ohci_device_setintr(ohci_softc_t *, 214 struct ohci_pipe *, int); 215 216 Static void ohci_timeout(void *); 217 Static void ohci_timeout_task(void *); 218 Static void ohci_rhsc_enable(void *); 219 220 Static void ohci_close_pipe(struct usbd_pipe *, ohci_soft_ed_t *); 221 Static void ohci_abort_xfer(struct usbd_xfer *, usbd_status); 222 223 Static void ohci_device_clear_toggle(struct usbd_pipe *); 224 Static void ohci_noop(struct usbd_pipe *); 225 226 #ifdef OHCI_DEBUG 227 Static void ohci_dumpregs(ohci_softc_t *); 228 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 229 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 230 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 231 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 232 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 233 #endif 234 235 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 236 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 237 #define OWRITE1(sc, r, x) \ 238 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 239 #define OWRITE2(sc, r, x) \ 240 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 241 #define OWRITE4(sc, r, x) \ 242 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 243 244 static __inline uint32_t 245 OREAD4(ohci_softc_t *sc, bus_size_t r) 246 { 247 248 OBARR(sc); 249 return bus_space_read_4(sc->iot, sc->ioh, r); 250 } 251 252 /* Reverse the bits in a value 0 .. 31 */ 253 Static uint8_t revbits[OHCI_NO_INTRS] = 254 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 255 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 256 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 257 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 258 259 struct ohci_pipe { 260 struct usbd_pipe pipe; 261 ohci_soft_ed_t *sed; 262 union { 263 ohci_soft_td_t *td; 264 ohci_soft_itd_t *itd; 265 } tail; 266 /* Info needed for different pipe kinds. */ 267 union { 268 /* Control pipe */ 269 struct { 270 usb_dma_t reqdma; 271 } ctrl; 272 /* Interrupt pipe */ 273 struct { 274 int nslots; 275 int pos; 276 } intr; 277 /* Isochronous pipe */ 278 struct isoc { 279 int next, inuse; 280 } isoc; 281 }; 282 }; 283 284 Static const struct usbd_bus_methods ohci_bus_methods = { 285 .ubm_open = ohci_open, 286 .ubm_softint = ohci_softintr, 287 .ubm_dopoll = ohci_poll, 288 .ubm_allocx = ohci_allocx, 289 .ubm_freex = ohci_freex, 290 .ubm_getlock = ohci_get_lock, 291 .ubm_rhctrl = ohci_roothub_ctrl, 292 }; 293 294 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 295 .upm_transfer = ohci_root_intr_transfer, 296 .upm_start = ohci_root_intr_start, 297 .upm_abort = ohci_root_intr_abort, 298 .upm_close = ohci_root_intr_close, 299 .upm_cleartoggle = ohci_noop, 300 .upm_done = ohci_root_intr_done, 301 }; 302 303 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 304 .upm_init = ohci_device_ctrl_init, 305 .upm_fini = ohci_device_ctrl_fini, 306 .upm_transfer = ohci_device_ctrl_transfer, 307 .upm_start = ohci_device_ctrl_start, 308 .upm_abort = ohci_device_ctrl_abort, 309 .upm_close = ohci_device_ctrl_close, 310 .upm_cleartoggle = ohci_noop, 311 .upm_done = ohci_device_ctrl_done, 312 }; 313 314 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 315 .upm_init = ohci_device_intr_init, 316 .upm_fini = ohci_device_intr_fini, 317 .upm_transfer = ohci_device_intr_transfer, 318 .upm_start = ohci_device_intr_start, 319 .upm_abort = ohci_device_intr_abort, 320 .upm_close = ohci_device_intr_close, 321 .upm_cleartoggle = ohci_device_clear_toggle, 322 .upm_done = ohci_device_intr_done, 323 }; 324 325 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 326 .upm_init = ohci_device_bulk_init, 327 .upm_fini = ohci_device_bulk_fini, 328 .upm_transfer = ohci_device_bulk_transfer, 329 .upm_start = ohci_device_bulk_start, 330 .upm_abort = ohci_device_bulk_abort, 331 .upm_close = ohci_device_bulk_close, 332 .upm_cleartoggle = ohci_device_clear_toggle, 333 .upm_done = ohci_device_bulk_done, 334 }; 335 336 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 337 .upm_init = ohci_device_isoc_init, 338 .upm_fini = ohci_device_isoc_fini, 339 .upm_transfer = ohci_device_isoc_transfer, 340 .upm_start = ohci_device_isoc_start, 341 .upm_abort = ohci_device_isoc_abort, 342 .upm_close = ohci_device_isoc_close, 343 .upm_cleartoggle = ohci_noop, 344 .upm_done = ohci_device_isoc_done, 345 }; 346 347 int 348 ohci_activate(device_t self, enum devact act) 349 { 350 struct ohci_softc *sc = device_private(self); 351 352 switch (act) { 353 case DVACT_DEACTIVATE: 354 sc->sc_dying = 1; 355 return 0; 356 default: 357 return EOPNOTSUPP; 358 } 359 } 360 361 void 362 ohci_childdet(device_t self, device_t child) 363 { 364 struct ohci_softc *sc = device_private(self); 365 366 KASSERT(sc->sc_child == child); 367 sc->sc_child = NULL; 368 } 369 370 int 371 ohci_detach(struct ohci_softc *sc, int flags) 372 { 373 int rv = 0; 374 375 if (sc->sc_child != NULL) 376 rv = config_detach(sc->sc_child, flags); 377 378 if (rv != 0) 379 return rv; 380 381 callout_halt(&sc->sc_tmo_rhsc, &sc->sc_lock); 382 383 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 384 callout_destroy(&sc->sc_tmo_rhsc); 385 386 softint_disestablish(sc->sc_rhsc_si); 387 388 cv_destroy(&sc->sc_softwake_cv); 389 390 mutex_destroy(&sc->sc_lock); 391 mutex_destroy(&sc->sc_intr_lock); 392 393 if (sc->sc_hcca != NULL) 394 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 395 pool_cache_destroy(sc->sc_xferpool); 396 397 return rv; 398 } 399 400 ohci_soft_ed_t * 401 ohci_alloc_sed(ohci_softc_t *sc) 402 { 403 ohci_soft_ed_t *sed; 404 usbd_status err; 405 int i, offs; 406 usb_dma_t dma; 407 408 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 409 410 mutex_enter(&sc->sc_lock); 411 if (sc->sc_freeeds == NULL) { 412 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 413 mutex_exit(&sc->sc_lock); 414 415 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 416 OHCI_ED_ALIGN, &dma); 417 if (err) 418 return 0; 419 420 mutex_enter(&sc->sc_lock); 421 for (i = 0; i < OHCI_SED_CHUNK; i++) { 422 offs = i * OHCI_SED_SIZE; 423 sed = KERNADDR(&dma, offs); 424 sed->physaddr = DMAADDR(&dma, offs); 425 sed->dma = dma; 426 sed->offs = offs; 427 sed->next = sc->sc_freeeds; 428 sc->sc_freeeds = sed; 429 } 430 } 431 sed = sc->sc_freeeds; 432 sc->sc_freeeds = sed->next; 433 mutex_exit(&sc->sc_lock); 434 435 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 436 sed->next = 0; 437 return sed; 438 } 439 440 static inline void 441 ohci_free_sed_locked(ohci_softc_t *sc, ohci_soft_ed_t *sed) 442 { 443 444 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 445 446 sed->next = sc->sc_freeeds; 447 sc->sc_freeeds = sed; 448 } 449 450 void 451 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 452 { 453 454 mutex_enter(&sc->sc_lock); 455 ohci_free_sed_locked(sc, sed); 456 mutex_exit(&sc->sc_lock); 457 } 458 459 ohci_soft_td_t * 460 ohci_alloc_std(ohci_softc_t *sc) 461 { 462 ohci_soft_td_t *std; 463 usbd_status err; 464 int i, offs; 465 usb_dma_t dma; 466 467 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 468 469 mutex_enter(&sc->sc_lock); 470 if (sc->sc_freetds == NULL) { 471 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 472 mutex_exit(&sc->sc_lock); 473 474 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 475 OHCI_TD_ALIGN, &dma); 476 if (err) 477 return NULL; 478 479 mutex_enter(&sc->sc_lock); 480 for(i = 0; i < OHCI_STD_CHUNK; i++) { 481 offs = i * OHCI_STD_SIZE; 482 std = KERNADDR(&dma, offs); 483 std->physaddr = DMAADDR(&dma, offs); 484 std->dma = dma; 485 std->offs = offs; 486 std->nexttd = sc->sc_freetds; 487 sc->sc_freetds = std; 488 } 489 } 490 491 std = sc->sc_freetds; 492 sc->sc_freetds = std->nexttd; 493 mutex_exit(&sc->sc_lock); 494 495 memset(&std->td, 0, sizeof(ohci_td_t)); 496 std->nexttd = NULL; 497 std->xfer = NULL; 498 499 return std; 500 } 501 502 void 503 ohci_free_std_locked(ohci_softc_t *sc, ohci_soft_td_t *std) 504 { 505 506 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 507 508 std->nexttd = sc->sc_freetds; 509 sc->sc_freetds = std; 510 } 511 512 void 513 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 514 { 515 516 mutex_enter(&sc->sc_lock); 517 ohci_free_std_locked(sc, std); 518 mutex_exit(&sc->sc_lock); 519 } 520 521 Static usbd_status 522 ohci_alloc_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, int alen, int rd) 523 { 524 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 525 struct usbd_pipe *pipe = xfer->ux_pipe; 526 ohci_soft_td_t *next, *cur; 527 ohci_physaddr_t dataphys, dataphysend; 528 uint32_t tdflags; 529 int len = alen; 530 int curlen; 531 usb_dma_t *dma = &xfer->ux_dmabuf; 532 uint16_t flags = xfer->ux_flags; 533 534 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 535 536 DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d", 537 pipe->up_dev->ud_addr, 538 UE_GET_ADDR(pipe->up_endpoint->ue_edesc->bEndpointAddress), 539 alen, pipe->up_dev->ud_speed); 540 541 ASSERT_SLEEPABLE(); 542 543 size_t nstd = (flags & USBD_FORCE_SHORT_XFER) ? 1 : 0; 544 nstd += ((len + OHCI_PAGE_SIZE - 1) / OHCI_PAGE_SIZE); 545 ox->ox_stds = kmem_zalloc(sizeof(ohci_soft_td_t *) * nstd, 546 KM_SLEEP); 547 ox->ox_nstd = nstd; 548 int mps = UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize); 549 550 DPRINTFN(8, "xfer %p nstd %d mps %d", xfer, nstd, mps, 0); 551 552 len = alen; 553 cur = ohci_alloc_std(sc); 554 if (cur == NULL) 555 goto nomem; 556 557 dataphys = DMAADDR(dma, 0); 558 dataphysend = OHCI_PAGE(dataphys + len - 1); 559 tdflags = HTOO32( 560 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 561 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 562 563 for (size_t j = 0;;) { 564 ox->ox_stds[j++] = cur; 565 next = ohci_alloc_std(sc); 566 if (next == NULL) 567 goto nomem; 568 569 /* The OHCI hardware can handle at most one page crossing. */ 570 if (OHCI_PAGE(dataphys) == dataphysend || 571 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 572 /* we can handle it in this TD */ 573 curlen = len; 574 } else { 575 /* must use multiple TDs, fill as much as possible. */ 576 curlen = 2 * OHCI_PAGE_SIZE - 577 (dataphys & (OHCI_PAGE_SIZE-1)); 578 /* the length must be a multiple of the max size */ 579 curlen -= curlen % mps; 580 KASSERT(curlen != 0); 581 } 582 DPRINTFN(4, "dataphys=0x%08x dataphysend=0x%08x " 583 "len=%d curlen=%d", dataphys, dataphysend, len, curlen); 584 len -= curlen; 585 586 cur->td.td_flags = tdflags; 587 cur->td.td_cbp = HTOO32(dataphys); 588 cur->td.td_nexttd = HTOO32(next->physaddr); 589 cur->td.td_be = HTOO32(dataphys + curlen - 1); 590 cur->nexttd = next; 591 cur->len = curlen; 592 cur->flags = OHCI_ADD_LEN; 593 cur->xfer = xfer; 594 595 DPRINTFN(10, "cbp=0x%08x be=0x%08x", dataphys, 596 dataphys + curlen - 1, 0, 0); 597 if (len == 0) 598 break; 599 DPRINTFN(10, "extend chain", 0, 0, 0, 0); 600 dataphys += curlen; 601 cur = next; 602 } 603 if (!rd && (flags & USBD_FORCE_SHORT_XFER) && 604 alen % mps == 0) { 605 /* Force a 0 length transfer at the end. */ 606 607 cur = next; 608 next = ohci_alloc_std(sc); 609 if (next == NULL) 610 goto nomem; 611 612 cur->td.td_flags = tdflags; 613 cur->td.td_cbp = 0; /* indicate 0 length packet */ 614 cur->td.td_nexttd = HTOO32(next->physaddr); 615 cur->td.td_be = ~0; 616 cur->nexttd = next; 617 cur->len = 0; 618 cur->flags = 0; 619 cur->xfer = xfer; 620 621 DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0); 622 } 623 624 return USBD_NORMAL_COMPLETION; 625 626 nomem: 627 ohci_free_stds(sc, ox); 628 629 return USBD_NOMEM; 630 } 631 632 Static void 633 ohci_free_stds(ohci_softc_t *sc, struct ohci_xfer *ox) 634 { 635 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 636 DPRINTF("ox=%p", ox, 0, 0, 0); 637 638 mutex_enter(&sc->sc_lock); 639 for (size_t i = 0; i < ox->ox_nstd; i++) { 640 ohci_soft_td_t *std = ox->ox_stds[i]; 641 if (std == NULL) 642 break; 643 ohci_free_std_locked(sc, std); 644 } 645 mutex_exit(&sc->sc_lock); 646 } 647 648 void 649 ohci_reset_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, 650 int alen, int rd, ohci_soft_td_t *sp, ohci_soft_td_t **ep) 651 { 652 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 653 ohci_soft_td_t *next, *cur; 654 ohci_physaddr_t dataphys, dataphysend; 655 uint32_t tdflags; 656 int len, curlen; 657 usb_dma_t *dma = &xfer->ux_dmabuf; 658 uint16_t flags = xfer->ux_flags; 659 660 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 661 DPRINTF("start len=%d", alen, 0, 0, 0); 662 663 KASSERT(mutex_owned(&sc->sc_lock)); 664 665 DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d", 666 xfer->ux_pipe->up_dev->ud_addr, 667 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 668 alen, xfer->ux_pipe->up_dev->ud_speed); 669 670 KASSERT(sp); 671 672 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 673 674 len = alen; 675 cur = sp; 676 677 dataphys = DMAADDR(dma, 0); 678 dataphysend = OHCI_PAGE(dataphys + len - 1); 679 usb_syncmem(dma, 0, len, 680 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 681 tdflags = HTOO32( 682 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 683 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 684 685 for (size_t j = 1;;) { 686 if (j == ox->ox_nstd) 687 next = NULL; 688 else 689 next = ox->ox_stds[j++]; 690 KASSERT(next != cur); 691 692 /* The OHCI hardware can handle at most one page crossing. */ 693 if (OHCI_PAGE(dataphys) == dataphysend || 694 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 695 /* we can handle it in this TD */ 696 curlen = len; 697 } else { 698 /* must use multiple TDs, fill as much as possible. */ 699 curlen = 2 * OHCI_PAGE_SIZE - 700 (dataphys & (OHCI_PAGE_SIZE - 1)); 701 /* the length must be a multiple of the max size */ 702 curlen -= curlen % mps; 703 KASSERT(curlen != 0); 704 } 705 DPRINTFN(4, "dataphys=0x%08x dataphysend=0x%08x " 706 "len=%d curlen=%d", dataphys, dataphysend, len, curlen); 707 len -= curlen; 708 709 cur->td.td_flags = tdflags; 710 cur->td.td_cbp = HTOO32(dataphys); 711 cur->td.td_be = HTOO32(dataphys + curlen - 1); 712 cur->td.td_nexttd = (next != NULL) ? HTOO32(next->physaddr) : 0; 713 cur->nexttd = next; 714 cur->len = curlen; 715 cur->flags = OHCI_ADD_LEN; 716 cur->xfer = xfer; 717 ohci_hash_add_td(sc, cur); 718 719 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 720 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 721 DPRINTFN(10, "cbp=0x%08x be=0x%08x", dataphys, 722 dataphys + curlen - 1, 0, 0); 723 if (len == 0) 724 break; 725 KASSERT(next != NULL); 726 DPRINTFN(10, "extend chain", 0, 0, 0, 0); 727 dataphys += curlen; 728 cur = next; 729 } 730 cur->td.td_flags |= 731 (xfer->ux_flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0); 732 733 if (!rd && 734 (flags & USBD_FORCE_SHORT_XFER) && 735 alen % mps == 0) { 736 /* Force a 0 length transfer at the end. */ 737 738 KASSERT(next != NULL); 739 cur = next; 740 741 cur->td.td_flags = tdflags; 742 cur->td.td_cbp = 0; /* indicate 0 length packet */ 743 cur->td.td_nexttd = HTOO32(next->physaddr); 744 cur->td.td_be = ~0; 745 cur->nexttd = NULL; 746 cur->len = 0; 747 cur->flags = 0; 748 cur->xfer = xfer; 749 ohci_hash_add_td(sc, cur); 750 751 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 752 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 753 DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0); 754 } 755 *ep = cur; 756 } 757 758 ohci_soft_itd_t * 759 ohci_alloc_sitd(ohci_softc_t *sc) 760 { 761 ohci_soft_itd_t *sitd; 762 usbd_status err; 763 int i, offs; 764 usb_dma_t dma; 765 766 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 767 768 mutex_enter(&sc->sc_lock); 769 if (sc->sc_freeitds == NULL) { 770 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 771 mutex_exit(&sc->sc_lock); 772 773 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 774 OHCI_ITD_ALIGN, &dma); 775 if (err) 776 return NULL; 777 mutex_enter(&sc->sc_lock); 778 for(i = 0; i < OHCI_SITD_CHUNK; i++) { 779 offs = i * OHCI_SITD_SIZE; 780 sitd = KERNADDR(&dma, offs); 781 sitd->physaddr = DMAADDR(&dma, offs); 782 sitd->dma = dma; 783 sitd->offs = offs; 784 sitd->nextitd = sc->sc_freeitds; 785 sc->sc_freeitds = sitd; 786 } 787 } 788 789 sitd = sc->sc_freeitds; 790 sc->sc_freeitds = sitd->nextitd; 791 mutex_exit(&sc->sc_lock); 792 793 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 794 sitd->nextitd = NULL; 795 sitd->xfer = NULL; 796 797 #ifdef DIAGNOSTIC 798 sitd->isdone = true; 799 #endif 800 801 return sitd; 802 } 803 804 Static void 805 ohci_free_sitd_locked(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 806 { 807 808 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 809 DPRINTFN(10, "sitd=%p", sitd, 0, 0, 0); 810 811 KASSERT(sitd->isdone); 812 #ifdef DIAGNOSTIC 813 /* Warn double free */ 814 sitd->isdone = false; 815 #endif 816 817 sitd->nextitd = sc->sc_freeitds; 818 sc->sc_freeitds = sitd; 819 } 820 821 void 822 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 823 { 824 825 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 826 827 mutex_enter(&sc->sc_lock); 828 ohci_free_sitd_locked(sc, sitd); 829 mutex_exit(&sc->sc_lock); 830 } 831 832 int 833 ohci_init(ohci_softc_t *sc) 834 { 835 ohci_soft_ed_t *sed, *psed; 836 usbd_status err; 837 int i; 838 uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */; 839 840 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 841 842 aprint_normal_dev(sc->sc_dev, ""); 843 844 sc->sc_hcca = NULL; 845 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 846 847 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 848 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 849 cv_init(&sc->sc_softwake_cv, "ohciab"); 850 851 sc->sc_rhsc_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 852 ohci_rhsc_softint, sc); 853 854 for (i = 0; i < OHCI_HASH_SIZE; i++) 855 LIST_INIT(&sc->sc_hash_tds[i]); 856 for (i = 0; i < OHCI_HASH_SIZE; i++) 857 LIST_INIT(&sc->sc_hash_itds[i]); 858 859 sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0, 860 "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL); 861 862 rev = OREAD4(sc, OHCI_REVISION); 863 aprint_normal("OHCI version %d.%d%s\n", 864 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 865 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 866 867 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 868 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 869 sc->sc_bus.ub_revision = USBREV_UNKNOWN; 870 return -1; 871 } 872 sc->sc_bus.ub_revision = USBREV_1_0; 873 sc->sc_bus.ub_usedma = true; 874 875 /* XXX determine alignment by R/W */ 876 /* Allocate the HCCA area. */ 877 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 878 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 879 if (err) { 880 sc->sc_hcca = NULL; 881 return err; 882 } 883 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 884 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 885 886 sc->sc_eintrs = OHCI_NORMAL_INTRS; 887 888 /* Allocate dummy ED that starts the control list. */ 889 sc->sc_ctrl_head = ohci_alloc_sed(sc); 890 if (sc->sc_ctrl_head == NULL) { 891 err = ENOMEM; 892 goto bad1; 893 } 894 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 895 896 /* Allocate dummy ED that starts the bulk list. */ 897 sc->sc_bulk_head = ohci_alloc_sed(sc); 898 if (sc->sc_bulk_head == NULL) { 899 err = ENOMEM; 900 goto bad2; 901 } 902 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 903 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 904 sizeof(sc->sc_bulk_head->ed), 905 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 906 907 /* Allocate dummy ED that starts the isochronous list. */ 908 sc->sc_isoc_head = ohci_alloc_sed(sc); 909 if (sc->sc_isoc_head == NULL) { 910 err = ENOMEM; 911 goto bad3; 912 } 913 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 914 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 915 sizeof(sc->sc_isoc_head->ed), 916 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 917 918 /* Allocate all the dummy EDs that make up the interrupt tree. */ 919 for (i = 0; i < OHCI_NO_EDS; i++) { 920 sed = ohci_alloc_sed(sc); 921 if (sed == NULL) { 922 while (--i >= 0) 923 ohci_free_sed(sc, sc->sc_eds[i]); 924 err = ENOMEM; 925 goto bad4; 926 } 927 /* All ED fields are set to 0. */ 928 sc->sc_eds[i] = sed; 929 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 930 if (i != 0) 931 psed = sc->sc_eds[(i-1) / 2]; 932 else 933 psed= sc->sc_isoc_head; 934 sed->next = psed; 935 sed->ed.ed_nexted = HTOO32(psed->physaddr); 936 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 937 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 938 } 939 /* 940 * Fill HCCA interrupt table. The bit reversal is to get 941 * the tree set up properly to spread the interrupts. 942 */ 943 for (i = 0; i < OHCI_NO_INTRS; i++) 944 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 945 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 946 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 947 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 948 949 #ifdef OHCI_DEBUG 950 DPRINTFN(15, "--- dump start ---", 0, 0, 0 ,0); 951 if (ohcidebug >= 15) { 952 for (i = 0; i < OHCI_NO_EDS; i++) { 953 DPRINTFN(15, "ed#%d ", i, 0, 0, 0); 954 ohci_dump_ed(sc, sc->sc_eds[i]); 955 } 956 DPRINTFN(15, "iso", 0, 0, 0 ,0); 957 ohci_dump_ed(sc, sc->sc_isoc_head); 958 } 959 DPRINTFN(15, "--- dump end ---", 0, 0, 0 ,0); 960 #endif 961 962 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 963 ctl = OREAD4(sc, OHCI_CONTROL); 964 rwc = ctl & OHCI_RWC; 965 fm = OREAD4(sc, OHCI_FM_INTERVAL); 966 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 967 /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */ 968 969 /* Determine in what context we are running. */ 970 if (ctl & OHCI_IR) { 971 /* SMM active, request change */ 972 DPRINTF("SMM active, request owner change", 0, 0, 0, 0); 973 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 974 (OHCI_OC | OHCI_MIE)) 975 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 976 s = OREAD4(sc, OHCI_COMMAND_STATUS); 977 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 978 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 979 usb_delay_ms(&sc->sc_bus, 1); 980 ctl = OREAD4(sc, OHCI_CONTROL); 981 } 982 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 983 if ((ctl & OHCI_IR) == 0) { 984 aprint_error_dev(sc->sc_dev, 985 "SMM does not respond, resetting\n"); 986 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 987 goto reset; 988 } 989 #if 0 990 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 991 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 992 /* BIOS started controller. */ 993 DPRINTF("BIOS active", 0, 0, 0, 0); 994 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 995 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 996 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 997 } 998 #endif 999 } else { 1000 DPRINTF("cold started", 0 ,0 ,0 ,0); 1001 reset: 1002 /* Controller was cold started. */ 1003 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 1004 } 1005 1006 /* 1007 * This reset should not be necessary according to the OHCI spec, but 1008 * without it some controllers do not start. 1009 */ 1010 DPRINTF("sc %p: resetting", sc, 0, 0, 0); 1011 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 1012 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 1013 1014 /* We now own the host controller and the bus has been reset. */ 1015 1016 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 1017 /* Nominal time for a reset is 10 us. */ 1018 for (i = 0; i < 10; i++) { 1019 delay(10); 1020 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 1021 if (!hcr) 1022 break; 1023 } 1024 if (hcr) { 1025 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 1026 err = EIO; 1027 goto bad5; 1028 } 1029 #ifdef OHCI_DEBUG 1030 if (ohcidebug >= 15) 1031 ohci_dumpregs(sc); 1032 #endif 1033 1034 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 1035 1036 /* Set up HC registers. */ 1037 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1038 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 1039 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 1040 /* disable all interrupts and then switch on all desired interrupts */ 1041 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 1042 /* switch on desired functional features */ 1043 ctl = OREAD4(sc, OHCI_CONTROL); 1044 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 1045 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 1046 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 1047 /* And finally start it! */ 1048 OWRITE4(sc, OHCI_CONTROL, ctl); 1049 1050 /* 1051 * The controller is now OPERATIONAL. Set a some final 1052 * registers that should be set earlier, but that the 1053 * controller ignores when in the SUSPEND state. 1054 */ 1055 ival = OHCI_GET_IVAL(fm); 1056 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 1057 fm |= OHCI_FSMPS(ival) | ival; 1058 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 1059 per = OHCI_PERIODIC(ival); /* 90% periodic */ 1060 OWRITE4(sc, OHCI_PERIODIC_START, per); 1061 1062 if (sc->sc_flags & OHCIF_SUPERIO) { 1063 /* no overcurrent protection */ 1064 desca |= OHCI_NOCP; 1065 /* 1066 * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning 1067 * that 1068 * - ports are always power switched 1069 * - don't wait for powered root hub port 1070 */ 1071 desca &= ~(__SHIFTIN(0xff, OHCI_POTPGT_MASK) | OHCI_NPS); 1072 } 1073 1074 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 1075 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 1076 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 1077 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 1078 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 1079 1080 /* 1081 * The AMD756 requires a delay before re-reading the register, 1082 * otherwise it will occasionally report 0 ports. 1083 */ 1084 sc->sc_noport = 0; 1085 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 1086 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 1087 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 1088 } 1089 1090 #ifdef OHCI_DEBUG 1091 if (ohcidebug >= 5) 1092 ohci_dumpregs(sc); 1093 #endif 1094 1095 /* Set up the bus struct. */ 1096 sc->sc_bus.ub_methods = &ohci_bus_methods; 1097 sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe); 1098 1099 sc->sc_control = sc->sc_intre = 0; 1100 1101 /* Finally, turn on interrupts. */ 1102 DPRINTF("enabling %#x", sc->sc_eintrs | OHCI_MIE, 0, 0, 0); 1103 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 1104 1105 return 0; 1106 1107 bad5: 1108 for (i = 0; i < OHCI_NO_EDS; i++) 1109 ohci_free_sed(sc, sc->sc_eds[i]); 1110 bad4: 1111 ohci_free_sed(sc, sc->sc_isoc_head); 1112 bad3: 1113 ohci_free_sed(sc, sc->sc_bulk_head); 1114 bad2: 1115 ohci_free_sed(sc, sc->sc_ctrl_head); 1116 bad1: 1117 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 1118 sc->sc_hcca = NULL; 1119 return err; 1120 } 1121 1122 struct usbd_xfer * 1123 ohci_allocx(struct usbd_bus *bus, unsigned int nframes) 1124 { 1125 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1126 struct usbd_xfer *xfer; 1127 1128 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1129 if (xfer != NULL) { 1130 memset(xfer, 0, sizeof(struct ohci_xfer)); 1131 #ifdef DIAGNOSTIC 1132 xfer->ux_state = XFER_BUSY; 1133 #endif 1134 } 1135 return xfer; 1136 } 1137 1138 void 1139 ohci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1140 { 1141 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1142 1143 KASSERTMSG(xfer->ux_state == XFER_BUSY, 1144 "xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state); 1145 #ifdef DIAGNOSTIC 1146 xfer->ux_state = XFER_FREE; 1147 #endif 1148 pool_cache_put(sc->sc_xferpool, xfer); 1149 } 1150 1151 Static void 1152 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1153 { 1154 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1155 1156 *lock = &sc->sc_lock; 1157 } 1158 1159 /* 1160 * Shut down the controller when the system is going down. 1161 */ 1162 bool 1163 ohci_shutdown(device_t self, int flags) 1164 { 1165 ohci_softc_t *sc = device_private(self); 1166 1167 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1168 1169 DPRINTF("stopping the HC", 0, 0, 0, 0); 1170 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1171 return true; 1172 } 1173 1174 bool 1175 ohci_resume(device_t dv, const pmf_qual_t *qual) 1176 { 1177 ohci_softc_t *sc = device_private(dv); 1178 uint32_t ctl; 1179 1180 mutex_spin_enter(&sc->sc_intr_lock); 1181 sc->sc_bus.ub_usepolling++; 1182 mutex_spin_exit(&sc->sc_intr_lock); 1183 1184 /* Some broken BIOSes do not recover these values */ 1185 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1186 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1187 sc->sc_ctrl_head->physaddr); 1188 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1189 sc->sc_bulk_head->physaddr); 1190 if (sc->sc_intre) 1191 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1192 (OHCI_ALL_INTRS | OHCI_MIE)); 1193 if (sc->sc_control) 1194 ctl = sc->sc_control; 1195 else 1196 ctl = OREAD4(sc, OHCI_CONTROL); 1197 ctl |= OHCI_HCFS_RESUME; 1198 OWRITE4(sc, OHCI_CONTROL, ctl); 1199 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1200 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1201 OWRITE4(sc, OHCI_CONTROL, ctl); 1202 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1203 sc->sc_control = sc->sc_intre = 0; 1204 1205 mutex_spin_enter(&sc->sc_intr_lock); 1206 sc->sc_bus.ub_usepolling--; 1207 mutex_spin_exit(&sc->sc_intr_lock); 1208 1209 return true; 1210 } 1211 1212 bool 1213 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1214 { 1215 ohci_softc_t *sc = device_private(dv); 1216 uint32_t ctl; 1217 1218 mutex_spin_enter(&sc->sc_intr_lock); 1219 sc->sc_bus.ub_usepolling++; 1220 mutex_spin_exit(&sc->sc_intr_lock); 1221 1222 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1223 if (sc->sc_control == 0) { 1224 /* 1225 * Preserve register values, in case that BIOS 1226 * does not recover them. 1227 */ 1228 sc->sc_control = ctl; 1229 sc->sc_intre = OREAD4(sc, 1230 OHCI_INTERRUPT_ENABLE); 1231 } 1232 ctl |= OHCI_HCFS_SUSPEND; 1233 OWRITE4(sc, OHCI_CONTROL, ctl); 1234 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1235 1236 mutex_spin_enter(&sc->sc_intr_lock); 1237 sc->sc_bus.ub_usepolling--; 1238 mutex_spin_exit(&sc->sc_intr_lock); 1239 1240 return true; 1241 } 1242 1243 #ifdef OHCI_DEBUG 1244 void 1245 ohci_dumpregs(ohci_softc_t *sc) 1246 { 1247 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1248 1249 DPRINTF("rev=0x%08x control=0x%08x command=0x%08x", 1250 OREAD4(sc, OHCI_REVISION), 1251 OREAD4(sc, OHCI_CONTROL), 1252 OREAD4(sc, OHCI_COMMAND_STATUS), 0); 1253 DPRINTF(" intrstat=0x%08x intre=0x%08x intrd=0x%08x", 1254 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1255 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1256 OREAD4(sc, OHCI_INTERRUPT_DISABLE), 0); 1257 DPRINTF(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x", 1258 OREAD4(sc, OHCI_HCCA), 1259 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1260 OREAD4(sc, OHCI_CONTROL_HEAD_ED), 0); 1261 DPRINTF(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x", 1262 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1263 OREAD4(sc, OHCI_BULK_HEAD_ED), 1264 OREAD4(sc, OHCI_BULK_CURRENT_ED) ,0); 1265 DPRINTF(" done=0x%08x fmival=0x%08x fmrem=0x%08x", 1266 OREAD4(sc, OHCI_DONE_HEAD), 1267 OREAD4(sc, OHCI_FM_INTERVAL), 1268 OREAD4(sc, OHCI_FM_REMAINING), 0); 1269 DPRINTF(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x", 1270 OREAD4(sc, OHCI_FM_NUMBER), 1271 OREAD4(sc, OHCI_PERIODIC_START), 1272 OREAD4(sc, OHCI_LS_THRESHOLD), 0); 1273 DPRINTF(" desca=0x%08x descb=0x%08x stat=0x%08x", 1274 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1275 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1276 OREAD4(sc, OHCI_RH_STATUS), 0); 1277 DPRINTF(" port1=0x%08x port2=0x%08x", 1278 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1279 OREAD4(sc, OHCI_RH_PORT_STATUS(2)), 0, 0); 1280 DPRINTF(" HCCA: frame_number=0x%04x done_head=0x%08x", 1281 O32TOH(sc->sc_hcca->hcca_frame_number), 1282 O32TOH(sc->sc_hcca->hcca_done_head), 0, 0); 1283 } 1284 #endif 1285 1286 Static int ohci_intr1(ohci_softc_t *); 1287 1288 int 1289 ohci_intr(void *p) 1290 { 1291 ohci_softc_t *sc = p; 1292 int ret = 0; 1293 1294 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1295 1296 if (sc == NULL) 1297 return 0; 1298 1299 mutex_spin_enter(&sc->sc_intr_lock); 1300 1301 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1302 goto done; 1303 1304 /* If we get an interrupt while polling, then just ignore it. */ 1305 if (sc->sc_bus.ub_usepolling) { 1306 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1307 /* for level triggered intrs, should do something to ack */ 1308 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1309 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1310 1311 goto done; 1312 } 1313 1314 ret = ohci_intr1(sc); 1315 1316 done: 1317 mutex_spin_exit(&sc->sc_intr_lock); 1318 return ret; 1319 } 1320 1321 Static int 1322 ohci_intr1(ohci_softc_t *sc) 1323 { 1324 uint32_t intrs, eintrs; 1325 1326 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1327 1328 /* In case the interrupt occurs before initialization has completed. */ 1329 if (sc == NULL || sc->sc_hcca == NULL) { 1330 #ifdef DIAGNOSTIC 1331 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1332 #endif 1333 return 0; 1334 } 1335 1336 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1337 1338 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1339 if (!intrs) 1340 return 0; 1341 1342 /* Acknowledge */ 1343 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); 1344 eintrs = intrs & sc->sc_eintrs; 1345 DPRINTFN(7, "sc=%p", sc, 0, 0, 0); 1346 DPRINTFN(7, "intrs=%#x(%#x) eintrs=%#x(%#x)", 1347 intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), eintrs, 1348 sc->sc_eintrs); 1349 1350 if (!eintrs) { 1351 return 0; 1352 } 1353 1354 if (eintrs & OHCI_SO) { 1355 sc->sc_overrun_cnt++; 1356 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1357 printf("%s: %u scheduling overruns\n", 1358 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1359 sc->sc_overrun_cnt = 0; 1360 } 1361 /* XXX do what */ 1362 eintrs &= ~OHCI_SO; 1363 } 1364 if (eintrs & OHCI_WDH) { 1365 /* 1366 * We block the interrupt below, and reenable it later from 1367 * ohci_softintr(). 1368 */ 1369 usb_schedsoftintr(&sc->sc_bus); 1370 } 1371 if (eintrs & OHCI_RD) { 1372 DPRINTFN(5, "resume detect", sc, 0, 0, 0); 1373 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1374 /* XXX process resume detect */ 1375 } 1376 if (eintrs & OHCI_UE) { 1377 DPRINTFN(5, "unrecoverable error", sc, 0, 0, 0); 1378 printf("%s: unrecoverable error, controller halted\n", 1379 device_xname(sc->sc_dev)); 1380 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1381 /* XXX what else */ 1382 } 1383 if (eintrs & OHCI_RHSC) { 1384 /* 1385 * We block the interrupt below, and reenable it later from 1386 * a timeout. 1387 */ 1388 softint_schedule(sc->sc_rhsc_si); 1389 } 1390 1391 if (eintrs != 0) { 1392 /* Block unprocessed interrupts. */ 1393 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1394 sc->sc_eintrs &= ~eintrs; 1395 DPRINTF("sc %p blocking intrs 0x%x", sc, eintrs, 0, 0); 1396 } 1397 1398 return 1; 1399 } 1400 1401 void 1402 ohci_rhsc_enable(void *v_sc) 1403 { 1404 ohci_softc_t *sc = v_sc; 1405 1406 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1407 DPRINTF("sc %p", sc, 0, 0, 0); 1408 mutex_spin_enter(&sc->sc_intr_lock); 1409 sc->sc_eintrs |= OHCI_RHSC; 1410 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1411 mutex_spin_exit(&sc->sc_intr_lock); 1412 } 1413 1414 #ifdef OHCI_DEBUG 1415 const char *ohci_cc_strs[] = { 1416 "NO_ERROR", 1417 "CRC", 1418 "BIT_STUFFING", 1419 "DATA_TOGGLE_MISMATCH", 1420 "STALL", 1421 "DEVICE_NOT_RESPONDING", 1422 "PID_CHECK_FAILURE", 1423 "UNEXPECTED_PID", 1424 "DATA_OVERRUN", 1425 "DATA_UNDERRUN", 1426 "BUFFER_OVERRUN", 1427 "BUFFER_UNDERRUN", 1428 "reserved", 1429 "reserved", 1430 "NOT_ACCESSED", 1431 "NOT_ACCESSED", 1432 }; 1433 #endif 1434 1435 void 1436 ohci_softintr(void *v) 1437 { 1438 struct usbd_bus *bus = v; 1439 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1440 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1441 ohci_soft_td_t *std, *sdone, *stdnext; 1442 struct usbd_xfer *xfer; 1443 struct ohci_pipe *opipe; 1444 int len, cc; 1445 int i, j, actlen, iframes, uedir; 1446 ohci_physaddr_t done; 1447 1448 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1449 1450 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1451 1452 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1453 sizeof(sc->sc_hcca->hcca_done_head), 1454 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1455 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1456 sc->sc_hcca->hcca_done_head = 0; 1457 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1458 sizeof(sc->sc_hcca->hcca_done_head), 1459 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1460 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1461 sc->sc_eintrs |= OHCI_WDH; 1462 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1463 1464 /* Reverse the done list. */ 1465 for (sdone = NULL, sidone = NULL; done != 0; ) { 1466 std = ohci_hash_find_td(sc, done); 1467 if (std != NULL) { 1468 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1469 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1470 std->dnext = sdone; 1471 done = O32TOH(std->td.td_nexttd); 1472 sdone = std; 1473 DPRINTFN(10, "add TD %p", std, 0, 0, 0); 1474 continue; 1475 } 1476 sitd = ohci_hash_find_itd(sc, done); 1477 if (sitd != NULL) { 1478 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1479 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1480 sitd->dnext = sidone; 1481 done = O32TOH(sitd->itd.itd_nextitd); 1482 sidone = sitd; 1483 DPRINTFN(5, "add ITD %p", sitd, 0, 0, 0); 1484 continue; 1485 } 1486 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1487 (u_long)done); 1488 break; 1489 } 1490 1491 DPRINTFN(10, "sdone=%p sidone=%p", sdone, sidone, 0, 0); 1492 DPRINTFN(10, "--- TD dump start ---", 0, 0, 0, 0); 1493 #ifdef OHCI_DEBUG 1494 if (ohcidebug >= 10) { 1495 for (std = sdone; std; std = std->dnext) 1496 ohci_dump_td(sc, std); 1497 } 1498 #endif 1499 DPRINTFN(10, "--- TD dump end ---", 0, 0, 0, 0); 1500 1501 for (std = sdone; std; std = stdnext) { 1502 xfer = std->xfer; 1503 stdnext = std->dnext; 1504 DPRINTFN(10, "std=%p xfer=%p hcpriv=%p", std, xfer, 1505 xfer ? xfer->ux_hcpriv : 0, 0); 1506 if (xfer == NULL) { 1507 /* 1508 * xfer == NULL: There seems to be no xfer associated 1509 * with this TD. It is tailp that happened to end up on 1510 * the done queue. 1511 * Shouldn't happen, but some chips are broken(?). 1512 */ 1513 continue; 1514 } 1515 if (xfer->ux_status == USBD_CANCELLED || 1516 xfer->ux_status == USBD_TIMEOUT) { 1517 DPRINTF("cancel/timeout %p", xfer, 0, 0, 0); 1518 /* Handled by abort routine. */ 1519 continue; 1520 } 1521 callout_stop(&xfer->ux_callout); 1522 1523 len = std->len; 1524 if (std->td.td_cbp != 0) 1525 len -= O32TOH(std->td.td_be) - 1526 O32TOH(std->td.td_cbp) + 1; 1527 DPRINTFN(10, "len=%d, flags=0x%x", len, std->flags, 0, 0); 1528 if (std->flags & OHCI_ADD_LEN) 1529 xfer->ux_actlen += len; 1530 1531 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1532 if (cc == OHCI_CC_NO_ERROR) { 1533 ohci_hash_rem_td(sc, std); 1534 if (std->flags & OHCI_CALL_DONE) { 1535 xfer->ux_status = USBD_NORMAL_COMPLETION; 1536 usb_transfer_complete(xfer); 1537 } 1538 } else { 1539 /* 1540 * Endpoint is halted. First unlink all the TDs 1541 * belonging to the failed transfer, and then restart 1542 * the endpoint. 1543 */ 1544 ohci_soft_td_t *p, *n; 1545 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1546 1547 DPRINTFN(10, "error cc=%d", cc, 0, 0, 0); 1548 1549 /* remove xfer's TDs from the hash */ 1550 for (p = std; p->xfer == xfer; p = n) { 1551 n = p->nexttd; 1552 ohci_hash_rem_td(sc, p); 1553 } 1554 1555 ohci_soft_ed_t *sed = opipe->sed; 1556 1557 /* clear halt and TD chain */ 1558 sed->ed.ed_headp = HTOO32(p->physaddr); 1559 usb_syncmem(&sed->dma, 1560 sed->offs + offsetof(ohci_ed_t, ed_headp), 1561 sizeof(sed->ed.ed_headp), 1562 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1563 1564 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1565 1566 if (cc == OHCI_CC_DATA_UNDERRUN) 1567 xfer->ux_status = USBD_NORMAL_COMPLETION; 1568 else if (cc == OHCI_CC_STALL) 1569 xfer->ux_status = USBD_STALLED; 1570 else 1571 xfer->ux_status = USBD_IOERROR; 1572 usb_transfer_complete(xfer); 1573 } 1574 } 1575 DPRINTFN(10, "--- ITD dump start ---", 0, 0, 0, 0); 1576 #ifdef OHCI_DEBUG 1577 if (ohcidebug >= 10) { 1578 for (sitd = sidone; sitd; sitd = sitd->dnext) 1579 ohci_dump_itd(sc, sitd); 1580 } 1581 #endif 1582 DPRINTFN(10, "--- ITD dump end ---", 0, 0, 0, 0); 1583 1584 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1585 xfer = sitd->xfer; 1586 sitdnext = sitd->dnext; 1587 DPRINTFN(1, "sitd=%p xfer=%p hcpriv=%p", sitd, xfer, 1588 xfer ? xfer->ux_hcpriv : 0, 0); 1589 if (xfer == NULL) 1590 continue; 1591 if (xfer->ux_status == USBD_CANCELLED || 1592 xfer->ux_status == USBD_TIMEOUT) { 1593 DPRINTF("cancel/timeout %p", xfer, 0, 0, 0); 1594 /* Handled by abort routine. */ 1595 continue; 1596 } 1597 KASSERT(!sitd->isdone); 1598 #ifdef DIAGNOSTIC 1599 sitd->isdone = true; 1600 #endif 1601 if (sitd->flags & OHCI_CALL_DONE) { 1602 ohci_soft_itd_t *next; 1603 1604 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1605 opipe->isoc.inuse -= xfer->ux_nframes; 1606 uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc-> 1607 bEndpointAddress); 1608 xfer->ux_status = USBD_NORMAL_COMPLETION; 1609 actlen = 0; 1610 for (i = 0, sitd = xfer->ux_hcpriv;; 1611 sitd = next) { 1612 next = sitd->nextitd; 1613 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1614 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1615 xfer->ux_status = USBD_IOERROR; 1616 /* For input, update frlengths with actual */ 1617 /* XXX anything necessary for output? */ 1618 if (uedir == UE_DIR_IN && 1619 xfer->ux_status == USBD_NORMAL_COMPLETION) { 1620 iframes = OHCI_ITD_GET_FC(O32TOH( 1621 sitd->itd.itd_flags)); 1622 for (j = 0; j < iframes; i++, j++) { 1623 len = O16TOH(sitd-> 1624 itd.itd_offset[j]); 1625 if ((OHCI_ITD_PSW_GET_CC(len) & 1626 OHCI_CC_NOT_ACCESSED_MASK) 1627 == OHCI_CC_NOT_ACCESSED) 1628 len = 0; 1629 else 1630 len = OHCI_ITD_PSW_LENGTH(len); 1631 xfer->ux_frlengths[i] = len; 1632 actlen += len; 1633 } 1634 } 1635 if (sitd->flags & OHCI_CALL_DONE) 1636 break; 1637 ohci_hash_rem_itd(sc, sitd); 1638 1639 } 1640 ohci_hash_rem_itd(sc, sitd); 1641 if (uedir == UE_DIR_IN && 1642 xfer->ux_status == USBD_NORMAL_COMPLETION) 1643 xfer->ux_actlen = actlen; 1644 xfer->ux_hcpriv = NULL; 1645 1646 usb_transfer_complete(xfer); 1647 } 1648 } 1649 1650 if (sc->sc_softwake) { 1651 sc->sc_softwake = 0; 1652 cv_broadcast(&sc->sc_softwake_cv); 1653 } 1654 1655 DPRINTFN(10, "done", 0, 0, 0, 0); 1656 } 1657 1658 void 1659 ohci_device_ctrl_done(struct usbd_xfer *xfer) 1660 { 1661 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1662 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1663 int len = UGETW(xfer->ux_request.wLength); 1664 int isread = (xfer->ux_request.bmRequestType & UT_READ); 1665 1666 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1667 DPRINTFN(10, "xfer=%p", xfer, 0, 0, 0); 1668 1669 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1670 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 1671 1672 if (len) 1673 usb_syncmem(&xfer->ux_dmabuf, 0, len, 1674 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1675 usb_syncmem(&opipe->ctrl.reqdma, 0, 1676 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1677 } 1678 1679 void 1680 ohci_device_intr_done(struct usbd_xfer *xfer) 1681 { 1682 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1683 int isread = 1684 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1685 1686 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1687 DPRINTFN(10, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0); 1688 1689 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1690 1691 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1692 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1693 } 1694 1695 void 1696 ohci_device_bulk_done(struct usbd_xfer *xfer) 1697 { 1698 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1699 1700 int isread = 1701 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1702 1703 KASSERT(mutex_owned(&sc->sc_lock)); 1704 1705 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1706 DPRINTFN(10, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0); 1707 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1708 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1709 } 1710 1711 Static void 1712 ohci_rhsc_softint(void *arg) 1713 { 1714 ohci_softc_t *sc = arg; 1715 1716 mutex_enter(&sc->sc_lock); 1717 1718 ohci_rhsc(sc, sc->sc_intrxfer); 1719 1720 /* Do not allow RHSC interrupts > 1 per second */ 1721 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1722 1723 mutex_exit(&sc->sc_lock); 1724 } 1725 1726 void 1727 ohci_rhsc(ohci_softc_t *sc, struct usbd_xfer *xfer) 1728 { 1729 u_char *p; 1730 int i, m; 1731 int hstatus __unused; 1732 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1733 1734 KASSERT(mutex_owned(&sc->sc_lock)); 1735 1736 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1737 DPRINTF("sc=%p xfer=%p hstatus=0x%08x", sc, xfer, hstatus, 0); 1738 1739 if (xfer == NULL) { 1740 /* Just ignore the change. */ 1741 return; 1742 } 1743 1744 p = xfer->ux_buf; 1745 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 1746 memset(p, 0, xfer->ux_length); 1747 for (i = 1; i <= m; i++) { 1748 /* Pick out CHANGE bits from the status reg. */ 1749 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1750 p[i/8] |= 1 << (i%8); 1751 } 1752 DPRINTF("change=0x%02x", *p, 0, 0, 0); 1753 xfer->ux_actlen = xfer->ux_length; 1754 xfer->ux_status = USBD_NORMAL_COMPLETION; 1755 1756 usb_transfer_complete(xfer); 1757 } 1758 1759 void 1760 ohci_root_intr_done(struct usbd_xfer *xfer) 1761 { 1762 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1763 1764 KASSERT(mutex_owned(&sc->sc_lock)); 1765 1766 KASSERT(sc->sc_intrxfer == xfer); 1767 sc->sc_intrxfer = NULL; 1768 } 1769 1770 /* 1771 * Wait here until controller claims to have an interrupt. 1772 * Then call ohci_intr and return. Use timeout to avoid waiting 1773 * too long. 1774 */ 1775 void 1776 ohci_waitintr(ohci_softc_t *sc, struct usbd_xfer *xfer) 1777 { 1778 int timo; 1779 uint32_t intrs; 1780 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1781 1782 mutex_enter(&sc->sc_lock); 1783 1784 xfer->ux_status = USBD_IN_PROGRESS; 1785 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1786 usb_delay_ms(&sc->sc_bus, 1); 1787 if (sc->sc_dying) 1788 break; 1789 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 1790 DPRINTFN(15, "intrs 0x%04x", intrs, 0, 0, 0); 1791 #ifdef OHCI_DEBUG 1792 if (ohcidebug > 15) 1793 ohci_dumpregs(sc); 1794 #endif 1795 if (intrs) { 1796 mutex_spin_enter(&sc->sc_intr_lock); 1797 ohci_intr1(sc); 1798 mutex_spin_exit(&sc->sc_intr_lock); 1799 if (xfer->ux_status != USBD_IN_PROGRESS) 1800 goto done; 1801 } 1802 } 1803 1804 /* Timeout */ 1805 DPRINTF("timeout", 0, 0, 0, 0); 1806 xfer->ux_status = USBD_TIMEOUT; 1807 usb_transfer_complete(xfer); 1808 1809 done: 1810 mutex_exit(&sc->sc_lock); 1811 } 1812 1813 void 1814 ohci_poll(struct usbd_bus *bus) 1815 { 1816 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1817 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1818 1819 #ifdef OHCI_DEBUG 1820 static int last; 1821 int new; 1822 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1823 if (new != last) { 1824 DPRINTFN(10, "intrs=0x%04x", new, 0, 0, 0); 1825 last = new; 1826 } 1827 #endif 1828 sc->sc_eintrs |= OHCI_WDH; 1829 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1830 mutex_spin_enter(&sc->sc_intr_lock); 1831 ohci_intr1(sc); 1832 mutex_spin_exit(&sc->sc_intr_lock); 1833 } 1834 } 1835 1836 /* 1837 * Add an ED to the schedule. Called with USB lock held. 1838 */ 1839 Static void 1840 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1841 { 1842 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1843 DPRINTFN(8, "sed=%p head=%p", sed, head, 0, 0); 1844 1845 KASSERT(mutex_owned(&sc->sc_lock)); 1846 1847 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1848 sizeof(head->ed.ed_nexted), 1849 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1850 sed->next = head->next; 1851 sed->ed.ed_nexted = head->ed.ed_nexted; 1852 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1853 sizeof(sed->ed.ed_nexted), 1854 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1855 head->next = sed; 1856 head->ed.ed_nexted = HTOO32(sed->physaddr); 1857 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1858 sizeof(head->ed.ed_nexted), 1859 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1860 } 1861 1862 /* 1863 * Remove an ED from the schedule. Called with USB lock held. 1864 */ 1865 Static void 1866 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1867 { 1868 ohci_soft_ed_t *p; 1869 1870 KASSERT(mutex_owned(&sc->sc_lock)); 1871 1872 /* XXX */ 1873 for (p = head; p != NULL && p->next != sed; p = p->next) 1874 ; 1875 KASSERT(p != NULL); 1876 1877 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1878 sizeof(sed->ed.ed_nexted), 1879 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1880 p->next = sed->next; 1881 p->ed.ed_nexted = sed->ed.ed_nexted; 1882 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1883 sizeof(p->ed.ed_nexted), 1884 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1885 } 1886 1887 /* 1888 * When a transfer is completed the TD is added to the done queue by 1889 * the host controller. This queue is the processed by software. 1890 * Unfortunately the queue contains the physical address of the TD 1891 * and we have no simple way to translate this back to a kernel address. 1892 * To make the translation possible (and fast) we use a hash table of 1893 * TDs currently in the schedule. The physical address is used as the 1894 * hash value. 1895 */ 1896 1897 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1898 /* Called with USB lock held. */ 1899 void 1900 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1901 { 1902 int h = HASH(std->physaddr); 1903 1904 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1905 1906 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1907 } 1908 1909 /* Called with USB lock held. */ 1910 void 1911 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1912 { 1913 1914 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1915 1916 LIST_REMOVE(std, hnext); 1917 } 1918 1919 ohci_soft_td_t * 1920 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1921 { 1922 int h = HASH(a); 1923 ohci_soft_td_t *std; 1924 1925 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1926 std != NULL; 1927 std = LIST_NEXT(std, hnext)) 1928 if (std->physaddr == a) 1929 return std; 1930 return NULL; 1931 } 1932 1933 /* Called with USB lock held. */ 1934 void 1935 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1936 { 1937 int h = HASH(sitd->physaddr); 1938 1939 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1940 1941 KASSERT(mutex_owned(&sc->sc_lock)); 1942 1943 DPRINTFN(10, "sitd=%p physaddr=0x%08lx", sitd, (u_long)sitd->physaddr, 1944 0, 0); 1945 1946 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1947 } 1948 1949 /* Called with USB lock held. */ 1950 void 1951 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1952 { 1953 1954 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1955 1956 KASSERT(mutex_owned(&sc->sc_lock)); 1957 1958 DPRINTFN(10, "sitd=%p physaddr=0x%08lx", sitd, (u_long)sitd->physaddr, 1959 0, 0); 1960 1961 LIST_REMOVE(sitd, hnext); 1962 } 1963 1964 ohci_soft_itd_t * 1965 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1966 { 1967 int h = HASH(a); 1968 ohci_soft_itd_t *sitd; 1969 1970 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1971 sitd != NULL; 1972 sitd = LIST_NEXT(sitd, hnext)) 1973 if (sitd->physaddr == a) 1974 return sitd; 1975 return NULL; 1976 } 1977 1978 void 1979 ohci_timeout(void *addr) 1980 { 1981 struct usbd_xfer *xfer = addr; 1982 struct ohci_xfer *oxfer = OHCI_XFER2OXFER(xfer); 1983 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1984 1985 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1986 DPRINTF("oxfer=%p", oxfer, 0, 0, 0); 1987 1988 if (sc->sc_dying) { 1989 mutex_enter(&sc->sc_lock); 1990 ohci_abort_xfer(xfer, USBD_TIMEOUT); 1991 mutex_exit(&sc->sc_lock); 1992 return; 1993 } 1994 1995 /* Execute the abort in a process context. */ 1996 usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr, 1997 USB_TASKQ_MPSAFE); 1998 usb_add_task(xfer->ux_pipe->up_dev, &oxfer->abort_task, 1999 USB_TASKQ_HC); 2000 } 2001 2002 void 2003 ohci_timeout_task(void *addr) 2004 { 2005 struct usbd_xfer *xfer = addr; 2006 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2007 2008 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2009 2010 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2011 2012 mutex_enter(&sc->sc_lock); 2013 ohci_abort_xfer(xfer, USBD_TIMEOUT); 2014 mutex_exit(&sc->sc_lock); 2015 } 2016 2017 #ifdef OHCI_DEBUG 2018 void 2019 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 2020 { 2021 for (; std; std = std->nexttd) { 2022 ohci_dump_td(sc, std); 2023 KASSERTMSG(std->nexttd == NULL || std != std->nexttd, 2024 "std %p next %p", std, std->nexttd); 2025 } 2026 } 2027 2028 void 2029 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 2030 { 2031 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2032 2033 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2034 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2035 2036 uint32_t flags = O32TOH(std->td.td_flags); 2037 DPRINTF("TD(%p) at 0x%08lx:", std, (u_long)std->physaddr, 0, 0); 2038 DPRINTF(" round=%d DP=%x DI=%x T=%x", 2039 !!(flags & OHCI_TD_R), 2040 __SHIFTOUT(flags, OHCI_TD_DP_MASK), 2041 OHCI_TD_GET_DI(flags), 2042 __SHIFTOUT(flags, OHCI_TD_TOGGLE_MASK)); 2043 DPRINTF(" EC=%d CC=%d", OHCI_TD_GET_EC(flags), OHCI_TD_GET_CC(flags), 2044 0, 0); 2045 DPRINTF(" td_cbp=0x%08lx td_nexttd=0x%08lx td_be=0x%08lx", 2046 (u_long)O32TOH(std->td.td_cbp), 2047 (u_long)O32TOH(std->td.td_nexttd), 2048 (u_long)O32TOH(std->td.td_be), 0); 2049 } 2050 2051 void 2052 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2053 { 2054 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2055 2056 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 2057 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2058 2059 uint32_t flags = O32TOH(sitd->itd.itd_flags); 2060 DPRINTF("ITD(%p) at 0x%08lx", sitd, (u_long)sitd->physaddr, 0, 0); 2061 DPRINTF(" sf=%d di=%d fc=%d cc=%d", 2062 OHCI_ITD_GET_SF(flags), OHCI_ITD_GET_DI(flags), 2063 OHCI_ITD_GET_FC(flags), OHCI_ITD_GET_CC(flags)); 2064 DPRINTF(" bp0=0x%08x next=0x%08x be=0x%08x", 2065 O32TOH(sitd->itd.itd_bp0), 2066 O32TOH(sitd->itd.itd_nextitd), 2067 O32TOH(sitd->itd.itd_be), 0); 2068 CTASSERT(OHCI_ITD_NOFFSET == 8); 2069 DPRINTF(" offs[0] = 0x%04x offs[1] = 0x%04x " 2070 "offs[2] = 0x%04x offs[3] = 0x%04x", 2071 O16TOH(sitd->itd.itd_offset[0]), 2072 O16TOH(sitd->itd.itd_offset[1]), 2073 O16TOH(sitd->itd.itd_offset[2]), 2074 O16TOH(sitd->itd.itd_offset[3])); 2075 DPRINTF(" offs[4] = 0x%04x offs[5] = 0x%04x " 2076 "offs[6] = 0x%04x offs[7] = 0x%04x", 2077 O16TOH(sitd->itd.itd_offset[4]), 2078 O16TOH(sitd->itd.itd_offset[5]), 2079 O16TOH(sitd->itd.itd_offset[6]), 2080 O16TOH(sitd->itd.itd_offset[7])); 2081 } 2082 2083 void 2084 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2085 { 2086 for (; sitd; sitd = sitd->nextitd) 2087 ohci_dump_itd(sc, sitd); 2088 } 2089 2090 void 2091 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2092 { 2093 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2094 2095 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2096 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2097 2098 uint32_t flags = O32TOH(sed->ed.ed_flags); 2099 DPRINTF("ED(%p) at 0x%08lx:", sed, sed->physaddr, 0, 0); 2100 DPRINTF(" addr=%d endpt=%d maxp=%d", 2101 OHCI_ED_GET_FA(flags), 2102 OHCI_ED_GET_EN(flags), 2103 OHCI_ED_GET_MAXP(flags), 2104 0); 2105 DPRINTF(" dir=%d speed=%d skip=%d iso=%d", 2106 __SHIFTOUT(flags, OHCI_ED_DIR_MASK), 2107 !!(flags & OHCI_ED_SPEED), 2108 !!(flags & OHCI_ED_SKIP), 2109 !!(flags & OHCI_ED_FORMAT_ISO)); 2110 DPRINTF(" tailp=0x%08lx", (u_long)O32TOH(sed->ed.ed_tailp), 2111 0, 0, 0); 2112 DPRINTF(" headp=0x%08lx nexted=0x%08lx halted=%d carry=%d", 2113 O32TOH(sed->ed.ed_headp), O32TOH(sed->ed.ed_nexted), 2114 !!(O32TOH(sed->ed.ed_headp) & OHCI_HALTED), 2115 !!(O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 2116 } 2117 #endif 2118 2119 usbd_status 2120 ohci_open(struct usbd_pipe *pipe) 2121 { 2122 struct usbd_device *dev = pipe->up_dev; 2123 struct usbd_bus *bus = dev->ud_bus; 2124 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2125 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 2126 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2127 uint8_t addr = dev->ud_addr; 2128 uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2129 ohci_soft_ed_t *sed; 2130 ohci_soft_td_t *std; 2131 ohci_soft_itd_t *sitd; 2132 ohci_physaddr_t tdphys; 2133 uint32_t fmt; 2134 usbd_status err = USBD_NOMEM; 2135 int ival; 2136 2137 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2138 DPRINTFN(1, "pipe=%p, addr=%d, endpt=%d (%d)", pipe, addr, 2139 ed->bEndpointAddress, bus->ub_rhaddr); 2140 2141 if (sc->sc_dying) { 2142 return USBD_IOERROR; 2143 } 2144 2145 std = NULL; 2146 sed = NULL; 2147 2148 if (addr == bus->ub_rhaddr) { 2149 switch (ed->bEndpointAddress) { 2150 case USB_CONTROL_ENDPOINT: 2151 pipe->up_methods = &roothub_ctrl_methods; 2152 break; 2153 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 2154 pipe->up_methods = &ohci_root_intr_methods; 2155 break; 2156 default: 2157 err = USBD_INVAL; 2158 goto bad; 2159 } 2160 } else { 2161 sed = ohci_alloc_sed(sc); 2162 if (sed == NULL) 2163 goto bad; 2164 opipe->sed = sed; 2165 if (xfertype == UE_ISOCHRONOUS) { 2166 sitd = ohci_alloc_sitd(sc); 2167 if (sitd == NULL) 2168 goto bad; 2169 2170 opipe->tail.itd = sitd; 2171 tdphys = sitd->physaddr; 2172 fmt = OHCI_ED_FORMAT_ISO; 2173 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2174 fmt |= OHCI_ED_DIR_IN; 2175 else 2176 fmt |= OHCI_ED_DIR_OUT; 2177 } else { 2178 std = ohci_alloc_std(sc); 2179 if (std == NULL) 2180 goto bad; 2181 2182 opipe->tail.td = std; 2183 tdphys = std->physaddr; 2184 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2185 } 2186 sed->ed.ed_flags = HTOO32( 2187 OHCI_ED_SET_FA(addr) | 2188 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2189 (dev->ud_speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2190 fmt | 2191 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2192 sed->ed.ed_headp = HTOO32(tdphys | 2193 (pipe->up_endpoint->ue_toggle ? OHCI_TOGGLECARRY : 0)); 2194 sed->ed.ed_tailp = HTOO32(tdphys); 2195 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2196 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2197 2198 switch (xfertype) { 2199 case UE_CONTROL: 2200 pipe->up_methods = &ohci_device_ctrl_methods; 2201 err = usb_allocmem(&sc->sc_bus, 2202 sizeof(usb_device_request_t), 2203 0, &opipe->ctrl.reqdma); 2204 if (err) 2205 goto bad; 2206 mutex_enter(&sc->sc_lock); 2207 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2208 mutex_exit(&sc->sc_lock); 2209 break; 2210 case UE_INTERRUPT: 2211 pipe->up_methods = &ohci_device_intr_methods; 2212 ival = pipe->up_interval; 2213 if (ival == USBD_DEFAULT_INTERVAL) 2214 ival = ed->bInterval; 2215 err = ohci_device_setintr(sc, opipe, ival); 2216 if (err) 2217 goto bad; 2218 break; 2219 case UE_ISOCHRONOUS: 2220 pipe->up_methods = &ohci_device_isoc_methods; 2221 return ohci_setup_isoc(pipe); 2222 case UE_BULK: 2223 pipe->up_methods = &ohci_device_bulk_methods; 2224 mutex_enter(&sc->sc_lock); 2225 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2226 mutex_exit(&sc->sc_lock); 2227 break; 2228 } 2229 } 2230 2231 return USBD_NORMAL_COMPLETION; 2232 2233 bad: 2234 if (std != NULL) { 2235 ohci_free_std(sc, std); 2236 } 2237 if (sed != NULL) 2238 ohci_free_sed(sc, sed); 2239 return err; 2240 2241 } 2242 2243 /* 2244 * Close a reqular pipe. 2245 * Assumes that there are no pending transactions. 2246 */ 2247 void 2248 ohci_close_pipe(struct usbd_pipe *pipe, ohci_soft_ed_t *head) 2249 { 2250 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2251 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2252 ohci_soft_ed_t *sed = opipe->sed; 2253 2254 KASSERT(mutex_owned(&sc->sc_lock)); 2255 2256 #ifdef DIAGNOSTIC 2257 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2258 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2259 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2260 ohci_soft_td_t *std; 2261 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2262 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2263 "tl=0x%x pipe=%p, std=%p\n", sed, 2264 (int)O32TOH(sed->ed.ed_headp), 2265 (int)O32TOH(sed->ed.ed_tailp), 2266 pipe, std); 2267 #ifdef OHCI_DEBUG 2268 usbd_dump_pipe(&opipe->pipe); 2269 ohci_dump_ed(sc, sed); 2270 if (std) 2271 ohci_dump_td(sc, std); 2272 #endif 2273 usb_delay_ms(&sc->sc_bus, 2); 2274 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2275 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2276 printf("ohci_close_pipe: pipe still not empty\n"); 2277 } 2278 #endif 2279 ohci_rem_ed(sc, sed, head); 2280 /* Make sure the host controller is not touching this ED */ 2281 usb_delay_ms(&sc->sc_bus, 1); 2282 pipe->up_endpoint->ue_toggle = 2283 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2284 ohci_free_sed_locked(sc, opipe->sed); 2285 } 2286 2287 /* 2288 * Abort a device request. 2289 * If this routine is called at splusb() it guarantees that the request 2290 * will be removed from the hardware scheduling and that the callback 2291 * for it will be called with USBD_CANCELLED status. 2292 * It's impossible to guarantee that the requested transfer will not 2293 * have happened since the hardware runs concurrently. 2294 * If the transaction has already happened we rely on the ordinary 2295 * interrupt processing to process it. 2296 * XXX This is most probably wrong. 2297 * XXXMRG this doesn't make sense anymore. 2298 */ 2299 void 2300 ohci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2301 { 2302 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2303 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2304 ohci_soft_ed_t *sed = opipe->sed; 2305 ohci_soft_td_t *p, *n; 2306 ohci_physaddr_t headp; 2307 int hit; 2308 int wake; 2309 2310 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2311 DPRINTF("xfer=%p pipe=%p sed=%p", xfer, opipe,sed, 0); 2312 2313 KASSERT(mutex_owned(&sc->sc_lock)); 2314 ASSERT_SLEEPABLE(); 2315 2316 if (sc->sc_dying) { 2317 /* If we're dying, just do the software part. */ 2318 xfer->ux_status = status; /* make software ignore it */ 2319 callout_halt(&xfer->ux_callout, &sc->sc_lock); 2320 usb_transfer_complete(xfer); 2321 return; 2322 } 2323 2324 /* 2325 * If an abort is already in progress then just wait for it to 2326 * complete and return. 2327 */ 2328 if (xfer->ux_hcflags & UXFER_ABORTING) { 2329 DPRINTFN(2, "already aborting", 0, 0, 0, 0); 2330 #ifdef DIAGNOSTIC 2331 if (status == USBD_TIMEOUT) 2332 printf("%s: TIMEOUT while aborting\n", __func__); 2333 #endif 2334 /* Override the status which might be USBD_TIMEOUT. */ 2335 xfer->ux_status = status; 2336 DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0); 2337 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2338 while (xfer->ux_hcflags & UXFER_ABORTING) 2339 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2340 goto done; 2341 } 2342 xfer->ux_hcflags |= UXFER_ABORTING; 2343 2344 /* 2345 * Step 1: Make interrupt routine and hardware ignore xfer. 2346 */ 2347 xfer->ux_status = status; /* make software ignore it */ 2348 callout_stop(&xfer->ux_callout); 2349 DPRINTFN(1, "stop ed=%p", sed, 0, 0, 0); 2350 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2351 sizeof(sed->ed.ed_flags), 2352 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2353 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2354 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2355 sizeof(sed->ed.ed_flags), 2356 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2357 2358 /* 2359 * Step 2: Wait until we know hardware has finished any possible 2360 * use of the xfer. Also make sure the soft interrupt routine 2361 * has run. 2362 */ 2363 /* Hardware finishes in 1ms */ 2364 usb_delay_ms_locked(opipe->pipe.up_dev->ud_bus, 20, &sc->sc_lock); 2365 sc->sc_softwake = 1; 2366 usb_schedsoftintr(&sc->sc_bus); 2367 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2368 2369 /* 2370 * Step 3: Remove any vestiges of the xfer from the hardware. 2371 * The complication here is that the hardware may have executed 2372 * beyond the xfer we're trying to abort. So as we're scanning 2373 * the TDs of this xfer we check if the hardware points to 2374 * any of them. 2375 */ 2376 p = xfer->ux_hcpriv; 2377 KASSERT(p); 2378 2379 #ifdef OHCI_DEBUG 2380 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2381 2382 if (ohcidebug >= 2) { 2383 DPRINTF("sed:", 0, 0, 0, 0); 2384 ohci_dump_ed(sc, sed); 2385 ohci_dump_tds(sc, p); 2386 } 2387 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2388 #endif 2389 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2390 hit = 0; 2391 for (; p->xfer == xfer; p = n) { 2392 hit |= headp == p->physaddr; 2393 n = p->nexttd; 2394 ohci_hash_rem_td(sc, p); 2395 } 2396 /* Zap headp register if hardware pointed inside the xfer. */ 2397 if (hit) { 2398 DPRINTFN(1, "set hd=0x%08x, tl=0x%08x", (int)p->physaddr, 2399 (int)O32TOH(sed->ed.ed_tailp), 0, 0); 2400 sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */ 2401 usb_syncmem(&sed->dma, 2402 sed->offs + offsetof(ohci_ed_t, ed_headp), 2403 sizeof(sed->ed.ed_headp), 2404 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2405 } else { 2406 DPRINTFN(1, "no hit", 0, 0, 0, 0); 2407 } 2408 2409 /* 2410 * Step 4: Turn on hardware again. 2411 */ 2412 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2413 sizeof(sed->ed.ed_flags), 2414 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2415 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2416 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2417 sizeof(sed->ed.ed_flags), 2418 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2419 2420 /* 2421 * Step 5: Execute callback. 2422 */ 2423 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2424 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2425 usb_transfer_complete(xfer); 2426 if (wake) 2427 cv_broadcast(&xfer->ux_hccv); 2428 2429 done: 2430 KASSERT(mutex_owned(&sc->sc_lock)); 2431 } 2432 2433 /* 2434 * Data structures and routines to emulate the root hub. 2435 */ 2436 Static int 2437 ohci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2438 void *buf, int buflen) 2439 { 2440 ohci_softc_t *sc = OHCI_BUS2SC(bus); 2441 usb_port_status_t ps; 2442 uint16_t len, value, index; 2443 int l, totlen = 0; 2444 int port, i; 2445 uint32_t v; 2446 2447 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2448 2449 if (sc->sc_dying) 2450 return -1; 2451 2452 DPRINTFN(4, "type=0x%02x request=%02x", req->bmRequestType, 2453 req->bRequest, 0, 0); 2454 2455 len = UGETW(req->wLength); 2456 value = UGETW(req->wValue); 2457 index = UGETW(req->wIndex); 2458 2459 #define C(x,y) ((x) | ((y) << 8)) 2460 switch (C(req->bRequest, req->bmRequestType)) { 2461 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2462 DPRINTFN(8, "wValue=0x%04x", value, 0, 0, 0); 2463 if (len == 0) 2464 break; 2465 switch (value) { 2466 case C(0, UDESC_DEVICE): { 2467 usb_device_descriptor_t devd; 2468 2469 totlen = min(buflen, sizeof(devd)); 2470 memcpy(&devd, buf, totlen); 2471 USETW(devd.idVendor, sc->sc_id_vendor); 2472 memcpy(buf, &devd, totlen); 2473 break; 2474 } 2475 case C(1, UDESC_STRING): 2476 #define sd ((usb_string_descriptor_t *)buf) 2477 /* Vendor */ 2478 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2479 break; 2480 case C(2, UDESC_STRING): 2481 /* Product */ 2482 totlen = usb_makestrdesc(sd, len, "OHCI root hub"); 2483 break; 2484 #undef sd 2485 default: 2486 /* default from usbroothub */ 2487 return buflen; 2488 } 2489 break; 2490 2491 /* Hub requests */ 2492 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2493 break; 2494 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2495 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 2496 index, value, 0, 0); 2497 if (index < 1 || index > sc->sc_noport) { 2498 return -1; 2499 } 2500 port = OHCI_RH_PORT_STATUS(index); 2501 switch(value) { 2502 case UHF_PORT_ENABLE: 2503 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2504 break; 2505 case UHF_PORT_SUSPEND: 2506 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2507 break; 2508 case UHF_PORT_POWER: 2509 /* Yes, writing to the LOW_SPEED bit clears power. */ 2510 OWRITE4(sc, port, UPS_LOW_SPEED); 2511 break; 2512 case UHF_C_PORT_CONNECTION: 2513 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2514 break; 2515 case UHF_C_PORT_ENABLE: 2516 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2517 break; 2518 case UHF_C_PORT_SUSPEND: 2519 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2520 break; 2521 case UHF_C_PORT_OVER_CURRENT: 2522 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2523 break; 2524 case UHF_C_PORT_RESET: 2525 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2526 break; 2527 default: 2528 return -1; 2529 } 2530 switch(value) { 2531 case UHF_C_PORT_CONNECTION: 2532 case UHF_C_PORT_ENABLE: 2533 case UHF_C_PORT_SUSPEND: 2534 case UHF_C_PORT_OVER_CURRENT: 2535 case UHF_C_PORT_RESET: 2536 /* Enable RHSC interrupt if condition is cleared. */ 2537 if ((OREAD4(sc, port) >> 16) == 0) 2538 ohci_rhsc_enable(sc); 2539 break; 2540 default: 2541 break; 2542 } 2543 break; 2544 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2545 if (len == 0) 2546 break; 2547 if ((value & 0xff) != 0) { 2548 return -1; 2549 } 2550 usb_hub_descriptor_t hubd; 2551 2552 totlen = min(buflen, sizeof(hubd)); 2553 memcpy(&hubd, buf, totlen); 2554 2555 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2556 hubd.bNbrPorts = sc->sc_noport; 2557 USETW(hubd.wHubCharacteristics, 2558 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2559 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2560 /* XXX overcurrent */ 2561 ); 2562 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2563 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2564 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2565 hubd.DeviceRemovable[i++] = (uint8_t)v; 2566 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2567 totlen = min(totlen, hubd.bDescLength); 2568 memcpy(buf, &hubd, totlen); 2569 break; 2570 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2571 if (len != 4) { 2572 return -1; 2573 } 2574 memset(buf, 0, len); /* ? XXX */ 2575 totlen = len; 2576 break; 2577 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2578 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 2579 if (index < 1 || index > sc->sc_noport) { 2580 return -1; 2581 } 2582 if (len != 4) { 2583 return -1; 2584 } 2585 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2586 DPRINTFN(8, "port status=0x%04x", v, 0, 0, 0); 2587 USETW(ps.wPortStatus, v); 2588 USETW(ps.wPortChange, v >> 16); 2589 totlen = min(len, sizeof(ps)); 2590 memcpy(buf, &ps, totlen); 2591 break; 2592 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2593 return -1; 2594 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2595 break; 2596 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2597 if (index < 1 || index > sc->sc_noport) { 2598 return -1; 2599 } 2600 port = OHCI_RH_PORT_STATUS(index); 2601 switch(value) { 2602 case UHF_PORT_ENABLE: 2603 OWRITE4(sc, port, UPS_PORT_ENABLED); 2604 break; 2605 case UHF_PORT_SUSPEND: 2606 OWRITE4(sc, port, UPS_SUSPEND); 2607 break; 2608 case UHF_PORT_RESET: 2609 DPRINTFN(5, "reset port %d", index, 0, 0, 0); 2610 OWRITE4(sc, port, UPS_RESET); 2611 for (i = 0; i < 5; i++) { 2612 usb_delay_ms(&sc->sc_bus, 2613 USB_PORT_ROOT_RESET_DELAY); 2614 if (sc->sc_dying) { 2615 return -1; 2616 } 2617 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2618 break; 2619 } 2620 DPRINTFN(8, "port %d reset, status = 0x%04x", index, 2621 OREAD4(sc, port), 0, 0); 2622 break; 2623 case UHF_PORT_POWER: 2624 DPRINTFN(2, "set port power %d", index, 0, 0, 0); 2625 OWRITE4(sc, port, UPS_PORT_POWER); 2626 break; 2627 default: 2628 return -1; 2629 } 2630 break; 2631 default: 2632 /* default from usbroothub */ 2633 return buflen; 2634 } 2635 2636 return totlen; 2637 } 2638 2639 Static usbd_status 2640 ohci_root_intr_transfer(struct usbd_xfer *xfer) 2641 { 2642 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2643 usbd_status err; 2644 2645 /* Insert last in queue. */ 2646 mutex_enter(&sc->sc_lock); 2647 err = usb_insert_transfer(xfer); 2648 mutex_exit(&sc->sc_lock); 2649 if (err) 2650 return err; 2651 2652 /* Pipe isn't running, start first */ 2653 return ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2654 } 2655 2656 Static usbd_status 2657 ohci_root_intr_start(struct usbd_xfer *xfer) 2658 { 2659 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2660 2661 if (sc->sc_dying) 2662 return USBD_IOERROR; 2663 2664 mutex_enter(&sc->sc_lock); 2665 KASSERT(sc->sc_intrxfer == NULL); 2666 sc->sc_intrxfer = xfer; 2667 mutex_exit(&sc->sc_lock); 2668 2669 return USBD_IN_PROGRESS; 2670 } 2671 2672 /* Abort a root interrupt request. */ 2673 Static void 2674 ohci_root_intr_abort(struct usbd_xfer *xfer) 2675 { 2676 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2677 2678 KASSERT(mutex_owned(&sc->sc_lock)); 2679 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2680 2681 sc->sc_intrxfer = NULL; 2682 2683 xfer->ux_status = USBD_CANCELLED; 2684 usb_transfer_complete(xfer); 2685 } 2686 2687 /* Close the root pipe. */ 2688 Static void 2689 ohci_root_intr_close(struct usbd_pipe *pipe) 2690 { 2691 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2692 2693 KASSERT(mutex_owned(&sc->sc_lock)); 2694 2695 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2696 2697 sc->sc_intrxfer = NULL; 2698 } 2699 2700 /************************/ 2701 2702 int 2703 ohci_device_ctrl_init(struct usbd_xfer *xfer) 2704 { 2705 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2706 usb_device_request_t *req = &xfer->ux_request; 2707 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2708 ohci_soft_td_t *stat, *setup; 2709 int isread = req->bmRequestType & UT_READ; 2710 int len = xfer->ux_bufsize; 2711 int err = ENOMEM; 2712 2713 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2714 2715 setup = ohci_alloc_std(sc); 2716 if (setup == NULL) { 2717 goto bad1; 2718 } 2719 stat = ohci_alloc_std(sc); 2720 if (stat == NULL) { 2721 goto bad2; 2722 } 2723 2724 ox->ox_setup = setup; 2725 ox->ox_stat = stat; 2726 ox->ox_nstd = 0; 2727 2728 /* Set up data transaction */ 2729 if (len != 0) { 2730 err = ohci_alloc_std_chain(sc, xfer, len, isread); 2731 if (err) { 2732 goto bad3; 2733 } 2734 } 2735 return 0; 2736 2737 bad3: 2738 ohci_free_std(sc, stat); 2739 bad2: 2740 ohci_free_std(sc, setup); 2741 bad1: 2742 return err; 2743 } 2744 2745 void 2746 ohci_device_ctrl_fini(struct usbd_xfer *xfer) 2747 { 2748 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2749 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2750 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2751 2752 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2753 DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0); 2754 2755 mutex_enter(&sc->sc_lock); 2756 if (ox->ox_setup != opipe->tail.td) { 2757 ohci_free_std_locked(sc, ox->ox_setup); 2758 } 2759 for (size_t i = 0; i < ox->ox_nstd; i++) { 2760 ohci_soft_td_t *std = ox->ox_stds[i]; 2761 if (std == NULL) 2762 break; 2763 ohci_free_std_locked(sc, std); 2764 } 2765 ohci_free_std_locked(sc, ox->ox_stat); 2766 mutex_exit(&sc->sc_lock); 2767 2768 if (ox->ox_nstd) { 2769 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 2770 kmem_free(ox->ox_stds, sz); 2771 } 2772 } 2773 2774 Static usbd_status 2775 ohci_device_ctrl_transfer(struct usbd_xfer *xfer) 2776 { 2777 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2778 usbd_status err; 2779 2780 /* Insert last in queue. */ 2781 mutex_enter(&sc->sc_lock); 2782 err = usb_insert_transfer(xfer); 2783 mutex_exit(&sc->sc_lock); 2784 if (err) 2785 return err; 2786 2787 /* Pipe isn't running, start first */ 2788 return ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2789 } 2790 2791 Static usbd_status 2792 ohci_device_ctrl_start(struct usbd_xfer *xfer) 2793 { 2794 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2795 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2796 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2797 usb_device_request_t *req = &xfer->ux_request; 2798 struct usbd_device *dev __diagused = opipe->pipe.up_dev; 2799 ohci_soft_td_t *setup, *stat, *next, *tail; 2800 ohci_soft_ed_t *sed; 2801 int isread; 2802 int len; 2803 2804 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2805 2806 if (sc->sc_dying) 2807 return USBD_IOERROR; 2808 2809 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2810 2811 isread = req->bmRequestType & UT_READ; 2812 len = UGETW(req->wLength); 2813 2814 DPRINTF("xfer=%p len=%d, addr=%d, endpt=%d", xfer, len, dev->ud_addr, 2815 opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress); 2816 DPRINTF("type=0x%02x, request=0x%02x, wValue=0x%04x, wIndex=0x%04x", 2817 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2818 UGETW(req->wIndex)); 2819 2820 /* Need to take lock here for pipe->tail.td */ 2821 mutex_enter(&sc->sc_lock); 2822 2823 /* 2824 * Use the pipe "tail" TD as our first and loan our first TD to the 2825 * next transfer 2826 */ 2827 setup = opipe->tail.td; 2828 opipe->tail.td = ox->ox_setup; 2829 ox->ox_setup = setup; 2830 2831 stat = ox->ox_stat; 2832 2833 /* point at sentinel */ 2834 tail = opipe->tail.td; 2835 sed = opipe->sed; 2836 2837 KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->ud_addr, 2838 "address ED %d pipe %d\n", 2839 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->ud_addr); 2840 KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) == 2841 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 2842 "MPL ED %d pipe %d\n", 2843 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), 2844 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 2845 2846 /* next will point to data if len != 0 */ 2847 next = stat; 2848 2849 /* Set up data transaction */ 2850 if (len != 0) { 2851 ohci_soft_td_t *std; 2852 ohci_soft_td_t *end; 2853 2854 next = ox->ox_stds[0]; 2855 ohci_reset_std_chain(sc, xfer, len, isread, next, &end); 2856 2857 end->td.td_nexttd = HTOO32(stat->physaddr); 2858 end->nexttd = stat; 2859 2860 usb_syncmem(&end->dma, 2861 end->offs + offsetof(ohci_td_t, td_nexttd), 2862 sizeof(end->td.td_nexttd), 2863 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2864 2865 usb_syncmem(&xfer->ux_dmabuf, 0, len, 2866 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2867 std = ox->ox_stds[0]; 2868 /* Start toggle at 1 and then use the carried toggle. */ 2869 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 2870 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 2871 usb_syncmem(&std->dma, 2872 std->offs + offsetof(ohci_td_t, td_flags), 2873 sizeof(std->td.td_flags), 2874 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2875 } 2876 2877 DPRINTFN(8, "setup %p data %p stat %p tail %p", setup, 2878 (len != 0 ? ox->ox_stds[0] : NULL), stat, tail); 2879 KASSERT(opipe->tail.td == tail); 2880 2881 memcpy(KERNADDR(&opipe->ctrl.reqdma, 0), req, sizeof(*req)); 2882 usb_syncmem(&opipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2883 2884 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 2885 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 2886 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->ctrl.reqdma, 0)); 2887 setup->td.td_nexttd = HTOO32(next->physaddr); 2888 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof(*req) - 1); 2889 setup->nexttd = next; 2890 setup->len = 0; 2891 setup->xfer = xfer; 2892 setup->flags = 0; 2893 ohci_hash_add_td(sc, setup); 2894 2895 xfer->ux_hcpriv = setup; 2896 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2897 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2898 2899 stat->td.td_flags = HTOO32( 2900 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 2901 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 2902 stat->td.td_cbp = 0; 2903 stat->td.td_nexttd = HTOO32(tail->physaddr); 2904 stat->td.td_be = 0; 2905 stat->nexttd = tail; 2906 stat->flags = OHCI_CALL_DONE; 2907 stat->len = 0; 2908 stat->xfer = xfer; 2909 ohci_hash_add_td(sc, stat); 2910 2911 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2912 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2913 2914 memset(&tail->td, 0, sizeof(tail->td)); 2915 tail->nexttd = NULL; 2916 tail->xfer = NULL; 2917 2918 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 2919 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2920 2921 #ifdef OHCI_DEBUG 2922 USBHIST_LOGN(ohcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2923 if (ohcidebug >= 5) { 2924 ohci_dump_ed(sc, sed); 2925 ohci_dump_tds(sc, setup); 2926 } 2927 USBHIST_LOGN(ohcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2928 #endif 2929 2930 /* Insert ED in schedule */ 2931 sed->ed.ed_tailp = HTOO32(tail->physaddr); 2932 usb_syncmem(&sed->dma, 2933 sed->offs + offsetof(ohci_ed_t, ed_tailp), 2934 sizeof(sed->ed.ed_tailp), 2935 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2936 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2937 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2938 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2939 ohci_timeout, xfer); 2940 } 2941 2942 DPRINTF("done", 0, 0, 0, 0); 2943 2944 mutex_exit(&sc->sc_lock); 2945 2946 if (sc->sc_bus.ub_usepolling) 2947 ohci_waitintr(sc, xfer); 2948 2949 return USBD_IN_PROGRESS; 2950 } 2951 2952 /* Abort a device control request. */ 2953 Static void 2954 ohci_device_ctrl_abort(struct usbd_xfer *xfer) 2955 { 2956 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 2957 2958 KASSERT(mutex_owned(&sc->sc_lock)); 2959 2960 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2961 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2962 ohci_abort_xfer(xfer, USBD_CANCELLED); 2963 } 2964 2965 /* Close a device control pipe. */ 2966 Static void 2967 ohci_device_ctrl_close(struct usbd_pipe *pipe) 2968 { 2969 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2970 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2971 2972 KASSERT(mutex_owned(&sc->sc_lock)); 2973 2974 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2975 DPRINTF("pipe=%p", pipe, 0, 0, 0); 2976 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2977 ohci_free_std_locked(sc, opipe->tail.td); 2978 } 2979 2980 /************************/ 2981 2982 Static void 2983 ohci_device_clear_toggle(struct usbd_pipe *pipe) 2984 { 2985 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2986 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2987 2988 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2989 } 2990 2991 Static void 2992 ohci_noop(struct usbd_pipe *pipe) 2993 { 2994 } 2995 2996 Static int 2997 ohci_device_bulk_init(struct usbd_xfer *xfer) 2998 { 2999 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3000 int len = xfer->ux_bufsize; 3001 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;; 3002 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3003 int err; 3004 3005 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3006 3007 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3008 3009 DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread, 3010 xfer->ux_flags); 3011 DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0); 3012 3013 /* Allocate a chain of new TDs (including a new tail). */ 3014 err = ohci_alloc_std_chain(sc, xfer, len, isread); 3015 if (err) 3016 return err; 3017 3018 return 0; 3019 } 3020 3021 Static void 3022 ohci_device_bulk_fini(struct usbd_xfer *xfer) 3023 { 3024 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3025 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3026 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3027 3028 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3029 DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0); 3030 3031 mutex_enter(&sc->sc_lock); 3032 for (size_t i = 0; i < ox->ox_nstd; i++) { 3033 ohci_soft_td_t *std = ox->ox_stds[i]; 3034 if (std == NULL) 3035 break; 3036 if (std != opipe->tail.td) 3037 ohci_free_std_locked(sc, std); 3038 } 3039 mutex_exit(&sc->sc_lock); 3040 3041 if (ox->ox_nstd) { 3042 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 3043 kmem_free(ox->ox_stds, sz); 3044 } 3045 } 3046 3047 Static usbd_status 3048 ohci_device_bulk_transfer(struct usbd_xfer *xfer) 3049 { 3050 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3051 usbd_status err; 3052 3053 /* Insert last in queue. */ 3054 mutex_enter(&sc->sc_lock); 3055 err = usb_insert_transfer(xfer); 3056 mutex_exit(&sc->sc_lock); 3057 if (err) 3058 return err; 3059 3060 /* Pipe isn't running, start first */ 3061 return ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3062 } 3063 3064 Static usbd_status 3065 ohci_device_bulk_start(struct usbd_xfer *xfer) 3066 { 3067 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3068 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3069 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3070 ohci_soft_td_t *last; 3071 ohci_soft_td_t *data, *tail, *tdp; 3072 ohci_soft_ed_t *sed; 3073 int len, isread, endpt; 3074 3075 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3076 3077 if (sc->sc_dying) 3078 return USBD_IOERROR; 3079 3080 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3081 3082 len = xfer->ux_length; 3083 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3084 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3085 sed = opipe->sed; 3086 3087 DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread, 3088 xfer->ux_flags); 3089 DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0); 3090 3091 mutex_enter(&sc->sc_lock); 3092 3093 /* 3094 * Use the pipe "tail" TD as our first and loan our first TD to the 3095 * next transfer 3096 */ 3097 data = opipe->tail.td; 3098 opipe->tail.td = ox->ox_stds[0]; 3099 ox->ox_stds[0] = data; 3100 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3101 3102 /* point at sentinel */ 3103 tail = opipe->tail.td; 3104 memset(&tail->td, 0, sizeof(tail->td)); 3105 tail->nexttd = NULL; 3106 tail->xfer = NULL; 3107 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3108 BUS_DMASYNC_PREWRITE); 3109 xfer->ux_hcpriv = data; 3110 3111 DPRINTFN(8, "xfer %p data %p tail %p", xfer, ox->ox_stds[0], tail, 0); 3112 KASSERT(opipe->tail.td == tail); 3113 3114 /* We want interrupt at the end of the transfer. */ 3115 last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3116 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3117 3118 last->td.td_nexttd = HTOO32(tail->physaddr); 3119 last->nexttd = tail; 3120 last->flags |= OHCI_CALL_DONE; 3121 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3122 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3123 3124 DPRINTFN(4, "ed_flags=0x%08x td_flags=0x%08x " 3125 "td_cbp=0x%08x td_be=0x%08x", 3126 (int)O32TOH(sed->ed.ed_flags), 3127 (int)O32TOH(data->td.td_flags), 3128 (int)O32TOH(data->td.td_cbp), 3129 (int)O32TOH(data->td.td_be)); 3130 3131 #ifdef OHCI_DEBUG 3132 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3133 if (ohcidebug >= 5) { 3134 ohci_dump_ed(sc, sed); 3135 ohci_dump_tds(sc, data); 3136 } 3137 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3138 #endif 3139 3140 /* Insert ED in schedule */ 3141 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3142 KASSERT(tdp->xfer == xfer); 3143 } 3144 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3145 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3146 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3147 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3148 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3149 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3150 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3151 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3152 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3153 ohci_timeout, xfer); 3154 } 3155 mutex_exit(&sc->sc_lock); 3156 3157 return USBD_IN_PROGRESS; 3158 } 3159 3160 Static void 3161 ohci_device_bulk_abort(struct usbd_xfer *xfer) 3162 { 3163 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3164 3165 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3166 3167 KASSERT(mutex_owned(&sc->sc_lock)); 3168 3169 DPRINTF("xfer=%p", xfer, 0, 0, 0); 3170 ohci_abort_xfer(xfer, USBD_CANCELLED); 3171 } 3172 3173 /* 3174 * Close a device bulk pipe. 3175 */ 3176 Static void 3177 ohci_device_bulk_close(struct usbd_pipe *pipe) 3178 { 3179 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3180 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3181 3182 KASSERT(mutex_owned(&sc->sc_lock)); 3183 3184 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3185 3186 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3187 ohci_close_pipe(pipe, sc->sc_bulk_head); 3188 ohci_free_std_locked(sc, opipe->tail.td); 3189 } 3190 3191 /************************/ 3192 3193 Static int 3194 ohci_device_intr_init(struct usbd_xfer *xfer) 3195 { 3196 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3197 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3198 int len = xfer->ux_bufsize; 3199 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;; 3200 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3201 int err; 3202 3203 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3204 3205 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3206 KASSERT(len != 0); 3207 3208 DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread, 3209 xfer->ux_flags); 3210 DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0); 3211 3212 ox->ox_nstd = 0; 3213 3214 err = ohci_alloc_std_chain(sc, xfer, len, isread); 3215 if (err) { 3216 return err; 3217 } 3218 3219 return 0; 3220 } 3221 3222 Static void 3223 ohci_device_intr_fini(struct usbd_xfer *xfer) 3224 { 3225 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3226 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3227 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3228 3229 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3230 DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0); 3231 3232 mutex_enter(&sc->sc_lock); 3233 for (size_t i = 0; i < ox->ox_nstd; i++) { 3234 ohci_soft_td_t *std = ox->ox_stds[i]; 3235 if (std != NULL) 3236 break; 3237 if (std != opipe->tail.td) 3238 ohci_free_std_locked(sc, std); 3239 } 3240 mutex_exit(&sc->sc_lock); 3241 3242 if (ox->ox_nstd) { 3243 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 3244 kmem_free(ox->ox_stds, sz); 3245 } 3246 } 3247 3248 Static usbd_status 3249 ohci_device_intr_transfer(struct usbd_xfer *xfer) 3250 { 3251 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3252 usbd_status err; 3253 3254 /* Insert last in queue. */ 3255 mutex_enter(&sc->sc_lock); 3256 err = usb_insert_transfer(xfer); 3257 mutex_exit(&sc->sc_lock); 3258 if (err) 3259 return err; 3260 3261 /* Pipe isn't running, start first */ 3262 return ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3263 } 3264 3265 Static usbd_status 3266 ohci_device_intr_start(struct usbd_xfer *xfer) 3267 { 3268 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3269 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3270 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3271 ohci_soft_ed_t *sed = opipe->sed; 3272 ohci_soft_td_t *data, *last, *tail; 3273 int len, isread, endpt; 3274 3275 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3276 3277 if (sc->sc_dying) 3278 return USBD_IOERROR; 3279 3280 DPRINTFN(3, "xfer=%p len=%d flags=%d priv=%p", xfer, xfer->ux_length, 3281 xfer->ux_flags, xfer->ux_priv); 3282 3283 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3284 3285 len = xfer->ux_length; 3286 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3287 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3288 3289 mutex_enter(&sc->sc_lock); 3290 3291 /* 3292 * Use the pipe "tail" TD as our first and loan our first TD to the 3293 * next transfer. 3294 */ 3295 data = opipe->tail.td; 3296 opipe->tail.td = ox->ox_stds[0]; 3297 ox->ox_stds[0] = data; 3298 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3299 3300 /* point at sentinel */ 3301 tail = opipe->tail.td; 3302 memset(&tail->td, 0, sizeof(tail->td)); 3303 tail->nexttd = NULL; 3304 tail->xfer = NULL; 3305 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3306 BUS_DMASYNC_PREWRITE); 3307 xfer->ux_hcpriv = data; 3308 3309 DPRINTFN(8, "data %p tail %p", ox->ox_stds[0], tail, 0, 0); 3310 KASSERT(opipe->tail.td == tail); 3311 3312 /* We want interrupt at the end of the transfer. */ 3313 last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3314 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3315 3316 last->td.td_nexttd = HTOO32(tail->physaddr); 3317 last->nexttd = tail; 3318 last->flags |= OHCI_CALL_DONE; 3319 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3320 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3321 3322 #ifdef OHCI_DEBUG 3323 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3324 if (ohcidebug >= 5) { 3325 ohci_dump_ed(sc, sed); 3326 ohci_dump_tds(sc, data); 3327 } 3328 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3329 #endif 3330 3331 /* Insert ED in schedule */ 3332 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3333 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3334 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3335 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3336 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3337 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3338 3339 mutex_exit(&sc->sc_lock); 3340 3341 return USBD_IN_PROGRESS; 3342 } 3343 3344 /* Abort a device interrupt request. */ 3345 Static void 3346 ohci_device_intr_abort(struct usbd_xfer *xfer) 3347 { 3348 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3349 3350 KASSERT(mutex_owned(&sc->sc_lock)); 3351 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3352 3353 ohci_abort_xfer(xfer, USBD_CANCELLED); 3354 } 3355 3356 /* Close a device interrupt pipe. */ 3357 Static void 3358 ohci_device_intr_close(struct usbd_pipe *pipe) 3359 { 3360 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3361 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3362 int nslots = opipe->intr.nslots; 3363 int pos = opipe->intr.pos; 3364 int j; 3365 ohci_soft_ed_t *p, *sed = opipe->sed; 3366 3367 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3368 3369 KASSERT(mutex_owned(&sc->sc_lock)); 3370 3371 DPRINTFN(1, "pipe=%p nslots=%d pos=%d", pipe, nslots, pos, 0); 3372 usb_syncmem(&sed->dma, sed->offs, 3373 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3374 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3375 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3376 sizeof(sed->ed.ed_flags), 3377 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3378 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3379 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3380 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3381 3382 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3383 continue; 3384 KASSERT(p); 3385 p->next = sed->next; 3386 p->ed.ed_nexted = sed->ed.ed_nexted; 3387 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3388 sizeof(p->ed.ed_nexted), 3389 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3390 3391 for (j = 0; j < nslots; j++) 3392 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3393 3394 ohci_free_std_locked(sc, opipe->tail.td); 3395 ohci_free_sed_locked(sc, opipe->sed); 3396 } 3397 3398 Static usbd_status 3399 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3400 { 3401 int i, j, best; 3402 u_int npoll, slow, shigh, nslots; 3403 u_int bestbw, bw; 3404 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3405 3406 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3407 3408 DPRINTFN(2, "pipe=%p", opipe, 0, 0, 0); 3409 if (ival == 0) { 3410 printf("ohci_setintr: 0 interval\n"); 3411 return USBD_INVAL; 3412 } 3413 3414 npoll = OHCI_NO_INTRS; 3415 while (npoll > ival) 3416 npoll /= 2; 3417 DPRINTFN(2, "ival=%d npoll=%d", ival, npoll, 0, 0); 3418 3419 /* 3420 * We now know which level in the tree the ED must go into. 3421 * Figure out which slot has most bandwidth left over. 3422 * Slots to examine: 3423 * npoll 3424 * 1 0 3425 * 2 1 2 3426 * 4 3 4 5 6 3427 * 8 7 8 9 10 11 12 13 14 3428 * N (N-1) .. (N-1+N-1) 3429 */ 3430 slow = npoll-1; 3431 shigh = slow + npoll; 3432 nslots = OHCI_NO_INTRS / npoll; 3433 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3434 bw = 0; 3435 for (j = 0; j < nslots; j++) 3436 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3437 if (bw < bestbw) { 3438 best = i; 3439 bestbw = bw; 3440 } 3441 } 3442 DPRINTFN(2, "best=%d(%d..%d) bestbw=%d", best, slow, shigh, bestbw); 3443 3444 mutex_enter(&sc->sc_lock); 3445 hsed = sc->sc_eds[best]; 3446 sed->next = hsed->next; 3447 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3448 sizeof(hsed->ed.ed_flags), 3449 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3450 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3451 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3452 sizeof(sed->ed.ed_flags), 3453 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3454 hsed->next = sed; 3455 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3456 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3457 sizeof(hsed->ed.ed_flags), 3458 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3459 mutex_exit(&sc->sc_lock); 3460 3461 for (j = 0; j < nslots; j++) 3462 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3463 opipe->intr.nslots = nslots; 3464 opipe->intr.pos = best; 3465 3466 DPRINTFN(5, "returns %p", opipe, 0, 0, 0); 3467 return USBD_NORMAL_COMPLETION; 3468 } 3469 3470 /***********************/ 3471 3472 Static int 3473 ohci_device_isoc_init(struct usbd_xfer *xfer) 3474 { 3475 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3476 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3477 ohci_soft_itd_t *sitd; 3478 size_t i; 3479 int err; 3480 3481 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3482 3483 DPRINTFN(1, "xfer %p len %d flags %d", xfer, xfer->ux_length, 3484 xfer->ux_flags, 0); 3485 3486 const size_t nfsitd = 3487 (xfer->ux_nframes + OHCI_ITD_NOFFSET - 1) / OHCI_ITD_NOFFSET; 3488 const size_t nbsitd = xfer->ux_bufsize / OHCI_PAGE_SIZE; 3489 const size_t nsitd = MAX(nfsitd, nbsitd) + 1; 3490 3491 ox->ox_sitds = kmem_zalloc(sizeof(ohci_soft_itd_t *) * nsitd, 3492 KM_SLEEP); 3493 ox->ox_nsitd = nsitd; 3494 3495 for (i = 0; i < nsitd; i++) { 3496 /* Allocate next ITD */ 3497 sitd = ohci_alloc_sitd(sc); 3498 if (sitd == NULL) { 3499 err = ENOMEM; 3500 goto fail; 3501 } 3502 ox->ox_sitds[i] = sitd; 3503 sitd->xfer = xfer; 3504 sitd->flags = 0; 3505 } 3506 3507 return 0; 3508 fail: 3509 for (; i > 0;) { 3510 ohci_free_sitd(sc, ox->ox_sitds[--i]); 3511 } 3512 return err; 3513 } 3514 3515 Static void 3516 ohci_device_isoc_fini(struct usbd_xfer *xfer) 3517 { 3518 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3519 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3520 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3521 3522 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3523 3524 mutex_enter(&sc->sc_lock); 3525 for (size_t i = 0; i < ox->ox_nsitd; i++) { 3526 if (ox->ox_sitds[i] != opipe->tail.itd) { 3527 ohci_free_sitd_locked(sc, ox->ox_sitds[i]); 3528 } 3529 } 3530 mutex_exit(&sc->sc_lock); 3531 3532 if (ox->ox_nsitd) { 3533 const size_t sz = sizeof(ohci_soft_itd_t *) * ox->ox_nsitd; 3534 kmem_free(ox->ox_sitds, sz); 3535 } 3536 } 3537 3538 3539 usbd_status 3540 ohci_device_isoc_transfer(struct usbd_xfer *xfer) 3541 { 3542 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3543 usbd_status err; 3544 3545 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3546 3547 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 3548 3549 /* Put it on our queue, */ 3550 mutex_enter(&sc->sc_lock); 3551 err = usb_insert_transfer(xfer); 3552 mutex_exit(&sc->sc_lock); 3553 3554 /* bail out on error, */ 3555 if (err && err != USBD_IN_PROGRESS) 3556 return err; 3557 3558 /* XXX should check inuse here */ 3559 3560 /* insert into schedule, */ 3561 ohci_device_isoc_enter(xfer); 3562 3563 /* and start if the pipe wasn't running */ 3564 if (!err) 3565 ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3566 3567 return err; 3568 } 3569 3570 void 3571 ohci_device_isoc_enter(struct usbd_xfer *xfer) 3572 { 3573 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3574 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3575 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3576 ohci_soft_ed_t *sed = opipe->sed; 3577 ohci_soft_itd_t *sitd, *nsitd, *tail; 3578 ohci_physaddr_t buf, offs, noffs, bp0; 3579 int i, ncur, nframes; 3580 3581 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3582 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 3583 3584 mutex_enter(&sc->sc_lock); 3585 3586 if (sc->sc_dying) { 3587 mutex_exit(&sc->sc_lock); 3588 return; 3589 } 3590 3591 struct isoc *isoc = &opipe->isoc; 3592 3593 DPRINTFN(1, "used=%d next=%d xfer=%p nframes=%d", 3594 isoc->inuse, isoc->next, xfer, xfer->ux_nframes); 3595 3596 if (isoc->next == -1) { 3597 /* Not in use yet, schedule it a few frames ahead. */ 3598 isoc->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3599 DPRINTFN(2,"start next=%d", isoc->next, 0, 0, 0); 3600 } 3601 3602 sitd = opipe->tail.itd; 3603 opipe->tail.itd = ox->ox_sitds[0]; 3604 ox->ox_sitds[0] = sitd; 3605 3606 buf = DMAADDR(&xfer->ux_dmabuf, 0); 3607 bp0 = OHCI_PAGE(buf); 3608 offs = OHCI_PAGE_OFFSET(buf); 3609 nframes = xfer->ux_nframes; 3610 xfer->ux_hcpriv = sitd; 3611 size_t j = 1; 3612 for (i = ncur = 0; i < nframes; i++, ncur++) { 3613 noffs = offs + xfer->ux_frlengths[i]; 3614 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3615 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3616 3617 /* Allocate next ITD */ 3618 nsitd = ox->ox_sitds[j++]; 3619 KASSERT(nsitd != NULL); 3620 KASSERT(j < ox->ox_nsitd); 3621 3622 /* Fill current ITD */ 3623 sitd->itd.itd_flags = HTOO32( 3624 OHCI_ITD_NOCC | 3625 OHCI_ITD_SET_SF(isoc->next) | 3626 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3627 OHCI_ITD_SET_FC(ncur)); 3628 sitd->itd.itd_bp0 = HTOO32(bp0); 3629 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3630 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3631 sitd->nextitd = nsitd; 3632 sitd->xfer = xfer; 3633 sitd->flags = 0; 3634 #ifdef DIAGNOSTIC 3635 sitd->isdone = false; 3636 #endif 3637 ohci_hash_add_itd(sc, sitd); 3638 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3639 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3640 3641 sitd = nsitd; 3642 isoc->next = isoc->next + ncur; 3643 bp0 = OHCI_PAGE(buf + offs); 3644 ncur = 0; 3645 } 3646 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3647 offs = noffs; 3648 } 3649 KASSERT(j <= ox->ox_nsitd); 3650 3651 /* point at sentinel */ 3652 tail = opipe->tail.itd; 3653 memset(&tail->itd, 0, sizeof(tail->itd)); 3654 tail->nextitd = NULL; 3655 tail->xfer = NULL; 3656 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->itd), 3657 BUS_DMASYNC_PREWRITE); 3658 3659 /* Fixup last used ITD */ 3660 sitd->itd.itd_flags = HTOO32( 3661 OHCI_ITD_NOCC | 3662 OHCI_ITD_SET_SF(isoc->next) | 3663 OHCI_ITD_SET_DI(0) | 3664 OHCI_ITD_SET_FC(ncur)); 3665 sitd->itd.itd_bp0 = HTOO32(bp0); 3666 sitd->itd.itd_nextitd = HTOO32(tail->physaddr); 3667 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3668 sitd->nextitd = tail; 3669 sitd->xfer = xfer; 3670 sitd->flags = OHCI_CALL_DONE; 3671 #ifdef DIAGNOSTIC 3672 sitd->isdone = false; 3673 #endif 3674 ohci_hash_add_itd(sc, sitd); 3675 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3676 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3677 3678 isoc->next = isoc->next + ncur; 3679 isoc->inuse += nframes; 3680 3681 /* XXX pretend we did it all */ 3682 xfer->ux_actlen = offs; 3683 xfer->ux_status = USBD_IN_PROGRESS; 3684 3685 #ifdef OHCI_DEBUG 3686 if (ohcidebug >= 5) { 3687 DPRINTF("frame=%d", O32TOH(sc->sc_hcca->hcca_frame_number), 3688 0, 0, 0); 3689 ohci_dump_itds(sc, xfer->ux_hcpriv); 3690 ohci_dump_ed(sc, sed); 3691 } 3692 #endif 3693 3694 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3695 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3696 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3697 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3698 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3699 sizeof(sed->ed.ed_flags), 3700 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3701 mutex_exit(&sc->sc_lock); 3702 } 3703 3704 usbd_status 3705 ohci_device_isoc_start(struct usbd_xfer *xfer) 3706 { 3707 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3708 3709 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3710 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 3711 3712 mutex_enter(&sc->sc_lock); 3713 3714 if (sc->sc_dying) { 3715 mutex_exit(&sc->sc_lock); 3716 return USBD_IOERROR; 3717 } 3718 3719 3720 #ifdef DIAGNOSTIC 3721 if (xfer->ux_status != USBD_IN_PROGRESS) 3722 printf("ohci_device_isoc_start: not in progress %p\n", xfer); 3723 #endif 3724 3725 /* XXX anything to do? */ 3726 3727 mutex_exit(&sc->sc_lock); 3728 3729 return USBD_IN_PROGRESS; 3730 } 3731 3732 void 3733 ohci_device_isoc_abort(struct usbd_xfer *xfer) 3734 { 3735 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3736 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3737 ohci_soft_ed_t *sed; 3738 ohci_soft_itd_t *sitd; 3739 3740 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3741 DPRINTFN(1, "xfer=%p", xfer, 0, 0, 0); 3742 3743 KASSERT(mutex_owned(&sc->sc_lock)); 3744 3745 /* Transfer is already done. */ 3746 if (xfer->ux_status != USBD_NOT_STARTED && 3747 xfer->ux_status != USBD_IN_PROGRESS) { 3748 printf("ohci_device_isoc_abort: early return\n"); 3749 goto done; 3750 } 3751 3752 /* Give xfer the requested abort code. */ 3753 xfer->ux_status = USBD_CANCELLED; 3754 3755 sed = opipe->sed; 3756 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3757 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3758 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3759 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3760 sizeof(sed->ed.ed_flags), 3761 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3762 3763 sitd = xfer->ux_hcpriv; 3764 KASSERT(sitd); 3765 3766 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3767 #ifdef DIAGNOSTIC 3768 DPRINTFN(1, "abort sets done sitd=%p", sitd, 0, 0, 0); 3769 sitd->isdone = true; 3770 #endif 3771 } 3772 3773 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3774 3775 /* Run callback. */ 3776 usb_transfer_complete(xfer); 3777 3778 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3779 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3780 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3781 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3782 3783 done: 3784 KASSERT(mutex_owned(&sc->sc_lock)); 3785 } 3786 3787 void 3788 ohci_device_isoc_done(struct usbd_xfer *xfer) 3789 { 3790 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3791 DPRINTFN(1, "xfer=%p", xfer, 0, 0, 0); 3792 } 3793 3794 usbd_status 3795 ohci_setup_isoc(struct usbd_pipe *pipe) 3796 { 3797 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3798 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3799 struct isoc *isoc = &opipe->isoc; 3800 3801 isoc->next = -1; 3802 isoc->inuse = 0; 3803 3804 mutex_enter(&sc->sc_lock); 3805 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3806 mutex_exit(&sc->sc_lock); 3807 3808 return USBD_NORMAL_COMPLETION; 3809 } 3810 3811 void 3812 ohci_device_isoc_close(struct usbd_pipe *pipe) 3813 { 3814 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3815 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3816 3817 KASSERT(mutex_owned(&sc->sc_lock)); 3818 3819 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3820 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3821 ohci_close_pipe(pipe, sc->sc_isoc_head); 3822 #ifdef DIAGNOSTIC 3823 opipe->tail.itd->isdone = true; 3824 #endif 3825 ohci_free_sitd_locked(sc, opipe->tail.itd); 3826 } 3827
Indexes created Fri Oct 03 02:09:57 GMT 2025