ohci.c revision 1.254.2.6
1 /* $NetBSD: ohci.c,v 1.254.2.6 2014/12/02 09:00:33 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * USB Open Host Controller driver. 38 * 39 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 40 * USB spec: http://www.usb.org/developers/docs/ 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.254.2.6 2014/12/02 09:00:33 skrll Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kmem.h> 49 #include <sys/kernel.h> 50 #include <sys/device.h> 51 #include <sys/select.h> 52 #include <sys/proc.h> 53 #include <sys/queue.h> 54 #include <sys/cpu.h> 55 56 #include <machine/endian.h> 57 58 #include <dev/usb/usb.h> 59 #include <dev/usb/usbdi.h> 60 #include <dev/usb/usbdivar.h> 61 #include <dev/usb/usb_mem.h> 62 #include <dev/usb/usb_quirks.h> 63 64 #include <dev/usb/ohcireg.h> 65 #include <dev/usb/ohcivar.h> 66 #include <dev/usb/usbroothub_subr.h> 67 68 69 70 #ifdef OHCI_DEBUG 71 #define DPRINTF(x) if (ohcidebug) printf x 72 #define DPRINTFN(n,x) if (ohcidebug>(n)) printf x 73 int ohcidebug = 0; 74 #else 75 #define DPRINTF(x) 76 #define DPRINTFN(n,x) 77 #endif 78 79 #if BYTE_ORDER == BIG_ENDIAN 80 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 81 #else 82 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 83 #endif 84 85 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 86 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 87 #define HTOO16(val) O16TOH(val) 88 #define HTOO32(val) O32TOH(val) 89 90 struct ohci_pipe; 91 92 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 93 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 94 95 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 96 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 97 98 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 99 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 100 101 Static void ohci_free_std_chain(ohci_softc_t *, ohci_soft_td_t *, 102 ohci_soft_td_t *); 103 Static usbd_status ohci_alloc_std_chain(struct ohci_pipe *, 104 ohci_softc_t *, int, int, usbd_xfer_handle, 105 ohci_soft_td_t *, ohci_soft_td_t **); 106 107 Static usbd_status ohci_open(usbd_pipe_handle); 108 Static void ohci_poll(struct usbd_bus *); 109 Static void ohci_softintr(void *); 110 Static void ohci_waitintr(ohci_softc_t *, usbd_xfer_handle); 111 Static void ohci_rhsc(ohci_softc_t *, usbd_xfer_handle); 112 Static void ohci_rhsc_softint(void *arg); 113 114 Static usbd_status ohci_device_request(usbd_xfer_handle xfer); 115 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 116 ohci_soft_ed_t *); 117 118 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 119 ohci_soft_ed_t *); 120 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 121 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 122 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 123 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 124 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 125 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 126 127 Static usbd_status ohci_setup_isoc(usbd_pipe_handle pipe); 128 Static void ohci_device_isoc_enter(usbd_xfer_handle); 129 130 Static usbd_xfer_handle ohci_allocx(struct usbd_bus *); 131 Static void ohci_freex(struct usbd_bus *, usbd_xfer_handle); 132 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 133 134 Static usbd_status ohci_root_ctrl_transfer(usbd_xfer_handle); 135 Static usbd_status ohci_root_ctrl_start(usbd_xfer_handle); 136 Static void ohci_root_ctrl_abort(usbd_xfer_handle); 137 Static void ohci_root_ctrl_close(usbd_pipe_handle); 138 Static void ohci_root_ctrl_done(usbd_xfer_handle); 139 140 Static usbd_status ohci_root_intr_transfer(usbd_xfer_handle); 141 Static usbd_status ohci_root_intr_start(usbd_xfer_handle); 142 Static void ohci_root_intr_abort(usbd_xfer_handle); 143 Static void ohci_root_intr_close(usbd_pipe_handle); 144 Static void ohci_root_intr_done(usbd_xfer_handle); 145 146 Static usbd_status ohci_device_ctrl_transfer(usbd_xfer_handle); 147 Static usbd_status ohci_device_ctrl_start(usbd_xfer_handle); 148 Static void ohci_device_ctrl_abort(usbd_xfer_handle); 149 Static void ohci_device_ctrl_close(usbd_pipe_handle); 150 Static void ohci_device_ctrl_done(usbd_xfer_handle); 151 152 Static usbd_status ohci_device_bulk_transfer(usbd_xfer_handle); 153 Static usbd_status ohci_device_bulk_start(usbd_xfer_handle); 154 Static void ohci_device_bulk_abort(usbd_xfer_handle); 155 Static void ohci_device_bulk_close(usbd_pipe_handle); 156 Static void ohci_device_bulk_done(usbd_xfer_handle); 157 158 Static usbd_status ohci_device_intr_transfer(usbd_xfer_handle); 159 Static usbd_status ohci_device_intr_start(usbd_xfer_handle); 160 Static void ohci_device_intr_abort(usbd_xfer_handle); 161 Static void ohci_device_intr_close(usbd_pipe_handle); 162 Static void ohci_device_intr_done(usbd_xfer_handle); 163 164 Static usbd_status ohci_device_isoc_transfer(usbd_xfer_handle); 165 Static usbd_status ohci_device_isoc_start(usbd_xfer_handle); 166 Static void ohci_device_isoc_abort(usbd_xfer_handle); 167 Static void ohci_device_isoc_close(usbd_pipe_handle); 168 Static void ohci_device_isoc_done(usbd_xfer_handle); 169 170 Static usbd_status ohci_device_setintr(ohci_softc_t *sc, 171 struct ohci_pipe *pipe, int ival); 172 173 Static void ohci_timeout(void *); 174 Static void ohci_timeout_task(void *); 175 Static void ohci_rhsc_enable(void *); 176 177 Static void ohci_close_pipe(usbd_pipe_handle, ohci_soft_ed_t *); 178 Static void ohci_abort_xfer(usbd_xfer_handle, usbd_status); 179 180 Static void ohci_device_clear_toggle(usbd_pipe_handle pipe); 181 Static void ohci_noop(usbd_pipe_handle pipe); 182 183 #ifdef OHCI_DEBUG 184 Static void ohci_dumpregs(ohci_softc_t *); 185 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 186 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 187 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 188 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 189 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 190 #endif 191 192 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 193 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 194 #define OWRITE1(sc, r, x) \ 195 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 196 #define OWRITE2(sc, r, x) \ 197 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 198 #define OWRITE4(sc, r, x) \ 199 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 200 201 static __inline uint32_t 202 OREAD4(ohci_softc_t *sc, bus_size_t r) 203 { 204 205 OBARR(sc); 206 return bus_space_read_4(sc->iot, sc->ioh, r); 207 } 208 209 /* Reverse the bits in a value 0 .. 31 */ 210 Static uint8_t revbits[OHCI_NO_INTRS] = 211 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 212 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 213 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 214 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 215 216 struct ohci_pipe { 217 struct usbd_pipe pipe; 218 ohci_soft_ed_t *sed; 219 union { 220 ohci_soft_td_t *td; 221 ohci_soft_itd_t *itd; 222 } tail; 223 /* Info needed for different pipe kinds. */ 224 union { 225 /* Control pipe */ 226 struct { 227 usb_dma_t reqdma; 228 u_int length; 229 ohci_soft_td_t *setup, *data, *stat; 230 } ctl; 231 /* Interrupt pipe */ 232 struct { 233 int nslots; 234 int pos; 235 } intr; 236 /* Bulk pipe */ 237 struct { 238 u_int length; 239 int isread; 240 } bulk; 241 /* Iso pipe */ 242 struct iso { 243 int next, inuse; 244 } iso; 245 } u; 246 }; 247 248 #define OHCI_INTR_ENDPT 1 249 250 Static const struct usbd_bus_methods ohci_bus_methods = { 251 .ubm_open = ohci_open, 252 .ubm_softint = ohci_softintr, 253 .ubm_dopoll = ohci_poll, 254 .ubm_allocx = ohci_allocx, 255 .ubm_freex = ohci_freex, 256 .ubm_getlock = ohci_get_lock, 257 .ubm_newdev = NULL, 258 }; 259 260 Static const struct usbd_pipe_methods ohci_root_ctrl_methods = { 261 .upm_transfer = ohci_root_ctrl_transfer, 262 .upm_start = ohci_root_ctrl_start, 263 .upm_abort = ohci_root_ctrl_abort, 264 .upm_close = ohci_root_ctrl_close, 265 .upm_cleartoggle = ohci_noop, 266 .upm_done = ohci_root_ctrl_done, 267 }; 268 269 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 270 .upm_transfer = ohci_root_intr_transfer, 271 .upm_start = ohci_root_intr_start, 272 .upm_abort = ohci_root_intr_abort, 273 .upm_close = ohci_root_intr_close, 274 .upm_cleartoggle = ohci_noop, 275 .upm_done = ohci_root_intr_done, 276 }; 277 278 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 279 .upm_transfer = ohci_device_ctrl_transfer, 280 .upm_start = ohci_device_ctrl_start, 281 .upm_abort = ohci_device_ctrl_abort, 282 .upm_close = ohci_device_ctrl_close, 283 .upm_cleartoggle = ohci_noop, 284 .upm_done = ohci_device_ctrl_done, 285 }; 286 287 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 288 .upm_transfer = ohci_device_intr_transfer, 289 .upm_start = ohci_device_intr_start, 290 .upm_abort = ohci_device_intr_abort, 291 .upm_close = ohci_device_intr_close, 292 .upm_cleartoggle = ohci_device_clear_toggle, 293 .upm_done = ohci_device_intr_done, 294 }; 295 296 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 297 .upm_transfer = ohci_device_bulk_transfer, 298 .upm_start = ohci_device_bulk_start, 299 .upm_abort = ohci_device_bulk_abort, 300 .upm_close = ohci_device_bulk_close, 301 .upm_cleartoggle = ohci_device_clear_toggle, 302 .upm_done = ohci_device_bulk_done, 303 }; 304 305 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 306 .upm_transfer = ohci_device_isoc_transfer, 307 .upm_start = ohci_device_isoc_start, 308 .upm_abort = ohci_device_isoc_abort, 309 .upm_close = ohci_device_isoc_close, 310 .upm_cleartoggle = ohci_noop, 311 .upm_done = ohci_device_isoc_done, 312 }; 313 314 int 315 ohci_activate(device_t self, enum devact act) 316 { 317 struct ohci_softc *sc = device_private(self); 318 319 switch (act) { 320 case DVACT_DEACTIVATE: 321 sc->sc_dying = 1; 322 return 0; 323 default: 324 return EOPNOTSUPP; 325 } 326 } 327 328 void 329 ohci_childdet(device_t self, device_t child) 330 { 331 struct ohci_softc *sc = device_private(self); 332 333 KASSERT(sc->sc_child == child); 334 sc->sc_child = NULL; 335 } 336 337 int 338 ohci_detach(struct ohci_softc *sc, int flags) 339 { 340 int rv = 0; 341 342 if (sc->sc_child != NULL) 343 rv = config_detach(sc->sc_child, flags); 344 345 if (rv != 0) 346 return (rv); 347 348 callout_halt(&sc->sc_tmo_rhsc, &sc->sc_lock); 349 350 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 351 callout_destroy(&sc->sc_tmo_rhsc); 352 353 softint_disestablish(sc->sc_rhsc_si); 354 355 cv_destroy(&sc->sc_softwake_cv); 356 357 mutex_destroy(&sc->sc_lock); 358 mutex_destroy(&sc->sc_intr_lock); 359 360 if (sc->sc_hcca != NULL) 361 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 362 pool_cache_destroy(sc->sc_xferpool); 363 364 return (rv); 365 } 366 367 ohci_soft_ed_t * 368 ohci_alloc_sed(ohci_softc_t *sc) 369 { 370 ohci_soft_ed_t *sed; 371 usbd_status err; 372 int i, offs; 373 usb_dma_t dma; 374 375 if (sc->sc_freeeds == NULL) { 376 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n")); 377 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 378 OHCI_ED_ALIGN, &dma); 379 if (err) 380 return (0); 381 for (i = 0; i < OHCI_SED_CHUNK; i++) { 382 offs = i * OHCI_SED_SIZE; 383 sed = KERNADDR(&dma, offs); 384 sed->physaddr = DMAADDR(&dma, offs); 385 sed->dma = dma; 386 sed->offs = offs; 387 sed->next = sc->sc_freeeds; 388 sc->sc_freeeds = sed; 389 } 390 } 391 sed = sc->sc_freeeds; 392 sc->sc_freeeds = sed->next; 393 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 394 sed->next = 0; 395 return (sed); 396 } 397 398 void 399 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 400 { 401 sed->next = sc->sc_freeeds; 402 sc->sc_freeeds = sed; 403 } 404 405 ohci_soft_td_t * 406 ohci_alloc_std(ohci_softc_t *sc) 407 { 408 ohci_soft_td_t *std; 409 usbd_status err; 410 int i, offs; 411 usb_dma_t dma; 412 413 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 414 415 if (sc->sc_freetds == NULL) { 416 DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n")); 417 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 418 OHCI_TD_ALIGN, &dma); 419 if (err) 420 return (NULL); 421 for(i = 0; i < OHCI_STD_CHUNK; i++) { 422 offs = i * OHCI_STD_SIZE; 423 std = KERNADDR(&dma, offs); 424 std->physaddr = DMAADDR(&dma, offs); 425 std->dma = dma; 426 std->offs = offs; 427 std->nexttd = sc->sc_freetds; 428 sc->sc_freetds = std; 429 } 430 } 431 432 std = sc->sc_freetds; 433 sc->sc_freetds = std->nexttd; 434 memset(&std->td, 0, sizeof(ohci_td_t)); 435 std->nexttd = NULL; 436 std->xfer = NULL; 437 ohci_hash_add_td(sc, std); 438 439 return (std); 440 } 441 442 void 443 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 444 { 445 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 446 447 ohci_hash_rem_td(sc, std); 448 std->nexttd = sc->sc_freetds; 449 sc->sc_freetds = std; 450 } 451 452 usbd_status 453 ohci_alloc_std_chain(struct ohci_pipe *opipe, ohci_softc_t *sc, 454 int alen, int rd, usbd_xfer_handle xfer, 455 ohci_soft_td_t *sp, ohci_soft_td_t **ep) 456 { 457 ohci_soft_td_t *next, *cur; 458 ohci_physaddr_t dataphys, dataphysend; 459 uint32_t tdflags; 460 int len, curlen; 461 usb_dma_t *dma = &xfer->dmabuf; 462 uint16_t flags = xfer->flags; 463 464 DPRINTFN(alen < 4096,("ohci_alloc_std_chain: start len=%d\n", alen)); 465 466 KASSERT(mutex_owned(&sc->sc_lock)); 467 468 len = alen; 469 cur = sp; 470 dataphys = DMAADDR(dma, 0); 471 dataphysend = OHCI_PAGE(dataphys + len - 1); 472 usb_syncmem(dma, 0, len, 473 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 474 tdflags = HTOO32( 475 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 476 (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) | 477 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 478 479 for (;;) { 480 next = ohci_alloc_std(sc); 481 if (next == NULL) 482 goto nomem; 483 484 /* The OHCI hardware can handle at most one page crossing. */ 485 if (OHCI_PAGE(dataphys) == dataphysend || 486 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 487 /* we can handle it in this TD */ 488 curlen = len; 489 } else { 490 /* must use multiple TDs, fill as much as possible. */ 491 curlen = 2 * OHCI_PAGE_SIZE - 492 (dataphys & (OHCI_PAGE_SIZE-1)); 493 /* the length must be a multiple of the max size */ 494 curlen -= curlen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize); 495 #ifdef DIAGNOSTIC 496 if (curlen == 0) 497 panic("ohci_alloc_std: curlen == 0"); 498 #endif 499 } 500 DPRINTFN(4,("ohci_alloc_std_chain: dataphys=0x%08x " 501 "dataphysend=0x%08x len=%d curlen=%d\n", 502 dataphys, dataphysend, 503 len, curlen)); 504 len -= curlen; 505 506 cur->td.td_flags = tdflags; 507 cur->td.td_cbp = HTOO32(dataphys); 508 cur->nexttd = next; 509 cur->td.td_nexttd = HTOO32(next->physaddr); 510 cur->td.td_be = HTOO32(dataphys + curlen - 1); 511 cur->len = curlen; 512 cur->flags = OHCI_ADD_LEN; 513 cur->xfer = xfer; 514 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 515 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 516 DPRINTFN(10,("ohci_alloc_std_chain: cbp=0x%08x be=0x%08x\n", 517 dataphys, dataphys + curlen - 1)); 518 if (len == 0) 519 break; 520 DPRINTFN(10,("ohci_alloc_std_chain: extend chain\n")); 521 dataphys += curlen; 522 cur = next; 523 } 524 if (!rd && (flags & USBD_FORCE_SHORT_XFER) && 525 alen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize) == 0) { 526 /* Force a 0 length transfer at the end. */ 527 528 cur = next; 529 next = ohci_alloc_std(sc); 530 if (next == NULL) 531 goto nomem; 532 533 cur->td.td_flags = tdflags; 534 cur->td.td_cbp = 0; /* indicate 0 length packet */ 535 cur->nexttd = next; 536 cur->td.td_nexttd = HTOO32(next->physaddr); 537 cur->td.td_be = ~0; 538 cur->len = 0; 539 cur->flags = 0; 540 cur->xfer = xfer; 541 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 542 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 543 DPRINTFN(2,("ohci_alloc_std_chain: add 0 xfer\n")); 544 } 545 *ep = cur; 546 547 return (USBD_NORMAL_COMPLETION); 548 549 nomem: 550 551 /* Don't free sp - let the caller do that */ 552 ohci_free_std_chain(sc, sp->nexttd, NULL); 553 554 return (USBD_NOMEM); 555 } 556 557 Static void 558 ohci_free_std_chain(ohci_softc_t *sc, ohci_soft_td_t *std, 559 ohci_soft_td_t *stdend) 560 { 561 ohci_soft_td_t *p; 562 563 for (; std != stdend; std = p) { 564 p = std->nexttd; 565 ohci_free_std(sc, std); 566 } 567 } 568 569 ohci_soft_itd_t * 570 ohci_alloc_sitd(ohci_softc_t *sc) 571 { 572 ohci_soft_itd_t *sitd; 573 usbd_status err; 574 int i, offs; 575 usb_dma_t dma; 576 577 if (sc->sc_freeitds == NULL) { 578 DPRINTFN(2, ("ohci_alloc_sitd: allocating chunk\n")); 579 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 580 OHCI_ITD_ALIGN, &dma); 581 if (err) 582 return (NULL); 583 for(i = 0; i < OHCI_SITD_CHUNK; i++) { 584 offs = i * OHCI_SITD_SIZE; 585 sitd = KERNADDR(&dma, offs); 586 sitd->physaddr = DMAADDR(&dma, offs); 587 sitd->dma = dma; 588 sitd->offs = offs; 589 sitd->nextitd = sc->sc_freeitds; 590 sc->sc_freeitds = sitd; 591 } 592 } 593 594 sitd = sc->sc_freeitds; 595 sc->sc_freeitds = sitd->nextitd; 596 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 597 sitd->nextitd = NULL; 598 sitd->xfer = NULL; 599 ohci_hash_add_itd(sc, sitd); 600 601 #ifdef DIAGNOSTIC 602 sitd->isdone = 0; 603 #endif 604 605 return (sitd); 606 } 607 608 void 609 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 610 { 611 612 DPRINTFN(10,("ohci_free_sitd: sitd=%p\n", sitd)); 613 614 #ifdef DIAGNOSTIC 615 if (!sitd->isdone) { 616 panic("ohci_free_sitd: sitd=%p not done", sitd); 617 return; 618 } 619 /* Warn double free */ 620 sitd->isdone = 0; 621 #endif 622 623 ohci_hash_rem_itd(sc, sitd); 624 sitd->nextitd = sc->sc_freeitds; 625 sc->sc_freeitds = sitd; 626 } 627 628 usbd_status 629 ohci_init(ohci_softc_t *sc) 630 { 631 ohci_soft_ed_t *sed, *psed; 632 usbd_status err; 633 int i; 634 uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */; 635 636 DPRINTF(("ohci_init: start\n")); 637 aprint_normal_dev(sc->sc_dev, ""); 638 639 sc->sc_hcca = NULL; 640 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 641 642 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 643 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 644 cv_init(&sc->sc_softwake_cv, "ohciab"); 645 646 sc->sc_rhsc_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 647 ohci_rhsc_softint, sc); 648 649 for (i = 0; i < OHCI_HASH_SIZE; i++) 650 LIST_INIT(&sc->sc_hash_tds[i]); 651 for (i = 0; i < OHCI_HASH_SIZE; i++) 652 LIST_INIT(&sc->sc_hash_itds[i]); 653 654 sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0, 655 "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL); 656 657 rev = OREAD4(sc, OHCI_REVISION); 658 aprint_normal("OHCI version %d.%d%s\n", 659 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 660 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 661 662 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 663 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 664 sc->sc_bus.usbrev = USBREV_UNKNOWN; 665 return (USBD_INVAL); 666 } 667 sc->sc_bus.usbrev = USBREV_1_0; 668 sc->sc_bus.usedma = true; 669 670 /* XXX determine alignment by R/W */ 671 /* Allocate the HCCA area. */ 672 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 673 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 674 if (err) { 675 sc->sc_hcca = NULL; 676 return err; 677 } 678 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 679 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 680 681 sc->sc_eintrs = OHCI_NORMAL_INTRS; 682 683 /* Allocate dummy ED that starts the control list. */ 684 sc->sc_ctrl_head = ohci_alloc_sed(sc); 685 if (sc->sc_ctrl_head == NULL) { 686 err = USBD_NOMEM; 687 goto bad1; 688 } 689 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 690 691 /* Allocate dummy ED that starts the bulk list. */ 692 sc->sc_bulk_head = ohci_alloc_sed(sc); 693 if (sc->sc_bulk_head == NULL) { 694 err = USBD_NOMEM; 695 goto bad2; 696 } 697 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 698 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 699 sizeof(sc->sc_bulk_head->ed), 700 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 701 702 /* Allocate dummy ED that starts the isochronous list. */ 703 sc->sc_isoc_head = ohci_alloc_sed(sc); 704 if (sc->sc_isoc_head == NULL) { 705 err = USBD_NOMEM; 706 goto bad3; 707 } 708 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 709 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 710 sizeof(sc->sc_isoc_head->ed), 711 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 712 713 /* Allocate all the dummy EDs that make up the interrupt tree. */ 714 for (i = 0; i < OHCI_NO_EDS; i++) { 715 sed = ohci_alloc_sed(sc); 716 if (sed == NULL) { 717 while (--i >= 0) 718 ohci_free_sed(sc, sc->sc_eds[i]); 719 err = USBD_NOMEM; 720 goto bad4; 721 } 722 /* All ED fields are set to 0. */ 723 sc->sc_eds[i] = sed; 724 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 725 if (i != 0) 726 psed = sc->sc_eds[(i-1) / 2]; 727 else 728 psed= sc->sc_isoc_head; 729 sed->next = psed; 730 sed->ed.ed_nexted = HTOO32(psed->physaddr); 731 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 732 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 733 } 734 /* 735 * Fill HCCA interrupt table. The bit reversal is to get 736 * the tree set up properly to spread the interrupts. 737 */ 738 for (i = 0; i < OHCI_NO_INTRS; i++) 739 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 740 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 741 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 742 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 743 744 #ifdef OHCI_DEBUG 745 if (ohcidebug > 15) { 746 for (i = 0; i < OHCI_NO_EDS; i++) { 747 printf("ed#%d ", i); 748 ohci_dump_ed(sc, sc->sc_eds[i]); 749 } 750 printf("iso "); 751 ohci_dump_ed(sc, sc->sc_isoc_head); 752 } 753 #endif 754 755 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 756 ctl = OREAD4(sc, OHCI_CONTROL); 757 rwc = ctl & OHCI_RWC; 758 fm = OREAD4(sc, OHCI_FM_INTERVAL); 759 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 760 /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */ 761 762 /* Determine in what context we are running. */ 763 if (ctl & OHCI_IR) { 764 /* SMM active, request change */ 765 DPRINTF(("ohci_init: SMM active, request owner change\n")); 766 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 767 (OHCI_OC | OHCI_MIE)) 768 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 769 s = OREAD4(sc, OHCI_COMMAND_STATUS); 770 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 771 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 772 usb_delay_ms(&sc->sc_bus, 1); 773 ctl = OREAD4(sc, OHCI_CONTROL); 774 } 775 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 776 if ((ctl & OHCI_IR) == 0) { 777 aprint_error_dev(sc->sc_dev, 778 "SMM does not respond, resetting\n"); 779 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 780 goto reset; 781 } 782 #if 0 783 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 784 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 785 /* BIOS started controller. */ 786 DPRINTF(("ohci_init: BIOS active\n")); 787 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 788 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 789 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 790 } 791 #endif 792 } else { 793 DPRINTF(("ohci_init: cold started\n")); 794 reset: 795 /* Controller was cold started. */ 796 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 797 } 798 799 /* 800 * This reset should not be necessary according to the OHCI spec, but 801 * without it some controllers do not start. 802 */ 803 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 804 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 805 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 806 807 /* We now own the host controller and the bus has been reset. */ 808 809 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 810 /* Nominal time for a reset is 10 us. */ 811 for (i = 0; i < 10; i++) { 812 delay(10); 813 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 814 if (!hcr) 815 break; 816 } 817 if (hcr) { 818 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 819 err = USBD_IOERROR; 820 goto bad5; 821 } 822 #ifdef OHCI_DEBUG 823 if (ohcidebug > 15) 824 ohci_dumpregs(sc); 825 #endif 826 827 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 828 829 /* Set up HC registers. */ 830 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 831 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 832 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 833 /* disable all interrupts and then switch on all desired interrupts */ 834 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 835 /* switch on desired functional features */ 836 ctl = OREAD4(sc, OHCI_CONTROL); 837 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 838 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 839 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 840 /* And finally start it! */ 841 OWRITE4(sc, OHCI_CONTROL, ctl); 842 843 /* 844 * The controller is now OPERATIONAL. Set a some final 845 * registers that should be set earlier, but that the 846 * controller ignores when in the SUSPEND state. 847 */ 848 ival = OHCI_GET_IVAL(fm); 849 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 850 fm |= OHCI_FSMPS(ival) | ival; 851 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 852 per = OHCI_PERIODIC(ival); /* 90% periodic */ 853 OWRITE4(sc, OHCI_PERIODIC_START, per); 854 855 if (sc->sc_flags & OHCIF_SUPERIO) { 856 /* no overcurrent protection */ 857 desca |= OHCI_NOCP; 858 /* 859 * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning 860 * that 861 * - ports are always power switched 862 * - don't wait for powered root hub port 863 */ 864 desca &= ~(__SHIFTIN(0xff, OHCI_POTPGT_MASK) | OHCI_NPS); 865 } 866 867 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 868 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 869 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 870 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 871 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 872 873 /* 874 * The AMD756 requires a delay before re-reading the register, 875 * otherwise it will occasionally report 0 ports. 876 */ 877 sc->sc_noport = 0; 878 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 879 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 880 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 881 } 882 883 #ifdef OHCI_DEBUG 884 if (ohcidebug > 5) 885 ohci_dumpregs(sc); 886 #endif 887 888 /* Set up the bus struct. */ 889 sc->sc_bus.methods = &ohci_bus_methods; 890 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe); 891 892 sc->sc_control = sc->sc_intre = 0; 893 894 /* Finally, turn on interrupts. */ 895 DPRINTFN(1,("ohci_init: enabling %#x\n", sc->sc_eintrs | OHCI_MIE)); 896 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 897 898 return (USBD_NORMAL_COMPLETION); 899 900 bad5: 901 for (i = 0; i < OHCI_NO_EDS; i++) 902 ohci_free_sed(sc, sc->sc_eds[i]); 903 bad4: 904 ohci_free_sed(sc, sc->sc_isoc_head); 905 bad3: 906 ohci_free_sed(sc, sc->sc_bulk_head); 907 bad2: 908 ohci_free_sed(sc, sc->sc_ctrl_head); 909 bad1: 910 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 911 sc->sc_hcca = NULL; 912 return (err); 913 } 914 915 usbd_xfer_handle 916 ohci_allocx(struct usbd_bus *bus) 917 { 918 struct ohci_softc *sc = bus->hci_private; 919 usbd_xfer_handle xfer; 920 921 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 922 if (xfer != NULL) { 923 memset(xfer, 0, sizeof(struct ohci_xfer)); 924 #ifdef DIAGNOSTIC 925 xfer->busy_free = XFER_BUSY; 926 #endif 927 } 928 return (xfer); 929 } 930 931 void 932 ohci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 933 { 934 struct ohci_softc *sc = bus->hci_private; 935 936 #ifdef DIAGNOSTIC 937 if (xfer->busy_free != XFER_BUSY) { 938 printf("ohci_freex: xfer=%p not busy, 0x%08x\n", xfer, 939 xfer->busy_free); 940 } 941 xfer->busy_free = XFER_FREE; 942 #endif 943 pool_cache_put(sc->sc_xferpool, xfer); 944 } 945 946 Static void 947 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 948 { 949 struct ohci_softc *sc = bus->hci_private; 950 951 *lock = &sc->sc_lock; 952 } 953 954 /* 955 * Shut down the controller when the system is going down. 956 */ 957 bool 958 ohci_shutdown(device_t self, int flags) 959 { 960 ohci_softc_t *sc = device_private(self); 961 962 DPRINTF(("ohci_shutdown: stopping the HC\n")); 963 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 964 return true; 965 } 966 967 bool 968 ohci_resume(device_t dv, const pmf_qual_t *qual) 969 { 970 ohci_softc_t *sc = device_private(dv); 971 uint32_t ctl; 972 973 mutex_spin_enter(&sc->sc_intr_lock); 974 sc->sc_bus.use_polling++; 975 mutex_spin_exit(&sc->sc_intr_lock); 976 977 /* Some broken BIOSes do not recover these values */ 978 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 979 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 980 sc->sc_ctrl_head->physaddr); 981 OWRITE4(sc, OHCI_BULK_HEAD_ED, 982 sc->sc_bulk_head->physaddr); 983 if (sc->sc_intre) 984 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 985 (OHCI_ALL_INTRS | OHCI_MIE)); 986 if (sc->sc_control) 987 ctl = sc->sc_control; 988 else 989 ctl = OREAD4(sc, OHCI_CONTROL); 990 ctl |= OHCI_HCFS_RESUME; 991 OWRITE4(sc, OHCI_CONTROL, ctl); 992 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 993 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 994 OWRITE4(sc, OHCI_CONTROL, ctl); 995 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 996 sc->sc_control = sc->sc_intre = 0; 997 998 mutex_spin_enter(&sc->sc_intr_lock); 999 sc->sc_bus.use_polling--; 1000 mutex_spin_exit(&sc->sc_intr_lock); 1001 1002 return true; 1003 } 1004 1005 bool 1006 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1007 { 1008 ohci_softc_t *sc = device_private(dv); 1009 uint32_t ctl; 1010 1011 mutex_spin_enter(&sc->sc_intr_lock); 1012 sc->sc_bus.use_polling++; 1013 mutex_spin_exit(&sc->sc_intr_lock); 1014 1015 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1016 if (sc->sc_control == 0) { 1017 /* 1018 * Preserve register values, in case that BIOS 1019 * does not recover them. 1020 */ 1021 sc->sc_control = ctl; 1022 sc->sc_intre = OREAD4(sc, 1023 OHCI_INTERRUPT_ENABLE); 1024 } 1025 ctl |= OHCI_HCFS_SUSPEND; 1026 OWRITE4(sc, OHCI_CONTROL, ctl); 1027 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1028 1029 mutex_spin_enter(&sc->sc_intr_lock); 1030 sc->sc_bus.use_polling--; 1031 mutex_spin_exit(&sc->sc_intr_lock); 1032 1033 return true; 1034 } 1035 1036 #ifdef OHCI_DEBUG 1037 void 1038 ohci_dumpregs(ohci_softc_t *sc) 1039 { 1040 DPRINTF(("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 1041 OREAD4(sc, OHCI_REVISION), 1042 OREAD4(sc, OHCI_CONTROL), 1043 OREAD4(sc, OHCI_COMMAND_STATUS))); 1044 DPRINTF((" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 1045 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1046 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1047 OREAD4(sc, OHCI_INTERRUPT_DISABLE))); 1048 DPRINTF((" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 1049 OREAD4(sc, OHCI_HCCA), 1050 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1051 OREAD4(sc, OHCI_CONTROL_HEAD_ED))); 1052 DPRINTF((" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 1053 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1054 OREAD4(sc, OHCI_BULK_HEAD_ED), 1055 OREAD4(sc, OHCI_BULK_CURRENT_ED))); 1056 DPRINTF((" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 1057 OREAD4(sc, OHCI_DONE_HEAD), 1058 OREAD4(sc, OHCI_FM_INTERVAL), 1059 OREAD4(sc, OHCI_FM_REMAINING))); 1060 DPRINTF((" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 1061 OREAD4(sc, OHCI_FM_NUMBER), 1062 OREAD4(sc, OHCI_PERIODIC_START), 1063 OREAD4(sc, OHCI_LS_THRESHOLD))); 1064 DPRINTF((" desca=0x%08x descb=0x%08x stat=0x%08x\n", 1065 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1066 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1067 OREAD4(sc, OHCI_RH_STATUS))); 1068 DPRINTF((" port1=0x%08x port2=0x%08x\n", 1069 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1070 OREAD4(sc, OHCI_RH_PORT_STATUS(2)))); 1071 DPRINTF((" HCCA: frame_number=0x%04x done_head=0x%08x\n", 1072 O32TOH(sc->sc_hcca->hcca_frame_number), 1073 O32TOH(sc->sc_hcca->hcca_done_head))); 1074 } 1075 #endif 1076 1077 Static int ohci_intr1(ohci_softc_t *); 1078 1079 int 1080 ohci_intr(void *p) 1081 { 1082 ohci_softc_t *sc = p; 1083 int ret = 0; 1084 1085 if (sc == NULL) 1086 return (0); 1087 1088 mutex_spin_enter(&sc->sc_intr_lock); 1089 1090 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1091 goto done; 1092 1093 /* If we get an interrupt while polling, then just ignore it. */ 1094 if (sc->sc_bus.use_polling) { 1095 #ifdef DIAGNOSTIC 1096 DPRINTFN(16, ("ohci_intr: ignored interrupt while polling\n")); 1097 #endif 1098 /* for level triggered intrs, should do something to ack */ 1099 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1100 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1101 1102 goto done; 1103 } 1104 1105 ret = ohci_intr1(sc); 1106 1107 done: 1108 mutex_spin_exit(&sc->sc_intr_lock); 1109 return ret; 1110 } 1111 1112 Static int 1113 ohci_intr1(ohci_softc_t *sc) 1114 { 1115 uint32_t intrs, eintrs; 1116 1117 DPRINTFN(14,("ohci_intr1: enter\n")); 1118 1119 /* In case the interrupt occurs before initialization has completed. */ 1120 if (sc == NULL || sc->sc_hcca == NULL) { 1121 #ifdef DIAGNOSTIC 1122 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1123 #endif 1124 return (0); 1125 } 1126 1127 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1128 1129 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1130 if (!intrs) 1131 return (0); 1132 1133 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); /* Acknowledge */ 1134 eintrs = intrs & sc->sc_eintrs; 1135 DPRINTFN(7, ("ohci_intr: sc=%p intrs=%#x(%#x) eintrs=%#x(%#x)\n", 1136 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), 1137 (u_int)eintrs, sc->sc_eintrs)); 1138 1139 if (!eintrs) { 1140 return (0); 1141 } 1142 1143 if (eintrs & OHCI_SO) { 1144 sc->sc_overrun_cnt++; 1145 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1146 printf("%s: %u scheduling overruns\n", 1147 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1148 sc->sc_overrun_cnt = 0; 1149 } 1150 /* XXX do what */ 1151 eintrs &= ~OHCI_SO; 1152 } 1153 if (eintrs & OHCI_WDH) { 1154 /* 1155 * We block the interrupt below, and reenable it later from 1156 * ohci_softintr(). 1157 */ 1158 usb_schedsoftintr(&sc->sc_bus); 1159 } 1160 if (eintrs & OHCI_RD) { 1161 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1162 /* XXX process resume detect */ 1163 } 1164 if (eintrs & OHCI_UE) { 1165 printf("%s: unrecoverable error, controller halted\n", 1166 device_xname(sc->sc_dev)); 1167 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1168 /* XXX what else */ 1169 } 1170 if (eintrs & OHCI_RHSC) { 1171 /* 1172 * We block the interrupt below, and reenable it later from 1173 * a timeout. 1174 */ 1175 softint_schedule(sc->sc_rhsc_si); 1176 } 1177 1178 if (eintrs != 0) { 1179 /* Block unprocessed interrupts. */ 1180 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1181 sc->sc_eintrs &= ~eintrs; 1182 DPRINTFN(1, ("%s: blocking intrs 0x%x\n", 1183 device_xname(sc->sc_dev), eintrs)); 1184 } 1185 1186 return (1); 1187 } 1188 1189 void 1190 ohci_rhsc_enable(void *v_sc) 1191 { 1192 ohci_softc_t *sc = v_sc; 1193 1194 DPRINTFN(1, ("%s: %s\n", __func__, device_xname(sc->sc_dev))); 1195 mutex_spin_enter(&sc->sc_intr_lock); 1196 sc->sc_eintrs |= OHCI_RHSC; 1197 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1198 mutex_spin_exit(&sc->sc_intr_lock); 1199 } 1200 1201 #ifdef OHCI_DEBUG 1202 const char *ohci_cc_strs[] = { 1203 "NO_ERROR", 1204 "CRC", 1205 "BIT_STUFFING", 1206 "DATA_TOGGLE_MISMATCH", 1207 "STALL", 1208 "DEVICE_NOT_RESPONDING", 1209 "PID_CHECK_FAILURE", 1210 "UNEXPECTED_PID", 1211 "DATA_OVERRUN", 1212 "DATA_UNDERRUN", 1213 "BUFFER_OVERRUN", 1214 "BUFFER_UNDERRUN", 1215 "reserved", 1216 "reserved", 1217 "NOT_ACCESSED", 1218 "NOT_ACCESSED", 1219 }; 1220 #endif 1221 1222 void 1223 ohci_softintr(void *v) 1224 { 1225 struct usbd_bus *bus = v; 1226 ohci_softc_t *sc = bus->hci_private; 1227 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1228 ohci_soft_td_t *std, *sdone, *stdnext; 1229 usbd_xfer_handle xfer; 1230 struct ohci_pipe *opipe; 1231 int len, cc; 1232 int i, j, actlen, iframes, uedir; 1233 ohci_physaddr_t done; 1234 1235 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1236 1237 DPRINTFN(10,("ohci_softintr: enter\n")); 1238 1239 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1240 sizeof(sc->sc_hcca->hcca_done_head), 1241 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1242 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1243 sc->sc_hcca->hcca_done_head = 0; 1244 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1245 sizeof(sc->sc_hcca->hcca_done_head), 1246 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1247 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1248 sc->sc_eintrs |= OHCI_WDH; 1249 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1250 1251 /* Reverse the done list. */ 1252 for (sdone = NULL, sidone = NULL; done != 0; ) { 1253 std = ohci_hash_find_td(sc, done); 1254 if (std != NULL) { 1255 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1256 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1257 std->dnext = sdone; 1258 done = O32TOH(std->td.td_nexttd); 1259 sdone = std; 1260 DPRINTFN(10,("add TD %p\n", std)); 1261 continue; 1262 } 1263 sitd = ohci_hash_find_itd(sc, done); 1264 if (sitd != NULL) { 1265 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1266 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1267 sitd->dnext = sidone; 1268 done = O32TOH(sitd->itd.itd_nextitd); 1269 sidone = sitd; 1270 DPRINTFN(5,("add ITD %p\n", sitd)); 1271 continue; 1272 } 1273 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1274 (u_long)done); 1275 break; 1276 } 1277 1278 DPRINTFN(10,("ohci_softintr: sdone=%p sidone=%p\n", sdone, sidone)); 1279 1280 #ifdef OHCI_DEBUG 1281 if (ohcidebug > 10) { 1282 DPRINTF(("ohci_process_done: TD done:\n")); 1283 for (std = sdone; std; std = std->dnext) 1284 ohci_dump_td(sc, std); 1285 } 1286 #endif 1287 1288 for (std = sdone; std; std = stdnext) { 1289 xfer = std->xfer; 1290 stdnext = std->dnext; 1291 DPRINTFN(10, ("ohci_process_done: std=%p xfer=%p hcpriv=%p\n", 1292 std, xfer, xfer ? xfer->hcpriv : 0)); 1293 if (xfer == NULL) { 1294 /* 1295 * xfer == NULL: There seems to be no xfer associated 1296 * with this TD. It is tailp that happened to end up on 1297 * the done queue. 1298 * Shouldn't happen, but some chips are broken(?). 1299 */ 1300 continue; 1301 } 1302 if (xfer->status == USBD_CANCELLED || 1303 xfer->status == USBD_TIMEOUT) { 1304 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1305 xfer)); 1306 /* Handled by abort routine. */ 1307 continue; 1308 } 1309 callout_stop(&xfer->timeout_handle); 1310 1311 len = std->len; 1312 if (std->td.td_cbp != 0) 1313 len -= O32TOH(std->td.td_be) - 1314 O32TOH(std->td.td_cbp) + 1; 1315 DPRINTFN(10, ("ohci_process_done: len=%d, flags=0x%x\n", len, 1316 std->flags)); 1317 if (std->flags & OHCI_ADD_LEN) 1318 xfer->actlen += len; 1319 1320 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1321 if (cc == OHCI_CC_NO_ERROR) { 1322 if (std->flags & OHCI_CALL_DONE) { 1323 xfer->status = USBD_NORMAL_COMPLETION; 1324 usb_transfer_complete(xfer); 1325 } 1326 ohci_free_std(sc, std); 1327 } else { 1328 /* 1329 * Endpoint is halted. First unlink all the TDs 1330 * belonging to the failed transfer, and then restart 1331 * the endpoint. 1332 */ 1333 ohci_soft_td_t *p, *n; 1334 opipe = (struct ohci_pipe *)xfer->pipe; 1335 1336 DPRINTFN(15,("ohci_process_done: error cc=%d (%s)\n", 1337 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 1338 ohci_cc_strs[OHCI_TD_GET_CC(O32TOH(std->td.td_flags))])); 1339 1340 /* remove TDs */ 1341 for (p = std; p->xfer == xfer; p = n) { 1342 n = p->nexttd; 1343 ohci_free_std(sc, p); 1344 } 1345 1346 /* clear halt */ 1347 opipe->sed->ed.ed_headp = HTOO32(p->physaddr); 1348 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1349 1350 if (cc == OHCI_CC_STALL) 1351 xfer->status = USBD_STALLED; 1352 else 1353 xfer->status = USBD_IOERROR; 1354 usb_transfer_complete(xfer); 1355 } 1356 } 1357 1358 #ifdef OHCI_DEBUG 1359 if (ohcidebug > 10) { 1360 DPRINTF(("ohci_softintr: ITD done:\n")); 1361 for (sitd = sidone; sitd; sitd = sitd->dnext) 1362 ohci_dump_itd(sc, sitd); 1363 } 1364 #endif 1365 1366 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1367 xfer = sitd->xfer; 1368 sitdnext = sitd->dnext; 1369 DPRINTFN(1, ("ohci_process_done: sitd=%p xfer=%p hcpriv=%p\n", 1370 sitd, xfer, xfer ? xfer->hcpriv : 0)); 1371 if (xfer == NULL) 1372 continue; 1373 if (xfer->status == USBD_CANCELLED || 1374 xfer->status == USBD_TIMEOUT) { 1375 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1376 xfer)); 1377 /* Handled by abort routine. */ 1378 continue; 1379 } 1380 #ifdef DIAGNOSTIC 1381 if (sitd->isdone) 1382 printf("ohci_softintr: sitd=%p is done\n", sitd); 1383 sitd->isdone = 1; 1384 #endif 1385 if (sitd->flags & OHCI_CALL_DONE) { 1386 ohci_soft_itd_t *next; 1387 1388 opipe = (struct ohci_pipe *)xfer->pipe; 1389 opipe->u.iso.inuse -= xfer->nframes; 1390 uedir = UE_GET_DIR(xfer->pipe->endpoint->edesc-> 1391 bEndpointAddress); 1392 xfer->status = USBD_NORMAL_COMPLETION; 1393 actlen = 0; 1394 for (i = 0, sitd = xfer->hcpriv;; 1395 sitd = next) { 1396 next = sitd->nextitd; 1397 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1398 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1399 xfer->status = USBD_IOERROR; 1400 /* For input, update frlengths with actual */ 1401 /* XXX anything necessary for output? */ 1402 if (uedir == UE_DIR_IN && 1403 xfer->status == USBD_NORMAL_COMPLETION) { 1404 iframes = OHCI_ITD_GET_FC(O32TOH( 1405 sitd->itd.itd_flags)); 1406 for (j = 0; j < iframes; i++, j++) { 1407 len = O16TOH(sitd-> 1408 itd.itd_offset[j]); 1409 if ((OHCI_ITD_PSW_GET_CC(len) & 1410 OHCI_CC_NOT_ACCESSED_MASK) 1411 == OHCI_CC_NOT_ACCESSED) 1412 len = 0; 1413 else 1414 len = OHCI_ITD_PSW_LENGTH(len); 1415 xfer->frlengths[i] = len; 1416 actlen += len; 1417 } 1418 } 1419 if (sitd->flags & OHCI_CALL_DONE) 1420 break; 1421 ohci_free_sitd(sc, sitd); 1422 } 1423 ohci_free_sitd(sc, sitd); 1424 if (uedir == UE_DIR_IN && 1425 xfer->status == USBD_NORMAL_COMPLETION) 1426 xfer->actlen = actlen; 1427 xfer->hcpriv = NULL; 1428 1429 usb_transfer_complete(xfer); 1430 } 1431 } 1432 1433 if (sc->sc_softwake) { 1434 sc->sc_softwake = 0; 1435 cv_broadcast(&sc->sc_softwake_cv); 1436 } 1437 1438 DPRINTFN(10,("ohci_softintr: done:\n")); 1439 } 1440 1441 void 1442 ohci_device_ctrl_done(usbd_xfer_handle xfer) 1443 { 1444 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1445 #ifdef DIAGNOSTIC 1446 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1447 #endif 1448 int len = UGETW(xfer->request.wLength); 1449 int isread = (xfer->request.bmRequestType & UT_READ); 1450 1451 DPRINTFN(10,("ohci_device_ctrl_done: xfer=%p\n", xfer)); 1452 1453 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1454 1455 #ifdef DIAGNOSTIC 1456 if (!(xfer->rqflags & URQ_REQUEST)) { 1457 panic("ohci_device_ctrl_done: not a request"); 1458 } 1459 #endif 1460 if (len) 1461 usb_syncmem(&xfer->dmabuf, 0, len, 1462 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1463 usb_syncmem(&opipe->u.ctl.reqdma, 0, 1464 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1465 } 1466 1467 void 1468 ohci_device_intr_done(usbd_xfer_handle xfer) 1469 { 1470 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1471 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 1472 ohci_soft_ed_t *sed = opipe->sed; 1473 ohci_soft_td_t *data, *tail; 1474 int isread = 1475 (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN); 1476 1477 DPRINTFN(10,("ohci_device_intr_done: xfer=%p, actlen=%d\n", 1478 xfer, xfer->actlen)); 1479 1480 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1481 1482 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 1483 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1484 if (xfer->pipe->repeat) { 1485 data = opipe->tail.td; 1486 tail = ohci_alloc_std(sc); /* XXX should reuse TD */ 1487 if (tail == NULL) { 1488 xfer->status = USBD_NOMEM; 1489 return; 1490 } 1491 tail->xfer = NULL; 1492 1493 data->td.td_flags = HTOO32( 1494 OHCI_TD_IN | OHCI_TD_NOCC | 1495 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 1496 if (xfer->flags & USBD_SHORT_XFER_OK) 1497 data->td.td_flags |= HTOO32(OHCI_TD_R); 1498 data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0)); 1499 data->nexttd = tail; 1500 data->td.td_nexttd = HTOO32(tail->physaddr); 1501 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + 1502 xfer->length - 1); 1503 data->len = xfer->length; 1504 data->xfer = xfer; 1505 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 1506 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 1507 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1508 xfer->hcpriv = data; 1509 xfer->actlen = 0; 1510 1511 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1512 usb_syncmem(&sed->dma, 1513 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1514 sizeof(sed->ed.ed_tailp), 1515 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1516 opipe->tail.td = tail; 1517 } 1518 } 1519 1520 void 1521 ohci_device_bulk_done(usbd_xfer_handle xfer) 1522 { 1523 #ifdef DIAGNOSTIC 1524 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1525 #endif 1526 int isread = 1527 (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN); 1528 1529 KASSERT(mutex_owned(&sc->sc_lock)); 1530 1531 DPRINTFN(10,("ohci_device_bulk_done: xfer=%p, actlen=%d\n", 1532 xfer, xfer->actlen)); 1533 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 1534 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1535 } 1536 1537 Static void 1538 ohci_rhsc_softint(void *arg) 1539 { 1540 ohci_softc_t *sc = arg; 1541 1542 mutex_enter(&sc->sc_lock); 1543 1544 ohci_rhsc(sc, sc->sc_intrxfer); 1545 1546 /* Do not allow RHSC interrupts > 1 per second */ 1547 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1548 1549 mutex_exit(&sc->sc_lock); 1550 } 1551 1552 void 1553 ohci_rhsc(ohci_softc_t *sc, usbd_xfer_handle xfer) 1554 { 1555 u_char *p; 1556 int i, m; 1557 int hstatus __unused; 1558 1559 KASSERT(mutex_owned(&sc->sc_lock)); 1560 1561 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1562 DPRINTF(("ohci_rhsc: sc=%p xfer=%p hstatus=0x%08x\n", 1563 sc, xfer, hstatus)); 1564 1565 if (xfer == NULL) { 1566 /* Just ignore the change. */ 1567 return; 1568 } 1569 1570 p = xfer->buf; 1571 m = min(sc->sc_noport, xfer->length * 8 - 1); 1572 memset(p, 0, xfer->length); 1573 for (i = 1; i <= m; i++) { 1574 /* Pick out CHANGE bits from the status reg. */ 1575 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1576 p[i/8] |= 1 << (i%8); 1577 } 1578 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p)); 1579 xfer->actlen = xfer->length; 1580 xfer->status = USBD_NORMAL_COMPLETION; 1581 1582 usb_transfer_complete(xfer); 1583 } 1584 1585 void 1586 ohci_root_intr_done(usbd_xfer_handle xfer) 1587 { 1588 } 1589 1590 void 1591 ohci_root_ctrl_done(usbd_xfer_handle xfer) 1592 { 1593 } 1594 1595 /* 1596 * Wait here until controller claims to have an interrupt. 1597 * Then call ohci_intr and return. Use timeout to avoid waiting 1598 * too long. 1599 */ 1600 void 1601 ohci_waitintr(ohci_softc_t *sc, usbd_xfer_handle xfer) 1602 { 1603 int timo; 1604 uint32_t intrs; 1605 1606 mutex_enter(&sc->sc_lock); 1607 1608 xfer->status = USBD_IN_PROGRESS; 1609 for (timo = xfer->timeout; timo >= 0; timo--) { 1610 usb_delay_ms(&sc->sc_bus, 1); 1611 if (sc->sc_dying) 1612 break; 1613 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 1614 DPRINTFN(15,("ohci_waitintr: 0x%04x\n", intrs)); 1615 #ifdef OHCI_DEBUG 1616 if (ohcidebug > 15) 1617 ohci_dumpregs(sc); 1618 #endif 1619 if (intrs) { 1620 mutex_spin_enter(&sc->sc_intr_lock); 1621 ohci_intr1(sc); 1622 mutex_spin_exit(&sc->sc_intr_lock); 1623 if (xfer->status != USBD_IN_PROGRESS) 1624 goto done; 1625 } 1626 } 1627 1628 /* Timeout */ 1629 DPRINTF(("ohci_waitintr: timeout\n")); 1630 xfer->status = USBD_TIMEOUT; 1631 usb_transfer_complete(xfer); 1632 1633 /* XXX should free TD */ 1634 1635 done: 1636 mutex_exit(&sc->sc_lock); 1637 } 1638 1639 void 1640 ohci_poll(struct usbd_bus *bus) 1641 { 1642 ohci_softc_t *sc = bus->hci_private; 1643 #ifdef OHCI_DEBUG 1644 static int last; 1645 int new; 1646 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1647 if (new != last) { 1648 DPRINTFN(10,("ohci_poll: intrs=0x%04x\n", new)); 1649 last = new; 1650 } 1651 #endif 1652 sc->sc_eintrs |= OHCI_WDH; 1653 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1654 mutex_spin_enter(&sc->sc_intr_lock); 1655 ohci_intr1(sc); 1656 mutex_spin_exit(&sc->sc_intr_lock); 1657 } 1658 } 1659 1660 usbd_status 1661 ohci_device_request(usbd_xfer_handle xfer) 1662 { 1663 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1664 usb_device_request_t *req = &xfer->request; 1665 usbd_device_handle dev = opipe->pipe.device; 1666 ohci_softc_t *sc = dev->bus->hci_private; 1667 ohci_soft_td_t *setup, *stat, *next, *tail; 1668 ohci_soft_ed_t *sed; 1669 int isread; 1670 int len; 1671 usbd_status err; 1672 1673 KASSERT(mutex_owned(&sc->sc_lock)); 1674 1675 isread = req->bmRequestType & UT_READ; 1676 len = UGETW(req->wLength); 1677 1678 DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, " 1679 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 1680 req->bmRequestType, req->bRequest, UGETW(req->wValue), 1681 UGETW(req->wIndex), len, dev->address, 1682 opipe->pipe.endpoint->edesc->bEndpointAddress)); 1683 1684 setup = opipe->tail.td; 1685 stat = ohci_alloc_std(sc); 1686 if (stat == NULL) { 1687 err = USBD_NOMEM; 1688 goto bad1; 1689 } 1690 tail = ohci_alloc_std(sc); 1691 if (tail == NULL) { 1692 err = USBD_NOMEM; 1693 goto bad2; 1694 } 1695 tail->xfer = NULL; 1696 1697 sed = opipe->sed; 1698 opipe->u.ctl.length = len; 1699 1700 KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->address, 1701 "address ED %d pipe %d\n", 1702 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->address); 1703 KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) == 1704 UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize), 1705 "MPL ED %d pipe %d\n", 1706 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), 1707 UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize)); 1708 1709 next = stat; 1710 1711 /* Set up data transaction */ 1712 if (len != 0) { 1713 ohci_soft_td_t *std = stat; 1714 1715 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 1716 std, &stat); 1717 if (err) { 1718 /* stat is unchanged if error */ 1719 goto bad3; 1720 } 1721 stat = stat->nexttd; /* point at free TD */ 1722 1723 /* Start toggle at 1 and then use the carried toggle. */ 1724 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 1725 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 1726 usb_syncmem(&std->dma, 1727 std->offs + offsetof(ohci_td_t, td_flags), 1728 sizeof(std->td.td_flags), 1729 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1730 } 1731 1732 memcpy(KERNADDR(&opipe->u.ctl.reqdma, 0), req, sizeof *req); 1733 usb_syncmem(&opipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 1734 1735 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1736 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1737 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->u.ctl.reqdma, 0)); 1738 setup->nexttd = next; 1739 setup->td.td_nexttd = HTOO32(next->physaddr); 1740 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof *req - 1); 1741 setup->len = 0; 1742 setup->xfer = xfer; 1743 setup->flags = 0; 1744 xfer->hcpriv = setup; 1745 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 1746 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1747 1748 stat->td.td_flags = HTOO32( 1749 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 1750 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1751 stat->td.td_cbp = 0; 1752 stat->nexttd = tail; 1753 stat->td.td_nexttd = HTOO32(tail->physaddr); 1754 stat->td.td_be = 0; 1755 stat->flags = OHCI_CALL_DONE; 1756 stat->len = 0; 1757 stat->xfer = xfer; 1758 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 1759 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1760 1761 #ifdef OHCI_DEBUG 1762 if (ohcidebug > 5) { 1763 DPRINTF(("ohci_device_request:\n")); 1764 ohci_dump_ed(sc, sed); 1765 ohci_dump_tds(sc, setup); 1766 } 1767 #endif 1768 1769 /* Insert ED in schedule */ 1770 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1771 usb_syncmem(&sed->dma, 1772 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1773 sizeof(sed->ed.ed_tailp), 1774 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1775 opipe->tail.td = tail; 1776 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1777 if (xfer->timeout && !sc->sc_bus.use_polling) { 1778 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 1779 ohci_timeout, xfer); 1780 } 1781 1782 #ifdef OHCI_DEBUG 1783 if (ohcidebug > 20) { 1784 delay(10000); 1785 DPRINTF(("ohci_device_request: status=%x\n", 1786 OREAD4(sc, OHCI_COMMAND_STATUS))); 1787 ohci_dumpregs(sc); 1788 printf("ctrl head:\n"); 1789 ohci_dump_ed(sc, sc->sc_ctrl_head); 1790 printf("sed:\n"); 1791 ohci_dump_ed(sc, sed); 1792 ohci_dump_tds(sc, setup); 1793 } 1794 #endif 1795 1796 return (USBD_NORMAL_COMPLETION); 1797 1798 bad3: 1799 ohci_free_std(sc, tail); 1800 bad2: 1801 ohci_free_std(sc, stat); 1802 bad1: 1803 return (err); 1804 } 1805 1806 /* 1807 * Add an ED to the schedule. Called with USB lock held. 1808 */ 1809 Static void 1810 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1811 { 1812 DPRINTFN(8,("ohci_add_ed: sed=%p head=%p\n", sed, head)); 1813 1814 KASSERT(mutex_owned(&sc->sc_lock)); 1815 1816 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1817 sizeof(head->ed.ed_nexted), 1818 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1819 sed->next = head->next; 1820 sed->ed.ed_nexted = head->ed.ed_nexted; 1821 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1822 sizeof(sed->ed.ed_nexted), 1823 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1824 head->next = sed; 1825 head->ed.ed_nexted = HTOO32(sed->physaddr); 1826 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1827 sizeof(head->ed.ed_nexted), 1828 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1829 } 1830 1831 /* 1832 * Remove an ED from the schedule. Called with USB lock held. 1833 */ 1834 Static void 1835 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1836 { 1837 ohci_soft_ed_t *p; 1838 1839 KASSERT(mutex_owned(&sc->sc_lock)); 1840 1841 /* XXX */ 1842 for (p = head; p != NULL && p->next != sed; p = p->next) 1843 ; 1844 if (p == NULL) 1845 panic("ohci_rem_ed: ED not found"); 1846 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1847 sizeof(sed->ed.ed_nexted), 1848 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1849 p->next = sed->next; 1850 p->ed.ed_nexted = sed->ed.ed_nexted; 1851 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1852 sizeof(p->ed.ed_nexted), 1853 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1854 } 1855 1856 /* 1857 * When a transfer is completed the TD is added to the done queue by 1858 * the host controller. This queue is the processed by software. 1859 * Unfortunately the queue contains the physical address of the TD 1860 * and we have no simple way to translate this back to a kernel address. 1861 * To make the translation possible (and fast) we use a hash table of 1862 * TDs currently in the schedule. The physical address is used as the 1863 * hash value. 1864 */ 1865 1866 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1867 /* Called with USB lock held. */ 1868 void 1869 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1870 { 1871 int h = HASH(std->physaddr); 1872 1873 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1874 1875 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1876 } 1877 1878 /* Called with USB lock held. */ 1879 void 1880 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1881 { 1882 1883 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1884 1885 LIST_REMOVE(std, hnext); 1886 } 1887 1888 ohci_soft_td_t * 1889 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1890 { 1891 int h = HASH(a); 1892 ohci_soft_td_t *std; 1893 1894 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1895 std != NULL; 1896 std = LIST_NEXT(std, hnext)) 1897 if (std->physaddr == a) 1898 return (std); 1899 return (NULL); 1900 } 1901 1902 /* Called with USB lock held. */ 1903 void 1904 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1905 { 1906 int h = HASH(sitd->physaddr); 1907 1908 KASSERT(mutex_owned(&sc->sc_lock)); 1909 1910 DPRINTFN(10,("ohci_hash_add_itd: sitd=%p physaddr=0x%08lx\n", 1911 sitd, (u_long)sitd->physaddr)); 1912 1913 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1914 } 1915 1916 /* Called with USB lock held. */ 1917 void 1918 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1919 { 1920 1921 KASSERT(mutex_owned(&sc->sc_lock)); 1922 1923 DPRINTFN(10,("ohci_hash_rem_itd: sitd=%p physaddr=0x%08lx\n", 1924 sitd, (u_long)sitd->physaddr)); 1925 1926 LIST_REMOVE(sitd, hnext); 1927 } 1928 1929 ohci_soft_itd_t * 1930 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1931 { 1932 int h = HASH(a); 1933 ohci_soft_itd_t *sitd; 1934 1935 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1936 sitd != NULL; 1937 sitd = LIST_NEXT(sitd, hnext)) 1938 if (sitd->physaddr == a) 1939 return (sitd); 1940 return (NULL); 1941 } 1942 1943 void 1944 ohci_timeout(void *addr) 1945 { 1946 struct ohci_xfer *oxfer = addr; 1947 struct ohci_pipe *opipe = (struct ohci_pipe *)oxfer->xfer.pipe; 1948 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 1949 1950 DPRINTF(("ohci_timeout: oxfer=%p\n", oxfer)); 1951 1952 if (sc->sc_dying) { 1953 mutex_enter(&sc->sc_lock); 1954 ohci_abort_xfer(&oxfer->xfer, USBD_TIMEOUT); 1955 mutex_exit(&sc->sc_lock); 1956 return; 1957 } 1958 1959 /* Execute the abort in a process context. */ 1960 usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr, 1961 USB_TASKQ_MPSAFE); 1962 usb_add_task(oxfer->xfer.pipe->device, &oxfer->abort_task, 1963 USB_TASKQ_HC); 1964 } 1965 1966 void 1967 ohci_timeout_task(void *addr) 1968 { 1969 usbd_xfer_handle xfer = addr; 1970 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1971 1972 DPRINTF(("ohci_timeout_task: xfer=%p\n", xfer)); 1973 1974 mutex_enter(&sc->sc_lock); 1975 ohci_abort_xfer(xfer, USBD_TIMEOUT); 1976 mutex_exit(&sc->sc_lock); 1977 } 1978 1979 #ifdef OHCI_DEBUG 1980 void 1981 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 1982 { 1983 for (; std; std = std->nexttd) 1984 ohci_dump_td(sc, std); 1985 } 1986 1987 void 1988 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1989 { 1990 char sbuf[128]; 1991 1992 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1993 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1994 snprintb(sbuf, sizeof(sbuf), 1995 "\177\20" 1996 "b\22R\0" 1997 "f\23\02DP\0" 1998 "=\x0" "setup\0" 1999 "=\x1" "out\0" 2000 "=\x2" "in\0" 2001 "=\x3" "reserved\0" 2002 "f\25\03DI\0" 2003 "=\x07" "none\0" 2004 "f\30\02T\0" 2005 "=\x0" "carry\0" 2006 "=\x1" "carry\0" 2007 "=\x2" "0\0" 2008 "=\x3" "1\0" 2009 "f\32\02EC\0" 2010 "f\34\04CC\0", 2011 (uint32_t)O32TOH(std->td.td_flags)); 2012 printf("TD(%p) at %08lx:\n\tflags=%s\n\tcbp=0x%08lx nexttd=0x%08lx be=0x%08lx\n", 2013 std, (u_long)std->physaddr, sbuf, 2014 (u_long)O32TOH(std->td.td_cbp), 2015 (u_long)O32TOH(std->td.td_nexttd), 2016 (u_long)O32TOH(std->td.td_be)); 2017 } 2018 2019 void 2020 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2021 { 2022 int i; 2023 2024 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 2025 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2026 printf("ITD(%p) at %08lx: sf=%d di=%d fc=%d cc=%d\n" 2027 "bp0=0x%08lx next=0x%08lx be=0x%08lx\n", 2028 sitd, (u_long)sitd->physaddr, 2029 OHCI_ITD_GET_SF(O32TOH(sitd->itd.itd_flags)), 2030 OHCI_ITD_GET_DI(O32TOH(sitd->itd.itd_flags)), 2031 OHCI_ITD_GET_FC(O32TOH(sitd->itd.itd_flags)), 2032 OHCI_ITD_GET_CC(O32TOH(sitd->itd.itd_flags)), 2033 (u_long)O32TOH(sitd->itd.itd_bp0), 2034 (u_long)O32TOH(sitd->itd.itd_nextitd), 2035 (u_long)O32TOH(sitd->itd.itd_be)); 2036 for (i = 0; i < OHCI_ITD_NOFFSET; i++) 2037 printf("offs[%d]=0x%04x ", i, 2038 (u_int)O16TOH(sitd->itd.itd_offset[i])); 2039 printf("\n"); 2040 } 2041 2042 void 2043 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2044 { 2045 for (; sitd; sitd = sitd->nextitd) 2046 ohci_dump_itd(sc, sitd); 2047 } 2048 2049 void 2050 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2051 { 2052 char sbuf[128], sbuf2[128]; 2053 2054 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2055 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2056 snprintb(sbuf, sizeof(sbuf), 2057 "\20\14OUT\15IN\16LOWSPEED\17SKIP\20ISO", 2058 (uint32_t)O32TOH(sed->ed.ed_flags)); 2059 snprintb(sbuf2, sizeof(sbuf2), "\20\1HALT\2CARRY", 2060 (uint32_t)O32TOH(sed->ed.ed_headp)); 2061 2062 printf("ED(%p) at 0x%08lx: addr=%d endpt=%d maxp=%d flags=%s\ntailp=0x%08lx " 2063 "headflags=%s headp=0x%08lx nexted=0x%08lx\n", 2064 sed, (u_long)sed->physaddr, 2065 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), 2066 OHCI_ED_GET_EN(O32TOH(sed->ed.ed_flags)), 2067 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), sbuf, 2068 (u_long)O32TOH(sed->ed.ed_tailp), sbuf2, 2069 (u_long)O32TOH(sed->ed.ed_headp), 2070 (u_long)O32TOH(sed->ed.ed_nexted)); 2071 } 2072 #endif 2073 2074 usbd_status 2075 ohci_open(usbd_pipe_handle pipe) 2076 { 2077 usbd_device_handle dev = pipe->device; 2078 ohci_softc_t *sc = dev->bus->hci_private; 2079 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 2080 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2081 uint8_t addr = dev->address; 2082 uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2083 ohci_soft_ed_t *sed; 2084 ohci_soft_td_t *std; 2085 ohci_soft_itd_t *sitd; 2086 ohci_physaddr_t tdphys; 2087 uint32_t fmt; 2088 usbd_status err = USBD_NOMEM; 2089 int ival; 2090 2091 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 2092 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 2093 2094 if (sc->sc_dying) { 2095 return USBD_IOERROR; 2096 } 2097 2098 std = NULL; 2099 sed = NULL; 2100 2101 if (addr == sc->sc_addr) { 2102 switch (ed->bEndpointAddress) { 2103 case USB_CONTROL_ENDPOINT: 2104 pipe->methods = &ohci_root_ctrl_methods; 2105 break; 2106 case UE_DIR_IN | OHCI_INTR_ENDPT: 2107 pipe->methods = &ohci_root_intr_methods; 2108 break; 2109 default: 2110 err = USBD_INVAL; 2111 goto bad; 2112 } 2113 } else { 2114 sed = ohci_alloc_sed(sc); 2115 if (sed == NULL) 2116 goto bad; 2117 opipe->sed = sed; 2118 if (xfertype == UE_ISOCHRONOUS) { 2119 mutex_enter(&sc->sc_lock); 2120 sitd = ohci_alloc_sitd(sc); 2121 mutex_exit(&sc->sc_lock); 2122 if (sitd == NULL) 2123 goto bad; 2124 2125 opipe->tail.itd = sitd; 2126 tdphys = sitd->physaddr; 2127 fmt = OHCI_ED_FORMAT_ISO; 2128 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2129 fmt |= OHCI_ED_DIR_IN; 2130 else 2131 fmt |= OHCI_ED_DIR_OUT; 2132 } else { 2133 mutex_enter(&sc->sc_lock); 2134 std = ohci_alloc_std(sc); 2135 mutex_exit(&sc->sc_lock); 2136 if (std == NULL) 2137 goto bad; 2138 2139 opipe->tail.td = std; 2140 tdphys = std->physaddr; 2141 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2142 } 2143 sed->ed.ed_flags = HTOO32( 2144 OHCI_ED_SET_FA(addr) | 2145 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2146 (dev->speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2147 fmt | 2148 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2149 sed->ed.ed_headp = HTOO32(tdphys | 2150 (pipe->endpoint->datatoggle ? OHCI_TOGGLECARRY : 0)); 2151 sed->ed.ed_tailp = HTOO32(tdphys); 2152 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2153 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2154 2155 switch (xfertype) { 2156 case UE_CONTROL: 2157 pipe->methods = &ohci_device_ctrl_methods; 2158 err = usb_allocmem(&sc->sc_bus, 2159 sizeof(usb_device_request_t), 2160 0, &opipe->u.ctl.reqdma); 2161 if (err) 2162 goto bad; 2163 mutex_enter(&sc->sc_lock); 2164 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2165 mutex_exit(&sc->sc_lock); 2166 break; 2167 case UE_INTERRUPT: 2168 pipe->methods = &ohci_device_intr_methods; 2169 ival = pipe->interval; 2170 if (ival == USBD_DEFAULT_INTERVAL) 2171 ival = ed->bInterval; 2172 err = ohci_device_setintr(sc, opipe, ival); 2173 if (err) 2174 goto bad; 2175 break; 2176 case UE_ISOCHRONOUS: 2177 pipe->methods = &ohci_device_isoc_methods; 2178 return (ohci_setup_isoc(pipe)); 2179 case UE_BULK: 2180 pipe->methods = &ohci_device_bulk_methods; 2181 mutex_enter(&sc->sc_lock); 2182 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2183 mutex_exit(&sc->sc_lock); 2184 break; 2185 } 2186 } 2187 2188 return USBD_NORMAL_COMPLETION; 2189 2190 bad: 2191 if (std != NULL) { 2192 mutex_enter(&sc->sc_lock); 2193 ohci_free_std(sc, std); 2194 mutex_exit(&sc->sc_lock); 2195 } 2196 if (sed != NULL) 2197 ohci_free_sed(sc, sed); 2198 return err; 2199 2200 } 2201 2202 /* 2203 * Close a reqular pipe. 2204 * Assumes that there are no pending transactions. 2205 */ 2206 void 2207 ohci_close_pipe(usbd_pipe_handle pipe, ohci_soft_ed_t *head) 2208 { 2209 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2210 ohci_softc_t *sc = pipe->device->bus->hci_private; 2211 ohci_soft_ed_t *sed = opipe->sed; 2212 2213 KASSERT(mutex_owned(&sc->sc_lock)); 2214 2215 #ifdef DIAGNOSTIC 2216 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2217 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2218 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2219 ohci_soft_td_t *std; 2220 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2221 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2222 "tl=0x%x pipe=%p, std=%p\n", sed, 2223 (int)O32TOH(sed->ed.ed_headp), 2224 (int)O32TOH(sed->ed.ed_tailp), 2225 pipe, std); 2226 #ifdef OHCI_DEBUG 2227 usbd_dump_pipe(&opipe->pipe); 2228 ohci_dump_ed(sc, sed); 2229 if (std) 2230 ohci_dump_td(sc, std); 2231 #endif 2232 usb_delay_ms(&sc->sc_bus, 2); 2233 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2234 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2235 printf("ohci_close_pipe: pipe still not empty\n"); 2236 } 2237 #endif 2238 ohci_rem_ed(sc, sed, head); 2239 /* Make sure the host controller is not touching this ED */ 2240 usb_delay_ms(&sc->sc_bus, 1); 2241 pipe->endpoint->datatoggle = 2242 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2243 ohci_free_sed(sc, opipe->sed); 2244 } 2245 2246 /* 2247 * Abort a device request. 2248 * If this routine is called at splusb() it guarantees that the request 2249 * will be removed from the hardware scheduling and that the callback 2250 * for it will be called with USBD_CANCELLED status. 2251 * It's impossible to guarantee that the requested transfer will not 2252 * have happened since the hardware runs concurrently. 2253 * If the transaction has already happened we rely on the ordinary 2254 * interrupt processing to process it. 2255 * XXX This is most probably wrong. 2256 * XXXMRG this doesn't make sense anymore. 2257 */ 2258 void 2259 ohci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2260 { 2261 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2262 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 2263 ohci_soft_ed_t *sed = opipe->sed; 2264 ohci_soft_td_t *p, *n; 2265 ohci_physaddr_t headp; 2266 int hit; 2267 int wake; 2268 2269 DPRINTF(("ohci_abort_xfer: xfer=%p pipe=%p sed=%p\n", xfer, opipe,sed)); 2270 2271 KASSERT(mutex_owned(&sc->sc_lock)); 2272 ASSERT_SLEEPABLE(); 2273 2274 if (sc->sc_dying) { 2275 /* If we're dying, just do the software part. */ 2276 xfer->status = status; /* make software ignore it */ 2277 callout_halt(&xfer->timeout_handle, &sc->sc_lock); 2278 usb_transfer_complete(xfer); 2279 return; 2280 } 2281 2282 /* 2283 * If an abort is already in progress then just wait for it to 2284 * complete and return. 2285 */ 2286 if (xfer->hcflags & UXFER_ABORTING) { 2287 DPRINTFN(2, ("ohci_abort_xfer: already aborting\n")); 2288 #ifdef DIAGNOSTIC 2289 if (status == USBD_TIMEOUT) 2290 printf("%s: TIMEOUT while aborting\n", __func__); 2291 #endif 2292 /* Override the status which might be USBD_TIMEOUT. */ 2293 xfer->status = status; 2294 DPRINTFN(2, ("ohci_abort_xfer: waiting for abort to finish\n")); 2295 xfer->hcflags |= UXFER_ABORTWAIT; 2296 while (xfer->hcflags & UXFER_ABORTING) 2297 cv_wait(&xfer->hccv, &sc->sc_lock); 2298 goto done; 2299 } 2300 xfer->hcflags |= UXFER_ABORTING; 2301 2302 /* 2303 * Step 1: Make interrupt routine and hardware ignore xfer. 2304 */ 2305 xfer->status = status; /* make software ignore it */ 2306 callout_stop(&xfer->timeout_handle); 2307 DPRINTFN(1,("ohci_abort_xfer: stop ed=%p\n", sed)); 2308 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2309 sizeof(sed->ed.ed_flags), 2310 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2311 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2312 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2313 sizeof(sed->ed.ed_flags), 2314 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2315 2316 /* 2317 * Step 2: Wait until we know hardware has finished any possible 2318 * use of the xfer. Also make sure the soft interrupt routine 2319 * has run. 2320 */ 2321 /* Hardware finishes in 1ms */ 2322 usb_delay_ms_locked(opipe->pipe.device->bus, 20, &sc->sc_lock); 2323 sc->sc_softwake = 1; 2324 usb_schedsoftintr(&sc->sc_bus); 2325 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2326 2327 /* 2328 * Step 3: Remove any vestiges of the xfer from the hardware. 2329 * The complication here is that the hardware may have executed 2330 * beyond the xfer we're trying to abort. So as we're scanning 2331 * the TDs of this xfer we check if the hardware points to 2332 * any of them. 2333 */ 2334 p = xfer->hcpriv; 2335 #ifdef DIAGNOSTIC 2336 if (p == NULL) { 2337 xfer->hcflags &= ~UXFER_ABORTING; /* XXX */ 2338 printf("ohci_abort_xfer: hcpriv is NULL\n"); 2339 goto done; 2340 } 2341 #endif 2342 #ifdef OHCI_DEBUG 2343 if (ohcidebug > 1) { 2344 DPRINTF(("ohci_abort_xfer: sed=\n")); 2345 ohci_dump_ed(sc, sed); 2346 ohci_dump_tds(sc, p); 2347 } 2348 #endif 2349 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2350 hit = 0; 2351 for (; p->xfer == xfer; p = n) { 2352 hit |= headp == p->physaddr; 2353 n = p->nexttd; 2354 ohci_free_std(sc, p); 2355 } 2356 /* Zap headp register if hardware pointed inside the xfer. */ 2357 if (hit) { 2358 DPRINTFN(1,("ohci_abort_xfer: set hd=0x%08x, tl=0x%08x\n", 2359 (int)p->physaddr, (int)O32TOH(sed->ed.ed_tailp))); 2360 sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */ 2361 usb_syncmem(&sed->dma, 2362 sed->offs + offsetof(ohci_ed_t, ed_headp), 2363 sizeof(sed->ed.ed_headp), 2364 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2365 } else { 2366 DPRINTFN(1,("ohci_abort_xfer: no hit\n")); 2367 } 2368 2369 /* 2370 * Step 4: Turn on hardware again. 2371 */ 2372 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2373 sizeof(sed->ed.ed_flags), 2374 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2375 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2376 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2377 sizeof(sed->ed.ed_flags), 2378 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2379 2380 /* 2381 * Step 5: Execute callback. 2382 */ 2383 wake = xfer->hcflags & UXFER_ABORTWAIT; 2384 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2385 usb_transfer_complete(xfer); 2386 if (wake) 2387 cv_broadcast(&xfer->hccv); 2388 2389 done: 2390 KASSERT(mutex_owned(&sc->sc_lock)); 2391 } 2392 2393 /* 2394 * Data structures and routines to emulate the root hub. 2395 */ 2396 Static usb_device_descriptor_t ohci_devd = { 2397 USB_DEVICE_DESCRIPTOR_SIZE, 2398 UDESC_DEVICE, /* type */ 2399 {0x00, 0x01}, /* USB version */ 2400 UDCLASS_HUB, /* class */ 2401 UDSUBCLASS_HUB, /* subclass */ 2402 UDPROTO_FSHUB, /* protocol */ 2403 64, /* max packet */ 2404 {0},{0},{0x00,0x01}, /* device id */ 2405 1,2,0, /* string indicies */ 2406 1 /* # of configurations */ 2407 }; 2408 2409 Static const usb_config_descriptor_t ohci_confd = { 2410 USB_CONFIG_DESCRIPTOR_SIZE, 2411 UDESC_CONFIG, 2412 {USB_CONFIG_DESCRIPTOR_SIZE + 2413 USB_INTERFACE_DESCRIPTOR_SIZE + 2414 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2415 1, 2416 1, 2417 0, 2418 UC_ATTR_MBO | UC_SELF_POWERED, 2419 0 /* max power */ 2420 }; 2421 2422 Static const usb_interface_descriptor_t ohci_ifcd = { 2423 USB_INTERFACE_DESCRIPTOR_SIZE, 2424 UDESC_INTERFACE, 2425 0, 2426 0, 2427 1, 2428 UICLASS_HUB, 2429 UISUBCLASS_HUB, 2430 UIPROTO_FSHUB, 2431 0 2432 }; 2433 2434 Static const usb_endpoint_descriptor_t ohci_endpd = { 2435 .bLength = USB_ENDPOINT_DESCRIPTOR_SIZE, 2436 .bDescriptorType = UDESC_ENDPOINT, 2437 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT, 2438 .bmAttributes = UE_INTERRUPT, 2439 .wMaxPacketSize = {8, 0}, /* max packet */ 2440 .bInterval = 255, 2441 }; 2442 2443 Static const usb_hub_descriptor_t ohci_hubd = { 2444 .bDescLength = USB_HUB_DESCRIPTOR_SIZE, 2445 .bDescriptorType = UDESC_HUB, 2446 }; 2447 2448 /* 2449 * Simulate a hardware hub by handling all the necessary requests. 2450 */ 2451 Static usbd_status 2452 ohci_root_ctrl_transfer(usbd_xfer_handle xfer) 2453 { 2454 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2455 usbd_status err; 2456 2457 /* Insert last in queue. */ 2458 mutex_enter(&sc->sc_lock); 2459 err = usb_insert_transfer(xfer); 2460 mutex_exit(&sc->sc_lock); 2461 if (err) 2462 return (err); 2463 2464 /* Pipe isn't running, start first */ 2465 return (ohci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2466 } 2467 2468 Static usbd_status 2469 ohci_root_ctrl_start(usbd_xfer_handle xfer) 2470 { 2471 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2472 usb_device_request_t *req; 2473 void *buf = NULL; 2474 int port, i; 2475 int len, value, index, l, totlen = 0; 2476 usb_port_status_t ps; 2477 usb_hub_descriptor_t hubd; 2478 usbd_status err; 2479 uint32_t v; 2480 2481 if (sc->sc_dying) 2482 return (USBD_IOERROR); 2483 2484 #ifdef DIAGNOSTIC 2485 if (!(xfer->rqflags & URQ_REQUEST)) 2486 /* XXX panic */ 2487 return (USBD_INVAL); 2488 #endif 2489 req = &xfer->request; 2490 2491 DPRINTFN(4,("ohci_root_ctrl_control type=0x%02x request=%02x\n", 2492 req->bmRequestType, req->bRequest)); 2493 2494 len = UGETW(req->wLength); 2495 value = UGETW(req->wValue); 2496 index = UGETW(req->wIndex); 2497 2498 if (len != 0) 2499 buf = xfer->buf; 2500 2501 #define C(x,y) ((x) | ((y) << 8)) 2502 switch(C(req->bRequest, req->bmRequestType)) { 2503 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2504 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2505 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2506 /* 2507 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2508 * for the integrated root hub. 2509 */ 2510 break; 2511 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2512 if (len > 0) { 2513 *(uint8_t *)buf = sc->sc_conf; 2514 totlen = 1; 2515 } 2516 break; 2517 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2518 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value)); 2519 if (len == 0) 2520 break; 2521 switch(value >> 8) { 2522 case UDESC_DEVICE: 2523 if ((value & 0xff) != 0) { 2524 err = USBD_IOERROR; 2525 goto ret; 2526 } 2527 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2528 USETW(ohci_devd.idVendor, sc->sc_id_vendor); 2529 memcpy(buf, &ohci_devd, l); 2530 break; 2531 case UDESC_CONFIG: 2532 if ((value & 0xff) != 0) { 2533 err = USBD_IOERROR; 2534 goto ret; 2535 } 2536 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2537 memcpy(buf, &ohci_confd, l); 2538 buf = (char *)buf + l; 2539 len -= l; 2540 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2541 totlen += l; 2542 memcpy(buf, &ohci_ifcd, l); 2543 buf = (char *)buf + l; 2544 len -= l; 2545 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2546 totlen += l; 2547 memcpy(buf, &ohci_endpd, l); 2548 break; 2549 case UDESC_STRING: 2550 #define sd ((usb_string_descriptor_t *)buf) 2551 switch (value & 0xff) { 2552 case 0: /* Language table */ 2553 totlen = usb_makelangtbl(sd, len); 2554 break; 2555 case 1: /* Vendor */ 2556 totlen = usb_makestrdesc(sd, len, 2557 sc->sc_vendor); 2558 break; 2559 case 2: /* Product */ 2560 totlen = usb_makestrdesc(sd, len, 2561 "OHCI root hub"); 2562 break; 2563 } 2564 #undef sd 2565 break; 2566 default: 2567 err = USBD_IOERROR; 2568 goto ret; 2569 } 2570 break; 2571 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2572 if (len > 0) { 2573 *(uint8_t *)buf = 0; 2574 totlen = 1; 2575 } 2576 break; 2577 case C(UR_GET_STATUS, UT_READ_DEVICE): 2578 if (len > 1) { 2579 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2580 totlen = 2; 2581 } 2582 break; 2583 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2584 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2585 if (len > 1) { 2586 USETW(((usb_status_t *)buf)->wStatus, 0); 2587 totlen = 2; 2588 } 2589 break; 2590 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2591 if (value >= USB_MAX_DEVICES) { 2592 err = USBD_IOERROR; 2593 goto ret; 2594 } 2595 sc->sc_addr = value; 2596 break; 2597 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2598 if (value != 0 && value != 1) { 2599 err = USBD_IOERROR; 2600 goto ret; 2601 } 2602 sc->sc_conf = value; 2603 break; 2604 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2605 break; 2606 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2607 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2608 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2609 err = USBD_IOERROR; 2610 goto ret; 2611 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2612 break; 2613 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2614 break; 2615 /* Hub requests */ 2616 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2617 break; 2618 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2619 DPRINTFN(8, ("ohci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 2620 "port=%d feature=%d\n", 2621 index, value)); 2622 if (index < 1 || index > sc->sc_noport) { 2623 err = USBD_IOERROR; 2624 goto ret; 2625 } 2626 port = OHCI_RH_PORT_STATUS(index); 2627 switch(value) { 2628 case UHF_PORT_ENABLE: 2629 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2630 break; 2631 case UHF_PORT_SUSPEND: 2632 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2633 break; 2634 case UHF_PORT_POWER: 2635 /* Yes, writing to the LOW_SPEED bit clears power. */ 2636 OWRITE4(sc, port, UPS_LOW_SPEED); 2637 break; 2638 case UHF_C_PORT_CONNECTION: 2639 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2640 break; 2641 case UHF_C_PORT_ENABLE: 2642 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2643 break; 2644 case UHF_C_PORT_SUSPEND: 2645 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2646 break; 2647 case UHF_C_PORT_OVER_CURRENT: 2648 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2649 break; 2650 case UHF_C_PORT_RESET: 2651 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2652 break; 2653 default: 2654 err = USBD_IOERROR; 2655 goto ret; 2656 } 2657 switch(value) { 2658 case UHF_C_PORT_CONNECTION: 2659 case UHF_C_PORT_ENABLE: 2660 case UHF_C_PORT_SUSPEND: 2661 case UHF_C_PORT_OVER_CURRENT: 2662 case UHF_C_PORT_RESET: 2663 /* Enable RHSC interrupt if condition is cleared. */ 2664 if ((OREAD4(sc, port) >> 16) == 0) 2665 ohci_rhsc_enable(sc); 2666 break; 2667 default: 2668 break; 2669 } 2670 break; 2671 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2672 if (len == 0) 2673 break; 2674 if ((value & 0xff) != 0) { 2675 err = USBD_IOERROR; 2676 goto ret; 2677 } 2678 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2679 hubd = ohci_hubd; 2680 hubd.bNbrPorts = sc->sc_noport; 2681 USETW(hubd.wHubCharacteristics, 2682 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2683 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2684 /* XXX overcurrent */ 2685 ); 2686 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2687 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2688 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2689 hubd.DeviceRemovable[i++] = (uint8_t)v; 2690 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2691 l = min(len, hubd.bDescLength); 2692 totlen = l; 2693 memcpy(buf, &hubd, l); 2694 break; 2695 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2696 if (len != 4) { 2697 err = USBD_IOERROR; 2698 goto ret; 2699 } 2700 memset(buf, 0, len); /* ? XXX */ 2701 totlen = len; 2702 break; 2703 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2704 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n", 2705 index)); 2706 if (index < 1 || index > sc->sc_noport) { 2707 err = USBD_IOERROR; 2708 goto ret; 2709 } 2710 if (len != 4) { 2711 err = USBD_IOERROR; 2712 goto ret; 2713 } 2714 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2715 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n", 2716 v)); 2717 USETW(ps.wPortStatus, v); 2718 USETW(ps.wPortChange, v >> 16); 2719 l = min(len, sizeof ps); 2720 memcpy(buf, &ps, l); 2721 totlen = l; 2722 break; 2723 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2724 err = USBD_IOERROR; 2725 goto ret; 2726 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2727 break; 2728 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2729 if (index < 1 || index > sc->sc_noport) { 2730 err = USBD_IOERROR; 2731 goto ret; 2732 } 2733 port = OHCI_RH_PORT_STATUS(index); 2734 switch(value) { 2735 case UHF_PORT_ENABLE: 2736 OWRITE4(sc, port, UPS_PORT_ENABLED); 2737 break; 2738 case UHF_PORT_SUSPEND: 2739 OWRITE4(sc, port, UPS_SUSPEND); 2740 break; 2741 case UHF_PORT_RESET: 2742 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n", 2743 index)); 2744 OWRITE4(sc, port, UPS_RESET); 2745 for (i = 0; i < 5; i++) { 2746 usb_delay_ms(&sc->sc_bus, 2747 USB_PORT_ROOT_RESET_DELAY); 2748 if (sc->sc_dying) { 2749 err = USBD_IOERROR; 2750 goto ret; 2751 } 2752 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2753 break; 2754 } 2755 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n", 2756 index, OREAD4(sc, port))); 2757 break; 2758 case UHF_PORT_POWER: 2759 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power " 2760 "%d\n", index)); 2761 OWRITE4(sc, port, UPS_PORT_POWER); 2762 break; 2763 default: 2764 err = USBD_IOERROR; 2765 goto ret; 2766 } 2767 break; 2768 default: 2769 err = USBD_IOERROR; 2770 goto ret; 2771 } 2772 xfer->actlen = totlen; 2773 err = USBD_NORMAL_COMPLETION; 2774 ret: 2775 xfer->status = err; 2776 mutex_enter(&sc->sc_lock); 2777 usb_transfer_complete(xfer); 2778 mutex_exit(&sc->sc_lock); 2779 return (USBD_IN_PROGRESS); 2780 } 2781 2782 /* Abort a root control request. */ 2783 Static void 2784 ohci_root_ctrl_abort(usbd_xfer_handle xfer) 2785 { 2786 /* Nothing to do, all transfers are synchronous. */ 2787 } 2788 2789 /* Close the root pipe. */ 2790 Static void 2791 ohci_root_ctrl_close(usbd_pipe_handle pipe) 2792 { 2793 DPRINTF(("ohci_root_ctrl_close\n")); 2794 /* Nothing to do. */ 2795 } 2796 2797 Static usbd_status 2798 ohci_root_intr_transfer(usbd_xfer_handle xfer) 2799 { 2800 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2801 usbd_status err; 2802 2803 /* Insert last in queue. */ 2804 mutex_enter(&sc->sc_lock); 2805 err = usb_insert_transfer(xfer); 2806 mutex_exit(&sc->sc_lock); 2807 if (err) 2808 return (err); 2809 2810 /* Pipe isn't running, start first */ 2811 return (ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2812 } 2813 2814 Static usbd_status 2815 ohci_root_intr_start(usbd_xfer_handle xfer) 2816 { 2817 usbd_pipe_handle pipe = xfer->pipe; 2818 ohci_softc_t *sc = pipe->device->bus->hci_private; 2819 2820 if (sc->sc_dying) 2821 return (USBD_IOERROR); 2822 2823 mutex_enter(&sc->sc_lock); 2824 KASSERT(sc->sc_intrxfer == NULL); 2825 sc->sc_intrxfer = xfer; 2826 mutex_exit(&sc->sc_lock); 2827 2828 return (USBD_IN_PROGRESS); 2829 } 2830 2831 /* Abort a root interrupt request. */ 2832 Static void 2833 ohci_root_intr_abort(usbd_xfer_handle xfer) 2834 { 2835 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2836 2837 KASSERT(mutex_owned(&sc->sc_lock)); 2838 KASSERT(xfer->pipe->intrxfer == xfer); 2839 2840 sc->sc_intrxfer = NULL; 2841 2842 xfer->status = USBD_CANCELLED; 2843 usb_transfer_complete(xfer); 2844 } 2845 2846 /* Close the root pipe. */ 2847 Static void 2848 ohci_root_intr_close(usbd_pipe_handle pipe) 2849 { 2850 ohci_softc_t *sc = pipe->device->bus->hci_private; 2851 2852 KASSERT(mutex_owned(&sc->sc_lock)); 2853 2854 DPRINTF(("ohci_root_intr_close\n")); 2855 2856 sc->sc_intrxfer = NULL; 2857 } 2858 2859 /************************/ 2860 2861 Static usbd_status 2862 ohci_device_ctrl_transfer(usbd_xfer_handle xfer) 2863 { 2864 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2865 usbd_status err; 2866 2867 /* Insert last in queue. */ 2868 mutex_enter(&sc->sc_lock); 2869 err = usb_insert_transfer(xfer); 2870 mutex_exit(&sc->sc_lock); 2871 if (err) 2872 return (err); 2873 2874 /* Pipe isn't running, start first */ 2875 return (ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2876 } 2877 2878 Static usbd_status 2879 ohci_device_ctrl_start(usbd_xfer_handle xfer) 2880 { 2881 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2882 usbd_status err; 2883 2884 if (sc->sc_dying) 2885 return (USBD_IOERROR); 2886 2887 #ifdef DIAGNOSTIC 2888 if (!(xfer->rqflags & URQ_REQUEST)) { 2889 /* XXX panic */ 2890 printf("ohci_device_ctrl_transfer: not a request\n"); 2891 return (USBD_INVAL); 2892 } 2893 #endif 2894 2895 mutex_enter(&sc->sc_lock); 2896 err = ohci_device_request(xfer); 2897 mutex_exit(&sc->sc_lock); 2898 if (err) 2899 return (err); 2900 2901 if (sc->sc_bus.use_polling) 2902 ohci_waitintr(sc, xfer); 2903 return (USBD_IN_PROGRESS); 2904 } 2905 2906 /* Abort a device control request. */ 2907 Static void 2908 ohci_device_ctrl_abort(usbd_xfer_handle xfer) 2909 { 2910 #ifdef DIAGNOSTIC 2911 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2912 #endif 2913 2914 KASSERT(mutex_owned(&sc->sc_lock)); 2915 2916 DPRINTF(("ohci_device_ctrl_abort: xfer=%p\n", xfer)); 2917 ohci_abort_xfer(xfer, USBD_CANCELLED); 2918 } 2919 2920 /* Close a device control pipe. */ 2921 Static void 2922 ohci_device_ctrl_close(usbd_pipe_handle pipe) 2923 { 2924 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2925 ohci_softc_t *sc = pipe->device->bus->hci_private; 2926 2927 KASSERT(mutex_owned(&sc->sc_lock)); 2928 2929 DPRINTF(("ohci_device_ctrl_close: pipe=%p\n", pipe)); 2930 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2931 ohci_free_std(sc, opipe->tail.td); 2932 } 2933 2934 /************************/ 2935 2936 Static void 2937 ohci_device_clear_toggle(usbd_pipe_handle pipe) 2938 { 2939 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2940 ohci_softc_t *sc = pipe->device->bus->hci_private; 2941 2942 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2943 } 2944 2945 Static void 2946 ohci_noop(usbd_pipe_handle pipe) 2947 { 2948 } 2949 2950 Static usbd_status 2951 ohci_device_bulk_transfer(usbd_xfer_handle xfer) 2952 { 2953 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2954 usbd_status err; 2955 2956 /* Insert last in queue. */ 2957 mutex_enter(&sc->sc_lock); 2958 err = usb_insert_transfer(xfer); 2959 mutex_exit(&sc->sc_lock); 2960 if (err) 2961 return (err); 2962 2963 /* Pipe isn't running, start first */ 2964 return (ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2965 } 2966 2967 Static usbd_status 2968 ohci_device_bulk_start(usbd_xfer_handle xfer) 2969 { 2970 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2971 usbd_device_handle dev = opipe->pipe.device; 2972 ohci_softc_t *sc = dev->bus->hci_private; 2973 int addr = dev->address; 2974 ohci_soft_td_t *data, *tail, *tdp; 2975 ohci_soft_ed_t *sed; 2976 int len, isread, endpt; 2977 usbd_status err; 2978 2979 if (sc->sc_dying) 2980 return (USBD_IOERROR); 2981 2982 #ifdef DIAGNOSTIC 2983 if (xfer->rqflags & URQ_REQUEST) { 2984 /* XXX panic */ 2985 printf("ohci_device_bulk_start: a request\n"); 2986 return (USBD_INVAL); 2987 } 2988 #endif 2989 2990 mutex_enter(&sc->sc_lock); 2991 2992 len = xfer->length; 2993 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 2994 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2995 sed = opipe->sed; 2996 2997 DPRINTFN(4,("ohci_device_bulk_start: xfer=%p len=%d isread=%d " 2998 "flags=%d endpt=%d\n", xfer, len, isread, xfer->flags, 2999 endpt)); 3000 3001 opipe->u.bulk.isread = isread; 3002 opipe->u.bulk.length = len; 3003 3004 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3005 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3006 /* Update device address */ 3007 sed->ed.ed_flags = HTOO32( 3008 (O32TOH(sed->ed.ed_flags) & ~OHCI_ED_ADDRMASK) | 3009 OHCI_ED_SET_FA(addr)); 3010 3011 /* Allocate a chain of new TDs (including a new tail). */ 3012 data = opipe->tail.td; 3013 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 3014 data, &tail); 3015 if (err) 3016 return err; 3017 3018 /* We want interrupt at the end of the transfer. */ 3019 tail->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3020 tail->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3021 tail->flags |= OHCI_CALL_DONE; 3022 tail = tail->nexttd; /* point at sentinel */ 3023 usb_syncmem(&tail->dma, tail->offs + offsetof(ohci_td_t, td_flags), 3024 sizeof(tail->td.td_flags), 3025 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3026 if (err) { 3027 mutex_exit(&sc->sc_lock); 3028 return (err); 3029 } 3030 3031 tail->xfer = NULL; 3032 xfer->hcpriv = data; 3033 3034 DPRINTFN(4,("ohci_device_bulk_start: ed_flags=0x%08x td_flags=0x%08x " 3035 "td_cbp=0x%08x td_be=0x%08x\n", 3036 (int)O32TOH(sed->ed.ed_flags), 3037 (int)O32TOH(data->td.td_flags), 3038 (int)O32TOH(data->td.td_cbp), 3039 (int)O32TOH(data->td.td_be))); 3040 3041 #ifdef OHCI_DEBUG 3042 if (ohcidebug > 5) { 3043 ohci_dump_ed(sc, sed); 3044 ohci_dump_tds(sc, data); 3045 } 3046 #endif 3047 3048 /* Insert ED in schedule */ 3049 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3050 tdp->xfer = xfer; 3051 } 3052 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3053 opipe->tail.td = tail; 3054 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3055 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3056 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3057 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3058 if (xfer->timeout && !sc->sc_bus.use_polling) { 3059 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3060 ohci_timeout, xfer); 3061 } 3062 mutex_exit(&sc->sc_lock); 3063 3064 #if 0 3065 /* This goes wrong if we are too slow. */ 3066 if (ohcidebug > 10) { 3067 delay(10000); 3068 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3069 OREAD4(sc, OHCI_COMMAND_STATUS))); 3070 ohci_dump_ed(sc, sed); 3071 ohci_dump_tds(sc, data); 3072 } 3073 #endif 3074 3075 return (USBD_IN_PROGRESS); 3076 } 3077 3078 Static void 3079 ohci_device_bulk_abort(usbd_xfer_handle xfer) 3080 { 3081 #ifdef DIAGNOSTIC 3082 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3083 #endif 3084 3085 KASSERT(mutex_owned(&sc->sc_lock)); 3086 3087 DPRINTF(("ohci_device_bulk_abort: xfer=%p\n", xfer)); 3088 ohci_abort_xfer(xfer, USBD_CANCELLED); 3089 } 3090 3091 /* 3092 * Close a device bulk pipe. 3093 */ 3094 Static void 3095 ohci_device_bulk_close(usbd_pipe_handle pipe) 3096 { 3097 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3098 ohci_softc_t *sc = pipe->device->bus->hci_private; 3099 3100 KASSERT(mutex_owned(&sc->sc_lock)); 3101 3102 DPRINTF(("ohci_device_bulk_close: pipe=%p\n", pipe)); 3103 ohci_close_pipe(pipe, sc->sc_bulk_head); 3104 ohci_free_std(sc, opipe->tail.td); 3105 } 3106 3107 /************************/ 3108 3109 Static usbd_status 3110 ohci_device_intr_transfer(usbd_xfer_handle xfer) 3111 { 3112 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3113 usbd_status err; 3114 3115 /* Insert last in queue. */ 3116 mutex_enter(&sc->sc_lock); 3117 err = usb_insert_transfer(xfer); 3118 mutex_exit(&sc->sc_lock); 3119 if (err) 3120 return (err); 3121 3122 /* Pipe isn't running, start first */ 3123 return (ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3124 } 3125 3126 Static usbd_status 3127 ohci_device_intr_start(usbd_xfer_handle xfer) 3128 { 3129 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3130 usbd_device_handle dev = opipe->pipe.device; 3131 ohci_softc_t *sc = dev->bus->hci_private; 3132 ohci_soft_ed_t *sed = opipe->sed; 3133 ohci_soft_td_t *data, *tail; 3134 int len, isread, endpt; 3135 3136 if (sc->sc_dying) 3137 return (USBD_IOERROR); 3138 3139 DPRINTFN(3, ("ohci_device_intr_transfer: xfer=%p len=%d " 3140 "flags=%d priv=%p\n", 3141 xfer, xfer->length, xfer->flags, xfer->priv)); 3142 3143 #ifdef DIAGNOSTIC 3144 if (xfer->rqflags & URQ_REQUEST) 3145 panic("ohci_device_intr_transfer: a request"); 3146 #endif 3147 3148 len = xfer->length; 3149 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3150 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3151 3152 data = opipe->tail.td; 3153 mutex_enter(&sc->sc_lock); 3154 tail = ohci_alloc_std(sc); 3155 mutex_exit(&sc->sc_lock); 3156 if (tail == NULL) 3157 return (USBD_NOMEM); 3158 tail->xfer = NULL; 3159 3160 data->td.td_flags = HTOO32( 3161 isread ? OHCI_TD_IN : OHCI_TD_OUT | 3162 OHCI_TD_NOCC | 3163 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 3164 if (xfer->flags & USBD_SHORT_XFER_OK) 3165 data->td.td_flags |= HTOO32(OHCI_TD_R); 3166 data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0)); 3167 data->nexttd = tail; 3168 data->td.td_nexttd = HTOO32(tail->physaddr); 3169 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + len - 1); 3170 data->len = len; 3171 data->xfer = xfer; 3172 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 3173 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 3174 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3175 xfer->hcpriv = data; 3176 3177 #ifdef OHCI_DEBUG 3178 if (ohcidebug > 5) { 3179 DPRINTF(("ohci_device_intr_transfer:\n")); 3180 ohci_dump_ed(sc, sed); 3181 ohci_dump_tds(sc, data); 3182 } 3183 #endif 3184 3185 /* Insert ED in schedule */ 3186 mutex_enter(&sc->sc_lock); 3187 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3188 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3189 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3190 opipe->tail.td = tail; 3191 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3192 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3193 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3194 3195 #if 0 3196 /* 3197 * This goes horribly wrong, printing thousands of descriptors, 3198 * because false references are followed due to the fact that the 3199 * TD is gone. 3200 */ 3201 if (ohcidebug > 5) { 3202 usb_delay_ms_locked(&sc->sc_bus, 5, &sc->sc_lock); 3203 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3204 OREAD4(sc, OHCI_COMMAND_STATUS))); 3205 ohci_dump_ed(sc, sed); 3206 ohci_dump_tds(sc, data); 3207 } 3208 #endif 3209 mutex_exit(&sc->sc_lock); 3210 3211 return (USBD_IN_PROGRESS); 3212 } 3213 3214 /* Abort a device interrupt request. */ 3215 Static void 3216 ohci_device_intr_abort(usbd_xfer_handle xfer) 3217 { 3218 #ifdef DIAGNOSTIC 3219 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3220 #endif 3221 3222 KASSERT(mutex_owned(&sc->sc_lock)); 3223 KASSERT(xfer->pipe->intrxfer == xfer); 3224 3225 ohci_abort_xfer(xfer, USBD_CANCELLED); 3226 } 3227 3228 /* Close a device interrupt pipe. */ 3229 Static void 3230 ohci_device_intr_close(usbd_pipe_handle pipe) 3231 { 3232 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3233 ohci_softc_t *sc = pipe->device->bus->hci_private; 3234 int nslots = opipe->u.intr.nslots; 3235 int pos = opipe->u.intr.pos; 3236 int j; 3237 ohci_soft_ed_t *p, *sed = opipe->sed; 3238 3239 KASSERT(mutex_owned(&sc->sc_lock)); 3240 3241 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n", 3242 pipe, nslots, pos)); 3243 usb_syncmem(&sed->dma, sed->offs, 3244 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3245 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3246 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3247 sizeof(sed->ed.ed_flags), 3248 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3249 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3250 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3251 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3252 3253 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3254 continue; 3255 #ifdef DIAGNOSTIC 3256 if (p == NULL) 3257 panic("ohci_device_intr_close: ED not found"); 3258 #endif 3259 p->next = sed->next; 3260 p->ed.ed_nexted = sed->ed.ed_nexted; 3261 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3262 sizeof(p->ed.ed_nexted), 3263 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3264 3265 for (j = 0; j < nslots; j++) 3266 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3267 3268 ohci_free_std(sc, opipe->tail.td); 3269 ohci_free_sed(sc, opipe->sed); 3270 } 3271 3272 Static usbd_status 3273 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3274 { 3275 int i, j, best; 3276 u_int npoll, slow, shigh, nslots; 3277 u_int bestbw, bw; 3278 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3279 3280 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe)); 3281 if (ival == 0) { 3282 printf("ohci_setintr: 0 interval\n"); 3283 return (USBD_INVAL); 3284 } 3285 3286 npoll = OHCI_NO_INTRS; 3287 while (npoll > ival) 3288 npoll /= 2; 3289 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll)); 3290 3291 /* 3292 * We now know which level in the tree the ED must go into. 3293 * Figure out which slot has most bandwidth left over. 3294 * Slots to examine: 3295 * npoll 3296 * 1 0 3297 * 2 1 2 3298 * 4 3 4 5 6 3299 * 8 7 8 9 10 11 12 13 14 3300 * N (N-1) .. (N-1+N-1) 3301 */ 3302 slow = npoll-1; 3303 shigh = slow + npoll; 3304 nslots = OHCI_NO_INTRS / npoll; 3305 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3306 bw = 0; 3307 for (j = 0; j < nslots; j++) 3308 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3309 if (bw < bestbw) { 3310 best = i; 3311 bestbw = bw; 3312 } 3313 } 3314 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n", 3315 best, slow, shigh, bestbw)); 3316 3317 mutex_enter(&sc->sc_lock); 3318 hsed = sc->sc_eds[best]; 3319 sed->next = hsed->next; 3320 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3321 sizeof(hsed->ed.ed_flags), 3322 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3323 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3324 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3325 sizeof(sed->ed.ed_flags), 3326 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3327 hsed->next = sed; 3328 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3329 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3330 sizeof(hsed->ed.ed_flags), 3331 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3332 mutex_exit(&sc->sc_lock); 3333 3334 for (j = 0; j < nslots; j++) 3335 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3336 opipe->u.intr.nslots = nslots; 3337 opipe->u.intr.pos = best; 3338 3339 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe)); 3340 return (USBD_NORMAL_COMPLETION); 3341 } 3342 3343 /***********************/ 3344 3345 usbd_status 3346 ohci_device_isoc_transfer(usbd_xfer_handle xfer) 3347 { 3348 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3349 usbd_status err; 3350 3351 DPRINTFN(5,("ohci_device_isoc_transfer: xfer=%p\n", xfer)); 3352 3353 /* Put it on our queue, */ 3354 mutex_enter(&sc->sc_lock); 3355 err = usb_insert_transfer(xfer); 3356 mutex_exit(&sc->sc_lock); 3357 3358 /* bail out on error, */ 3359 if (err && err != USBD_IN_PROGRESS) 3360 return (err); 3361 3362 /* XXX should check inuse here */ 3363 3364 /* insert into schedule, */ 3365 ohci_device_isoc_enter(xfer); 3366 3367 /* and start if the pipe wasn't running */ 3368 if (!err) 3369 ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 3370 3371 return (err); 3372 } 3373 3374 void 3375 ohci_device_isoc_enter(usbd_xfer_handle xfer) 3376 { 3377 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3378 usbd_device_handle dev = opipe->pipe.device; 3379 ohci_softc_t *sc = dev->bus->hci_private; 3380 ohci_soft_ed_t *sed = opipe->sed; 3381 struct iso *iso = &opipe->u.iso; 3382 ohci_soft_itd_t *sitd, *nsitd; 3383 ohci_physaddr_t buf, offs, noffs, bp0; 3384 int i, ncur, nframes; 3385 3386 DPRINTFN(1,("ohci_device_isoc_enter: used=%d next=%d xfer=%p " 3387 "nframes=%d\n", 3388 iso->inuse, iso->next, xfer, xfer->nframes)); 3389 3390 if (sc->sc_dying) 3391 return; 3392 3393 if (iso->next == -1) { 3394 /* Not in use yet, schedule it a few frames ahead. */ 3395 iso->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3396 DPRINTFN(2,("ohci_device_isoc_enter: start next=%d\n", 3397 iso->next)); 3398 } 3399 3400 sitd = opipe->tail.itd; 3401 buf = DMAADDR(&xfer->dmabuf, 0); 3402 bp0 = OHCI_PAGE(buf); 3403 offs = OHCI_PAGE_OFFSET(buf); 3404 nframes = xfer->nframes; 3405 xfer->hcpriv = sitd; 3406 for (i = ncur = 0; i < nframes; i++, ncur++) { 3407 noffs = offs + xfer->frlengths[i]; 3408 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3409 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3410 3411 /* Allocate next ITD */ 3412 mutex_enter(&sc->sc_lock); 3413 nsitd = ohci_alloc_sitd(sc); 3414 mutex_exit(&sc->sc_lock); 3415 if (nsitd == NULL) { 3416 /* XXX what now? */ 3417 printf("%s: isoc TD alloc failed\n", 3418 device_xname(sc->sc_dev)); 3419 return; 3420 } 3421 3422 /* Fill current ITD */ 3423 sitd->itd.itd_flags = HTOO32( 3424 OHCI_ITD_NOCC | 3425 OHCI_ITD_SET_SF(iso->next) | 3426 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3427 OHCI_ITD_SET_FC(ncur)); 3428 sitd->itd.itd_bp0 = HTOO32(bp0); 3429 sitd->nextitd = nsitd; 3430 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3431 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3432 sitd->xfer = xfer; 3433 sitd->flags = 0; 3434 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3435 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3436 3437 sitd = nsitd; 3438 iso->next = iso->next + ncur; 3439 bp0 = OHCI_PAGE(buf + offs); 3440 ncur = 0; 3441 } 3442 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3443 offs = noffs; 3444 } 3445 mutex_enter(&sc->sc_lock); 3446 nsitd = ohci_alloc_sitd(sc); 3447 mutex_exit(&sc->sc_lock); 3448 if (nsitd == NULL) { 3449 /* XXX what now? */ 3450 printf("%s: isoc TD alloc failed\n", 3451 device_xname(sc->sc_dev)); 3452 return; 3453 } 3454 /* Fixup last used ITD */ 3455 sitd->itd.itd_flags = HTOO32( 3456 OHCI_ITD_NOCC | 3457 OHCI_ITD_SET_SF(iso->next) | 3458 OHCI_ITD_SET_DI(0) | 3459 OHCI_ITD_SET_FC(ncur)); 3460 sitd->itd.itd_bp0 = HTOO32(bp0); 3461 sitd->nextitd = nsitd; 3462 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3463 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3464 sitd->xfer = xfer; 3465 sitd->flags = OHCI_CALL_DONE; 3466 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3467 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3468 3469 iso->next = iso->next + ncur; 3470 iso->inuse += nframes; 3471 3472 xfer->actlen = offs; /* XXX pretend we did it all */ 3473 3474 xfer->status = USBD_IN_PROGRESS; 3475 3476 #ifdef OHCI_DEBUG 3477 if (ohcidebug > 5) { 3478 DPRINTF(("ohci_device_isoc_enter: frame=%d\n", 3479 O32TOH(sc->sc_hcca->hcca_frame_number))); 3480 ohci_dump_itds(sc, xfer->hcpriv); 3481 ohci_dump_ed(sc, sed); 3482 } 3483 #endif 3484 3485 mutex_enter(&sc->sc_lock); 3486 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3487 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3488 sed->ed.ed_tailp = HTOO32(nsitd->physaddr); 3489 opipe->tail.itd = nsitd; 3490 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3491 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3492 sizeof(sed->ed.ed_flags), 3493 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3494 mutex_exit(&sc->sc_lock); 3495 3496 #ifdef OHCI_DEBUG 3497 if (ohcidebug > 5) { 3498 delay(150000); 3499 DPRINTF(("ohci_device_isoc_enter: after frame=%d\n", 3500 O32TOH(sc->sc_hcca->hcca_frame_number))); 3501 ohci_dump_itds(sc, xfer->hcpriv); 3502 ohci_dump_ed(sc, sed); 3503 } 3504 #endif 3505 } 3506 3507 usbd_status 3508 ohci_device_isoc_start(usbd_xfer_handle xfer) 3509 { 3510 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3511 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 3512 3513 DPRINTFN(5,("ohci_device_isoc_start: xfer=%p\n", xfer)); 3514 3515 mutex_enter(&sc->sc_lock); 3516 3517 if (sc->sc_dying) { 3518 mutex_exit(&sc->sc_lock); 3519 return (USBD_IOERROR); 3520 } 3521 3522 #ifdef DIAGNOSTIC 3523 if (xfer->status != USBD_IN_PROGRESS) 3524 printf("ohci_device_isoc_start: not in progress %p\n", xfer); 3525 #endif 3526 3527 /* XXX anything to do? */ 3528 3529 mutex_exit(&sc->sc_lock); 3530 3531 return (USBD_IN_PROGRESS); 3532 } 3533 3534 void 3535 ohci_device_isoc_abort(usbd_xfer_handle xfer) 3536 { 3537 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3538 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 3539 ohci_soft_ed_t *sed; 3540 ohci_soft_itd_t *sitd; 3541 3542 DPRINTFN(1,("ohci_device_isoc_abort: xfer=%p lock=%p\n", xfer, &sc->sc_lock)); 3543 3544 KASSERT(mutex_owned(&sc->sc_lock)); 3545 3546 /* Transfer is already done. */ 3547 if (xfer->status != USBD_NOT_STARTED && 3548 xfer->status != USBD_IN_PROGRESS) { 3549 printf("ohci_device_isoc_abort: early return\n"); 3550 goto done; 3551 } 3552 3553 /* Give xfer the requested abort code. */ 3554 xfer->status = USBD_CANCELLED; 3555 3556 sed = opipe->sed; 3557 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3558 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3559 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3560 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3561 sizeof(sed->ed.ed_flags), 3562 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3563 3564 sitd = xfer->hcpriv; 3565 #ifdef DIAGNOSTIC 3566 if (sitd == NULL) { 3567 printf("ohci_device_isoc_abort: hcpriv==0\n"); 3568 goto done; 3569 } 3570 #endif 3571 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3572 #ifdef DIAGNOSTIC 3573 DPRINTFN(1,("abort sets done sitd=%p\n", sitd)); 3574 sitd->isdone = 1; 3575 #endif 3576 } 3577 3578 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3579 3580 /* Run callback. */ 3581 usb_transfer_complete(xfer); 3582 3583 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3584 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3585 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3586 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3587 3588 done: 3589 KASSERT(mutex_owned(&sc->sc_lock)); 3590 } 3591 3592 void 3593 ohci_device_isoc_done(usbd_xfer_handle xfer) 3594 { 3595 DPRINTFN(1,("ohci_device_isoc_done: xfer=%p\n", xfer)); 3596 } 3597 3598 usbd_status 3599 ohci_setup_isoc(usbd_pipe_handle pipe) 3600 { 3601 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3602 ohci_softc_t *sc = pipe->device->bus->hci_private; 3603 struct iso *iso = &opipe->u.iso; 3604 3605 iso->next = -1; 3606 iso->inuse = 0; 3607 3608 mutex_enter(&sc->sc_lock); 3609 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3610 mutex_exit(&sc->sc_lock); 3611 3612 return (USBD_NORMAL_COMPLETION); 3613 } 3614 3615 void 3616 ohci_device_isoc_close(usbd_pipe_handle pipe) 3617 { 3618 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3619 ohci_softc_t *sc = pipe->device->bus->hci_private; 3620 3621 KASSERT(mutex_owned(&sc->sc_lock)); 3622 3623 DPRINTF(("ohci_device_isoc_close: pipe=%p\n", pipe)); 3624 ohci_close_pipe(pipe, sc->sc_isoc_head); 3625 #ifdef DIAGNOSTIC 3626 opipe->tail.itd->isdone = 1; 3627 #endif 3628 ohci_free_sitd(sc, opipe->tail.itd); 3629 } 3630
Indexes created Fri Oct 03 02:09:57 GMT 2025