ohci.c revision 1.254.2.79
1 /* $NetBSD: ohci.c,v 1.254.2.79 2016/12/05 10:55:18 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * USB Open Host Controller driver. 38 * 39 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 40 * USB spec: http://www.usb.org/developers/docs/ 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.254.2.79 2016/12/05 10:55:18 skrll Exp $"); 45 46 #ifdef _KERNEL_OPT 47 #include "opt_usb.h" 48 #endif 49 50 #include <sys/param.h> 51 52 #include <sys/cpu.h> 53 #include <sys/device.h> 54 #include <sys/kernel.h> 55 #include <sys/kmem.h> 56 #include <sys/proc.h> 57 #include <sys/queue.h> 58 #include <sys/select.h> 59 #include <sys/sysctl.h> 60 #include <sys/systm.h> 61 62 #include <machine/endian.h> 63 64 #include <dev/usb/usb.h> 65 #include <dev/usb/usbdi.h> 66 #include <dev/usb/usbdivar.h> 67 #include <dev/usb/usb_mem.h> 68 #include <dev/usb/usb_quirks.h> 69 70 #include <dev/usb/ohcireg.h> 71 #include <dev/usb/ohcivar.h> 72 #include <dev/usb/usbroothub.h> 73 #include <dev/usb/usbhist.h> 74 75 #ifdef USB_DEBUG 76 #ifndef OHCI_DEBUG 77 #define ohcidebug 0 78 #else 79 static int ohcidebug = 10; 80 81 SYSCTL_SETUP(sysctl_hw_ohci_setup, "sysctl hw.ohci setup") 82 { 83 int err; 84 const struct sysctlnode *rnode; 85 const struct sysctlnode *cnode; 86 87 err = sysctl_createv(clog, 0, NULL, &rnode, 88 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ohci", 89 SYSCTL_DESCR("ohci global controls"), 90 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 91 92 if (err) 93 goto fail; 94 95 /* control debugging printfs */ 96 err = sysctl_createv(clog, 0, &rnode, &cnode, 97 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 98 "debug", SYSCTL_DESCR("Enable debugging output"), 99 NULL, 0, &ohcidebug, sizeof(ohcidebug), CTL_CREATE, CTL_EOL); 100 if (err) 101 goto fail; 102 103 return; 104 fail: 105 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 106 } 107 108 #endif /* OHCI_DEBUG */ 109 #endif /* USB_DEBUG */ 110 111 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ohcidebug,FMT,A,B,C,D) 112 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ohcidebug,N,FMT,A,B,C,D) 113 #define OHCIHIST_FUNC() USBHIST_FUNC() 114 #define OHCIHIST_CALLED(name) USBHIST_CALLED(ohcidebug) 115 116 #if BYTE_ORDER == BIG_ENDIAN 117 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 118 #else 119 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 120 #endif 121 122 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 123 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 124 #define HTOO16(val) O16TOH(val) 125 #define HTOO32(val) O32TOH(val) 126 127 struct ohci_pipe; 128 129 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 130 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 131 132 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 133 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 134 Static void ohci_free_std_locked(ohci_softc_t *, ohci_soft_td_t *); 135 136 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 137 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 138 Static void ohci_free_sitd_locked(ohci_softc_t *, 139 ohci_soft_itd_t *); 140 141 Static int ohci_alloc_std_chain(ohci_softc_t *, struct usbd_xfer *, 142 int, int); 143 Static void ohci_free_stds(ohci_softc_t *, struct ohci_xfer *); 144 145 Static void ohci_reset_std_chain(ohci_softc_t *, struct usbd_xfer *, 146 int, int, ohci_soft_td_t *, ohci_soft_td_t **); 147 148 Static usbd_status ohci_open(struct usbd_pipe *); 149 Static void ohci_poll(struct usbd_bus *); 150 Static void ohci_softintr(void *); 151 Static void ohci_rhsc(ohci_softc_t *, struct usbd_xfer *); 152 Static void ohci_rhsc_softint(void *); 153 154 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 155 ohci_soft_ed_t *); 156 157 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 158 ohci_soft_ed_t *); 159 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 160 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 161 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 162 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 163 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 164 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 165 166 Static usbd_status ohci_setup_isoc(struct usbd_pipe *); 167 Static void ohci_device_isoc_enter(struct usbd_xfer *); 168 169 Static struct usbd_xfer * 170 ohci_allocx(struct usbd_bus *, unsigned int); 171 Static void ohci_freex(struct usbd_bus *, struct usbd_xfer *); 172 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 173 Static int ohci_roothub_ctrl(struct usbd_bus *, 174 usb_device_request_t *, void *, int); 175 176 Static usbd_status ohci_root_intr_transfer(struct usbd_xfer *); 177 Static usbd_status ohci_root_intr_start(struct usbd_xfer *); 178 Static void ohci_root_intr_abort(struct usbd_xfer *); 179 Static void ohci_root_intr_close(struct usbd_pipe *); 180 Static void ohci_root_intr_done(struct usbd_xfer *); 181 182 Static int ohci_device_ctrl_init(struct usbd_xfer *); 183 Static void ohci_device_ctrl_fini(struct usbd_xfer *); 184 Static usbd_status ohci_device_ctrl_transfer(struct usbd_xfer *); 185 Static usbd_status ohci_device_ctrl_start(struct usbd_xfer *); 186 Static void ohci_device_ctrl_abort(struct usbd_xfer *); 187 Static void ohci_device_ctrl_close(struct usbd_pipe *); 188 Static void ohci_device_ctrl_done(struct usbd_xfer *); 189 190 Static int ohci_device_bulk_init(struct usbd_xfer *); 191 Static void ohci_device_bulk_fini(struct usbd_xfer *); 192 Static usbd_status ohci_device_bulk_transfer(struct usbd_xfer *); 193 Static usbd_status ohci_device_bulk_start(struct usbd_xfer *); 194 Static void ohci_device_bulk_abort(struct usbd_xfer *); 195 Static void ohci_device_bulk_close(struct usbd_pipe *); 196 Static void ohci_device_bulk_done(struct usbd_xfer *); 197 198 Static int ohci_device_intr_init(struct usbd_xfer *); 199 Static void ohci_device_intr_fini(struct usbd_xfer *); 200 Static usbd_status ohci_device_intr_transfer(struct usbd_xfer *); 201 Static usbd_status ohci_device_intr_start(struct usbd_xfer *); 202 Static void ohci_device_intr_abort(struct usbd_xfer *); 203 Static void ohci_device_intr_close(struct usbd_pipe *); 204 Static void ohci_device_intr_done(struct usbd_xfer *); 205 206 Static int ohci_device_isoc_init(struct usbd_xfer *); 207 Static void ohci_device_isoc_fini(struct usbd_xfer *); 208 Static usbd_status ohci_device_isoc_transfer(struct usbd_xfer *); 209 Static void ohci_device_isoc_abort(struct usbd_xfer *); 210 Static void ohci_device_isoc_close(struct usbd_pipe *); 211 Static void ohci_device_isoc_done(struct usbd_xfer *); 212 213 Static usbd_status ohci_device_setintr(ohci_softc_t *, 214 struct ohci_pipe *, int); 215 216 Static void ohci_timeout(void *); 217 Static void ohci_timeout_task(void *); 218 Static void ohci_rhsc_enable(void *); 219 220 Static void ohci_close_pipe(struct usbd_pipe *, ohci_soft_ed_t *); 221 Static void ohci_abort_xfer(struct usbd_xfer *, usbd_status); 222 223 Static void ohci_device_clear_toggle(struct usbd_pipe *); 224 Static void ohci_noop(struct usbd_pipe *); 225 226 #ifdef OHCI_DEBUG 227 Static void ohci_dumpregs(ohci_softc_t *); 228 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 229 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 230 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 231 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 232 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 233 #endif 234 235 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 236 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 237 #define OWRITE1(sc, r, x) \ 238 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 239 #define OWRITE2(sc, r, x) \ 240 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 241 #define OWRITE4(sc, r, x) \ 242 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 243 244 static __inline uint32_t 245 OREAD4(ohci_softc_t *sc, bus_size_t r) 246 { 247 248 OBARR(sc); 249 return bus_space_read_4(sc->iot, sc->ioh, r); 250 } 251 252 /* Reverse the bits in a value 0 .. 31 */ 253 Static uint8_t revbits[OHCI_NO_INTRS] = 254 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 255 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 256 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 257 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 258 259 struct ohci_pipe { 260 struct usbd_pipe pipe; 261 ohci_soft_ed_t *sed; 262 union { 263 ohci_soft_td_t *td; 264 ohci_soft_itd_t *itd; 265 } tail; 266 /* Info needed for different pipe kinds. */ 267 union { 268 /* Control pipe */ 269 struct { 270 usb_dma_t reqdma; 271 } ctrl; 272 /* Interrupt pipe */ 273 struct { 274 int nslots; 275 int pos; 276 } intr; 277 /* Isochronous pipe */ 278 struct isoc { 279 int next, inuse; 280 } isoc; 281 }; 282 }; 283 284 Static const struct usbd_bus_methods ohci_bus_methods = { 285 .ubm_open = ohci_open, 286 .ubm_softint = ohci_softintr, 287 .ubm_dopoll = ohci_poll, 288 .ubm_allocx = ohci_allocx, 289 .ubm_freex = ohci_freex, 290 .ubm_getlock = ohci_get_lock, 291 .ubm_rhctrl = ohci_roothub_ctrl, 292 }; 293 294 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 295 .upm_transfer = ohci_root_intr_transfer, 296 .upm_start = ohci_root_intr_start, 297 .upm_abort = ohci_root_intr_abort, 298 .upm_close = ohci_root_intr_close, 299 .upm_cleartoggle = ohci_noop, 300 .upm_done = ohci_root_intr_done, 301 }; 302 303 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 304 .upm_init = ohci_device_ctrl_init, 305 .upm_fini = ohci_device_ctrl_fini, 306 .upm_transfer = ohci_device_ctrl_transfer, 307 .upm_start = ohci_device_ctrl_start, 308 .upm_abort = ohci_device_ctrl_abort, 309 .upm_close = ohci_device_ctrl_close, 310 .upm_cleartoggle = ohci_noop, 311 .upm_done = ohci_device_ctrl_done, 312 }; 313 314 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 315 .upm_init = ohci_device_intr_init, 316 .upm_fini = ohci_device_intr_fini, 317 .upm_transfer = ohci_device_intr_transfer, 318 .upm_start = ohci_device_intr_start, 319 .upm_abort = ohci_device_intr_abort, 320 .upm_close = ohci_device_intr_close, 321 .upm_cleartoggle = ohci_device_clear_toggle, 322 .upm_done = ohci_device_intr_done, 323 }; 324 325 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 326 .upm_init = ohci_device_bulk_init, 327 .upm_fini = ohci_device_bulk_fini, 328 .upm_transfer = ohci_device_bulk_transfer, 329 .upm_start = ohci_device_bulk_start, 330 .upm_abort = ohci_device_bulk_abort, 331 .upm_close = ohci_device_bulk_close, 332 .upm_cleartoggle = ohci_device_clear_toggle, 333 .upm_done = ohci_device_bulk_done, 334 }; 335 336 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 337 .upm_init = ohci_device_isoc_init, 338 .upm_fini = ohci_device_isoc_fini, 339 .upm_transfer = ohci_device_isoc_transfer, 340 .upm_abort = ohci_device_isoc_abort, 341 .upm_close = ohci_device_isoc_close, 342 .upm_cleartoggle = ohci_noop, 343 .upm_done = ohci_device_isoc_done, 344 }; 345 346 int 347 ohci_activate(device_t self, enum devact act) 348 { 349 struct ohci_softc *sc = device_private(self); 350 351 switch (act) { 352 case DVACT_DEACTIVATE: 353 sc->sc_dying = 1; 354 return 0; 355 default: 356 return EOPNOTSUPP; 357 } 358 } 359 360 void 361 ohci_childdet(device_t self, device_t child) 362 { 363 struct ohci_softc *sc = device_private(self); 364 365 KASSERT(sc->sc_child == child); 366 sc->sc_child = NULL; 367 } 368 369 int 370 ohci_detach(struct ohci_softc *sc, int flags) 371 { 372 int rv = 0; 373 374 if (sc->sc_child != NULL) 375 rv = config_detach(sc->sc_child, flags); 376 377 if (rv != 0) 378 return rv; 379 380 callout_halt(&sc->sc_tmo_rhsc, &sc->sc_lock); 381 382 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 383 callout_destroy(&sc->sc_tmo_rhsc); 384 385 softint_disestablish(sc->sc_rhsc_si); 386 387 cv_destroy(&sc->sc_softwake_cv); 388 389 mutex_destroy(&sc->sc_lock); 390 mutex_destroy(&sc->sc_intr_lock); 391 392 if (sc->sc_hcca != NULL) 393 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 394 pool_cache_destroy(sc->sc_xferpool); 395 396 return rv; 397 } 398 399 ohci_soft_ed_t * 400 ohci_alloc_sed(ohci_softc_t *sc) 401 { 402 ohci_soft_ed_t *sed; 403 usbd_status err; 404 int i, offs; 405 usb_dma_t dma; 406 407 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 408 409 mutex_enter(&sc->sc_lock); 410 if (sc->sc_freeeds == NULL) { 411 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 412 mutex_exit(&sc->sc_lock); 413 414 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 415 OHCI_ED_ALIGN, &dma); 416 if (err) 417 return 0; 418 419 mutex_enter(&sc->sc_lock); 420 for (i = 0; i < OHCI_SED_CHUNK; i++) { 421 offs = i * OHCI_SED_SIZE; 422 sed = KERNADDR(&dma, offs); 423 sed->physaddr = DMAADDR(&dma, offs); 424 sed->dma = dma; 425 sed->offs = offs; 426 sed->next = sc->sc_freeeds; 427 sc->sc_freeeds = sed; 428 } 429 } 430 sed = sc->sc_freeeds; 431 sc->sc_freeeds = sed->next; 432 mutex_exit(&sc->sc_lock); 433 434 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 435 sed->next = 0; 436 return sed; 437 } 438 439 static inline void 440 ohci_free_sed_locked(ohci_softc_t *sc, ohci_soft_ed_t *sed) 441 { 442 443 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 444 445 sed->next = sc->sc_freeeds; 446 sc->sc_freeeds = sed; 447 } 448 449 void 450 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 451 { 452 453 mutex_enter(&sc->sc_lock); 454 ohci_free_sed_locked(sc, sed); 455 mutex_exit(&sc->sc_lock); 456 } 457 458 ohci_soft_td_t * 459 ohci_alloc_std(ohci_softc_t *sc) 460 { 461 ohci_soft_td_t *std; 462 usbd_status err; 463 int i, offs; 464 usb_dma_t dma; 465 466 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 467 468 mutex_enter(&sc->sc_lock); 469 if (sc->sc_freetds == NULL) { 470 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 471 mutex_exit(&sc->sc_lock); 472 473 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 474 OHCI_TD_ALIGN, &dma); 475 if (err) 476 return NULL; 477 478 mutex_enter(&sc->sc_lock); 479 for (i = 0; i < OHCI_STD_CHUNK; i++) { 480 offs = i * OHCI_STD_SIZE; 481 std = KERNADDR(&dma, offs); 482 std->physaddr = DMAADDR(&dma, offs); 483 std->dma = dma; 484 std->offs = offs; 485 std->nexttd = sc->sc_freetds; 486 sc->sc_freetds = std; 487 } 488 } 489 490 std = sc->sc_freetds; 491 sc->sc_freetds = std->nexttd; 492 mutex_exit(&sc->sc_lock); 493 494 memset(&std->td, 0, sizeof(ohci_td_t)); 495 std->nexttd = NULL; 496 std->xfer = NULL; 497 std->held = NULL; 498 499 return std; 500 } 501 502 void 503 ohci_free_std_locked(ohci_softc_t *sc, ohci_soft_td_t *std) 504 { 505 506 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 507 508 std->nexttd = sc->sc_freetds; 509 sc->sc_freetds = std; 510 } 511 512 void 513 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 514 { 515 516 mutex_enter(&sc->sc_lock); 517 ohci_free_std_locked(sc, std); 518 mutex_exit(&sc->sc_lock); 519 } 520 521 Static int 522 ohci_alloc_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, int length, int rd) 523 { 524 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 525 uint16_t flags = xfer->ux_flags; 526 527 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 528 529 DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d", 530 xfer->ux_pipe->up_dev->ud_addr, 531 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 532 length, xfer->ux_pipe->up_dev->ud_speed); 533 534 ASSERT_SLEEPABLE(); 535 KASSERT(length != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 536 537 size_t nstd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 538 nstd += ((length + OHCI_PAGE_SIZE - 1) / OHCI_PAGE_SIZE); 539 ox->ox_stds = kmem_zalloc(sizeof(ohci_soft_td_t *) * nstd, 540 KM_SLEEP); 541 ox->ox_nstd = nstd; 542 543 DPRINTFN(8, "xfer %p nstd %d", xfer, nstd, 0, 0); 544 545 for (size_t j = 0; j < ox->ox_nstd; j++) { 546 ohci_soft_td_t *cur = ohci_alloc_std(sc); 547 if (cur == NULL) 548 goto nomem; 549 550 ox->ox_stds[j] = cur; 551 cur->held = &ox->ox_stds[j]; 552 cur->xfer = xfer; 553 cur->flags = 0; 554 DPRINTFN(10, "xfer=%p new std=%p held at %p", ox, cur, 555 cur->held, 0); 556 } 557 558 return 0; 559 560 nomem: 561 ohci_free_stds(sc, ox); 562 kmem_free(ox->ox_stds, sizeof(ohci_soft_td_t *) * nstd); 563 564 return ENOMEM; 565 } 566 567 Static void 568 ohci_free_stds(ohci_softc_t *sc, struct ohci_xfer *ox) 569 { 570 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 571 DPRINTF("ox=%p", ox, 0, 0, 0); 572 573 mutex_enter(&sc->sc_lock); 574 for (size_t i = 0; i < ox->ox_nstd; i++) { 575 ohci_soft_td_t *std = ox->ox_stds[i]; 576 if (std == NULL) 577 break; 578 ohci_free_std_locked(sc, std); 579 } 580 mutex_exit(&sc->sc_lock); 581 } 582 583 void 584 ohci_reset_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, 585 int alen, int rd, ohci_soft_td_t *sp, ohci_soft_td_t **ep) 586 { 587 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 588 ohci_soft_td_t *next, *cur; 589 int len, curlen; 590 usb_dma_t *dma = &xfer->ux_dmabuf; 591 uint16_t flags = xfer->ux_flags; 592 593 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 594 DPRINTF("start len=%d", alen, 0, 0, 0); 595 596 KASSERT(mutex_owned(&sc->sc_lock)); 597 598 DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d", 599 xfer->ux_pipe->up_dev->ud_addr, 600 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 601 alen, xfer->ux_pipe->up_dev->ud_speed); 602 603 KASSERT(sp); 604 605 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 606 607 /* 608 * Assign next for the len == 0 case where we don't go through the 609 * main loop. 610 */ 611 len = alen; 612 cur = next = sp; 613 614 usb_syncmem(dma, 0, len, 615 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 616 const uint32_t tdflags = HTOO32( 617 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 618 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 619 620 size_t curoffs = 0; 621 for (size_t j = 1; len != 0;) { 622 if (j == ox->ox_nstd) 623 next = NULL; 624 else 625 next = ox->ox_stds[j++]; 626 KASSERT(next != cur); 627 628 curlen = 0; 629 ohci_physaddr_t sdataphys = DMAADDR(dma, curoffs); 630 ohci_physaddr_t edataphys = DMAADDR(dma, curoffs + len - 1); 631 632 ohci_physaddr_t sphyspg = OHCI_PAGE(sdataphys); 633 ohci_physaddr_t ephyspg = OHCI_PAGE(edataphys); 634 /* 635 * The OHCI hardware can handle at most one page 636 * crossing per TD 637 */ 638 curlen = len; 639 if (!(sphyspg == ephyspg || sphyspg + 1 == ephyspg)) { 640 /* must use multiple TDs, fill as much as possible. */ 641 curlen = 2 * OHCI_PAGE_SIZE - 642 (sdataphys & (OHCI_PAGE_SIZE - 1)); 643 /* the length must be a multiple of the max size */ 644 curlen -= curlen % mps; 645 } 646 KASSERT(curlen != 0); 647 DPRINTFN(4, "sdataphys=0x%08x edataphys=0x%08x " 648 "len=%d curlen=%d", sdataphys, edataphys, len, curlen); 649 650 cur->td.td_flags = tdflags; 651 cur->td.td_cbp = HTOO32(sdataphys); 652 cur->td.td_be = HTOO32(edataphys); 653 cur->td.td_nexttd = (next != NULL) ? HTOO32(next->physaddr) : 0; 654 cur->nexttd = next; 655 cur->len = curlen; 656 cur->flags = OHCI_ADD_LEN; 657 cur->xfer = xfer; 658 ohci_hash_add_td(sc, cur); 659 660 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 661 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 662 663 curoffs += curlen; 664 len -= curlen; 665 666 if (len != 0) { 667 KASSERT(next != NULL); 668 DPRINTFN(10, "extend chain", 0, 0, 0, 0); 669 cur = next; 670 } 671 } 672 cur->td.td_flags |= 673 HTOO32(xfer->ux_flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0); 674 675 if (!rd && 676 (flags & USBD_FORCE_SHORT_XFER) && 677 alen % mps == 0) { 678 /* Force a 0 length transfer at the end. */ 679 680 KASSERT(next != NULL); 681 cur = next; 682 683 cur->td.td_flags = tdflags; 684 cur->td.td_cbp = 0; /* indicate 0 length packet */ 685 cur->td.td_nexttd = 0; 686 cur->td.td_be = ~0; 687 cur->nexttd = NULL; 688 cur->len = 0; 689 cur->flags = 0; 690 cur->xfer = xfer; 691 ohci_hash_add_td(sc, cur); 692 693 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 694 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 695 DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0); 696 } 697 *ep = cur; 698 } 699 700 ohci_soft_itd_t * 701 ohci_alloc_sitd(ohci_softc_t *sc) 702 { 703 ohci_soft_itd_t *sitd; 704 usbd_status err; 705 int i, offs; 706 usb_dma_t dma; 707 708 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 709 710 mutex_enter(&sc->sc_lock); 711 if (sc->sc_freeitds == NULL) { 712 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 713 mutex_exit(&sc->sc_lock); 714 715 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 716 OHCI_ITD_ALIGN, &dma); 717 if (err) 718 return NULL; 719 mutex_enter(&sc->sc_lock); 720 for (i = 0; i < OHCI_SITD_CHUNK; i++) { 721 offs = i * OHCI_SITD_SIZE; 722 sitd = KERNADDR(&dma, offs); 723 sitd->physaddr = DMAADDR(&dma, offs); 724 sitd->dma = dma; 725 sitd->offs = offs; 726 sitd->nextitd = sc->sc_freeitds; 727 sc->sc_freeitds = sitd; 728 } 729 } 730 731 sitd = sc->sc_freeitds; 732 sc->sc_freeitds = sitd->nextitd; 733 mutex_exit(&sc->sc_lock); 734 735 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 736 sitd->nextitd = NULL; 737 sitd->xfer = NULL; 738 739 #ifdef DIAGNOSTIC 740 sitd->isdone = true; 741 #endif 742 743 return sitd; 744 } 745 746 Static void 747 ohci_free_sitd_locked(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 748 { 749 750 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 751 DPRINTFN(10, "sitd=%p", sitd, 0, 0, 0); 752 753 KASSERT(sitd->isdone); 754 #ifdef DIAGNOSTIC 755 /* Warn double free */ 756 sitd->isdone = false; 757 #endif 758 759 sitd->nextitd = sc->sc_freeitds; 760 sc->sc_freeitds = sitd; 761 } 762 763 void 764 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 765 { 766 767 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 768 769 mutex_enter(&sc->sc_lock); 770 ohci_free_sitd_locked(sc, sitd); 771 mutex_exit(&sc->sc_lock); 772 } 773 774 int 775 ohci_init(ohci_softc_t *sc) 776 { 777 ohci_soft_ed_t *sed, *psed; 778 usbd_status err; 779 int i; 780 uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */; 781 782 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 783 784 aprint_normal_dev(sc->sc_dev, ""); 785 786 sc->sc_hcca = NULL; 787 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 788 789 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 790 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 791 cv_init(&sc->sc_softwake_cv, "ohciab"); 792 793 sc->sc_rhsc_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 794 ohci_rhsc_softint, sc); 795 796 for (i = 0; i < OHCI_HASH_SIZE; i++) 797 LIST_INIT(&sc->sc_hash_tds[i]); 798 for (i = 0; i < OHCI_HASH_SIZE; i++) 799 LIST_INIT(&sc->sc_hash_itds[i]); 800 801 TAILQ_INIT(&sc->sc_abortingxfers); 802 803 sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0, 804 "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL); 805 806 rev = OREAD4(sc, OHCI_REVISION); 807 aprint_normal("OHCI version %d.%d%s\n", 808 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 809 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 810 811 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 812 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 813 sc->sc_bus.ub_revision = USBREV_UNKNOWN; 814 return -1; 815 } 816 sc->sc_bus.ub_revision = USBREV_1_0; 817 sc->sc_bus.ub_usedma = true; 818 819 /* XXX determine alignment by R/W */ 820 /* Allocate the HCCA area. */ 821 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 822 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 823 if (err) { 824 sc->sc_hcca = NULL; 825 return err; 826 } 827 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 828 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 829 830 sc->sc_eintrs = OHCI_NORMAL_INTRS; 831 832 /* Allocate dummy ED that starts the control list. */ 833 sc->sc_ctrl_head = ohci_alloc_sed(sc); 834 if (sc->sc_ctrl_head == NULL) { 835 err = ENOMEM; 836 goto bad1; 837 } 838 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 839 840 /* Allocate dummy ED that starts the bulk list. */ 841 sc->sc_bulk_head = ohci_alloc_sed(sc); 842 if (sc->sc_bulk_head == NULL) { 843 err = ENOMEM; 844 goto bad2; 845 } 846 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 847 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 848 sizeof(sc->sc_bulk_head->ed), 849 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 850 851 /* Allocate dummy ED that starts the isochronous list. */ 852 sc->sc_isoc_head = ohci_alloc_sed(sc); 853 if (sc->sc_isoc_head == NULL) { 854 err = ENOMEM; 855 goto bad3; 856 } 857 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 858 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 859 sizeof(sc->sc_isoc_head->ed), 860 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 861 862 /* Allocate all the dummy EDs that make up the interrupt tree. */ 863 for (i = 0; i < OHCI_NO_EDS; i++) { 864 sed = ohci_alloc_sed(sc); 865 if (sed == NULL) { 866 while (--i >= 0) 867 ohci_free_sed(sc, sc->sc_eds[i]); 868 err = ENOMEM; 869 goto bad4; 870 } 871 /* All ED fields are set to 0. */ 872 sc->sc_eds[i] = sed; 873 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 874 if (i != 0) 875 psed = sc->sc_eds[(i-1) / 2]; 876 else 877 psed= sc->sc_isoc_head; 878 sed->next = psed; 879 sed->ed.ed_nexted = HTOO32(psed->physaddr); 880 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 881 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 882 } 883 /* 884 * Fill HCCA interrupt table. The bit reversal is to get 885 * the tree set up properly to spread the interrupts. 886 */ 887 for (i = 0; i < OHCI_NO_INTRS; i++) 888 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 889 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 890 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 891 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 892 893 #ifdef OHCI_DEBUG 894 DPRINTFN(15, "--- dump start ---", 0, 0, 0 ,0); 895 if (ohcidebug >= 15) { 896 for (i = 0; i < OHCI_NO_EDS; i++) { 897 DPRINTFN(15, "ed#%d ", i, 0, 0, 0); 898 ohci_dump_ed(sc, sc->sc_eds[i]); 899 } 900 DPRINTFN(15, "iso", 0, 0, 0 ,0); 901 ohci_dump_ed(sc, sc->sc_isoc_head); 902 } 903 DPRINTFN(15, "--- dump end ---", 0, 0, 0 ,0); 904 #endif 905 906 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 907 ctl = OREAD4(sc, OHCI_CONTROL); 908 rwc = ctl & OHCI_RWC; 909 fm = OREAD4(sc, OHCI_FM_INTERVAL); 910 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 911 /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */ 912 913 /* Determine in what context we are running. */ 914 if (ctl & OHCI_IR) { 915 /* SMM active, request change */ 916 DPRINTF("SMM active, request owner change", 0, 0, 0, 0); 917 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 918 (OHCI_OC | OHCI_MIE)) 919 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 920 s = OREAD4(sc, OHCI_COMMAND_STATUS); 921 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 922 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 923 usb_delay_ms(&sc->sc_bus, 1); 924 ctl = OREAD4(sc, OHCI_CONTROL); 925 } 926 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 927 if ((ctl & OHCI_IR) == 0) { 928 aprint_error_dev(sc->sc_dev, 929 "SMM does not respond, resetting\n"); 930 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 931 goto reset; 932 } 933 #if 0 934 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 935 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 936 /* BIOS started controller. */ 937 DPRINTF("BIOS active", 0, 0, 0, 0); 938 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 939 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 940 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 941 } 942 #endif 943 } else { 944 DPRINTF("cold started", 0 ,0 ,0 ,0); 945 reset: 946 /* Controller was cold started. */ 947 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 948 } 949 950 /* 951 * This reset should not be necessary according to the OHCI spec, but 952 * without it some controllers do not start. 953 */ 954 DPRINTF("sc %p: resetting", sc, 0, 0, 0); 955 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 956 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 957 958 /* We now own the host controller and the bus has been reset. */ 959 960 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 961 /* Nominal time for a reset is 10 us. */ 962 for (i = 0; i < 10; i++) { 963 delay(10); 964 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 965 if (!hcr) 966 break; 967 } 968 if (hcr) { 969 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 970 err = EIO; 971 goto bad5; 972 } 973 #ifdef OHCI_DEBUG 974 if (ohcidebug >= 15) 975 ohci_dumpregs(sc); 976 #endif 977 978 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 979 980 /* Set up HC registers. */ 981 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 982 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 983 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 984 /* disable all interrupts and then switch on all desired interrupts */ 985 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 986 /* switch on desired functional features */ 987 ctl = OREAD4(sc, OHCI_CONTROL); 988 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 989 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 990 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 991 /* And finally start it! */ 992 OWRITE4(sc, OHCI_CONTROL, ctl); 993 994 /* 995 * The controller is now OPERATIONAL. Set a some final 996 * registers that should be set earlier, but that the 997 * controller ignores when in the SUSPEND state. 998 */ 999 ival = OHCI_GET_IVAL(fm); 1000 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 1001 fm |= OHCI_FSMPS(ival) | ival; 1002 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 1003 per = OHCI_PERIODIC(ival); /* 90% periodic */ 1004 OWRITE4(sc, OHCI_PERIODIC_START, per); 1005 1006 if (sc->sc_flags & OHCIF_SUPERIO) { 1007 /* no overcurrent protection */ 1008 desca |= OHCI_NOCP; 1009 /* 1010 * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning 1011 * that 1012 * - ports are always power switched 1013 * - don't wait for powered root hub port 1014 */ 1015 desca &= ~(__SHIFTIN(0xff, OHCI_POTPGT_MASK) | OHCI_NPS); 1016 } 1017 1018 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 1019 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 1020 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 1021 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 1022 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 1023 1024 /* 1025 * The AMD756 requires a delay before re-reading the register, 1026 * otherwise it will occasionally report 0 ports. 1027 */ 1028 sc->sc_noport = 0; 1029 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 1030 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 1031 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 1032 } 1033 1034 #ifdef OHCI_DEBUG 1035 if (ohcidebug >= 5) 1036 ohci_dumpregs(sc); 1037 #endif 1038 1039 /* Set up the bus struct. */ 1040 sc->sc_bus.ub_methods = &ohci_bus_methods; 1041 sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe); 1042 1043 sc->sc_control = sc->sc_intre = 0; 1044 1045 /* Finally, turn on interrupts. */ 1046 DPRINTF("enabling %#x", sc->sc_eintrs | OHCI_MIE, 0, 0, 0); 1047 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 1048 1049 return 0; 1050 1051 bad5: 1052 for (i = 0; i < OHCI_NO_EDS; i++) 1053 ohci_free_sed(sc, sc->sc_eds[i]); 1054 bad4: 1055 ohci_free_sed(sc, sc->sc_isoc_head); 1056 bad3: 1057 ohci_free_sed(sc, sc->sc_bulk_head); 1058 bad2: 1059 ohci_free_sed(sc, sc->sc_ctrl_head); 1060 bad1: 1061 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 1062 sc->sc_hcca = NULL; 1063 return err; 1064 } 1065 1066 struct usbd_xfer * 1067 ohci_allocx(struct usbd_bus *bus, unsigned int nframes) 1068 { 1069 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1070 struct usbd_xfer *xfer; 1071 1072 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1073 if (xfer != NULL) { 1074 memset(xfer, 0, sizeof(struct ohci_xfer)); 1075 #ifdef DIAGNOSTIC 1076 xfer->ux_state = XFER_BUSY; 1077 #endif 1078 } 1079 return xfer; 1080 } 1081 1082 void 1083 ohci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1084 { 1085 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1086 1087 KASSERTMSG(xfer->ux_state == XFER_BUSY, 1088 "xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state); 1089 #ifdef DIAGNOSTIC 1090 xfer->ux_state = XFER_FREE; 1091 #endif 1092 pool_cache_put(sc->sc_xferpool, xfer); 1093 } 1094 1095 Static void 1096 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1097 { 1098 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1099 1100 *lock = &sc->sc_lock; 1101 } 1102 1103 /* 1104 * Shut down the controller when the system is going down. 1105 */ 1106 bool 1107 ohci_shutdown(device_t self, int flags) 1108 { 1109 ohci_softc_t *sc = device_private(self); 1110 1111 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1112 1113 DPRINTF("stopping the HC", 0, 0, 0, 0); 1114 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1115 return true; 1116 } 1117 1118 bool 1119 ohci_resume(device_t dv, const pmf_qual_t *qual) 1120 { 1121 ohci_softc_t *sc = device_private(dv); 1122 uint32_t ctl; 1123 1124 mutex_spin_enter(&sc->sc_intr_lock); 1125 sc->sc_bus.ub_usepolling++; 1126 mutex_spin_exit(&sc->sc_intr_lock); 1127 1128 /* Some broken BIOSes do not recover these values */ 1129 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1130 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1131 sc->sc_ctrl_head->physaddr); 1132 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1133 sc->sc_bulk_head->physaddr); 1134 if (sc->sc_intre) 1135 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1136 (OHCI_ALL_INTRS | OHCI_MIE)); 1137 if (sc->sc_control) 1138 ctl = sc->sc_control; 1139 else 1140 ctl = OREAD4(sc, OHCI_CONTROL); 1141 ctl |= OHCI_HCFS_RESUME; 1142 OWRITE4(sc, OHCI_CONTROL, ctl); 1143 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1144 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1145 OWRITE4(sc, OHCI_CONTROL, ctl); 1146 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1147 sc->sc_control = sc->sc_intre = 0; 1148 1149 mutex_spin_enter(&sc->sc_intr_lock); 1150 sc->sc_bus.ub_usepolling--; 1151 mutex_spin_exit(&sc->sc_intr_lock); 1152 1153 return true; 1154 } 1155 1156 bool 1157 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1158 { 1159 ohci_softc_t *sc = device_private(dv); 1160 uint32_t ctl; 1161 1162 mutex_spin_enter(&sc->sc_intr_lock); 1163 sc->sc_bus.ub_usepolling++; 1164 mutex_spin_exit(&sc->sc_intr_lock); 1165 1166 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1167 if (sc->sc_control == 0) { 1168 /* 1169 * Preserve register values, in case that BIOS 1170 * does not recover them. 1171 */ 1172 sc->sc_control = ctl; 1173 sc->sc_intre = OREAD4(sc, 1174 OHCI_INTERRUPT_ENABLE); 1175 } 1176 ctl |= OHCI_HCFS_SUSPEND; 1177 OWRITE4(sc, OHCI_CONTROL, ctl); 1178 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1179 1180 mutex_spin_enter(&sc->sc_intr_lock); 1181 sc->sc_bus.ub_usepolling--; 1182 mutex_spin_exit(&sc->sc_intr_lock); 1183 1184 return true; 1185 } 1186 1187 #ifdef OHCI_DEBUG 1188 void 1189 ohci_dumpregs(ohci_softc_t *sc) 1190 { 1191 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1192 1193 DPRINTF("rev=0x%08x control=0x%08x command=0x%08x", 1194 OREAD4(sc, OHCI_REVISION), 1195 OREAD4(sc, OHCI_CONTROL), 1196 OREAD4(sc, OHCI_COMMAND_STATUS), 0); 1197 DPRINTF(" intrstat=0x%08x intre=0x%08x intrd=0x%08x", 1198 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1199 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1200 OREAD4(sc, OHCI_INTERRUPT_DISABLE), 0); 1201 DPRINTF(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x", 1202 OREAD4(sc, OHCI_HCCA), 1203 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1204 OREAD4(sc, OHCI_CONTROL_HEAD_ED), 0); 1205 DPRINTF(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x", 1206 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1207 OREAD4(sc, OHCI_BULK_HEAD_ED), 1208 OREAD4(sc, OHCI_BULK_CURRENT_ED) ,0); 1209 DPRINTF(" done=0x%08x fmival=0x%08x fmrem=0x%08x", 1210 OREAD4(sc, OHCI_DONE_HEAD), 1211 OREAD4(sc, OHCI_FM_INTERVAL), 1212 OREAD4(sc, OHCI_FM_REMAINING), 0); 1213 DPRINTF(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x", 1214 OREAD4(sc, OHCI_FM_NUMBER), 1215 OREAD4(sc, OHCI_PERIODIC_START), 1216 OREAD4(sc, OHCI_LS_THRESHOLD), 0); 1217 DPRINTF(" desca=0x%08x descb=0x%08x stat=0x%08x", 1218 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1219 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1220 OREAD4(sc, OHCI_RH_STATUS), 0); 1221 DPRINTF(" port1=0x%08x port2=0x%08x", 1222 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1223 OREAD4(sc, OHCI_RH_PORT_STATUS(2)), 0, 0); 1224 DPRINTF(" HCCA: frame_number=0x%04x done_head=0x%08x", 1225 O32TOH(sc->sc_hcca->hcca_frame_number), 1226 O32TOH(sc->sc_hcca->hcca_done_head), 0, 0); 1227 } 1228 #endif 1229 1230 Static int ohci_intr1(ohci_softc_t *); 1231 1232 int 1233 ohci_intr(void *p) 1234 { 1235 ohci_softc_t *sc = p; 1236 int ret = 0; 1237 1238 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1239 1240 if (sc == NULL) 1241 return 0; 1242 1243 mutex_spin_enter(&sc->sc_intr_lock); 1244 1245 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1246 goto done; 1247 1248 /* If we get an interrupt while polling, then just ignore it. */ 1249 if (sc->sc_bus.ub_usepolling) { 1250 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1251 /* for level triggered intrs, should do something to ack */ 1252 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1253 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1254 1255 goto done; 1256 } 1257 1258 ret = ohci_intr1(sc); 1259 1260 done: 1261 mutex_spin_exit(&sc->sc_intr_lock); 1262 return ret; 1263 } 1264 1265 Static int 1266 ohci_intr1(ohci_softc_t *sc) 1267 { 1268 uint32_t intrs, eintrs; 1269 1270 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1271 1272 /* In case the interrupt occurs before initialization has completed. */ 1273 if (sc == NULL || sc->sc_hcca == NULL) { 1274 #ifdef DIAGNOSTIC 1275 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1276 #endif 1277 return 0; 1278 } 1279 1280 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1281 1282 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1283 if (!intrs) 1284 return 0; 1285 1286 /* Acknowledge */ 1287 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); 1288 eintrs = intrs & sc->sc_eintrs; 1289 DPRINTFN(7, "sc=%p", sc, 0, 0, 0); 1290 DPRINTFN(7, "intrs=%#x(%#x) eintrs=%#x(%#x)", 1291 intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), eintrs, 1292 sc->sc_eintrs); 1293 1294 if (!eintrs) { 1295 return 0; 1296 } 1297 1298 if (eintrs & OHCI_SO) { 1299 sc->sc_overrun_cnt++; 1300 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1301 printf("%s: %u scheduling overruns\n", 1302 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1303 sc->sc_overrun_cnt = 0; 1304 } 1305 /* XXX do what */ 1306 eintrs &= ~OHCI_SO; 1307 } 1308 if (eintrs & OHCI_WDH) { 1309 /* 1310 * We block the interrupt below, and reenable it later from 1311 * ohci_softintr(). 1312 */ 1313 usb_schedsoftintr(&sc->sc_bus); 1314 } 1315 if (eintrs & OHCI_RD) { 1316 DPRINTFN(5, "resume detect", sc, 0, 0, 0); 1317 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1318 /* XXX process resume detect */ 1319 } 1320 if (eintrs & OHCI_UE) { 1321 DPRINTFN(5, "unrecoverable error", sc, 0, 0, 0); 1322 printf("%s: unrecoverable error, controller halted\n", 1323 device_xname(sc->sc_dev)); 1324 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1325 /* XXX what else */ 1326 } 1327 if (eintrs & OHCI_RHSC) { 1328 /* 1329 * We block the interrupt below, and reenable it later from 1330 * a timeout. 1331 */ 1332 softint_schedule(sc->sc_rhsc_si); 1333 } 1334 if (eintrs & OHCI_SF) { 1335 struct ohci_xfer *ox, *tmp; 1336 TAILQ_FOREACH_SAFE(ox, &sc->sc_abortingxfers, ox_abnext, tmp) { 1337 DPRINTFN(10, "SF %p xfer %p", sc, ox, 0, 0); 1338 ox->ox_abintrs &= ~OHCI_SF; 1339 KASSERT(ox->ox_abintrs == 0); 1340 TAILQ_REMOVE(&sc->sc_abortingxfers, ox, ox_abnext); 1341 } 1342 cv_broadcast(&sc->sc_softwake_cv); 1343 1344 KASSERT(TAILQ_EMPTY(&sc->sc_abortingxfers)); 1345 DPRINTFN(10, "end SOF %p", sc, 0, 0, 0); 1346 /* Don't remove OHIC_SF from eintrs so it is blocked below */ 1347 } 1348 1349 if (eintrs != 0) { 1350 /* Block unprocessed interrupts. */ 1351 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1352 sc->sc_eintrs &= ~eintrs; 1353 DPRINTF("sc %p blocking/removing intrs 0x%x", sc, eintrs, 0, 0); 1354 } 1355 1356 return 1; 1357 } 1358 1359 void 1360 ohci_rhsc_enable(void *v_sc) 1361 { 1362 ohci_softc_t *sc = v_sc; 1363 1364 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1365 DPRINTF("sc %p", sc, 0, 0, 0); 1366 mutex_spin_enter(&sc->sc_intr_lock); 1367 sc->sc_eintrs |= OHCI_RHSC; 1368 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1369 mutex_spin_exit(&sc->sc_intr_lock); 1370 } 1371 1372 #ifdef OHCI_DEBUG 1373 const char *ohci_cc_strs[] = { 1374 "NO_ERROR", 1375 "CRC", 1376 "BIT_STUFFING", 1377 "DATA_TOGGLE_MISMATCH", 1378 "STALL", 1379 "DEVICE_NOT_RESPONDING", 1380 "PID_CHECK_FAILURE", 1381 "UNEXPECTED_PID", 1382 "DATA_OVERRUN", 1383 "DATA_UNDERRUN", 1384 "BUFFER_OVERRUN", 1385 "BUFFER_UNDERRUN", 1386 "reserved", 1387 "reserved", 1388 "NOT_ACCESSED", 1389 "NOT_ACCESSED", 1390 }; 1391 #endif 1392 1393 void 1394 ohci_softintr(void *v) 1395 { 1396 struct usbd_bus *bus = v; 1397 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1398 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1399 ohci_soft_td_t *std, *sdone, *stdnext; 1400 struct usbd_xfer *xfer; 1401 struct ohci_pipe *opipe; 1402 int len, cc; 1403 int i, j, actlen, iframes, uedir; 1404 ohci_physaddr_t done = 0; 1405 1406 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1407 1408 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1409 1410 /* 1411 * Only read hccadone if WDH is set - we might get here from places 1412 * other than an interrupt 1413 */ 1414 if (!(OREAD4(sc, OHCI_INTERRUPT_STATUS) & OHCI_WDH)) { 1415 DPRINTFN(10, "no WDH %p", sc, 0, 0, 0); 1416 return; 1417 } 1418 1419 DPRINTFN(10, "WDH %p", sc, 0, 0, 0); 1420 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1421 sizeof(sc->sc_hcca->hcca_done_head), 1422 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1423 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1424 sc->sc_hcca->hcca_done_head = 0; 1425 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1426 sizeof(sc->sc_hcca->hcca_done_head), 1427 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1428 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1429 sc->sc_eintrs |= OHCI_WDH; 1430 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1431 1432 /* Reverse the done list. */ 1433 for (sdone = NULL, sidone = NULL; done != 0; ) { 1434 std = ohci_hash_find_td(sc, done); 1435 if (std != NULL) { 1436 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1437 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1438 std->dnext = sdone; 1439 done = O32TOH(std->td.td_nexttd); 1440 sdone = std; 1441 DPRINTFN(10, "add TD %p", std, 0, 0, 0); 1442 continue; 1443 } 1444 sitd = ohci_hash_find_itd(sc, done); 1445 if (sitd != NULL) { 1446 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1447 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1448 sitd->dnext = sidone; 1449 done = O32TOH(sitd->itd.itd_nextitd); 1450 sidone = sitd; 1451 DPRINTFN(5, "add ITD %p", sitd, 0, 0, 0); 1452 continue; 1453 } 1454 DPRINTFN(10, "addr %p not found", done, 0, 0, 0); 1455 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1456 (u_long)done); 1457 break; 1458 } 1459 1460 DPRINTFN(10, "sdone=%p sidone=%p", sdone, sidone, 0, 0); 1461 DPRINTFN(10, "--- TD dump start ---", 0, 0, 0, 0); 1462 #ifdef OHCI_DEBUG 1463 if (ohcidebug >= 10) { 1464 for (std = sdone; std; std = std->dnext) 1465 ohci_dump_td(sc, std); 1466 } 1467 #endif 1468 DPRINTFN(10, "--- TD dump end ---", 0, 0, 0, 0); 1469 1470 for (std = sdone; std; std = stdnext) { 1471 xfer = std->xfer; 1472 stdnext = std->dnext; 1473 DPRINTFN(10, "std=%p xfer=%p hcpriv=%p dnext=%p", std, xfer, 1474 xfer ? xfer->ux_hcpriv : 0, stdnext); 1475 if (xfer == NULL) { 1476 /* 1477 * xfer == NULL: There seems to be no xfer associated 1478 * with this TD. It is tailp that happened to end up on 1479 * the done queue. 1480 * Shouldn't happen, but some chips are broken(?). 1481 */ 1482 continue; 1483 } 1484 if (std->held == NULL) { 1485 DPRINTFN(10, "std=%p held is null", std, 0, 0, 0); 1486 ohci_hash_rem_td(sc, std); 1487 ohci_free_std_locked(sc, std); 1488 continue; 1489 } 1490 /* 1491 * Make sure the timeout handler didn't run or ran to the end 1492 * and set the transfer status. 1493 */ 1494 callout_halt(&xfer->ux_callout, &sc->sc_lock); 1495 1496 if (xfer->ux_status == USBD_CANCELLED || 1497 xfer->ux_status == USBD_TIMEOUT) { 1498 DPRINTF("cancel/timeout %p", xfer, 0, 0, 0); 1499 1500 /* Handled by abort routine. */ 1501 continue; 1502 } 1503 1504 len = std->len; 1505 if (std->td.td_cbp != 0) 1506 len -= O32TOH(std->td.td_be) - 1507 O32TOH(std->td.td_cbp) + 1; 1508 DPRINTFN(10, "len=%d, flags=0x%x", len, std->flags, 0, 0); 1509 if (std->flags & OHCI_ADD_LEN) 1510 xfer->ux_actlen += len; 1511 1512 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1513 if (cc == OHCI_CC_NO_ERROR) { 1514 ohci_hash_rem_td(sc, std); 1515 if (std->flags & OHCI_CALL_DONE) { 1516 xfer->ux_status = USBD_NORMAL_COMPLETION; 1517 usb_transfer_complete(xfer); 1518 } 1519 } else { 1520 /* 1521 * Endpoint is halted. First unlink all the TDs 1522 * belonging to the failed transfer, and then restart 1523 * the endpoint. 1524 */ 1525 ohci_soft_td_t *p, *n; 1526 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1527 1528 DPRINTFN(10, "error cc=%d", cc, 0, 0, 0); 1529 1530 /* remove xfer's TDs from the hash */ 1531 for (p = std; p->xfer == xfer; p = n) { 1532 n = p->nexttd; 1533 ohci_hash_rem_td(sc, p); 1534 } 1535 1536 ohci_soft_ed_t *sed = opipe->sed; 1537 1538 /* clear halt and TD chain */ 1539 sed->ed.ed_headp = HTOO32(p->physaddr); 1540 usb_syncmem(&sed->dma, 1541 sed->offs + offsetof(ohci_ed_t, ed_headp), 1542 sizeof(sed->ed.ed_headp), 1543 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1544 1545 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1546 1547 if (cc == OHCI_CC_DATA_UNDERRUN) 1548 xfer->ux_status = USBD_NORMAL_COMPLETION; 1549 else if (cc == OHCI_CC_STALL) 1550 xfer->ux_status = USBD_STALLED; 1551 else 1552 xfer->ux_status = USBD_IOERROR; 1553 usb_transfer_complete(xfer); 1554 } 1555 } 1556 DPRINTFN(10, "--- ITD dump start ---", 0, 0, 0, 0); 1557 #ifdef OHCI_DEBUG 1558 if (ohcidebug >= 10) { 1559 for (sitd = sidone; sitd; sitd = sitd->dnext) 1560 ohci_dump_itd(sc, sitd); 1561 } 1562 #endif 1563 DPRINTFN(10, "--- ITD dump end ---", 0, 0, 0, 0); 1564 1565 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1566 xfer = sitd->xfer; 1567 sitdnext = sitd->dnext; 1568 DPRINTFN(1, "sitd=%p xfer=%p hcpriv=%p", sitd, xfer, 1569 xfer ? xfer->ux_hcpriv : 0, 0); 1570 if (xfer == NULL) 1571 continue; 1572 if (xfer->ux_status == USBD_CANCELLED || 1573 xfer->ux_status == USBD_TIMEOUT) { 1574 DPRINTF("cancel/timeout %p", xfer, 0, 0, 0); 1575 /* Handled by abort routine. */ 1576 continue; 1577 } 1578 KASSERT(!sitd->isdone); 1579 #ifdef DIAGNOSTIC 1580 sitd->isdone = true; 1581 #endif 1582 if (sitd->flags & OHCI_CALL_DONE) { 1583 ohci_soft_itd_t *next; 1584 1585 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1586 opipe->isoc.inuse -= xfer->ux_nframes; 1587 uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc-> 1588 bEndpointAddress); 1589 xfer->ux_status = USBD_NORMAL_COMPLETION; 1590 actlen = 0; 1591 for (i = 0, sitd = xfer->ux_hcpriv;; 1592 sitd = next) { 1593 next = sitd->nextitd; 1594 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1595 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1596 xfer->ux_status = USBD_IOERROR; 1597 /* For input, update frlengths with actual */ 1598 /* XXX anything necessary for output? */ 1599 if (uedir == UE_DIR_IN && 1600 xfer->ux_status == USBD_NORMAL_COMPLETION) { 1601 iframes = OHCI_ITD_GET_FC(O32TOH( 1602 sitd->itd.itd_flags)); 1603 for (j = 0; j < iframes; i++, j++) { 1604 len = O16TOH(sitd-> 1605 itd.itd_offset[j]); 1606 if ((OHCI_ITD_PSW_GET_CC(len) & 1607 OHCI_CC_NOT_ACCESSED_MASK) 1608 == OHCI_CC_NOT_ACCESSED) 1609 len = 0; 1610 else 1611 len = OHCI_ITD_PSW_LENGTH(len); 1612 xfer->ux_frlengths[i] = len; 1613 actlen += len; 1614 } 1615 } 1616 if (sitd->flags & OHCI_CALL_DONE) 1617 break; 1618 ohci_hash_rem_itd(sc, sitd); 1619 1620 } 1621 ohci_hash_rem_itd(sc, sitd); 1622 if (uedir == UE_DIR_IN && 1623 xfer->ux_status == USBD_NORMAL_COMPLETION) 1624 xfer->ux_actlen = actlen; 1625 xfer->ux_hcpriv = NULL; 1626 1627 usb_transfer_complete(xfer); 1628 } 1629 } 1630 1631 DPRINTFN(10, "done", 0, 0, 0, 0); 1632 } 1633 1634 void 1635 ohci_device_ctrl_done(struct usbd_xfer *xfer) 1636 { 1637 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1638 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1639 int len = UGETW(xfer->ux_request.wLength); 1640 int isread = (xfer->ux_request.bmRequestType & UT_READ); 1641 1642 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1643 DPRINTFN(10, "xfer=%p", xfer, 0, 0, 0); 1644 1645 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1646 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 1647 1648 if (len) 1649 usb_syncmem(&xfer->ux_dmabuf, 0, len, 1650 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1651 usb_syncmem(&opipe->ctrl.reqdma, 0, 1652 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1653 } 1654 1655 void 1656 ohci_device_intr_done(struct usbd_xfer *xfer) 1657 { 1658 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1659 int isread = 1660 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1661 1662 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1663 DPRINTFN(10, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0); 1664 1665 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1666 1667 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1668 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1669 } 1670 1671 void 1672 ohci_device_bulk_done(struct usbd_xfer *xfer) 1673 { 1674 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1675 1676 int isread = 1677 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1678 1679 KASSERT(mutex_owned(&sc->sc_lock)); 1680 1681 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1682 DPRINTFN(10, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0); 1683 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1684 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1685 } 1686 1687 Static void 1688 ohci_rhsc_softint(void *arg) 1689 { 1690 ohci_softc_t *sc = arg; 1691 1692 mutex_enter(&sc->sc_lock); 1693 1694 ohci_rhsc(sc, sc->sc_intrxfer); 1695 1696 /* Do not allow RHSC interrupts > 1 per second */ 1697 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1698 1699 mutex_exit(&sc->sc_lock); 1700 } 1701 1702 void 1703 ohci_rhsc(ohci_softc_t *sc, struct usbd_xfer *xfer) 1704 { 1705 u_char *p; 1706 int i, m; 1707 int hstatus __unused; 1708 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1709 1710 KASSERT(mutex_owned(&sc->sc_lock)); 1711 1712 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1713 DPRINTF("sc=%p xfer=%p hstatus=0x%08x", sc, xfer, hstatus, 0); 1714 1715 if (xfer == NULL) { 1716 /* Just ignore the change. */ 1717 return; 1718 } 1719 1720 p = xfer->ux_buf; 1721 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 1722 memset(p, 0, xfer->ux_length); 1723 for (i = 1; i <= m; i++) { 1724 /* Pick out CHANGE bits from the status reg. */ 1725 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1726 p[i/8] |= 1 << (i%8); 1727 } 1728 DPRINTF("change=0x%02x", *p, 0, 0, 0); 1729 xfer->ux_actlen = xfer->ux_length; 1730 xfer->ux_status = USBD_NORMAL_COMPLETION; 1731 1732 usb_transfer_complete(xfer); 1733 } 1734 1735 void 1736 ohci_root_intr_done(struct usbd_xfer *xfer) 1737 { 1738 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1739 1740 KASSERT(mutex_owned(&sc->sc_lock)); 1741 1742 KASSERT(sc->sc_intrxfer == xfer); 1743 sc->sc_intrxfer = NULL; 1744 } 1745 1746 void 1747 ohci_poll(struct usbd_bus *bus) 1748 { 1749 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1750 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1751 1752 #ifdef OHCI_DEBUG 1753 static int last; 1754 int new; 1755 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1756 if (new != last) { 1757 DPRINTFN(10, "intrs=0x%04x", new, 0, 0, 0); 1758 last = new; 1759 } 1760 #endif 1761 sc->sc_eintrs |= OHCI_WDH; 1762 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1763 mutex_spin_enter(&sc->sc_intr_lock); 1764 ohci_intr1(sc); 1765 mutex_spin_exit(&sc->sc_intr_lock); 1766 } 1767 } 1768 1769 /* 1770 * Add an ED to the schedule. Called with USB lock held. 1771 */ 1772 Static void 1773 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1774 { 1775 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1776 DPRINTFN(8, "sed=%p head=%p", sed, head, 0, 0); 1777 1778 KASSERT(mutex_owned(&sc->sc_lock)); 1779 1780 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1781 sizeof(head->ed.ed_nexted), 1782 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1783 sed->next = head->next; 1784 sed->ed.ed_nexted = head->ed.ed_nexted; 1785 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1786 sizeof(sed->ed.ed_nexted), 1787 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1788 head->next = sed; 1789 head->ed.ed_nexted = HTOO32(sed->physaddr); 1790 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1791 sizeof(head->ed.ed_nexted), 1792 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1793 } 1794 1795 /* 1796 * Remove an ED from the schedule. Called with USB lock held. 1797 */ 1798 Static void 1799 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1800 { 1801 ohci_soft_ed_t *p; 1802 1803 KASSERT(mutex_owned(&sc->sc_lock)); 1804 1805 /* XXX */ 1806 for (p = head; p != NULL && p->next != sed; p = p->next) 1807 ; 1808 KASSERT(p != NULL); 1809 1810 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1811 sizeof(sed->ed.ed_nexted), 1812 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1813 p->next = sed->next; 1814 p->ed.ed_nexted = sed->ed.ed_nexted; 1815 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1816 sizeof(p->ed.ed_nexted), 1817 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1818 } 1819 1820 /* 1821 * When a transfer is completed the TD is added to the done queue by 1822 * the host controller. This queue is the processed by software. 1823 * Unfortunately the queue contains the physical address of the TD 1824 * and we have no simple way to translate this back to a kernel address. 1825 * To make the translation possible (and fast) we use a hash table of 1826 * TDs currently in the schedule. The physical address is used as the 1827 * hash value. 1828 */ 1829 1830 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1831 /* Called with USB lock held. */ 1832 void 1833 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1834 { 1835 int h = HASH(std->physaddr); 1836 1837 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1838 1839 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1840 } 1841 1842 /* Called with USB lock held. */ 1843 void 1844 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1845 { 1846 1847 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1848 1849 LIST_REMOVE(std, hnext); 1850 } 1851 1852 ohci_soft_td_t * 1853 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1854 { 1855 int h = HASH(a); 1856 ohci_soft_td_t *std; 1857 1858 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1859 std != NULL; 1860 std = LIST_NEXT(std, hnext)) 1861 if (std->physaddr == a) 1862 return std; 1863 return NULL; 1864 } 1865 1866 /* Called with USB lock held. */ 1867 void 1868 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1869 { 1870 int h = HASH(sitd->physaddr); 1871 1872 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1873 1874 KASSERT(mutex_owned(&sc->sc_lock)); 1875 1876 DPRINTFN(10, "sitd=%p physaddr=0x%08lx", sitd, (u_long)sitd->physaddr, 1877 0, 0); 1878 1879 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1880 } 1881 1882 /* Called with USB lock held. */ 1883 void 1884 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1885 { 1886 1887 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1888 1889 KASSERT(mutex_owned(&sc->sc_lock)); 1890 1891 DPRINTFN(10, "sitd=%p physaddr=0x%08lx", sitd, (u_long)sitd->physaddr, 1892 0, 0); 1893 1894 LIST_REMOVE(sitd, hnext); 1895 } 1896 1897 ohci_soft_itd_t * 1898 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1899 { 1900 int h = HASH(a); 1901 ohci_soft_itd_t *sitd; 1902 1903 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1904 sitd != NULL; 1905 sitd = LIST_NEXT(sitd, hnext)) 1906 if (sitd->physaddr == a) 1907 return sitd; 1908 return NULL; 1909 } 1910 1911 void 1912 ohci_timeout(void *addr) 1913 { 1914 struct usbd_xfer *xfer = addr; 1915 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1916 bool timeout = false; 1917 1918 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1919 DPRINTF("xfer=%p", xfer, 0, 0, 0); 1920 1921 mutex_enter(&sc->sc_lock); 1922 if (sc->sc_dying) { 1923 ohci_abort_xfer(xfer, USBD_TIMEOUT); 1924 mutex_exit(&sc->sc_lock); 1925 return; 1926 } 1927 1928 if (xfer->ux_status != USBD_CANCELLED) { 1929 xfer->ux_status = USBD_TIMEOUT; 1930 timeout = true; 1931 } 1932 mutex_exit(&sc->sc_lock); 1933 1934 if (timeout) { 1935 /* Execute the abort in a process context. */ 1936 usb_init_task(&xfer->ux_aborttask, ohci_timeout_task, addr, 1937 USB_TASKQ_MPSAFE); 1938 usb_add_task(xfer->ux_pipe->up_dev, &xfer->ux_aborttask, 1939 USB_TASKQ_HC); 1940 } 1941 } 1942 1943 void 1944 ohci_timeout_task(void *addr) 1945 { 1946 struct usbd_xfer *xfer = addr; 1947 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1948 1949 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1950 1951 DPRINTF("xfer=%p", xfer, 0, 0, 0); 1952 1953 mutex_enter(&sc->sc_lock); 1954 ohci_abort_xfer(xfer, USBD_TIMEOUT); 1955 mutex_exit(&sc->sc_lock); 1956 } 1957 1958 #ifdef OHCI_DEBUG 1959 void 1960 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 1961 { 1962 for (; std; std = std->nexttd) { 1963 ohci_dump_td(sc, std); 1964 KASSERTMSG(std->nexttd == NULL || std != std->nexttd, 1965 "std %p next %p", std, std->nexttd); 1966 } 1967 } 1968 1969 void 1970 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1971 { 1972 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1973 1974 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1975 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1976 1977 uint32_t flags = O32TOH(std->td.td_flags); 1978 DPRINTF("TD(%p) at 0x%08lx:", std, (u_long)std->physaddr, 0, 0); 1979 DPRINTF(" round=%d DP=%x DI=%x T=%x", 1980 !!(flags & OHCI_TD_R), 1981 __SHIFTOUT(flags, OHCI_TD_DP_MASK), 1982 OHCI_TD_GET_DI(flags), 1983 __SHIFTOUT(flags, OHCI_TD_TOGGLE_MASK)); 1984 DPRINTF(" EC=%d CC=%d", OHCI_TD_GET_EC(flags), OHCI_TD_GET_CC(flags), 1985 0, 0); 1986 DPRINTF(" td_cbp=0x%08lx td_nexttd=0x%08lx td_be=0x%08lx", 1987 (u_long)O32TOH(std->td.td_cbp), 1988 (u_long)O32TOH(std->td.td_nexttd), 1989 (u_long)O32TOH(std->td.td_be), 0); 1990 } 1991 1992 void 1993 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1994 { 1995 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1996 1997 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1998 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1999 2000 uint32_t flags = O32TOH(sitd->itd.itd_flags); 2001 DPRINTF("ITD(%p) at 0x%08lx", sitd, (u_long)sitd->physaddr, 0, 0); 2002 DPRINTF(" sf=%d di=%d fc=%d cc=%d", 2003 OHCI_ITD_GET_SF(flags), OHCI_ITD_GET_DI(flags), 2004 OHCI_ITD_GET_FC(flags), OHCI_ITD_GET_CC(flags)); 2005 DPRINTF(" bp0=0x%08x next=0x%08x be=0x%08x", 2006 O32TOH(sitd->itd.itd_bp0), 2007 O32TOH(sitd->itd.itd_nextitd), 2008 O32TOH(sitd->itd.itd_be), 0); 2009 CTASSERT(OHCI_ITD_NOFFSET == 8); 2010 DPRINTF(" offs[0] = 0x%04x offs[1] = 0x%04x " 2011 "offs[2] = 0x%04x offs[3] = 0x%04x", 2012 O16TOH(sitd->itd.itd_offset[0]), 2013 O16TOH(sitd->itd.itd_offset[1]), 2014 O16TOH(sitd->itd.itd_offset[2]), 2015 O16TOH(sitd->itd.itd_offset[3])); 2016 DPRINTF(" offs[4] = 0x%04x offs[5] = 0x%04x " 2017 "offs[6] = 0x%04x offs[7] = 0x%04x", 2018 O16TOH(sitd->itd.itd_offset[4]), 2019 O16TOH(sitd->itd.itd_offset[5]), 2020 O16TOH(sitd->itd.itd_offset[6]), 2021 O16TOH(sitd->itd.itd_offset[7])); 2022 } 2023 2024 void 2025 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2026 { 2027 for (; sitd; sitd = sitd->nextitd) 2028 ohci_dump_itd(sc, sitd); 2029 } 2030 2031 void 2032 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2033 { 2034 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2035 2036 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2037 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2038 2039 uint32_t flags = O32TOH(sed->ed.ed_flags); 2040 DPRINTF("ED(%p) at 0x%08lx:", sed, sed->physaddr, 0, 0); 2041 DPRINTF(" addr=%d endpt=%d maxp=%d", 2042 OHCI_ED_GET_FA(flags), 2043 OHCI_ED_GET_EN(flags), 2044 OHCI_ED_GET_MAXP(flags), 2045 0); 2046 DPRINTF(" dir=%d speed=%d skip=%d iso=%d", 2047 __SHIFTOUT(flags, OHCI_ED_DIR_MASK), 2048 !!(flags & OHCI_ED_SPEED), 2049 !!(flags & OHCI_ED_SKIP), 2050 !!(flags & OHCI_ED_FORMAT_ISO)); 2051 DPRINTF(" tailp=0x%08lx", (u_long)O32TOH(sed->ed.ed_tailp), 2052 0, 0, 0); 2053 DPRINTF(" headp=0x%08lx nexted=0x%08lx halted=%d carry=%d", 2054 O32TOH(sed->ed.ed_headp), O32TOH(sed->ed.ed_nexted), 2055 !!(O32TOH(sed->ed.ed_headp) & OHCI_HALTED), 2056 !!(O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 2057 } 2058 #endif 2059 2060 usbd_status 2061 ohci_open(struct usbd_pipe *pipe) 2062 { 2063 struct usbd_device *dev = pipe->up_dev; 2064 struct usbd_bus *bus = dev->ud_bus; 2065 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2066 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 2067 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2068 uint8_t addr = dev->ud_addr; 2069 uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2070 ohci_soft_ed_t *sed; 2071 ohci_soft_td_t *std; 2072 ohci_soft_itd_t *sitd; 2073 ohci_physaddr_t tdphys; 2074 uint32_t fmt; 2075 usbd_status err = USBD_NOMEM; 2076 int ival; 2077 2078 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2079 DPRINTFN(1, "pipe=%p, addr=%d, endpt=%d (%d)", pipe, addr, 2080 ed->bEndpointAddress, bus->ub_rhaddr); 2081 2082 if (sc->sc_dying) { 2083 return USBD_IOERROR; 2084 } 2085 2086 std = NULL; 2087 sed = NULL; 2088 2089 if (addr == bus->ub_rhaddr) { 2090 switch (ed->bEndpointAddress) { 2091 case USB_CONTROL_ENDPOINT: 2092 pipe->up_methods = &roothub_ctrl_methods; 2093 break; 2094 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 2095 pipe->up_methods = &ohci_root_intr_methods; 2096 break; 2097 default: 2098 err = USBD_INVAL; 2099 goto bad; 2100 } 2101 } else { 2102 sed = ohci_alloc_sed(sc); 2103 if (sed == NULL) 2104 goto bad; 2105 opipe->sed = sed; 2106 if (xfertype == UE_ISOCHRONOUS) { 2107 sitd = ohci_alloc_sitd(sc); 2108 if (sitd == NULL) 2109 goto bad; 2110 2111 opipe->tail.itd = sitd; 2112 sitd->held = &opipe->tail.itd; 2113 tdphys = sitd->physaddr; 2114 fmt = OHCI_ED_FORMAT_ISO; 2115 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2116 fmt |= OHCI_ED_DIR_IN; 2117 else 2118 fmt |= OHCI_ED_DIR_OUT; 2119 } else { 2120 std = ohci_alloc_std(sc); 2121 if (std == NULL) 2122 goto bad; 2123 2124 opipe->tail.td = std; 2125 std->held = &opipe->tail.td; 2126 tdphys = std->physaddr; 2127 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2128 } 2129 sed->ed.ed_flags = HTOO32( 2130 OHCI_ED_SET_FA(addr) | 2131 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2132 (dev->ud_speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2133 fmt | 2134 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2135 sed->ed.ed_headp = HTOO32(tdphys | 2136 (pipe->up_endpoint->ue_toggle ? OHCI_TOGGLECARRY : 0)); 2137 sed->ed.ed_tailp = HTOO32(tdphys); 2138 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2139 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2140 2141 switch (xfertype) { 2142 case UE_CONTROL: 2143 pipe->up_methods = &ohci_device_ctrl_methods; 2144 err = usb_allocmem(&sc->sc_bus, 2145 sizeof(usb_device_request_t), 2146 0, &opipe->ctrl.reqdma); 2147 if (err) 2148 goto bad; 2149 mutex_enter(&sc->sc_lock); 2150 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2151 mutex_exit(&sc->sc_lock); 2152 break; 2153 case UE_INTERRUPT: 2154 pipe->up_methods = &ohci_device_intr_methods; 2155 ival = pipe->up_interval; 2156 if (ival == USBD_DEFAULT_INTERVAL) 2157 ival = ed->bInterval; 2158 err = ohci_device_setintr(sc, opipe, ival); 2159 if (err) 2160 goto bad; 2161 break; 2162 case UE_ISOCHRONOUS: 2163 pipe->up_serialise = false; 2164 pipe->up_methods = &ohci_device_isoc_methods; 2165 return ohci_setup_isoc(pipe); 2166 case UE_BULK: 2167 pipe->up_methods = &ohci_device_bulk_methods; 2168 mutex_enter(&sc->sc_lock); 2169 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2170 mutex_exit(&sc->sc_lock); 2171 break; 2172 } 2173 } 2174 2175 return USBD_NORMAL_COMPLETION; 2176 2177 bad: 2178 if (std != NULL) { 2179 ohci_free_std(sc, std); 2180 } 2181 if (sed != NULL) 2182 ohci_free_sed(sc, sed); 2183 return err; 2184 2185 } 2186 2187 /* 2188 * Close a reqular pipe. 2189 * Assumes that there are no pending transactions. 2190 */ 2191 void 2192 ohci_close_pipe(struct usbd_pipe *pipe, ohci_soft_ed_t *head) 2193 { 2194 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2195 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2196 ohci_soft_ed_t *sed = opipe->sed; 2197 2198 KASSERT(mutex_owned(&sc->sc_lock)); 2199 2200 #ifdef DIAGNOSTIC 2201 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2202 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2203 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2204 ohci_soft_td_t *std; 2205 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2206 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2207 "tl=0x%x pipe=%p, std=%p\n", sed, 2208 (int)O32TOH(sed->ed.ed_headp), 2209 (int)O32TOH(sed->ed.ed_tailp), 2210 pipe, std); 2211 #ifdef OHCI_DEBUG 2212 usbd_dump_pipe(&opipe->pipe); 2213 ohci_dump_ed(sc, sed); 2214 if (std) 2215 ohci_dump_td(sc, std); 2216 #endif 2217 usb_delay_ms(&sc->sc_bus, 2); 2218 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2219 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2220 printf("ohci_close_pipe: pipe still not empty\n"); 2221 } 2222 #endif 2223 ohci_rem_ed(sc, sed, head); 2224 /* Make sure the host controller is not touching this ED */ 2225 usb_delay_ms(&sc->sc_bus, 1); 2226 pipe->up_endpoint->ue_toggle = 2227 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2228 ohci_free_sed_locked(sc, opipe->sed); 2229 } 2230 2231 /* 2232 * Cancel or timeour a device request. We have two cases to deal with 2233 * 2234 * 1) A driver wants to stop scheduled or inflight transfers 2235 * 2) A transfer has timed out 2236 * 2237 * It's impossible to guarantee that the requested transfer will not 2238 * have (partially) happened since the hardware runs concurrently. 2239 * 2240 * Transfer state is protected by the bus lock and we set the transfer status 2241 * as soon as either of the above happens (with bus lock held). 2242 * 2243 * Then we arrange for the hardware to tells us that it is not still 2244 * processing the TDs by setting the sKip bit and requesting a SOF interrupt 2245 * 2246 * Once we see the SOF interrupt we can check the transfer TDs/iTDs to see if 2247 * they've been processed and either 2248 * a) if they're unused recover them for later use, or 2249 * b) if they've been used allocate new TD/iTDs to replace those 2250 * used. The softint handler will free the old ones. 2251 */ 2252 void 2253 ohci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2254 { 2255 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2256 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2257 ohci_soft_ed_t *sed = opipe->sed; 2258 ohci_soft_td_t *p, *n; 2259 ohci_physaddr_t headp; 2260 int hit; 2261 int wake; 2262 2263 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2264 DPRINTF("xfer=%p pipe=%p sed=%p", xfer, opipe,sed, 0); 2265 2266 KASSERT(mutex_owned(&sc->sc_lock)); 2267 ASSERT_SLEEPABLE(); 2268 2269 if (sc->sc_dying) { 2270 /* If we're dying, just do the software part. */ 2271 KASSERT(xfer->ux_status == status); 2272 callout_halt(&xfer->ux_callout, &sc->sc_lock); 2273 usb_transfer_complete(xfer); 2274 return; 2275 } 2276 2277 /* 2278 * If an abort is already in progress then just wait for it to 2279 * complete and return. 2280 */ 2281 if (xfer->ux_hcflags & UXFER_ABORTING) { 2282 DPRINTFN(2, "already aborting", 0, 0, 0, 0); 2283 #ifdef DIAGNOSTIC 2284 if (status == USBD_TIMEOUT) 2285 printf("%s: TIMEOUT while aborting\n", __func__); 2286 #endif 2287 /* Override the status which might be USBD_TIMEOUT. */ 2288 xfer->ux_status = status; 2289 DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0); 2290 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2291 while (xfer->ux_hcflags & UXFER_ABORTING) 2292 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2293 goto done; 2294 } 2295 xfer->ux_hcflags |= UXFER_ABORTING; 2296 2297 /* 2298 * Step 1: When cancelling a transfer make sure the timeout handler 2299 * didn't run or ran to the end and saw the USBD_CANCELLED status. 2300 * Otherwise we must have got here via a timeout. 2301 * 2302 * If we timed out then 2303 */ 2304 if (status == USBD_CANCELLED) { 2305 xfer->ux_status = status; 2306 callout_halt(&xfer->ux_callout, &sc->sc_lock); 2307 } else { 2308 KASSERT(xfer->ux_status == USBD_TIMEOUT); 2309 } 2310 2311 /* 2312 * Step 2: Unless the endpoint is already halted, we set the endpoint 2313 * descriptor sKip bit and wait for hardware to complete processing. 2314 * 2315 * This includes ensuring that any TDs of the transfer that got onto 2316 * the done list are also removed. We ensure this by waiting for 2317 * both a WDH and SOF interrupt. 2318 */ 2319 DPRINTFN(1, "stop ed=%p", sed, 0, 0, 0); 2320 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2321 sizeof(sed->ed.ed_flags), 2322 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2323 if (!(sed->ed.ed_flags & OHCI_HALTED)) { 2324 /* force hardware skip */ 2325 DPRINTFN(1, "pausing ed=%p", sed, 0, 0, 0); 2326 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2327 usb_syncmem(&sed->dma, 2328 sed->offs + offsetof(ohci_ed_t, ed_flags), 2329 sizeof(sed->ed.ed_flags), 2330 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2331 2332 DPRINTFN(10, "WDH %p xfer %p", sc, xfer, 0, 0); 2333 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2334 ox->ox_abintrs = OHCI_SF; 2335 TAILQ_INSERT_TAIL(&sc->sc_abortingxfers, ox, ox_abnext); 2336 2337 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_SF); 2338 sc->sc_eintrs |= OHCI_SF; 2339 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_SF); 2340 /* 2341 * Step 2: Wait until we know hardware has finished any possible 2342 * use of the xfer. 2343 */ 2344 while (ox->ox_abintrs != 0) { 2345 DPRINTFN(10, "WDH %p xfer %p intrs %#x", sc, xfer, 2346 ox->ox_abintrs, 0); 2347 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2348 } 2349 } else { 2350 DPRINTFN(1, "halted ed=%p", sed, 0, 0, 0); 2351 } 2352 2353 /* 2354 * Step 3: Remove any vestiges of the xfer from the hardware. 2355 * The complication here is that the hardware may have executed 2356 * beyond the xfer we're trying to abort. So as we're scanning 2357 * the TDs of this xfer we check if the hardware points to 2358 * any of them. 2359 */ 2360 p = xfer->ux_hcpriv; 2361 KASSERT(p); 2362 2363 #ifdef OHCI_DEBUG 2364 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2365 2366 if (ohcidebug >= 2) { 2367 DPRINTF("sed:", 0, 0, 0, 0); 2368 ohci_dump_ed(sc, sed); 2369 ohci_dump_tds(sc, p); 2370 } 2371 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2372 #endif 2373 2374 #define OHCI_CC_ACCESSED_P(x) (((x) & OHCI_CC_NOT_ACCESSED_MASK) != OHCI_CC_NOT_ACCESSED) 2375 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2376 hit = 0; 2377 for (; p->xfer == xfer; p = n) { 2378 hit |= headp == p->physaddr; 2379 n = p->nexttd; 2380 2381 int cc = OHCI_TD_GET_CC(O32TOH(p->td.td_flags)); 2382 if (!OHCI_CC_ACCESSED_P(cc)) { 2383 ohci_hash_rem_td(sc, p); 2384 continue; 2385 } 2386 DPRINTFN(10, "std=%p has been touched by HC", p, 0, 0, 0); 2387 2388 mutex_exit(&sc->sc_lock); 2389 ohci_soft_td_t *std = ohci_alloc_std(sc); 2390 if (std == NULL) { 2391 /* XXX What to do??? */ 2392 panic("hmm"); 2393 } 2394 mutex_enter(&sc->sc_lock); 2395 2396 DPRINTFN(10, "new std=%p now held at %p", std, p->held, 0, 0); 2397 *(p->held) = std; 2398 std->held = p->held; 2399 std->xfer = xfer; 2400 p->held = NULL; 2401 } 2402 /* Zap headp register if hardware pointed inside the xfer. */ 2403 if (hit) { 2404 DPRINTFN(1, "set hd=0x%08x, tl=0x%08x", (int)p->physaddr, 2405 (int)O32TOH(sed->ed.ed_tailp), 0, 0); 2406 sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */ 2407 usb_syncmem(&sed->dma, 2408 sed->offs + offsetof(ohci_ed_t, ed_headp), 2409 sizeof(sed->ed.ed_headp), 2410 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2411 } else { 2412 DPRINTFN(1, "no hit", 0, 0, 0, 0); 2413 } 2414 2415 /* 2416 * Step 4: Turn on hardware again. 2417 */ 2418 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2419 sizeof(sed->ed.ed_flags), 2420 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2421 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2422 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2423 sizeof(sed->ed.ed_flags), 2424 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2425 2426 /* 2427 * Step 5: Execute callback. 2428 */ 2429 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2430 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2431 usb_transfer_complete(xfer); 2432 if (wake) 2433 cv_broadcast(&xfer->ux_hccv); 2434 2435 done: 2436 KASSERT(mutex_owned(&sc->sc_lock)); 2437 } 2438 2439 /* 2440 * Data structures and routines to emulate the root hub. 2441 */ 2442 Static int 2443 ohci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2444 void *buf, int buflen) 2445 { 2446 ohci_softc_t *sc = OHCI_BUS2SC(bus); 2447 usb_port_status_t ps; 2448 uint16_t len, value, index; 2449 int l, totlen = 0; 2450 int port, i; 2451 uint32_t v; 2452 2453 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2454 2455 if (sc->sc_dying) 2456 return -1; 2457 2458 DPRINTFN(4, "type=0x%02x request=%02x", req->bmRequestType, 2459 req->bRequest, 0, 0); 2460 2461 len = UGETW(req->wLength); 2462 value = UGETW(req->wValue); 2463 index = UGETW(req->wIndex); 2464 2465 #define C(x,y) ((x) | ((y) << 8)) 2466 switch (C(req->bRequest, req->bmRequestType)) { 2467 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2468 DPRINTFN(8, "wValue=0x%04x", value, 0, 0, 0); 2469 if (len == 0) 2470 break; 2471 switch (value) { 2472 case C(0, UDESC_DEVICE): { 2473 usb_device_descriptor_t devd; 2474 2475 totlen = min(buflen, sizeof(devd)); 2476 memcpy(&devd, buf, totlen); 2477 USETW(devd.idVendor, sc->sc_id_vendor); 2478 memcpy(buf, &devd, totlen); 2479 break; 2480 } 2481 case C(1, UDESC_STRING): 2482 #define sd ((usb_string_descriptor_t *)buf) 2483 /* Vendor */ 2484 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2485 break; 2486 case C(2, UDESC_STRING): 2487 /* Product */ 2488 totlen = usb_makestrdesc(sd, len, "OHCI root hub"); 2489 break; 2490 #undef sd 2491 default: 2492 /* default from usbroothub */ 2493 return buflen; 2494 } 2495 break; 2496 2497 /* Hub requests */ 2498 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2499 break; 2500 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2501 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 2502 index, value, 0, 0); 2503 if (index < 1 || index > sc->sc_noport) { 2504 return -1; 2505 } 2506 port = OHCI_RH_PORT_STATUS(index); 2507 switch(value) { 2508 case UHF_PORT_ENABLE: 2509 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2510 break; 2511 case UHF_PORT_SUSPEND: 2512 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2513 break; 2514 case UHF_PORT_POWER: 2515 /* Yes, writing to the LOW_SPEED bit clears power. */ 2516 OWRITE4(sc, port, UPS_LOW_SPEED); 2517 break; 2518 case UHF_C_PORT_CONNECTION: 2519 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2520 break; 2521 case UHF_C_PORT_ENABLE: 2522 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2523 break; 2524 case UHF_C_PORT_SUSPEND: 2525 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2526 break; 2527 case UHF_C_PORT_OVER_CURRENT: 2528 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2529 break; 2530 case UHF_C_PORT_RESET: 2531 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2532 break; 2533 default: 2534 return -1; 2535 } 2536 switch(value) { 2537 case UHF_C_PORT_CONNECTION: 2538 case UHF_C_PORT_ENABLE: 2539 case UHF_C_PORT_SUSPEND: 2540 case UHF_C_PORT_OVER_CURRENT: 2541 case UHF_C_PORT_RESET: 2542 /* Enable RHSC interrupt if condition is cleared. */ 2543 if ((OREAD4(sc, port) >> 16) == 0) 2544 ohci_rhsc_enable(sc); 2545 break; 2546 default: 2547 break; 2548 } 2549 break; 2550 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2551 if (len == 0) 2552 break; 2553 if ((value & 0xff) != 0) { 2554 return -1; 2555 } 2556 usb_hub_descriptor_t hubd; 2557 2558 totlen = min(buflen, sizeof(hubd)); 2559 memcpy(&hubd, buf, totlen); 2560 2561 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2562 hubd.bNbrPorts = sc->sc_noport; 2563 USETW(hubd.wHubCharacteristics, 2564 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2565 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2566 /* XXX overcurrent */ 2567 ); 2568 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2569 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2570 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2571 hubd.DeviceRemovable[i++] = (uint8_t)v; 2572 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2573 totlen = min(totlen, hubd.bDescLength); 2574 memcpy(buf, &hubd, totlen); 2575 break; 2576 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2577 if (len != 4) { 2578 return -1; 2579 } 2580 memset(buf, 0, len); /* ? XXX */ 2581 totlen = len; 2582 break; 2583 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2584 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 2585 if (index < 1 || index > sc->sc_noport) { 2586 return -1; 2587 } 2588 if (len != 4) { 2589 return -1; 2590 } 2591 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2592 DPRINTFN(8, "port status=0x%04x", v, 0, 0, 0); 2593 USETW(ps.wPortStatus, v); 2594 USETW(ps.wPortChange, v >> 16); 2595 totlen = min(len, sizeof(ps)); 2596 memcpy(buf, &ps, totlen); 2597 break; 2598 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2599 return -1; 2600 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2601 break; 2602 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2603 if (index < 1 || index > sc->sc_noport) { 2604 return -1; 2605 } 2606 port = OHCI_RH_PORT_STATUS(index); 2607 switch(value) { 2608 case UHF_PORT_ENABLE: 2609 OWRITE4(sc, port, UPS_PORT_ENABLED); 2610 break; 2611 case UHF_PORT_SUSPEND: 2612 OWRITE4(sc, port, UPS_SUSPEND); 2613 break; 2614 case UHF_PORT_RESET: 2615 DPRINTFN(5, "reset port %d", index, 0, 0, 0); 2616 OWRITE4(sc, port, UPS_RESET); 2617 for (i = 0; i < 5; i++) { 2618 usb_delay_ms(&sc->sc_bus, 2619 USB_PORT_ROOT_RESET_DELAY); 2620 if (sc->sc_dying) { 2621 return -1; 2622 } 2623 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2624 break; 2625 } 2626 DPRINTFN(8, "port %d reset, status = 0x%04x", index, 2627 OREAD4(sc, port), 0, 0); 2628 break; 2629 case UHF_PORT_POWER: 2630 DPRINTFN(2, "set port power %d", index, 0, 0, 0); 2631 OWRITE4(sc, port, UPS_PORT_POWER); 2632 break; 2633 default: 2634 return -1; 2635 } 2636 break; 2637 default: 2638 /* default from usbroothub */ 2639 return buflen; 2640 } 2641 2642 return totlen; 2643 } 2644 2645 Static usbd_status 2646 ohci_root_intr_transfer(struct usbd_xfer *xfer) 2647 { 2648 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2649 usbd_status err; 2650 2651 /* Insert last in queue. */ 2652 mutex_enter(&sc->sc_lock); 2653 err = usb_insert_transfer(xfer); 2654 mutex_exit(&sc->sc_lock); 2655 if (err) 2656 return err; 2657 2658 /* Pipe isn't running, start first */ 2659 return ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2660 } 2661 2662 Static usbd_status 2663 ohci_root_intr_start(struct usbd_xfer *xfer) 2664 { 2665 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2666 2667 if (sc->sc_dying) 2668 return USBD_IOERROR; 2669 2670 mutex_enter(&sc->sc_lock); 2671 KASSERT(sc->sc_intrxfer == NULL); 2672 sc->sc_intrxfer = xfer; 2673 mutex_exit(&sc->sc_lock); 2674 2675 return USBD_IN_PROGRESS; 2676 } 2677 2678 /* Abort a root interrupt request. */ 2679 Static void 2680 ohci_root_intr_abort(struct usbd_xfer *xfer) 2681 { 2682 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2683 2684 KASSERT(mutex_owned(&sc->sc_lock)); 2685 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2686 2687 sc->sc_intrxfer = NULL; 2688 2689 xfer->ux_status = USBD_CANCELLED; 2690 usb_transfer_complete(xfer); 2691 } 2692 2693 /* Close the root pipe. */ 2694 Static void 2695 ohci_root_intr_close(struct usbd_pipe *pipe) 2696 { 2697 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2698 2699 KASSERT(mutex_owned(&sc->sc_lock)); 2700 2701 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2702 2703 sc->sc_intrxfer = NULL; 2704 } 2705 2706 /************************/ 2707 2708 int 2709 ohci_device_ctrl_init(struct usbd_xfer *xfer) 2710 { 2711 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2712 usb_device_request_t *req = &xfer->ux_request; 2713 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2714 ohci_soft_td_t *stat, *setup; 2715 int isread = req->bmRequestType & UT_READ; 2716 int len = xfer->ux_bufsize; 2717 int err = ENOMEM; 2718 2719 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2720 2721 setup = ohci_alloc_std(sc); 2722 if (setup == NULL) { 2723 goto bad1; 2724 } 2725 stat = ohci_alloc_std(sc); 2726 if (stat == NULL) { 2727 goto bad2; 2728 } 2729 2730 ox->ox_setup = setup; 2731 ox->ox_stat = stat; 2732 ox->ox_nstd = 0; 2733 setup->held = &ox->ox_setup; 2734 stat->held = &ox->ox_stat; 2735 2736 DPRINTFN(10, "xfer=%p setup=%p held at %p", ox, setup, setup->held, 0); 2737 DPRINTFN(10, "xfer=%p stat= %p held at %p", ox, stat, stat->held, 0); 2738 2739 /* Set up data transaction */ 2740 if (len != 0) { 2741 err = ohci_alloc_std_chain(sc, xfer, len, isread); 2742 if (err) { 2743 goto bad3; 2744 } 2745 } 2746 return 0; 2747 2748 bad3: 2749 ohci_free_std(sc, stat); 2750 bad2: 2751 ohci_free_std(sc, setup); 2752 bad1: 2753 return err; 2754 } 2755 2756 void 2757 ohci_device_ctrl_fini(struct usbd_xfer *xfer) 2758 { 2759 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2760 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2761 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2762 2763 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2764 DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0); 2765 2766 mutex_enter(&sc->sc_lock); 2767 if (ox->ox_setup != opipe->tail.td) { 2768 ohci_free_std_locked(sc, ox->ox_setup); 2769 } 2770 for (size_t i = 0; i < ox->ox_nstd; i++) { 2771 ohci_soft_td_t *std = ox->ox_stds[i]; 2772 if (std == NULL) 2773 break; 2774 ohci_free_std_locked(sc, std); 2775 } 2776 ohci_free_std_locked(sc, ox->ox_stat); 2777 mutex_exit(&sc->sc_lock); 2778 2779 if (ox->ox_nstd) { 2780 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 2781 kmem_free(ox->ox_stds, sz); 2782 } 2783 } 2784 2785 Static usbd_status 2786 ohci_device_ctrl_transfer(struct usbd_xfer *xfer) 2787 { 2788 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2789 usbd_status err; 2790 2791 /* Insert last in queue. */ 2792 mutex_enter(&sc->sc_lock); 2793 err = usb_insert_transfer(xfer); 2794 mutex_exit(&sc->sc_lock); 2795 if (err) 2796 return err; 2797 2798 /* Pipe isn't running, start first */ 2799 return ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2800 } 2801 2802 Static usbd_status 2803 ohci_device_ctrl_start(struct usbd_xfer *xfer) 2804 { 2805 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2806 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2807 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2808 usb_device_request_t *req = &xfer->ux_request; 2809 struct usbd_device *dev __diagused = opipe->pipe.up_dev; 2810 ohci_soft_td_t *setup, *stat, *next, *tail; 2811 ohci_soft_ed_t *sed; 2812 int isread; 2813 int len; 2814 2815 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2816 2817 if (sc->sc_dying) 2818 return USBD_IOERROR; 2819 2820 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2821 2822 isread = req->bmRequestType & UT_READ; 2823 len = UGETW(req->wLength); 2824 2825 DPRINTF("xfer=%p len=%d, addr=%d, endpt=%d", xfer, len, dev->ud_addr, 2826 opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress); 2827 DPRINTF("type=0x%02x, request=0x%02x, wValue=0x%04x, wIndex=0x%04x", 2828 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2829 UGETW(req->wIndex)); 2830 2831 /* Need to take lock here for pipe->tail.td */ 2832 mutex_enter(&sc->sc_lock); 2833 2834 /* 2835 * Use the pipe "tail" TD as our first and loan our first TD to the 2836 * next transfer 2837 */ 2838 setup = opipe->tail.td; 2839 opipe->tail.td = ox->ox_setup; 2840 ox->ox_setup = setup; 2841 setup->held = &ox->ox_setup; 2842 2843 DPRINTFN(10, "xfer=%p new setup=%p held at %p", ox, setup, setup->held, 0); 2844 2845 stat = ox->ox_stat; 2846 2847 /* point at sentinel */ 2848 tail = opipe->tail.td; 2849 tail->held = &opipe->tail.td; 2850 sed = opipe->sed; 2851 2852 DPRINTFN(10, "xfer=%p new tail=%p held at %p", ox, tail, tail->held, 0); 2853 2854 KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->ud_addr, 2855 "address ED %d pipe %d\n", 2856 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->ud_addr); 2857 KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) == 2858 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 2859 "MPL ED %d pipe %d\n", 2860 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), 2861 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 2862 2863 /* next will point to data if len != 0 */ 2864 next = stat; 2865 2866 /* Set up data transaction */ 2867 if (len != 0) { 2868 ohci_soft_td_t *std; 2869 ohci_soft_td_t *end; 2870 2871 next = ox->ox_stds[0]; 2872 ohci_reset_std_chain(sc, xfer, len, isread, next, &end); 2873 2874 end->td.td_nexttd = HTOO32(stat->physaddr); 2875 end->nexttd = stat; 2876 2877 usb_syncmem(&end->dma, 2878 end->offs + offsetof(ohci_td_t, td_nexttd), 2879 sizeof(end->td.td_nexttd), 2880 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2881 2882 usb_syncmem(&xfer->ux_dmabuf, 0, len, 2883 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2884 std = ox->ox_stds[0]; 2885 /* Start toggle at 1 and then use the carried toggle. */ 2886 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 2887 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 2888 usb_syncmem(&std->dma, 2889 std->offs + offsetof(ohci_td_t, td_flags), 2890 sizeof(std->td.td_flags), 2891 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2892 } 2893 2894 DPRINTFN(8, "setup %p data %p stat %p tail %p", setup, 2895 (len != 0 ? ox->ox_stds[0] : NULL), stat, tail); 2896 KASSERT(opipe->tail.td == tail); 2897 2898 memcpy(KERNADDR(&opipe->ctrl.reqdma, 0), req, sizeof(*req)); 2899 usb_syncmem(&opipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2900 2901 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 2902 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 2903 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->ctrl.reqdma, 0)); 2904 setup->td.td_nexttd = HTOO32(next->physaddr); 2905 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof(*req) - 1); 2906 setup->nexttd = next; 2907 setup->len = 0; 2908 setup->xfer = xfer; 2909 setup->flags = 0; 2910 ohci_hash_add_td(sc, setup); 2911 2912 xfer->ux_hcpriv = setup; 2913 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2914 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2915 2916 stat->td.td_flags = HTOO32( 2917 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 2918 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 2919 stat->td.td_cbp = 0; 2920 stat->td.td_nexttd = HTOO32(tail->physaddr); 2921 stat->td.td_be = 0; 2922 stat->nexttd = tail; 2923 stat->flags = OHCI_CALL_DONE; 2924 stat->len = 0; 2925 stat->xfer = xfer; 2926 ohci_hash_add_td(sc, stat); 2927 2928 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2929 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2930 2931 memset(&tail->td, 0, sizeof(tail->td)); 2932 tail->nexttd = NULL; 2933 tail->xfer = NULL; 2934 2935 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 2936 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2937 2938 #ifdef OHCI_DEBUG 2939 USBHIST_LOGN(ohcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2940 if (ohcidebug >= 5) { 2941 ohci_dump_ed(sc, sed); 2942 ohci_dump_tds(sc, setup); 2943 } 2944 USBHIST_LOGN(ohcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2945 #endif 2946 2947 /* Insert ED in schedule */ 2948 sed->ed.ed_tailp = HTOO32(tail->physaddr); 2949 usb_syncmem(&sed->dma, 2950 sed->offs + offsetof(ohci_ed_t, ed_tailp), 2951 sizeof(sed->ed.ed_tailp), 2952 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2953 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2954 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2955 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2956 ohci_timeout, xfer); 2957 } 2958 2959 DPRINTF("done", 0, 0, 0, 0); 2960 2961 mutex_exit(&sc->sc_lock); 2962 2963 return USBD_IN_PROGRESS; 2964 } 2965 2966 /* Abort a device control request. */ 2967 Static void 2968 ohci_device_ctrl_abort(struct usbd_xfer *xfer) 2969 { 2970 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 2971 2972 KASSERT(mutex_owned(&sc->sc_lock)); 2973 2974 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2975 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2976 ohci_abort_xfer(xfer, USBD_CANCELLED); 2977 } 2978 2979 /* Close a device control pipe. */ 2980 Static void 2981 ohci_device_ctrl_close(struct usbd_pipe *pipe) 2982 { 2983 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2984 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2985 2986 KASSERT(mutex_owned(&sc->sc_lock)); 2987 2988 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2989 DPRINTF("pipe=%p", pipe, 0, 0, 0); 2990 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2991 ohci_free_std_locked(sc, opipe->tail.td); 2992 } 2993 2994 /************************/ 2995 2996 Static void 2997 ohci_device_clear_toggle(struct usbd_pipe *pipe) 2998 { 2999 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3000 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3001 3002 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 3003 } 3004 3005 Static void 3006 ohci_noop(struct usbd_pipe *pipe) 3007 { 3008 } 3009 3010 Static int 3011 ohci_device_bulk_init(struct usbd_xfer *xfer) 3012 { 3013 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3014 int len = xfer->ux_bufsize; 3015 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;; 3016 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3017 int err; 3018 3019 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3020 3021 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3022 3023 DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread, 3024 xfer->ux_flags); 3025 DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0); 3026 3027 /* Allocate a chain of new TDs (including a new tail). */ 3028 err = ohci_alloc_std_chain(sc, xfer, len, isread); 3029 if (err) 3030 return err; 3031 3032 return 0; 3033 } 3034 3035 Static void 3036 ohci_device_bulk_fini(struct usbd_xfer *xfer) 3037 { 3038 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3039 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3040 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3041 3042 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3043 DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0); 3044 3045 mutex_enter(&sc->sc_lock); 3046 for (size_t i = 0; i < ox->ox_nstd; i++) { 3047 ohci_soft_td_t *std = ox->ox_stds[i]; 3048 if (std == NULL) 3049 break; 3050 if (std != opipe->tail.td) 3051 ohci_free_std_locked(sc, std); 3052 } 3053 mutex_exit(&sc->sc_lock); 3054 3055 if (ox->ox_nstd) { 3056 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 3057 kmem_free(ox->ox_stds, sz); 3058 } 3059 } 3060 3061 Static usbd_status 3062 ohci_device_bulk_transfer(struct usbd_xfer *xfer) 3063 { 3064 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3065 usbd_status err; 3066 3067 /* Insert last in queue. */ 3068 mutex_enter(&sc->sc_lock); 3069 err = usb_insert_transfer(xfer); 3070 mutex_exit(&sc->sc_lock); 3071 if (err) 3072 return err; 3073 3074 /* Pipe isn't running, start first */ 3075 return ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3076 } 3077 3078 Static usbd_status 3079 ohci_device_bulk_start(struct usbd_xfer *xfer) 3080 { 3081 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3082 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3083 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3084 ohci_soft_td_t *last; 3085 ohci_soft_td_t *data, *tail, *tdp; 3086 ohci_soft_ed_t *sed; 3087 int len, isread, endpt; 3088 3089 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3090 3091 if (sc->sc_dying) 3092 return USBD_IOERROR; 3093 3094 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3095 3096 len = xfer->ux_length; 3097 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3098 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3099 sed = opipe->sed; 3100 3101 DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread, 3102 xfer->ux_flags); 3103 DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0); 3104 3105 mutex_enter(&sc->sc_lock); 3106 3107 /* 3108 * Use the pipe "tail" TD as our first and loan our first TD to the 3109 * next transfer 3110 */ 3111 data = opipe->tail.td; 3112 opipe->tail.td = ox->ox_stds[0]; 3113 ox->ox_stds[0] = data; 3114 data->held = &ox->ox_stds[0]; 3115 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3116 DPRINTFN(10, "xfer=%p new data=%p held at %p", ox, data, data->held, 0); 3117 3118 /* point at sentinel */ 3119 tail = opipe->tail.td; 3120 memset(&tail->td, 0, sizeof(tail->td)); 3121 tail->held = &opipe->tail.td; 3122 tail->nexttd = NULL; 3123 tail->xfer = NULL; 3124 DPRINTFN(10, "xfer=%p new tail=%p held at %p", ox, tail, tail->held, 0); 3125 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3126 BUS_DMASYNC_PREWRITE); 3127 xfer->ux_hcpriv = data; 3128 3129 DPRINTFN(8, "xfer %p data %p tail %p", xfer, ox->ox_stds[0], tail, 0); 3130 KASSERT(opipe->tail.td == tail); 3131 3132 /* We want interrupt at the end of the transfer. */ 3133 last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3134 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3135 last->td.td_nexttd = HTOO32(tail->physaddr); 3136 last->nexttd = tail; 3137 last->flags |= OHCI_CALL_DONE; 3138 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3139 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3140 3141 DPRINTFN(4, "ed_flags=0x%08x td_flags=0x%08x " 3142 "td_cbp=0x%08x td_be=0x%08x", 3143 (int)O32TOH(sed->ed.ed_flags), 3144 (int)O32TOH(data->td.td_flags), 3145 (int)O32TOH(data->td.td_cbp), 3146 (int)O32TOH(data->td.td_be)); 3147 3148 #ifdef OHCI_DEBUG 3149 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3150 if (ohcidebug >= 5) { 3151 ohci_dump_ed(sc, sed); 3152 ohci_dump_tds(sc, data); 3153 } 3154 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3155 #endif 3156 3157 /* Insert ED in schedule */ 3158 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3159 KASSERT(tdp->xfer == xfer); 3160 } 3161 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3162 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3163 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3164 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3165 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3166 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3167 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3168 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3169 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3170 ohci_timeout, xfer); 3171 } 3172 mutex_exit(&sc->sc_lock); 3173 3174 return USBD_IN_PROGRESS; 3175 } 3176 3177 Static void 3178 ohci_device_bulk_abort(struct usbd_xfer *xfer) 3179 { 3180 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3181 3182 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3183 3184 KASSERT(mutex_owned(&sc->sc_lock)); 3185 3186 DPRINTF("xfer=%p", xfer, 0, 0, 0); 3187 ohci_abort_xfer(xfer, USBD_CANCELLED); 3188 } 3189 3190 /* 3191 * Close a device bulk pipe. 3192 */ 3193 Static void 3194 ohci_device_bulk_close(struct usbd_pipe *pipe) 3195 { 3196 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3197 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3198 3199 KASSERT(mutex_owned(&sc->sc_lock)); 3200 3201 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3202 3203 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3204 ohci_close_pipe(pipe, sc->sc_bulk_head); 3205 ohci_free_std_locked(sc, opipe->tail.td); 3206 } 3207 3208 /************************/ 3209 3210 Static int 3211 ohci_device_intr_init(struct usbd_xfer *xfer) 3212 { 3213 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3214 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3215 int len = xfer->ux_bufsize; 3216 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;; 3217 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3218 int err; 3219 3220 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3221 3222 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3223 KASSERT(len != 0); 3224 3225 DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread, 3226 xfer->ux_flags); 3227 DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0); 3228 3229 ox->ox_nstd = 0; 3230 3231 err = ohci_alloc_std_chain(sc, xfer, len, isread); 3232 if (err) { 3233 return err; 3234 } 3235 3236 return 0; 3237 } 3238 3239 Static void 3240 ohci_device_intr_fini(struct usbd_xfer *xfer) 3241 { 3242 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3243 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3244 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3245 3246 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3247 DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0); 3248 3249 mutex_enter(&sc->sc_lock); 3250 for (size_t i = 0; i < ox->ox_nstd; i++) { 3251 ohci_soft_td_t *std = ox->ox_stds[i]; 3252 if (std != NULL) 3253 break; 3254 if (std != opipe->tail.td) 3255 ohci_free_std_locked(sc, std); 3256 } 3257 mutex_exit(&sc->sc_lock); 3258 3259 if (ox->ox_nstd) { 3260 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 3261 kmem_free(ox->ox_stds, sz); 3262 } 3263 } 3264 3265 Static usbd_status 3266 ohci_device_intr_transfer(struct usbd_xfer *xfer) 3267 { 3268 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3269 usbd_status err; 3270 3271 /* Insert last in queue. */ 3272 mutex_enter(&sc->sc_lock); 3273 err = usb_insert_transfer(xfer); 3274 mutex_exit(&sc->sc_lock); 3275 if (err) 3276 return err; 3277 3278 /* Pipe isn't running, start first */ 3279 return ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3280 } 3281 3282 Static usbd_status 3283 ohci_device_intr_start(struct usbd_xfer *xfer) 3284 { 3285 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3286 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3287 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3288 ohci_soft_ed_t *sed = opipe->sed; 3289 ohci_soft_td_t *data, *last, *tail; 3290 int len, isread, endpt; 3291 3292 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3293 3294 if (sc->sc_dying) 3295 return USBD_IOERROR; 3296 3297 DPRINTFN(3, "xfer=%p len=%d flags=%d priv=%p", xfer, xfer->ux_length, 3298 xfer->ux_flags, xfer->ux_priv); 3299 3300 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3301 3302 len = xfer->ux_length; 3303 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3304 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3305 3306 mutex_enter(&sc->sc_lock); 3307 3308 /* 3309 * Use the pipe "tail" TD as our first and loan our first TD to the 3310 * next transfer. 3311 */ 3312 data = opipe->tail.td; 3313 opipe->tail.td = ox->ox_stds[0]; 3314 ox->ox_stds[0] = data; 3315 data->held = &ox->ox_stds[0]; 3316 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3317 DPRINTFN(10, "xfer=%p new data=%p held at %p", ox, data, data->held, 0); 3318 3319 /* point at sentinel */ 3320 tail = opipe->tail.td; 3321 memset(&tail->td, 0, sizeof(tail->td)); 3322 tail->held = &opipe->tail.td; 3323 tail->nexttd = NULL; 3324 tail->xfer = NULL; 3325 DPRINTFN(10, "xfer=%p new tail=%p held at %p", ox, tail, tail->held, 0); 3326 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3327 BUS_DMASYNC_PREWRITE); 3328 xfer->ux_hcpriv = data; 3329 3330 DPRINTFN(8, "data %p tail %p", ox->ox_stds[0], tail, 0, 0); 3331 KASSERT(opipe->tail.td == tail); 3332 3333 /* We want interrupt at the end of the transfer. */ 3334 last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3335 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3336 3337 last->td.td_nexttd = HTOO32(tail->physaddr); 3338 last->nexttd = tail; 3339 last->flags |= OHCI_CALL_DONE; 3340 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3341 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3342 3343 #ifdef OHCI_DEBUG 3344 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3345 if (ohcidebug >= 5) { 3346 ohci_dump_ed(sc, sed); 3347 ohci_dump_tds(sc, data); 3348 } 3349 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3350 #endif 3351 3352 /* Insert ED in schedule */ 3353 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3354 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3355 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3356 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3357 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3358 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3359 3360 mutex_exit(&sc->sc_lock); 3361 3362 return USBD_IN_PROGRESS; 3363 } 3364 3365 /* Abort a device interrupt request. */ 3366 Static void 3367 ohci_device_intr_abort(struct usbd_xfer *xfer) 3368 { 3369 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3370 3371 KASSERT(mutex_owned(&sc->sc_lock)); 3372 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3373 3374 ohci_abort_xfer(xfer, USBD_CANCELLED); 3375 } 3376 3377 /* Close a device interrupt pipe. */ 3378 Static void 3379 ohci_device_intr_close(struct usbd_pipe *pipe) 3380 { 3381 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3382 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3383 int nslots = opipe->intr.nslots; 3384 int pos = opipe->intr.pos; 3385 int j; 3386 ohci_soft_ed_t *p, *sed = opipe->sed; 3387 3388 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3389 3390 KASSERT(mutex_owned(&sc->sc_lock)); 3391 3392 DPRINTFN(1, "pipe=%p nslots=%d pos=%d", pipe, nslots, pos, 0); 3393 usb_syncmem(&sed->dma, sed->offs, 3394 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3395 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3396 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3397 sizeof(sed->ed.ed_flags), 3398 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3399 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3400 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3401 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3402 3403 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3404 continue; 3405 KASSERT(p); 3406 p->next = sed->next; 3407 p->ed.ed_nexted = sed->ed.ed_nexted; 3408 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3409 sizeof(p->ed.ed_nexted), 3410 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3411 3412 for (j = 0; j < nslots; j++) 3413 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3414 3415 ohci_free_std_locked(sc, opipe->tail.td); 3416 ohci_free_sed_locked(sc, opipe->sed); 3417 } 3418 3419 Static usbd_status 3420 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3421 { 3422 int i, j, best; 3423 u_int npoll, slow, shigh, nslots; 3424 u_int bestbw, bw; 3425 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3426 3427 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3428 3429 DPRINTFN(2, "pipe=%p", opipe, 0, 0, 0); 3430 if (ival == 0) { 3431 printf("ohci_setintr: 0 interval\n"); 3432 return USBD_INVAL; 3433 } 3434 3435 npoll = OHCI_NO_INTRS; 3436 while (npoll > ival) 3437 npoll /= 2; 3438 DPRINTFN(2, "ival=%d npoll=%d", ival, npoll, 0, 0); 3439 3440 /* 3441 * We now know which level in the tree the ED must go into. 3442 * Figure out which slot has most bandwidth left over. 3443 * Slots to examine: 3444 * npoll 3445 * 1 0 3446 * 2 1 2 3447 * 4 3 4 5 6 3448 * 8 7 8 9 10 11 12 13 14 3449 * N (N-1) .. (N-1+N-1) 3450 */ 3451 slow = npoll-1; 3452 shigh = slow + npoll; 3453 nslots = OHCI_NO_INTRS / npoll; 3454 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3455 bw = 0; 3456 for (j = 0; j < nslots; j++) 3457 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3458 if (bw < bestbw) { 3459 best = i; 3460 bestbw = bw; 3461 } 3462 } 3463 DPRINTFN(2, "best=%d(%d..%d) bestbw=%d", best, slow, shigh, bestbw); 3464 3465 mutex_enter(&sc->sc_lock); 3466 hsed = sc->sc_eds[best]; 3467 sed->next = hsed->next; 3468 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3469 sizeof(hsed->ed.ed_flags), 3470 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3471 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3472 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3473 sizeof(sed->ed.ed_flags), 3474 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3475 hsed->next = sed; 3476 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3477 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3478 sizeof(hsed->ed.ed_flags), 3479 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3480 mutex_exit(&sc->sc_lock); 3481 3482 for (j = 0; j < nslots; j++) 3483 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3484 opipe->intr.nslots = nslots; 3485 opipe->intr.pos = best; 3486 3487 DPRINTFN(5, "returns %p", opipe, 0, 0, 0); 3488 return USBD_NORMAL_COMPLETION; 3489 } 3490 3491 /***********************/ 3492 3493 Static int 3494 ohci_device_isoc_init(struct usbd_xfer *xfer) 3495 { 3496 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3497 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3498 ohci_soft_itd_t *sitd; 3499 size_t i; 3500 int err; 3501 3502 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3503 3504 DPRINTFN(1, "xfer %p len %d flags %d", xfer, xfer->ux_length, 3505 xfer->ux_flags, 0); 3506 3507 const size_t nfsitd = 3508 (xfer->ux_nframes + OHCI_ITD_NOFFSET - 1) / OHCI_ITD_NOFFSET; 3509 const size_t nbsitd = xfer->ux_bufsize / OHCI_PAGE_SIZE; 3510 const size_t nsitd = MAX(nfsitd, nbsitd) + 1; 3511 3512 ox->ox_sitds = kmem_zalloc(sizeof(ohci_soft_itd_t *) * nsitd, 3513 KM_SLEEP); 3514 ox->ox_nsitd = nsitd; 3515 3516 for (i = 0; i < nsitd; i++) { 3517 /* Allocate next ITD */ 3518 sitd = ohci_alloc_sitd(sc); 3519 if (sitd == NULL) { 3520 err = ENOMEM; 3521 goto fail; 3522 } 3523 ox->ox_sitds[i] = sitd; 3524 sitd->held = &ox->ox_sitds[i]; 3525 sitd->xfer = xfer; 3526 sitd->flags = 0; 3527 // DPRINTFN(10, "xfer=%p new tail=%p held at %p", ox, tail, tail->held, 0); 3528 } 3529 3530 return 0; 3531 fail: 3532 for (; i > 0;) { 3533 ohci_free_sitd(sc, ox->ox_sitds[--i]); 3534 } 3535 return err; 3536 } 3537 3538 Static void 3539 ohci_device_isoc_fini(struct usbd_xfer *xfer) 3540 { 3541 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3542 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3543 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3544 3545 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3546 3547 mutex_enter(&sc->sc_lock); 3548 for (size_t i = 0; i < ox->ox_nsitd; i++) { 3549 if (ox->ox_sitds[i] != opipe->tail.itd) { 3550 ohci_free_sitd_locked(sc, ox->ox_sitds[i]); 3551 } 3552 } 3553 mutex_exit(&sc->sc_lock); 3554 3555 if (ox->ox_nsitd) { 3556 const size_t sz = sizeof(ohci_soft_itd_t *) * ox->ox_nsitd; 3557 kmem_free(ox->ox_sitds, sz); 3558 } 3559 } 3560 3561 3562 usbd_status 3563 ohci_device_isoc_transfer(struct usbd_xfer *xfer) 3564 { 3565 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3566 usbd_status __diagused err; 3567 3568 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3569 3570 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 3571 3572 /* Put it on our queue, */ 3573 mutex_enter(&sc->sc_lock); 3574 err = usb_insert_transfer(xfer); 3575 mutex_exit(&sc->sc_lock); 3576 3577 KASSERT(err == USBD_NORMAL_COMPLETION); 3578 3579 /* insert into schedule, */ 3580 ohci_device_isoc_enter(xfer); 3581 3582 /* and start if the pipe wasn't running */ 3583 return USBD_IN_PROGRESS; 3584 } 3585 3586 void 3587 ohci_device_isoc_enter(struct usbd_xfer *xfer) 3588 { 3589 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3590 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3591 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3592 ohci_soft_ed_t *sed = opipe->sed; 3593 ohci_soft_itd_t *sitd, *nsitd, *tail; 3594 ohci_physaddr_t buf, offs, noffs, bp0; 3595 int i, ncur, nframes; 3596 3597 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3598 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 3599 3600 mutex_enter(&sc->sc_lock); 3601 3602 if (sc->sc_dying) { 3603 mutex_exit(&sc->sc_lock); 3604 return; 3605 } 3606 3607 struct isoc *isoc = &opipe->isoc; 3608 3609 DPRINTFN(1, "used=%d next=%d xfer=%p nframes=%d", 3610 isoc->inuse, isoc->next, xfer, xfer->ux_nframes); 3611 3612 if (isoc->next == -1) { 3613 /* Not in use yet, schedule it a few frames ahead. */ 3614 isoc->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3615 DPRINTFN(2,"start next=%d", isoc->next, 0, 0, 0); 3616 } 3617 3618 sitd = opipe->tail.itd; 3619 opipe->tail.itd = ox->ox_sitds[0]; 3620 ox->ox_sitds[0] = sitd; 3621 sitd->held = &ox->ox_sitds[0]; 3622 3623 buf = DMAADDR(&xfer->ux_dmabuf, 0); 3624 bp0 = OHCI_PAGE(buf); 3625 offs = OHCI_PAGE_OFFSET(buf); 3626 nframes = xfer->ux_nframes; 3627 xfer->ux_hcpriv = sitd; 3628 size_t j = 1; 3629 for (i = ncur = 0; i < nframes; i++, ncur++) { 3630 noffs = offs + xfer->ux_frlengths[i]; 3631 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3632 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3633 3634 /* Allocate next ITD */ 3635 nsitd = ox->ox_sitds[j++]; 3636 KASSERT(nsitd != NULL); 3637 KASSERT(j < ox->ox_nsitd); 3638 3639 /* Fill current ITD */ 3640 sitd->itd.itd_flags = HTOO32( 3641 OHCI_ITD_NOCC | 3642 OHCI_ITD_SET_SF(isoc->next) | 3643 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3644 OHCI_ITD_SET_FC(ncur)); 3645 sitd->itd.itd_bp0 = HTOO32(bp0); 3646 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3647 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3648 sitd->nextitd = nsitd; 3649 sitd->xfer = xfer; 3650 sitd->flags = 0; 3651 #ifdef DIAGNOSTIC 3652 sitd->isdone = false; 3653 #endif 3654 ohci_hash_add_itd(sc, sitd); 3655 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3656 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3657 3658 sitd = nsitd; 3659 isoc->next = isoc->next + ncur; 3660 bp0 = OHCI_PAGE(buf + offs); 3661 ncur = 0; 3662 } 3663 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3664 offs = noffs; 3665 } 3666 KASSERT(j <= ox->ox_nsitd); 3667 3668 /* point at sentinel */ 3669 tail = opipe->tail.itd; 3670 memset(&tail->itd, 0, sizeof(tail->itd)); 3671 tail->held = &opipe->tail.itd; 3672 tail->nextitd = NULL; 3673 tail->xfer = NULL; 3674 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->itd), 3675 BUS_DMASYNC_PREWRITE); 3676 3677 /* Fixup last used ITD */ 3678 sitd->itd.itd_flags = HTOO32( 3679 OHCI_ITD_NOCC | 3680 OHCI_ITD_SET_SF(isoc->next) | 3681 OHCI_ITD_SET_DI(0) | 3682 OHCI_ITD_SET_FC(ncur)); 3683 sitd->itd.itd_bp0 = HTOO32(bp0); 3684 sitd->itd.itd_nextitd = HTOO32(tail->physaddr); 3685 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3686 sitd->nextitd = tail; 3687 sitd->xfer = xfer; 3688 sitd->flags = OHCI_CALL_DONE; 3689 #ifdef DIAGNOSTIC 3690 sitd->isdone = false; 3691 #endif 3692 ohci_hash_add_itd(sc, sitd); 3693 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3694 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3695 3696 isoc->next = isoc->next + ncur; 3697 isoc->inuse += nframes; 3698 3699 /* XXX pretend we did it all */ 3700 xfer->ux_actlen = offs; 3701 xfer->ux_status = USBD_IN_PROGRESS; 3702 3703 #ifdef OHCI_DEBUG 3704 if (ohcidebug >= 5) { 3705 DPRINTF("frame=%d", O32TOH(sc->sc_hcca->hcca_frame_number), 3706 0, 0, 0); 3707 ohci_dump_itds(sc, xfer->ux_hcpriv); 3708 ohci_dump_ed(sc, sed); 3709 } 3710 #endif 3711 3712 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3713 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3714 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3715 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3716 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3717 sizeof(sed->ed.ed_flags), 3718 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3719 mutex_exit(&sc->sc_lock); 3720 } 3721 3722 void 3723 ohci_device_isoc_abort(struct usbd_xfer *xfer) 3724 { 3725 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3726 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3727 ohci_soft_ed_t *sed; 3728 ohci_soft_itd_t *sitd; 3729 3730 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3731 DPRINTFN(1, "xfer=%p", xfer, 0, 0, 0); 3732 3733 KASSERT(mutex_owned(&sc->sc_lock)); 3734 3735 /* Transfer is already done. */ 3736 if (xfer->ux_status != USBD_NOT_STARTED && 3737 xfer->ux_status != USBD_IN_PROGRESS) { 3738 printf("ohci_device_isoc_abort: early return\n"); 3739 goto done; 3740 } 3741 3742 /* Give xfer the requested abort code. */ 3743 xfer->ux_status = USBD_CANCELLED; 3744 3745 sed = opipe->sed; 3746 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3747 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3748 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3749 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3750 sizeof(sed->ed.ed_flags), 3751 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3752 3753 sitd = xfer->ux_hcpriv; 3754 KASSERT(sitd); 3755 3756 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3757 3758 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3759 ohci_hash_rem_itd(sc, sitd); 3760 #ifdef DIAGNOSTIC 3761 DPRINTFN(1, "abort sets done sitd=%p", sitd, 0, 0, 0); 3762 sitd->isdone = true; 3763 #endif 3764 } 3765 3766 /* Run callback. */ 3767 usb_transfer_complete(xfer); 3768 3769 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3770 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3771 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3772 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3773 3774 done: 3775 KASSERT(mutex_owned(&sc->sc_lock)); 3776 } 3777 3778 void 3779 ohci_device_isoc_done(struct usbd_xfer *xfer) 3780 { 3781 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3782 DPRINTFN(1, "xfer=%p", xfer, 0, 0, 0); 3783 } 3784 3785 usbd_status 3786 ohci_setup_isoc(struct usbd_pipe *pipe) 3787 { 3788 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3789 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3790 struct isoc *isoc = &opipe->isoc; 3791 3792 isoc->next = -1; 3793 isoc->inuse = 0; 3794 3795 mutex_enter(&sc->sc_lock); 3796 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3797 mutex_exit(&sc->sc_lock); 3798 3799 return USBD_NORMAL_COMPLETION; 3800 } 3801 3802 void 3803 ohci_device_isoc_close(struct usbd_pipe *pipe) 3804 { 3805 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3806 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3807 3808 KASSERT(mutex_owned(&sc->sc_lock)); 3809 3810 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3811 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3812 ohci_close_pipe(pipe, sc->sc_isoc_head); 3813 #ifdef DIAGNOSTIC 3814 opipe->tail.itd->isdone = true; 3815 #endif 3816 ohci_free_sitd_locked(sc, opipe->tail.itd); 3817 } 3818
Indexes created Fri Oct 03 02:09:57 GMT 2025