ohci.c revision 1.254.2.82
1 /* $NetBSD: ohci.c,v 1.254.2.82 2016/12/27 08:32:19 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * USB Open Host Controller driver. 38 * 39 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 40 * USB spec: http://www.usb.org/developers/docs/ 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.254.2.82 2016/12/27 08:32:19 skrll Exp $"); 45 46 #ifdef _KERNEL_OPT 47 #include "opt_usb.h" 48 #endif 49 50 #include <sys/param.h> 51 52 #include <sys/cpu.h> 53 #include <sys/device.h> 54 #include <sys/kernel.h> 55 #include <sys/kmem.h> 56 #include <sys/proc.h> 57 #include <sys/queue.h> 58 #include <sys/select.h> 59 #include <sys/sysctl.h> 60 #include <sys/systm.h> 61 62 #include <machine/endian.h> 63 64 #include <dev/usb/usb.h> 65 #include <dev/usb/usbdi.h> 66 #include <dev/usb/usbdivar.h> 67 #include <dev/usb/usb_mem.h> 68 #include <dev/usb/usb_quirks.h> 69 70 #include <dev/usb/ohcireg.h> 71 #include <dev/usb/ohcivar.h> 72 #include <dev/usb/usbroothub.h> 73 #include <dev/usb/usbhist.h> 74 75 #ifdef USB_DEBUG 76 #ifndef OHCI_DEBUG 77 #define ohcidebug 0 78 #else 79 static int ohcidebug = 10; 80 81 SYSCTL_SETUP(sysctl_hw_ohci_setup, "sysctl hw.ohci setup") 82 { 83 int err; 84 const struct sysctlnode *rnode; 85 const struct sysctlnode *cnode; 86 87 err = sysctl_createv(clog, 0, NULL, &rnode, 88 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ohci", 89 SYSCTL_DESCR("ohci global controls"), 90 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 91 92 if (err) 93 goto fail; 94 95 /* control debugging printfs */ 96 err = sysctl_createv(clog, 0, &rnode, &cnode, 97 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 98 "debug", SYSCTL_DESCR("Enable debugging output"), 99 NULL, 0, &ohcidebug, sizeof(ohcidebug), CTL_CREATE, CTL_EOL); 100 if (err) 101 goto fail; 102 103 return; 104 fail: 105 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 106 } 107 108 #endif /* OHCI_DEBUG */ 109 #endif /* USB_DEBUG */ 110 111 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ohcidebug,FMT,A,B,C,D) 112 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ohcidebug,N,FMT,A,B,C,D) 113 #define OHCIHIST_FUNC() USBHIST_FUNC() 114 #define OHCIHIST_CALLED(name) USBHIST_CALLED(ohcidebug) 115 116 #if BYTE_ORDER == BIG_ENDIAN 117 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 118 #else 119 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 120 #endif 121 122 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 123 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 124 #define HTOO16(val) O16TOH(val) 125 #define HTOO32(val) O32TOH(val) 126 127 struct ohci_pipe; 128 129 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 130 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 131 132 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 133 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 134 Static void ohci_free_std_locked(ohci_softc_t *, ohci_soft_td_t *); 135 136 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 137 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 138 Static void ohci_free_sitd_locked(ohci_softc_t *, 139 ohci_soft_itd_t *); 140 141 Static int ohci_alloc_std_chain(ohci_softc_t *, struct usbd_xfer *, 142 int, int); 143 Static void ohci_free_stds(ohci_softc_t *, struct ohci_xfer *); 144 145 Static void ohci_reset_std_chain(ohci_softc_t *, struct usbd_xfer *, 146 int, int, ohci_soft_td_t *, ohci_soft_td_t **); 147 148 Static usbd_status ohci_open(struct usbd_pipe *); 149 Static void ohci_poll(struct usbd_bus *); 150 Static void ohci_softintr(void *); 151 Static void ohci_rhsc(ohci_softc_t *, struct usbd_xfer *); 152 Static void ohci_rhsc_softint(void *); 153 154 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 155 ohci_soft_ed_t *); 156 157 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 158 ohci_soft_ed_t *); 159 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 160 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 161 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 162 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 163 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 164 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 165 166 Static usbd_status ohci_setup_isoc(struct usbd_pipe *); 167 Static void ohci_device_isoc_enter(struct usbd_xfer *); 168 169 Static struct usbd_xfer * 170 ohci_allocx(struct usbd_bus *, unsigned int); 171 Static void ohci_freex(struct usbd_bus *, struct usbd_xfer *); 172 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 173 Static int ohci_roothub_ctrl(struct usbd_bus *, 174 usb_device_request_t *, void *, int); 175 176 Static usbd_status ohci_root_intr_transfer(struct usbd_xfer *); 177 Static usbd_status ohci_root_intr_start(struct usbd_xfer *); 178 Static void ohci_root_intr_abort(struct usbd_xfer *); 179 Static void ohci_root_intr_close(struct usbd_pipe *); 180 Static void ohci_root_intr_done(struct usbd_xfer *); 181 182 Static int ohci_device_ctrl_init(struct usbd_xfer *); 183 Static void ohci_device_ctrl_fini(struct usbd_xfer *); 184 Static usbd_status ohci_device_ctrl_transfer(struct usbd_xfer *); 185 Static usbd_status ohci_device_ctrl_start(struct usbd_xfer *); 186 Static void ohci_device_ctrl_abort(struct usbd_xfer *); 187 Static void ohci_device_ctrl_close(struct usbd_pipe *); 188 Static void ohci_device_ctrl_done(struct usbd_xfer *); 189 190 Static int ohci_device_bulk_init(struct usbd_xfer *); 191 Static void ohci_device_bulk_fini(struct usbd_xfer *); 192 Static usbd_status ohci_device_bulk_transfer(struct usbd_xfer *); 193 Static usbd_status ohci_device_bulk_start(struct usbd_xfer *); 194 Static void ohci_device_bulk_abort(struct usbd_xfer *); 195 Static void ohci_device_bulk_close(struct usbd_pipe *); 196 Static void ohci_device_bulk_done(struct usbd_xfer *); 197 198 Static int ohci_device_intr_init(struct usbd_xfer *); 199 Static void ohci_device_intr_fini(struct usbd_xfer *); 200 Static usbd_status ohci_device_intr_transfer(struct usbd_xfer *); 201 Static usbd_status ohci_device_intr_start(struct usbd_xfer *); 202 Static void ohci_device_intr_abort(struct usbd_xfer *); 203 Static void ohci_device_intr_close(struct usbd_pipe *); 204 Static void ohci_device_intr_done(struct usbd_xfer *); 205 206 Static int ohci_device_isoc_init(struct usbd_xfer *); 207 Static void ohci_device_isoc_fini(struct usbd_xfer *); 208 Static usbd_status ohci_device_isoc_transfer(struct usbd_xfer *); 209 Static void ohci_device_isoc_abort(struct usbd_xfer *); 210 Static void ohci_device_isoc_close(struct usbd_pipe *); 211 Static void ohci_device_isoc_done(struct usbd_xfer *); 212 213 Static usbd_status ohci_device_setintr(ohci_softc_t *, 214 struct ohci_pipe *, int); 215 216 Static void ohci_timeout(void *); 217 Static void ohci_timeout_task(void *); 218 Static void ohci_rhsc_enable(void *); 219 220 Static void ohci_close_pipe(struct usbd_pipe *, ohci_soft_ed_t *); 221 Static void ohci_abort_xfer(struct usbd_xfer *, usbd_status); 222 223 Static void ohci_device_clear_toggle(struct usbd_pipe *); 224 Static void ohci_noop(struct usbd_pipe *); 225 226 #ifdef OHCI_DEBUG 227 Static void ohci_dumpregs(ohci_softc_t *); 228 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 229 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 230 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 231 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 232 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 233 #endif 234 235 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 236 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 237 #define OWRITE1(sc, r, x) \ 238 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 239 #define OWRITE2(sc, r, x) \ 240 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 241 #define OWRITE4(sc, r, x) \ 242 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 243 244 static __inline uint32_t 245 OREAD4(ohci_softc_t *sc, bus_size_t r) 246 { 247 248 OBARR(sc); 249 return bus_space_read_4(sc->iot, sc->ioh, r); 250 } 251 252 /* Reverse the bits in a value 0 .. 31 */ 253 Static uint8_t revbits[OHCI_NO_INTRS] = 254 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 255 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 256 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 257 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 258 259 struct ohci_pipe { 260 struct usbd_pipe pipe; 261 ohci_soft_ed_t *sed; 262 union { 263 ohci_soft_td_t *td; 264 ohci_soft_itd_t *itd; 265 } tail; 266 /* Info needed for different pipe kinds. */ 267 union { 268 /* Control pipe */ 269 struct { 270 usb_dma_t reqdma; 271 } ctrl; 272 /* Interrupt pipe */ 273 struct { 274 int nslots; 275 int pos; 276 } intr; 277 /* Isochronous pipe */ 278 struct isoc { 279 int next, inuse; 280 } isoc; 281 }; 282 }; 283 284 Static const struct usbd_bus_methods ohci_bus_methods = { 285 .ubm_open = ohci_open, 286 .ubm_softint = ohci_softintr, 287 .ubm_dopoll = ohci_poll, 288 .ubm_allocx = ohci_allocx, 289 .ubm_freex = ohci_freex, 290 .ubm_getlock = ohci_get_lock, 291 .ubm_rhctrl = ohci_roothub_ctrl, 292 }; 293 294 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 295 .upm_transfer = ohci_root_intr_transfer, 296 .upm_start = ohci_root_intr_start, 297 .upm_abort = ohci_root_intr_abort, 298 .upm_close = ohci_root_intr_close, 299 .upm_cleartoggle = ohci_noop, 300 .upm_done = ohci_root_intr_done, 301 }; 302 303 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 304 .upm_init = ohci_device_ctrl_init, 305 .upm_fini = ohci_device_ctrl_fini, 306 .upm_transfer = ohci_device_ctrl_transfer, 307 .upm_start = ohci_device_ctrl_start, 308 .upm_abort = ohci_device_ctrl_abort, 309 .upm_close = ohci_device_ctrl_close, 310 .upm_cleartoggle = ohci_noop, 311 .upm_done = ohci_device_ctrl_done, 312 }; 313 314 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 315 .upm_init = ohci_device_intr_init, 316 .upm_fini = ohci_device_intr_fini, 317 .upm_transfer = ohci_device_intr_transfer, 318 .upm_start = ohci_device_intr_start, 319 .upm_abort = ohci_device_intr_abort, 320 .upm_close = ohci_device_intr_close, 321 .upm_cleartoggle = ohci_device_clear_toggle, 322 .upm_done = ohci_device_intr_done, 323 }; 324 325 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 326 .upm_init = ohci_device_bulk_init, 327 .upm_fini = ohci_device_bulk_fini, 328 .upm_transfer = ohci_device_bulk_transfer, 329 .upm_start = ohci_device_bulk_start, 330 .upm_abort = ohci_device_bulk_abort, 331 .upm_close = ohci_device_bulk_close, 332 .upm_cleartoggle = ohci_device_clear_toggle, 333 .upm_done = ohci_device_bulk_done, 334 }; 335 336 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 337 .upm_init = ohci_device_isoc_init, 338 .upm_fini = ohci_device_isoc_fini, 339 .upm_transfer = ohci_device_isoc_transfer, 340 .upm_abort = ohci_device_isoc_abort, 341 .upm_close = ohci_device_isoc_close, 342 .upm_cleartoggle = ohci_noop, 343 .upm_done = ohci_device_isoc_done, 344 }; 345 346 int 347 ohci_activate(device_t self, enum devact act) 348 { 349 struct ohci_softc *sc = device_private(self); 350 351 switch (act) { 352 case DVACT_DEACTIVATE: 353 sc->sc_dying = 1; 354 return 0; 355 default: 356 return EOPNOTSUPP; 357 } 358 } 359 360 void 361 ohci_childdet(device_t self, device_t child) 362 { 363 struct ohci_softc *sc = device_private(self); 364 365 KASSERT(sc->sc_child == child); 366 sc->sc_child = NULL; 367 } 368 369 int 370 ohci_detach(struct ohci_softc *sc, int flags) 371 { 372 int rv = 0; 373 374 if (sc->sc_child != NULL) 375 rv = config_detach(sc->sc_child, flags); 376 377 if (rv != 0) 378 return rv; 379 380 callout_halt(&sc->sc_tmo_rhsc, &sc->sc_lock); 381 382 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 383 callout_destroy(&sc->sc_tmo_rhsc); 384 385 softint_disestablish(sc->sc_rhsc_si); 386 387 cv_destroy(&sc->sc_softwake_cv); 388 389 mutex_destroy(&sc->sc_lock); 390 mutex_destroy(&sc->sc_intr_lock); 391 392 if (sc->sc_hcca != NULL) 393 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 394 pool_cache_destroy(sc->sc_xferpool); 395 396 return rv; 397 } 398 399 ohci_soft_ed_t * 400 ohci_alloc_sed(ohci_softc_t *sc) 401 { 402 ohci_soft_ed_t *sed; 403 usbd_status err; 404 int i, offs; 405 usb_dma_t dma; 406 407 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 408 409 mutex_enter(&sc->sc_lock); 410 if (sc->sc_freeeds == NULL) { 411 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 412 mutex_exit(&sc->sc_lock); 413 414 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 415 OHCI_ED_ALIGN, &dma); 416 if (err) 417 return 0; 418 419 mutex_enter(&sc->sc_lock); 420 for (i = 0; i < OHCI_SED_CHUNK; i++) { 421 offs = i * OHCI_SED_SIZE; 422 sed = KERNADDR(&dma, offs); 423 sed->physaddr = DMAADDR(&dma, offs); 424 sed->dma = dma; 425 sed->offs = offs; 426 sed->next = sc->sc_freeeds; 427 sc->sc_freeeds = sed; 428 } 429 } 430 sed = sc->sc_freeeds; 431 sc->sc_freeeds = sed->next; 432 mutex_exit(&sc->sc_lock); 433 434 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 435 sed->next = 0; 436 return sed; 437 } 438 439 static inline void 440 ohci_free_sed_locked(ohci_softc_t *sc, ohci_soft_ed_t *sed) 441 { 442 443 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 444 445 sed->next = sc->sc_freeeds; 446 sc->sc_freeeds = sed; 447 } 448 449 void 450 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 451 { 452 453 mutex_enter(&sc->sc_lock); 454 ohci_free_sed_locked(sc, sed); 455 mutex_exit(&sc->sc_lock); 456 } 457 458 ohci_soft_td_t * 459 ohci_alloc_std(ohci_softc_t *sc) 460 { 461 ohci_soft_td_t *std; 462 usbd_status err; 463 int i, offs; 464 usb_dma_t dma; 465 466 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 467 468 mutex_enter(&sc->sc_lock); 469 if (sc->sc_freetds == NULL) { 470 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 471 mutex_exit(&sc->sc_lock); 472 473 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 474 OHCI_TD_ALIGN, &dma); 475 if (err) 476 return NULL; 477 478 mutex_enter(&sc->sc_lock); 479 for (i = 0; i < OHCI_STD_CHUNK; i++) { 480 offs = i * OHCI_STD_SIZE; 481 std = KERNADDR(&dma, offs); 482 std->physaddr = DMAADDR(&dma, offs); 483 std->dma = dma; 484 std->offs = offs; 485 std->nexttd = sc->sc_freetds; 486 sc->sc_freetds = std; 487 } 488 } 489 490 std = sc->sc_freetds; 491 sc->sc_freetds = std->nexttd; 492 mutex_exit(&sc->sc_lock); 493 494 memset(&std->td, 0, sizeof(ohci_td_t)); 495 std->nexttd = NULL; 496 std->xfer = NULL; 497 std->held = NULL; 498 499 return std; 500 } 501 502 void 503 ohci_free_std_locked(ohci_softc_t *sc, ohci_soft_td_t *std) 504 { 505 506 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 507 508 std->nexttd = sc->sc_freetds; 509 sc->sc_freetds = std; 510 } 511 512 void 513 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 514 { 515 516 mutex_enter(&sc->sc_lock); 517 ohci_free_std_locked(sc, std); 518 mutex_exit(&sc->sc_lock); 519 } 520 521 Static int 522 ohci_alloc_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, int length, int rd) 523 { 524 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 525 uint16_t flags = xfer->ux_flags; 526 527 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 528 529 DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d", 530 xfer->ux_pipe->up_dev->ud_addr, 531 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 532 length, xfer->ux_pipe->up_dev->ud_speed); 533 534 ASSERT_SLEEPABLE(); 535 KASSERT(length != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 536 537 size_t nstd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 538 nstd += ((length + OHCI_PAGE_SIZE - 1) / OHCI_PAGE_SIZE); 539 ox->ox_stds = kmem_zalloc(sizeof(ohci_soft_td_t *) * nstd, 540 KM_SLEEP); 541 ox->ox_nstd = nstd; 542 543 DPRINTFN(8, "xfer %p nstd %d", xfer, nstd, 0, 0); 544 545 for (size_t j = 0; j < ox->ox_nstd; j++) { 546 ohci_soft_td_t *cur = ohci_alloc_std(sc); 547 if (cur == NULL) 548 goto nomem; 549 550 ox->ox_stds[j] = cur; 551 cur->held = &ox->ox_stds[j]; 552 cur->xfer = xfer; 553 cur->flags = 0; 554 DPRINTFN(10, "xfer=%p new std=%p held at %p", ox, cur, 555 cur->held, 0); 556 } 557 558 return 0; 559 560 nomem: 561 ohci_free_stds(sc, ox); 562 kmem_free(ox->ox_stds, sizeof(ohci_soft_td_t *) * nstd); 563 564 return ENOMEM; 565 } 566 567 Static void 568 ohci_free_stds(ohci_softc_t *sc, struct ohci_xfer *ox) 569 { 570 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 571 DPRINTF("ox=%p", ox, 0, 0, 0); 572 573 mutex_enter(&sc->sc_lock); 574 for (size_t i = 0; i < ox->ox_nstd; i++) { 575 ohci_soft_td_t *std = ox->ox_stds[i]; 576 if (std == NULL) 577 break; 578 ohci_free_std_locked(sc, std); 579 } 580 mutex_exit(&sc->sc_lock); 581 } 582 583 void 584 ohci_reset_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, 585 int alen, int rd, ohci_soft_td_t *sp, ohci_soft_td_t **ep) 586 { 587 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 588 ohci_soft_td_t *next, *cur; 589 int len, curlen; 590 usb_dma_t *dma = &xfer->ux_dmabuf; 591 uint16_t flags = xfer->ux_flags; 592 593 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 594 DPRINTF("start len=%d", alen, 0, 0, 0); 595 596 KASSERT(mutex_owned(&sc->sc_lock)); 597 598 DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d", 599 xfer->ux_pipe->up_dev->ud_addr, 600 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 601 alen, xfer->ux_pipe->up_dev->ud_speed); 602 603 KASSERT(sp); 604 605 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 606 607 /* 608 * Assign next for the len == 0 case where we don't go through the 609 * main loop. 610 */ 611 len = alen; 612 cur = next = sp; 613 614 usb_syncmem(dma, 0, len, 615 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 616 const uint32_t tdflags = HTOO32( 617 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 618 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 619 620 size_t curoffs = 0; 621 for (size_t j = 1; len != 0;) { 622 if (j == ox->ox_nstd) 623 next = NULL; 624 else 625 next = ox->ox_stds[j++]; 626 KASSERT(next != cur); 627 628 curlen = 0; 629 ohci_physaddr_t sdataphys = DMAADDR(dma, curoffs); 630 ohci_physaddr_t edataphys = DMAADDR(dma, curoffs + len - 1); 631 632 ohci_physaddr_t sphyspg = OHCI_PAGE(sdataphys); 633 ohci_physaddr_t ephyspg = OHCI_PAGE(edataphys); 634 /* 635 * The OHCI hardware can handle at most one page 636 * crossing per TD 637 */ 638 curlen = len; 639 if (!(sphyspg == ephyspg || sphyspg + 1 == ephyspg)) { 640 /* must use multiple TDs, fill as much as possible. */ 641 curlen = 2 * OHCI_PAGE_SIZE - 642 (sdataphys & (OHCI_PAGE_SIZE - 1)); 643 /* the length must be a multiple of the max size */ 644 curlen -= curlen % mps; 645 } 646 KASSERT(curlen != 0); 647 DPRINTFN(4, "sdataphys=0x%08x edataphys=0x%08x " 648 "len=%d curlen=%d", sdataphys, edataphys, len, curlen); 649 650 cur->td.td_flags = tdflags; 651 cur->td.td_cbp = HTOO32(sdataphys); 652 cur->td.td_be = HTOO32(edataphys); 653 cur->td.td_nexttd = (next != NULL) ? HTOO32(next->physaddr) : 0; 654 cur->nexttd = next; 655 cur->len = curlen; 656 cur->flags = OHCI_ADD_LEN; 657 cur->xfer = xfer; 658 ohci_hash_add_td(sc, cur); 659 660 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 661 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 662 663 curoffs += curlen; 664 len -= curlen; 665 666 if (len != 0) { 667 KASSERT(next != NULL); 668 DPRINTFN(10, "extend chain", 0, 0, 0, 0); 669 cur = next; 670 } 671 } 672 cur->td.td_flags |= 673 HTOO32(xfer->ux_flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0); 674 675 if (!rd && 676 (flags & USBD_FORCE_SHORT_XFER) && 677 alen % mps == 0) { 678 /* Force a 0 length transfer at the end. */ 679 680 KASSERT(next != NULL); 681 cur = next; 682 683 cur->td.td_flags = tdflags; 684 cur->td.td_cbp = 0; /* indicate 0 length packet */ 685 cur->td.td_nexttd = 0; 686 cur->td.td_be = ~0; 687 cur->nexttd = NULL; 688 cur->len = 0; 689 cur->flags = 0; 690 cur->xfer = xfer; 691 ohci_hash_add_td(sc, cur); 692 693 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 694 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 695 DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0); 696 } 697 *ep = cur; 698 } 699 700 ohci_soft_itd_t * 701 ohci_alloc_sitd(ohci_softc_t *sc) 702 { 703 ohci_soft_itd_t *sitd; 704 usbd_status err; 705 int i, offs; 706 usb_dma_t dma; 707 708 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 709 710 mutex_enter(&sc->sc_lock); 711 if (sc->sc_freeitds == NULL) { 712 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 713 mutex_exit(&sc->sc_lock); 714 715 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 716 OHCI_ITD_ALIGN, &dma); 717 if (err) 718 return NULL; 719 mutex_enter(&sc->sc_lock); 720 for (i = 0; i < OHCI_SITD_CHUNK; i++) { 721 offs = i * OHCI_SITD_SIZE; 722 sitd = KERNADDR(&dma, offs); 723 sitd->physaddr = DMAADDR(&dma, offs); 724 sitd->dma = dma; 725 sitd->offs = offs; 726 sitd->nextitd = sc->sc_freeitds; 727 sc->sc_freeitds = sitd; 728 } 729 } 730 731 sitd = sc->sc_freeitds; 732 sc->sc_freeitds = sitd->nextitd; 733 mutex_exit(&sc->sc_lock); 734 735 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 736 sitd->nextitd = NULL; 737 sitd->xfer = NULL; 738 739 #ifdef DIAGNOSTIC 740 sitd->isdone = true; 741 #endif 742 743 return sitd; 744 } 745 746 Static void 747 ohci_free_sitd_locked(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 748 { 749 750 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 751 DPRINTFN(10, "sitd=%p", sitd, 0, 0, 0); 752 753 KASSERT(sitd->isdone); 754 #ifdef DIAGNOSTIC 755 /* Warn double free */ 756 sitd->isdone = false; 757 #endif 758 759 sitd->nextitd = sc->sc_freeitds; 760 sc->sc_freeitds = sitd; 761 } 762 763 void 764 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 765 { 766 767 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 768 769 mutex_enter(&sc->sc_lock); 770 ohci_free_sitd_locked(sc, sitd); 771 mutex_exit(&sc->sc_lock); 772 } 773 774 int 775 ohci_init(ohci_softc_t *sc) 776 { 777 ohci_soft_ed_t *sed, *psed; 778 usbd_status err; 779 int i; 780 uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */; 781 782 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 783 784 aprint_normal_dev(sc->sc_dev, ""); 785 786 sc->sc_hcca = NULL; 787 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 788 789 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 790 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 791 cv_init(&sc->sc_softwake_cv, "ohciab"); 792 793 sc->sc_rhsc_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 794 ohci_rhsc_softint, sc); 795 796 for (i = 0; i < OHCI_HASH_SIZE; i++) 797 LIST_INIT(&sc->sc_hash_tds[i]); 798 for (i = 0; i < OHCI_HASH_SIZE; i++) 799 LIST_INIT(&sc->sc_hash_itds[i]); 800 801 TAILQ_INIT(&sc->sc_abortingxfers); 802 803 sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0, 804 "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL); 805 806 rev = OREAD4(sc, OHCI_REVISION); 807 aprint_normal("OHCI version %d.%d%s\n", 808 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 809 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 810 811 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 812 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 813 sc->sc_bus.ub_revision = USBREV_UNKNOWN; 814 return -1; 815 } 816 sc->sc_bus.ub_revision = USBREV_1_0; 817 sc->sc_bus.ub_usedma = true; 818 819 /* XXX determine alignment by R/W */ 820 /* Allocate the HCCA area. */ 821 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 822 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 823 if (err) { 824 sc->sc_hcca = NULL; 825 return err; 826 } 827 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 828 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 829 830 sc->sc_eintrs = OHCI_NORMAL_INTRS; 831 832 /* Allocate dummy ED that starts the control list. */ 833 sc->sc_ctrl_head = ohci_alloc_sed(sc); 834 if (sc->sc_ctrl_head == NULL) { 835 err = ENOMEM; 836 goto bad1; 837 } 838 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 839 840 /* Allocate dummy ED that starts the bulk list. */ 841 sc->sc_bulk_head = ohci_alloc_sed(sc); 842 if (sc->sc_bulk_head == NULL) { 843 err = ENOMEM; 844 goto bad2; 845 } 846 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 847 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 848 sizeof(sc->sc_bulk_head->ed), 849 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 850 851 /* Allocate dummy ED that starts the isochronous list. */ 852 sc->sc_isoc_head = ohci_alloc_sed(sc); 853 if (sc->sc_isoc_head == NULL) { 854 err = ENOMEM; 855 goto bad3; 856 } 857 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 858 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 859 sizeof(sc->sc_isoc_head->ed), 860 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 861 862 /* Allocate all the dummy EDs that make up the interrupt tree. */ 863 for (i = 0; i < OHCI_NO_EDS; i++) { 864 sed = ohci_alloc_sed(sc); 865 if (sed == NULL) { 866 while (--i >= 0) 867 ohci_free_sed(sc, sc->sc_eds[i]); 868 err = ENOMEM; 869 goto bad4; 870 } 871 /* All ED fields are set to 0. */ 872 sc->sc_eds[i] = sed; 873 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 874 if (i != 0) 875 psed = sc->sc_eds[(i-1) / 2]; 876 else 877 psed= sc->sc_isoc_head; 878 sed->next = psed; 879 sed->ed.ed_nexted = HTOO32(psed->physaddr); 880 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 881 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 882 } 883 /* 884 * Fill HCCA interrupt table. The bit reversal is to get 885 * the tree set up properly to spread the interrupts. 886 */ 887 for (i = 0; i < OHCI_NO_INTRS; i++) 888 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 889 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 890 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 891 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 892 893 #ifdef OHCI_DEBUG 894 DPRINTFN(15, "--- dump start ---", 0, 0, 0 ,0); 895 if (ohcidebug >= 15) { 896 for (i = 0; i < OHCI_NO_EDS; i++) { 897 DPRINTFN(15, "ed#%d ", i, 0, 0, 0); 898 ohci_dump_ed(sc, sc->sc_eds[i]); 899 } 900 DPRINTFN(15, "iso", 0, 0, 0 ,0); 901 ohci_dump_ed(sc, sc->sc_isoc_head); 902 } 903 DPRINTFN(15, "--- dump end ---", 0, 0, 0 ,0); 904 #endif 905 906 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 907 ctl = OREAD4(sc, OHCI_CONTROL); 908 rwc = ctl & OHCI_RWC; 909 fm = OREAD4(sc, OHCI_FM_INTERVAL); 910 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 911 /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */ 912 913 /* Determine in what context we are running. */ 914 if (ctl & OHCI_IR) { 915 /* SMM active, request change */ 916 DPRINTF("SMM active, request owner change", 0, 0, 0, 0); 917 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 918 (OHCI_OC | OHCI_MIE)) 919 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 920 s = OREAD4(sc, OHCI_COMMAND_STATUS); 921 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 922 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 923 usb_delay_ms(&sc->sc_bus, 1); 924 ctl = OREAD4(sc, OHCI_CONTROL); 925 } 926 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 927 if ((ctl & OHCI_IR) == 0) { 928 aprint_error_dev(sc->sc_dev, 929 "SMM does not respond, resetting\n"); 930 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 931 goto reset; 932 } 933 #if 0 934 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 935 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 936 /* BIOS started controller. */ 937 DPRINTF("BIOS active", 0, 0, 0, 0); 938 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 939 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 940 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 941 } 942 #endif 943 } else { 944 DPRINTF("cold started", 0 ,0 ,0 ,0); 945 reset: 946 /* Controller was cold started. */ 947 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 948 } 949 950 /* 951 * This reset should not be necessary according to the OHCI spec, but 952 * without it some controllers do not start. 953 */ 954 DPRINTF("sc %p: resetting", sc, 0, 0, 0); 955 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 956 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 957 958 /* We now own the host controller and the bus has been reset. */ 959 960 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 961 /* Nominal time for a reset is 10 us. */ 962 for (i = 0; i < 10; i++) { 963 delay(10); 964 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 965 if (!hcr) 966 break; 967 } 968 if (hcr) { 969 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 970 err = EIO; 971 goto bad5; 972 } 973 #ifdef OHCI_DEBUG 974 if (ohcidebug >= 15) 975 ohci_dumpregs(sc); 976 #endif 977 978 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 979 980 /* Set up HC registers. */ 981 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 982 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 983 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 984 /* disable all interrupts and then switch on all desired interrupts */ 985 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 986 /* switch on desired functional features */ 987 ctl = OREAD4(sc, OHCI_CONTROL); 988 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 989 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 990 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 991 /* And finally start it! */ 992 OWRITE4(sc, OHCI_CONTROL, ctl); 993 994 /* 995 * The controller is now OPERATIONAL. Set a some final 996 * registers that should be set earlier, but that the 997 * controller ignores when in the SUSPEND state. 998 */ 999 ival = OHCI_GET_IVAL(fm); 1000 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 1001 fm |= OHCI_FSMPS(ival) | ival; 1002 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 1003 per = OHCI_PERIODIC(ival); /* 90% periodic */ 1004 OWRITE4(sc, OHCI_PERIODIC_START, per); 1005 1006 if (sc->sc_flags & OHCIF_SUPERIO) { 1007 /* no overcurrent protection */ 1008 desca |= OHCI_NOCP; 1009 /* 1010 * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning 1011 * that 1012 * - ports are always power switched 1013 * - don't wait for powered root hub port 1014 */ 1015 desca &= ~(__SHIFTIN(0xff, OHCI_POTPGT_MASK) | OHCI_NPS); 1016 } 1017 1018 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 1019 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 1020 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 1021 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 1022 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 1023 1024 /* 1025 * The AMD756 requires a delay before re-reading the register, 1026 * otherwise it will occasionally report 0 ports. 1027 */ 1028 sc->sc_noport = 0; 1029 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 1030 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 1031 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 1032 } 1033 1034 #ifdef OHCI_DEBUG 1035 if (ohcidebug >= 5) 1036 ohci_dumpregs(sc); 1037 #endif 1038 1039 /* Set up the bus struct. */ 1040 sc->sc_bus.ub_methods = &ohci_bus_methods; 1041 sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe); 1042 1043 sc->sc_control = sc->sc_intre = 0; 1044 1045 /* Finally, turn on interrupts. */ 1046 DPRINTF("enabling %#x", sc->sc_eintrs | OHCI_MIE, 0, 0, 0); 1047 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 1048 1049 return 0; 1050 1051 bad5: 1052 for (i = 0; i < OHCI_NO_EDS; i++) 1053 ohci_free_sed(sc, sc->sc_eds[i]); 1054 bad4: 1055 ohci_free_sed(sc, sc->sc_isoc_head); 1056 bad3: 1057 ohci_free_sed(sc, sc->sc_bulk_head); 1058 bad2: 1059 ohci_free_sed(sc, sc->sc_ctrl_head); 1060 bad1: 1061 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 1062 sc->sc_hcca = NULL; 1063 return err; 1064 } 1065 1066 struct usbd_xfer * 1067 ohci_allocx(struct usbd_bus *bus, unsigned int nframes) 1068 { 1069 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1070 struct usbd_xfer *xfer; 1071 1072 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1073 if (xfer != NULL) { 1074 memset(xfer, 0, sizeof(struct ohci_xfer)); 1075 #ifdef DIAGNOSTIC 1076 xfer->ux_state = XFER_BUSY; 1077 #endif 1078 } 1079 return xfer; 1080 } 1081 1082 void 1083 ohci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1084 { 1085 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1086 1087 KASSERTMSG(xfer->ux_state == XFER_BUSY, 1088 "xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state); 1089 #ifdef DIAGNOSTIC 1090 xfer->ux_state = XFER_FREE; 1091 #endif 1092 pool_cache_put(sc->sc_xferpool, xfer); 1093 } 1094 1095 Static void 1096 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1097 { 1098 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1099 1100 *lock = &sc->sc_lock; 1101 } 1102 1103 /* 1104 * Shut down the controller when the system is going down. 1105 */ 1106 bool 1107 ohci_shutdown(device_t self, int flags) 1108 { 1109 ohci_softc_t *sc = device_private(self); 1110 1111 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1112 1113 DPRINTF("stopping the HC", 0, 0, 0, 0); 1114 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1115 return true; 1116 } 1117 1118 bool 1119 ohci_resume(device_t dv, const pmf_qual_t *qual) 1120 { 1121 ohci_softc_t *sc = device_private(dv); 1122 uint32_t ctl; 1123 1124 mutex_spin_enter(&sc->sc_intr_lock); 1125 sc->sc_bus.ub_usepolling++; 1126 mutex_spin_exit(&sc->sc_intr_lock); 1127 1128 /* Some broken BIOSes do not recover these values */ 1129 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1130 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1131 sc->sc_ctrl_head->physaddr); 1132 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1133 sc->sc_bulk_head->physaddr); 1134 if (sc->sc_intre) 1135 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1136 (OHCI_ALL_INTRS | OHCI_MIE)); 1137 if (sc->sc_control) 1138 ctl = sc->sc_control; 1139 else 1140 ctl = OREAD4(sc, OHCI_CONTROL); 1141 ctl |= OHCI_HCFS_RESUME; 1142 OWRITE4(sc, OHCI_CONTROL, ctl); 1143 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1144 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1145 OWRITE4(sc, OHCI_CONTROL, ctl); 1146 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1147 sc->sc_control = sc->sc_intre = 0; 1148 1149 mutex_spin_enter(&sc->sc_intr_lock); 1150 sc->sc_bus.ub_usepolling--; 1151 mutex_spin_exit(&sc->sc_intr_lock); 1152 1153 return true; 1154 } 1155 1156 bool 1157 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1158 { 1159 ohci_softc_t *sc = device_private(dv); 1160 uint32_t ctl; 1161 1162 mutex_spin_enter(&sc->sc_intr_lock); 1163 sc->sc_bus.ub_usepolling++; 1164 mutex_spin_exit(&sc->sc_intr_lock); 1165 1166 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1167 if (sc->sc_control == 0) { 1168 /* 1169 * Preserve register values, in case that BIOS 1170 * does not recover them. 1171 */ 1172 sc->sc_control = ctl; 1173 sc->sc_intre = OREAD4(sc, 1174 OHCI_INTERRUPT_ENABLE); 1175 } 1176 ctl |= OHCI_HCFS_SUSPEND; 1177 OWRITE4(sc, OHCI_CONTROL, ctl); 1178 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1179 1180 mutex_spin_enter(&sc->sc_intr_lock); 1181 sc->sc_bus.ub_usepolling--; 1182 mutex_spin_exit(&sc->sc_intr_lock); 1183 1184 return true; 1185 } 1186 1187 #ifdef OHCI_DEBUG 1188 void 1189 ohci_dumpregs(ohci_softc_t *sc) 1190 { 1191 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1192 1193 DPRINTF("rev=0x%08x control=0x%08x command=0x%08x", 1194 OREAD4(sc, OHCI_REVISION), 1195 OREAD4(sc, OHCI_CONTROL), 1196 OREAD4(sc, OHCI_COMMAND_STATUS), 0); 1197 DPRINTF(" intrstat=0x%08x intre=0x%08x intrd=0x%08x", 1198 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1199 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1200 OREAD4(sc, OHCI_INTERRUPT_DISABLE), 0); 1201 DPRINTF(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x", 1202 OREAD4(sc, OHCI_HCCA), 1203 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1204 OREAD4(sc, OHCI_CONTROL_HEAD_ED), 0); 1205 DPRINTF(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x", 1206 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1207 OREAD4(sc, OHCI_BULK_HEAD_ED), 1208 OREAD4(sc, OHCI_BULK_CURRENT_ED) ,0); 1209 DPRINTF(" done=0x%08x fmival=0x%08x fmrem=0x%08x", 1210 OREAD4(sc, OHCI_DONE_HEAD), 1211 OREAD4(sc, OHCI_FM_INTERVAL), 1212 OREAD4(sc, OHCI_FM_REMAINING), 0); 1213 DPRINTF(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x", 1214 OREAD4(sc, OHCI_FM_NUMBER), 1215 OREAD4(sc, OHCI_PERIODIC_START), 1216 OREAD4(sc, OHCI_LS_THRESHOLD), 0); 1217 DPRINTF(" desca=0x%08x descb=0x%08x stat=0x%08x", 1218 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1219 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1220 OREAD4(sc, OHCI_RH_STATUS), 0); 1221 DPRINTF(" port1=0x%08x port2=0x%08x", 1222 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1223 OREAD4(sc, OHCI_RH_PORT_STATUS(2)), 0, 0); 1224 DPRINTF(" HCCA: frame_number=0x%04x done_head=0x%08x", 1225 O32TOH(sc->sc_hcca->hcca_frame_number), 1226 O32TOH(sc->sc_hcca->hcca_done_head), 0, 0); 1227 } 1228 #endif 1229 1230 Static int ohci_intr1(ohci_softc_t *); 1231 1232 int 1233 ohci_intr(void *p) 1234 { 1235 ohci_softc_t *sc = p; 1236 int ret = 0; 1237 1238 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1239 1240 if (sc == NULL) 1241 return 0; 1242 1243 mutex_spin_enter(&sc->sc_intr_lock); 1244 1245 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1246 goto done; 1247 1248 /* If we get an interrupt while polling, then just ignore it. */ 1249 if (sc->sc_bus.ub_usepolling) { 1250 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1251 /* for level triggered intrs, should do something to ack */ 1252 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1253 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1254 1255 goto done; 1256 } 1257 1258 ret = ohci_intr1(sc); 1259 1260 done: 1261 mutex_spin_exit(&sc->sc_intr_lock); 1262 return ret; 1263 } 1264 1265 Static int 1266 ohci_intr1(ohci_softc_t *sc) 1267 { 1268 uint32_t intrs, eintrs; 1269 1270 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1271 1272 /* In case the interrupt occurs before initialization has completed. */ 1273 if (sc == NULL || sc->sc_hcca == NULL) { 1274 #ifdef DIAGNOSTIC 1275 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1276 #endif 1277 return 0; 1278 } 1279 1280 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1281 1282 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1283 if (!intrs) 1284 return 0; 1285 1286 /* Acknowledge */ 1287 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); 1288 eintrs = intrs & sc->sc_eintrs; 1289 DPRINTFN(7, "sc=%p", sc, 0, 0, 0); 1290 DPRINTFN(7, "intrs=%#x(%#x) eintrs=%#x(%#x)", 1291 intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), eintrs, 1292 sc->sc_eintrs); 1293 1294 if (!eintrs) { 1295 return 0; 1296 } 1297 1298 if (eintrs & OHCI_SO) { 1299 sc->sc_overrun_cnt++; 1300 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1301 printf("%s: %u scheduling overruns\n", 1302 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1303 sc->sc_overrun_cnt = 0; 1304 } 1305 /* XXX do what */ 1306 eintrs &= ~OHCI_SO; 1307 } 1308 if (eintrs & OHCI_WDH) { 1309 /* 1310 * We block the interrupt below, and reenable it later from 1311 * ohci_softintr(). 1312 */ 1313 usb_schedsoftintr(&sc->sc_bus); 1314 } 1315 if (eintrs & OHCI_RD) { 1316 DPRINTFN(5, "resume detect", sc, 0, 0, 0); 1317 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1318 /* XXX process resume detect */ 1319 } 1320 if (eintrs & OHCI_UE) { 1321 DPRINTFN(5, "unrecoverable error", sc, 0, 0, 0); 1322 printf("%s: unrecoverable error, controller halted\n", 1323 device_xname(sc->sc_dev)); 1324 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1325 /* XXX what else */ 1326 } 1327 if (eintrs & OHCI_RHSC) { 1328 /* 1329 * We block the interrupt below, and reenable it later from 1330 * a timeout. 1331 */ 1332 softint_schedule(sc->sc_rhsc_si); 1333 } 1334 if (eintrs & OHCI_SF) { 1335 struct ohci_xfer *ox, *tmp; 1336 TAILQ_FOREACH_SAFE(ox, &sc->sc_abortingxfers, ox_abnext, tmp) { 1337 DPRINTFN(10, "SF %p xfer %p", sc, ox, 0, 0); 1338 ox->ox_abintrs &= ~OHCI_SF; 1339 KASSERT(ox->ox_abintrs == 0); 1340 TAILQ_REMOVE(&sc->sc_abortingxfers, ox, ox_abnext); 1341 } 1342 cv_broadcast(&sc->sc_softwake_cv); 1343 1344 KASSERT(TAILQ_EMPTY(&sc->sc_abortingxfers)); 1345 DPRINTFN(10, "end SOF %p", sc, 0, 0, 0); 1346 /* Don't remove OHIC_SF from eintrs so it is blocked below */ 1347 } 1348 1349 if (eintrs != 0) { 1350 /* Block unprocessed interrupts. */ 1351 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1352 sc->sc_eintrs &= ~eintrs; 1353 DPRINTF("sc %p blocking/removing intrs 0x%x", sc, eintrs, 0, 0); 1354 } 1355 1356 return 1; 1357 } 1358 1359 void 1360 ohci_rhsc_enable(void *v_sc) 1361 { 1362 ohci_softc_t *sc = v_sc; 1363 1364 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1365 DPRINTF("sc %p", sc, 0, 0, 0); 1366 mutex_spin_enter(&sc->sc_intr_lock); 1367 sc->sc_eintrs |= OHCI_RHSC; 1368 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1369 mutex_spin_exit(&sc->sc_intr_lock); 1370 } 1371 1372 #ifdef OHCI_DEBUG 1373 const char *ohci_cc_strs[] = { 1374 "NO_ERROR", 1375 "CRC", 1376 "BIT_STUFFING", 1377 "DATA_TOGGLE_MISMATCH", 1378 "STALL", 1379 "DEVICE_NOT_RESPONDING", 1380 "PID_CHECK_FAILURE", 1381 "UNEXPECTED_PID", 1382 "DATA_OVERRUN", 1383 "DATA_UNDERRUN", 1384 "BUFFER_OVERRUN", 1385 "BUFFER_UNDERRUN", 1386 "reserved", 1387 "reserved", 1388 "NOT_ACCESSED", 1389 "NOT_ACCESSED", 1390 }; 1391 #endif 1392 1393 void 1394 ohci_softintr(void *v) 1395 { 1396 struct usbd_bus *bus = v; 1397 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1398 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1399 ohci_soft_td_t *std, *sdone, *stdnext; 1400 struct usbd_xfer *xfer; 1401 struct ohci_pipe *opipe; 1402 int len, cc; 1403 int i, j, actlen, iframes, uedir; 1404 ohci_physaddr_t done = 0; 1405 bool polling = sc->sc_bus.ub_usepolling; 1406 1407 KASSERT(polling || mutex_owned(&sc->sc_lock)); 1408 1409 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1410 1411 /* 1412 * Only read hccadone if WDH is set - we might get here from places 1413 * other than an interrupt 1414 */ 1415 if (!(OREAD4(sc, OHCI_INTERRUPT_STATUS) & OHCI_WDH)) { 1416 DPRINTFN(10, "no WDH %p", sc, 0, 0, 0); 1417 return; 1418 } 1419 1420 DPRINTFN(10, "WDH %p", sc, 0, 0, 0); 1421 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1422 sizeof(sc->sc_hcca->hcca_done_head), 1423 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1424 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1425 sc->sc_hcca->hcca_done_head = 0; 1426 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1427 sizeof(sc->sc_hcca->hcca_done_head), 1428 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1429 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1430 sc->sc_eintrs |= OHCI_WDH; 1431 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1432 1433 /* Reverse the done list. */ 1434 for (sdone = NULL, sidone = NULL; done != 0; ) { 1435 std = ohci_hash_find_td(sc, done); 1436 if (std != NULL) { 1437 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1438 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1439 std->dnext = sdone; 1440 done = O32TOH(std->td.td_nexttd); 1441 sdone = std; 1442 DPRINTFN(10, "add TD %p", std, 0, 0, 0); 1443 continue; 1444 } 1445 sitd = ohci_hash_find_itd(sc, done); 1446 if (sitd != NULL) { 1447 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1448 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1449 sitd->dnext = sidone; 1450 done = O32TOH(sitd->itd.itd_nextitd); 1451 sidone = sitd; 1452 DPRINTFN(5, "add ITD %p", sitd, 0, 0, 0); 1453 continue; 1454 } 1455 DPRINTFN(10, "addr %p not found", done, 0, 0, 0); 1456 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1457 (u_long)done); 1458 break; 1459 } 1460 1461 DPRINTFN(10, "sdone=%p sidone=%p", sdone, sidone, 0, 0); 1462 DPRINTFN(10, "--- TD dump start ---", 0, 0, 0, 0); 1463 #ifdef OHCI_DEBUG 1464 if (ohcidebug >= 10) { 1465 for (std = sdone; std; std = std->dnext) 1466 ohci_dump_td(sc, std); 1467 } 1468 #endif 1469 DPRINTFN(10, "--- TD dump end ---", 0, 0, 0, 0); 1470 1471 for (std = sdone; std; std = stdnext) { 1472 xfer = std->xfer; 1473 stdnext = std->dnext; 1474 DPRINTFN(10, "std=%p xfer=%p hcpriv=%p dnext=%p", std, xfer, 1475 xfer ? xfer->ux_hcpriv : 0, stdnext); 1476 if (xfer == NULL) { 1477 /* 1478 * xfer == NULL: There seems to be no xfer associated 1479 * with this TD. It is tailp that happened to end up on 1480 * the done queue. 1481 * Shouldn't happen, but some chips are broken(?). 1482 */ 1483 continue; 1484 } 1485 if (std->held == NULL) { 1486 DPRINTFN(10, "std=%p held is null", std, 0, 0, 0); 1487 ohci_hash_rem_td(sc, std); 1488 ohci_free_std_locked(sc, std); 1489 continue; 1490 } 1491 /* 1492 * Make sure the timeout handler didn't run or ran to the end 1493 * and set the transfer status. 1494 */ 1495 callout_halt(&xfer->ux_callout, polling ? NULL : &sc->sc_lock); 1496 1497 if (xfer->ux_status == USBD_CANCELLED || 1498 xfer->ux_status == USBD_TIMEOUT) { 1499 DPRINTF("cancel/timeout %p", xfer, 0, 0, 0); 1500 1501 /* Handled by abort routine. */ 1502 continue; 1503 } 1504 1505 len = std->len; 1506 if (std->td.td_cbp != 0) 1507 len -= O32TOH(std->td.td_be) - 1508 O32TOH(std->td.td_cbp) + 1; 1509 DPRINTFN(10, "len=%d, flags=0x%x", len, std->flags, 0, 0); 1510 if (std->flags & OHCI_ADD_LEN) 1511 xfer->ux_actlen += len; 1512 1513 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1514 if (cc == OHCI_CC_NO_ERROR) { 1515 ohci_hash_rem_td(sc, std); 1516 if (std->flags & OHCI_CALL_DONE) { 1517 xfer->ux_status = USBD_NORMAL_COMPLETION; 1518 usb_transfer_complete(xfer); 1519 } 1520 } else { 1521 /* 1522 * Endpoint is halted. First unlink all the TDs 1523 * belonging to the failed transfer, and then restart 1524 * the endpoint. 1525 */ 1526 ohci_soft_td_t *p, *n; 1527 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1528 1529 DPRINTFN(10, "error cc=%d", cc, 0, 0, 0); 1530 1531 /* remove xfer's TDs from the hash */ 1532 for (p = std; p->xfer == xfer; p = n) { 1533 n = p->nexttd; 1534 ohci_hash_rem_td(sc, p); 1535 } 1536 1537 ohci_soft_ed_t *sed = opipe->sed; 1538 1539 /* clear halt and TD chain */ 1540 sed->ed.ed_headp = HTOO32(p->physaddr); 1541 usb_syncmem(&sed->dma, 1542 sed->offs + offsetof(ohci_ed_t, ed_headp), 1543 sizeof(sed->ed.ed_headp), 1544 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1545 1546 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1547 1548 if (cc == OHCI_CC_DATA_UNDERRUN) 1549 xfer->ux_status = USBD_NORMAL_COMPLETION; 1550 else if (cc == OHCI_CC_STALL) 1551 xfer->ux_status = USBD_STALLED; 1552 else 1553 xfer->ux_status = USBD_IOERROR; 1554 usb_transfer_complete(xfer); 1555 } 1556 } 1557 DPRINTFN(10, "--- ITD dump start ---", 0, 0, 0, 0); 1558 #ifdef OHCI_DEBUG 1559 if (ohcidebug >= 10) { 1560 for (sitd = sidone; sitd; sitd = sitd->dnext) 1561 ohci_dump_itd(sc, sitd); 1562 } 1563 #endif 1564 DPRINTFN(10, "--- ITD dump end ---", 0, 0, 0, 0); 1565 1566 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1567 xfer = sitd->xfer; 1568 sitdnext = sitd->dnext; 1569 DPRINTFN(1, "sitd=%p xfer=%p hcpriv=%p", sitd, xfer, 1570 xfer ? xfer->ux_hcpriv : 0, 0); 1571 if (xfer == NULL) 1572 continue; 1573 if (xfer->ux_status == USBD_CANCELLED || 1574 xfer->ux_status == USBD_TIMEOUT) { 1575 DPRINTF("cancel/timeout %p", xfer, 0, 0, 0); 1576 /* Handled by abort routine. */ 1577 continue; 1578 } 1579 KASSERT(!sitd->isdone); 1580 #ifdef DIAGNOSTIC 1581 sitd->isdone = true; 1582 #endif 1583 if (sitd->flags & OHCI_CALL_DONE) { 1584 ohci_soft_itd_t *next; 1585 1586 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1587 opipe->isoc.inuse -= xfer->ux_nframes; 1588 uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc-> 1589 bEndpointAddress); 1590 xfer->ux_status = USBD_NORMAL_COMPLETION; 1591 actlen = 0; 1592 for (i = 0, sitd = xfer->ux_hcpriv;; 1593 sitd = next) { 1594 next = sitd->nextitd; 1595 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1596 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1597 xfer->ux_status = USBD_IOERROR; 1598 /* For input, update frlengths with actual */ 1599 /* XXX anything necessary for output? */ 1600 if (uedir == UE_DIR_IN && 1601 xfer->ux_status == USBD_NORMAL_COMPLETION) { 1602 iframes = OHCI_ITD_GET_FC(O32TOH( 1603 sitd->itd.itd_flags)); 1604 for (j = 0; j < iframes; i++, j++) { 1605 len = O16TOH(sitd-> 1606 itd.itd_offset[j]); 1607 if ((OHCI_ITD_PSW_GET_CC(len) & 1608 OHCI_CC_NOT_ACCESSED_MASK) 1609 == OHCI_CC_NOT_ACCESSED) 1610 len = 0; 1611 else 1612 len = OHCI_ITD_PSW_LENGTH(len); 1613 xfer->ux_frlengths[i] = len; 1614 actlen += len; 1615 } 1616 } 1617 if (sitd->flags & OHCI_CALL_DONE) 1618 break; 1619 ohci_hash_rem_itd(sc, sitd); 1620 1621 } 1622 ohci_hash_rem_itd(sc, sitd); 1623 if (uedir == UE_DIR_IN && 1624 xfer->ux_status == USBD_NORMAL_COMPLETION) 1625 xfer->ux_actlen = actlen; 1626 xfer->ux_hcpriv = NULL; 1627 1628 usb_transfer_complete(xfer); 1629 } 1630 } 1631 1632 DPRINTFN(10, "done", 0, 0, 0, 0); 1633 } 1634 1635 void 1636 ohci_device_ctrl_done(struct usbd_xfer *xfer) 1637 { 1638 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1639 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1640 int len = UGETW(xfer->ux_request.wLength); 1641 int isread = (xfer->ux_request.bmRequestType & UT_READ); 1642 1643 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1644 DPRINTFN(10, "xfer=%p", xfer, 0, 0, 0); 1645 1646 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1647 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 1648 1649 if (len) 1650 usb_syncmem(&xfer->ux_dmabuf, 0, len, 1651 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1652 usb_syncmem(&opipe->ctrl.reqdma, 0, 1653 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1654 } 1655 1656 void 1657 ohci_device_intr_done(struct usbd_xfer *xfer) 1658 { 1659 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1660 int isread = 1661 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1662 1663 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1664 DPRINTFN(10, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0); 1665 1666 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1667 1668 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1669 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1670 } 1671 1672 void 1673 ohci_device_bulk_done(struct usbd_xfer *xfer) 1674 { 1675 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1676 1677 int isread = 1678 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1679 1680 KASSERT(mutex_owned(&sc->sc_lock)); 1681 1682 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1683 DPRINTFN(10, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0); 1684 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1685 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1686 } 1687 1688 Static void 1689 ohci_rhsc_softint(void *arg) 1690 { 1691 ohci_softc_t *sc = arg; 1692 1693 mutex_enter(&sc->sc_lock); 1694 1695 ohci_rhsc(sc, sc->sc_intrxfer); 1696 1697 /* Do not allow RHSC interrupts > 1 per second */ 1698 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1699 1700 mutex_exit(&sc->sc_lock); 1701 } 1702 1703 void 1704 ohci_rhsc(ohci_softc_t *sc, struct usbd_xfer *xfer) 1705 { 1706 u_char *p; 1707 int i, m; 1708 int hstatus __unused; 1709 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1710 1711 KASSERT(mutex_owned(&sc->sc_lock)); 1712 1713 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1714 DPRINTF("sc=%p xfer=%p hstatus=0x%08x", sc, xfer, hstatus, 0); 1715 1716 if (xfer == NULL) { 1717 /* Just ignore the change. */ 1718 return; 1719 } 1720 1721 p = xfer->ux_buf; 1722 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 1723 memset(p, 0, xfer->ux_length); 1724 for (i = 1; i <= m; i++) { 1725 /* Pick out CHANGE bits from the status reg. */ 1726 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1727 p[i/8] |= 1 << (i%8); 1728 } 1729 DPRINTF("change=0x%02x", *p, 0, 0, 0); 1730 xfer->ux_actlen = xfer->ux_length; 1731 xfer->ux_status = USBD_NORMAL_COMPLETION; 1732 1733 usb_transfer_complete(xfer); 1734 } 1735 1736 void 1737 ohci_root_intr_done(struct usbd_xfer *xfer) 1738 { 1739 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1740 1741 KASSERT(mutex_owned(&sc->sc_lock)); 1742 1743 KASSERT(sc->sc_intrxfer == xfer); 1744 sc->sc_intrxfer = NULL; 1745 } 1746 1747 void 1748 ohci_poll(struct usbd_bus *bus) 1749 { 1750 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1751 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1752 1753 #ifdef OHCI_DEBUG 1754 static int last; 1755 int new; 1756 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1757 if (new != last) { 1758 DPRINTFN(10, "intrs=0x%04x", new, 0, 0, 0); 1759 last = new; 1760 } 1761 #endif 1762 sc->sc_eintrs |= OHCI_WDH; 1763 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1764 mutex_spin_enter(&sc->sc_intr_lock); 1765 ohci_intr1(sc); 1766 mutex_spin_exit(&sc->sc_intr_lock); 1767 } 1768 } 1769 1770 /* 1771 * Add an ED to the schedule. Called with USB lock held. 1772 */ 1773 Static void 1774 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1775 { 1776 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1777 DPRINTFN(8, "sed=%p head=%p", sed, head, 0, 0); 1778 1779 KASSERT(mutex_owned(&sc->sc_lock)); 1780 1781 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1782 sizeof(head->ed.ed_nexted), 1783 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1784 sed->next = head->next; 1785 sed->ed.ed_nexted = head->ed.ed_nexted; 1786 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1787 sizeof(sed->ed.ed_nexted), 1788 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1789 head->next = sed; 1790 head->ed.ed_nexted = HTOO32(sed->physaddr); 1791 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1792 sizeof(head->ed.ed_nexted), 1793 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1794 } 1795 1796 /* 1797 * Remove an ED from the schedule. Called with USB lock held. 1798 */ 1799 Static void 1800 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1801 { 1802 ohci_soft_ed_t *p; 1803 1804 KASSERT(mutex_owned(&sc->sc_lock)); 1805 1806 /* XXX */ 1807 for (p = head; p != NULL && p->next != sed; p = p->next) 1808 ; 1809 KASSERT(p != NULL); 1810 1811 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1812 sizeof(sed->ed.ed_nexted), 1813 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1814 p->next = sed->next; 1815 p->ed.ed_nexted = sed->ed.ed_nexted; 1816 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1817 sizeof(p->ed.ed_nexted), 1818 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1819 } 1820 1821 /* 1822 * When a transfer is completed the TD is added to the done queue by 1823 * the host controller. This queue is the processed by software. 1824 * Unfortunately the queue contains the physical address of the TD 1825 * and we have no simple way to translate this back to a kernel address. 1826 * To make the translation possible (and fast) we use a hash table of 1827 * TDs currently in the schedule. The physical address is used as the 1828 * hash value. 1829 */ 1830 1831 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1832 /* Called with USB lock held. */ 1833 void 1834 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1835 { 1836 int h = HASH(std->physaddr); 1837 1838 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1839 1840 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1841 } 1842 1843 /* Called with USB lock held. */ 1844 void 1845 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1846 { 1847 1848 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1849 1850 LIST_REMOVE(std, hnext); 1851 } 1852 1853 ohci_soft_td_t * 1854 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1855 { 1856 int h = HASH(a); 1857 ohci_soft_td_t *std; 1858 1859 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1860 std != NULL; 1861 std = LIST_NEXT(std, hnext)) 1862 if (std->physaddr == a) 1863 return std; 1864 return NULL; 1865 } 1866 1867 /* Called with USB lock held. */ 1868 void 1869 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1870 { 1871 int h = HASH(sitd->physaddr); 1872 1873 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1874 1875 KASSERT(mutex_owned(&sc->sc_lock)); 1876 1877 DPRINTFN(10, "sitd=%p physaddr=0x%08lx", sitd, (u_long)sitd->physaddr, 1878 0, 0); 1879 1880 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1881 } 1882 1883 /* Called with USB lock held. */ 1884 void 1885 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1886 { 1887 1888 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1889 1890 KASSERT(mutex_owned(&sc->sc_lock)); 1891 1892 DPRINTFN(10, "sitd=%p physaddr=0x%08lx", sitd, (u_long)sitd->physaddr, 1893 0, 0); 1894 1895 LIST_REMOVE(sitd, hnext); 1896 } 1897 1898 ohci_soft_itd_t * 1899 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1900 { 1901 int h = HASH(a); 1902 ohci_soft_itd_t *sitd; 1903 1904 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1905 sitd != NULL; 1906 sitd = LIST_NEXT(sitd, hnext)) 1907 if (sitd->physaddr == a) 1908 return sitd; 1909 return NULL; 1910 } 1911 1912 void 1913 ohci_timeout(void *addr) 1914 { 1915 struct usbd_xfer *xfer = addr; 1916 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1917 bool timeout = false; 1918 1919 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1920 DPRINTF("xfer=%p", xfer, 0, 0, 0); 1921 1922 mutex_enter(&sc->sc_lock); 1923 if (sc->sc_dying) { 1924 ohci_abort_xfer(xfer, USBD_TIMEOUT); 1925 mutex_exit(&sc->sc_lock); 1926 return; 1927 } 1928 1929 if (xfer->ux_status != USBD_CANCELLED) { 1930 xfer->ux_status = USBD_TIMEOUT; 1931 timeout = true; 1932 } 1933 mutex_exit(&sc->sc_lock); 1934 1935 if (timeout) { 1936 /* Execute the abort in a process context. */ 1937 usb_init_task(&xfer->ux_aborttask, ohci_timeout_task, addr, 1938 USB_TASKQ_MPSAFE); 1939 usb_add_task(xfer->ux_pipe->up_dev, &xfer->ux_aborttask, 1940 USB_TASKQ_HC); 1941 } 1942 } 1943 1944 void 1945 ohci_timeout_task(void *addr) 1946 { 1947 struct usbd_xfer *xfer = addr; 1948 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1949 1950 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1951 1952 DPRINTF("xfer=%p", xfer, 0, 0, 0); 1953 1954 mutex_enter(&sc->sc_lock); 1955 ohci_abort_xfer(xfer, USBD_TIMEOUT); 1956 mutex_exit(&sc->sc_lock); 1957 } 1958 1959 #ifdef OHCI_DEBUG 1960 void 1961 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 1962 { 1963 for (; std; std = std->nexttd) { 1964 ohci_dump_td(sc, std); 1965 KASSERTMSG(std->nexttd == NULL || std != std->nexttd, 1966 "std %p next %p", std, std->nexttd); 1967 } 1968 } 1969 1970 void 1971 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1972 { 1973 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1974 1975 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1976 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1977 1978 uint32_t flags = O32TOH(std->td.td_flags); 1979 DPRINTF("TD(%p) at 0x%08lx:", std, (u_long)std->physaddr, 0, 0); 1980 DPRINTF(" round=%d DP=%x DI=%x T=%x", 1981 !!(flags & OHCI_TD_R), 1982 __SHIFTOUT(flags, OHCI_TD_DP_MASK), 1983 OHCI_TD_GET_DI(flags), 1984 __SHIFTOUT(flags, OHCI_TD_TOGGLE_MASK)); 1985 DPRINTF(" EC=%d CC=%d", OHCI_TD_GET_EC(flags), OHCI_TD_GET_CC(flags), 1986 0, 0); 1987 DPRINTF(" td_cbp=0x%08lx td_nexttd=0x%08lx td_be=0x%08lx", 1988 (u_long)O32TOH(std->td.td_cbp), 1989 (u_long)O32TOH(std->td.td_nexttd), 1990 (u_long)O32TOH(std->td.td_be), 0); 1991 } 1992 1993 void 1994 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1995 { 1996 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1997 1998 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1999 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2000 2001 uint32_t flags = O32TOH(sitd->itd.itd_flags); 2002 DPRINTF("ITD(%p) at 0x%08lx", sitd, (u_long)sitd->physaddr, 0, 0); 2003 DPRINTF(" sf=%d di=%d fc=%d cc=%d", 2004 OHCI_ITD_GET_SF(flags), OHCI_ITD_GET_DI(flags), 2005 OHCI_ITD_GET_FC(flags), OHCI_ITD_GET_CC(flags)); 2006 DPRINTF(" bp0=0x%08x next=0x%08x be=0x%08x", 2007 O32TOH(sitd->itd.itd_bp0), 2008 O32TOH(sitd->itd.itd_nextitd), 2009 O32TOH(sitd->itd.itd_be), 0); 2010 CTASSERT(OHCI_ITD_NOFFSET == 8); 2011 DPRINTF(" offs[0] = 0x%04x offs[1] = 0x%04x " 2012 "offs[2] = 0x%04x offs[3] = 0x%04x", 2013 O16TOH(sitd->itd.itd_offset[0]), 2014 O16TOH(sitd->itd.itd_offset[1]), 2015 O16TOH(sitd->itd.itd_offset[2]), 2016 O16TOH(sitd->itd.itd_offset[3])); 2017 DPRINTF(" offs[4] = 0x%04x offs[5] = 0x%04x " 2018 "offs[6] = 0x%04x offs[7] = 0x%04x", 2019 O16TOH(sitd->itd.itd_offset[4]), 2020 O16TOH(sitd->itd.itd_offset[5]), 2021 O16TOH(sitd->itd.itd_offset[6]), 2022 O16TOH(sitd->itd.itd_offset[7])); 2023 } 2024 2025 void 2026 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2027 { 2028 for (; sitd; sitd = sitd->nextitd) 2029 ohci_dump_itd(sc, sitd); 2030 } 2031 2032 void 2033 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2034 { 2035 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2036 2037 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2038 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2039 2040 uint32_t flags = O32TOH(sed->ed.ed_flags); 2041 DPRINTF("ED(%p) at 0x%08lx:", sed, sed->physaddr, 0, 0); 2042 DPRINTF(" addr=%d endpt=%d maxp=%d", 2043 OHCI_ED_GET_FA(flags), 2044 OHCI_ED_GET_EN(flags), 2045 OHCI_ED_GET_MAXP(flags), 2046 0); 2047 DPRINTF(" dir=%d speed=%d skip=%d iso=%d", 2048 __SHIFTOUT(flags, OHCI_ED_DIR_MASK), 2049 !!(flags & OHCI_ED_SPEED), 2050 !!(flags & OHCI_ED_SKIP), 2051 !!(flags & OHCI_ED_FORMAT_ISO)); 2052 DPRINTF(" tailp=0x%08lx", (u_long)O32TOH(sed->ed.ed_tailp), 2053 0, 0, 0); 2054 DPRINTF(" headp=0x%08lx nexted=0x%08lx halted=%d carry=%d", 2055 O32TOH(sed->ed.ed_headp), O32TOH(sed->ed.ed_nexted), 2056 !!(O32TOH(sed->ed.ed_headp) & OHCI_HALTED), 2057 !!(O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 2058 } 2059 #endif 2060 2061 usbd_status 2062 ohci_open(struct usbd_pipe *pipe) 2063 { 2064 struct usbd_device *dev = pipe->up_dev; 2065 struct usbd_bus *bus = dev->ud_bus; 2066 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2067 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 2068 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2069 uint8_t addr = dev->ud_addr; 2070 uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2071 ohci_soft_ed_t *sed; 2072 ohci_soft_td_t *std; 2073 ohci_soft_itd_t *sitd; 2074 ohci_physaddr_t tdphys; 2075 uint32_t fmt; 2076 usbd_status err = USBD_NOMEM; 2077 int ival; 2078 2079 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2080 DPRINTFN(1, "pipe=%p, addr=%d, endpt=%d (%d)", pipe, addr, 2081 ed->bEndpointAddress, bus->ub_rhaddr); 2082 2083 if (sc->sc_dying) { 2084 return USBD_IOERROR; 2085 } 2086 2087 std = NULL; 2088 sed = NULL; 2089 2090 if (addr == bus->ub_rhaddr) { 2091 switch (ed->bEndpointAddress) { 2092 case USB_CONTROL_ENDPOINT: 2093 pipe->up_methods = &roothub_ctrl_methods; 2094 break; 2095 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 2096 pipe->up_methods = &ohci_root_intr_methods; 2097 break; 2098 default: 2099 err = USBD_INVAL; 2100 goto bad; 2101 } 2102 } else { 2103 sed = ohci_alloc_sed(sc); 2104 if (sed == NULL) 2105 goto bad; 2106 opipe->sed = sed; 2107 if (xfertype == UE_ISOCHRONOUS) { 2108 sitd = ohci_alloc_sitd(sc); 2109 if (sitd == NULL) 2110 goto bad; 2111 2112 opipe->tail.itd = sitd; 2113 sitd->held = &opipe->tail.itd; 2114 tdphys = sitd->physaddr; 2115 fmt = OHCI_ED_FORMAT_ISO; 2116 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2117 fmt |= OHCI_ED_DIR_IN; 2118 else 2119 fmt |= OHCI_ED_DIR_OUT; 2120 } else { 2121 std = ohci_alloc_std(sc); 2122 if (std == NULL) 2123 goto bad; 2124 2125 opipe->tail.td = std; 2126 std->held = &opipe->tail.td; 2127 tdphys = std->physaddr; 2128 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2129 } 2130 sed->ed.ed_flags = HTOO32( 2131 OHCI_ED_SET_FA(addr) | 2132 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2133 (dev->ud_speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2134 fmt | 2135 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2136 sed->ed.ed_headp = HTOO32(tdphys | 2137 (pipe->up_endpoint->ue_toggle ? OHCI_TOGGLECARRY : 0)); 2138 sed->ed.ed_tailp = HTOO32(tdphys); 2139 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2140 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2141 2142 switch (xfertype) { 2143 case UE_CONTROL: 2144 pipe->up_methods = &ohci_device_ctrl_methods; 2145 err = usb_allocmem(&sc->sc_bus, 2146 sizeof(usb_device_request_t), 2147 0, &opipe->ctrl.reqdma); 2148 if (err) 2149 goto bad; 2150 mutex_enter(&sc->sc_lock); 2151 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2152 mutex_exit(&sc->sc_lock); 2153 break; 2154 case UE_INTERRUPT: 2155 pipe->up_methods = &ohci_device_intr_methods; 2156 ival = pipe->up_interval; 2157 if (ival == USBD_DEFAULT_INTERVAL) 2158 ival = ed->bInterval; 2159 err = ohci_device_setintr(sc, opipe, ival); 2160 if (err) 2161 goto bad; 2162 break; 2163 case UE_ISOCHRONOUS: 2164 pipe->up_serialise = false; 2165 pipe->up_methods = &ohci_device_isoc_methods; 2166 return ohci_setup_isoc(pipe); 2167 case UE_BULK: 2168 pipe->up_methods = &ohci_device_bulk_methods; 2169 mutex_enter(&sc->sc_lock); 2170 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2171 mutex_exit(&sc->sc_lock); 2172 break; 2173 } 2174 } 2175 2176 return USBD_NORMAL_COMPLETION; 2177 2178 bad: 2179 if (std != NULL) { 2180 ohci_free_std(sc, std); 2181 } 2182 if (sed != NULL) 2183 ohci_free_sed(sc, sed); 2184 return err; 2185 2186 } 2187 2188 /* 2189 * Close a reqular pipe. 2190 * Assumes that there are no pending transactions. 2191 */ 2192 void 2193 ohci_close_pipe(struct usbd_pipe *pipe, ohci_soft_ed_t *head) 2194 { 2195 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2196 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2197 ohci_soft_ed_t *sed = opipe->sed; 2198 2199 KASSERT(mutex_owned(&sc->sc_lock)); 2200 2201 #ifdef DIAGNOSTIC 2202 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2203 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2204 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2205 ohci_soft_td_t *std; 2206 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2207 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2208 "tl=0x%x pipe=%p, std=%p\n", sed, 2209 (int)O32TOH(sed->ed.ed_headp), 2210 (int)O32TOH(sed->ed.ed_tailp), 2211 pipe, std); 2212 #ifdef OHCI_DEBUG 2213 usbd_dump_pipe(&opipe->pipe); 2214 ohci_dump_ed(sc, sed); 2215 if (std) 2216 ohci_dump_td(sc, std); 2217 #endif 2218 usb_delay_ms(&sc->sc_bus, 2); 2219 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2220 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2221 printf("ohci_close_pipe: pipe still not empty\n"); 2222 } 2223 #endif 2224 ohci_rem_ed(sc, sed, head); 2225 /* Make sure the host controller is not touching this ED */ 2226 usb_delay_ms(&sc->sc_bus, 1); 2227 pipe->up_endpoint->ue_toggle = 2228 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2229 ohci_free_sed_locked(sc, opipe->sed); 2230 } 2231 2232 /* 2233 * Cancel or timeout a device request. We have two cases to deal with 2234 * 2235 * 1) A driver wants to stop scheduled or inflight transfers 2236 * 2) A transfer has timed out 2237 * 2238 * It's impossible to guarantee that the requested transfer will not 2239 * have (partially) happened since the hardware runs concurrently. 2240 * 2241 * Transfer state is protected by the bus lock and we set the transfer status 2242 * as soon as either of the above happens (with bus lock held). 2243 * 2244 * Then we arrange for the hardware to tells us that it is not still 2245 * processing the TDs by setting the sKip bit and requesting a SOF interrupt 2246 * 2247 * Once we see the SOF interrupt we can check the transfer TDs/iTDs to see if 2248 * they've been processed and either 2249 * a) if they're unused recover them for later use, or 2250 * b) if they've been used allocate new TD/iTDs to replace those 2251 * used. The softint handler will free the old ones. 2252 */ 2253 void 2254 ohci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2255 { 2256 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2257 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2258 ohci_soft_ed_t *sed = opipe->sed; 2259 ohci_soft_td_t *p, *n; 2260 ohci_physaddr_t headp; 2261 int hit; 2262 int wake; 2263 2264 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2265 DPRINTF("xfer=%p pipe=%p sed=%p", xfer, opipe,sed, 0); 2266 2267 KASSERT(mutex_owned(&sc->sc_lock)); 2268 ASSERT_SLEEPABLE(); 2269 2270 if (sc->sc_dying) { 2271 /* If we're dying, just do the software part. */ 2272 KASSERT(xfer->ux_status == status); 2273 callout_halt(&xfer->ux_callout, &sc->sc_lock); 2274 usb_transfer_complete(xfer); 2275 return; 2276 } 2277 2278 /* 2279 * If an abort is already in progress then just wait for it to 2280 * complete and return. 2281 */ 2282 if (xfer->ux_hcflags & UXFER_ABORTING) { 2283 DPRINTFN(2, "already aborting", 0, 0, 0, 0); 2284 #ifdef DIAGNOSTIC 2285 if (status == USBD_TIMEOUT) 2286 printf("%s: TIMEOUT while aborting\n", __func__); 2287 #endif 2288 /* Override the status which might be USBD_TIMEOUT. */ 2289 xfer->ux_status = status; 2290 DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0); 2291 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2292 while (xfer->ux_hcflags & UXFER_ABORTING) 2293 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2294 goto done; 2295 } 2296 xfer->ux_hcflags |= UXFER_ABORTING; 2297 2298 /* 2299 * Step 1: When cancelling a transfer make sure the timeout handler 2300 * didn't run or ran to the end and saw the USBD_CANCELLED status. 2301 * Otherwise we must have got here via a timeout. 2302 */ 2303 if (status == USBD_CANCELLED) { 2304 xfer->ux_status = status; 2305 callout_halt(&xfer->ux_callout, &sc->sc_lock); 2306 } else { 2307 KASSERT(xfer->ux_status == USBD_TIMEOUT); 2308 } 2309 2310 /* 2311 * Step 2: Unless the endpoint is already halted, we set the endpoint 2312 * descriptor sKip bit and wait for hardware to complete processing. 2313 * 2314 * This includes ensuring that any TDs of the transfer that got onto 2315 * the done list are also removed. We ensure this by waiting for 2316 * both a WDH and SOF interrupt. 2317 */ 2318 DPRINTFN(1, "stop ed=%p", sed, 0, 0, 0); 2319 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2320 sizeof(sed->ed.ed_flags), 2321 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2322 if (!(sed->ed.ed_flags & OHCI_HALTED)) { 2323 /* force hardware skip */ 2324 DPRINTFN(1, "pausing ed=%p", sed, 0, 0, 0); 2325 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2326 usb_syncmem(&sed->dma, 2327 sed->offs + offsetof(ohci_ed_t, ed_flags), 2328 sizeof(sed->ed.ed_flags), 2329 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2330 2331 DPRINTFN(10, "WDH %p xfer %p", sc, xfer, 0, 0); 2332 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2333 ox->ox_abintrs = OHCI_SF; 2334 TAILQ_INSERT_TAIL(&sc->sc_abortingxfers, ox, ox_abnext); 2335 2336 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_SF); 2337 sc->sc_eintrs |= OHCI_SF; 2338 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_SF); 2339 /* 2340 * Step 2: Wait until we know hardware has finished any possible 2341 * use of the xfer. 2342 */ 2343 while (ox->ox_abintrs != 0) { 2344 DPRINTFN(10, "WDH %p xfer %p intrs %#x", sc, xfer, 2345 ox->ox_abintrs, 0); 2346 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2347 } 2348 } else { 2349 DPRINTFN(1, "halted ed=%p", sed, 0, 0, 0); 2350 } 2351 2352 /* 2353 * Step 3: Remove any vestiges of the xfer from the hardware. 2354 * The complication here is that the hardware may have executed 2355 * beyond the xfer we're trying to abort. So as we're scanning 2356 * the TDs of this xfer we check if the hardware points to 2357 * any of them. 2358 */ 2359 p = xfer->ux_hcpriv; 2360 KASSERT(p); 2361 2362 #ifdef OHCI_DEBUG 2363 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2364 2365 if (ohcidebug >= 2) { 2366 DPRINTF("sed:", 0, 0, 0, 0); 2367 ohci_dump_ed(sc, sed); 2368 ohci_dump_tds(sc, p); 2369 } 2370 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2371 #endif 2372 2373 #define OHCI_CC_ACCESSED_P(x) \ 2374 (((x) & OHCI_CC_NOT_ACCESSED_MASK) != OHCI_CC_NOT_ACCESSED) 2375 2376 2377 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2378 hit = 0; 2379 for (; p->xfer == xfer; p = n) { 2380 hit |= headp == p->physaddr; 2381 n = p->nexttd; 2382 2383 int cc = OHCI_TD_GET_CC(O32TOH(p->td.td_flags)); 2384 if (!OHCI_CC_ACCESSED_P(cc)) { 2385 ohci_hash_rem_td(sc, p); 2386 continue; 2387 } 2388 DPRINTFN(10, "std=%p has been touched by HC", p, 0, 0, 0); 2389 2390 mutex_exit(&sc->sc_lock); 2391 ohci_soft_td_t *std = ohci_alloc_std(sc); 2392 if (std == NULL) { 2393 /* XXX What to do??? */ 2394 panic("hmm"); 2395 } 2396 mutex_enter(&sc->sc_lock); 2397 2398 DPRINTFN(10, "new std=%p now held at %p", std, p->held, 0, 0); 2399 *(p->held) = std; 2400 std->held = p->held; 2401 std->xfer = xfer; 2402 p->held = NULL; 2403 } 2404 /* Zap headp register if hardware pointed inside the xfer. */ 2405 if (hit) { 2406 DPRINTFN(1, "set hd=0x%08x, tl=0x%08x", (int)p->physaddr, 2407 (int)O32TOH(sed->ed.ed_tailp), 0, 0); 2408 sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */ 2409 usb_syncmem(&sed->dma, 2410 sed->offs + offsetof(ohci_ed_t, ed_headp), 2411 sizeof(sed->ed.ed_headp), 2412 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2413 } else { 2414 DPRINTFN(1, "no hit", 0, 0, 0, 0); 2415 } 2416 2417 /* 2418 * Step 4: Turn on hardware again. 2419 */ 2420 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2421 sizeof(sed->ed.ed_flags), 2422 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2423 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2424 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2425 sizeof(sed->ed.ed_flags), 2426 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2427 2428 /* 2429 * Step 5: Execute callback. 2430 */ 2431 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2432 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2433 usb_transfer_complete(xfer); 2434 if (wake) 2435 cv_broadcast(&xfer->ux_hccv); 2436 2437 done: 2438 KASSERT(mutex_owned(&sc->sc_lock)); 2439 } 2440 2441 /* 2442 * Data structures and routines to emulate the root hub. 2443 */ 2444 Static int 2445 ohci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2446 void *buf, int buflen) 2447 { 2448 ohci_softc_t *sc = OHCI_BUS2SC(bus); 2449 usb_port_status_t ps; 2450 uint16_t len, value, index; 2451 int l, totlen = 0; 2452 int port, i; 2453 uint32_t v; 2454 2455 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2456 2457 if (sc->sc_dying) 2458 return -1; 2459 2460 DPRINTFN(4, "type=0x%02x request=%02x", req->bmRequestType, 2461 req->bRequest, 0, 0); 2462 2463 len = UGETW(req->wLength); 2464 value = UGETW(req->wValue); 2465 index = UGETW(req->wIndex); 2466 2467 #define C(x,y) ((x) | ((y) << 8)) 2468 switch (C(req->bRequest, req->bmRequestType)) { 2469 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2470 DPRINTFN(8, "wValue=0x%04x", value, 0, 0, 0); 2471 if (len == 0) 2472 break; 2473 switch (value) { 2474 case C(0, UDESC_DEVICE): { 2475 usb_device_descriptor_t devd; 2476 2477 totlen = min(buflen, sizeof(devd)); 2478 memcpy(&devd, buf, totlen); 2479 USETW(devd.idVendor, sc->sc_id_vendor); 2480 memcpy(buf, &devd, totlen); 2481 break; 2482 } 2483 case C(1, UDESC_STRING): 2484 #define sd ((usb_string_descriptor_t *)buf) 2485 /* Vendor */ 2486 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2487 break; 2488 case C(2, UDESC_STRING): 2489 /* Product */ 2490 totlen = usb_makestrdesc(sd, len, "OHCI root hub"); 2491 break; 2492 #undef sd 2493 default: 2494 /* default from usbroothub */ 2495 return buflen; 2496 } 2497 break; 2498 2499 /* Hub requests */ 2500 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2501 break; 2502 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2503 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 2504 index, value, 0, 0); 2505 if (index < 1 || index > sc->sc_noport) { 2506 return -1; 2507 } 2508 port = OHCI_RH_PORT_STATUS(index); 2509 switch(value) { 2510 case UHF_PORT_ENABLE: 2511 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2512 break; 2513 case UHF_PORT_SUSPEND: 2514 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2515 break; 2516 case UHF_PORT_POWER: 2517 /* Yes, writing to the LOW_SPEED bit clears power. */ 2518 OWRITE4(sc, port, UPS_LOW_SPEED); 2519 break; 2520 case UHF_C_PORT_CONNECTION: 2521 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2522 break; 2523 case UHF_C_PORT_ENABLE: 2524 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2525 break; 2526 case UHF_C_PORT_SUSPEND: 2527 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2528 break; 2529 case UHF_C_PORT_OVER_CURRENT: 2530 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2531 break; 2532 case UHF_C_PORT_RESET: 2533 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2534 break; 2535 default: 2536 return -1; 2537 } 2538 switch(value) { 2539 case UHF_C_PORT_CONNECTION: 2540 case UHF_C_PORT_ENABLE: 2541 case UHF_C_PORT_SUSPEND: 2542 case UHF_C_PORT_OVER_CURRENT: 2543 case UHF_C_PORT_RESET: 2544 /* Enable RHSC interrupt if condition is cleared. */ 2545 if ((OREAD4(sc, port) >> 16) == 0) 2546 ohci_rhsc_enable(sc); 2547 break; 2548 default: 2549 break; 2550 } 2551 break; 2552 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2553 if (len == 0) 2554 break; 2555 if ((value & 0xff) != 0) { 2556 return -1; 2557 } 2558 usb_hub_descriptor_t hubd; 2559 2560 totlen = min(buflen, sizeof(hubd)); 2561 memcpy(&hubd, buf, totlen); 2562 2563 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2564 hubd.bNbrPorts = sc->sc_noport; 2565 USETW(hubd.wHubCharacteristics, 2566 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2567 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2568 /* XXX overcurrent */ 2569 ); 2570 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2571 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2572 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2573 hubd.DeviceRemovable[i++] = (uint8_t)v; 2574 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2575 totlen = min(totlen, hubd.bDescLength); 2576 memcpy(buf, &hubd, totlen); 2577 break; 2578 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2579 if (len != 4) { 2580 return -1; 2581 } 2582 memset(buf, 0, len); /* ? XXX */ 2583 totlen = len; 2584 break; 2585 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2586 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 2587 if (index < 1 || index > sc->sc_noport) { 2588 return -1; 2589 } 2590 if (len != 4) { 2591 return -1; 2592 } 2593 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2594 DPRINTFN(8, "port status=0x%04x", v, 0, 0, 0); 2595 USETW(ps.wPortStatus, v); 2596 USETW(ps.wPortChange, v >> 16); 2597 totlen = min(len, sizeof(ps)); 2598 memcpy(buf, &ps, totlen); 2599 break; 2600 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2601 return -1; 2602 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2603 break; 2604 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2605 if (index < 1 || index > sc->sc_noport) { 2606 return -1; 2607 } 2608 port = OHCI_RH_PORT_STATUS(index); 2609 switch(value) { 2610 case UHF_PORT_ENABLE: 2611 OWRITE4(sc, port, UPS_PORT_ENABLED); 2612 break; 2613 case UHF_PORT_SUSPEND: 2614 OWRITE4(sc, port, UPS_SUSPEND); 2615 break; 2616 case UHF_PORT_RESET: 2617 DPRINTFN(5, "reset port %d", index, 0, 0, 0); 2618 OWRITE4(sc, port, UPS_RESET); 2619 for (i = 0; i < 5; i++) { 2620 usb_delay_ms(&sc->sc_bus, 2621 USB_PORT_ROOT_RESET_DELAY); 2622 if (sc->sc_dying) { 2623 return -1; 2624 } 2625 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2626 break; 2627 } 2628 DPRINTFN(8, "port %d reset, status = 0x%04x", index, 2629 OREAD4(sc, port), 0, 0); 2630 break; 2631 case UHF_PORT_POWER: 2632 DPRINTFN(2, "set port power %d", index, 0, 0, 0); 2633 OWRITE4(sc, port, UPS_PORT_POWER); 2634 break; 2635 default: 2636 return -1; 2637 } 2638 break; 2639 default: 2640 /* default from usbroothub */ 2641 return buflen; 2642 } 2643 2644 return totlen; 2645 } 2646 2647 Static usbd_status 2648 ohci_root_intr_transfer(struct usbd_xfer *xfer) 2649 { 2650 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2651 usbd_status err; 2652 2653 /* Insert last in queue. */ 2654 mutex_enter(&sc->sc_lock); 2655 err = usb_insert_transfer(xfer); 2656 mutex_exit(&sc->sc_lock); 2657 if (err) 2658 return err; 2659 2660 /* Pipe isn't running, start first */ 2661 return ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2662 } 2663 2664 Static usbd_status 2665 ohci_root_intr_start(struct usbd_xfer *xfer) 2666 { 2667 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2668 2669 if (sc->sc_dying) 2670 return USBD_IOERROR; 2671 2672 mutex_enter(&sc->sc_lock); 2673 KASSERT(sc->sc_intrxfer == NULL); 2674 sc->sc_intrxfer = xfer; 2675 mutex_exit(&sc->sc_lock); 2676 2677 return USBD_IN_PROGRESS; 2678 } 2679 2680 /* Abort a root interrupt request. */ 2681 Static void 2682 ohci_root_intr_abort(struct usbd_xfer *xfer) 2683 { 2684 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2685 2686 KASSERT(mutex_owned(&sc->sc_lock)); 2687 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2688 2689 sc->sc_intrxfer = NULL; 2690 2691 xfer->ux_status = USBD_CANCELLED; 2692 usb_transfer_complete(xfer); 2693 } 2694 2695 /* Close the root pipe. */ 2696 Static void 2697 ohci_root_intr_close(struct usbd_pipe *pipe) 2698 { 2699 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2700 2701 KASSERT(mutex_owned(&sc->sc_lock)); 2702 2703 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2704 2705 sc->sc_intrxfer = NULL; 2706 } 2707 2708 /************************/ 2709 2710 int 2711 ohci_device_ctrl_init(struct usbd_xfer *xfer) 2712 { 2713 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2714 usb_device_request_t *req = &xfer->ux_request; 2715 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2716 ohci_soft_td_t *stat, *setup; 2717 int isread = req->bmRequestType & UT_READ; 2718 int len = xfer->ux_bufsize; 2719 int err = ENOMEM; 2720 2721 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2722 2723 setup = ohci_alloc_std(sc); 2724 if (setup == NULL) { 2725 goto bad1; 2726 } 2727 stat = ohci_alloc_std(sc); 2728 if (stat == NULL) { 2729 goto bad2; 2730 } 2731 2732 ox->ox_setup = setup; 2733 ox->ox_stat = stat; 2734 ox->ox_nstd = 0; 2735 setup->held = &ox->ox_setup; 2736 stat->held = &ox->ox_stat; 2737 2738 DPRINTFN(10, "xfer=%p setup=%p held at %p", ox, setup, setup->held, 0); 2739 DPRINTFN(10, "xfer=%p stat= %p held at %p", ox, stat, stat->held, 0); 2740 2741 /* Set up data transaction */ 2742 if (len != 0) { 2743 err = ohci_alloc_std_chain(sc, xfer, len, isread); 2744 if (err) { 2745 goto bad3; 2746 } 2747 } 2748 return 0; 2749 2750 bad3: 2751 ohci_free_std(sc, stat); 2752 bad2: 2753 ohci_free_std(sc, setup); 2754 bad1: 2755 return err; 2756 } 2757 2758 void 2759 ohci_device_ctrl_fini(struct usbd_xfer *xfer) 2760 { 2761 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2762 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2763 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2764 2765 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2766 DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0); 2767 2768 mutex_enter(&sc->sc_lock); 2769 if (ox->ox_setup != opipe->tail.td) { 2770 ohci_free_std_locked(sc, ox->ox_setup); 2771 } 2772 for (size_t i = 0; i < ox->ox_nstd; i++) { 2773 ohci_soft_td_t *std = ox->ox_stds[i]; 2774 if (std == NULL) 2775 break; 2776 ohci_free_std_locked(sc, std); 2777 } 2778 ohci_free_std_locked(sc, ox->ox_stat); 2779 mutex_exit(&sc->sc_lock); 2780 2781 if (ox->ox_nstd) { 2782 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 2783 kmem_free(ox->ox_stds, sz); 2784 } 2785 } 2786 2787 Static usbd_status 2788 ohci_device_ctrl_transfer(struct usbd_xfer *xfer) 2789 { 2790 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2791 usbd_status err; 2792 2793 /* Insert last in queue. */ 2794 mutex_enter(&sc->sc_lock); 2795 err = usb_insert_transfer(xfer); 2796 mutex_exit(&sc->sc_lock); 2797 if (err) 2798 return err; 2799 2800 /* Pipe isn't running, start first */ 2801 return ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2802 } 2803 2804 Static usbd_status 2805 ohci_device_ctrl_start(struct usbd_xfer *xfer) 2806 { 2807 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2808 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2809 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2810 usb_device_request_t *req = &xfer->ux_request; 2811 struct usbd_device *dev __diagused = opipe->pipe.up_dev; 2812 ohci_soft_td_t *setup, *stat, *next, *tail; 2813 ohci_soft_ed_t *sed; 2814 int isread; 2815 int len; 2816 2817 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2818 2819 if (sc->sc_dying) 2820 return USBD_IOERROR; 2821 2822 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2823 2824 isread = req->bmRequestType & UT_READ; 2825 len = UGETW(req->wLength); 2826 2827 DPRINTF("xfer=%p len=%d, addr=%d, endpt=%d", xfer, len, dev->ud_addr, 2828 opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress); 2829 DPRINTF("type=0x%02x, request=0x%02x, wValue=0x%04x, wIndex=0x%04x", 2830 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2831 UGETW(req->wIndex)); 2832 2833 /* Need to take lock here for pipe->tail.td */ 2834 mutex_enter(&sc->sc_lock); 2835 2836 /* 2837 * Use the pipe "tail" TD as our first and loan our first TD to the 2838 * next transfer 2839 */ 2840 setup = opipe->tail.td; 2841 opipe->tail.td = ox->ox_setup; 2842 ox->ox_setup = setup; 2843 setup->held = &ox->ox_setup; 2844 2845 DPRINTFN(10, "xfer=%p new setup=%p held at %p", ox, setup, setup->held, 0); 2846 2847 stat = ox->ox_stat; 2848 2849 /* point at sentinel */ 2850 tail = opipe->tail.td; 2851 tail->held = &opipe->tail.td; 2852 sed = opipe->sed; 2853 2854 DPRINTFN(10, "xfer=%p new tail=%p held at %p", ox, tail, tail->held, 0); 2855 2856 KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->ud_addr, 2857 "address ED %d pipe %d\n", 2858 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->ud_addr); 2859 KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) == 2860 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 2861 "MPL ED %d pipe %d\n", 2862 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), 2863 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 2864 2865 /* next will point to data if len != 0 */ 2866 next = stat; 2867 2868 /* Set up data transaction */ 2869 if (len != 0) { 2870 ohci_soft_td_t *std; 2871 ohci_soft_td_t *end; 2872 2873 next = ox->ox_stds[0]; 2874 ohci_reset_std_chain(sc, xfer, len, isread, next, &end); 2875 2876 end->td.td_nexttd = HTOO32(stat->physaddr); 2877 end->nexttd = stat; 2878 2879 usb_syncmem(&end->dma, 2880 end->offs + offsetof(ohci_td_t, td_nexttd), 2881 sizeof(end->td.td_nexttd), 2882 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2883 2884 usb_syncmem(&xfer->ux_dmabuf, 0, len, 2885 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2886 std = ox->ox_stds[0]; 2887 /* Start toggle at 1 and then use the carried toggle. */ 2888 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 2889 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 2890 usb_syncmem(&std->dma, 2891 std->offs + offsetof(ohci_td_t, td_flags), 2892 sizeof(std->td.td_flags), 2893 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2894 } 2895 2896 DPRINTFN(8, "setup %p data %p stat %p tail %p", setup, 2897 (len != 0 ? ox->ox_stds[0] : NULL), stat, tail); 2898 KASSERT(opipe->tail.td == tail); 2899 2900 memcpy(KERNADDR(&opipe->ctrl.reqdma, 0), req, sizeof(*req)); 2901 usb_syncmem(&opipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2902 2903 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 2904 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 2905 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->ctrl.reqdma, 0)); 2906 setup->td.td_nexttd = HTOO32(next->physaddr); 2907 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof(*req) - 1); 2908 setup->nexttd = next; 2909 setup->len = 0; 2910 setup->xfer = xfer; 2911 setup->flags = 0; 2912 ohci_hash_add_td(sc, setup); 2913 2914 xfer->ux_hcpriv = setup; 2915 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2916 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2917 2918 stat->td.td_flags = HTOO32( 2919 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 2920 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 2921 stat->td.td_cbp = 0; 2922 stat->td.td_nexttd = HTOO32(tail->physaddr); 2923 stat->td.td_be = 0; 2924 stat->nexttd = tail; 2925 stat->flags = OHCI_CALL_DONE; 2926 stat->len = 0; 2927 stat->xfer = xfer; 2928 ohci_hash_add_td(sc, stat); 2929 2930 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2931 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2932 2933 memset(&tail->td, 0, sizeof(tail->td)); 2934 tail->nexttd = NULL; 2935 tail->xfer = NULL; 2936 2937 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 2938 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2939 2940 #ifdef OHCI_DEBUG 2941 USBHIST_LOGN(ohcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2942 if (ohcidebug >= 5) { 2943 ohci_dump_ed(sc, sed); 2944 ohci_dump_tds(sc, setup); 2945 } 2946 USBHIST_LOGN(ohcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2947 #endif 2948 2949 /* Insert ED in schedule */ 2950 sed->ed.ed_tailp = HTOO32(tail->physaddr); 2951 usb_syncmem(&sed->dma, 2952 sed->offs + offsetof(ohci_ed_t, ed_tailp), 2953 sizeof(sed->ed.ed_tailp), 2954 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2955 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2956 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2957 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2958 ohci_timeout, xfer); 2959 } 2960 2961 DPRINTF("done", 0, 0, 0, 0); 2962 2963 mutex_exit(&sc->sc_lock); 2964 2965 return USBD_IN_PROGRESS; 2966 } 2967 2968 /* Abort a device control request. */ 2969 Static void 2970 ohci_device_ctrl_abort(struct usbd_xfer *xfer) 2971 { 2972 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 2973 2974 KASSERT(mutex_owned(&sc->sc_lock)); 2975 2976 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2977 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2978 ohci_abort_xfer(xfer, USBD_CANCELLED); 2979 } 2980 2981 /* Close a device control pipe. */ 2982 Static void 2983 ohci_device_ctrl_close(struct usbd_pipe *pipe) 2984 { 2985 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2986 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2987 2988 KASSERT(mutex_owned(&sc->sc_lock)); 2989 2990 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2991 DPRINTF("pipe=%p", pipe, 0, 0, 0); 2992 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2993 ohci_free_std_locked(sc, opipe->tail.td); 2994 } 2995 2996 /************************/ 2997 2998 Static void 2999 ohci_device_clear_toggle(struct usbd_pipe *pipe) 3000 { 3001 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3002 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3003 3004 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 3005 } 3006 3007 Static void 3008 ohci_noop(struct usbd_pipe *pipe) 3009 { 3010 } 3011 3012 Static int 3013 ohci_device_bulk_init(struct usbd_xfer *xfer) 3014 { 3015 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3016 int len = xfer->ux_bufsize; 3017 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;; 3018 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3019 int err; 3020 3021 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3022 3023 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3024 3025 DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread, 3026 xfer->ux_flags); 3027 DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0); 3028 3029 /* Allocate a chain of new TDs (including a new tail). */ 3030 err = ohci_alloc_std_chain(sc, xfer, len, isread); 3031 if (err) 3032 return err; 3033 3034 return 0; 3035 } 3036 3037 Static void 3038 ohci_device_bulk_fini(struct usbd_xfer *xfer) 3039 { 3040 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3041 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3042 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3043 3044 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3045 DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0); 3046 3047 mutex_enter(&sc->sc_lock); 3048 for (size_t i = 0; i < ox->ox_nstd; i++) { 3049 ohci_soft_td_t *std = ox->ox_stds[i]; 3050 if (std == NULL) 3051 break; 3052 if (std != opipe->tail.td) 3053 ohci_free_std_locked(sc, std); 3054 } 3055 mutex_exit(&sc->sc_lock); 3056 3057 if (ox->ox_nstd) { 3058 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 3059 kmem_free(ox->ox_stds, sz); 3060 } 3061 } 3062 3063 Static usbd_status 3064 ohci_device_bulk_transfer(struct usbd_xfer *xfer) 3065 { 3066 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3067 usbd_status err; 3068 3069 /* Insert last in queue. */ 3070 mutex_enter(&sc->sc_lock); 3071 err = usb_insert_transfer(xfer); 3072 mutex_exit(&sc->sc_lock); 3073 if (err) 3074 return err; 3075 3076 /* Pipe isn't running, start first */ 3077 return ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3078 } 3079 3080 Static usbd_status 3081 ohci_device_bulk_start(struct usbd_xfer *xfer) 3082 { 3083 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3084 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3085 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3086 ohci_soft_td_t *last; 3087 ohci_soft_td_t *data, *tail, *tdp; 3088 ohci_soft_ed_t *sed; 3089 int len, isread, endpt; 3090 3091 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3092 3093 if (sc->sc_dying) 3094 return USBD_IOERROR; 3095 3096 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3097 3098 len = xfer->ux_length; 3099 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3100 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3101 sed = opipe->sed; 3102 3103 DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread, 3104 xfer->ux_flags); 3105 DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0); 3106 3107 mutex_enter(&sc->sc_lock); 3108 3109 /* 3110 * Use the pipe "tail" TD as our first and loan our first TD to the 3111 * next transfer 3112 */ 3113 data = opipe->tail.td; 3114 opipe->tail.td = ox->ox_stds[0]; 3115 ox->ox_stds[0] = data; 3116 data->held = &ox->ox_stds[0]; 3117 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3118 DPRINTFN(10, "xfer=%p new data=%p held at %p", ox, data, data->held, 0); 3119 3120 /* point at sentinel */ 3121 tail = opipe->tail.td; 3122 memset(&tail->td, 0, sizeof(tail->td)); 3123 tail->held = &opipe->tail.td; 3124 tail->nexttd = NULL; 3125 tail->xfer = NULL; 3126 DPRINTFN(10, "xfer=%p new tail=%p held at %p", ox, tail, tail->held, 0); 3127 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3128 BUS_DMASYNC_PREWRITE); 3129 xfer->ux_hcpriv = data; 3130 3131 DPRINTFN(8, "xfer %p data %p tail %p", xfer, ox->ox_stds[0], tail, 0); 3132 KASSERT(opipe->tail.td == tail); 3133 3134 /* We want interrupt at the end of the transfer. */ 3135 last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3136 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3137 last->td.td_nexttd = HTOO32(tail->physaddr); 3138 last->nexttd = tail; 3139 last->flags |= OHCI_CALL_DONE; 3140 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3141 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3142 3143 DPRINTFN(4, "ed_flags=0x%08x td_flags=0x%08x " 3144 "td_cbp=0x%08x td_be=0x%08x", 3145 (int)O32TOH(sed->ed.ed_flags), 3146 (int)O32TOH(data->td.td_flags), 3147 (int)O32TOH(data->td.td_cbp), 3148 (int)O32TOH(data->td.td_be)); 3149 3150 #ifdef OHCI_DEBUG 3151 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3152 if (ohcidebug >= 5) { 3153 ohci_dump_ed(sc, sed); 3154 ohci_dump_tds(sc, data); 3155 } 3156 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3157 #endif 3158 3159 /* Insert ED in schedule */ 3160 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3161 KASSERT(tdp->xfer == xfer); 3162 } 3163 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3164 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3165 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3166 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3167 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3168 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3169 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3170 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3171 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3172 ohci_timeout, xfer); 3173 } 3174 mutex_exit(&sc->sc_lock); 3175 3176 return USBD_IN_PROGRESS; 3177 } 3178 3179 Static void 3180 ohci_device_bulk_abort(struct usbd_xfer *xfer) 3181 { 3182 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3183 3184 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3185 3186 KASSERT(mutex_owned(&sc->sc_lock)); 3187 3188 DPRINTF("xfer=%p", xfer, 0, 0, 0); 3189 ohci_abort_xfer(xfer, USBD_CANCELLED); 3190 } 3191 3192 /* 3193 * Close a device bulk pipe. 3194 */ 3195 Static void 3196 ohci_device_bulk_close(struct usbd_pipe *pipe) 3197 { 3198 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3199 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3200 3201 KASSERT(mutex_owned(&sc->sc_lock)); 3202 3203 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3204 3205 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3206 ohci_close_pipe(pipe, sc->sc_bulk_head); 3207 ohci_free_std_locked(sc, opipe->tail.td); 3208 } 3209 3210 /************************/ 3211 3212 Static int 3213 ohci_device_intr_init(struct usbd_xfer *xfer) 3214 { 3215 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3216 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3217 int len = xfer->ux_bufsize; 3218 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;; 3219 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3220 int err; 3221 3222 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3223 3224 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3225 KASSERT(len != 0); 3226 3227 DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread, 3228 xfer->ux_flags); 3229 DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0); 3230 3231 ox->ox_nstd = 0; 3232 3233 err = ohci_alloc_std_chain(sc, xfer, len, isread); 3234 if (err) { 3235 return err; 3236 } 3237 3238 return 0; 3239 } 3240 3241 Static void 3242 ohci_device_intr_fini(struct usbd_xfer *xfer) 3243 { 3244 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3245 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3246 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3247 3248 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3249 DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0); 3250 3251 mutex_enter(&sc->sc_lock); 3252 for (size_t i = 0; i < ox->ox_nstd; i++) { 3253 ohci_soft_td_t *std = ox->ox_stds[i]; 3254 if (std != NULL) 3255 break; 3256 if (std != opipe->tail.td) 3257 ohci_free_std_locked(sc, std); 3258 } 3259 mutex_exit(&sc->sc_lock); 3260 3261 if (ox->ox_nstd) { 3262 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 3263 kmem_free(ox->ox_stds, sz); 3264 } 3265 } 3266 3267 Static usbd_status 3268 ohci_device_intr_transfer(struct usbd_xfer *xfer) 3269 { 3270 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3271 usbd_status err; 3272 3273 /* Insert last in queue. */ 3274 mutex_enter(&sc->sc_lock); 3275 err = usb_insert_transfer(xfer); 3276 mutex_exit(&sc->sc_lock); 3277 if (err) 3278 return err; 3279 3280 /* Pipe isn't running, start first */ 3281 return ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3282 } 3283 3284 Static usbd_status 3285 ohci_device_intr_start(struct usbd_xfer *xfer) 3286 { 3287 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3288 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3289 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3290 ohci_soft_ed_t *sed = opipe->sed; 3291 ohci_soft_td_t *data, *last, *tail; 3292 int len, isread, endpt; 3293 3294 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3295 3296 if (sc->sc_dying) 3297 return USBD_IOERROR; 3298 3299 DPRINTFN(3, "xfer=%p len=%d flags=%d priv=%p", xfer, xfer->ux_length, 3300 xfer->ux_flags, xfer->ux_priv); 3301 3302 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3303 3304 len = xfer->ux_length; 3305 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3306 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3307 3308 mutex_enter(&sc->sc_lock); 3309 3310 /* 3311 * Use the pipe "tail" TD as our first and loan our first TD to the 3312 * next transfer. 3313 */ 3314 data = opipe->tail.td; 3315 opipe->tail.td = ox->ox_stds[0]; 3316 ox->ox_stds[0] = data; 3317 data->held = &ox->ox_stds[0]; 3318 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3319 DPRINTFN(10, "xfer=%p new data=%p held at %p", ox, data, data->held, 0); 3320 3321 /* point at sentinel */ 3322 tail = opipe->tail.td; 3323 memset(&tail->td, 0, sizeof(tail->td)); 3324 tail->held = &opipe->tail.td; 3325 tail->nexttd = NULL; 3326 tail->xfer = NULL; 3327 DPRINTFN(10, "xfer=%p new tail=%p held at %p", ox, tail, tail->held, 0); 3328 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3329 BUS_DMASYNC_PREWRITE); 3330 xfer->ux_hcpriv = data; 3331 3332 DPRINTFN(8, "data %p tail %p", ox->ox_stds[0], tail, 0, 0); 3333 KASSERT(opipe->tail.td == tail); 3334 3335 /* We want interrupt at the end of the transfer. */ 3336 last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3337 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3338 3339 last->td.td_nexttd = HTOO32(tail->physaddr); 3340 last->nexttd = tail; 3341 last->flags |= OHCI_CALL_DONE; 3342 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3343 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3344 3345 #ifdef OHCI_DEBUG 3346 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3347 if (ohcidebug >= 5) { 3348 ohci_dump_ed(sc, sed); 3349 ohci_dump_tds(sc, data); 3350 } 3351 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3352 #endif 3353 3354 /* Insert ED in schedule */ 3355 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3356 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3357 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3358 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3359 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3360 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3361 3362 mutex_exit(&sc->sc_lock); 3363 3364 return USBD_IN_PROGRESS; 3365 } 3366 3367 /* Abort a device interrupt request. */ 3368 Static void 3369 ohci_device_intr_abort(struct usbd_xfer *xfer) 3370 { 3371 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3372 3373 KASSERT(mutex_owned(&sc->sc_lock)); 3374 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3375 3376 ohci_abort_xfer(xfer, USBD_CANCELLED); 3377 } 3378 3379 /* Close a device interrupt pipe. */ 3380 Static void 3381 ohci_device_intr_close(struct usbd_pipe *pipe) 3382 { 3383 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3384 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3385 int nslots = opipe->intr.nslots; 3386 int pos = opipe->intr.pos; 3387 int j; 3388 ohci_soft_ed_t *p, *sed = opipe->sed; 3389 3390 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3391 3392 KASSERT(mutex_owned(&sc->sc_lock)); 3393 3394 DPRINTFN(1, "pipe=%p nslots=%d pos=%d", pipe, nslots, pos, 0); 3395 usb_syncmem(&sed->dma, sed->offs, 3396 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3397 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3398 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3399 sizeof(sed->ed.ed_flags), 3400 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3401 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3402 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3403 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3404 3405 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3406 continue; 3407 KASSERT(p); 3408 p->next = sed->next; 3409 p->ed.ed_nexted = sed->ed.ed_nexted; 3410 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3411 sizeof(p->ed.ed_nexted), 3412 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3413 3414 for (j = 0; j < nslots; j++) 3415 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3416 3417 ohci_free_std_locked(sc, opipe->tail.td); 3418 ohci_free_sed_locked(sc, opipe->sed); 3419 } 3420 3421 Static usbd_status 3422 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3423 { 3424 int i, j, best; 3425 u_int npoll, slow, shigh, nslots; 3426 u_int bestbw, bw; 3427 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3428 3429 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3430 3431 DPRINTFN(2, "pipe=%p", opipe, 0, 0, 0); 3432 if (ival == 0) { 3433 printf("ohci_setintr: 0 interval\n"); 3434 return USBD_INVAL; 3435 } 3436 3437 npoll = OHCI_NO_INTRS; 3438 while (npoll > ival) 3439 npoll /= 2; 3440 DPRINTFN(2, "ival=%d npoll=%d", ival, npoll, 0, 0); 3441 3442 /* 3443 * We now know which level in the tree the ED must go into. 3444 * Figure out which slot has most bandwidth left over. 3445 * Slots to examine: 3446 * npoll 3447 * 1 0 3448 * 2 1 2 3449 * 4 3 4 5 6 3450 * 8 7 8 9 10 11 12 13 14 3451 * N (N-1) .. (N-1+N-1) 3452 */ 3453 slow = npoll-1; 3454 shigh = slow + npoll; 3455 nslots = OHCI_NO_INTRS / npoll; 3456 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3457 bw = 0; 3458 for (j = 0; j < nslots; j++) 3459 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3460 if (bw < bestbw) { 3461 best = i; 3462 bestbw = bw; 3463 } 3464 } 3465 DPRINTFN(2, "best=%d(%d..%d) bestbw=%d", best, slow, shigh, bestbw); 3466 3467 mutex_enter(&sc->sc_lock); 3468 hsed = sc->sc_eds[best]; 3469 sed->next = hsed->next; 3470 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3471 sizeof(hsed->ed.ed_flags), 3472 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3473 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3474 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3475 sizeof(sed->ed.ed_flags), 3476 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3477 hsed->next = sed; 3478 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3479 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3480 sizeof(hsed->ed.ed_flags), 3481 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3482 mutex_exit(&sc->sc_lock); 3483 3484 for (j = 0; j < nslots; j++) 3485 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3486 opipe->intr.nslots = nslots; 3487 opipe->intr.pos = best; 3488 3489 DPRINTFN(5, "returns %p", opipe, 0, 0, 0); 3490 return USBD_NORMAL_COMPLETION; 3491 } 3492 3493 /***********************/ 3494 3495 Static int 3496 ohci_device_isoc_init(struct usbd_xfer *xfer) 3497 { 3498 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3499 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3500 ohci_soft_itd_t *sitd; 3501 size_t i; 3502 int err; 3503 3504 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3505 3506 DPRINTFN(1, "xfer %p len %d flags %d", xfer, xfer->ux_length, 3507 xfer->ux_flags, 0); 3508 3509 const size_t nfsitd = 3510 (xfer->ux_nframes + OHCI_ITD_NOFFSET - 1) / OHCI_ITD_NOFFSET; 3511 const size_t nbsitd = xfer->ux_bufsize / OHCI_PAGE_SIZE; 3512 const size_t nsitd = MAX(nfsitd, nbsitd) + 1; 3513 3514 ox->ox_sitds = kmem_zalloc(sizeof(ohci_soft_itd_t *) * nsitd, 3515 KM_SLEEP); 3516 ox->ox_nsitd = nsitd; 3517 3518 for (i = 0; i < nsitd; i++) { 3519 /* Allocate next ITD */ 3520 sitd = ohci_alloc_sitd(sc); 3521 if (sitd == NULL) { 3522 err = ENOMEM; 3523 goto fail; 3524 } 3525 ox->ox_sitds[i] = sitd; 3526 sitd->held = &ox->ox_sitds[i]; 3527 sitd->xfer = xfer; 3528 sitd->flags = 0; 3529 // DPRINTFN(10, "xfer=%p new tail=%p held at %p", ox, tail, tail->held, 0); 3530 } 3531 3532 return 0; 3533 fail: 3534 for (; i > 0;) { 3535 ohci_free_sitd(sc, ox->ox_sitds[--i]); 3536 } 3537 return err; 3538 } 3539 3540 Static void 3541 ohci_device_isoc_fini(struct usbd_xfer *xfer) 3542 { 3543 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3544 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3545 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3546 3547 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3548 3549 mutex_enter(&sc->sc_lock); 3550 for (size_t i = 0; i < ox->ox_nsitd; i++) { 3551 if (ox->ox_sitds[i] != opipe->tail.itd) { 3552 ohci_free_sitd_locked(sc, ox->ox_sitds[i]); 3553 } 3554 } 3555 mutex_exit(&sc->sc_lock); 3556 3557 if (ox->ox_nsitd) { 3558 const size_t sz = sizeof(ohci_soft_itd_t *) * ox->ox_nsitd; 3559 kmem_free(ox->ox_sitds, sz); 3560 } 3561 } 3562 3563 3564 usbd_status 3565 ohci_device_isoc_transfer(struct usbd_xfer *xfer) 3566 { 3567 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3568 usbd_status __diagused err; 3569 3570 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3571 3572 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 3573 3574 /* Put it on our queue, */ 3575 mutex_enter(&sc->sc_lock); 3576 err = usb_insert_transfer(xfer); 3577 mutex_exit(&sc->sc_lock); 3578 3579 KASSERT(err == USBD_NORMAL_COMPLETION); 3580 3581 /* insert into schedule, */ 3582 ohci_device_isoc_enter(xfer); 3583 3584 /* and start if the pipe wasn't running */ 3585 return USBD_IN_PROGRESS; 3586 } 3587 3588 void 3589 ohci_device_isoc_enter(struct usbd_xfer *xfer) 3590 { 3591 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3592 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3593 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3594 ohci_soft_ed_t *sed = opipe->sed; 3595 ohci_soft_itd_t *sitd, *nsitd, *tail; 3596 ohci_physaddr_t buf, offs, noffs, bp0; 3597 int i, ncur, nframes; 3598 3599 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3600 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 3601 3602 mutex_enter(&sc->sc_lock); 3603 3604 if (sc->sc_dying) { 3605 mutex_exit(&sc->sc_lock); 3606 return; 3607 } 3608 3609 struct isoc *isoc = &opipe->isoc; 3610 3611 DPRINTFN(1, "used=%d next=%d xfer=%p nframes=%d", 3612 isoc->inuse, isoc->next, xfer, xfer->ux_nframes); 3613 3614 if (isoc->next == -1) { 3615 /* Not in use yet, schedule it a few frames ahead. */ 3616 isoc->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3617 DPRINTFN(2,"start next=%d", isoc->next, 0, 0, 0); 3618 } 3619 3620 sitd = opipe->tail.itd; 3621 opipe->tail.itd = ox->ox_sitds[0]; 3622 ox->ox_sitds[0] = sitd; 3623 sitd->held = &ox->ox_sitds[0]; 3624 3625 buf = DMAADDR(&xfer->ux_dmabuf, 0); 3626 bp0 = OHCI_PAGE(buf); 3627 offs = OHCI_PAGE_OFFSET(buf); 3628 nframes = xfer->ux_nframes; 3629 xfer->ux_hcpriv = sitd; 3630 size_t j = 1; 3631 for (i = ncur = 0; i < nframes; i++, ncur++) { 3632 noffs = offs + xfer->ux_frlengths[i]; 3633 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3634 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3635 3636 /* Allocate next ITD */ 3637 nsitd = ox->ox_sitds[j++]; 3638 KASSERT(nsitd != NULL); 3639 KASSERT(j < ox->ox_nsitd); 3640 3641 /* Fill current ITD */ 3642 sitd->itd.itd_flags = HTOO32( 3643 OHCI_ITD_NOCC | 3644 OHCI_ITD_SET_SF(isoc->next) | 3645 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3646 OHCI_ITD_SET_FC(ncur)); 3647 sitd->itd.itd_bp0 = HTOO32(bp0); 3648 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3649 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3650 sitd->nextitd = nsitd; 3651 sitd->xfer = xfer; 3652 sitd->flags = 0; 3653 #ifdef DIAGNOSTIC 3654 sitd->isdone = false; 3655 #endif 3656 ohci_hash_add_itd(sc, sitd); 3657 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3658 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3659 3660 sitd = nsitd; 3661 isoc->next = isoc->next + ncur; 3662 bp0 = OHCI_PAGE(buf + offs); 3663 ncur = 0; 3664 } 3665 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3666 offs = noffs; 3667 } 3668 KASSERT(j <= ox->ox_nsitd); 3669 3670 /* point at sentinel */ 3671 tail = opipe->tail.itd; 3672 memset(&tail->itd, 0, sizeof(tail->itd)); 3673 tail->held = &opipe->tail.itd; 3674 tail->nextitd = NULL; 3675 tail->xfer = NULL; 3676 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->itd), 3677 BUS_DMASYNC_PREWRITE); 3678 3679 /* Fixup last used ITD */ 3680 sitd->itd.itd_flags = HTOO32( 3681 OHCI_ITD_NOCC | 3682 OHCI_ITD_SET_SF(isoc->next) | 3683 OHCI_ITD_SET_DI(0) | 3684 OHCI_ITD_SET_FC(ncur)); 3685 sitd->itd.itd_bp0 = HTOO32(bp0); 3686 sitd->itd.itd_nextitd = HTOO32(tail->physaddr); 3687 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3688 sitd->nextitd = tail; 3689 sitd->xfer = xfer; 3690 sitd->flags = OHCI_CALL_DONE; 3691 #ifdef DIAGNOSTIC 3692 sitd->isdone = false; 3693 #endif 3694 ohci_hash_add_itd(sc, sitd); 3695 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3696 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3697 3698 isoc->next = isoc->next + ncur; 3699 isoc->inuse += nframes; 3700 3701 /* XXX pretend we did it all */ 3702 xfer->ux_actlen = offs; 3703 xfer->ux_status = USBD_IN_PROGRESS; 3704 3705 #ifdef OHCI_DEBUG 3706 if (ohcidebug >= 5) { 3707 DPRINTF("frame=%d", O32TOH(sc->sc_hcca->hcca_frame_number), 3708 0, 0, 0); 3709 ohci_dump_itds(sc, xfer->ux_hcpriv); 3710 ohci_dump_ed(sc, sed); 3711 } 3712 #endif 3713 3714 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3715 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3716 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3717 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3718 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3719 sizeof(sed->ed.ed_flags), 3720 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3721 mutex_exit(&sc->sc_lock); 3722 } 3723 3724 void 3725 ohci_device_isoc_abort(struct usbd_xfer *xfer) 3726 { 3727 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3728 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3729 ohci_soft_ed_t *sed; 3730 ohci_soft_itd_t *sitd; 3731 3732 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3733 DPRINTFN(1, "xfer=%p", xfer, 0, 0, 0); 3734 3735 KASSERT(mutex_owned(&sc->sc_lock)); 3736 3737 /* Transfer is already done. */ 3738 if (xfer->ux_status != USBD_NOT_STARTED && 3739 xfer->ux_status != USBD_IN_PROGRESS) { 3740 printf("ohci_device_isoc_abort: early return\n"); 3741 goto done; 3742 } 3743 3744 /* Give xfer the requested abort code. */ 3745 xfer->ux_status = USBD_CANCELLED; 3746 3747 sed = opipe->sed; 3748 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3749 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3750 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3751 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3752 sizeof(sed->ed.ed_flags), 3753 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3754 3755 sitd = xfer->ux_hcpriv; 3756 KASSERT(sitd); 3757 3758 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3759 3760 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3761 ohci_hash_rem_itd(sc, sitd); 3762 #ifdef DIAGNOSTIC 3763 DPRINTFN(1, "abort sets done sitd=%p", sitd, 0, 0, 0); 3764 sitd->isdone = true; 3765 #endif 3766 } 3767 3768 /* Run callback. */ 3769 usb_transfer_complete(xfer); 3770 3771 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3772 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3773 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3774 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3775 3776 done: 3777 KASSERT(mutex_owned(&sc->sc_lock)); 3778 } 3779 3780 void 3781 ohci_device_isoc_done(struct usbd_xfer *xfer) 3782 { 3783 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3784 DPRINTFN(1, "xfer=%p", xfer, 0, 0, 0); 3785 } 3786 3787 usbd_status 3788 ohci_setup_isoc(struct usbd_pipe *pipe) 3789 { 3790 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3791 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3792 struct isoc *isoc = &opipe->isoc; 3793 3794 isoc->next = -1; 3795 isoc->inuse = 0; 3796 3797 mutex_enter(&sc->sc_lock); 3798 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3799 mutex_exit(&sc->sc_lock); 3800 3801 return USBD_NORMAL_COMPLETION; 3802 } 3803 3804 void 3805 ohci_device_isoc_close(struct usbd_pipe *pipe) 3806 { 3807 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3808 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3809 3810 KASSERT(mutex_owned(&sc->sc_lock)); 3811 3812 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3813 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3814 ohci_close_pipe(pipe, sc->sc_isoc_head); 3815 #ifdef DIAGNOSTIC 3816 opipe->tail.itd->isdone = true; 3817 #endif 3818 ohci_free_sitd_locked(sc, opipe->tail.itd); 3819 } 3820
Indexes created Fri Oct 03 02:09:57 GMT 2025