ohci.c revision 1.26
1 /* $NetBSD: ohci.c,v 1.26 1999/01/13 10:08:59 augustss Exp $ */ 2 3 /* 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (augustss (at) carlstedt.se) at 9 * Carlstedt Research & Technology. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * USB Open Host Controller driver. 42 * 43 * OHCI spec: http://www.intel.com/design/usb/ohci11d.pdf 44 * USB spec: http://www.teleport.com/cgi-bin/mailmerge.cgi/~usb/cgiform.tpl 45 */ 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/malloc.h> 51 #if defined(__NetBSD__) 52 #include <sys/device.h> 53 #elif defined(__FreeBSD__) 54 #include <sys/module.h> 55 #include <sys/bus.h> 56 #endif 57 #include <sys/proc.h> 58 #include <sys/queue.h> 59 #include <sys/select.h> 60 61 #include <machine/bus.h> 62 #include <machine/endian.h> 63 64 #include <dev/usb/usb.h> 65 #include <dev/usb/usbdi.h> 66 #include <dev/usb/usbdivar.h> 67 #include <dev/usb/usb_quirks.h> 68 #include <dev/usb/usb_mem.h> 69 70 #include <dev/usb/ohcireg.h> 71 #include <dev/usb/ohcivar.h> 72 73 #if defined(__FreeBSD__) 74 #include <machine/clock.h> 75 76 #define delay(d) DELAY(d) 77 78 #endif 79 80 /* 81 * The OHCI controller is little endian, so on big endian machines 82 * the data strored in memory needs to be swapped. 83 */ 84 #if BYTE_ORDER == BIG_ENDIAN 85 #define LE(x) (bswap32(x)) 86 #else 87 #define LE(x) (x) 88 #endif 89 90 struct ohci_pipe; 91 92 ohci_soft_ed_t *ohci_alloc_sed __P((ohci_softc_t *)); 93 void ohci_free_sed __P((ohci_softc_t *, ohci_soft_ed_t *)); 94 95 ohci_soft_td_t *ohci_alloc_std __P((ohci_softc_t *)); 96 void ohci_free_std __P((ohci_softc_t *, ohci_soft_td_t *)); 97 98 usbd_status ohci_open __P((usbd_pipe_handle)); 99 void ohci_poll __P((struct usbd_bus *)); 100 void ohci_waitintr __P((ohci_softc_t *, usbd_request_handle)); 101 void ohci_rhsc __P((ohci_softc_t *, usbd_request_handle)); 102 void ohci_process_done __P((ohci_softc_t *, ohci_physaddr_t)); 103 void ohci_ii_done __P((ohci_softc_t *, usbd_request_handle)); 104 void ohci_ctrl_done __P((ohci_softc_t *, usbd_request_handle)); 105 void ohci_intr_done __P((ohci_softc_t *, usbd_request_handle)); 106 void ohci_bulk_done __P((ohci_softc_t *, usbd_request_handle)); 107 108 usbd_status ohci_device_request __P((usbd_request_handle reqh)); 109 void ohci_add_ed __P((ohci_soft_ed_t *, ohci_soft_ed_t *)); 110 void ohci_rem_ed __P((ohci_soft_ed_t *, ohci_soft_ed_t *)); 111 void ohci_hash_add_td __P((ohci_softc_t *, ohci_soft_td_t *)); 112 void ohci_hash_rem_td __P((ohci_softc_t *, ohci_soft_td_t *)); 113 ohci_soft_td_t *ohci_hash_find_td __P((ohci_softc_t *, ohci_physaddr_t)); 114 115 usbd_status ohci_root_ctrl_transfer __P((usbd_request_handle)); 116 usbd_status ohci_root_ctrl_start __P((usbd_request_handle)); 117 void ohci_root_ctrl_abort __P((usbd_request_handle)); 118 void ohci_root_ctrl_close __P((usbd_pipe_handle)); 119 120 usbd_status ohci_root_intr_transfer __P((usbd_request_handle)); 121 usbd_status ohci_root_intr_start __P((usbd_request_handle)); 122 void ohci_root_intr_abort __P((usbd_request_handle)); 123 void ohci_root_intr_close __P((usbd_pipe_handle)); 124 125 usbd_status ohci_device_ctrl_transfer __P((usbd_request_handle)); 126 usbd_status ohci_device_ctrl_start __P((usbd_request_handle)); 127 void ohci_device_ctrl_abort __P((usbd_request_handle)); 128 void ohci_device_ctrl_close __P((usbd_pipe_handle)); 129 130 usbd_status ohci_device_bulk_transfer __P((usbd_request_handle)); 131 usbd_status ohci_device_bulk_start __P((usbd_request_handle)); 132 void ohci_device_bulk_abort __P((usbd_request_handle)); 133 void ohci_device_bulk_close __P((usbd_pipe_handle)); 134 135 usbd_status ohci_device_intr_transfer __P((usbd_request_handle)); 136 usbd_status ohci_device_intr_start __P((usbd_request_handle)); 137 void ohci_device_intr_abort __P((usbd_request_handle)); 138 void ohci_device_intr_close __P((usbd_pipe_handle)); 139 usbd_status ohci_device_setintr __P((ohci_softc_t *sc, 140 struct ohci_pipe *pipe, int ival)); 141 142 int ohci_str __P((usb_string_descriptor_t *, int, char *)); 143 144 void ohci_timeout __P((void *)); 145 void ohci_rhsc_able __P((ohci_softc_t *, int)); 146 147 #ifdef USB_DEBUG 148 ohci_softc_t *thesc; 149 void ohci_dumpregs __P((ohci_softc_t *)); 150 void ohci_dump_tds __P((ohci_soft_td_t *)); 151 void ohci_dump_td __P((ohci_soft_td_t *)); 152 void ohci_dump_ed __P((ohci_soft_ed_t *)); 153 #endif 154 155 #if defined(__NetBSD__) 156 #define OWRITE4(sc, r, x) bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)) 157 #define OREAD4(sc, r) bus_space_read_4((sc)->iot, (sc)->ioh, (r)) 158 #define OREAD2(sc, r) bus_space_read_2((sc)->iot, (sc)->ioh, (r)) 159 #elif defined(__FreeBSD__) 160 #define OWRITE4(sc, r, x) *(unsigned int *) ((sc)->sc_iobase + (r)) = x 161 #define OREAD4(sc, r) (*(unsigned int *) ((sc)->sc_iobase + (r))) 162 #define OREAD2(sc, r) (*(unsigned short *) ((sc)->sc_iobase + (r))) 163 #endif 164 165 /* Reverse the bits in a value 0 .. 31 */ 166 static u_int8_t revbits[OHCI_NO_INTRS] = 167 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 168 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 169 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 170 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 171 172 struct ohci_pipe { 173 struct usbd_pipe pipe; 174 ohci_soft_ed_t *sed; 175 ohci_soft_td_t *tail; 176 /* Info needed for different pipe kinds. */ 177 union { 178 /* Control pipe */ 179 struct { 180 usb_dma_t datadma; 181 usb_dma_t reqdma; 182 u_int length; 183 ohci_soft_td_t *setup, *xfer, *stat; 184 } ctl; 185 /* Interrupt pipe */ 186 struct { 187 usb_dma_t datadma; 188 int nslots; 189 int pos; 190 } intr; 191 /* Bulk pipe */ 192 struct { 193 usb_dma_t datadma; 194 u_int length; 195 } bulk; 196 } u; 197 }; 198 199 #define OHCI_INTR_ENDPT 1 200 201 struct usbd_methods ohci_root_ctrl_methods = { 202 ohci_root_ctrl_transfer, 203 ohci_root_ctrl_start, 204 ohci_root_ctrl_abort, 205 ohci_root_ctrl_close, 206 0, 207 }; 208 209 struct usbd_methods ohci_root_intr_methods = { 210 ohci_root_intr_transfer, 211 ohci_root_intr_start, 212 ohci_root_intr_abort, 213 ohci_root_intr_close, 214 0, 215 }; 216 217 struct usbd_methods ohci_device_ctrl_methods = { 218 ohci_device_ctrl_transfer, 219 ohci_device_ctrl_start, 220 ohci_device_ctrl_abort, 221 ohci_device_ctrl_close, 222 0, 223 }; 224 225 struct usbd_methods ohci_device_intr_methods = { 226 ohci_device_intr_transfer, 227 ohci_device_intr_start, 228 ohci_device_intr_abort, 229 ohci_device_intr_close, 230 }; 231 232 struct usbd_methods ohci_device_bulk_methods = { 233 ohci_device_bulk_transfer, 234 ohci_device_bulk_start, 235 ohci_device_bulk_abort, 236 ohci_device_bulk_close, 237 0, 238 }; 239 240 ohci_soft_ed_t * 241 ohci_alloc_sed(sc) 242 ohci_softc_t *sc; 243 { 244 ohci_soft_ed_t *sed; 245 usbd_status r; 246 int i, offs; 247 usb_dma_t dma; 248 249 if (!sc->sc_freeeds) { 250 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n")); 251 sed = malloc(sizeof(ohci_soft_ed_t) * OHCI_ED_CHUNK, 252 M_USBDEV, M_NOWAIT); 253 if (!sed) 254 return 0; 255 r = usb_allocmem(sc->sc_dmatag, OHCI_ED_SIZE * OHCI_ED_CHUNK, 256 OHCI_ED_ALIGN, &dma); 257 if (r != USBD_NORMAL_COMPLETION) { 258 free(sed, M_USBDEV); 259 return 0; 260 } 261 for(i = 0; i < OHCI_ED_CHUNK; i++, sed++) { 262 offs = i * OHCI_ED_SIZE; 263 sed->physaddr = DMAADDR(&dma) + offs; 264 sed->ed = (ohci_ed_t *) 265 ((char *)KERNADDR(&dma) + offs); 266 sed->next = sc->sc_freeeds; 267 sc->sc_freeeds = sed; 268 } 269 } 270 sed = sc->sc_freeeds; 271 sc->sc_freeeds = sed->next; 272 memset(sed->ed, 0, OHCI_ED_SIZE); 273 sed->next = 0; 274 return sed; 275 } 276 277 void 278 ohci_free_sed(sc, sed) 279 ohci_softc_t *sc; 280 ohci_soft_ed_t *sed; 281 { 282 sed->next = sc->sc_freeeds; 283 sc->sc_freeeds = sed; 284 } 285 286 ohci_soft_td_t * 287 ohci_alloc_std(sc) 288 ohci_softc_t *sc; 289 { 290 ohci_soft_td_t *std; 291 usbd_status r; 292 int i, offs; 293 usb_dma_t dma; 294 295 if (!sc->sc_freetds) { 296 DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n")); 297 std = malloc(sizeof(ohci_soft_td_t) * OHCI_TD_CHUNK, 298 M_USBDEV, M_NOWAIT); 299 if (!std) 300 return 0; 301 r = usb_allocmem(sc->sc_dmatag, OHCI_TD_SIZE * OHCI_TD_CHUNK, 302 OHCI_TD_ALIGN, &dma); 303 if (r != USBD_NORMAL_COMPLETION) { 304 free(std, M_USBDEV); 305 return 0; 306 } 307 for(i = 0; i < OHCI_TD_CHUNK; i++, std++) { 308 offs = i * OHCI_TD_SIZE; 309 std->physaddr = DMAADDR(&dma) + offs; 310 std->td = (ohci_td_t *) 311 ((char *)KERNADDR(&dma) + offs); 312 std->nexttd = sc->sc_freetds; 313 sc->sc_freetds = std; 314 } 315 } 316 std = sc->sc_freetds; 317 sc->sc_freetds = std->nexttd; 318 memset(std->td, 0, OHCI_TD_SIZE); 319 std->nexttd = 0; 320 return (std); 321 } 322 323 void 324 ohci_free_std(sc, std) 325 ohci_softc_t *sc; 326 ohci_soft_td_t *std; 327 { 328 std->nexttd = sc->sc_freetds; 329 sc->sc_freetds = std; 330 } 331 332 usbd_status 333 ohci_init(sc) 334 ohci_softc_t *sc; 335 { 336 ohci_soft_ed_t *sed, *psed; 337 usbd_status r; 338 int rev; 339 int i; 340 u_int32_t s, ctl, ival, hcr, fm, per; 341 342 DPRINTF(("ohci_init: start\n")); 343 rev = OREAD4(sc, OHCI_REVISION); 344 printf("%s: OHCI version %d.%d%s\n", USBDEVNAME(sc->sc_bus.bdev), 345 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 346 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 347 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 348 printf("%s: unsupported OHCI revision\n", 349 USBDEVNAME(sc->sc_bus.bdev)); 350 return (USBD_INVAL); 351 } 352 353 for (i = 0; i < OHCI_HASH_SIZE; i++) 354 LIST_INIT(&sc->sc_hash_tds[i]); 355 356 /* Allocate the HCCA area. */ 357 r = usb_allocmem(sc->sc_dmatag, OHCI_HCCA_SIZE, 358 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 359 if (r != USBD_NORMAL_COMPLETION) 360 return (r); 361 sc->sc_hcca = (struct ohci_hcca *)KERNADDR(&sc->sc_hccadma); 362 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 363 364 sc->sc_eintrs = OHCI_NORMAL_INTRS; 365 366 sc->sc_ctrl_head = ohci_alloc_sed(sc); 367 if (!sc->sc_ctrl_head) { 368 r = USBD_NOMEM; 369 goto bad1; 370 } 371 sc->sc_ctrl_head->ed->ed_flags |= LE(OHCI_ED_SKIP); 372 sc->sc_bulk_head = ohci_alloc_sed(sc); 373 if (!sc->sc_bulk_head) { 374 r = USBD_NOMEM; 375 goto bad2; 376 } 377 sc->sc_bulk_head->ed->ed_flags |= LE(OHCI_ED_SKIP); 378 379 /* Allocate all the dummy EDs that make up the interrupt tree. */ 380 for (i = 0; i < OHCI_NO_EDS; i++) { 381 sed = ohci_alloc_sed(sc); 382 if (!sed) { 383 while (--i >= 0) 384 ohci_free_sed(sc, sc->sc_eds[i]); 385 r = USBD_NOMEM; 386 goto bad3; 387 } 388 /* All ED fields are set to 0. */ 389 sc->sc_eds[i] = sed; 390 sed->ed->ed_flags |= LE(OHCI_ED_SKIP); 391 if (i != 0) { 392 psed = sc->sc_eds[(i-1) / 2]; 393 sed->next = psed; 394 sed->ed->ed_nexted = LE(psed->physaddr); 395 } 396 } 397 /* 398 * Fill HCCA interrupt table. The bit reversal is to get 399 * the tree set up properly to spread the interrupts. 400 */ 401 for (i = 0; i < OHCI_NO_INTRS; i++) 402 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 403 LE(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 404 405 /* Determine in what context we are running. */ 406 ctl = OREAD4(sc, OHCI_CONTROL); 407 if (ctl & OHCI_IR) { 408 /* SMM active, request change */ 409 DPRINTF(("ohci_init: SMM active, request owner change\n")); 410 s = OREAD4(sc, OHCI_COMMAND_STATUS); 411 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 412 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 413 delay(1000); 414 ctl = OREAD4(sc, OHCI_CONTROL); 415 } 416 if ((ctl & OHCI_IR) == 0) { 417 printf("%s: SMM does not respond, resetting\n", 418 USBDEVNAME(sc->sc_bus.bdev)); 419 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 420 goto reset; 421 } 422 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 423 /* BIOS started controller. */ 424 DPRINTF(("ohci_init: BIOS active\n")); 425 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 426 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL); 427 delay(USB_RESUME_DELAY * 1000); 428 } 429 } else { 430 DPRINTF(("ohci_init: cold started\n")); 431 reset: 432 /* Controller was cold started. */ 433 delay(USB_BUS_RESET_DELAY * 1000); 434 } 435 436 /* 437 * This reset should not be necessary according to the OHCI spec, but 438 * without it some controllers do not start. 439 */ 440 DPRINTF(("%s: resetting\n", USBDEVNAME(sc->sc_bus.bdev))); 441 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 442 delay(USB_BUS_RESET_DELAY * 1000); 443 444 /* We now own the host controller and the bus has been reset. */ 445 ival = OHCI_GET_IVAL(OREAD4(sc, OHCI_FM_INTERVAL)); 446 447 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 448 /* Nominal time for a reset is 10 us. */ 449 for (i = 0; i < 10; i++) { 450 delay(10); 451 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 452 if (!hcr) 453 break; 454 } 455 if (hcr) { 456 printf("%s: reset timeout\n", USBDEVNAME(sc->sc_bus.bdev)); 457 r = USBD_IOERROR; 458 goto bad3; 459 } 460 #ifdef USB_DEBUG 461 thesc = sc; 462 if (ohcidebug > 15) 463 ohci_dumpregs(sc); 464 #endif 465 466 /* The controller is now in suspend state, we have 2ms to finish. */ 467 468 /* Set up HC registers. */ 469 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma)); 470 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 471 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 472 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 473 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 474 ctl = OREAD4(sc, OHCI_CONTROL); 475 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 476 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 477 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL; 478 /* And finally start it! */ 479 OWRITE4(sc, OHCI_CONTROL, ctl); 480 481 /* 482 * The controller is now OPERATIONAL. Set a some final 483 * registers that should be set earlier, but that the 484 * controller ignores when in the SUSPEND state. 485 */ 486 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 487 fm |= OHCI_FSMPS(ival) | ival; 488 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 489 per = OHCI_PERIODIC(ival); /* 90% periodic */ 490 OWRITE4(sc, OHCI_PERIODIC_START, per); 491 492 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 493 494 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 495 496 #ifdef USB_DEBUG 497 if (ohcidebug > 5) 498 ohci_dumpregs(sc); 499 #endif 500 501 /* Set up the bus struct. */ 502 sc->sc_bus.open_pipe = ohci_open; 503 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe); 504 sc->sc_bus.do_poll = ohci_poll; 505 506 return (USBD_NORMAL_COMPLETION); 507 508 bad3: 509 ohci_free_sed(sc, sc->sc_ctrl_head); 510 bad2: 511 ohci_free_sed(sc, sc->sc_bulk_head); 512 bad1: 513 usb_freemem(sc->sc_dmatag, &sc->sc_hccadma); 514 return (r); 515 } 516 517 #ifdef USB_DEBUG 518 void ohcidump(void); 519 void ohcidump(void) { ohci_dumpregs(thesc); } 520 521 void 522 ohci_dumpregs(sc) 523 ohci_softc_t *sc; 524 { 525 printf("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 526 OREAD4(sc, OHCI_REVISION), 527 OREAD4(sc, OHCI_CONTROL), 528 OREAD4(sc, OHCI_COMMAND_STATUS)); 529 printf(" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 530 OREAD4(sc, OHCI_INTERRUPT_STATUS), 531 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 532 OREAD4(sc, OHCI_INTERRUPT_DISABLE)); 533 printf(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 534 OREAD4(sc, OHCI_HCCA), 535 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 536 OREAD4(sc, OHCI_CONTROL_HEAD_ED)); 537 printf(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 538 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 539 OREAD4(sc, OHCI_BULK_HEAD_ED), 540 OREAD4(sc, OHCI_BULK_CURRENT_ED)); 541 printf(" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 542 OREAD4(sc, OHCI_DONE_HEAD), 543 OREAD4(sc, OHCI_FM_INTERVAL), 544 OREAD4(sc, OHCI_FM_REMAINING)); 545 printf(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 546 OREAD4(sc, OHCI_FM_NUMBER), 547 OREAD4(sc, OHCI_PERIODIC_START), 548 OREAD4(sc, OHCI_LS_THRESHOLD)); 549 printf(" desca=0x%08x descb=0x%08x stat=0x%08x\n", 550 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 551 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 552 OREAD4(sc, OHCI_RH_STATUS)); 553 printf(" port1=0x%08x port2=0x%08x\n", 554 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 555 OREAD4(sc, OHCI_RH_PORT_STATUS(2))); 556 printf(" HCCA: frame_number=0x%04x done_head=0x%08x\n", 557 LE(sc->sc_hcca->hcca_frame_number), 558 LE(sc->sc_hcca->hcca_done_head)); 559 } 560 #endif 561 562 int 563 ohci_intr(p) 564 void *p; 565 { 566 ohci_softc_t *sc = p; 567 u_int32_t intrs, eintrs; 568 ohci_physaddr_t done; 569 570 /* In case the interrupt occurs before initialization has completed. */ 571 if (sc == NULL || sc->sc_hcca == NULL) { /* NWH added sc==0 */ 572 #ifdef DIAGNOSTIC 573 printf("ohci_intr: sc->sc_hcca == NULL\n"); 574 #endif 575 return (0); 576 } 577 578 done = LE(sc->sc_hcca->hcca_done_head); 579 if (done != 0) { 580 sc->sc_hcca->hcca_done_head = 0; 581 if (done & ~OHCI_DONE_INTRS) 582 intrs = OHCI_WDH; 583 if (done & OHCI_DONE_INTRS) 584 intrs |= OREAD4(sc, OHCI_INTERRUPT_STATUS); 585 } else 586 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 587 if (!intrs) 588 return (0); 589 intrs &= ~OHCI_MIE; 590 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs); /* Acknowledge */ 591 eintrs = intrs & sc->sc_eintrs; 592 if (!eintrs) 593 return (0); 594 595 sc->sc_intrs++; 596 DPRINTFN(7, ("ohci_intr: sc=%p intrs=%x(%x) eintr=%x\n", 597 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), 598 (u_int)eintrs)); 599 600 if (eintrs & OHCI_SO) { 601 printf("%s: scheduling overrun\n",USBDEVNAME(sc->sc_bus.bdev)); 602 /* XXX do what */ 603 intrs &= ~OHCI_SO; 604 } 605 if (eintrs & OHCI_WDH) { 606 ohci_process_done(sc, done &~ OHCI_DONE_INTRS); 607 sc->sc_hcca->hcca_done_head = 0; 608 intrs &= ~OHCI_WDH; 609 } 610 if (eintrs & OHCI_RD) { 611 /* XXX process resume detect */ 612 } 613 if (eintrs & OHCI_UE) { 614 printf("%s: unrecoverable error, controller halted\n", 615 USBDEVNAME(sc->sc_bus.bdev)); 616 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 617 /* XXX what else */ 618 } 619 if (eintrs & OHCI_RHSC) { 620 ohci_rhsc(sc, sc->sc_intrreqh); 621 intrs &= ~OHCI_RHSC; 622 623 /* 624 * Disable RHSC interrupt for now, because it will be 625 * on until the port has been reset. 626 */ 627 ohci_rhsc_able(sc, 0); 628 } 629 630 /* Block unprocessed interrupts. XXX */ 631 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, intrs); 632 sc->sc_eintrs &= ~intrs; 633 634 return (1); 635 } 636 637 void 638 ohci_rhsc_able(sc, on) 639 ohci_softc_t *sc; 640 int on; 641 { 642 DPRINTFN(4, ("ohci_rhsc_able: on=%d\n", on)); 643 if (on) { 644 sc->sc_eintrs |= OHCI_RHSC; 645 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 646 } else { 647 sc->sc_eintrs &= ~OHCI_RHSC; 648 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_RHSC); 649 } 650 } 651 652 #ifdef USB_DEBUG 653 char *ohci_cc_strs[] = { 654 "NO_ERROR", 655 "CRC", 656 "BIT_STUFFING", 657 "DATA_TOGGLE_MISMATCH", 658 "STALL", 659 "DEVICE_NOT_RESPONDING", 660 "PID_CHECK_FAILURE", 661 "UNEXPECTED_PID", 662 "DATA_OVERRUN", 663 "DATA_UNDERRUN", 664 "BUFFER_OVERRUN", 665 "BUFFER_UNDERRUN", 666 "NOT_ACCESSED", 667 }; 668 #endif 669 670 void 671 ohci_process_done(sc, done) 672 ohci_softc_t *sc; 673 ohci_physaddr_t done; 674 { 675 ohci_soft_td_t *std, *sdone; 676 usbd_request_handle reqh; 677 int len, cc; 678 679 DPRINTFN(10,("ohci_process_done: done=0x%08lx\n", (u_long)done)); 680 681 /* Reverse the done list. */ 682 for (sdone = 0; done; done = LE(std->td->td_nexttd)) { 683 std = ohci_hash_find_td(sc, done); 684 std->dnext = sdone; 685 sdone = std; 686 } 687 688 #ifdef USB_DEBUG 689 if (ohcidebug > 10) { 690 printf("ohci_process_done: TD done:\n"); 691 ohci_dump_tds(sdone); 692 } 693 #endif 694 695 for (std = sdone; std; std = std->dnext) { 696 reqh = std->reqh; 697 DPRINTFN(10, ("ohci_process_done: std=%p reqh=%p\n",std,reqh)); 698 cc = OHCI_TD_GET_CC(LE(std->td->td_flags)); 699 if (cc == OHCI_CC_NO_ERROR) { 700 if (std->td->td_cbp == 0) 701 len = std->len; 702 else 703 len = LE(std->td->td_be) - 704 LE(std->td->td_cbp) + 1; 705 /* 706 * Only do a callback on the last stage of a transfer. 707 * Others have hcpriv = 0. 708 */ 709 if ((reqh->pipe->endpoint->edesc->bmAttributes & 710 UE_XFERTYPE) == UE_CONTROL) { 711 /* For a control transfer the length is in 712 * the xfer stage */ 713 if (reqh->hcpriv == std) { 714 reqh->status = USBD_NORMAL_COMPLETION; 715 ohci_ii_done(sc, reqh); 716 } else 717 reqh->actlen = len; 718 } else { 719 if (reqh->hcpriv == std) { 720 reqh->actlen = len; 721 reqh->status = USBD_NORMAL_COMPLETION; 722 ohci_ii_done(sc, reqh); 723 } 724 } 725 } else { 726 ohci_soft_td_t *p, *n; 727 struct ohci_pipe *opipe = 728 (struct ohci_pipe *)reqh->pipe; 729 DPRINTFN(-1,("ohci_process_done: error cc=%d (%s)\n", 730 OHCI_TD_GET_CC(LE(std->td->td_flags)), 731 ohci_cc_strs[OHCI_TD_GET_CC(LE(std->td->td_flags))])); 732 /* 733 * Endpoint is halted. First unlink all the TDs 734 * belonging to the failed transfer, and then restart 735 * the endpoint. 736 */ 737 for (p = std->nexttd; p->reqh == reqh; p = n) { 738 n = p->nexttd; 739 ohci_hash_rem_td(sc, p); 740 ohci_free_std(sc, p); 741 } 742 /* clear halt */ 743 opipe->sed->ed->ed_headp = LE(p->physaddr); 744 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 745 746 if (cc == OHCI_CC_STALL) 747 reqh->status = USBD_STALLED; 748 else 749 reqh->status = USBD_IOERROR; 750 ohci_ii_done(sc, reqh); 751 } 752 ohci_hash_rem_td(sc, std); 753 ohci_free_std(sc, std); 754 } 755 } 756 757 void 758 ohci_ii_done(sc, reqh) 759 ohci_softc_t *sc; 760 usbd_request_handle reqh; 761 { 762 switch (reqh->pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 763 case UE_CONTROL: 764 ohci_ctrl_done(sc, reqh); 765 usb_start_next(reqh->pipe); 766 break; 767 case UE_INTERRUPT: 768 ohci_intr_done(sc, reqh); 769 break; 770 case UE_BULK: 771 ohci_bulk_done(sc, reqh); 772 usb_start_next(reqh->pipe); 773 break; 774 case UE_ISOCHRONOUS: 775 printf("ohci_process_done: ISO done?\n"); 776 usb_start_next(reqh->pipe); 777 break; 778 } 779 780 /* And finally execute callback. */ 781 reqh->xfercb(reqh); 782 } 783 784 void 785 ohci_ctrl_done(sc, reqh) 786 ohci_softc_t *sc; 787 usbd_request_handle reqh; 788 { 789 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 790 u_int len = opipe->u.ctl.length; 791 usb_dma_t *dma; 792 793 DPRINTFN(10,("ohci_ctrl_done: reqh=%p\n", reqh)); 794 795 if (!reqh->isreq) { 796 panic("ohci_ctrl_done: not a request\n"); 797 return; 798 } 799 800 if (len != 0) { 801 dma = &opipe->u.ctl.datadma; 802 if (reqh->request.bmRequestType & UT_READ) 803 memcpy(reqh->buffer, KERNADDR(dma), len); 804 usb_freemem(sc->sc_dmatag, dma); 805 } 806 usb_untimeout(ohci_timeout, reqh, reqh->timo_handle); 807 } 808 809 void 810 ohci_intr_done(sc, reqh) 811 ohci_softc_t *sc; 812 usbd_request_handle reqh; 813 { 814 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 815 usb_dma_t *dma; 816 ohci_soft_ed_t *sed = opipe->sed; 817 ohci_soft_td_t *xfer, *tail; 818 819 820 DPRINTFN(10,("ohci_intr_done: reqh=%p, actlen=%d\n", 821 reqh, reqh->actlen)); 822 823 dma = &opipe->u.intr.datadma; 824 memcpy(reqh->buffer, KERNADDR(dma), reqh->actlen); 825 826 if (reqh->pipe->intrreqh == reqh) { 827 xfer = opipe->tail; 828 tail = ohci_alloc_std(sc); /* XXX should reuse TD */ 829 if (!tail) { 830 reqh->status = USBD_NOMEM; 831 return; 832 } 833 tail->reqh = 0; 834 835 xfer->td->td_flags = LE( 836 OHCI_TD_IN | OHCI_TD_NOCC | 837 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 838 if (reqh->flags & USBD_SHORT_XFER_OK) 839 xfer->td->td_flags |= LE(OHCI_TD_R); 840 xfer->td->td_cbp = LE(DMAADDR(dma)); 841 xfer->nexttd = tail; 842 xfer->td->td_nexttd = LE(tail->physaddr); 843 xfer->td->td_be = LE(LE(xfer->td->td_cbp) + reqh->length - 1); 844 xfer->len = reqh->length; 845 xfer->reqh = reqh; 846 847 reqh->hcpriv = xfer; 848 849 ohci_hash_add_td(sc, xfer); 850 sed->ed->ed_tailp = LE(tail->physaddr); 851 opipe->tail = tail; 852 } else { 853 usb_freemem(sc->sc_dmatag, dma); 854 usb_start_next(reqh->pipe); 855 } 856 } 857 858 void 859 ohci_bulk_done(sc, reqh) 860 ohci_softc_t *sc; 861 usbd_request_handle reqh; 862 { 863 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 864 usb_dma_t *dma; 865 866 867 DPRINTFN(10,("ohci_bulk_done: reqh=%p, actlen=%d\n", 868 reqh, reqh->actlen)); 869 870 dma = &opipe->u.bulk.datadma; 871 if (reqh->request.bmRequestType & UT_READ) 872 memcpy(reqh->buffer, KERNADDR(dma), reqh->actlen); 873 usb_freemem(sc->sc_dmatag, dma); 874 usb_untimeout(ohci_timeout, reqh, reqh->timo_handle); 875 } 876 877 void 878 ohci_rhsc(sc, reqh) 879 ohci_softc_t *sc; 880 usbd_request_handle reqh; 881 { 882 usbd_pipe_handle pipe; 883 struct ohci_pipe *opipe; 884 u_char *p; 885 int i, m; 886 int hstatus; 887 888 hstatus = OREAD4(sc, OHCI_RH_STATUS); 889 DPRINTF(("ohci_rhsc: sc=%p reqh=%p hstatus=0x%08x\n", 890 sc, reqh, hstatus)); 891 892 if (reqh == 0) { 893 /* Just ignore the change. */ 894 return; 895 } 896 897 pipe = reqh->pipe; 898 opipe = (struct ohci_pipe *)pipe; 899 900 p = KERNADDR(&opipe->u.intr.datadma); 901 m = min(sc->sc_noport, reqh->length * 8 - 1); 902 memset(p, 0, reqh->length); 903 for (i = 1; i <= m; i++) { 904 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 905 p[i/8] |= 1 << (i%8); 906 } 907 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p)); 908 reqh->actlen = reqh->length; 909 reqh->status = USBD_NORMAL_COMPLETION; 910 reqh->xfercb(reqh); 911 912 if (reqh->pipe->intrreqh != reqh) { 913 sc->sc_intrreqh = 0; 914 usb_freemem(sc->sc_dmatag, &opipe->u.intr.datadma); 915 usb_start_next(reqh->pipe); 916 } 917 } 918 919 /* 920 * Wait here until controller claims to have an interrupt. 921 * Then call ohci_intr and return. Use timeout to avoid waiting 922 * too long. 923 */ 924 void 925 ohci_waitintr(sc, reqh) 926 ohci_softc_t *sc; 927 usbd_request_handle reqh; 928 { 929 int timo = reqh->timeout; 930 int usecs; 931 u_int32_t intrs; 932 933 reqh->status = USBD_IN_PROGRESS; 934 for (usecs = timo * 1000000 / hz; usecs > 0; usecs -= 1000) { 935 usb_delay_ms(&sc->sc_bus, 1); 936 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 937 DPRINTFN(10,("ohci_waitintr: 0x%04x\n", intrs)); 938 #ifdef USB_DEBUG 939 if (ohcidebug > 15) 940 ohci_dumpregs(sc); 941 #endif 942 if (intrs) { 943 ohci_intr(sc); 944 if (reqh->status != USBD_IN_PROGRESS) 945 return; 946 } 947 } 948 949 /* Timeout */ 950 DPRINTF(("ohci_waitintr: timeout\n")); 951 reqh->status = USBD_TIMEOUT; 952 ohci_ii_done(sc, reqh); 953 /* XXX should free TD */ 954 } 955 956 void 957 ohci_poll(bus) 958 struct usbd_bus *bus; 959 { 960 ohci_softc_t *sc = (ohci_softc_t *)bus; 961 962 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) 963 ohci_intr(sc); 964 } 965 966 usbd_status 967 ohci_device_request(reqh) 968 usbd_request_handle reqh; 969 { 970 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 971 usb_device_request_t *req = &reqh->request; 972 usbd_device_handle dev = opipe->pipe.device; 973 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 974 int addr = dev->address; 975 ohci_soft_td_t *setup, *xfer = 0, *stat, *next, *tail; 976 ohci_soft_ed_t *sed; 977 usb_dma_t *dmap; 978 int isread; 979 int len; 980 usbd_status r; 981 int s; 982 983 isread = req->bmRequestType & UT_READ; 984 len = UGETW(req->wLength); 985 986 DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, " 987 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 988 req->bmRequestType, req->bRequest, UGETW(req->wValue), 989 UGETW(req->wIndex), len, addr, 990 opipe->pipe.endpoint->edesc->bEndpointAddress)); 991 992 setup = opipe->tail; 993 stat = ohci_alloc_std(sc); 994 if (!stat) { 995 r = USBD_NOMEM; 996 goto bad1; 997 } 998 tail = ohci_alloc_std(sc); 999 if (!tail) { 1000 r = USBD_NOMEM; 1001 goto bad2; 1002 } 1003 tail->reqh = 0; 1004 1005 sed = opipe->sed; 1006 dmap = &opipe->u.ctl.datadma; 1007 opipe->u.ctl.length = len; 1008 1009 /* Update device address and length since they may have changed. */ 1010 /* XXX This only needs to be done once, but it's too early in open. */ 1011 sed->ed->ed_flags = LE( 1012 (LE(sed->ed->ed_flags) & ~(OHCI_ED_ADDRMASK | OHCI_ED_MAXPMASK)) | 1013 OHCI_ED_SET_FA(addr) | 1014 OHCI_ED_SET_MAXP(UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize))); 1015 1016 /* Set up data transaction */ 1017 if (len != 0) { 1018 xfer = ohci_alloc_std(sc); 1019 if (!xfer) { 1020 r = USBD_NOMEM; 1021 goto bad3; 1022 } 1023 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap); 1024 if (r != USBD_NORMAL_COMPLETION) 1025 goto bad4; 1026 xfer->td->td_flags = LE( 1027 (isread ? OHCI_TD_IN : OHCI_TD_OUT) | OHCI_TD_NOCC | 1028 OHCI_TD_TOGGLE_1 | OHCI_TD_NOINTR | 1029 (reqh->flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0)); 1030 xfer->td->td_cbp = LE(DMAADDR(dmap)); 1031 xfer->nexttd = stat; 1032 xfer->td->td_nexttd = LE(stat->physaddr); 1033 xfer->td->td_be = LE(LE(xfer->td->td_cbp) + len - 1); 1034 xfer->len = len; 1035 xfer->reqh = reqh; 1036 1037 next = xfer; 1038 } else 1039 next = stat; 1040 1041 memcpy(KERNADDR(&opipe->u.ctl.reqdma), req, sizeof *req); 1042 if (!isread && len != 0) 1043 memcpy(KERNADDR(dmap), reqh->buffer, len); 1044 1045 setup->td->td_flags = LE(OHCI_TD_SETUP | OHCI_TD_NOCC | 1046 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1047 setup->td->td_cbp = LE(DMAADDR(&opipe->u.ctl.reqdma)); 1048 setup->nexttd = next; 1049 setup->td->td_nexttd = LE(next->physaddr); 1050 setup->td->td_be = LE(LE(setup->td->td_cbp) + sizeof *req - 1); 1051 setup->len = 0; /* XXX The number of byte we count */ 1052 setup->reqh = reqh; 1053 1054 stat->td->td_flags = LE( 1055 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | OHCI_TD_NOCC | 1056 OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1057 stat->td->td_cbp = 0; 1058 stat->nexttd = tail; 1059 stat->td->td_nexttd = LE(tail->physaddr); 1060 stat->td->td_be = 0; 1061 stat->len = 0; 1062 stat->reqh = reqh; 1063 1064 reqh->hcpriv = stat; 1065 1066 #if USB_DEBUG 1067 if (ohcidebug > 5) { 1068 printf("ohci_device_request:\n"); 1069 ohci_dump_ed(sed); 1070 ohci_dump_tds(setup); 1071 } 1072 #endif 1073 1074 /* Insert ED in schedule */ 1075 s = splusb(); 1076 ohci_hash_add_td(sc, setup); 1077 if (len != 0) 1078 ohci_hash_add_td(sc, xfer); 1079 ohci_hash_add_td(sc, stat); 1080 sed->ed->ed_tailp = LE(tail->physaddr); 1081 opipe->tail = tail; 1082 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1083 if (reqh->timeout && !sc->sc_bus.use_polling) { 1084 usb_timeout(ohci_timeout, reqh, 1085 MS_TO_TICKS(reqh->timeout), reqh->timo_handle); 1086 } 1087 splx(s); 1088 1089 #if USB_DEBUG 1090 if (ohcidebug > 5) { 1091 delay(5000); 1092 printf("ohci_device_request: status=%x\n", 1093 OREAD4(sc, OHCI_COMMAND_STATUS)); 1094 ohci_dump_ed(sed); 1095 ohci_dump_tds(setup); 1096 } 1097 #endif 1098 1099 return (USBD_NORMAL_COMPLETION); 1100 1101 bad4: 1102 ohci_free_std(sc, xfer); 1103 bad3: 1104 ohci_free_std(sc, tail); 1105 bad2: 1106 ohci_free_std(sc, stat); 1107 bad1: 1108 return (r); 1109 } 1110 1111 /* 1112 * Add an ED to the schedule. Called at splusb(). 1113 */ 1114 void 1115 ohci_add_ed(sed, head) 1116 ohci_soft_ed_t *sed; 1117 ohci_soft_ed_t *head; 1118 { 1119 sed->next = head->next; 1120 sed->ed->ed_nexted = head->ed->ed_nexted; 1121 head->next = sed; 1122 head->ed->ed_nexted = LE(sed->physaddr); 1123 } 1124 1125 /* 1126 * Remove an ED from the schedule. Called at splusb(). 1127 */ 1128 void 1129 ohci_rem_ed(sed, head) 1130 ohci_soft_ed_t *sed; 1131 ohci_soft_ed_t *head; 1132 { 1133 ohci_soft_ed_t *p; 1134 1135 /* XXX */ 1136 for (p = head; p && p->next != sed; p = p->next) 1137 ; 1138 if (!p) 1139 panic("ohci_rem_ed: ED not found\n"); 1140 p->next = sed->next; 1141 p->ed->ed_nexted = sed->ed->ed_nexted; 1142 } 1143 1144 /* 1145 * When a transfer is completed the TD is added to the done queue by 1146 * the host controller. This queue is the processed by software. 1147 * Unfortunately the queue contains the physical address of the TD 1148 * and we have no simple way to translate this back to a kernel address. 1149 * To make the translation possible (and fast) we use a hash table of 1150 * TDs currently in the schedule. The physical address is used as the 1151 * hash value. 1152 */ 1153 1154 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1155 /* Called at splusb() */ 1156 void 1157 ohci_hash_add_td(sc, std) 1158 ohci_softc_t *sc; 1159 ohci_soft_td_t *std; 1160 { 1161 int h = HASH(std->physaddr); 1162 1163 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1164 } 1165 1166 /* Called at splusb() */ 1167 void 1168 ohci_hash_rem_td(sc, std) 1169 ohci_softc_t *sc; 1170 ohci_soft_td_t *std; 1171 { 1172 LIST_REMOVE(std, hnext); 1173 } 1174 1175 ohci_soft_td_t * 1176 ohci_hash_find_td(sc, a) 1177 ohci_softc_t *sc; 1178 ohci_physaddr_t a; 1179 { 1180 int h = HASH(a); 1181 ohci_soft_td_t *std; 1182 1183 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1184 std != 0; 1185 std = LIST_NEXT(std, hnext)) 1186 if (std->physaddr == a) 1187 return (std); 1188 panic("ohci_hash_find_td: addr 0x%08lx not found\n", (u_long)a); 1189 } 1190 1191 void 1192 ohci_timeout(addr) 1193 void *addr; 1194 { 1195 #if 0 1196 usbd_request_handle *reqh = addr; 1197 int s; 1198 1199 DPRINTF(("ohci_timeout: reqh=%p\n", reqh)); 1200 s = splusb(); 1201 /* XXX need to inactivate TD before calling interrupt routine */ 1202 ohci_XXX_done(reqh); 1203 splx(s); 1204 #endif 1205 } 1206 1207 #ifdef USB_DEBUG 1208 void 1209 ohci_dump_tds(std) 1210 ohci_soft_td_t *std; 1211 { 1212 for (; std; std = std->nexttd) 1213 ohci_dump_td(std); 1214 } 1215 1216 void 1217 ohci_dump_td(std) 1218 ohci_soft_td_t *std; 1219 { 1220 printf("TD(%p) at %08lx: %b delay=%d ec=%d cc=%d\ncbp=0x%08lx " 1221 "nexttd=0x%08lx be=0x%08lx\n", 1222 std, (u_long)std->physaddr, 1223 (u_long)LE(std->td->td_flags), 1224 "\20\23R\24OUT\25IN\31TOG1\32SETTOGGLE", 1225 OHCI_TD_GET_DI(LE(std->td->td_flags)), 1226 OHCI_TD_GET_EC(LE(std->td->td_flags)), 1227 OHCI_TD_GET_CC(LE(std->td->td_flags)), 1228 (u_long)LE(std->td->td_cbp), 1229 (u_long)LE(std->td->td_nexttd), (u_long)LE(std->td->td_be)); 1230 } 1231 1232 void 1233 ohci_dump_ed(sed) 1234 ohci_soft_ed_t *sed; 1235 { 1236 printf("ED(%p) at %08lx: addr=%d endpt=%d maxp=%d %b\ntailp=0x%08lx " 1237 "headp=%b nexted=0x%08lx\n", 1238 sed, (u_long)sed->physaddr, 1239 OHCI_ED_GET_FA(LE(sed->ed->ed_flags)), 1240 OHCI_ED_GET_EN(LE(sed->ed->ed_flags)), 1241 OHCI_ED_GET_MAXP(LE(sed->ed->ed_flags)), 1242 (u_long)LE(sed->ed->ed_flags), 1243 "\20\14OUT\15IN\16LOWSPEED\17SKIP\20ISO", 1244 (u_long)LE(sed->ed->ed_tailp), 1245 (u_long)LE(sed->ed->ed_headp), "\20\1HALT\2CARRY", 1246 (u_long)LE(sed->ed->ed_nexted)); 1247 } 1248 #endif 1249 1250 usbd_status 1251 ohci_open(pipe) 1252 usbd_pipe_handle pipe; 1253 { 1254 usbd_device_handle dev = pipe->device; 1255 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 1256 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1257 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 1258 u_int8_t addr = dev->address; 1259 ohci_soft_ed_t *sed; 1260 ohci_soft_td_t *std; 1261 usbd_status r; 1262 int s; 1263 1264 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1265 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1266 if (addr == sc->sc_addr) { 1267 switch (ed->bEndpointAddress) { 1268 case USB_CONTROL_ENDPOINT: 1269 pipe->methods = &ohci_root_ctrl_methods; 1270 break; 1271 case UE_IN | OHCI_INTR_ENDPT: 1272 pipe->methods = &ohci_root_intr_methods; 1273 break; 1274 default: 1275 return (USBD_INVAL); 1276 } 1277 } else { 1278 sed = ohci_alloc_sed(sc); 1279 if (sed == 0) 1280 goto bad0; 1281 std = ohci_alloc_std(sc); 1282 if (std == 0) 1283 goto bad1; 1284 opipe->sed = sed; 1285 opipe->tail = std; 1286 sed->ed->ed_flags = LE( 1287 OHCI_ED_SET_FA(addr) | 1288 OHCI_ED_SET_EN(ed->bEndpointAddress) | 1289 OHCI_ED_DIR_TD | 1290 (dev->lowspeed ? OHCI_ED_SPEED : 0) | 1291 ((ed->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS ? 1292 OHCI_ED_FORMAT_ISO : OHCI_ED_FORMAT_GEN) | 1293 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 1294 sed->ed->ed_headp = sed->ed->ed_tailp = LE(std->physaddr); 1295 1296 switch (ed->bmAttributes & UE_XFERTYPE) { 1297 case UE_CONTROL: 1298 pipe->methods = &ohci_device_ctrl_methods; 1299 r = usb_allocmem(sc->sc_dmatag, 1300 sizeof(usb_device_request_t), 1301 0, &opipe->u.ctl.reqdma); 1302 if (r != USBD_NORMAL_COMPLETION) 1303 goto bad; 1304 s = splusb(); 1305 ohci_add_ed(sed, sc->sc_ctrl_head); 1306 splx(s); 1307 break; 1308 case UE_INTERRUPT: 1309 pipe->methods = &ohci_device_intr_methods; 1310 return (ohci_device_setintr(sc, opipe, ed->bInterval)); 1311 case UE_ISOCHRONOUS: 1312 printf("ohci_open: open iso unimplemented\n"); 1313 return (USBD_XXX); 1314 case UE_BULK: 1315 pipe->methods = &ohci_device_bulk_methods; 1316 s = splusb(); 1317 ohci_add_ed(sed, sc->sc_bulk_head); 1318 splx(s); 1319 break; 1320 } 1321 } 1322 return (USBD_NORMAL_COMPLETION); 1323 1324 bad: 1325 ohci_free_std(sc, std); 1326 bad1: 1327 ohci_free_sed(sc, sed); 1328 bad0: 1329 return (USBD_NOMEM); 1330 1331 } 1332 1333 /* 1334 * Data structures and routines to emulate the root hub. 1335 */ 1336 usb_device_descriptor_t ohci_devd = { 1337 USB_DEVICE_DESCRIPTOR_SIZE, 1338 UDESC_DEVICE, /* type */ 1339 {0x00, 0x01}, /* USB version */ 1340 UCLASS_HUB, /* class */ 1341 USUBCLASS_HUB, /* subclass */ 1342 0, /* protocol */ 1343 64, /* max packet */ 1344 {0},{0},{0x00,0x01}, /* device id */ 1345 1,2,0, /* string indicies */ 1346 1 /* # of configurations */ 1347 }; 1348 1349 usb_config_descriptor_t ohci_confd = { 1350 USB_CONFIG_DESCRIPTOR_SIZE, 1351 UDESC_CONFIG, 1352 {USB_CONFIG_DESCRIPTOR_SIZE + 1353 USB_INTERFACE_DESCRIPTOR_SIZE + 1354 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1355 1, 1356 1, 1357 0, 1358 UC_SELF_POWERED, 1359 0 /* max power */ 1360 }; 1361 1362 usb_interface_descriptor_t ohci_ifcd = { 1363 USB_INTERFACE_DESCRIPTOR_SIZE, 1364 UDESC_INTERFACE, 1365 0, 1366 0, 1367 1, 1368 UCLASS_HUB, 1369 USUBCLASS_HUB, 1370 0, 1371 0 1372 }; 1373 1374 usb_endpoint_descriptor_t ohci_endpd = { 1375 USB_ENDPOINT_DESCRIPTOR_SIZE, 1376 UDESC_ENDPOINT, 1377 UE_IN | OHCI_INTR_ENDPT, 1378 UE_INTERRUPT, 1379 {8, 0}, /* max packet */ 1380 255 1381 }; 1382 1383 usb_hub_descriptor_t ohci_hubd = { 1384 USB_HUB_DESCRIPTOR_SIZE, 1385 UDESC_HUB, 1386 0, 1387 {0,0}, 1388 0, 1389 0, 1390 {0}, 1391 }; 1392 1393 int 1394 ohci_str(p, l, s) 1395 usb_string_descriptor_t *p; 1396 int l; 1397 char *s; 1398 { 1399 int i; 1400 1401 if (l == 0) 1402 return (0); 1403 p->bLength = 2 * strlen(s) + 2; 1404 if (l == 1) 1405 return (1); 1406 p->bDescriptorType = UDESC_STRING; 1407 l -= 2; 1408 for (i = 0; s[i] && l > 1; i++, l -= 2) 1409 USETW2(p->bString[i], 0, s[i]); 1410 return (2*i+2); 1411 } 1412 1413 /* 1414 * Simulate a hardware hub by handling all the necessary requests. 1415 */ 1416 usbd_status 1417 ohci_root_ctrl_transfer(reqh) 1418 usbd_request_handle reqh; 1419 { 1420 int s; 1421 usbd_status r; 1422 1423 s = splusb(); 1424 r = usb_insert_transfer(reqh); 1425 splx(s); 1426 if (r != USBD_NORMAL_COMPLETION) 1427 return (r); 1428 else 1429 return (ohci_root_ctrl_start(reqh)); 1430 } 1431 1432 usbd_status 1433 ohci_root_ctrl_start(reqh) 1434 usbd_request_handle reqh; 1435 { 1436 ohci_softc_t *sc = (ohci_softc_t *)reqh->pipe->device->bus; 1437 usb_device_request_t *req; 1438 void *buf; 1439 int port, i; 1440 int len, value, index, l, totlen = 0; 1441 usb_port_status_t ps; 1442 usb_hub_descriptor_t hubd; 1443 usbd_status r; 1444 u_int32_t v; 1445 1446 if (!reqh->isreq) 1447 /* XXX panic */ 1448 return (USBD_INVAL); 1449 req = &reqh->request; 1450 buf = reqh->buffer; 1451 1452 DPRINTFN(4,("ohci_root_ctrl_control type=0x%02x request=%02x\n", 1453 req->bmRequestType, req->bRequest)); 1454 1455 len = UGETW(req->wLength); 1456 value = UGETW(req->wValue); 1457 index = UGETW(req->wIndex); 1458 #define C(x,y) ((x) | ((y) << 8)) 1459 switch(C(req->bRequest, req->bmRequestType)) { 1460 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 1461 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 1462 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 1463 /* 1464 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 1465 * for the integrated root hub. 1466 */ 1467 break; 1468 case C(UR_GET_CONFIG, UT_READ_DEVICE): 1469 if (len > 0) { 1470 *(u_int8_t *)buf = sc->sc_conf; 1471 totlen = 1; 1472 } 1473 break; 1474 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 1475 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value)); 1476 switch(value >> 8) { 1477 case UDESC_DEVICE: 1478 if ((value & 0xff) != 0) { 1479 r = USBD_IOERROR; 1480 goto ret; 1481 } 1482 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1483 memcpy(buf, &ohci_devd, l); 1484 break; 1485 case UDESC_CONFIG: 1486 if ((value & 0xff) != 0) { 1487 r = USBD_IOERROR; 1488 goto ret; 1489 } 1490 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 1491 memcpy(buf, &ohci_confd, l); 1492 buf = (char *)buf + l; 1493 len -= l; 1494 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 1495 totlen += l; 1496 memcpy(buf, &ohci_ifcd, l); 1497 buf = (char *)buf + l; 1498 len -= l; 1499 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 1500 totlen += l; 1501 memcpy(buf, &ohci_endpd, l); 1502 break; 1503 case UDESC_STRING: 1504 if (len == 0) 1505 break; 1506 *(u_int8_t *)buf = 0; 1507 totlen = 1; 1508 switch (value & 0xff) { 1509 case 1: /* Vendor */ 1510 totlen = ohci_str(buf, len, sc->sc_vendor); 1511 break; 1512 case 2: /* Product */ 1513 totlen = ohci_str(buf, len, "OHCI root hub"); 1514 break; 1515 } 1516 break; 1517 default: 1518 r = USBD_IOERROR; 1519 goto ret; 1520 } 1521 break; 1522 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 1523 if (len > 0) { 1524 *(u_int8_t *)buf = 0; 1525 totlen = 1; 1526 } 1527 break; 1528 case C(UR_GET_STATUS, UT_READ_DEVICE): 1529 if (len > 1) { 1530 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 1531 totlen = 2; 1532 } 1533 break; 1534 case C(UR_GET_STATUS, UT_READ_INTERFACE): 1535 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 1536 if (len > 1) { 1537 USETW(((usb_status_t *)buf)->wStatus, 0); 1538 totlen = 2; 1539 } 1540 break; 1541 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 1542 if (value >= USB_MAX_DEVICES) { 1543 r = USBD_IOERROR; 1544 goto ret; 1545 } 1546 sc->sc_addr = value; 1547 break; 1548 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 1549 if (value != 0 && value != 1) { 1550 r = USBD_IOERROR; 1551 goto ret; 1552 } 1553 sc->sc_conf = value; 1554 break; 1555 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 1556 break; 1557 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 1558 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 1559 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 1560 r = USBD_IOERROR; 1561 goto ret; 1562 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 1563 break; 1564 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 1565 break; 1566 /* Hub requests */ 1567 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 1568 break; 1569 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 1570 DPRINTFN(8, ("ohci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 1571 "port=%d feature=%d\n", 1572 index, value)); 1573 if (index < 1 || index > sc->sc_noport) { 1574 r = USBD_IOERROR; 1575 goto ret; 1576 } 1577 port = OHCI_RH_PORT_STATUS(index); 1578 switch(value) { 1579 case UHF_PORT_ENABLE: 1580 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 1581 break; 1582 case UHF_PORT_SUSPEND: 1583 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 1584 break; 1585 case UHF_PORT_POWER: 1586 OWRITE4(sc, port, UPS_LOW_SPEED); 1587 break; 1588 case UHF_C_PORT_CONNECTION: 1589 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 1590 break; 1591 case UHF_C_PORT_ENABLE: 1592 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 1593 break; 1594 case UHF_C_PORT_SUSPEND: 1595 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 1596 break; 1597 case UHF_C_PORT_OVER_CURRENT: 1598 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 1599 break; 1600 case UHF_C_PORT_RESET: 1601 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 1602 break; 1603 default: 1604 r = USBD_IOERROR; 1605 goto ret; 1606 } 1607 switch(value) { 1608 case UHF_C_PORT_CONNECTION: 1609 case UHF_C_PORT_ENABLE: 1610 case UHF_C_PORT_SUSPEND: 1611 case UHF_C_PORT_OVER_CURRENT: 1612 case UHF_C_PORT_RESET: 1613 /* Enable RHSC interrupt if condition is cleared. */ 1614 if ((OREAD4(sc, port) >> 16) == 0) 1615 ohci_rhsc_able(sc, 1); 1616 break; 1617 default: 1618 break; 1619 } 1620 break; 1621 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 1622 if (value != 0) { 1623 r = USBD_IOERROR; 1624 goto ret; 1625 } 1626 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 1627 hubd = ohci_hubd; 1628 hubd.bNbrPorts = sc->sc_noport; 1629 USETW(hubd.wHubCharacteristics, 1630 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 1631 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 1632 /* XXX overcurrent */ 1633 ); 1634 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 1635 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 1636 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 1637 hubd.DeviceRemovable[i++] = (u_int8_t)v; 1638 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 1639 l = min(len, hubd.bDescLength); 1640 totlen = l; 1641 memcpy(buf, &hubd, l); 1642 break; 1643 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 1644 if (len != 4) { 1645 r = USBD_IOERROR; 1646 goto ret; 1647 } 1648 memset(buf, 0, len); /* ? XXX */ 1649 totlen = len; 1650 break; 1651 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 1652 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n", 1653 index)); 1654 if (index < 1 || index > sc->sc_noport) { 1655 r = USBD_IOERROR; 1656 goto ret; 1657 } 1658 if (len != 4) { 1659 r = USBD_IOERROR; 1660 goto ret; 1661 } 1662 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 1663 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n", 1664 v)); 1665 USETW(ps.wPortStatus, v); 1666 USETW(ps.wPortChange, v >> 16); 1667 l = min(len, sizeof ps); 1668 memcpy(buf, &ps, l); 1669 totlen = l; 1670 break; 1671 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 1672 r = USBD_IOERROR; 1673 goto ret; 1674 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 1675 break; 1676 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 1677 if (index < 1 || index > sc->sc_noport) { 1678 r = USBD_IOERROR; 1679 goto ret; 1680 } 1681 port = OHCI_RH_PORT_STATUS(index); 1682 switch(value) { 1683 case UHF_PORT_ENABLE: 1684 OWRITE4(sc, port, UPS_PORT_ENABLED); 1685 break; 1686 case UHF_PORT_SUSPEND: 1687 OWRITE4(sc, port, UPS_SUSPEND); 1688 break; 1689 case UHF_PORT_RESET: 1690 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n", 1691 index)); 1692 OWRITE4(sc, port, UPS_RESET); 1693 for (i = 0; i < 10; i++) { 1694 usb_delay_ms(&sc->sc_bus, 10); 1695 if ((OREAD4(sc, port) & UPS_RESET) == 0) 1696 break; 1697 } 1698 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n", 1699 index, OREAD4(sc, port))); 1700 break; 1701 case UHF_PORT_POWER: 1702 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power " 1703 "%d\n", index)); 1704 OWRITE4(sc, port, UPS_PORT_POWER); 1705 break; 1706 default: 1707 r = USBD_IOERROR; 1708 goto ret; 1709 } 1710 break; 1711 default: 1712 r = USBD_IOERROR; 1713 goto ret; 1714 } 1715 reqh->actlen = totlen; 1716 r = USBD_NORMAL_COMPLETION; 1717 ret: 1718 reqh->status = r; 1719 reqh->xfercb(reqh); 1720 usb_start_next(reqh->pipe); 1721 return (USBD_IN_PROGRESS); 1722 } 1723 1724 /* Abort a root control request. */ 1725 void 1726 ohci_root_ctrl_abort(reqh) 1727 usbd_request_handle reqh; 1728 { 1729 /* Nothing to do, all transfers are synchronous. */ 1730 } 1731 1732 /* Close the root pipe. */ 1733 void 1734 ohci_root_ctrl_close(pipe) 1735 usbd_pipe_handle pipe; 1736 { 1737 DPRINTF(("ohci_root_ctrl_close\n")); 1738 } 1739 1740 usbd_status 1741 ohci_root_intr_transfer(reqh) 1742 usbd_request_handle reqh; 1743 { 1744 int s; 1745 usbd_status r; 1746 1747 s = splusb(); 1748 r = usb_insert_transfer(reqh); 1749 splx(s); 1750 if (r != USBD_NORMAL_COMPLETION) 1751 return (r); 1752 else 1753 return (ohci_root_intr_start(reqh)); 1754 } 1755 1756 usbd_status 1757 ohci_root_intr_start(reqh) 1758 usbd_request_handle reqh; 1759 { 1760 usbd_pipe_handle pipe = reqh->pipe; 1761 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 1762 struct ohci_pipe *upipe = (struct ohci_pipe *)pipe; 1763 usb_dma_t *dmap; 1764 usbd_status r; 1765 int len; 1766 1767 len = reqh->length; 1768 dmap = &upipe->u.intr.datadma; 1769 if (len == 0) 1770 return (USBD_INVAL); /* XXX should it be? */ 1771 1772 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap); 1773 if (r != USBD_NORMAL_COMPLETION) 1774 return (r); 1775 sc->sc_intrreqh = reqh; 1776 1777 return (USBD_IN_PROGRESS); 1778 } 1779 1780 /* Abort a root interrupt request. */ 1781 void 1782 ohci_root_intr_abort(reqh) 1783 usbd_request_handle reqh; 1784 { 1785 /* No need to abort. */ 1786 } 1787 1788 /* Close the root pipe. */ 1789 void 1790 ohci_root_intr_close(pipe) 1791 usbd_pipe_handle pipe; 1792 { 1793 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 1794 sc->sc_intrreqh = 0; 1795 1796 DPRINTF(("ohci_root_intr_close\n")); 1797 } 1798 1799 /************************/ 1800 1801 usbd_status 1802 ohci_device_ctrl_transfer(reqh) 1803 usbd_request_handle reqh; 1804 { 1805 int s; 1806 usbd_status r; 1807 1808 s = splusb(); 1809 r = usb_insert_transfer(reqh); 1810 splx(s); 1811 if (r != USBD_NORMAL_COMPLETION) 1812 return (r); 1813 else 1814 return (ohci_device_ctrl_start(reqh)); 1815 } 1816 1817 usbd_status 1818 ohci_device_ctrl_start(reqh) 1819 usbd_request_handle reqh; 1820 { 1821 ohci_softc_t *sc = (ohci_softc_t *)reqh->pipe->device->bus; 1822 usbd_status r; 1823 1824 if (!reqh->isreq) { 1825 /* XXX panic */ 1826 printf("ohci_device_ctrl_transfer: not a request\n"); 1827 return (USBD_INVAL); 1828 } 1829 1830 r = ohci_device_request(reqh); 1831 if (r != USBD_NORMAL_COMPLETION) 1832 return (r); 1833 1834 if (sc->sc_bus.use_polling) 1835 ohci_waitintr(sc, reqh); 1836 return (USBD_IN_PROGRESS); 1837 } 1838 1839 /* Abort a device control request. */ 1840 void 1841 ohci_device_ctrl_abort(reqh) 1842 usbd_request_handle reqh; 1843 { 1844 /* XXX inactivate */ 1845 usb_delay_ms(reqh->pipe->device->bus, 1); /* make sure it is donw */ 1846 /* XXX call done */ 1847 } 1848 1849 /* Close a device control pipe. */ 1850 void 1851 ohci_device_ctrl_close(pipe) 1852 usbd_pipe_handle pipe; 1853 { 1854 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 1855 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 1856 ohci_soft_ed_t *sed = opipe->sed; 1857 int s; 1858 1859 s = splusb(); 1860 sed->ed->ed_flags |= LE(OHCI_ED_SKIP); 1861 if ((LE(sed->ed->ed_tailp) & OHCI_TAILMASK) != LE(sed->ed->ed_headp)) 1862 usb_delay_ms(&sc->sc_bus, 2); 1863 ohci_rem_ed(sed, sc->sc_ctrl_head); 1864 splx(s); 1865 ohci_free_std(sc, opipe->tail); 1866 ohci_free_sed(sc, opipe->sed); 1867 /* XXX free other resources */ 1868 } 1869 1870 /************************/ 1871 1872 usbd_status 1873 ohci_device_bulk_transfer(reqh) 1874 usbd_request_handle reqh; 1875 { 1876 int s; 1877 usbd_status r; 1878 1879 s = splusb(); 1880 r = usb_insert_transfer(reqh); 1881 splx(s); 1882 if (r != USBD_NORMAL_COMPLETION) 1883 return (r); 1884 else 1885 return (ohci_device_bulk_start(reqh)); 1886 } 1887 1888 usbd_status 1889 ohci_device_bulk_start(reqh) 1890 usbd_request_handle reqh; 1891 { 1892 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 1893 usbd_device_handle dev = opipe->pipe.device; 1894 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 1895 int addr = dev->address; 1896 ohci_soft_td_t *xfer, *tail; 1897 ohci_soft_ed_t *sed; 1898 usb_dma_t *dmap; 1899 usbd_status r; 1900 int s, len, isread; 1901 1902 if (reqh->isreq) { 1903 /* XXX panic */ 1904 printf("ohci_device_bulk_transfer: a request\n"); 1905 return (USBD_INVAL); 1906 } 1907 1908 len = reqh->length; 1909 dmap = &opipe->u.bulk.datadma; 1910 isread = reqh->pipe->endpoint->edesc->bEndpointAddress & UE_IN; 1911 sed = opipe->sed; 1912 1913 opipe->u.bulk.length = len; 1914 1915 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap); 1916 if (r != USBD_NORMAL_COMPLETION) 1917 goto ret1; 1918 1919 tail = ohci_alloc_std(sc); 1920 if (!tail) { 1921 r = USBD_NOMEM; 1922 goto ret2; 1923 } 1924 tail->reqh = 0; 1925 1926 /* Update device address */ 1927 sed->ed->ed_flags = LE( 1928 (LE(sed->ed->ed_flags) & ~OHCI_ED_ADDRMASK) | 1929 OHCI_ED_SET_FA(addr)); 1930 1931 /* Set up data transaction */ 1932 xfer = opipe->tail; 1933 xfer->td->td_flags = LE( 1934 (isread ? OHCI_TD_IN : OHCI_TD_OUT) | OHCI_TD_NOCC | 1935 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY | 1936 (reqh->flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0)); 1937 xfer->td->td_cbp = LE(DMAADDR(dmap)); 1938 xfer->nexttd = tail; 1939 xfer->td->td_nexttd = LE(tail->physaddr); 1940 xfer->td->td_be = LE(LE(xfer->td->td_cbp) + len - 1); 1941 xfer->len = len; 1942 xfer->reqh = reqh; 1943 1944 reqh->hcpriv = xfer; 1945 1946 if (!isread) 1947 memcpy(KERNADDR(dmap), reqh->buffer, len); 1948 1949 /* Insert ED in schedule */ 1950 s = splusb(); 1951 ohci_hash_add_td(sc, xfer); 1952 sed->ed->ed_tailp = LE(tail->physaddr); 1953 opipe->tail = tail; 1954 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 1955 if (reqh->timeout && !sc->sc_bus.use_polling) { 1956 usb_timeout(ohci_timeout, reqh, 1957 MS_TO_TICKS(reqh->timeout), reqh->timo_handle); 1958 } 1959 splx(s); 1960 1961 return (USBD_IN_PROGRESS); 1962 1963 ret2: 1964 usb_freemem(sc->sc_dmatag, dmap); 1965 ret1: 1966 return (r); 1967 } 1968 1969 /* Abort a device bulk request. */ 1970 void 1971 ohci_device_bulk_abort(reqh) 1972 usbd_request_handle reqh; 1973 { 1974 #if 0 1975 sed->ed->ed_flags |= LE(OHCI_ED_SKIP); 1976 if ((LE(sed->ed->ed_tailp) & OHCI_TAILMASK) != LE(sed->ed->ed_headp)) 1977 usb_delay_ms(reqh->pipe->device->bus, 2); 1978 #endif 1979 /* XXX inactivate */ 1980 usb_delay_ms(reqh->pipe->device->bus, 1); /* make sure it is done */ 1981 /* XXX call done */ 1982 } 1983 1984 /* Close a device bulk pipe. */ 1985 void 1986 ohci_device_bulk_close(pipe) 1987 usbd_pipe_handle pipe; 1988 { 1989 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 1990 usbd_device_handle dev = opipe->pipe.device; 1991 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 1992 int s; 1993 1994 s = splusb(); 1995 ohci_rem_ed(opipe->sed, sc->sc_bulk_head); 1996 splx(s); 1997 ohci_free_std(sc, opipe->tail); 1998 ohci_free_sed(sc, opipe->sed); 1999 /* XXX free other resources */ 2000 } 2001 2002 /************************/ 2003 2004 usbd_status 2005 ohci_device_intr_transfer(reqh) 2006 usbd_request_handle reqh; 2007 { 2008 int s; 2009 usbd_status r; 2010 2011 s = splusb(); 2012 r = usb_insert_transfer(reqh); 2013 splx(s); 2014 if (r != USBD_NORMAL_COMPLETION) 2015 return (r); 2016 else 2017 return (ohci_device_intr_start(reqh)); 2018 } 2019 2020 usbd_status 2021 ohci_device_intr_start(reqh) 2022 usbd_request_handle reqh; 2023 { 2024 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 2025 usbd_device_handle dev = opipe->pipe.device; 2026 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 2027 ohci_soft_ed_t *sed = opipe->sed; 2028 ohci_soft_td_t *xfer, *tail; 2029 usb_dma_t *dmap; 2030 usbd_status r; 2031 int len; 2032 int s; 2033 2034 DPRINTFN(3, ("ohci_device_intr_transfer: reqh=%p buf=%p len=%d " 2035 "flags=%d priv=%p\n", 2036 reqh, reqh->buffer, reqh->length, reqh->flags, reqh->priv)); 2037 2038 if (reqh->isreq) 2039 panic("ohci_device_intr_transfer: a request\n"); 2040 2041 len = reqh->length; 2042 dmap = &opipe->u.intr.datadma; 2043 if (len == 0) 2044 return (USBD_INVAL); /* XXX should it be? */ 2045 2046 xfer = opipe->tail; 2047 tail = ohci_alloc_std(sc); 2048 if (!tail) { 2049 r = USBD_NOMEM; 2050 goto ret1; 2051 } 2052 tail->reqh = 0; 2053 2054 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap); 2055 if (r != USBD_NORMAL_COMPLETION) 2056 goto ret2; 2057 2058 xfer->td->td_flags = LE( 2059 OHCI_TD_IN | OHCI_TD_NOCC | 2060 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 2061 if (reqh->flags & USBD_SHORT_XFER_OK) 2062 xfer->td->td_flags |= LE(OHCI_TD_R); 2063 xfer->td->td_cbp = LE(DMAADDR(dmap)); 2064 xfer->nexttd = tail; 2065 xfer->td->td_nexttd = LE(tail->physaddr); 2066 xfer->td->td_be = LE(LE(xfer->td->td_cbp) + len - 1); 2067 xfer->len = len; 2068 xfer->reqh = reqh; 2069 2070 reqh->hcpriv = xfer; 2071 2072 #if USB_DEBUG 2073 if (ohcidebug > 5) { 2074 printf("ohci_device_intr_transfer:\n"); 2075 ohci_dump_ed(sed); 2076 ohci_dump_tds(xfer); 2077 } 2078 #endif 2079 2080 /* Insert ED in schedule */ 2081 s = splusb(); 2082 ohci_hash_add_td(sc, xfer); 2083 sed->ed->ed_tailp = LE(tail->physaddr); 2084 opipe->tail = tail; 2085 #if 0 2086 if (reqh->timeout && !sc->sc_bus.use_polling) { 2087 usb_timeout(ohci_timeout, reqh, 2088 MS_TO_TICKS(reqh->timeout), reqh->timo_handle); 2089 } 2090 #endif 2091 sed->ed->ed_flags &= LE(~OHCI_ED_SKIP); 2092 2093 #ifdef USB_DEBUG 2094 if (ohcidebug > 5) { 2095 delay(5000); 2096 printf("ohci_device_intr_transfer: status=%x\n", 2097 OREAD4(sc, OHCI_COMMAND_STATUS)); 2098 ohci_dump_ed(sed); 2099 ohci_dump_tds(xfer); 2100 } 2101 #endif 2102 splx(s); 2103 2104 return (USBD_IN_PROGRESS); 2105 2106 ret2: 2107 ohci_free_std(sc, xfer); 2108 ret1: 2109 return (r); 2110 } 2111 2112 /* Abort a device control request. */ 2113 void 2114 ohci_device_intr_abort(reqh) 2115 usbd_request_handle reqh; 2116 { 2117 /* XXX inactivate */ 2118 usb_delay_ms(reqh->pipe->device->bus, 1); /* make sure it is done */ 2119 if (reqh->pipe->intrreqh == reqh) { 2120 DPRINTF(("ohci_device_intr_abort: remove\n")); 2121 reqh->pipe->intrreqh = 0; 2122 ohci_intr_done((ohci_softc_t *)reqh->pipe->device->bus, reqh); 2123 } 2124 } 2125 2126 /* Close a device interrupt pipe. */ 2127 void 2128 ohci_device_intr_close(pipe) 2129 usbd_pipe_handle pipe; 2130 { 2131 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2132 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 2133 int nslots = opipe->u.intr.nslots; 2134 int pos = opipe->u.intr.pos; 2135 int j; 2136 ohci_soft_ed_t *p, *sed = opipe->sed; 2137 int s; 2138 2139 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n", 2140 pipe, nslots, pos)); 2141 s = splusb(); 2142 sed->ed->ed_flags |= LE(OHCI_ED_SKIP); 2143 if ((sed->ed->ed_tailp & LE(OHCI_TAILMASK)) != sed->ed->ed_headp) 2144 usb_delay_ms(&sc->sc_bus, 2); 2145 2146 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 2147 ; 2148 if (!p) 2149 panic("ohci_device_intr_close: ED not found\n"); 2150 p->next = sed->next; 2151 p->ed->ed_nexted = sed->ed->ed_nexted; 2152 splx(s); 2153 2154 for (j = 0; j < nslots; j++) 2155 --sc->sc_bws[pos * nslots + j]; 2156 2157 ohci_free_std(sc, opipe->tail); 2158 ohci_free_sed(sc, opipe->sed); 2159 /* XXX free other resources */ 2160 } 2161 2162 usbd_status 2163 ohci_device_setintr(sc, opipe, ival) 2164 ohci_softc_t *sc; 2165 struct ohci_pipe *opipe; 2166 int ival; 2167 { 2168 int i, j, s, best; 2169 u_int npoll, slow, shigh, nslots; 2170 u_int bestbw, bw; 2171 ohci_soft_ed_t *hsed, *sed = opipe->sed; 2172 2173 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe)); 2174 if (ival == 0) { 2175 printf("ohci_setintr: 0 interval\n"); 2176 return (USBD_INVAL); 2177 } 2178 2179 npoll = OHCI_NO_INTRS; 2180 while (npoll > ival) 2181 npoll /= 2; 2182 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll)); 2183 2184 /* 2185 * We now know which level in the tree the ED must go into. 2186 * Figure out which slot has most bandwidth left over. 2187 * Slots to examine: 2188 * npoll 2189 * 1 0 2190 * 2 1 2 2191 * 4 3 4 5 6 2192 * 8 7 8 9 10 11 12 13 14 2193 * N (N-1) .. (N-1+N-1) 2194 */ 2195 slow = npoll-1; 2196 shigh = slow + npoll; 2197 nslots = OHCI_NO_INTRS / npoll; 2198 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 2199 bw = 0; 2200 for (j = 0; j < nslots; j++) 2201 bw += sc->sc_bws[i * nslots + j]; 2202 if (bw < bestbw) { 2203 best = i; 2204 bestbw = bw; 2205 } 2206 } 2207 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n", 2208 best, slow, shigh, bestbw)); 2209 2210 s = splusb(); 2211 hsed = sc->sc_eds[best]; 2212 sed->next = hsed->next; 2213 sed->ed->ed_nexted = hsed->ed->ed_nexted; 2214 hsed->next = sed; 2215 hsed->ed->ed_nexted = LE(sed->physaddr); 2216 splx(s); 2217 2218 for (j = 0; j < nslots; j++) 2219 ++sc->sc_bws[best * nslots + j]; 2220 opipe->u.intr.nslots = nslots; 2221 opipe->u.intr.pos = best; 2222 2223 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe)); 2224 return (USBD_NORMAL_COMPLETION); 2225 } 2226 2227
Indexes created Wed Sep 24 15:09:51 GMT 2025