ohci.c revision 1.271
1 /* $NetBSD: ohci.c,v 1.271 2017/01/30 21:42:08 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * USB Open Host Controller driver. 38 * 39 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 40 * USB spec: http://www.usb.org/developers/docs/ 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.271 2017/01/30 21:42:08 skrll Exp $"); 45 46 #ifdef _KERNEL_OPT 47 #include "opt_usb.h" 48 #endif 49 50 #include <sys/param.h> 51 52 #include <sys/cpu.h> 53 #include <sys/device.h> 54 #include <sys/kernel.h> 55 #include <sys/kmem.h> 56 #include <sys/proc.h> 57 #include <sys/queue.h> 58 #include <sys/select.h> 59 #include <sys/sysctl.h> 60 #include <sys/systm.h> 61 62 #include <machine/endian.h> 63 64 #include <dev/usb/usb.h> 65 #include <dev/usb/usbdi.h> 66 #include <dev/usb/usbdivar.h> 67 #include <dev/usb/usb_mem.h> 68 #include <dev/usb/usb_quirks.h> 69 70 #include <dev/usb/ohcireg.h> 71 #include <dev/usb/ohcivar.h> 72 #include <dev/usb/usbroothub.h> 73 #include <dev/usb/usbhist.h> 74 75 #ifdef USB_DEBUG 76 #ifndef OHCI_DEBUG 77 #define ohcidebug 0 78 #else 79 static int ohcidebug = 10; 80 81 SYSCTL_SETUP(sysctl_hw_ohci_setup, "sysctl hw.ohci setup") 82 { 83 int err; 84 const struct sysctlnode *rnode; 85 const struct sysctlnode *cnode; 86 87 err = sysctl_createv(clog, 0, NULL, &rnode, 88 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ohci", 89 SYSCTL_DESCR("ohci global controls"), 90 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 91 92 if (err) 93 goto fail; 94 95 /* control debugging printfs */ 96 err = sysctl_createv(clog, 0, &rnode, &cnode, 97 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 98 "debug", SYSCTL_DESCR("Enable debugging output"), 99 NULL, 0, &ohcidebug, sizeof(ohcidebug), CTL_CREATE, CTL_EOL); 100 if (err) 101 goto fail; 102 103 return; 104 fail: 105 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 106 } 107 108 #endif /* OHCI_DEBUG */ 109 #endif /* USB_DEBUG */ 110 111 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ohcidebug,FMT,A,B,C,D) 112 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ohcidebug,N,FMT,A,B,C,D) 113 #define OHCIHIST_FUNC() USBHIST_FUNC() 114 #define OHCIHIST_CALLED(name) USBHIST_CALLED(ohcidebug) 115 116 #if BYTE_ORDER == BIG_ENDIAN 117 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 118 #else 119 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 120 #endif 121 122 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 123 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 124 #define HTOO16(val) O16TOH(val) 125 #define HTOO32(val) O32TOH(val) 126 127 struct ohci_pipe; 128 129 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 130 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 131 132 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 133 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 134 Static void ohci_free_std_locked(ohci_softc_t *, ohci_soft_td_t *); 135 136 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 137 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 138 Static void ohci_free_sitd_locked(ohci_softc_t *, 139 ohci_soft_itd_t *); 140 141 Static int ohci_alloc_std_chain(ohci_softc_t *, struct usbd_xfer *, 142 int, int); 143 Static void ohci_free_stds(ohci_softc_t *, struct ohci_xfer *); 144 145 Static void ohci_reset_std_chain(ohci_softc_t *, struct usbd_xfer *, 146 int, int, ohci_soft_td_t *, ohci_soft_td_t **); 147 148 Static usbd_status ohci_open(struct usbd_pipe *); 149 Static void ohci_poll(struct usbd_bus *); 150 Static void ohci_softintr(void *); 151 Static void ohci_rhsc(ohci_softc_t *, struct usbd_xfer *); 152 Static void ohci_rhsc_softint(void *); 153 154 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 155 ohci_soft_ed_t *); 156 157 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 158 ohci_soft_ed_t *); 159 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 160 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 161 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 162 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 163 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 164 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 165 166 Static usbd_status ohci_setup_isoc(struct usbd_pipe *); 167 Static void ohci_device_isoc_enter(struct usbd_xfer *); 168 169 Static struct usbd_xfer * 170 ohci_allocx(struct usbd_bus *, unsigned int); 171 Static void ohci_freex(struct usbd_bus *, struct usbd_xfer *); 172 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 173 Static int ohci_roothub_ctrl(struct usbd_bus *, 174 usb_device_request_t *, void *, int); 175 176 Static usbd_status ohci_root_intr_transfer(struct usbd_xfer *); 177 Static usbd_status ohci_root_intr_start(struct usbd_xfer *); 178 Static void ohci_root_intr_abort(struct usbd_xfer *); 179 Static void ohci_root_intr_close(struct usbd_pipe *); 180 Static void ohci_root_intr_done(struct usbd_xfer *); 181 182 Static int ohci_device_ctrl_init(struct usbd_xfer *); 183 Static void ohci_device_ctrl_fini(struct usbd_xfer *); 184 Static usbd_status ohci_device_ctrl_transfer(struct usbd_xfer *); 185 Static usbd_status ohci_device_ctrl_start(struct usbd_xfer *); 186 Static void ohci_device_ctrl_abort(struct usbd_xfer *); 187 Static void ohci_device_ctrl_close(struct usbd_pipe *); 188 Static void ohci_device_ctrl_done(struct usbd_xfer *); 189 190 Static int ohci_device_bulk_init(struct usbd_xfer *); 191 Static void ohci_device_bulk_fini(struct usbd_xfer *); 192 Static usbd_status ohci_device_bulk_transfer(struct usbd_xfer *); 193 Static usbd_status ohci_device_bulk_start(struct usbd_xfer *); 194 Static void ohci_device_bulk_abort(struct usbd_xfer *); 195 Static void ohci_device_bulk_close(struct usbd_pipe *); 196 Static void ohci_device_bulk_done(struct usbd_xfer *); 197 198 Static int ohci_device_intr_init(struct usbd_xfer *); 199 Static void ohci_device_intr_fini(struct usbd_xfer *); 200 Static usbd_status ohci_device_intr_transfer(struct usbd_xfer *); 201 Static usbd_status ohci_device_intr_start(struct usbd_xfer *); 202 Static void ohci_device_intr_abort(struct usbd_xfer *); 203 Static void ohci_device_intr_close(struct usbd_pipe *); 204 Static void ohci_device_intr_done(struct usbd_xfer *); 205 206 Static int ohci_device_isoc_init(struct usbd_xfer *); 207 Static void ohci_device_isoc_fini(struct usbd_xfer *); 208 Static usbd_status ohci_device_isoc_transfer(struct usbd_xfer *); 209 Static void ohci_device_isoc_abort(struct usbd_xfer *); 210 Static void ohci_device_isoc_close(struct usbd_pipe *); 211 Static void ohci_device_isoc_done(struct usbd_xfer *); 212 213 Static usbd_status ohci_device_setintr(ohci_softc_t *, 214 struct ohci_pipe *, int); 215 216 Static void ohci_timeout(void *); 217 Static void ohci_timeout_task(void *); 218 Static void ohci_rhsc_enable(void *); 219 220 Static void ohci_close_pipe(struct usbd_pipe *, ohci_soft_ed_t *); 221 Static void ohci_abort_xfer(struct usbd_xfer *, usbd_status); 222 223 Static void ohci_device_clear_toggle(struct usbd_pipe *); 224 Static void ohci_noop(struct usbd_pipe *); 225 226 #ifdef OHCI_DEBUG 227 Static void ohci_dumpregs(ohci_softc_t *); 228 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 229 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 230 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 231 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 232 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 233 #endif 234 235 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 236 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 237 #define OWRITE1(sc, r, x) \ 238 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 239 #define OWRITE2(sc, r, x) \ 240 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 241 #define OWRITE4(sc, r, x) \ 242 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 243 244 static __inline uint32_t 245 OREAD4(ohci_softc_t *sc, bus_size_t r) 246 { 247 248 OBARR(sc); 249 return bus_space_read_4(sc->iot, sc->ioh, r); 250 } 251 252 /* Reverse the bits in a value 0 .. 31 */ 253 Static uint8_t revbits[OHCI_NO_INTRS] = 254 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 255 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 256 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 257 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 258 259 struct ohci_pipe { 260 struct usbd_pipe pipe; 261 ohci_soft_ed_t *sed; 262 union { 263 ohci_soft_td_t *td; 264 ohci_soft_itd_t *itd; 265 } tail; 266 /* Info needed for different pipe kinds. */ 267 union { 268 /* Control pipe */ 269 struct { 270 usb_dma_t reqdma; 271 } ctrl; 272 /* Interrupt pipe */ 273 struct { 274 int nslots; 275 int pos; 276 } intr; 277 /* Isochronous pipe */ 278 struct isoc { 279 int next, inuse; 280 } isoc; 281 }; 282 }; 283 284 Static const struct usbd_bus_methods ohci_bus_methods = { 285 .ubm_open = ohci_open, 286 .ubm_softint = ohci_softintr, 287 .ubm_dopoll = ohci_poll, 288 .ubm_allocx = ohci_allocx, 289 .ubm_freex = ohci_freex, 290 .ubm_getlock = ohci_get_lock, 291 .ubm_rhctrl = ohci_roothub_ctrl, 292 }; 293 294 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 295 .upm_transfer = ohci_root_intr_transfer, 296 .upm_start = ohci_root_intr_start, 297 .upm_abort = ohci_root_intr_abort, 298 .upm_close = ohci_root_intr_close, 299 .upm_cleartoggle = ohci_noop, 300 .upm_done = ohci_root_intr_done, 301 }; 302 303 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 304 .upm_init = ohci_device_ctrl_init, 305 .upm_fini = ohci_device_ctrl_fini, 306 .upm_transfer = ohci_device_ctrl_transfer, 307 .upm_start = ohci_device_ctrl_start, 308 .upm_abort = ohci_device_ctrl_abort, 309 .upm_close = ohci_device_ctrl_close, 310 .upm_cleartoggle = ohci_noop, 311 .upm_done = ohci_device_ctrl_done, 312 }; 313 314 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 315 .upm_init = ohci_device_intr_init, 316 .upm_fini = ohci_device_intr_fini, 317 .upm_transfer = ohci_device_intr_transfer, 318 .upm_start = ohci_device_intr_start, 319 .upm_abort = ohci_device_intr_abort, 320 .upm_close = ohci_device_intr_close, 321 .upm_cleartoggle = ohci_device_clear_toggle, 322 .upm_done = ohci_device_intr_done, 323 }; 324 325 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 326 .upm_init = ohci_device_bulk_init, 327 .upm_fini = ohci_device_bulk_fini, 328 .upm_transfer = ohci_device_bulk_transfer, 329 .upm_start = ohci_device_bulk_start, 330 .upm_abort = ohci_device_bulk_abort, 331 .upm_close = ohci_device_bulk_close, 332 .upm_cleartoggle = ohci_device_clear_toggle, 333 .upm_done = ohci_device_bulk_done, 334 }; 335 336 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 337 .upm_init = ohci_device_isoc_init, 338 .upm_fini = ohci_device_isoc_fini, 339 .upm_transfer = ohci_device_isoc_transfer, 340 .upm_abort = ohci_device_isoc_abort, 341 .upm_close = ohci_device_isoc_close, 342 .upm_cleartoggle = ohci_noop, 343 .upm_done = ohci_device_isoc_done, 344 }; 345 346 int 347 ohci_activate(device_t self, enum devact act) 348 { 349 struct ohci_softc *sc = device_private(self); 350 351 switch (act) { 352 case DVACT_DEACTIVATE: 353 sc->sc_dying = 1; 354 return 0; 355 default: 356 return EOPNOTSUPP; 357 } 358 } 359 360 void 361 ohci_childdet(device_t self, device_t child) 362 { 363 struct ohci_softc *sc = device_private(self); 364 365 KASSERT(sc->sc_child == child); 366 sc->sc_child = NULL; 367 } 368 369 int 370 ohci_detach(struct ohci_softc *sc, int flags) 371 { 372 int rv = 0; 373 374 if (sc->sc_child != NULL) 375 rv = config_detach(sc->sc_child, flags); 376 377 if (rv != 0) 378 return rv; 379 380 callout_halt(&sc->sc_tmo_rhsc, &sc->sc_lock); 381 382 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 383 callout_destroy(&sc->sc_tmo_rhsc); 384 385 softint_disestablish(sc->sc_rhsc_si); 386 387 cv_destroy(&sc->sc_softwake_cv); 388 389 mutex_destroy(&sc->sc_lock); 390 mutex_destroy(&sc->sc_intr_lock); 391 392 if (sc->sc_hcca != NULL) 393 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 394 pool_cache_destroy(sc->sc_xferpool); 395 396 return rv; 397 } 398 399 ohci_soft_ed_t * 400 ohci_alloc_sed(ohci_softc_t *sc) 401 { 402 ohci_soft_ed_t *sed; 403 usbd_status err; 404 int i, offs; 405 usb_dma_t dma; 406 407 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 408 409 mutex_enter(&sc->sc_lock); 410 if (sc->sc_freeeds == NULL) { 411 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 412 mutex_exit(&sc->sc_lock); 413 414 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 415 OHCI_ED_ALIGN, &dma); 416 if (err) 417 return 0; 418 419 mutex_enter(&sc->sc_lock); 420 for (i = 0; i < OHCI_SED_CHUNK; i++) { 421 offs = i * OHCI_SED_SIZE; 422 sed = KERNADDR(&dma, offs); 423 sed->physaddr = DMAADDR(&dma, offs); 424 sed->dma = dma; 425 sed->offs = offs; 426 sed->next = sc->sc_freeeds; 427 sc->sc_freeeds = sed; 428 } 429 } 430 sed = sc->sc_freeeds; 431 sc->sc_freeeds = sed->next; 432 mutex_exit(&sc->sc_lock); 433 434 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 435 sed->next = 0; 436 return sed; 437 } 438 439 static inline void 440 ohci_free_sed_locked(ohci_softc_t *sc, ohci_soft_ed_t *sed) 441 { 442 443 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 444 445 sed->next = sc->sc_freeeds; 446 sc->sc_freeeds = sed; 447 } 448 449 void 450 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 451 { 452 453 mutex_enter(&sc->sc_lock); 454 ohci_free_sed_locked(sc, sed); 455 mutex_exit(&sc->sc_lock); 456 } 457 458 ohci_soft_td_t * 459 ohci_alloc_std(ohci_softc_t *sc) 460 { 461 ohci_soft_td_t *std; 462 usbd_status err; 463 int i, offs; 464 usb_dma_t dma; 465 466 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 467 468 mutex_enter(&sc->sc_lock); 469 if (sc->sc_freetds == NULL) { 470 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 471 mutex_exit(&sc->sc_lock); 472 473 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 474 OHCI_TD_ALIGN, &dma); 475 if (err) 476 return NULL; 477 478 mutex_enter(&sc->sc_lock); 479 for (i = 0; i < OHCI_STD_CHUNK; i++) { 480 offs = i * OHCI_STD_SIZE; 481 std = KERNADDR(&dma, offs); 482 std->physaddr = DMAADDR(&dma, offs); 483 std->dma = dma; 484 std->offs = offs; 485 std->nexttd = sc->sc_freetds; 486 sc->sc_freetds = std; 487 } 488 } 489 490 std = sc->sc_freetds; 491 sc->sc_freetds = std->nexttd; 492 mutex_exit(&sc->sc_lock); 493 494 memset(&std->td, 0, sizeof(ohci_td_t)); 495 std->nexttd = NULL; 496 std->xfer = NULL; 497 498 return std; 499 } 500 501 void 502 ohci_free_std_locked(ohci_softc_t *sc, ohci_soft_td_t *std) 503 { 504 505 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 506 507 std->nexttd = sc->sc_freetds; 508 sc->sc_freetds = std; 509 } 510 511 void 512 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 513 { 514 515 mutex_enter(&sc->sc_lock); 516 ohci_free_std_locked(sc, std); 517 mutex_exit(&sc->sc_lock); 518 } 519 520 Static int 521 ohci_alloc_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, int length, int rd) 522 { 523 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 524 uint16_t flags = xfer->ux_flags; 525 526 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 527 528 DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d", 529 xfer->ux_pipe->up_dev->ud_addr, 530 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 531 length, xfer->ux_pipe->up_dev->ud_speed); 532 533 ASSERT_SLEEPABLE(); 534 KASSERT(length != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 535 536 size_t nstd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 537 nstd += ((length + OHCI_PAGE_SIZE - 1) / OHCI_PAGE_SIZE); 538 ox->ox_stds = kmem_zalloc(sizeof(ohci_soft_td_t *) * nstd, 539 KM_SLEEP); 540 ox->ox_nstd = nstd; 541 542 DPRINTFN(8, "xfer %p nstd %d", xfer, nstd, 0, 0); 543 544 for (size_t j = 0; j < ox->ox_nstd;) { 545 ohci_soft_td_t *cur = ohci_alloc_std(sc); 546 if (cur == NULL) 547 goto nomem; 548 549 ox->ox_stds[j++] = cur; 550 cur->xfer = xfer; 551 cur->flags = 0; 552 } 553 554 return 0; 555 556 nomem: 557 ohci_free_stds(sc, ox); 558 kmem_free(ox->ox_stds, sizeof(ohci_soft_td_t *) * nstd); 559 560 return ENOMEM; 561 } 562 563 Static void 564 ohci_free_stds(ohci_softc_t *sc, struct ohci_xfer *ox) 565 { 566 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 567 DPRINTF("ox=%p", ox, 0, 0, 0); 568 569 mutex_enter(&sc->sc_lock); 570 for (size_t i = 0; i < ox->ox_nstd; i++) { 571 ohci_soft_td_t *std = ox->ox_stds[i]; 572 if (std == NULL) 573 break; 574 ohci_free_std_locked(sc, std); 575 } 576 mutex_exit(&sc->sc_lock); 577 } 578 579 void 580 ohci_reset_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, 581 int alen, int rd, ohci_soft_td_t *sp, ohci_soft_td_t **ep) 582 { 583 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 584 ohci_soft_td_t *next, *cur; 585 int len, curlen; 586 usb_dma_t *dma = &xfer->ux_dmabuf; 587 uint16_t flags = xfer->ux_flags; 588 589 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 590 DPRINTF("start len=%d", alen, 0, 0, 0); 591 592 KASSERT(mutex_owned(&sc->sc_lock)); 593 594 DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d", 595 xfer->ux_pipe->up_dev->ud_addr, 596 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 597 alen, xfer->ux_pipe->up_dev->ud_speed); 598 599 KASSERT(sp); 600 601 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 602 603 /* 604 * Assign next for the len == 0 case where we don't go through the 605 * main loop. 606 */ 607 len = alen; 608 cur = next = sp; 609 610 usb_syncmem(dma, 0, len, 611 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 612 const uint32_t tdflags = HTOO32( 613 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 614 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 615 616 size_t curoffs = 0; 617 for (size_t j = 1; len != 0;) { 618 if (j == ox->ox_nstd) 619 next = NULL; 620 else 621 next = ox->ox_stds[j++]; 622 KASSERT(next != cur); 623 624 curlen = 0; 625 const ohci_physaddr_t sdataphys = DMAADDR(dma, curoffs); 626 ohci_physaddr_t edataphys = DMAADDR(dma, curoffs + len - 1); 627 628 const ohci_physaddr_t sphyspg = OHCI_PAGE(sdataphys); 629 ohci_physaddr_t ephyspg = OHCI_PAGE(edataphys); 630 /* 631 * The OHCI hardware can handle at most one page 632 * crossing per TD 633 */ 634 curlen = len; 635 if (sphyspg != ephyspg && 636 sphyspg + OHCI_PAGE_SIZE != ephyspg) { 637 /* must use multiple TDs, fill as much as possible. */ 638 curlen = 2 * OHCI_PAGE_SIZE - 639 OHCI_PAGE_OFFSET(sdataphys); 640 /* the length must be a multiple of the max size */ 641 curlen -= curlen % mps; 642 edataphys = DMAADDR(dma, curoffs + curlen - 1); 643 } 644 KASSERT(curlen != 0); 645 DPRINTFN(4, "sdataphys=0x%08x edataphys=0x%08x " 646 "len=%d curlen=%d", sdataphys, edataphys, len, curlen); 647 648 cur->td.td_flags = tdflags; 649 cur->td.td_cbp = HTOO32(sdataphys); 650 cur->td.td_be = HTOO32(edataphys); 651 cur->td.td_nexttd = (next != NULL) ? HTOO32(next->physaddr) : 0; 652 cur->nexttd = next; 653 cur->len = curlen; 654 cur->flags = OHCI_ADD_LEN; 655 cur->xfer = xfer; 656 ohci_hash_add_td(sc, cur); 657 658 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 659 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 660 661 curoffs += curlen; 662 len -= curlen; 663 664 if (len != 0) { 665 KASSERT(next != NULL); 666 DPRINTFN(10, "extend chain", 0, 0, 0, 0); 667 cur = next; 668 } 669 } 670 cur->td.td_flags |= 671 HTOO32(xfer->ux_flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0); 672 673 if (!rd && 674 (flags & USBD_FORCE_SHORT_XFER) && 675 alen % mps == 0) { 676 /* Force a 0 length transfer at the end. */ 677 678 KASSERT(next != NULL); 679 cur = next; 680 681 cur->td.td_flags = tdflags; 682 cur->td.td_cbp = 0; /* indicate 0 length packet */ 683 cur->td.td_nexttd = 0; 684 cur->td.td_be = ~0; 685 cur->nexttd = NULL; 686 cur->len = 0; 687 cur->flags = 0; 688 cur->xfer = xfer; 689 ohci_hash_add_td(sc, cur); 690 691 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 692 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 693 DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0); 694 } 695 *ep = cur; 696 } 697 698 ohci_soft_itd_t * 699 ohci_alloc_sitd(ohci_softc_t *sc) 700 { 701 ohci_soft_itd_t *sitd; 702 usbd_status err; 703 int i, offs; 704 usb_dma_t dma; 705 706 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 707 708 mutex_enter(&sc->sc_lock); 709 if (sc->sc_freeitds == NULL) { 710 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 711 mutex_exit(&sc->sc_lock); 712 713 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 714 OHCI_ITD_ALIGN, &dma); 715 if (err) 716 return NULL; 717 mutex_enter(&sc->sc_lock); 718 for (i = 0; i < OHCI_SITD_CHUNK; i++) { 719 offs = i * OHCI_SITD_SIZE; 720 sitd = KERNADDR(&dma, offs); 721 sitd->physaddr = DMAADDR(&dma, offs); 722 sitd->dma = dma; 723 sitd->offs = offs; 724 sitd->nextitd = sc->sc_freeitds; 725 sc->sc_freeitds = sitd; 726 } 727 } 728 729 sitd = sc->sc_freeitds; 730 sc->sc_freeitds = sitd->nextitd; 731 mutex_exit(&sc->sc_lock); 732 733 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 734 sitd->nextitd = NULL; 735 sitd->xfer = NULL; 736 737 #ifdef DIAGNOSTIC 738 sitd->isdone = true; 739 #endif 740 741 return sitd; 742 } 743 744 Static void 745 ohci_free_sitd_locked(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 746 { 747 748 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 749 DPRINTFN(10, "sitd=%p", sitd, 0, 0, 0); 750 751 KASSERT(sitd->isdone); 752 #ifdef DIAGNOSTIC 753 /* Warn double free */ 754 sitd->isdone = false; 755 #endif 756 757 sitd->nextitd = sc->sc_freeitds; 758 sc->sc_freeitds = sitd; 759 } 760 761 void 762 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 763 { 764 765 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 766 767 mutex_enter(&sc->sc_lock); 768 ohci_free_sitd_locked(sc, sitd); 769 mutex_exit(&sc->sc_lock); 770 } 771 772 int 773 ohci_init(ohci_softc_t *sc) 774 { 775 ohci_soft_ed_t *sed, *psed; 776 usbd_status err; 777 int i; 778 uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */; 779 780 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 781 782 aprint_normal_dev(sc->sc_dev, ""); 783 784 sc->sc_hcca = NULL; 785 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 786 787 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 788 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 789 cv_init(&sc->sc_softwake_cv, "ohciab"); 790 791 sc->sc_rhsc_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 792 ohci_rhsc_softint, sc); 793 794 for (i = 0; i < OHCI_HASH_SIZE; i++) 795 LIST_INIT(&sc->sc_hash_tds[i]); 796 for (i = 0; i < OHCI_HASH_SIZE; i++) 797 LIST_INIT(&sc->sc_hash_itds[i]); 798 799 sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0, 800 "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL); 801 802 rev = OREAD4(sc, OHCI_REVISION); 803 aprint_normal("OHCI version %d.%d%s\n", 804 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 805 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 806 807 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 808 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 809 sc->sc_bus.ub_revision = USBREV_UNKNOWN; 810 return -1; 811 } 812 sc->sc_bus.ub_revision = USBREV_1_0; 813 sc->sc_bus.ub_usedma = true; 814 815 /* XXX determine alignment by R/W */ 816 /* Allocate the HCCA area. */ 817 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 818 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 819 if (err) { 820 sc->sc_hcca = NULL; 821 return err; 822 } 823 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 824 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 825 826 sc->sc_eintrs = OHCI_NORMAL_INTRS; 827 828 /* Allocate dummy ED that starts the control list. */ 829 sc->sc_ctrl_head = ohci_alloc_sed(sc); 830 if (sc->sc_ctrl_head == NULL) { 831 err = ENOMEM; 832 goto bad1; 833 } 834 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 835 836 /* Allocate dummy ED that starts the bulk list. */ 837 sc->sc_bulk_head = ohci_alloc_sed(sc); 838 if (sc->sc_bulk_head == NULL) { 839 err = ENOMEM; 840 goto bad2; 841 } 842 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 843 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 844 sizeof(sc->sc_bulk_head->ed), 845 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 846 847 /* Allocate dummy ED that starts the isochronous list. */ 848 sc->sc_isoc_head = ohci_alloc_sed(sc); 849 if (sc->sc_isoc_head == NULL) { 850 err = ENOMEM; 851 goto bad3; 852 } 853 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 854 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 855 sizeof(sc->sc_isoc_head->ed), 856 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 857 858 /* Allocate all the dummy EDs that make up the interrupt tree. */ 859 for (i = 0; i < OHCI_NO_EDS; i++) { 860 sed = ohci_alloc_sed(sc); 861 if (sed == NULL) { 862 while (--i >= 0) 863 ohci_free_sed(sc, sc->sc_eds[i]); 864 err = ENOMEM; 865 goto bad4; 866 } 867 /* All ED fields are set to 0. */ 868 sc->sc_eds[i] = sed; 869 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 870 if (i != 0) 871 psed = sc->sc_eds[(i-1) / 2]; 872 else 873 psed= sc->sc_isoc_head; 874 sed->next = psed; 875 sed->ed.ed_nexted = HTOO32(psed->physaddr); 876 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 877 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 878 } 879 /* 880 * Fill HCCA interrupt table. The bit reversal is to get 881 * the tree set up properly to spread the interrupts. 882 */ 883 for (i = 0; i < OHCI_NO_INTRS; i++) 884 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 885 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 886 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 887 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 888 889 #ifdef OHCI_DEBUG 890 DPRINTFN(15, "--- dump start ---", 0, 0, 0 ,0); 891 if (ohcidebug >= 15) { 892 for (i = 0; i < OHCI_NO_EDS; i++) { 893 DPRINTFN(15, "ed#%d ", i, 0, 0, 0); 894 ohci_dump_ed(sc, sc->sc_eds[i]); 895 } 896 DPRINTFN(15, "iso", 0, 0, 0 ,0); 897 ohci_dump_ed(sc, sc->sc_isoc_head); 898 } 899 DPRINTFN(15, "--- dump end ---", 0, 0, 0 ,0); 900 #endif 901 902 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 903 ctl = OREAD4(sc, OHCI_CONTROL); 904 rwc = ctl & OHCI_RWC; 905 fm = OREAD4(sc, OHCI_FM_INTERVAL); 906 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 907 /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */ 908 909 /* Determine in what context we are running. */ 910 if (ctl & OHCI_IR) { 911 /* SMM active, request change */ 912 DPRINTF("SMM active, request owner change", 0, 0, 0, 0); 913 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 914 (OHCI_OC | OHCI_MIE)) 915 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 916 s = OREAD4(sc, OHCI_COMMAND_STATUS); 917 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 918 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 919 usb_delay_ms(&sc->sc_bus, 1); 920 ctl = OREAD4(sc, OHCI_CONTROL); 921 } 922 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 923 if ((ctl & OHCI_IR) == 0) { 924 aprint_error_dev(sc->sc_dev, 925 "SMM does not respond, resetting\n"); 926 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 927 goto reset; 928 } 929 #if 0 930 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 931 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 932 /* BIOS started controller. */ 933 DPRINTF("BIOS active", 0, 0, 0, 0); 934 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 935 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 936 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 937 } 938 #endif 939 } else { 940 DPRINTF("cold started", 0 ,0 ,0 ,0); 941 reset: 942 /* Controller was cold started. */ 943 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 944 } 945 946 /* 947 * This reset should not be necessary according to the OHCI spec, but 948 * without it some controllers do not start. 949 */ 950 DPRINTF("sc %p: resetting", sc, 0, 0, 0); 951 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 952 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 953 954 /* We now own the host controller and the bus has been reset. */ 955 956 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 957 /* Nominal time for a reset is 10 us. */ 958 for (i = 0; i < 10; i++) { 959 delay(10); 960 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 961 if (!hcr) 962 break; 963 } 964 if (hcr) { 965 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 966 err = EIO; 967 goto bad5; 968 } 969 #ifdef OHCI_DEBUG 970 if (ohcidebug >= 15) 971 ohci_dumpregs(sc); 972 #endif 973 974 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 975 976 /* Set up HC registers. */ 977 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 978 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 979 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 980 /* disable all interrupts and then switch on all desired interrupts */ 981 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 982 /* switch on desired functional features */ 983 ctl = OREAD4(sc, OHCI_CONTROL); 984 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 985 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 986 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 987 /* And finally start it! */ 988 OWRITE4(sc, OHCI_CONTROL, ctl); 989 990 /* 991 * The controller is now OPERATIONAL. Set a some final 992 * registers that should be set earlier, but that the 993 * controller ignores when in the SUSPEND state. 994 */ 995 ival = OHCI_GET_IVAL(fm); 996 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 997 fm |= OHCI_FSMPS(ival) | ival; 998 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 999 per = OHCI_PERIODIC(ival); /* 90% periodic */ 1000 OWRITE4(sc, OHCI_PERIODIC_START, per); 1001 1002 if (sc->sc_flags & OHCIF_SUPERIO) { 1003 /* no overcurrent protection */ 1004 desca |= OHCI_NOCP; 1005 /* 1006 * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning 1007 * that 1008 * - ports are always power switched 1009 * - don't wait for powered root hub port 1010 */ 1011 desca &= ~(__SHIFTIN(0xff, OHCI_POTPGT_MASK) | OHCI_NPS); 1012 } 1013 1014 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 1015 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 1016 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 1017 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 1018 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 1019 1020 /* 1021 * The AMD756 requires a delay before re-reading the register, 1022 * otherwise it will occasionally report 0 ports. 1023 */ 1024 sc->sc_noport = 0; 1025 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 1026 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 1027 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 1028 } 1029 1030 #ifdef OHCI_DEBUG 1031 if (ohcidebug >= 5) 1032 ohci_dumpregs(sc); 1033 #endif 1034 1035 /* Set up the bus struct. */ 1036 sc->sc_bus.ub_methods = &ohci_bus_methods; 1037 sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe); 1038 1039 sc->sc_control = sc->sc_intre = 0; 1040 1041 /* Finally, turn on interrupts. */ 1042 DPRINTF("enabling %#x", sc->sc_eintrs | OHCI_MIE, 0, 0, 0); 1043 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 1044 1045 return 0; 1046 1047 bad5: 1048 for (i = 0; i < OHCI_NO_EDS; i++) 1049 ohci_free_sed(sc, sc->sc_eds[i]); 1050 bad4: 1051 ohci_free_sed(sc, sc->sc_isoc_head); 1052 bad3: 1053 ohci_free_sed(sc, sc->sc_bulk_head); 1054 bad2: 1055 ohci_free_sed(sc, sc->sc_ctrl_head); 1056 bad1: 1057 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 1058 sc->sc_hcca = NULL; 1059 return err; 1060 } 1061 1062 struct usbd_xfer * 1063 ohci_allocx(struct usbd_bus *bus, unsigned int nframes) 1064 { 1065 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1066 struct usbd_xfer *xfer; 1067 1068 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1069 if (xfer != NULL) { 1070 memset(xfer, 0, sizeof(struct ohci_xfer)); 1071 #ifdef DIAGNOSTIC 1072 xfer->ux_state = XFER_BUSY; 1073 #endif 1074 } 1075 return xfer; 1076 } 1077 1078 void 1079 ohci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1080 { 1081 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1082 1083 KASSERTMSG(xfer->ux_state == XFER_BUSY, 1084 "xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state); 1085 #ifdef DIAGNOSTIC 1086 xfer->ux_state = XFER_FREE; 1087 #endif 1088 pool_cache_put(sc->sc_xferpool, xfer); 1089 } 1090 1091 Static void 1092 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1093 { 1094 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1095 1096 *lock = &sc->sc_lock; 1097 } 1098 1099 /* 1100 * Shut down the controller when the system is going down. 1101 */ 1102 bool 1103 ohci_shutdown(device_t self, int flags) 1104 { 1105 ohci_softc_t *sc = device_private(self); 1106 1107 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1108 1109 DPRINTF("stopping the HC", 0, 0, 0, 0); 1110 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1111 return true; 1112 } 1113 1114 bool 1115 ohci_resume(device_t dv, const pmf_qual_t *qual) 1116 { 1117 ohci_softc_t *sc = device_private(dv); 1118 uint32_t ctl; 1119 1120 mutex_spin_enter(&sc->sc_intr_lock); 1121 sc->sc_bus.ub_usepolling++; 1122 mutex_spin_exit(&sc->sc_intr_lock); 1123 1124 /* Some broken BIOSes do not recover these values */ 1125 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1126 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1127 sc->sc_ctrl_head->physaddr); 1128 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1129 sc->sc_bulk_head->physaddr); 1130 if (sc->sc_intre) 1131 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1132 (OHCI_ALL_INTRS | OHCI_MIE)); 1133 if (sc->sc_control) 1134 ctl = sc->sc_control; 1135 else 1136 ctl = OREAD4(sc, OHCI_CONTROL); 1137 ctl |= OHCI_HCFS_RESUME; 1138 OWRITE4(sc, OHCI_CONTROL, ctl); 1139 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1140 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1141 OWRITE4(sc, OHCI_CONTROL, ctl); 1142 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1143 sc->sc_control = sc->sc_intre = 0; 1144 1145 mutex_spin_enter(&sc->sc_intr_lock); 1146 sc->sc_bus.ub_usepolling--; 1147 mutex_spin_exit(&sc->sc_intr_lock); 1148 1149 return true; 1150 } 1151 1152 bool 1153 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1154 { 1155 ohci_softc_t *sc = device_private(dv); 1156 uint32_t ctl; 1157 1158 mutex_spin_enter(&sc->sc_intr_lock); 1159 sc->sc_bus.ub_usepolling++; 1160 mutex_spin_exit(&sc->sc_intr_lock); 1161 1162 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1163 if (sc->sc_control == 0) { 1164 /* 1165 * Preserve register values, in case that BIOS 1166 * does not recover them. 1167 */ 1168 sc->sc_control = ctl; 1169 sc->sc_intre = OREAD4(sc, 1170 OHCI_INTERRUPT_ENABLE); 1171 } 1172 ctl |= OHCI_HCFS_SUSPEND; 1173 OWRITE4(sc, OHCI_CONTROL, ctl); 1174 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1175 1176 mutex_spin_enter(&sc->sc_intr_lock); 1177 sc->sc_bus.ub_usepolling--; 1178 mutex_spin_exit(&sc->sc_intr_lock); 1179 1180 return true; 1181 } 1182 1183 #ifdef OHCI_DEBUG 1184 void 1185 ohci_dumpregs(ohci_softc_t *sc) 1186 { 1187 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1188 1189 DPRINTF("rev=0x%08x control=0x%08x command=0x%08x", 1190 OREAD4(sc, OHCI_REVISION), 1191 OREAD4(sc, OHCI_CONTROL), 1192 OREAD4(sc, OHCI_COMMAND_STATUS), 0); 1193 DPRINTF(" intrstat=0x%08x intre=0x%08x intrd=0x%08x", 1194 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1195 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1196 OREAD4(sc, OHCI_INTERRUPT_DISABLE), 0); 1197 DPRINTF(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x", 1198 OREAD4(sc, OHCI_HCCA), 1199 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1200 OREAD4(sc, OHCI_CONTROL_HEAD_ED), 0); 1201 DPRINTF(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x", 1202 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1203 OREAD4(sc, OHCI_BULK_HEAD_ED), 1204 OREAD4(sc, OHCI_BULK_CURRENT_ED) ,0); 1205 DPRINTF(" done=0x%08x fmival=0x%08x fmrem=0x%08x", 1206 OREAD4(sc, OHCI_DONE_HEAD), 1207 OREAD4(sc, OHCI_FM_INTERVAL), 1208 OREAD4(sc, OHCI_FM_REMAINING), 0); 1209 DPRINTF(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x", 1210 OREAD4(sc, OHCI_FM_NUMBER), 1211 OREAD4(sc, OHCI_PERIODIC_START), 1212 OREAD4(sc, OHCI_LS_THRESHOLD), 0); 1213 DPRINTF(" desca=0x%08x descb=0x%08x stat=0x%08x", 1214 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1215 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1216 OREAD4(sc, OHCI_RH_STATUS), 0); 1217 DPRINTF(" port1=0x%08x port2=0x%08x", 1218 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1219 OREAD4(sc, OHCI_RH_PORT_STATUS(2)), 0, 0); 1220 DPRINTF(" HCCA: frame_number=0x%04x done_head=0x%08x", 1221 O32TOH(sc->sc_hcca->hcca_frame_number), 1222 O32TOH(sc->sc_hcca->hcca_done_head), 0, 0); 1223 } 1224 #endif 1225 1226 Static int ohci_intr1(ohci_softc_t *); 1227 1228 int 1229 ohci_intr(void *p) 1230 { 1231 ohci_softc_t *sc = p; 1232 int ret = 0; 1233 1234 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1235 1236 if (sc == NULL) 1237 return 0; 1238 1239 mutex_spin_enter(&sc->sc_intr_lock); 1240 1241 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1242 goto done; 1243 1244 /* If we get an interrupt while polling, then just ignore it. */ 1245 if (sc->sc_bus.ub_usepolling) { 1246 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1247 /* for level triggered intrs, should do something to ack */ 1248 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1249 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1250 1251 goto done; 1252 } 1253 1254 ret = ohci_intr1(sc); 1255 1256 done: 1257 mutex_spin_exit(&sc->sc_intr_lock); 1258 return ret; 1259 } 1260 1261 Static int 1262 ohci_intr1(ohci_softc_t *sc) 1263 { 1264 uint32_t intrs, eintrs; 1265 1266 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1267 1268 /* In case the interrupt occurs before initialization has completed. */ 1269 if (sc == NULL || sc->sc_hcca == NULL) { 1270 #ifdef DIAGNOSTIC 1271 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1272 #endif 1273 return 0; 1274 } 1275 1276 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1277 1278 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1279 if (!intrs) 1280 return 0; 1281 1282 /* Acknowledge */ 1283 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); 1284 eintrs = intrs & sc->sc_eintrs; 1285 DPRINTFN(7, "sc=%p", sc, 0, 0, 0); 1286 DPRINTFN(7, "intrs=%#x(%#x) eintrs=%#x(%#x)", 1287 intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), eintrs, 1288 sc->sc_eintrs); 1289 1290 if (!eintrs) { 1291 return 0; 1292 } 1293 1294 if (eintrs & OHCI_SO) { 1295 sc->sc_overrun_cnt++; 1296 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1297 printf("%s: %u scheduling overruns\n", 1298 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1299 sc->sc_overrun_cnt = 0; 1300 } 1301 /* XXX do what */ 1302 eintrs &= ~OHCI_SO; 1303 } 1304 if (eintrs & OHCI_WDH) { 1305 /* 1306 * We block the interrupt below, and reenable it later from 1307 * ohci_softintr(). 1308 */ 1309 usb_schedsoftintr(&sc->sc_bus); 1310 } 1311 if (eintrs & OHCI_RD) { 1312 DPRINTFN(5, "resume detect", sc, 0, 0, 0); 1313 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1314 /* XXX process resume detect */ 1315 } 1316 if (eintrs & OHCI_UE) { 1317 DPRINTFN(5, "unrecoverable error", sc, 0, 0, 0); 1318 printf("%s: unrecoverable error, controller halted\n", 1319 device_xname(sc->sc_dev)); 1320 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1321 /* XXX what else */ 1322 } 1323 if (eintrs & OHCI_RHSC) { 1324 /* 1325 * We block the interrupt below, and reenable it later from 1326 * a timeout. 1327 */ 1328 softint_schedule(sc->sc_rhsc_si); 1329 } 1330 1331 if (eintrs != 0) { 1332 /* Block unprocessed interrupts. */ 1333 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1334 sc->sc_eintrs &= ~eintrs; 1335 DPRINTF("sc %p blocking intrs 0x%x", sc, eintrs, 0, 0); 1336 } 1337 1338 return 1; 1339 } 1340 1341 void 1342 ohci_rhsc_enable(void *v_sc) 1343 { 1344 ohci_softc_t *sc = v_sc; 1345 1346 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1347 DPRINTF("sc %p", sc, 0, 0, 0); 1348 mutex_spin_enter(&sc->sc_intr_lock); 1349 sc->sc_eintrs |= OHCI_RHSC; 1350 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1351 mutex_spin_exit(&sc->sc_intr_lock); 1352 } 1353 1354 #ifdef OHCI_DEBUG 1355 const char *ohci_cc_strs[] = { 1356 "NO_ERROR", 1357 "CRC", 1358 "BIT_STUFFING", 1359 "DATA_TOGGLE_MISMATCH", 1360 "STALL", 1361 "DEVICE_NOT_RESPONDING", 1362 "PID_CHECK_FAILURE", 1363 "UNEXPECTED_PID", 1364 "DATA_OVERRUN", 1365 "DATA_UNDERRUN", 1366 "BUFFER_OVERRUN", 1367 "BUFFER_UNDERRUN", 1368 "reserved", 1369 "reserved", 1370 "NOT_ACCESSED", 1371 "NOT_ACCESSED", 1372 }; 1373 #endif 1374 1375 void 1376 ohci_softintr(void *v) 1377 { 1378 struct usbd_bus *bus = v; 1379 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1380 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1381 ohci_soft_td_t *std, *sdone, *stdnext; 1382 struct usbd_xfer *xfer; 1383 struct ohci_pipe *opipe; 1384 int len, cc; 1385 int i, j, actlen, iframes, uedir; 1386 ohci_physaddr_t done; 1387 1388 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1389 1390 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1391 1392 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1393 sizeof(sc->sc_hcca->hcca_done_head), 1394 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1395 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1396 sc->sc_hcca->hcca_done_head = 0; 1397 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1398 sizeof(sc->sc_hcca->hcca_done_head), 1399 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1400 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1401 sc->sc_eintrs |= OHCI_WDH; 1402 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1403 1404 /* Reverse the done list. */ 1405 for (sdone = NULL, sidone = NULL; done != 0; ) { 1406 std = ohci_hash_find_td(sc, done); 1407 if (std != NULL) { 1408 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1409 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1410 std->dnext = sdone; 1411 done = O32TOH(std->td.td_nexttd); 1412 sdone = std; 1413 DPRINTFN(10, "add TD %p", std, 0, 0, 0); 1414 continue; 1415 } 1416 sitd = ohci_hash_find_itd(sc, done); 1417 if (sitd != NULL) { 1418 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1419 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1420 sitd->dnext = sidone; 1421 done = O32TOH(sitd->itd.itd_nextitd); 1422 sidone = sitd; 1423 DPRINTFN(5, "add ITD %p", sitd, 0, 0, 0); 1424 continue; 1425 } 1426 DPRINTFN(10, "addr %p not found", done, 0, 0, 0); 1427 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1428 (u_long)done); 1429 break; 1430 } 1431 1432 DPRINTFN(10, "sdone=%p sidone=%p", sdone, sidone, 0, 0); 1433 DPRINTFN(10, "--- TD dump start ---", 0, 0, 0, 0); 1434 #ifdef OHCI_DEBUG 1435 if (ohcidebug >= 10) { 1436 for (std = sdone; std; std = std->dnext) 1437 ohci_dump_td(sc, std); 1438 } 1439 #endif 1440 DPRINTFN(10, "--- TD dump end ---", 0, 0, 0, 0); 1441 1442 for (std = sdone; std; std = stdnext) { 1443 xfer = std->xfer; 1444 stdnext = std->dnext; 1445 DPRINTFN(10, "std=%p xfer=%p hcpriv=%p", std, xfer, 1446 xfer ? xfer->ux_hcpriv : 0, 0); 1447 if (xfer == NULL) { 1448 /* 1449 * xfer == NULL: There seems to be no xfer associated 1450 * with this TD. It is tailp that happened to end up on 1451 * the done queue. 1452 * Shouldn't happen, but some chips are broken(?). 1453 */ 1454 continue; 1455 } 1456 if (xfer->ux_status == USBD_CANCELLED || 1457 xfer->ux_status == USBD_TIMEOUT) { 1458 DPRINTF("cancel/timeout %p", xfer, 0, 0, 0); 1459 /* Handled by abort routine. */ 1460 continue; 1461 } 1462 callout_stop(&xfer->ux_callout); 1463 1464 len = std->len; 1465 if (std->td.td_cbp != 0) 1466 len -= O32TOH(std->td.td_be) - 1467 O32TOH(std->td.td_cbp) + 1; 1468 DPRINTFN(10, "len=%d, flags=0x%x", len, std->flags, 0, 0); 1469 if (std->flags & OHCI_ADD_LEN) 1470 xfer->ux_actlen += len; 1471 1472 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1473 if (cc == OHCI_CC_NO_ERROR) { 1474 ohci_hash_rem_td(sc, std); 1475 if (std->flags & OHCI_CALL_DONE) { 1476 xfer->ux_status = USBD_NORMAL_COMPLETION; 1477 usb_transfer_complete(xfer); 1478 } 1479 } else { 1480 /* 1481 * Endpoint is halted. First unlink all the TDs 1482 * belonging to the failed transfer, and then restart 1483 * the endpoint. 1484 */ 1485 ohci_soft_td_t *p, *n; 1486 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1487 1488 DPRINTFN(10, "error cc=%d", cc, 0, 0, 0); 1489 1490 /* remove xfer's TDs from the hash */ 1491 for (p = std; p->xfer == xfer; p = n) { 1492 n = p->nexttd; 1493 ohci_hash_rem_td(sc, p); 1494 } 1495 1496 ohci_soft_ed_t *sed = opipe->sed; 1497 1498 /* clear halt and TD chain */ 1499 sed->ed.ed_headp = HTOO32(p->physaddr); 1500 usb_syncmem(&sed->dma, 1501 sed->offs + offsetof(ohci_ed_t, ed_headp), 1502 sizeof(sed->ed.ed_headp), 1503 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1504 1505 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1506 1507 if (cc == OHCI_CC_DATA_UNDERRUN) 1508 xfer->ux_status = USBD_NORMAL_COMPLETION; 1509 else if (cc == OHCI_CC_STALL) 1510 xfer->ux_status = USBD_STALLED; 1511 else 1512 xfer->ux_status = USBD_IOERROR; 1513 usb_transfer_complete(xfer); 1514 } 1515 } 1516 DPRINTFN(10, "--- ITD dump start ---", 0, 0, 0, 0); 1517 #ifdef OHCI_DEBUG 1518 if (ohcidebug >= 10) { 1519 for (sitd = sidone; sitd; sitd = sitd->dnext) 1520 ohci_dump_itd(sc, sitd); 1521 } 1522 #endif 1523 DPRINTFN(10, "--- ITD dump end ---", 0, 0, 0, 0); 1524 1525 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1526 xfer = sitd->xfer; 1527 sitdnext = sitd->dnext; 1528 DPRINTFN(1, "sitd=%p xfer=%p hcpriv=%p", sitd, xfer, 1529 xfer ? xfer->ux_hcpriv : 0, 0); 1530 if (xfer == NULL) 1531 continue; 1532 if (xfer->ux_status == USBD_CANCELLED || 1533 xfer->ux_status == USBD_TIMEOUT) { 1534 DPRINTF("cancel/timeout %p", xfer, 0, 0, 0); 1535 /* Handled by abort routine. */ 1536 continue; 1537 } 1538 KASSERT(!sitd->isdone); 1539 #ifdef DIAGNOSTIC 1540 sitd->isdone = true; 1541 #endif 1542 if (sitd->flags & OHCI_CALL_DONE) { 1543 ohci_soft_itd_t *next; 1544 1545 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1546 opipe->isoc.inuse -= xfer->ux_nframes; 1547 uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc-> 1548 bEndpointAddress); 1549 xfer->ux_status = USBD_NORMAL_COMPLETION; 1550 actlen = 0; 1551 for (i = 0, sitd = xfer->ux_hcpriv;; 1552 sitd = next) { 1553 next = sitd->nextitd; 1554 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1555 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1556 xfer->ux_status = USBD_IOERROR; 1557 /* For input, update frlengths with actual */ 1558 /* XXX anything necessary for output? */ 1559 if (uedir == UE_DIR_IN && 1560 xfer->ux_status == USBD_NORMAL_COMPLETION) { 1561 iframes = OHCI_ITD_GET_FC(O32TOH( 1562 sitd->itd.itd_flags)); 1563 for (j = 0; j < iframes; i++, j++) { 1564 len = O16TOH(sitd-> 1565 itd.itd_offset[j]); 1566 if ((OHCI_ITD_PSW_GET_CC(len) & 1567 OHCI_CC_NOT_ACCESSED_MASK) 1568 == OHCI_CC_NOT_ACCESSED) 1569 len = 0; 1570 else 1571 len = OHCI_ITD_PSW_LENGTH(len); 1572 xfer->ux_frlengths[i] = len; 1573 actlen += len; 1574 } 1575 } 1576 if (sitd->flags & OHCI_CALL_DONE) 1577 break; 1578 ohci_hash_rem_itd(sc, sitd); 1579 1580 } 1581 ohci_hash_rem_itd(sc, sitd); 1582 if (uedir == UE_DIR_IN && 1583 xfer->ux_status == USBD_NORMAL_COMPLETION) 1584 xfer->ux_actlen = actlen; 1585 xfer->ux_hcpriv = NULL; 1586 1587 usb_transfer_complete(xfer); 1588 } 1589 } 1590 1591 if (sc->sc_softwake) { 1592 sc->sc_softwake = 0; 1593 cv_broadcast(&sc->sc_softwake_cv); 1594 } 1595 1596 DPRINTFN(10, "done", 0, 0, 0, 0); 1597 } 1598 1599 void 1600 ohci_device_ctrl_done(struct usbd_xfer *xfer) 1601 { 1602 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1603 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1604 int len = UGETW(xfer->ux_request.wLength); 1605 int isread = (xfer->ux_request.bmRequestType & UT_READ); 1606 1607 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1608 DPRINTFN(10, "xfer=%p", xfer, 0, 0, 0); 1609 1610 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1611 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 1612 1613 if (len) 1614 usb_syncmem(&xfer->ux_dmabuf, 0, len, 1615 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1616 usb_syncmem(&opipe->ctrl.reqdma, 0, 1617 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1618 } 1619 1620 void 1621 ohci_device_intr_done(struct usbd_xfer *xfer) 1622 { 1623 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1624 int isread = 1625 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1626 1627 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1628 DPRINTFN(10, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0); 1629 1630 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1631 1632 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1633 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1634 } 1635 1636 void 1637 ohci_device_bulk_done(struct usbd_xfer *xfer) 1638 { 1639 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1640 1641 int isread = 1642 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1643 1644 KASSERT(mutex_owned(&sc->sc_lock)); 1645 1646 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1647 DPRINTFN(10, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0); 1648 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1649 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1650 } 1651 1652 Static void 1653 ohci_rhsc_softint(void *arg) 1654 { 1655 ohci_softc_t *sc = arg; 1656 1657 mutex_enter(&sc->sc_lock); 1658 1659 ohci_rhsc(sc, sc->sc_intrxfer); 1660 1661 /* Do not allow RHSC interrupts > 1 per second */ 1662 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1663 1664 mutex_exit(&sc->sc_lock); 1665 } 1666 1667 void 1668 ohci_rhsc(ohci_softc_t *sc, struct usbd_xfer *xfer) 1669 { 1670 u_char *p; 1671 int i, m; 1672 int hstatus __unused; 1673 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1674 1675 KASSERT(mutex_owned(&sc->sc_lock)); 1676 1677 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1678 DPRINTF("sc=%p xfer=%p hstatus=0x%08x", sc, xfer, hstatus, 0); 1679 1680 if (xfer == NULL) { 1681 /* Just ignore the change. */ 1682 return; 1683 } 1684 1685 p = xfer->ux_buf; 1686 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 1687 memset(p, 0, xfer->ux_length); 1688 for (i = 1; i <= m; i++) { 1689 /* Pick out CHANGE bits from the status reg. */ 1690 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1691 p[i/8] |= 1 << (i%8); 1692 } 1693 DPRINTF("change=0x%02x", *p, 0, 0, 0); 1694 xfer->ux_actlen = xfer->ux_length; 1695 xfer->ux_status = USBD_NORMAL_COMPLETION; 1696 1697 usb_transfer_complete(xfer); 1698 } 1699 1700 void 1701 ohci_root_intr_done(struct usbd_xfer *xfer) 1702 { 1703 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1704 1705 KASSERT(mutex_owned(&sc->sc_lock)); 1706 1707 KASSERT(sc->sc_intrxfer == xfer); 1708 sc->sc_intrxfer = NULL; 1709 } 1710 1711 void 1712 ohci_poll(struct usbd_bus *bus) 1713 { 1714 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1715 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1716 1717 #ifdef OHCI_DEBUG 1718 static int last; 1719 int new; 1720 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1721 if (new != last) { 1722 DPRINTFN(10, "intrs=0x%04x", new, 0, 0, 0); 1723 last = new; 1724 } 1725 #endif 1726 sc->sc_eintrs |= OHCI_WDH; 1727 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1728 mutex_spin_enter(&sc->sc_intr_lock); 1729 ohci_intr1(sc); 1730 mutex_spin_exit(&sc->sc_intr_lock); 1731 } 1732 } 1733 1734 /* 1735 * Add an ED to the schedule. Called with USB lock held. 1736 */ 1737 Static void 1738 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1739 { 1740 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1741 DPRINTFN(8, "sed=%p head=%p", sed, head, 0, 0); 1742 1743 KASSERT(mutex_owned(&sc->sc_lock)); 1744 1745 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1746 sizeof(head->ed.ed_nexted), 1747 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1748 sed->next = head->next; 1749 sed->ed.ed_nexted = head->ed.ed_nexted; 1750 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1751 sizeof(sed->ed.ed_nexted), 1752 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1753 head->next = sed; 1754 head->ed.ed_nexted = HTOO32(sed->physaddr); 1755 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1756 sizeof(head->ed.ed_nexted), 1757 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1758 } 1759 1760 /* 1761 * Remove an ED from the schedule. Called with USB lock held. 1762 */ 1763 Static void 1764 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1765 { 1766 ohci_soft_ed_t *p; 1767 1768 KASSERT(mutex_owned(&sc->sc_lock)); 1769 1770 /* XXX */ 1771 for (p = head; p != NULL && p->next != sed; p = p->next) 1772 ; 1773 KASSERT(p != NULL); 1774 1775 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1776 sizeof(sed->ed.ed_nexted), 1777 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1778 p->next = sed->next; 1779 p->ed.ed_nexted = sed->ed.ed_nexted; 1780 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1781 sizeof(p->ed.ed_nexted), 1782 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1783 } 1784 1785 /* 1786 * When a transfer is completed the TD is added to the done queue by 1787 * the host controller. This queue is the processed by software. 1788 * Unfortunately the queue contains the physical address of the TD 1789 * and we have no simple way to translate this back to a kernel address. 1790 * To make the translation possible (and fast) we use a hash table of 1791 * TDs currently in the schedule. The physical address is used as the 1792 * hash value. 1793 */ 1794 1795 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1796 /* Called with USB lock held. */ 1797 void 1798 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1799 { 1800 int h = HASH(std->physaddr); 1801 1802 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1803 1804 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1805 } 1806 1807 /* Called with USB lock held. */ 1808 void 1809 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1810 { 1811 1812 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1813 1814 LIST_REMOVE(std, hnext); 1815 } 1816 1817 ohci_soft_td_t * 1818 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1819 { 1820 int h = HASH(a); 1821 ohci_soft_td_t *std; 1822 1823 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1824 std != NULL; 1825 std = LIST_NEXT(std, hnext)) 1826 if (std->physaddr == a) 1827 return std; 1828 return NULL; 1829 } 1830 1831 /* Called with USB lock held. */ 1832 void 1833 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1834 { 1835 int h = HASH(sitd->physaddr); 1836 1837 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1838 1839 KASSERT(mutex_owned(&sc->sc_lock)); 1840 1841 DPRINTFN(10, "sitd=%p physaddr=0x%08lx", sitd, (u_long)sitd->physaddr, 1842 0, 0); 1843 1844 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1845 } 1846 1847 /* Called with USB lock held. */ 1848 void 1849 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1850 { 1851 1852 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1853 1854 KASSERT(mutex_owned(&sc->sc_lock)); 1855 1856 DPRINTFN(10, "sitd=%p physaddr=0x%08lx", sitd, (u_long)sitd->physaddr, 1857 0, 0); 1858 1859 LIST_REMOVE(sitd, hnext); 1860 } 1861 1862 ohci_soft_itd_t * 1863 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1864 { 1865 int h = HASH(a); 1866 ohci_soft_itd_t *sitd; 1867 1868 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1869 sitd != NULL; 1870 sitd = LIST_NEXT(sitd, hnext)) 1871 if (sitd->physaddr == a) 1872 return sitd; 1873 return NULL; 1874 } 1875 1876 void 1877 ohci_timeout(void *addr) 1878 { 1879 struct usbd_xfer *xfer = addr; 1880 struct ohci_xfer *oxfer = OHCI_XFER2OXFER(xfer); 1881 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1882 1883 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1884 DPRINTF("oxfer=%p", oxfer, 0, 0, 0); 1885 1886 if (sc->sc_dying) { 1887 mutex_enter(&sc->sc_lock); 1888 ohci_abort_xfer(xfer, USBD_TIMEOUT); 1889 mutex_exit(&sc->sc_lock); 1890 return; 1891 } 1892 1893 /* Execute the abort in a process context. */ 1894 usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr, 1895 USB_TASKQ_MPSAFE); 1896 usb_add_task(xfer->ux_pipe->up_dev, &oxfer->abort_task, 1897 USB_TASKQ_HC); 1898 } 1899 1900 void 1901 ohci_timeout_task(void *addr) 1902 { 1903 struct usbd_xfer *xfer = addr; 1904 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1905 1906 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1907 1908 DPRINTF("xfer=%p", xfer, 0, 0, 0); 1909 1910 mutex_enter(&sc->sc_lock); 1911 ohci_abort_xfer(xfer, USBD_TIMEOUT); 1912 mutex_exit(&sc->sc_lock); 1913 } 1914 1915 #ifdef OHCI_DEBUG 1916 void 1917 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 1918 { 1919 for (; std; std = std->nexttd) { 1920 ohci_dump_td(sc, std); 1921 KASSERTMSG(std->nexttd == NULL || std != std->nexttd, 1922 "std %p next %p", std, std->nexttd); 1923 } 1924 } 1925 1926 void 1927 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1928 { 1929 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1930 1931 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1932 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1933 1934 uint32_t flags = O32TOH(std->td.td_flags); 1935 DPRINTF("TD(%p) at 0x%08lx:", std, (u_long)std->physaddr, 0, 0); 1936 DPRINTF(" round=%d DP=%x DI=%x T=%x", 1937 !!(flags & OHCI_TD_R), 1938 __SHIFTOUT(flags, OHCI_TD_DP_MASK), 1939 OHCI_TD_GET_DI(flags), 1940 __SHIFTOUT(flags, OHCI_TD_TOGGLE_MASK)); 1941 DPRINTF(" EC=%d CC=%d", OHCI_TD_GET_EC(flags), OHCI_TD_GET_CC(flags), 1942 0, 0); 1943 DPRINTF(" td_cbp=0x%08lx td_nexttd=0x%08lx td_be=0x%08lx", 1944 (u_long)O32TOH(std->td.td_cbp), 1945 (u_long)O32TOH(std->td.td_nexttd), 1946 (u_long)O32TOH(std->td.td_be), 0); 1947 } 1948 1949 void 1950 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1951 { 1952 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1953 1954 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1955 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1956 1957 uint32_t flags = O32TOH(sitd->itd.itd_flags); 1958 DPRINTF("ITD(%p) at 0x%08lx", sitd, (u_long)sitd->physaddr, 0, 0); 1959 DPRINTF(" sf=%d di=%d fc=%d cc=%d", 1960 OHCI_ITD_GET_SF(flags), OHCI_ITD_GET_DI(flags), 1961 OHCI_ITD_GET_FC(flags), OHCI_ITD_GET_CC(flags)); 1962 DPRINTF(" bp0=0x%08x next=0x%08x be=0x%08x", 1963 O32TOH(sitd->itd.itd_bp0), 1964 O32TOH(sitd->itd.itd_nextitd), 1965 O32TOH(sitd->itd.itd_be), 0); 1966 CTASSERT(OHCI_ITD_NOFFSET == 8); 1967 DPRINTF(" offs[0] = 0x%04x offs[1] = 0x%04x " 1968 "offs[2] = 0x%04x offs[3] = 0x%04x", 1969 O16TOH(sitd->itd.itd_offset[0]), 1970 O16TOH(sitd->itd.itd_offset[1]), 1971 O16TOH(sitd->itd.itd_offset[2]), 1972 O16TOH(sitd->itd.itd_offset[3])); 1973 DPRINTF(" offs[4] = 0x%04x offs[5] = 0x%04x " 1974 "offs[6] = 0x%04x offs[7] = 0x%04x", 1975 O16TOH(sitd->itd.itd_offset[4]), 1976 O16TOH(sitd->itd.itd_offset[5]), 1977 O16TOH(sitd->itd.itd_offset[6]), 1978 O16TOH(sitd->itd.itd_offset[7])); 1979 } 1980 1981 void 1982 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1983 { 1984 for (; sitd; sitd = sitd->nextitd) 1985 ohci_dump_itd(sc, sitd); 1986 } 1987 1988 void 1989 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 1990 { 1991 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1992 1993 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 1994 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1995 1996 uint32_t flags = O32TOH(sed->ed.ed_flags); 1997 DPRINTF("ED(%p) at 0x%08lx:", sed, sed->physaddr, 0, 0); 1998 DPRINTF(" addr=%d endpt=%d maxp=%d", 1999 OHCI_ED_GET_FA(flags), 2000 OHCI_ED_GET_EN(flags), 2001 OHCI_ED_GET_MAXP(flags), 2002 0); 2003 DPRINTF(" dir=%d speed=%d skip=%d iso=%d", 2004 __SHIFTOUT(flags, OHCI_ED_DIR_MASK), 2005 !!(flags & OHCI_ED_SPEED), 2006 !!(flags & OHCI_ED_SKIP), 2007 !!(flags & OHCI_ED_FORMAT_ISO)); 2008 DPRINTF(" tailp=0x%08lx", (u_long)O32TOH(sed->ed.ed_tailp), 2009 0, 0, 0); 2010 DPRINTF(" headp=0x%08lx nexted=0x%08lx halted=%d carry=%d", 2011 O32TOH(sed->ed.ed_headp), O32TOH(sed->ed.ed_nexted), 2012 !!(O32TOH(sed->ed.ed_headp) & OHCI_HALTED), 2013 !!(O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 2014 } 2015 #endif 2016 2017 usbd_status 2018 ohci_open(struct usbd_pipe *pipe) 2019 { 2020 struct usbd_device *dev = pipe->up_dev; 2021 struct usbd_bus *bus = dev->ud_bus; 2022 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2023 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 2024 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2025 uint8_t addr = dev->ud_addr; 2026 uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2027 ohci_soft_ed_t *sed; 2028 ohci_soft_td_t *std; 2029 ohci_soft_itd_t *sitd; 2030 ohci_physaddr_t tdphys; 2031 uint32_t fmt; 2032 usbd_status err = USBD_NOMEM; 2033 int ival; 2034 2035 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2036 DPRINTFN(1, "pipe=%p, addr=%d, endpt=%d (%d)", pipe, addr, 2037 ed->bEndpointAddress, bus->ub_rhaddr); 2038 2039 if (sc->sc_dying) { 2040 return USBD_IOERROR; 2041 } 2042 2043 std = NULL; 2044 sed = NULL; 2045 2046 if (addr == bus->ub_rhaddr) { 2047 switch (ed->bEndpointAddress) { 2048 case USB_CONTROL_ENDPOINT: 2049 pipe->up_methods = &roothub_ctrl_methods; 2050 break; 2051 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 2052 pipe->up_methods = &ohci_root_intr_methods; 2053 break; 2054 default: 2055 err = USBD_INVAL; 2056 goto bad; 2057 } 2058 } else { 2059 sed = ohci_alloc_sed(sc); 2060 if (sed == NULL) 2061 goto bad; 2062 opipe->sed = sed; 2063 if (xfertype == UE_ISOCHRONOUS) { 2064 sitd = ohci_alloc_sitd(sc); 2065 if (sitd == NULL) 2066 goto bad; 2067 2068 opipe->tail.itd = sitd; 2069 tdphys = sitd->physaddr; 2070 fmt = OHCI_ED_FORMAT_ISO; 2071 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2072 fmt |= OHCI_ED_DIR_IN; 2073 else 2074 fmt |= OHCI_ED_DIR_OUT; 2075 } else { 2076 std = ohci_alloc_std(sc); 2077 if (std == NULL) 2078 goto bad; 2079 2080 opipe->tail.td = std; 2081 tdphys = std->physaddr; 2082 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2083 } 2084 sed->ed.ed_flags = HTOO32( 2085 OHCI_ED_SET_FA(addr) | 2086 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2087 (dev->ud_speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2088 fmt | 2089 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2090 sed->ed.ed_headp = HTOO32(tdphys | 2091 (pipe->up_endpoint->ue_toggle ? OHCI_TOGGLECARRY : 0)); 2092 sed->ed.ed_tailp = HTOO32(tdphys); 2093 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2094 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2095 2096 switch (xfertype) { 2097 case UE_CONTROL: 2098 pipe->up_methods = &ohci_device_ctrl_methods; 2099 err = usb_allocmem(&sc->sc_bus, 2100 sizeof(usb_device_request_t), 2101 0, &opipe->ctrl.reqdma); 2102 if (err) 2103 goto bad; 2104 mutex_enter(&sc->sc_lock); 2105 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2106 mutex_exit(&sc->sc_lock); 2107 break; 2108 case UE_INTERRUPT: 2109 pipe->up_methods = &ohci_device_intr_methods; 2110 ival = pipe->up_interval; 2111 if (ival == USBD_DEFAULT_INTERVAL) 2112 ival = ed->bInterval; 2113 err = ohci_device_setintr(sc, opipe, ival); 2114 if (err) 2115 goto bad; 2116 break; 2117 case UE_ISOCHRONOUS: 2118 pipe->up_serialise = false; 2119 pipe->up_methods = &ohci_device_isoc_methods; 2120 return ohci_setup_isoc(pipe); 2121 case UE_BULK: 2122 pipe->up_methods = &ohci_device_bulk_methods; 2123 mutex_enter(&sc->sc_lock); 2124 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2125 mutex_exit(&sc->sc_lock); 2126 break; 2127 } 2128 } 2129 2130 return USBD_NORMAL_COMPLETION; 2131 2132 bad: 2133 if (std != NULL) { 2134 ohci_free_std(sc, std); 2135 } 2136 if (sed != NULL) 2137 ohci_free_sed(sc, sed); 2138 return err; 2139 2140 } 2141 2142 /* 2143 * Close a reqular pipe. 2144 * Assumes that there are no pending transactions. 2145 */ 2146 void 2147 ohci_close_pipe(struct usbd_pipe *pipe, ohci_soft_ed_t *head) 2148 { 2149 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2150 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2151 ohci_soft_ed_t *sed = opipe->sed; 2152 2153 KASSERT(mutex_owned(&sc->sc_lock)); 2154 2155 #ifdef DIAGNOSTIC 2156 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2157 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2158 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2159 ohci_soft_td_t *std; 2160 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2161 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2162 "tl=0x%x pipe=%p, std=%p\n", sed, 2163 (int)O32TOH(sed->ed.ed_headp), 2164 (int)O32TOH(sed->ed.ed_tailp), 2165 pipe, std); 2166 #ifdef OHCI_DEBUG 2167 usbd_dump_pipe(&opipe->pipe); 2168 ohci_dump_ed(sc, sed); 2169 if (std) 2170 ohci_dump_td(sc, std); 2171 #endif 2172 usb_delay_ms(&sc->sc_bus, 2); 2173 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2174 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2175 printf("ohci_close_pipe: pipe still not empty\n"); 2176 } 2177 #endif 2178 ohci_rem_ed(sc, sed, head); 2179 /* Make sure the host controller is not touching this ED */ 2180 usb_delay_ms(&sc->sc_bus, 1); 2181 pipe->up_endpoint->ue_toggle = 2182 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2183 ohci_free_sed_locked(sc, opipe->sed); 2184 } 2185 2186 /* 2187 * Abort a device request. 2188 * If this routine is called at splusb() it guarantees that the request 2189 * will be removed from the hardware scheduling and that the callback 2190 * for it will be called with USBD_CANCELLED status. 2191 * It's impossible to guarantee that the requested transfer will not 2192 * have happened since the hardware runs concurrently. 2193 * If the transaction has already happened we rely on the ordinary 2194 * interrupt processing to process it. 2195 * XXX This is most probably wrong. 2196 * XXXMRG this doesn't make sense anymore. 2197 */ 2198 void 2199 ohci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2200 { 2201 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2202 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2203 ohci_soft_ed_t *sed = opipe->sed; 2204 ohci_soft_td_t *p, *n; 2205 ohci_physaddr_t headp; 2206 int hit; 2207 int wake; 2208 2209 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2210 DPRINTF("xfer=%p pipe=%p sed=%p", xfer, opipe,sed, 0); 2211 2212 KASSERT(mutex_owned(&sc->sc_lock)); 2213 ASSERT_SLEEPABLE(); 2214 2215 if (sc->sc_dying) { 2216 /* If we're dying, just do the software part. */ 2217 xfer->ux_status = status; /* make software ignore it */ 2218 callout_halt(&xfer->ux_callout, &sc->sc_lock); 2219 usb_transfer_complete(xfer); 2220 return; 2221 } 2222 2223 /* 2224 * If an abort is already in progress then just wait for it to 2225 * complete and return. 2226 */ 2227 if (xfer->ux_hcflags & UXFER_ABORTING) { 2228 DPRINTFN(2, "already aborting", 0, 0, 0, 0); 2229 #ifdef DIAGNOSTIC 2230 if (status == USBD_TIMEOUT) 2231 printf("%s: TIMEOUT while aborting\n", __func__); 2232 #endif 2233 /* Override the status which might be USBD_TIMEOUT. */ 2234 xfer->ux_status = status; 2235 DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0); 2236 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2237 while (xfer->ux_hcflags & UXFER_ABORTING) 2238 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2239 goto done; 2240 } 2241 xfer->ux_hcflags |= UXFER_ABORTING; 2242 2243 /* 2244 * Step 1: Make interrupt routine and hardware ignore xfer. 2245 */ 2246 xfer->ux_status = status; /* make software ignore it */ 2247 callout_stop(&xfer->ux_callout); 2248 DPRINTFN(1, "stop ed=%p", sed, 0, 0, 0); 2249 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2250 sizeof(sed->ed.ed_flags), 2251 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2252 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2253 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2254 sizeof(sed->ed.ed_flags), 2255 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2256 2257 /* 2258 * Step 2: Wait until we know hardware has finished any possible 2259 * use of the xfer. Also make sure the soft interrupt routine 2260 * has run. 2261 */ 2262 /* Hardware finishes in 1ms */ 2263 usb_delay_ms_locked(opipe->pipe.up_dev->ud_bus, 20, &sc->sc_lock); 2264 sc->sc_softwake = 1; 2265 usb_schedsoftintr(&sc->sc_bus); 2266 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2267 2268 /* 2269 * Step 3: Remove any vestiges of the xfer from the hardware. 2270 * The complication here is that the hardware may have executed 2271 * beyond the xfer we're trying to abort. So as we're scanning 2272 * the TDs of this xfer we check if the hardware points to 2273 * any of them. 2274 */ 2275 p = xfer->ux_hcpriv; 2276 KASSERT(p); 2277 2278 #ifdef OHCI_DEBUG 2279 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2280 2281 if (ohcidebug >= 2) { 2282 DPRINTF("sed:", 0, 0, 0, 0); 2283 ohci_dump_ed(sc, sed); 2284 ohci_dump_tds(sc, p); 2285 } 2286 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2287 #endif 2288 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2289 hit = 0; 2290 for (; p->xfer == xfer; p = n) { 2291 hit |= headp == p->physaddr; 2292 n = p->nexttd; 2293 ohci_hash_rem_td(sc, p); 2294 } 2295 /* Zap headp register if hardware pointed inside the xfer. */ 2296 if (hit) { 2297 DPRINTFN(1, "set hd=0x%08x, tl=0x%08x", (int)p->physaddr, 2298 (int)O32TOH(sed->ed.ed_tailp), 0, 0); 2299 sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */ 2300 usb_syncmem(&sed->dma, 2301 sed->offs + offsetof(ohci_ed_t, ed_headp), 2302 sizeof(sed->ed.ed_headp), 2303 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2304 } else { 2305 DPRINTFN(1, "no hit", 0, 0, 0, 0); 2306 } 2307 2308 /* 2309 * Step 4: Turn on hardware again. 2310 */ 2311 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2312 sizeof(sed->ed.ed_flags), 2313 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2314 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2315 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2316 sizeof(sed->ed.ed_flags), 2317 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2318 2319 /* 2320 * Step 5: Execute callback. 2321 */ 2322 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2323 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2324 usb_transfer_complete(xfer); 2325 if (wake) 2326 cv_broadcast(&xfer->ux_hccv); 2327 2328 done: 2329 KASSERT(mutex_owned(&sc->sc_lock)); 2330 } 2331 2332 /* 2333 * Data structures and routines to emulate the root hub. 2334 */ 2335 Static int 2336 ohci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2337 void *buf, int buflen) 2338 { 2339 ohci_softc_t *sc = OHCI_BUS2SC(bus); 2340 usb_port_status_t ps; 2341 uint16_t len, value, index; 2342 int l, totlen = 0; 2343 int port, i; 2344 uint32_t v; 2345 2346 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2347 2348 if (sc->sc_dying) 2349 return -1; 2350 2351 DPRINTFN(4, "type=0x%02x request=%02x", req->bmRequestType, 2352 req->bRequest, 0, 0); 2353 2354 len = UGETW(req->wLength); 2355 value = UGETW(req->wValue); 2356 index = UGETW(req->wIndex); 2357 2358 #define C(x,y) ((x) | ((y) << 8)) 2359 switch (C(req->bRequest, req->bmRequestType)) { 2360 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2361 DPRINTFN(8, "wValue=0x%04x", value, 0, 0, 0); 2362 if (len == 0) 2363 break; 2364 switch (value) { 2365 case C(0, UDESC_DEVICE): { 2366 usb_device_descriptor_t devd; 2367 2368 totlen = min(buflen, sizeof(devd)); 2369 memcpy(&devd, buf, totlen); 2370 USETW(devd.idVendor, sc->sc_id_vendor); 2371 memcpy(buf, &devd, totlen); 2372 break; 2373 } 2374 case C(1, UDESC_STRING): 2375 #define sd ((usb_string_descriptor_t *)buf) 2376 /* Vendor */ 2377 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2378 break; 2379 case C(2, UDESC_STRING): 2380 /* Product */ 2381 totlen = usb_makestrdesc(sd, len, "OHCI root hub"); 2382 break; 2383 #undef sd 2384 default: 2385 /* default from usbroothub */ 2386 return buflen; 2387 } 2388 break; 2389 2390 /* Hub requests */ 2391 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2392 break; 2393 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2394 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 2395 index, value, 0, 0); 2396 if (index < 1 || index > sc->sc_noport) { 2397 return -1; 2398 } 2399 port = OHCI_RH_PORT_STATUS(index); 2400 switch(value) { 2401 case UHF_PORT_ENABLE: 2402 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2403 break; 2404 case UHF_PORT_SUSPEND: 2405 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2406 break; 2407 case UHF_PORT_POWER: 2408 /* Yes, writing to the LOW_SPEED bit clears power. */ 2409 OWRITE4(sc, port, UPS_LOW_SPEED); 2410 break; 2411 case UHF_C_PORT_CONNECTION: 2412 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2413 break; 2414 case UHF_C_PORT_ENABLE: 2415 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2416 break; 2417 case UHF_C_PORT_SUSPEND: 2418 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2419 break; 2420 case UHF_C_PORT_OVER_CURRENT: 2421 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2422 break; 2423 case UHF_C_PORT_RESET: 2424 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2425 break; 2426 default: 2427 return -1; 2428 } 2429 switch(value) { 2430 case UHF_C_PORT_CONNECTION: 2431 case UHF_C_PORT_ENABLE: 2432 case UHF_C_PORT_SUSPEND: 2433 case UHF_C_PORT_OVER_CURRENT: 2434 case UHF_C_PORT_RESET: 2435 /* Enable RHSC interrupt if condition is cleared. */ 2436 if ((OREAD4(sc, port) >> 16) == 0) 2437 ohci_rhsc_enable(sc); 2438 break; 2439 default: 2440 break; 2441 } 2442 break; 2443 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2444 if (len == 0) 2445 break; 2446 if ((value & 0xff) != 0) { 2447 return -1; 2448 } 2449 usb_hub_descriptor_t hubd; 2450 2451 totlen = min(buflen, sizeof(hubd)); 2452 memcpy(&hubd, buf, totlen); 2453 2454 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2455 hubd.bNbrPorts = sc->sc_noport; 2456 USETW(hubd.wHubCharacteristics, 2457 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2458 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2459 /* XXX overcurrent */ 2460 ); 2461 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2462 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2463 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2464 hubd.DeviceRemovable[i++] = (uint8_t)v; 2465 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2466 totlen = min(totlen, hubd.bDescLength); 2467 memcpy(buf, &hubd, totlen); 2468 break; 2469 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2470 if (len != 4) { 2471 return -1; 2472 } 2473 memset(buf, 0, len); /* ? XXX */ 2474 totlen = len; 2475 break; 2476 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2477 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 2478 if (index < 1 || index > sc->sc_noport) { 2479 return -1; 2480 } 2481 if (len != 4) { 2482 return -1; 2483 } 2484 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2485 DPRINTFN(8, "port status=0x%04x", v, 0, 0, 0); 2486 USETW(ps.wPortStatus, v); 2487 USETW(ps.wPortChange, v >> 16); 2488 totlen = min(len, sizeof(ps)); 2489 memcpy(buf, &ps, totlen); 2490 break; 2491 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2492 return -1; 2493 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2494 break; 2495 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2496 if (index < 1 || index > sc->sc_noport) { 2497 return -1; 2498 } 2499 port = OHCI_RH_PORT_STATUS(index); 2500 switch(value) { 2501 case UHF_PORT_ENABLE: 2502 OWRITE4(sc, port, UPS_PORT_ENABLED); 2503 break; 2504 case UHF_PORT_SUSPEND: 2505 OWRITE4(sc, port, UPS_SUSPEND); 2506 break; 2507 case UHF_PORT_RESET: 2508 DPRINTFN(5, "reset port %d", index, 0, 0, 0); 2509 OWRITE4(sc, port, UPS_RESET); 2510 for (i = 0; i < 5; i++) { 2511 usb_delay_ms(&sc->sc_bus, 2512 USB_PORT_ROOT_RESET_DELAY); 2513 if (sc->sc_dying) { 2514 return -1; 2515 } 2516 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2517 break; 2518 } 2519 DPRINTFN(8, "port %d reset, status = 0x%04x", index, 2520 OREAD4(sc, port), 0, 0); 2521 break; 2522 case UHF_PORT_POWER: 2523 DPRINTFN(2, "set port power %d", index, 0, 0, 0); 2524 OWRITE4(sc, port, UPS_PORT_POWER); 2525 break; 2526 default: 2527 return -1; 2528 } 2529 break; 2530 default: 2531 /* default from usbroothub */ 2532 return buflen; 2533 } 2534 2535 return totlen; 2536 } 2537 2538 Static usbd_status 2539 ohci_root_intr_transfer(struct usbd_xfer *xfer) 2540 { 2541 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2542 usbd_status err; 2543 2544 /* Insert last in queue. */ 2545 mutex_enter(&sc->sc_lock); 2546 err = usb_insert_transfer(xfer); 2547 mutex_exit(&sc->sc_lock); 2548 if (err) 2549 return err; 2550 2551 /* Pipe isn't running, start first */ 2552 return ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2553 } 2554 2555 Static usbd_status 2556 ohci_root_intr_start(struct usbd_xfer *xfer) 2557 { 2558 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2559 2560 if (sc->sc_dying) 2561 return USBD_IOERROR; 2562 2563 mutex_enter(&sc->sc_lock); 2564 KASSERT(sc->sc_intrxfer == NULL); 2565 sc->sc_intrxfer = xfer; 2566 mutex_exit(&sc->sc_lock); 2567 2568 return USBD_IN_PROGRESS; 2569 } 2570 2571 /* Abort a root interrupt request. */ 2572 Static void 2573 ohci_root_intr_abort(struct usbd_xfer *xfer) 2574 { 2575 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2576 2577 KASSERT(mutex_owned(&sc->sc_lock)); 2578 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2579 2580 sc->sc_intrxfer = NULL; 2581 2582 xfer->ux_status = USBD_CANCELLED; 2583 usb_transfer_complete(xfer); 2584 } 2585 2586 /* Close the root pipe. */ 2587 Static void 2588 ohci_root_intr_close(struct usbd_pipe *pipe) 2589 { 2590 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2591 2592 KASSERT(mutex_owned(&sc->sc_lock)); 2593 2594 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2595 2596 sc->sc_intrxfer = NULL; 2597 } 2598 2599 /************************/ 2600 2601 int 2602 ohci_device_ctrl_init(struct usbd_xfer *xfer) 2603 { 2604 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2605 usb_device_request_t *req = &xfer->ux_request; 2606 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2607 ohci_soft_td_t *stat, *setup; 2608 int isread = req->bmRequestType & UT_READ; 2609 int len = xfer->ux_bufsize; 2610 int err = ENOMEM; 2611 2612 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2613 2614 setup = ohci_alloc_std(sc); 2615 if (setup == NULL) { 2616 goto bad1; 2617 } 2618 stat = ohci_alloc_std(sc); 2619 if (stat == NULL) { 2620 goto bad2; 2621 } 2622 2623 ox->ox_setup = setup; 2624 ox->ox_stat = stat; 2625 ox->ox_nstd = 0; 2626 2627 /* Set up data transaction */ 2628 if (len != 0) { 2629 err = ohci_alloc_std_chain(sc, xfer, len, isread); 2630 if (err) { 2631 goto bad3; 2632 } 2633 } 2634 return 0; 2635 2636 bad3: 2637 ohci_free_std(sc, stat); 2638 bad2: 2639 ohci_free_std(sc, setup); 2640 bad1: 2641 return err; 2642 } 2643 2644 void 2645 ohci_device_ctrl_fini(struct usbd_xfer *xfer) 2646 { 2647 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2648 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2649 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2650 2651 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2652 DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0); 2653 2654 mutex_enter(&sc->sc_lock); 2655 if (ox->ox_setup != opipe->tail.td) { 2656 ohci_free_std_locked(sc, ox->ox_setup); 2657 } 2658 for (size_t i = 0; i < ox->ox_nstd; i++) { 2659 ohci_soft_td_t *std = ox->ox_stds[i]; 2660 if (std == NULL) 2661 break; 2662 ohci_free_std_locked(sc, std); 2663 } 2664 ohci_free_std_locked(sc, ox->ox_stat); 2665 mutex_exit(&sc->sc_lock); 2666 2667 if (ox->ox_nstd) { 2668 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 2669 kmem_free(ox->ox_stds, sz); 2670 } 2671 } 2672 2673 Static usbd_status 2674 ohci_device_ctrl_transfer(struct usbd_xfer *xfer) 2675 { 2676 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2677 usbd_status err; 2678 2679 /* Insert last in queue. */ 2680 mutex_enter(&sc->sc_lock); 2681 err = usb_insert_transfer(xfer); 2682 mutex_exit(&sc->sc_lock); 2683 if (err) 2684 return err; 2685 2686 /* Pipe isn't running, start first */ 2687 return ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2688 } 2689 2690 Static usbd_status 2691 ohci_device_ctrl_start(struct usbd_xfer *xfer) 2692 { 2693 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2694 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2695 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2696 usb_device_request_t *req = &xfer->ux_request; 2697 struct usbd_device *dev __diagused = opipe->pipe.up_dev; 2698 ohci_soft_td_t *setup, *stat, *next, *tail; 2699 ohci_soft_ed_t *sed; 2700 int isread; 2701 int len; 2702 2703 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2704 2705 if (sc->sc_dying) 2706 return USBD_IOERROR; 2707 2708 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2709 2710 isread = req->bmRequestType & UT_READ; 2711 len = UGETW(req->wLength); 2712 2713 DPRINTF("xfer=%p len=%d, addr=%d, endpt=%d", xfer, len, dev->ud_addr, 2714 opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress); 2715 DPRINTF("type=0x%02x, request=0x%02x, wValue=0x%04x, wIndex=0x%04x", 2716 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2717 UGETW(req->wIndex)); 2718 2719 /* Need to take lock here for pipe->tail.td */ 2720 mutex_enter(&sc->sc_lock); 2721 2722 /* 2723 * Use the pipe "tail" TD as our first and loan our first TD to the 2724 * next transfer 2725 */ 2726 setup = opipe->tail.td; 2727 opipe->tail.td = ox->ox_setup; 2728 ox->ox_setup = setup; 2729 2730 stat = ox->ox_stat; 2731 2732 /* point at sentinel */ 2733 tail = opipe->tail.td; 2734 sed = opipe->sed; 2735 2736 KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->ud_addr, 2737 "address ED %d pipe %d\n", 2738 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->ud_addr); 2739 KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) == 2740 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 2741 "MPL ED %d pipe %d\n", 2742 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), 2743 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 2744 2745 /* next will point to data if len != 0 */ 2746 next = stat; 2747 2748 /* Set up data transaction */ 2749 if (len != 0) { 2750 ohci_soft_td_t *std; 2751 ohci_soft_td_t *end; 2752 2753 next = ox->ox_stds[0]; 2754 ohci_reset_std_chain(sc, xfer, len, isread, next, &end); 2755 2756 end->td.td_nexttd = HTOO32(stat->physaddr); 2757 end->nexttd = stat; 2758 2759 usb_syncmem(&end->dma, 2760 end->offs + offsetof(ohci_td_t, td_nexttd), 2761 sizeof(end->td.td_nexttd), 2762 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2763 2764 usb_syncmem(&xfer->ux_dmabuf, 0, len, 2765 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2766 std = ox->ox_stds[0]; 2767 /* Start toggle at 1 and then use the carried toggle. */ 2768 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 2769 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 2770 usb_syncmem(&std->dma, 2771 std->offs + offsetof(ohci_td_t, td_flags), 2772 sizeof(std->td.td_flags), 2773 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2774 } 2775 2776 DPRINTFN(8, "setup %p data %p stat %p tail %p", setup, 2777 (len != 0 ? ox->ox_stds[0] : NULL), stat, tail); 2778 KASSERT(opipe->tail.td == tail); 2779 2780 memcpy(KERNADDR(&opipe->ctrl.reqdma, 0), req, sizeof(*req)); 2781 usb_syncmem(&opipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2782 2783 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 2784 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 2785 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->ctrl.reqdma, 0)); 2786 setup->td.td_nexttd = HTOO32(next->physaddr); 2787 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof(*req) - 1); 2788 setup->nexttd = next; 2789 setup->len = 0; 2790 setup->xfer = xfer; 2791 setup->flags = 0; 2792 ohci_hash_add_td(sc, setup); 2793 2794 xfer->ux_hcpriv = setup; 2795 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2796 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2797 2798 stat->td.td_flags = HTOO32( 2799 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 2800 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 2801 stat->td.td_cbp = 0; 2802 stat->td.td_nexttd = HTOO32(tail->physaddr); 2803 stat->td.td_be = 0; 2804 stat->nexttd = tail; 2805 stat->flags = OHCI_CALL_DONE; 2806 stat->len = 0; 2807 stat->xfer = xfer; 2808 ohci_hash_add_td(sc, stat); 2809 2810 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2811 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2812 2813 memset(&tail->td, 0, sizeof(tail->td)); 2814 tail->nexttd = NULL; 2815 tail->xfer = NULL; 2816 2817 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 2818 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2819 2820 #ifdef OHCI_DEBUG 2821 USBHIST_LOGN(ohcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2822 if (ohcidebug >= 5) { 2823 ohci_dump_ed(sc, sed); 2824 ohci_dump_tds(sc, setup); 2825 } 2826 USBHIST_LOGN(ohcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2827 #endif 2828 2829 /* Insert ED in schedule */ 2830 sed->ed.ed_tailp = HTOO32(tail->physaddr); 2831 usb_syncmem(&sed->dma, 2832 sed->offs + offsetof(ohci_ed_t, ed_tailp), 2833 sizeof(sed->ed.ed_tailp), 2834 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2835 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2836 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2837 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2838 ohci_timeout, xfer); 2839 } 2840 2841 DPRINTF("done", 0, 0, 0, 0); 2842 2843 mutex_exit(&sc->sc_lock); 2844 2845 return USBD_IN_PROGRESS; 2846 } 2847 2848 /* Abort a device control request. */ 2849 Static void 2850 ohci_device_ctrl_abort(struct usbd_xfer *xfer) 2851 { 2852 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 2853 2854 KASSERT(mutex_owned(&sc->sc_lock)); 2855 2856 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2857 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2858 ohci_abort_xfer(xfer, USBD_CANCELLED); 2859 } 2860 2861 /* Close a device control pipe. */ 2862 Static void 2863 ohci_device_ctrl_close(struct usbd_pipe *pipe) 2864 { 2865 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2866 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2867 2868 KASSERT(mutex_owned(&sc->sc_lock)); 2869 2870 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2871 DPRINTF("pipe=%p", pipe, 0, 0, 0); 2872 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2873 ohci_free_std_locked(sc, opipe->tail.td); 2874 } 2875 2876 /************************/ 2877 2878 Static void 2879 ohci_device_clear_toggle(struct usbd_pipe *pipe) 2880 { 2881 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2882 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2883 2884 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2885 } 2886 2887 Static void 2888 ohci_noop(struct usbd_pipe *pipe) 2889 { 2890 } 2891 2892 Static int 2893 ohci_device_bulk_init(struct usbd_xfer *xfer) 2894 { 2895 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2896 int len = xfer->ux_bufsize; 2897 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;; 2898 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2899 int err; 2900 2901 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2902 2903 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2904 2905 DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread, 2906 xfer->ux_flags); 2907 DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0); 2908 2909 /* Allocate a chain of new TDs (including a new tail). */ 2910 err = ohci_alloc_std_chain(sc, xfer, len, isread); 2911 if (err) 2912 return err; 2913 2914 return 0; 2915 } 2916 2917 Static void 2918 ohci_device_bulk_fini(struct usbd_xfer *xfer) 2919 { 2920 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2921 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2922 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2923 2924 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2925 DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0); 2926 2927 mutex_enter(&sc->sc_lock); 2928 for (size_t i = 0; i < ox->ox_nstd; i++) { 2929 ohci_soft_td_t *std = ox->ox_stds[i]; 2930 if (std == NULL) 2931 break; 2932 if (std != opipe->tail.td) 2933 ohci_free_std_locked(sc, std); 2934 } 2935 mutex_exit(&sc->sc_lock); 2936 2937 if (ox->ox_nstd) { 2938 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 2939 kmem_free(ox->ox_stds, sz); 2940 } 2941 } 2942 2943 Static usbd_status 2944 ohci_device_bulk_transfer(struct usbd_xfer *xfer) 2945 { 2946 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2947 usbd_status err; 2948 2949 /* Insert last in queue. */ 2950 mutex_enter(&sc->sc_lock); 2951 err = usb_insert_transfer(xfer); 2952 mutex_exit(&sc->sc_lock); 2953 if (err) 2954 return err; 2955 2956 /* Pipe isn't running, start first */ 2957 return ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2958 } 2959 2960 Static usbd_status 2961 ohci_device_bulk_start(struct usbd_xfer *xfer) 2962 { 2963 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2964 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2965 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2966 ohci_soft_td_t *last; 2967 ohci_soft_td_t *data, *tail, *tdp; 2968 ohci_soft_ed_t *sed; 2969 int len, isread, endpt; 2970 2971 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2972 2973 if (sc->sc_dying) 2974 return USBD_IOERROR; 2975 2976 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2977 2978 len = xfer->ux_length; 2979 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2980 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2981 sed = opipe->sed; 2982 2983 DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread, 2984 xfer->ux_flags); 2985 DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0); 2986 2987 mutex_enter(&sc->sc_lock); 2988 2989 /* 2990 * Use the pipe "tail" TD as our first and loan our first TD to the 2991 * next transfer 2992 */ 2993 data = opipe->tail.td; 2994 opipe->tail.td = ox->ox_stds[0]; 2995 ox->ox_stds[0] = data; 2996 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 2997 2998 /* point at sentinel */ 2999 tail = opipe->tail.td; 3000 memset(&tail->td, 0, sizeof(tail->td)); 3001 tail->nexttd = NULL; 3002 tail->xfer = NULL; 3003 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3004 BUS_DMASYNC_PREWRITE); 3005 xfer->ux_hcpriv = data; 3006 3007 DPRINTFN(8, "xfer %p data %p tail %p", xfer, ox->ox_stds[0], tail, 0); 3008 KASSERT(opipe->tail.td == tail); 3009 3010 /* We want interrupt at the end of the transfer. */ 3011 last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3012 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3013 last->td.td_nexttd = HTOO32(tail->physaddr); 3014 last->nexttd = tail; 3015 last->flags |= OHCI_CALL_DONE; 3016 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3017 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3018 3019 DPRINTFN(4, "ed_flags=0x%08x td_flags=0x%08x " 3020 "td_cbp=0x%08x td_be=0x%08x", 3021 (int)O32TOH(sed->ed.ed_flags), 3022 (int)O32TOH(data->td.td_flags), 3023 (int)O32TOH(data->td.td_cbp), 3024 (int)O32TOH(data->td.td_be)); 3025 3026 #ifdef OHCI_DEBUG 3027 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3028 if (ohcidebug >= 5) { 3029 ohci_dump_ed(sc, sed); 3030 ohci_dump_tds(sc, data); 3031 } 3032 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3033 #endif 3034 3035 /* Insert ED in schedule */ 3036 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3037 KASSERT(tdp->xfer == xfer); 3038 } 3039 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3040 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3041 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3042 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3043 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3044 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3045 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3046 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3047 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3048 ohci_timeout, xfer); 3049 } 3050 mutex_exit(&sc->sc_lock); 3051 3052 return USBD_IN_PROGRESS; 3053 } 3054 3055 Static void 3056 ohci_device_bulk_abort(struct usbd_xfer *xfer) 3057 { 3058 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3059 3060 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3061 3062 KASSERT(mutex_owned(&sc->sc_lock)); 3063 3064 DPRINTF("xfer=%p", xfer, 0, 0, 0); 3065 ohci_abort_xfer(xfer, USBD_CANCELLED); 3066 } 3067 3068 /* 3069 * Close a device bulk pipe. 3070 */ 3071 Static void 3072 ohci_device_bulk_close(struct usbd_pipe *pipe) 3073 { 3074 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3075 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3076 3077 KASSERT(mutex_owned(&sc->sc_lock)); 3078 3079 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3080 3081 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3082 ohci_close_pipe(pipe, sc->sc_bulk_head); 3083 ohci_free_std_locked(sc, opipe->tail.td); 3084 } 3085 3086 /************************/ 3087 3088 Static int 3089 ohci_device_intr_init(struct usbd_xfer *xfer) 3090 { 3091 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3092 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3093 int len = xfer->ux_bufsize; 3094 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;; 3095 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3096 int err; 3097 3098 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3099 3100 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3101 KASSERT(len != 0); 3102 3103 DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread, 3104 xfer->ux_flags); 3105 DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0); 3106 3107 ox->ox_nstd = 0; 3108 3109 err = ohci_alloc_std_chain(sc, xfer, len, isread); 3110 if (err) { 3111 return err; 3112 } 3113 3114 return 0; 3115 } 3116 3117 Static void 3118 ohci_device_intr_fini(struct usbd_xfer *xfer) 3119 { 3120 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3121 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3122 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3123 3124 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3125 DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0); 3126 3127 mutex_enter(&sc->sc_lock); 3128 for (size_t i = 0; i < ox->ox_nstd; i++) { 3129 ohci_soft_td_t *std = ox->ox_stds[i]; 3130 if (std != NULL) 3131 break; 3132 if (std != opipe->tail.td) 3133 ohci_free_std_locked(sc, std); 3134 } 3135 mutex_exit(&sc->sc_lock); 3136 3137 if (ox->ox_nstd) { 3138 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 3139 kmem_free(ox->ox_stds, sz); 3140 } 3141 } 3142 3143 Static usbd_status 3144 ohci_device_intr_transfer(struct usbd_xfer *xfer) 3145 { 3146 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3147 usbd_status err; 3148 3149 /* Insert last in queue. */ 3150 mutex_enter(&sc->sc_lock); 3151 err = usb_insert_transfer(xfer); 3152 mutex_exit(&sc->sc_lock); 3153 if (err) 3154 return err; 3155 3156 /* Pipe isn't running, start first */ 3157 return ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3158 } 3159 3160 Static usbd_status 3161 ohci_device_intr_start(struct usbd_xfer *xfer) 3162 { 3163 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3164 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3165 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3166 ohci_soft_ed_t *sed = opipe->sed; 3167 ohci_soft_td_t *data, *last, *tail; 3168 int len, isread, endpt; 3169 3170 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3171 3172 if (sc->sc_dying) 3173 return USBD_IOERROR; 3174 3175 DPRINTFN(3, "xfer=%p len=%d flags=%d priv=%p", xfer, xfer->ux_length, 3176 xfer->ux_flags, xfer->ux_priv); 3177 3178 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3179 3180 len = xfer->ux_length; 3181 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3182 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3183 3184 mutex_enter(&sc->sc_lock); 3185 3186 /* 3187 * Use the pipe "tail" TD as our first and loan our first TD to the 3188 * next transfer. 3189 */ 3190 data = opipe->tail.td; 3191 opipe->tail.td = ox->ox_stds[0]; 3192 ox->ox_stds[0] = data; 3193 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3194 3195 /* point at sentinel */ 3196 tail = opipe->tail.td; 3197 memset(&tail->td, 0, sizeof(tail->td)); 3198 tail->nexttd = NULL; 3199 tail->xfer = NULL; 3200 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3201 BUS_DMASYNC_PREWRITE); 3202 xfer->ux_hcpriv = data; 3203 3204 DPRINTFN(8, "data %p tail %p", ox->ox_stds[0], tail, 0, 0); 3205 KASSERT(opipe->tail.td == tail); 3206 3207 /* We want interrupt at the end of the transfer. */ 3208 last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3209 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3210 3211 last->td.td_nexttd = HTOO32(tail->physaddr); 3212 last->nexttd = tail; 3213 last->flags |= OHCI_CALL_DONE; 3214 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3215 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3216 3217 #ifdef OHCI_DEBUG 3218 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3219 if (ohcidebug >= 5) { 3220 ohci_dump_ed(sc, sed); 3221 ohci_dump_tds(sc, data); 3222 } 3223 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3224 #endif 3225 3226 /* Insert ED in schedule */ 3227 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3228 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3229 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3230 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3231 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3232 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3233 3234 mutex_exit(&sc->sc_lock); 3235 3236 return USBD_IN_PROGRESS; 3237 } 3238 3239 /* Abort a device interrupt request. */ 3240 Static void 3241 ohci_device_intr_abort(struct usbd_xfer *xfer) 3242 { 3243 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3244 3245 KASSERT(mutex_owned(&sc->sc_lock)); 3246 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3247 3248 ohci_abort_xfer(xfer, USBD_CANCELLED); 3249 } 3250 3251 /* Close a device interrupt pipe. */ 3252 Static void 3253 ohci_device_intr_close(struct usbd_pipe *pipe) 3254 { 3255 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3256 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3257 int nslots = opipe->intr.nslots; 3258 int pos = opipe->intr.pos; 3259 int j; 3260 ohci_soft_ed_t *p, *sed = opipe->sed; 3261 3262 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3263 3264 KASSERT(mutex_owned(&sc->sc_lock)); 3265 3266 DPRINTFN(1, "pipe=%p nslots=%d pos=%d", pipe, nslots, pos, 0); 3267 usb_syncmem(&sed->dma, sed->offs, 3268 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3269 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3270 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3271 sizeof(sed->ed.ed_flags), 3272 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3273 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3274 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3275 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3276 3277 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3278 continue; 3279 KASSERT(p); 3280 p->next = sed->next; 3281 p->ed.ed_nexted = sed->ed.ed_nexted; 3282 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3283 sizeof(p->ed.ed_nexted), 3284 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3285 3286 for (j = 0; j < nslots; j++) 3287 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3288 3289 ohci_free_std_locked(sc, opipe->tail.td); 3290 ohci_free_sed_locked(sc, opipe->sed); 3291 } 3292 3293 Static usbd_status 3294 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3295 { 3296 int i, j, best; 3297 u_int npoll, slow, shigh, nslots; 3298 u_int bestbw, bw; 3299 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3300 3301 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3302 3303 DPRINTFN(2, "pipe=%p", opipe, 0, 0, 0); 3304 if (ival == 0) { 3305 printf("ohci_setintr: 0 interval\n"); 3306 return USBD_INVAL; 3307 } 3308 3309 npoll = OHCI_NO_INTRS; 3310 while (npoll > ival) 3311 npoll /= 2; 3312 DPRINTFN(2, "ival=%d npoll=%d", ival, npoll, 0, 0); 3313 3314 /* 3315 * We now know which level in the tree the ED must go into. 3316 * Figure out which slot has most bandwidth left over. 3317 * Slots to examine: 3318 * npoll 3319 * 1 0 3320 * 2 1 2 3321 * 4 3 4 5 6 3322 * 8 7 8 9 10 11 12 13 14 3323 * N (N-1) .. (N-1+N-1) 3324 */ 3325 slow = npoll-1; 3326 shigh = slow + npoll; 3327 nslots = OHCI_NO_INTRS / npoll; 3328 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3329 bw = 0; 3330 for (j = 0; j < nslots; j++) 3331 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3332 if (bw < bestbw) { 3333 best = i; 3334 bestbw = bw; 3335 } 3336 } 3337 DPRINTFN(2, "best=%d(%d..%d) bestbw=%d", best, slow, shigh, bestbw); 3338 3339 mutex_enter(&sc->sc_lock); 3340 hsed = sc->sc_eds[best]; 3341 sed->next = hsed->next; 3342 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3343 sizeof(hsed->ed.ed_flags), 3344 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3345 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3346 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3347 sizeof(sed->ed.ed_flags), 3348 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3349 hsed->next = sed; 3350 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3351 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3352 sizeof(hsed->ed.ed_flags), 3353 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3354 mutex_exit(&sc->sc_lock); 3355 3356 for (j = 0; j < nslots; j++) 3357 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3358 opipe->intr.nslots = nslots; 3359 opipe->intr.pos = best; 3360 3361 DPRINTFN(5, "returns %p", opipe, 0, 0, 0); 3362 return USBD_NORMAL_COMPLETION; 3363 } 3364 3365 /***********************/ 3366 3367 Static int 3368 ohci_device_isoc_init(struct usbd_xfer *xfer) 3369 { 3370 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3371 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3372 ohci_soft_itd_t *sitd; 3373 size_t i; 3374 int err; 3375 3376 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3377 3378 DPRINTFN(1, "xfer %p len %d flags %d", xfer, xfer->ux_length, 3379 xfer->ux_flags, 0); 3380 3381 const size_t nfsitd = 3382 (xfer->ux_nframes + OHCI_ITD_NOFFSET - 1) / OHCI_ITD_NOFFSET; 3383 const size_t nbsitd = xfer->ux_bufsize / OHCI_PAGE_SIZE; 3384 const size_t nsitd = MAX(nfsitd, nbsitd) + 1; 3385 3386 ox->ox_sitds = kmem_zalloc(sizeof(ohci_soft_itd_t *) * nsitd, 3387 KM_SLEEP); 3388 ox->ox_nsitd = nsitd; 3389 3390 for (i = 0; i < nsitd; i++) { 3391 /* Allocate next ITD */ 3392 sitd = ohci_alloc_sitd(sc); 3393 if (sitd == NULL) { 3394 err = ENOMEM; 3395 goto fail; 3396 } 3397 ox->ox_sitds[i] = sitd; 3398 sitd->xfer = xfer; 3399 sitd->flags = 0; 3400 } 3401 3402 return 0; 3403 fail: 3404 for (; i > 0;) { 3405 ohci_free_sitd(sc, ox->ox_sitds[--i]); 3406 } 3407 return err; 3408 } 3409 3410 Static void 3411 ohci_device_isoc_fini(struct usbd_xfer *xfer) 3412 { 3413 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3414 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3415 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3416 3417 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3418 3419 mutex_enter(&sc->sc_lock); 3420 for (size_t i = 0; i < ox->ox_nsitd; i++) { 3421 if (ox->ox_sitds[i] != opipe->tail.itd) { 3422 ohci_free_sitd_locked(sc, ox->ox_sitds[i]); 3423 } 3424 } 3425 mutex_exit(&sc->sc_lock); 3426 3427 if (ox->ox_nsitd) { 3428 const size_t sz = sizeof(ohci_soft_itd_t *) * ox->ox_nsitd; 3429 kmem_free(ox->ox_sitds, sz); 3430 } 3431 } 3432 3433 3434 usbd_status 3435 ohci_device_isoc_transfer(struct usbd_xfer *xfer) 3436 { 3437 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3438 usbd_status __diagused err; 3439 3440 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3441 3442 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 3443 3444 /* Put it on our queue, */ 3445 mutex_enter(&sc->sc_lock); 3446 err = usb_insert_transfer(xfer); 3447 mutex_exit(&sc->sc_lock); 3448 3449 KASSERT(err == USBD_NORMAL_COMPLETION); 3450 3451 /* insert into schedule, */ 3452 ohci_device_isoc_enter(xfer); 3453 3454 /* and start if the pipe wasn't running */ 3455 return USBD_IN_PROGRESS; 3456 } 3457 3458 void 3459 ohci_device_isoc_enter(struct usbd_xfer *xfer) 3460 { 3461 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3462 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3463 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3464 ohci_soft_ed_t *sed = opipe->sed; 3465 ohci_soft_itd_t *sitd, *nsitd, *tail; 3466 ohci_physaddr_t buf, offs, noffs, bp0; 3467 int i, ncur, nframes; 3468 3469 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3470 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 3471 3472 mutex_enter(&sc->sc_lock); 3473 3474 if (sc->sc_dying) { 3475 mutex_exit(&sc->sc_lock); 3476 return; 3477 } 3478 3479 struct isoc *isoc = &opipe->isoc; 3480 3481 DPRINTFN(1, "used=%d next=%d xfer=%p nframes=%d", 3482 isoc->inuse, isoc->next, xfer, xfer->ux_nframes); 3483 3484 if (isoc->next == -1) { 3485 /* Not in use yet, schedule it a few frames ahead. */ 3486 isoc->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3487 DPRINTFN(2,"start next=%d", isoc->next, 0, 0, 0); 3488 } 3489 3490 sitd = opipe->tail.itd; 3491 opipe->tail.itd = ox->ox_sitds[0]; 3492 ox->ox_sitds[0] = sitd; 3493 3494 buf = DMAADDR(&xfer->ux_dmabuf, 0); 3495 bp0 = OHCI_PAGE(buf); 3496 offs = OHCI_PAGE_OFFSET(buf); 3497 nframes = xfer->ux_nframes; 3498 xfer->ux_hcpriv = sitd; 3499 size_t j = 1; 3500 for (i = ncur = 0; i < nframes; i++, ncur++) { 3501 noffs = offs + xfer->ux_frlengths[i]; 3502 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3503 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3504 3505 /* Allocate next ITD */ 3506 nsitd = ox->ox_sitds[j++]; 3507 KASSERT(nsitd != NULL); 3508 KASSERT(j < ox->ox_nsitd); 3509 3510 /* Fill current ITD */ 3511 sitd->itd.itd_flags = HTOO32( 3512 OHCI_ITD_NOCC | 3513 OHCI_ITD_SET_SF(isoc->next) | 3514 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3515 OHCI_ITD_SET_FC(ncur)); 3516 sitd->itd.itd_bp0 = HTOO32(bp0); 3517 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3518 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3519 sitd->nextitd = nsitd; 3520 sitd->xfer = xfer; 3521 sitd->flags = 0; 3522 #ifdef DIAGNOSTIC 3523 sitd->isdone = false; 3524 #endif 3525 ohci_hash_add_itd(sc, sitd); 3526 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3527 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3528 3529 sitd = nsitd; 3530 isoc->next = isoc->next + ncur; 3531 bp0 = OHCI_PAGE(buf + offs); 3532 ncur = 0; 3533 } 3534 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3535 offs = noffs; 3536 } 3537 KASSERT(j <= ox->ox_nsitd); 3538 3539 /* point at sentinel */ 3540 tail = opipe->tail.itd; 3541 memset(&tail->itd, 0, sizeof(tail->itd)); 3542 tail->nextitd = NULL; 3543 tail->xfer = NULL; 3544 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->itd), 3545 BUS_DMASYNC_PREWRITE); 3546 3547 /* Fixup last used ITD */ 3548 sitd->itd.itd_flags = HTOO32( 3549 OHCI_ITD_NOCC | 3550 OHCI_ITD_SET_SF(isoc->next) | 3551 OHCI_ITD_SET_DI(0) | 3552 OHCI_ITD_SET_FC(ncur)); 3553 sitd->itd.itd_bp0 = HTOO32(bp0); 3554 sitd->itd.itd_nextitd = HTOO32(tail->physaddr); 3555 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3556 sitd->nextitd = tail; 3557 sitd->xfer = xfer; 3558 sitd->flags = OHCI_CALL_DONE; 3559 #ifdef DIAGNOSTIC 3560 sitd->isdone = false; 3561 #endif 3562 ohci_hash_add_itd(sc, sitd); 3563 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3564 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3565 3566 isoc->next = isoc->next + ncur; 3567 isoc->inuse += nframes; 3568 3569 /* XXX pretend we did it all */ 3570 xfer->ux_actlen = offs; 3571 xfer->ux_status = USBD_IN_PROGRESS; 3572 3573 #ifdef OHCI_DEBUG 3574 if (ohcidebug >= 5) { 3575 DPRINTF("frame=%d", O32TOH(sc->sc_hcca->hcca_frame_number), 3576 0, 0, 0); 3577 ohci_dump_itds(sc, xfer->ux_hcpriv); 3578 ohci_dump_ed(sc, sed); 3579 } 3580 #endif 3581 3582 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3583 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3584 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3585 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3586 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3587 sizeof(sed->ed.ed_flags), 3588 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3589 mutex_exit(&sc->sc_lock); 3590 } 3591 3592 void 3593 ohci_device_isoc_abort(struct usbd_xfer *xfer) 3594 { 3595 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3596 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3597 ohci_soft_ed_t *sed; 3598 ohci_soft_itd_t *sitd; 3599 3600 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3601 DPRINTFN(1, "xfer=%p", xfer, 0, 0, 0); 3602 3603 KASSERT(mutex_owned(&sc->sc_lock)); 3604 3605 /* Transfer is already done. */ 3606 if (xfer->ux_status != USBD_NOT_STARTED && 3607 xfer->ux_status != USBD_IN_PROGRESS) { 3608 printf("ohci_device_isoc_abort: early return\n"); 3609 goto done; 3610 } 3611 3612 /* Give xfer the requested abort code. */ 3613 xfer->ux_status = USBD_CANCELLED; 3614 3615 sed = opipe->sed; 3616 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3617 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3618 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3619 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3620 sizeof(sed->ed.ed_flags), 3621 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3622 3623 sitd = xfer->ux_hcpriv; 3624 KASSERT(sitd); 3625 3626 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3627 3628 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3629 ohci_hash_rem_itd(sc, sitd); 3630 #ifdef DIAGNOSTIC 3631 DPRINTFN(1, "abort sets done sitd=%p", sitd, 0, 0, 0); 3632 sitd->isdone = true; 3633 #endif 3634 } 3635 3636 /* Run callback. */ 3637 usb_transfer_complete(xfer); 3638 3639 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3640 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3641 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3642 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3643 3644 done: 3645 KASSERT(mutex_owned(&sc->sc_lock)); 3646 } 3647 3648 void 3649 ohci_device_isoc_done(struct usbd_xfer *xfer) 3650 { 3651 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3652 DPRINTFN(1, "xfer=%p", xfer, 0, 0, 0); 3653 } 3654 3655 usbd_status 3656 ohci_setup_isoc(struct usbd_pipe *pipe) 3657 { 3658 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3659 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3660 struct isoc *isoc = &opipe->isoc; 3661 3662 isoc->next = -1; 3663 isoc->inuse = 0; 3664 3665 mutex_enter(&sc->sc_lock); 3666 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3667 mutex_exit(&sc->sc_lock); 3668 3669 return USBD_NORMAL_COMPLETION; 3670 } 3671 3672 void 3673 ohci_device_isoc_close(struct usbd_pipe *pipe) 3674 { 3675 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3676 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3677 3678 KASSERT(mutex_owned(&sc->sc_lock)); 3679 3680 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3681 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3682 ohci_close_pipe(pipe, sc->sc_isoc_head); 3683 #ifdef DIAGNOSTIC 3684 opipe->tail.itd->isdone = true; 3685 #endif 3686 ohci_free_sitd_locked(sc, opipe->tail.itd); 3687 } 3688
Indexes created Wed Sep 24 15:09:51 GMT 2025