ohci.c revision 1.274
1 /* $NetBSD: ohci.c,v 1.274 2017/10/28 00:37:12 pgoyette Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * USB Open Host Controller driver. 38 * 39 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 40 * USB spec: http://www.usb.org/developers/docs/ 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.274 2017/10/28 00:37:12 pgoyette Exp $"); 45 46 #ifdef _KERNEL_OPT 47 #include "opt_usb.h" 48 #endif 49 50 #include <sys/param.h> 51 52 #include <sys/cpu.h> 53 #include <sys/device.h> 54 #include <sys/kernel.h> 55 #include <sys/kmem.h> 56 #include <sys/proc.h> 57 #include <sys/queue.h> 58 #include <sys/select.h> 59 #include <sys/sysctl.h> 60 #include <sys/systm.h> 61 62 #include <machine/endian.h> 63 64 #include <dev/usb/usb.h> 65 #include <dev/usb/usbdi.h> 66 #include <dev/usb/usbdivar.h> 67 #include <dev/usb/usb_mem.h> 68 #include <dev/usb/usb_quirks.h> 69 70 #include <dev/usb/ohcireg.h> 71 #include <dev/usb/ohcivar.h> 72 #include <dev/usb/usbroothub.h> 73 #include <dev/usb/usbhist.h> 74 75 #ifdef USB_DEBUG 76 #ifndef OHCI_DEBUG 77 #define ohcidebug 0 78 #else 79 static int ohcidebug = 10; 80 81 SYSCTL_SETUP(sysctl_hw_ohci_setup, "sysctl hw.ohci setup") 82 { 83 int err; 84 const struct sysctlnode *rnode; 85 const struct sysctlnode *cnode; 86 87 err = sysctl_createv(clog, 0, NULL, &rnode, 88 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ohci", 89 SYSCTL_DESCR("ohci global controls"), 90 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 91 92 if (err) 93 goto fail; 94 95 /* control debugging printfs */ 96 err = sysctl_createv(clog, 0, &rnode, &cnode, 97 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 98 "debug", SYSCTL_DESCR("Enable debugging output"), 99 NULL, 0, &ohcidebug, sizeof(ohcidebug), CTL_CREATE, CTL_EOL); 100 if (err) 101 goto fail; 102 103 return; 104 fail: 105 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 106 } 107 108 #endif /* OHCI_DEBUG */ 109 #endif /* USB_DEBUG */ 110 111 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ohcidebug,FMT,A,B,C,D) 112 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ohcidebug,N,FMT,A,B,C,D) 113 #define OHCIHIST_FUNC() USBHIST_FUNC() 114 #define OHCIHIST_CALLED(name) USBHIST_CALLED(ohcidebug) 115 116 #if BYTE_ORDER == BIG_ENDIAN 117 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 118 #else 119 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 120 #endif 121 122 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 123 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 124 #define HTOO16(val) O16TOH(val) 125 #define HTOO32(val) O32TOH(val) 126 127 struct ohci_pipe; 128 129 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 130 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 131 132 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 133 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 134 Static void ohci_free_std_locked(ohci_softc_t *, ohci_soft_td_t *); 135 136 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 137 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 138 Static void ohci_free_sitd_locked(ohci_softc_t *, 139 ohci_soft_itd_t *); 140 141 Static int ohci_alloc_std_chain(ohci_softc_t *, struct usbd_xfer *, 142 int, int); 143 Static void ohci_free_stds(ohci_softc_t *, struct ohci_xfer *); 144 145 Static void ohci_reset_std_chain(ohci_softc_t *, struct usbd_xfer *, 146 int, int, ohci_soft_td_t *, ohci_soft_td_t **); 147 148 Static usbd_status ohci_open(struct usbd_pipe *); 149 Static void ohci_poll(struct usbd_bus *); 150 Static void ohci_softintr(void *); 151 Static void ohci_rhsc(ohci_softc_t *, struct usbd_xfer *); 152 Static void ohci_rhsc_softint(void *); 153 154 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 155 ohci_soft_ed_t *); 156 157 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 158 ohci_soft_ed_t *); 159 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 160 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 161 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 162 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 163 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 164 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 165 166 Static usbd_status ohci_setup_isoc(struct usbd_pipe *); 167 Static void ohci_device_isoc_enter(struct usbd_xfer *); 168 169 Static struct usbd_xfer * 170 ohci_allocx(struct usbd_bus *, unsigned int); 171 Static void ohci_freex(struct usbd_bus *, struct usbd_xfer *); 172 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 173 Static int ohci_roothub_ctrl(struct usbd_bus *, 174 usb_device_request_t *, void *, int); 175 176 Static usbd_status ohci_root_intr_transfer(struct usbd_xfer *); 177 Static usbd_status ohci_root_intr_start(struct usbd_xfer *); 178 Static void ohci_root_intr_abort(struct usbd_xfer *); 179 Static void ohci_root_intr_close(struct usbd_pipe *); 180 Static void ohci_root_intr_done(struct usbd_xfer *); 181 182 Static int ohci_device_ctrl_init(struct usbd_xfer *); 183 Static void ohci_device_ctrl_fini(struct usbd_xfer *); 184 Static usbd_status ohci_device_ctrl_transfer(struct usbd_xfer *); 185 Static usbd_status ohci_device_ctrl_start(struct usbd_xfer *); 186 Static void ohci_device_ctrl_abort(struct usbd_xfer *); 187 Static void ohci_device_ctrl_close(struct usbd_pipe *); 188 Static void ohci_device_ctrl_done(struct usbd_xfer *); 189 190 Static int ohci_device_bulk_init(struct usbd_xfer *); 191 Static void ohci_device_bulk_fini(struct usbd_xfer *); 192 Static usbd_status ohci_device_bulk_transfer(struct usbd_xfer *); 193 Static usbd_status ohci_device_bulk_start(struct usbd_xfer *); 194 Static void ohci_device_bulk_abort(struct usbd_xfer *); 195 Static void ohci_device_bulk_close(struct usbd_pipe *); 196 Static void ohci_device_bulk_done(struct usbd_xfer *); 197 198 Static int ohci_device_intr_init(struct usbd_xfer *); 199 Static void ohci_device_intr_fini(struct usbd_xfer *); 200 Static usbd_status ohci_device_intr_transfer(struct usbd_xfer *); 201 Static usbd_status ohci_device_intr_start(struct usbd_xfer *); 202 Static void ohci_device_intr_abort(struct usbd_xfer *); 203 Static void ohci_device_intr_close(struct usbd_pipe *); 204 Static void ohci_device_intr_done(struct usbd_xfer *); 205 206 Static int ohci_device_isoc_init(struct usbd_xfer *); 207 Static void ohci_device_isoc_fini(struct usbd_xfer *); 208 Static usbd_status ohci_device_isoc_transfer(struct usbd_xfer *); 209 Static void ohci_device_isoc_abort(struct usbd_xfer *); 210 Static void ohci_device_isoc_close(struct usbd_pipe *); 211 Static void ohci_device_isoc_done(struct usbd_xfer *); 212 213 Static usbd_status ohci_device_setintr(ohci_softc_t *, 214 struct ohci_pipe *, int); 215 216 Static void ohci_timeout(void *); 217 Static void ohci_timeout_task(void *); 218 Static void ohci_rhsc_enable(void *); 219 220 Static void ohci_close_pipe(struct usbd_pipe *, ohci_soft_ed_t *); 221 Static void ohci_abort_xfer(struct usbd_xfer *, usbd_status); 222 223 Static void ohci_device_clear_toggle(struct usbd_pipe *); 224 Static void ohci_noop(struct usbd_pipe *); 225 226 #ifdef OHCI_DEBUG 227 Static void ohci_dumpregs(ohci_softc_t *); 228 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 229 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 230 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 231 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 232 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 233 #endif 234 235 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 236 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 237 #define OWRITE1(sc, r, x) \ 238 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 239 #define OWRITE2(sc, r, x) \ 240 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 241 #define OWRITE4(sc, r, x) \ 242 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 243 244 static __inline uint32_t 245 OREAD4(ohci_softc_t *sc, bus_size_t r) 246 { 247 248 OBARR(sc); 249 return bus_space_read_4(sc->iot, sc->ioh, r); 250 } 251 252 /* Reverse the bits in a value 0 .. 31 */ 253 Static uint8_t revbits[OHCI_NO_INTRS] = 254 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 255 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 256 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 257 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 258 259 struct ohci_pipe { 260 struct usbd_pipe pipe; 261 ohci_soft_ed_t *sed; 262 union { 263 ohci_soft_td_t *td; 264 ohci_soft_itd_t *itd; 265 } tail; 266 /* Info needed for different pipe kinds. */ 267 union { 268 /* Control pipe */ 269 struct { 270 usb_dma_t reqdma; 271 } ctrl; 272 /* Interrupt pipe */ 273 struct { 274 int nslots; 275 int pos; 276 } intr; 277 /* Isochronous pipe */ 278 struct isoc { 279 int next, inuse; 280 } isoc; 281 }; 282 }; 283 284 Static const struct usbd_bus_methods ohci_bus_methods = { 285 .ubm_open = ohci_open, 286 .ubm_softint = ohci_softintr, 287 .ubm_dopoll = ohci_poll, 288 .ubm_allocx = ohci_allocx, 289 .ubm_freex = ohci_freex, 290 .ubm_getlock = ohci_get_lock, 291 .ubm_rhctrl = ohci_roothub_ctrl, 292 }; 293 294 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 295 .upm_transfer = ohci_root_intr_transfer, 296 .upm_start = ohci_root_intr_start, 297 .upm_abort = ohci_root_intr_abort, 298 .upm_close = ohci_root_intr_close, 299 .upm_cleartoggle = ohci_noop, 300 .upm_done = ohci_root_intr_done, 301 }; 302 303 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 304 .upm_init = ohci_device_ctrl_init, 305 .upm_fini = ohci_device_ctrl_fini, 306 .upm_transfer = ohci_device_ctrl_transfer, 307 .upm_start = ohci_device_ctrl_start, 308 .upm_abort = ohci_device_ctrl_abort, 309 .upm_close = ohci_device_ctrl_close, 310 .upm_cleartoggle = ohci_noop, 311 .upm_done = ohci_device_ctrl_done, 312 }; 313 314 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 315 .upm_init = ohci_device_intr_init, 316 .upm_fini = ohci_device_intr_fini, 317 .upm_transfer = ohci_device_intr_transfer, 318 .upm_start = ohci_device_intr_start, 319 .upm_abort = ohci_device_intr_abort, 320 .upm_close = ohci_device_intr_close, 321 .upm_cleartoggle = ohci_device_clear_toggle, 322 .upm_done = ohci_device_intr_done, 323 }; 324 325 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 326 .upm_init = ohci_device_bulk_init, 327 .upm_fini = ohci_device_bulk_fini, 328 .upm_transfer = ohci_device_bulk_transfer, 329 .upm_start = ohci_device_bulk_start, 330 .upm_abort = ohci_device_bulk_abort, 331 .upm_close = ohci_device_bulk_close, 332 .upm_cleartoggle = ohci_device_clear_toggle, 333 .upm_done = ohci_device_bulk_done, 334 }; 335 336 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 337 .upm_init = ohci_device_isoc_init, 338 .upm_fini = ohci_device_isoc_fini, 339 .upm_transfer = ohci_device_isoc_transfer, 340 .upm_abort = ohci_device_isoc_abort, 341 .upm_close = ohci_device_isoc_close, 342 .upm_cleartoggle = ohci_noop, 343 .upm_done = ohci_device_isoc_done, 344 }; 345 346 int 347 ohci_activate(device_t self, enum devact act) 348 { 349 struct ohci_softc *sc = device_private(self); 350 351 switch (act) { 352 case DVACT_DEACTIVATE: 353 sc->sc_dying = 1; 354 return 0; 355 default: 356 return EOPNOTSUPP; 357 } 358 } 359 360 void 361 ohci_childdet(device_t self, device_t child) 362 { 363 struct ohci_softc *sc = device_private(self); 364 365 KASSERT(sc->sc_child == child); 366 sc->sc_child = NULL; 367 } 368 369 int 370 ohci_detach(struct ohci_softc *sc, int flags) 371 { 372 int rv = 0; 373 374 if (sc->sc_child != NULL) 375 rv = config_detach(sc->sc_child, flags); 376 377 if (rv != 0) 378 return rv; 379 380 callout_halt(&sc->sc_tmo_rhsc, &sc->sc_lock); 381 382 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 383 callout_destroy(&sc->sc_tmo_rhsc); 384 385 softint_disestablish(sc->sc_rhsc_si); 386 387 cv_destroy(&sc->sc_softwake_cv); 388 389 mutex_destroy(&sc->sc_lock); 390 mutex_destroy(&sc->sc_intr_lock); 391 392 if (sc->sc_hcca != NULL) 393 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 394 pool_cache_destroy(sc->sc_xferpool); 395 396 return rv; 397 } 398 399 ohci_soft_ed_t * 400 ohci_alloc_sed(ohci_softc_t *sc) 401 { 402 ohci_soft_ed_t *sed; 403 usbd_status err; 404 int i, offs; 405 usb_dma_t dma; 406 407 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 408 409 mutex_enter(&sc->sc_lock); 410 if (sc->sc_freeeds == NULL) { 411 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 412 mutex_exit(&sc->sc_lock); 413 414 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 415 OHCI_ED_ALIGN, &dma); 416 if (err) 417 return 0; 418 419 mutex_enter(&sc->sc_lock); 420 for (i = 0; i < OHCI_SED_CHUNK; i++) { 421 offs = i * OHCI_SED_SIZE; 422 sed = KERNADDR(&dma, offs); 423 sed->physaddr = DMAADDR(&dma, offs); 424 sed->dma = dma; 425 sed->offs = offs; 426 sed->next = sc->sc_freeeds; 427 sc->sc_freeeds = sed; 428 } 429 } 430 sed = sc->sc_freeeds; 431 sc->sc_freeeds = sed->next; 432 mutex_exit(&sc->sc_lock); 433 434 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 435 sed->next = 0; 436 return sed; 437 } 438 439 static inline void 440 ohci_free_sed_locked(ohci_softc_t *sc, ohci_soft_ed_t *sed) 441 { 442 443 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 444 445 sed->next = sc->sc_freeeds; 446 sc->sc_freeeds = sed; 447 } 448 449 void 450 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 451 { 452 453 mutex_enter(&sc->sc_lock); 454 ohci_free_sed_locked(sc, sed); 455 mutex_exit(&sc->sc_lock); 456 } 457 458 ohci_soft_td_t * 459 ohci_alloc_std(ohci_softc_t *sc) 460 { 461 ohci_soft_td_t *std; 462 usbd_status err; 463 int i, offs; 464 usb_dma_t dma; 465 466 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 467 468 mutex_enter(&sc->sc_lock); 469 if (sc->sc_freetds == NULL) { 470 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 471 mutex_exit(&sc->sc_lock); 472 473 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 474 OHCI_TD_ALIGN, &dma); 475 if (err) 476 return NULL; 477 478 mutex_enter(&sc->sc_lock); 479 for (i = 0; i < OHCI_STD_CHUNK; i++) { 480 offs = i * OHCI_STD_SIZE; 481 std = KERNADDR(&dma, offs); 482 std->physaddr = DMAADDR(&dma, offs); 483 std->dma = dma; 484 std->offs = offs; 485 std->nexttd = sc->sc_freetds; 486 sc->sc_freetds = std; 487 } 488 } 489 490 std = sc->sc_freetds; 491 sc->sc_freetds = std->nexttd; 492 mutex_exit(&sc->sc_lock); 493 494 memset(&std->td, 0, sizeof(ohci_td_t)); 495 std->nexttd = NULL; 496 std->xfer = NULL; 497 498 return std; 499 } 500 501 void 502 ohci_free_std_locked(ohci_softc_t *sc, ohci_soft_td_t *std) 503 { 504 505 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 506 507 std->nexttd = sc->sc_freetds; 508 sc->sc_freetds = std; 509 } 510 511 void 512 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 513 { 514 515 mutex_enter(&sc->sc_lock); 516 ohci_free_std_locked(sc, std); 517 mutex_exit(&sc->sc_lock); 518 } 519 520 Static int 521 ohci_alloc_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, int length, int rd) 522 { 523 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 524 uint16_t flags = xfer->ux_flags; 525 526 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 527 528 DPRINTFN(8, "addr=%jd endpt=%jd len=%jd speed=%jd", 529 xfer->ux_pipe->up_dev->ud_addr, 530 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 531 length, xfer->ux_pipe->up_dev->ud_speed); 532 533 ASSERT_SLEEPABLE(); 534 KASSERT(length != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 535 536 size_t nstd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 537 nstd += ((length + OHCI_PAGE_SIZE - 1) / OHCI_PAGE_SIZE); 538 ox->ox_stds = kmem_zalloc(sizeof(ohci_soft_td_t *) * nstd, 539 KM_SLEEP); 540 ox->ox_nstd = nstd; 541 542 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, nstd, 0, 0); 543 544 for (size_t j = 0; j < ox->ox_nstd;) { 545 ohci_soft_td_t *cur = ohci_alloc_std(sc); 546 if (cur == NULL) 547 goto nomem; 548 549 ox->ox_stds[j++] = cur; 550 cur->xfer = xfer; 551 cur->flags = 0; 552 } 553 554 return 0; 555 556 nomem: 557 ohci_free_stds(sc, ox); 558 kmem_free(ox->ox_stds, sizeof(ohci_soft_td_t *) * nstd); 559 560 return ENOMEM; 561 } 562 563 Static void 564 ohci_free_stds(ohci_softc_t *sc, struct ohci_xfer *ox) 565 { 566 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 567 DPRINTF("ox=%#jx", (uintptr_t)ox, 0, 0, 0); 568 569 mutex_enter(&sc->sc_lock); 570 for (size_t i = 0; i < ox->ox_nstd; i++) { 571 ohci_soft_td_t *std = ox->ox_stds[i]; 572 if (std == NULL) 573 break; 574 ohci_free_std_locked(sc, std); 575 } 576 mutex_exit(&sc->sc_lock); 577 } 578 579 void 580 ohci_reset_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, 581 int alen, int rd, ohci_soft_td_t *sp, ohci_soft_td_t **ep) 582 { 583 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 584 ohci_soft_td_t *next, *cur; 585 int len, curlen; 586 usb_dma_t *dma = &xfer->ux_dmabuf; 587 uint16_t flags = xfer->ux_flags; 588 589 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 590 DPRINTF("start len=%jd", alen, 0, 0, 0); 591 592 KASSERT(mutex_owned(&sc->sc_lock)); 593 594 DPRINTFN(8, "addr=%jd endpt=%jd len=%jd speed=%jd", 595 xfer->ux_pipe->up_dev->ud_addr, 596 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 597 alen, xfer->ux_pipe->up_dev->ud_speed); 598 599 KASSERT(sp); 600 601 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 602 603 /* 604 * Assign next for the len == 0 case where we don't go through the 605 * main loop. 606 */ 607 len = alen; 608 cur = next = sp; 609 610 usb_syncmem(dma, 0, len, 611 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 612 const uint32_t tdflags = HTOO32( 613 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 614 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 615 616 size_t curoffs = 0; 617 for (size_t j = 1; len != 0;) { 618 if (j == ox->ox_nstd) 619 next = NULL; 620 else 621 next = ox->ox_stds[j++]; 622 KASSERT(next != cur); 623 624 curlen = 0; 625 const ohci_physaddr_t sdataphys = DMAADDR(dma, curoffs); 626 ohci_physaddr_t edataphys = DMAADDR(dma, curoffs + len - 1); 627 628 const ohci_physaddr_t sphyspg = OHCI_PAGE(sdataphys); 629 ohci_physaddr_t ephyspg = OHCI_PAGE(edataphys); 630 /* 631 * The OHCI hardware can handle at most one page 632 * crossing per TD 633 */ 634 curlen = len; 635 if (sphyspg != ephyspg && 636 sphyspg + OHCI_PAGE_SIZE != ephyspg) { 637 /* must use multiple TDs, fill as much as possible. */ 638 curlen = 2 * OHCI_PAGE_SIZE - 639 OHCI_PAGE_OFFSET(sdataphys); 640 /* the length must be a multiple of the max size */ 641 curlen -= curlen % mps; 642 edataphys = DMAADDR(dma, curoffs + curlen - 1); 643 } 644 KASSERT(curlen != 0); 645 DPRINTFN(4, "sdataphys=0x%08jx edataphys=0x%08jx " 646 "len=%jd curlen=%jd", sdataphys, edataphys, len, curlen); 647 648 cur->td.td_flags = tdflags; 649 cur->td.td_cbp = HTOO32(sdataphys); 650 cur->td.td_be = HTOO32(edataphys); 651 cur->td.td_nexttd = (next != NULL) ? HTOO32(next->physaddr) : 0; 652 cur->nexttd = next; 653 cur->len = curlen; 654 cur->flags = OHCI_ADD_LEN; 655 cur->xfer = xfer; 656 ohci_hash_add_td(sc, cur); 657 658 curoffs += curlen; 659 len -= curlen; 660 661 if (len != 0) { 662 KASSERT(next != NULL); 663 DPRINTFN(10, "extend chain", 0, 0, 0, 0); 664 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 665 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 666 667 cur = next; 668 } 669 } 670 cur->td.td_flags |= 671 HTOO32(xfer->ux_flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0); 672 673 if (!rd && 674 (flags & USBD_FORCE_SHORT_XFER) && 675 alen % mps == 0) { 676 /* We're adding a ZLP so sync the previous TD */ 677 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 678 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 679 680 /* Force a 0 length transfer at the end. */ 681 682 KASSERT(next != NULL); 683 cur = next; 684 685 cur->td.td_flags = tdflags; 686 cur->td.td_cbp = 0; /* indicate 0 length packet */ 687 cur->td.td_nexttd = 0; 688 cur->td.td_be = ~0; 689 cur->nexttd = NULL; 690 cur->len = 0; 691 cur->flags = 0; 692 cur->xfer = xfer; 693 ohci_hash_add_td(sc, cur); 694 695 DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0); 696 } 697 698 /* Last TD gets usb_syncmem'ed by caller */ 699 *ep = cur; 700 } 701 702 ohci_soft_itd_t * 703 ohci_alloc_sitd(ohci_softc_t *sc) 704 { 705 ohci_soft_itd_t *sitd; 706 usbd_status err; 707 int i, offs; 708 usb_dma_t dma; 709 710 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 711 712 mutex_enter(&sc->sc_lock); 713 if (sc->sc_freeitds == NULL) { 714 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 715 mutex_exit(&sc->sc_lock); 716 717 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 718 OHCI_ITD_ALIGN, &dma); 719 if (err) 720 return NULL; 721 mutex_enter(&sc->sc_lock); 722 for (i = 0; i < OHCI_SITD_CHUNK; i++) { 723 offs = i * OHCI_SITD_SIZE; 724 sitd = KERNADDR(&dma, offs); 725 sitd->physaddr = DMAADDR(&dma, offs); 726 sitd->dma = dma; 727 sitd->offs = offs; 728 sitd->nextitd = sc->sc_freeitds; 729 sc->sc_freeitds = sitd; 730 } 731 } 732 733 sitd = sc->sc_freeitds; 734 sc->sc_freeitds = sitd->nextitd; 735 mutex_exit(&sc->sc_lock); 736 737 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 738 sitd->nextitd = NULL; 739 sitd->xfer = NULL; 740 741 #ifdef DIAGNOSTIC 742 sitd->isdone = true; 743 #endif 744 745 return sitd; 746 } 747 748 Static void 749 ohci_free_sitd_locked(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 750 { 751 752 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 753 DPRINTFN(10, "sitd=%#jx", (uintptr_t)sitd, 0, 0, 0); 754 755 KASSERT(sitd->isdone); 756 #ifdef DIAGNOSTIC 757 /* Warn double free */ 758 sitd->isdone = false; 759 #endif 760 761 sitd->nextitd = sc->sc_freeitds; 762 sc->sc_freeitds = sitd; 763 } 764 765 void 766 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 767 { 768 769 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 770 771 mutex_enter(&sc->sc_lock); 772 ohci_free_sitd_locked(sc, sitd); 773 mutex_exit(&sc->sc_lock); 774 } 775 776 int 777 ohci_init(ohci_softc_t *sc) 778 { 779 ohci_soft_ed_t *sed, *psed; 780 usbd_status err; 781 int i; 782 uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */; 783 784 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 785 786 aprint_normal_dev(sc->sc_dev, ""); 787 788 sc->sc_hcca = NULL; 789 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 790 791 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 792 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 793 cv_init(&sc->sc_softwake_cv, "ohciab"); 794 795 sc->sc_rhsc_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 796 ohci_rhsc_softint, sc); 797 798 for (i = 0; i < OHCI_HASH_SIZE; i++) 799 LIST_INIT(&sc->sc_hash_tds[i]); 800 for (i = 0; i < OHCI_HASH_SIZE; i++) 801 LIST_INIT(&sc->sc_hash_itds[i]); 802 803 sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0, 804 "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL); 805 806 rev = OREAD4(sc, OHCI_REVISION); 807 aprint_normal("OHCI version %d.%d%s\n", 808 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 809 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 810 811 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 812 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 813 sc->sc_bus.ub_revision = USBREV_UNKNOWN; 814 return -1; 815 } 816 sc->sc_bus.ub_revision = USBREV_1_0; 817 sc->sc_bus.ub_usedma = true; 818 819 /* XXX determine alignment by R/W */ 820 /* Allocate the HCCA area. */ 821 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 822 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 823 if (err) { 824 sc->sc_hcca = NULL; 825 return err; 826 } 827 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 828 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 829 830 sc->sc_eintrs = OHCI_NORMAL_INTRS; 831 832 /* Allocate dummy ED that starts the control list. */ 833 sc->sc_ctrl_head = ohci_alloc_sed(sc); 834 if (sc->sc_ctrl_head == NULL) { 835 err = ENOMEM; 836 goto bad1; 837 } 838 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 839 840 /* Allocate dummy ED that starts the bulk list. */ 841 sc->sc_bulk_head = ohci_alloc_sed(sc); 842 if (sc->sc_bulk_head == NULL) { 843 err = ENOMEM; 844 goto bad2; 845 } 846 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 847 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 848 sizeof(sc->sc_bulk_head->ed), 849 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 850 851 /* Allocate dummy ED that starts the isochronous list. */ 852 sc->sc_isoc_head = ohci_alloc_sed(sc); 853 if (sc->sc_isoc_head == NULL) { 854 err = ENOMEM; 855 goto bad3; 856 } 857 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 858 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 859 sizeof(sc->sc_isoc_head->ed), 860 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 861 862 /* Allocate all the dummy EDs that make up the interrupt tree. */ 863 for (i = 0; i < OHCI_NO_EDS; i++) { 864 sed = ohci_alloc_sed(sc); 865 if (sed == NULL) { 866 while (--i >= 0) 867 ohci_free_sed(sc, sc->sc_eds[i]); 868 err = ENOMEM; 869 goto bad4; 870 } 871 /* All ED fields are set to 0. */ 872 sc->sc_eds[i] = sed; 873 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 874 if (i != 0) 875 psed = sc->sc_eds[(i-1) / 2]; 876 else 877 psed= sc->sc_isoc_head; 878 sed->next = psed; 879 sed->ed.ed_nexted = HTOO32(psed->physaddr); 880 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 881 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 882 } 883 /* 884 * Fill HCCA interrupt table. The bit reversal is to get 885 * the tree set up properly to spread the interrupts. 886 */ 887 for (i = 0; i < OHCI_NO_INTRS; i++) 888 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 889 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 890 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 891 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 892 893 #ifdef OHCI_DEBUG 894 DPRINTFN(15, "--- dump start ---", 0, 0, 0 ,0); 895 if (ohcidebug >= 15) { 896 for (i = 0; i < OHCI_NO_EDS; i++) { 897 DPRINTFN(15, "ed#%jd ", i, 0, 0, 0); 898 ohci_dump_ed(sc, sc->sc_eds[i]); 899 } 900 DPRINTFN(15, "iso", 0, 0, 0 ,0); 901 ohci_dump_ed(sc, sc->sc_isoc_head); 902 } 903 DPRINTFN(15, "--- dump end ---", 0, 0, 0 ,0); 904 #endif 905 906 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 907 ctl = OREAD4(sc, OHCI_CONTROL); 908 rwc = ctl & OHCI_RWC; 909 fm = OREAD4(sc, OHCI_FM_INTERVAL); 910 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 911 /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */ 912 913 /* Determine in what context we are running. */ 914 if (ctl & OHCI_IR) { 915 /* SMM active, request change */ 916 DPRINTF("SMM active, request owner change", 0, 0, 0, 0); 917 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 918 (OHCI_OC | OHCI_MIE)) 919 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 920 s = OREAD4(sc, OHCI_COMMAND_STATUS); 921 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 922 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 923 usb_delay_ms(&sc->sc_bus, 1); 924 ctl = OREAD4(sc, OHCI_CONTROL); 925 } 926 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 927 if ((ctl & OHCI_IR) == 0) { 928 aprint_error_dev(sc->sc_dev, 929 "SMM does not respond, resetting\n"); 930 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 931 goto reset; 932 } 933 #if 0 934 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 935 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 936 /* BIOS started controller. */ 937 DPRINTF("BIOS active", 0, 0, 0, 0); 938 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 939 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 940 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 941 } 942 #endif 943 } else { 944 DPRINTF("cold started", 0 ,0 ,0 ,0); 945 reset: 946 /* Controller was cold started. */ 947 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 948 } 949 950 /* 951 * This reset should not be necessary according to the OHCI spec, but 952 * without it some controllers do not start. 953 */ 954 DPRINTF("sc %#jx: resetting", (uintptr_t)sc, 0, 0, 0); 955 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 956 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 957 958 /* We now own the host controller and the bus has been reset. */ 959 960 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 961 /* Nominal time for a reset is 10 us. */ 962 for (i = 0; i < 10; i++) { 963 delay(10); 964 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 965 if (!hcr) 966 break; 967 } 968 if (hcr) { 969 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 970 err = EIO; 971 goto bad5; 972 } 973 #ifdef OHCI_DEBUG 974 if (ohcidebug >= 15) 975 ohci_dumpregs(sc); 976 #endif 977 978 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 979 980 /* Set up HC registers. */ 981 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 982 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 983 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 984 /* disable all interrupts and then switch on all desired interrupts */ 985 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 986 /* switch on desired functional features */ 987 ctl = OREAD4(sc, OHCI_CONTROL); 988 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 989 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 990 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 991 /* And finally start it! */ 992 OWRITE4(sc, OHCI_CONTROL, ctl); 993 994 /* 995 * The controller is now OPERATIONAL. Set a some final 996 * registers that should be set earlier, but that the 997 * controller ignores when in the SUSPEND state. 998 */ 999 ival = OHCI_GET_IVAL(fm); 1000 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 1001 fm |= OHCI_FSMPS(ival) | ival; 1002 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 1003 per = OHCI_PERIODIC(ival); /* 90% periodic */ 1004 OWRITE4(sc, OHCI_PERIODIC_START, per); 1005 1006 if (sc->sc_flags & OHCIF_SUPERIO) { 1007 /* no overcurrent protection */ 1008 desca |= OHCI_NOCP; 1009 /* 1010 * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning 1011 * that 1012 * - ports are always power switched 1013 * - don't wait for powered root hub port 1014 */ 1015 desca &= ~(__SHIFTIN(0xff, OHCI_POTPGT_MASK) | OHCI_NPS); 1016 } 1017 1018 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 1019 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 1020 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 1021 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 1022 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 1023 1024 /* 1025 * The AMD756 requires a delay before re-reading the register, 1026 * otherwise it will occasionally report 0 ports. 1027 */ 1028 sc->sc_noport = 0; 1029 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 1030 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 1031 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 1032 } 1033 1034 #ifdef OHCI_DEBUG 1035 if (ohcidebug >= 5) 1036 ohci_dumpregs(sc); 1037 #endif 1038 1039 /* Set up the bus struct. */ 1040 sc->sc_bus.ub_methods = &ohci_bus_methods; 1041 sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe); 1042 1043 sc->sc_control = sc->sc_intre = 0; 1044 1045 /* Finally, turn on interrupts. */ 1046 DPRINTF("enabling %#jx", sc->sc_eintrs | OHCI_MIE, 0, 0, 0); 1047 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 1048 1049 return 0; 1050 1051 bad5: 1052 for (i = 0; i < OHCI_NO_EDS; i++) 1053 ohci_free_sed(sc, sc->sc_eds[i]); 1054 bad4: 1055 ohci_free_sed(sc, sc->sc_isoc_head); 1056 bad3: 1057 ohci_free_sed(sc, sc->sc_bulk_head); 1058 bad2: 1059 ohci_free_sed(sc, sc->sc_ctrl_head); 1060 bad1: 1061 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 1062 sc->sc_hcca = NULL; 1063 return err; 1064 } 1065 1066 struct usbd_xfer * 1067 ohci_allocx(struct usbd_bus *bus, unsigned int nframes) 1068 { 1069 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1070 struct usbd_xfer *xfer; 1071 1072 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1073 if (xfer != NULL) { 1074 memset(xfer, 0, sizeof(struct ohci_xfer)); 1075 #ifdef DIAGNOSTIC 1076 xfer->ux_state = XFER_BUSY; 1077 #endif 1078 } 1079 return xfer; 1080 } 1081 1082 void 1083 ohci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1084 { 1085 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1086 1087 KASSERTMSG(xfer->ux_state == XFER_BUSY, 1088 "xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state); 1089 #ifdef DIAGNOSTIC 1090 xfer->ux_state = XFER_FREE; 1091 #endif 1092 pool_cache_put(sc->sc_xferpool, xfer); 1093 } 1094 1095 Static void 1096 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1097 { 1098 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1099 1100 *lock = &sc->sc_lock; 1101 } 1102 1103 /* 1104 * Shut down the controller when the system is going down. 1105 */ 1106 bool 1107 ohci_shutdown(device_t self, int flags) 1108 { 1109 ohci_softc_t *sc = device_private(self); 1110 1111 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1112 1113 DPRINTF("stopping the HC", 0, 0, 0, 0); 1114 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1115 return true; 1116 } 1117 1118 bool 1119 ohci_resume(device_t dv, const pmf_qual_t *qual) 1120 { 1121 ohci_softc_t *sc = device_private(dv); 1122 uint32_t ctl; 1123 1124 mutex_spin_enter(&sc->sc_intr_lock); 1125 sc->sc_bus.ub_usepolling++; 1126 mutex_spin_exit(&sc->sc_intr_lock); 1127 1128 /* Some broken BIOSes do not recover these values */ 1129 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1130 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1131 sc->sc_ctrl_head->physaddr); 1132 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1133 sc->sc_bulk_head->physaddr); 1134 if (sc->sc_intre) 1135 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1136 (OHCI_ALL_INTRS | OHCI_MIE)); 1137 if (sc->sc_control) 1138 ctl = sc->sc_control; 1139 else 1140 ctl = OREAD4(sc, OHCI_CONTROL); 1141 ctl |= OHCI_HCFS_RESUME; 1142 OWRITE4(sc, OHCI_CONTROL, ctl); 1143 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1144 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1145 OWRITE4(sc, OHCI_CONTROL, ctl); 1146 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1147 sc->sc_control = sc->sc_intre = 0; 1148 1149 mutex_spin_enter(&sc->sc_intr_lock); 1150 sc->sc_bus.ub_usepolling--; 1151 mutex_spin_exit(&sc->sc_intr_lock); 1152 1153 return true; 1154 } 1155 1156 bool 1157 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1158 { 1159 ohci_softc_t *sc = device_private(dv); 1160 uint32_t ctl; 1161 1162 mutex_spin_enter(&sc->sc_intr_lock); 1163 sc->sc_bus.ub_usepolling++; 1164 mutex_spin_exit(&sc->sc_intr_lock); 1165 1166 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1167 if (sc->sc_control == 0) { 1168 /* 1169 * Preserve register values, in case that BIOS 1170 * does not recover them. 1171 */ 1172 sc->sc_control = ctl; 1173 sc->sc_intre = OREAD4(sc, 1174 OHCI_INTERRUPT_ENABLE); 1175 } 1176 ctl |= OHCI_HCFS_SUSPEND; 1177 OWRITE4(sc, OHCI_CONTROL, ctl); 1178 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1179 1180 mutex_spin_enter(&sc->sc_intr_lock); 1181 sc->sc_bus.ub_usepolling--; 1182 mutex_spin_exit(&sc->sc_intr_lock); 1183 1184 return true; 1185 } 1186 1187 #ifdef OHCI_DEBUG 1188 void 1189 ohci_dumpregs(ohci_softc_t *sc) 1190 { 1191 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1192 1193 DPRINTF("rev=0x%08jx control=0x%08jx command=0x%08jx", 1194 OREAD4(sc, OHCI_REVISION), 1195 OREAD4(sc, OHCI_CONTROL), 1196 OREAD4(sc, OHCI_COMMAND_STATUS), 0); 1197 DPRINTF(" intrstat=0x%08jx intre=0x%08jx intrd=0x%08jx", 1198 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1199 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1200 OREAD4(sc, OHCI_INTERRUPT_DISABLE), 0); 1201 DPRINTF(" hcca=0x%08jx percur=0x%08jx ctrlhd=0x%08jx", 1202 OREAD4(sc, OHCI_HCCA), 1203 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1204 OREAD4(sc, OHCI_CONTROL_HEAD_ED), 0); 1205 DPRINTF(" ctrlcur=0x%08jx bulkhd=0x%08jx bulkcur=0x%08jx", 1206 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1207 OREAD4(sc, OHCI_BULK_HEAD_ED), 1208 OREAD4(sc, OHCI_BULK_CURRENT_ED) ,0); 1209 DPRINTF(" done=0x%08jx fmival=0x%08jx fmrem=0x%08jx", 1210 OREAD4(sc, OHCI_DONE_HEAD), 1211 OREAD4(sc, OHCI_FM_INTERVAL), 1212 OREAD4(sc, OHCI_FM_REMAINING), 0); 1213 DPRINTF(" fmnum=0x%08jx perst=0x%08jx lsthrs=0x%08jx", 1214 OREAD4(sc, OHCI_FM_NUMBER), 1215 OREAD4(sc, OHCI_PERIODIC_START), 1216 OREAD4(sc, OHCI_LS_THRESHOLD), 0); 1217 DPRINTF(" desca=0x%08jx descb=0x%08jx stat=0x%08jx", 1218 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1219 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1220 OREAD4(sc, OHCI_RH_STATUS), 0); 1221 DPRINTF(" port1=0x%08jx port2=0x%08jx", 1222 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1223 OREAD4(sc, OHCI_RH_PORT_STATUS(2)), 0, 0); 1224 DPRINTF(" HCCA: frame_number=0x%04jx done_head=0x%08jx", 1225 O32TOH(sc->sc_hcca->hcca_frame_number), 1226 O32TOH(sc->sc_hcca->hcca_done_head), 0, 0); 1227 } 1228 #endif 1229 1230 Static int ohci_intr1(ohci_softc_t *); 1231 1232 int 1233 ohci_intr(void *p) 1234 { 1235 ohci_softc_t *sc = p; 1236 int ret = 0; 1237 1238 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1239 1240 if (sc == NULL) 1241 return 0; 1242 1243 mutex_spin_enter(&sc->sc_intr_lock); 1244 1245 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1246 goto done; 1247 1248 /* If we get an interrupt while polling, then just ignore it. */ 1249 if (sc->sc_bus.ub_usepolling) { 1250 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1251 /* for level triggered intrs, should do something to ack */ 1252 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1253 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1254 1255 goto done; 1256 } 1257 1258 ret = ohci_intr1(sc); 1259 1260 done: 1261 mutex_spin_exit(&sc->sc_intr_lock); 1262 return ret; 1263 } 1264 1265 Static int 1266 ohci_intr1(ohci_softc_t *sc) 1267 { 1268 uint32_t intrs, eintrs; 1269 1270 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1271 1272 /* In case the interrupt occurs before initialization has completed. */ 1273 if (sc == NULL || sc->sc_hcca == NULL) { 1274 #ifdef DIAGNOSTIC 1275 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1276 #endif 1277 return 0; 1278 } 1279 1280 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1281 1282 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1283 if (!intrs) 1284 return 0; 1285 1286 /* Acknowledge */ 1287 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); 1288 eintrs = intrs & sc->sc_eintrs; 1289 DPRINTFN(7, "sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1290 DPRINTFN(7, "intrs=%#jx(%#jx) eintrs=%#jx(%#jx)", 1291 intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), eintrs, 1292 sc->sc_eintrs); 1293 1294 if (!eintrs) { 1295 return 0; 1296 } 1297 1298 if (eintrs & OHCI_SO) { 1299 sc->sc_overrun_cnt++; 1300 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1301 printf("%s: %u scheduling overruns\n", 1302 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1303 sc->sc_overrun_cnt = 0; 1304 } 1305 /* XXX do what */ 1306 eintrs &= ~OHCI_SO; 1307 } 1308 if (eintrs & OHCI_WDH) { 1309 /* 1310 * We block the interrupt below, and reenable it later from 1311 * ohci_softintr(). 1312 */ 1313 usb_schedsoftintr(&sc->sc_bus); 1314 } 1315 if (eintrs & OHCI_RD) { 1316 /* 1 argument, but zero format strings */ 1317 DPRINTFN(5, "resume detect", (uintptr_t)sc, 0, 0, 0); 1318 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1319 /* XXX process resume detect */ 1320 } 1321 if (eintrs & OHCI_UE) { 1322 /* 1 argument, but zero format strings */ 1323 DPRINTFN(5, "unrecoverable error", (uintptr_t)sc, 0, 0, 0); 1324 printf("%s: unrecoverable error, controller halted\n", 1325 device_xname(sc->sc_dev)); 1326 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1327 /* XXX what else */ 1328 } 1329 if (eintrs & OHCI_RHSC) { 1330 /* 1331 * We block the interrupt below, and reenable it later from 1332 * a timeout. 1333 */ 1334 softint_schedule(sc->sc_rhsc_si); 1335 } 1336 1337 if (eintrs != 0) { 1338 /* Block unprocessed interrupts. */ 1339 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1340 sc->sc_eintrs &= ~eintrs; 1341 DPRINTF("sc %#jx blocking intrs 0x%jx", (uintptr_t)sc, 1342 eintrs, 0, 0); 1343 } 1344 1345 return 1; 1346 } 1347 1348 void 1349 ohci_rhsc_enable(void *v_sc) 1350 { 1351 ohci_softc_t *sc = v_sc; 1352 1353 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1354 DPRINTF("sc %#jx", (uintptr_t)sc, 0, 0, 0); 1355 mutex_spin_enter(&sc->sc_intr_lock); 1356 sc->sc_eintrs |= OHCI_RHSC; 1357 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1358 mutex_spin_exit(&sc->sc_intr_lock); 1359 } 1360 1361 #ifdef OHCI_DEBUG 1362 const char *ohci_cc_strs[] = { 1363 "NO_ERROR", 1364 "CRC", 1365 "BIT_STUFFING", 1366 "DATA_TOGGLE_MISMATCH", 1367 "STALL", 1368 "DEVICE_NOT_RESPONDING", 1369 "PID_CHECK_FAILURE", 1370 "UNEXPECTED_PID", 1371 "DATA_OVERRUN", 1372 "DATA_UNDERRUN", 1373 "BUFFER_OVERRUN", 1374 "BUFFER_UNDERRUN", 1375 "reserved", 1376 "reserved", 1377 "NOT_ACCESSED", 1378 "NOT_ACCESSED", 1379 }; 1380 #endif 1381 1382 void 1383 ohci_softintr(void *v) 1384 { 1385 struct usbd_bus *bus = v; 1386 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1387 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1388 ohci_soft_td_t *std, *sdone, *stdnext; 1389 struct usbd_xfer *xfer; 1390 struct ohci_pipe *opipe; 1391 int len, cc; 1392 int i, j, actlen, iframes, uedir; 1393 ohci_physaddr_t done; 1394 1395 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1396 1397 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1398 1399 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1400 sizeof(sc->sc_hcca->hcca_done_head), 1401 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1402 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1403 sc->sc_hcca->hcca_done_head = 0; 1404 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1405 sizeof(sc->sc_hcca->hcca_done_head), 1406 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1407 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1408 sc->sc_eintrs |= OHCI_WDH; 1409 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1410 1411 /* Reverse the done list. */ 1412 for (sdone = NULL, sidone = NULL; done != 0; ) { 1413 std = ohci_hash_find_td(sc, done); 1414 if (std != NULL) { 1415 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1416 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1417 std->dnext = sdone; 1418 done = O32TOH(std->td.td_nexttd); 1419 sdone = std; 1420 DPRINTFN(10, "add TD %#jx", (uintptr_t)std, 0, 0, 0); 1421 continue; 1422 } 1423 sitd = ohci_hash_find_itd(sc, done); 1424 if (sitd != NULL) { 1425 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1426 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1427 sitd->dnext = sidone; 1428 done = O32TOH(sitd->itd.itd_nextitd); 1429 sidone = sitd; 1430 DPRINTFN(5, "add ITD %#jx", (uintptr_t)sitd, 0, 0, 0); 1431 continue; 1432 } 1433 DPRINTFN(10, "addr %#jx not found", (uintptr_t)done, 0, 0, 0); 1434 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1435 (u_long)done); 1436 break; 1437 } 1438 1439 DPRINTFN(10, "sdone=%#jx sidone=%#jx", (uintptr_t)sdone, 1440 (uintptr_t)sidone, 0, 0); 1441 DPRINTFN(10, "--- TD dump start ---", 0, 0, 0, 0); 1442 #ifdef OHCI_DEBUG 1443 if (ohcidebug >= 10) { 1444 for (std = sdone; std; std = std->dnext) 1445 ohci_dump_td(sc, std); 1446 } 1447 #endif 1448 DPRINTFN(10, "--- TD dump end ---", 0, 0, 0, 0); 1449 1450 for (std = sdone; std; std = stdnext) { 1451 xfer = std->xfer; 1452 stdnext = std->dnext; 1453 DPRINTFN(10, "std=%#jx xfer=%#jx hcpriv=%#jx", (uintptr_t)std, 1454 (uintptr_t)xfer, (uintptr_t)(xfer ? xfer->ux_hcpriv : 0), 1455 0); 1456 if (xfer == NULL) { 1457 /* 1458 * xfer == NULL: There seems to be no xfer associated 1459 * with this TD. It is tailp that happened to end up on 1460 * the done queue. 1461 * Shouldn't happen, but some chips are broken(?). 1462 */ 1463 continue; 1464 } 1465 if (xfer->ux_status == USBD_CANCELLED || 1466 xfer->ux_status == USBD_TIMEOUT) { 1467 DPRINTF("cancel/timeout %#jx", (uintptr_t)xfer, 0, 0, 1468 0); 1469 /* Handled by abort routine. */ 1470 continue; 1471 } 1472 callout_stop(&xfer->ux_callout); 1473 1474 len = std->len; 1475 if (std->td.td_cbp != 0) 1476 len -= O32TOH(std->td.td_be) - 1477 O32TOH(std->td.td_cbp) + 1; 1478 DPRINTFN(10, "len=%jd, flags=0x%jx", len, std->flags, 0, 0); 1479 if (std->flags & OHCI_ADD_LEN) 1480 xfer->ux_actlen += len; 1481 1482 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1483 if (cc == OHCI_CC_NO_ERROR) { 1484 ohci_hash_rem_td(sc, std); 1485 if (std->flags & OHCI_CALL_DONE) { 1486 xfer->ux_status = USBD_NORMAL_COMPLETION; 1487 usb_transfer_complete(xfer); 1488 } 1489 } else { 1490 /* 1491 * Endpoint is halted. First unlink all the TDs 1492 * belonging to the failed transfer, and then restart 1493 * the endpoint. 1494 */ 1495 ohci_soft_td_t *p, *n; 1496 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1497 1498 DPRINTFN(10, "error cc=%jd", cc, 0, 0, 0); 1499 1500 /* remove xfer's TDs from the hash */ 1501 for (p = std; p->xfer == xfer; p = n) { 1502 n = p->nexttd; 1503 ohci_hash_rem_td(sc, p); 1504 } 1505 1506 ohci_soft_ed_t *sed = opipe->sed; 1507 1508 /* clear halt and TD chain */ 1509 sed->ed.ed_headp = HTOO32(p->physaddr); 1510 usb_syncmem(&sed->dma, 1511 sed->offs + offsetof(ohci_ed_t, ed_headp), 1512 sizeof(sed->ed.ed_headp), 1513 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1514 1515 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1516 1517 if (cc == OHCI_CC_DATA_UNDERRUN) 1518 xfer->ux_status = USBD_NORMAL_COMPLETION; 1519 else if (cc == OHCI_CC_STALL) 1520 xfer->ux_status = USBD_STALLED; 1521 else 1522 xfer->ux_status = USBD_IOERROR; 1523 usb_transfer_complete(xfer); 1524 } 1525 } 1526 DPRINTFN(10, "--- ITD dump start ---", 0, 0, 0, 0); 1527 #ifdef OHCI_DEBUG 1528 if (ohcidebug >= 10) { 1529 for (sitd = sidone; sitd; sitd = sitd->dnext) 1530 ohci_dump_itd(sc, sitd); 1531 } 1532 #endif 1533 DPRINTFN(10, "--- ITD dump end ---", 0, 0, 0, 0); 1534 1535 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1536 xfer = sitd->xfer; 1537 sitdnext = sitd->dnext; 1538 DPRINTFN(1, "sitd=%#jx xfer=%#jx hcpriv=%#jx", (uintptr_t)sitd, 1539 (uintptr_t)xfer, (uintptr_t)(xfer ? xfer->ux_hcpriv : 0), 1540 0); 1541 if (xfer == NULL) 1542 continue; 1543 if (xfer->ux_status == USBD_CANCELLED || 1544 xfer->ux_status == USBD_TIMEOUT) { 1545 DPRINTF("cancel/timeout %#jx", 1546 (uintptr_t)xfer, 0, 0, 0); 1547 /* Handled by abort routine. */ 1548 continue; 1549 } 1550 KASSERT(!sitd->isdone); 1551 #ifdef DIAGNOSTIC 1552 sitd->isdone = true; 1553 #endif 1554 if (sitd->flags & OHCI_CALL_DONE) { 1555 ohci_soft_itd_t *next; 1556 1557 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1558 opipe->isoc.inuse -= xfer->ux_nframes; 1559 uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc-> 1560 bEndpointAddress); 1561 xfer->ux_status = USBD_NORMAL_COMPLETION; 1562 actlen = 0; 1563 for (i = 0, sitd = xfer->ux_hcpriv;; 1564 sitd = next) { 1565 next = sitd->nextitd; 1566 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1567 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1568 xfer->ux_status = USBD_IOERROR; 1569 /* For input, update frlengths with actual */ 1570 /* XXX anything necessary for output? */ 1571 if (uedir == UE_DIR_IN && 1572 xfer->ux_status == USBD_NORMAL_COMPLETION) { 1573 iframes = OHCI_ITD_GET_FC(O32TOH( 1574 sitd->itd.itd_flags)); 1575 for (j = 0; j < iframes; i++, j++) { 1576 len = O16TOH(sitd-> 1577 itd.itd_offset[j]); 1578 if ((OHCI_ITD_PSW_GET_CC(len) & 1579 OHCI_CC_NOT_ACCESSED_MASK) 1580 == OHCI_CC_NOT_ACCESSED) 1581 len = 0; 1582 else 1583 len = OHCI_ITD_PSW_LENGTH(len); 1584 xfer->ux_frlengths[i] = len; 1585 actlen += len; 1586 } 1587 } 1588 if (sitd->flags & OHCI_CALL_DONE) 1589 break; 1590 ohci_hash_rem_itd(sc, sitd); 1591 1592 } 1593 ohci_hash_rem_itd(sc, sitd); 1594 if (uedir == UE_DIR_IN && 1595 xfer->ux_status == USBD_NORMAL_COMPLETION) 1596 xfer->ux_actlen = actlen; 1597 xfer->ux_hcpriv = NULL; 1598 1599 usb_transfer_complete(xfer); 1600 } 1601 } 1602 1603 if (sc->sc_softwake) { 1604 sc->sc_softwake = 0; 1605 cv_broadcast(&sc->sc_softwake_cv); 1606 } 1607 1608 DPRINTFN(10, "done", 0, 0, 0, 0); 1609 } 1610 1611 void 1612 ohci_device_ctrl_done(struct usbd_xfer *xfer) 1613 { 1614 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1615 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1616 int len = UGETW(xfer->ux_request.wLength); 1617 int isread = (xfer->ux_request.bmRequestType & UT_READ); 1618 1619 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1620 DPRINTFN(10, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 1621 1622 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1623 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 1624 1625 if (len) 1626 usb_syncmem(&xfer->ux_dmabuf, 0, len, 1627 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1628 usb_syncmem(&opipe->ctrl.reqdma, 0, 1629 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1630 } 1631 1632 void 1633 ohci_device_intr_done(struct usbd_xfer *xfer) 1634 { 1635 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1636 int isread = 1637 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1638 1639 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1640 DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, 1641 xfer->ux_actlen, 0, 0); 1642 1643 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1644 1645 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1646 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1647 } 1648 1649 void 1650 ohci_device_bulk_done(struct usbd_xfer *xfer) 1651 { 1652 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1653 1654 int isread = 1655 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1656 1657 KASSERT(mutex_owned(&sc->sc_lock)); 1658 1659 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1660 DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 1661 0, 0); 1662 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1663 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1664 } 1665 1666 Static void 1667 ohci_rhsc_softint(void *arg) 1668 { 1669 ohci_softc_t *sc = arg; 1670 1671 mutex_enter(&sc->sc_lock); 1672 1673 ohci_rhsc(sc, sc->sc_intrxfer); 1674 1675 /* Do not allow RHSC interrupts > 1 per second */ 1676 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1677 1678 mutex_exit(&sc->sc_lock); 1679 } 1680 1681 void 1682 ohci_rhsc(ohci_softc_t *sc, struct usbd_xfer *xfer) 1683 { 1684 u_char *p; 1685 int i, m; 1686 int hstatus __unused; 1687 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1688 1689 KASSERT(mutex_owned(&sc->sc_lock)); 1690 1691 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1692 DPRINTF("sc=%#jx xfer=%#jx hstatus=0x%08jx", (uintptr_t)sc, 1693 (uintptr_t)xfer, hstatus, 0); 1694 1695 if (xfer == NULL) { 1696 /* Just ignore the change. */ 1697 return; 1698 } 1699 1700 p = xfer->ux_buf; 1701 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 1702 memset(p, 0, xfer->ux_length); 1703 for (i = 1; i <= m; i++) { 1704 /* Pick out CHANGE bits from the status reg. */ 1705 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1706 p[i/8] |= 1 << (i%8); 1707 } 1708 DPRINTF("change=0x%02jx", *p, 0, 0, 0); 1709 xfer->ux_actlen = xfer->ux_length; 1710 xfer->ux_status = USBD_NORMAL_COMPLETION; 1711 1712 usb_transfer_complete(xfer); 1713 } 1714 1715 void 1716 ohci_root_intr_done(struct usbd_xfer *xfer) 1717 { 1718 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1719 1720 KASSERT(mutex_owned(&sc->sc_lock)); 1721 1722 KASSERT(sc->sc_intrxfer == xfer); 1723 sc->sc_intrxfer = NULL; 1724 } 1725 1726 void 1727 ohci_poll(struct usbd_bus *bus) 1728 { 1729 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1730 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1731 1732 #ifdef OHCI_DEBUG 1733 static int last; 1734 int new; 1735 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1736 if (new != last) { 1737 DPRINTFN(10, "intrs=0x%04jx", new, 0, 0, 0); 1738 last = new; 1739 } 1740 #endif 1741 sc->sc_eintrs |= OHCI_WDH; 1742 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1743 mutex_spin_enter(&sc->sc_intr_lock); 1744 ohci_intr1(sc); 1745 mutex_spin_exit(&sc->sc_intr_lock); 1746 } 1747 } 1748 1749 /* 1750 * Add an ED to the schedule. Called with USB lock held. 1751 */ 1752 Static void 1753 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1754 { 1755 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1756 DPRINTFN(8, "sed=%#jx head=%#jx", (uintptr_t)sed, (uintptr_t)head, 0, 1757 0); 1758 1759 KASSERT(mutex_owned(&sc->sc_lock)); 1760 1761 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1762 sizeof(head->ed.ed_nexted), 1763 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1764 sed->next = head->next; 1765 sed->ed.ed_nexted = head->ed.ed_nexted; 1766 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1767 sizeof(sed->ed.ed_nexted), 1768 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1769 head->next = sed; 1770 head->ed.ed_nexted = HTOO32(sed->physaddr); 1771 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1772 sizeof(head->ed.ed_nexted), 1773 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1774 } 1775 1776 /* 1777 * Remove an ED from the schedule. Called with USB lock held. 1778 */ 1779 Static void 1780 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1781 { 1782 ohci_soft_ed_t *p; 1783 1784 KASSERT(mutex_owned(&sc->sc_lock)); 1785 1786 /* XXX */ 1787 for (p = head; p != NULL && p->next != sed; p = p->next) 1788 ; 1789 KASSERT(p != NULL); 1790 1791 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1792 sizeof(sed->ed.ed_nexted), 1793 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1794 p->next = sed->next; 1795 p->ed.ed_nexted = sed->ed.ed_nexted; 1796 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1797 sizeof(p->ed.ed_nexted), 1798 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1799 } 1800 1801 /* 1802 * When a transfer is completed the TD is added to the done queue by 1803 * the host controller. This queue is the processed by software. 1804 * Unfortunately the queue contains the physical address of the TD 1805 * and we have no simple way to translate this back to a kernel address. 1806 * To make the translation possible (and fast) we use a hash table of 1807 * TDs currently in the schedule. The physical address is used as the 1808 * hash value. 1809 */ 1810 1811 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1812 /* Called with USB lock held. */ 1813 void 1814 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1815 { 1816 int h = HASH(std->physaddr); 1817 1818 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1819 1820 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1821 } 1822 1823 /* Called with USB lock held. */ 1824 void 1825 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1826 { 1827 1828 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1829 1830 LIST_REMOVE(std, hnext); 1831 } 1832 1833 ohci_soft_td_t * 1834 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1835 { 1836 int h = HASH(a); 1837 ohci_soft_td_t *std; 1838 1839 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1840 std != NULL; 1841 std = LIST_NEXT(std, hnext)) 1842 if (std->physaddr == a) 1843 return std; 1844 return NULL; 1845 } 1846 1847 /* Called with USB lock held. */ 1848 void 1849 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1850 { 1851 int h = HASH(sitd->physaddr); 1852 1853 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1854 1855 KASSERT(mutex_owned(&sc->sc_lock)); 1856 1857 DPRINTFN(10, "sitd=%#jx physaddr=0x%08jx", 1858 (uintptr_t)sitd, (u_long)sitd->physaddr, 0, 0); 1859 1860 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1861 } 1862 1863 /* Called with USB lock held. */ 1864 void 1865 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1866 { 1867 1868 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1869 1870 KASSERT(mutex_owned(&sc->sc_lock)); 1871 1872 DPRINTFN(10, "sitd=%#jx physaddr=0x%08jx", (uintptr_t)sitd, 1873 sitd->physaddr, 0, 0); 1874 1875 LIST_REMOVE(sitd, hnext); 1876 } 1877 1878 ohci_soft_itd_t * 1879 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1880 { 1881 int h = HASH(a); 1882 ohci_soft_itd_t *sitd; 1883 1884 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1885 sitd != NULL; 1886 sitd = LIST_NEXT(sitd, hnext)) 1887 if (sitd->physaddr == a) 1888 return sitd; 1889 return NULL; 1890 } 1891 1892 void 1893 ohci_timeout(void *addr) 1894 { 1895 struct usbd_xfer *xfer = addr; 1896 struct ohci_xfer *oxfer = OHCI_XFER2OXFER(xfer); 1897 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1898 1899 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1900 DPRINTF("oxfer=%#jx", (uintptr_t)oxfer, 0, 0, 0); 1901 1902 if (sc->sc_dying) { 1903 mutex_enter(&sc->sc_lock); 1904 ohci_abort_xfer(xfer, USBD_TIMEOUT); 1905 mutex_exit(&sc->sc_lock); 1906 return; 1907 } 1908 1909 /* Execute the abort in a process context. */ 1910 usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr, 1911 USB_TASKQ_MPSAFE); 1912 usb_add_task(xfer->ux_pipe->up_dev, &oxfer->abort_task, 1913 USB_TASKQ_HC); 1914 } 1915 1916 void 1917 ohci_timeout_task(void *addr) 1918 { 1919 struct usbd_xfer *xfer = addr; 1920 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1921 1922 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1923 1924 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 1925 1926 mutex_enter(&sc->sc_lock); 1927 ohci_abort_xfer(xfer, USBD_TIMEOUT); 1928 mutex_exit(&sc->sc_lock); 1929 } 1930 1931 #ifdef OHCI_DEBUG 1932 void 1933 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 1934 { 1935 for (; std; std = std->nexttd) { 1936 ohci_dump_td(sc, std); 1937 KASSERTMSG(std->nexttd == NULL || std != std->nexttd, 1938 "std %p next %p", std, std->nexttd); 1939 } 1940 } 1941 1942 void 1943 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1944 { 1945 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1946 1947 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1948 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1949 1950 uint32_t flags = O32TOH(std->td.td_flags); 1951 DPRINTF("TD(%#jx) at 0x%08jx:", (uintptr_t)std, std->physaddr, 0, 0); 1952 DPRINTF(" round=%jd DP=%jx DI=%jx T=%jx", 1953 !!(flags & OHCI_TD_R), 1954 __SHIFTOUT(flags, OHCI_TD_DP_MASK), 1955 OHCI_TD_GET_DI(flags), 1956 __SHIFTOUT(flags, OHCI_TD_TOGGLE_MASK)); 1957 DPRINTF(" EC=%jd CC=%jd", OHCI_TD_GET_EC(flags), 1958 OHCI_TD_GET_CC(flags), 0, 0); 1959 DPRINTF(" td_cbp=0x%08jx td_nexttd=0x%08jx td_be=0x%08jx", 1960 (u_long)O32TOH(std->td.td_cbp), 1961 (u_long)O32TOH(std->td.td_nexttd), 1962 (u_long)O32TOH(std->td.td_be), 0); 1963 } 1964 1965 void 1966 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1967 { 1968 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1969 1970 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1971 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1972 1973 uint32_t flags = O32TOH(sitd->itd.itd_flags); 1974 DPRINTF("ITD(%#jx) at 0x%08jx", (uintptr_t)sitd, sitd->physaddr, 0, 0); 1975 DPRINTF(" sf=%jd di=%jd fc=%jd cc=%jd", 1976 OHCI_ITD_GET_SF(flags), OHCI_ITD_GET_DI(flags), 1977 OHCI_ITD_GET_FC(flags), OHCI_ITD_GET_CC(flags)); 1978 DPRINTF(" bp0=0x%08jx next=0x%08jx be=0x%08jx", 1979 O32TOH(sitd->itd.itd_bp0), 1980 O32TOH(sitd->itd.itd_nextitd), 1981 O32TOH(sitd->itd.itd_be), 0); 1982 CTASSERT(OHCI_ITD_NOFFSET == 8); 1983 DPRINTF(" offs[0] = 0x%04jx offs[1] = 0x%04jx " 1984 "offs[2] = 0x%04jx offs[3] = 0x%04jx", 1985 O16TOH(sitd->itd.itd_offset[0]), 1986 O16TOH(sitd->itd.itd_offset[1]), 1987 O16TOH(sitd->itd.itd_offset[2]), 1988 O16TOH(sitd->itd.itd_offset[3])); 1989 DPRINTF(" offs[4] = 0x%04jx offs[5] = 0x%04jx " 1990 "offs[6] = 0x%04jx offs[7] = 0x%04jx", 1991 O16TOH(sitd->itd.itd_offset[4]), 1992 O16TOH(sitd->itd.itd_offset[5]), 1993 O16TOH(sitd->itd.itd_offset[6]), 1994 O16TOH(sitd->itd.itd_offset[7])); 1995 } 1996 1997 void 1998 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1999 { 2000 for (; sitd; sitd = sitd->nextitd) 2001 ohci_dump_itd(sc, sitd); 2002 } 2003 2004 void 2005 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2006 { 2007 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2008 2009 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2010 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2011 2012 uint32_t flags = O32TOH(sed->ed.ed_flags); 2013 DPRINTF("ED(%#jx) at 0x%08jx:", (uintptr_t)sed, sed->physaddr, 0, 0); 2014 DPRINTF(" addr=%jd endpt=%jd maxp=%jd", 2015 OHCI_ED_GET_FA(flags), 2016 OHCI_ED_GET_EN(flags), 2017 OHCI_ED_GET_MAXP(flags), 2018 0); 2019 DPRINTF(" dir=%jd speed=%jd skip=%jd iso=%jd", 2020 __SHIFTOUT(flags, OHCI_ED_DIR_MASK), 2021 !!(flags & OHCI_ED_SPEED), 2022 !!(flags & OHCI_ED_SKIP), 2023 !!(flags & OHCI_ED_FORMAT_ISO)); 2024 DPRINTF(" tailp=0x%08jx", (u_long)O32TOH(sed->ed.ed_tailp), 2025 0, 0, 0); 2026 DPRINTF(" headp=0x%08jx nexted=0x%08jx halted=%jd carry=%jd", 2027 O32TOH(sed->ed.ed_headp), O32TOH(sed->ed.ed_nexted), 2028 !!(O32TOH(sed->ed.ed_headp) & OHCI_HALTED), 2029 !!(O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 2030 } 2031 #endif 2032 2033 usbd_status 2034 ohci_open(struct usbd_pipe *pipe) 2035 { 2036 struct usbd_device *dev = pipe->up_dev; 2037 struct usbd_bus *bus = dev->ud_bus; 2038 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2039 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 2040 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2041 uint8_t addr = dev->ud_addr; 2042 uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2043 ohci_soft_ed_t *sed; 2044 ohci_soft_td_t *std; 2045 ohci_soft_itd_t *sitd; 2046 ohci_physaddr_t tdphys; 2047 uint32_t fmt; 2048 usbd_status err = USBD_NOMEM; 2049 int ival; 2050 2051 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2052 DPRINTFN(1, "pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, 2053 addr, ed->bEndpointAddress, bus->ub_rhaddr); 2054 2055 if (sc->sc_dying) { 2056 return USBD_IOERROR; 2057 } 2058 2059 std = NULL; 2060 sed = NULL; 2061 2062 if (addr == bus->ub_rhaddr) { 2063 switch (ed->bEndpointAddress) { 2064 case USB_CONTROL_ENDPOINT: 2065 pipe->up_methods = &roothub_ctrl_methods; 2066 break; 2067 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 2068 pipe->up_methods = &ohci_root_intr_methods; 2069 break; 2070 default: 2071 err = USBD_INVAL; 2072 goto bad; 2073 } 2074 } else { 2075 sed = ohci_alloc_sed(sc); 2076 if (sed == NULL) 2077 goto bad; 2078 opipe->sed = sed; 2079 if (xfertype == UE_ISOCHRONOUS) { 2080 sitd = ohci_alloc_sitd(sc); 2081 if (sitd == NULL) 2082 goto bad; 2083 2084 opipe->tail.itd = sitd; 2085 tdphys = sitd->physaddr; 2086 fmt = OHCI_ED_FORMAT_ISO; 2087 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2088 fmt |= OHCI_ED_DIR_IN; 2089 else 2090 fmt |= OHCI_ED_DIR_OUT; 2091 } else { 2092 std = ohci_alloc_std(sc); 2093 if (std == NULL) 2094 goto bad; 2095 2096 opipe->tail.td = std; 2097 tdphys = std->physaddr; 2098 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2099 } 2100 sed->ed.ed_flags = HTOO32( 2101 OHCI_ED_SET_FA(addr) | 2102 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2103 (dev->ud_speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2104 fmt | 2105 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2106 sed->ed.ed_headp = HTOO32(tdphys | 2107 (pipe->up_endpoint->ue_toggle ? OHCI_TOGGLECARRY : 0)); 2108 sed->ed.ed_tailp = HTOO32(tdphys); 2109 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2110 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2111 2112 switch (xfertype) { 2113 case UE_CONTROL: 2114 pipe->up_methods = &ohci_device_ctrl_methods; 2115 err = usb_allocmem(&sc->sc_bus, 2116 sizeof(usb_device_request_t), 2117 0, &opipe->ctrl.reqdma); 2118 if (err) 2119 goto bad; 2120 mutex_enter(&sc->sc_lock); 2121 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2122 mutex_exit(&sc->sc_lock); 2123 break; 2124 case UE_INTERRUPT: 2125 pipe->up_methods = &ohci_device_intr_methods; 2126 ival = pipe->up_interval; 2127 if (ival == USBD_DEFAULT_INTERVAL) 2128 ival = ed->bInterval; 2129 err = ohci_device_setintr(sc, opipe, ival); 2130 if (err) 2131 goto bad; 2132 break; 2133 case UE_ISOCHRONOUS: 2134 pipe->up_serialise = false; 2135 pipe->up_methods = &ohci_device_isoc_methods; 2136 return ohci_setup_isoc(pipe); 2137 case UE_BULK: 2138 pipe->up_methods = &ohci_device_bulk_methods; 2139 mutex_enter(&sc->sc_lock); 2140 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2141 mutex_exit(&sc->sc_lock); 2142 break; 2143 } 2144 } 2145 2146 return USBD_NORMAL_COMPLETION; 2147 2148 bad: 2149 if (std != NULL) { 2150 ohci_free_std(sc, std); 2151 } 2152 if (sed != NULL) 2153 ohci_free_sed(sc, sed); 2154 return err; 2155 2156 } 2157 2158 /* 2159 * Close a reqular pipe. 2160 * Assumes that there are no pending transactions. 2161 */ 2162 void 2163 ohci_close_pipe(struct usbd_pipe *pipe, ohci_soft_ed_t *head) 2164 { 2165 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2166 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2167 ohci_soft_ed_t *sed = opipe->sed; 2168 2169 KASSERT(mutex_owned(&sc->sc_lock)); 2170 2171 #ifdef DIAGNOSTIC 2172 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2173 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2174 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2175 ohci_soft_td_t *std; 2176 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2177 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2178 "tl=0x%x pipe=%p, std=%p\n", sed, 2179 (int)O32TOH(sed->ed.ed_headp), 2180 (int)O32TOH(sed->ed.ed_tailp), 2181 pipe, std); 2182 #ifdef OHCI_DEBUG 2183 usbd_dump_pipe(&opipe->pipe); 2184 ohci_dump_ed(sc, sed); 2185 if (std) 2186 ohci_dump_td(sc, std); 2187 #endif 2188 usb_delay_ms(&sc->sc_bus, 2); 2189 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2190 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2191 printf("ohci_close_pipe: pipe still not empty\n"); 2192 } 2193 #endif 2194 ohci_rem_ed(sc, sed, head); 2195 /* Make sure the host controller is not touching this ED */ 2196 usb_delay_ms(&sc->sc_bus, 1); 2197 pipe->up_endpoint->ue_toggle = 2198 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2199 ohci_free_sed_locked(sc, opipe->sed); 2200 } 2201 2202 /* 2203 * Abort a device request. 2204 * If this routine is called at splusb() it guarantees that the request 2205 * will be removed from the hardware scheduling and that the callback 2206 * for it will be called with USBD_CANCELLED status. 2207 * It's impossible to guarantee that the requested transfer will not 2208 * have happened since the hardware runs concurrently. 2209 * If the transaction has already happened we rely on the ordinary 2210 * interrupt processing to process it. 2211 * XXX This is most probably wrong. 2212 * XXXMRG this doesn't make sense anymore. 2213 */ 2214 void 2215 ohci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2216 { 2217 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2218 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2219 ohci_soft_ed_t *sed = opipe->sed; 2220 ohci_soft_td_t *p, *n; 2221 ohci_physaddr_t headp; 2222 int hit; 2223 int wake; 2224 2225 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2226 DPRINTF("xfer=%#jx pipe=%#jx sed=%#jx", (uintptr_t)xfer, 2227 (uintptr_t)opipe, (uintptr_t)sed, 0); 2228 2229 KASSERT(mutex_owned(&sc->sc_lock)); 2230 ASSERT_SLEEPABLE(); 2231 2232 if (sc->sc_dying) { 2233 /* If we're dying, just do the software part. */ 2234 xfer->ux_status = status; /* make software ignore it */ 2235 callout_halt(&xfer->ux_callout, &sc->sc_lock); 2236 usb_transfer_complete(xfer); 2237 return; 2238 } 2239 2240 /* 2241 * If an abort is already in progress then just wait for it to 2242 * complete and return. 2243 */ 2244 if (xfer->ux_hcflags & UXFER_ABORTING) { 2245 DPRINTFN(2, "already aborting", 0, 0, 0, 0); 2246 #ifdef DIAGNOSTIC 2247 if (status == USBD_TIMEOUT) 2248 printf("%s: TIMEOUT while aborting\n", __func__); 2249 #endif 2250 /* Override the status which might be USBD_TIMEOUT. */ 2251 xfer->ux_status = status; 2252 DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0); 2253 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2254 while (xfer->ux_hcflags & UXFER_ABORTING) 2255 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2256 goto done; 2257 } 2258 xfer->ux_hcflags |= UXFER_ABORTING; 2259 2260 /* 2261 * Step 1: Make interrupt routine and hardware ignore xfer. 2262 */ 2263 xfer->ux_status = status; /* make software ignore it */ 2264 callout_stop(&xfer->ux_callout); 2265 DPRINTFN(1, "stop ed=%#jx", (uintptr_t)sed, 0, 0, 0); 2266 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2267 sizeof(sed->ed.ed_flags), 2268 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2269 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2270 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2271 sizeof(sed->ed.ed_flags), 2272 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2273 2274 /* 2275 * Step 2: Wait until we know hardware has finished any possible 2276 * use of the xfer. Also make sure the soft interrupt routine 2277 * has run. 2278 */ 2279 /* Hardware finishes in 1ms */ 2280 usb_delay_ms_locked(opipe->pipe.up_dev->ud_bus, 20, &sc->sc_lock); 2281 sc->sc_softwake = 1; 2282 usb_schedsoftintr(&sc->sc_bus); 2283 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2284 2285 /* 2286 * Step 3: Remove any vestiges of the xfer from the hardware. 2287 * The complication here is that the hardware may have executed 2288 * beyond the xfer we're trying to abort. So as we're scanning 2289 * the TDs of this xfer we check if the hardware points to 2290 * any of them. 2291 */ 2292 p = xfer->ux_hcpriv; 2293 KASSERT(p); 2294 2295 #ifdef OHCI_DEBUG 2296 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2297 2298 if (ohcidebug >= 2) { 2299 DPRINTF("sed:", 0, 0, 0, 0); 2300 ohci_dump_ed(sc, sed); 2301 ohci_dump_tds(sc, p); 2302 } 2303 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2304 #endif 2305 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2306 hit = 0; 2307 for (; p->xfer == xfer; p = n) { 2308 hit |= headp == p->physaddr; 2309 n = p->nexttd; 2310 ohci_hash_rem_td(sc, p); 2311 } 2312 /* Zap headp register if hardware pointed inside the xfer. */ 2313 if (hit) { 2314 DPRINTFN(1, "set hd=0x%08jx, tl=0x%08jx", (int)p->physaddr, 2315 (int)O32TOH(sed->ed.ed_tailp), 0, 0); 2316 sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */ 2317 usb_syncmem(&sed->dma, 2318 sed->offs + offsetof(ohci_ed_t, ed_headp), 2319 sizeof(sed->ed.ed_headp), 2320 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2321 } else { 2322 DPRINTFN(1, "no hit", 0, 0, 0, 0); 2323 } 2324 2325 /* 2326 * Step 4: Turn on hardware again. 2327 */ 2328 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2329 sizeof(sed->ed.ed_flags), 2330 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2331 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2332 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2333 sizeof(sed->ed.ed_flags), 2334 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2335 2336 /* 2337 * Step 5: Execute callback. 2338 */ 2339 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2340 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2341 usb_transfer_complete(xfer); 2342 if (wake) 2343 cv_broadcast(&xfer->ux_hccv); 2344 2345 done: 2346 KASSERT(mutex_owned(&sc->sc_lock)); 2347 } 2348 2349 /* 2350 * Data structures and routines to emulate the root hub. 2351 */ 2352 Static int 2353 ohci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2354 void *buf, int buflen) 2355 { 2356 ohci_softc_t *sc = OHCI_BUS2SC(bus); 2357 usb_port_status_t ps; 2358 uint16_t len, value, index; 2359 int l, totlen = 0; 2360 int port, i; 2361 uint32_t v; 2362 2363 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2364 2365 if (sc->sc_dying) 2366 return -1; 2367 2368 DPRINTFN(4, "type=0x%02jx request=%02jx", req->bmRequestType, 2369 req->bRequest, 0, 0); 2370 2371 len = UGETW(req->wLength); 2372 value = UGETW(req->wValue); 2373 index = UGETW(req->wIndex); 2374 2375 #define C(x,y) ((x) | ((y) << 8)) 2376 switch (C(req->bRequest, req->bmRequestType)) { 2377 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2378 DPRINTFN(8, "wValue=0x%04jx", value, 0, 0, 0); 2379 if (len == 0) 2380 break; 2381 switch (value) { 2382 case C(0, UDESC_DEVICE): { 2383 usb_device_descriptor_t devd; 2384 2385 totlen = min(buflen, sizeof(devd)); 2386 memcpy(&devd, buf, totlen); 2387 USETW(devd.idVendor, sc->sc_id_vendor); 2388 memcpy(buf, &devd, totlen); 2389 break; 2390 } 2391 case C(1, UDESC_STRING): 2392 #define sd ((usb_string_descriptor_t *)buf) 2393 /* Vendor */ 2394 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2395 break; 2396 case C(2, UDESC_STRING): 2397 /* Product */ 2398 totlen = usb_makestrdesc(sd, len, "OHCI root hub"); 2399 break; 2400 #undef sd 2401 default: 2402 /* default from usbroothub */ 2403 return buflen; 2404 } 2405 break; 2406 2407 /* Hub requests */ 2408 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2409 break; 2410 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2411 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", 2412 index, value, 0, 0); 2413 if (index < 1 || index > sc->sc_noport) { 2414 return -1; 2415 } 2416 port = OHCI_RH_PORT_STATUS(index); 2417 switch(value) { 2418 case UHF_PORT_ENABLE: 2419 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2420 break; 2421 case UHF_PORT_SUSPEND: 2422 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2423 break; 2424 case UHF_PORT_POWER: 2425 /* Yes, writing to the LOW_SPEED bit clears power. */ 2426 OWRITE4(sc, port, UPS_LOW_SPEED); 2427 break; 2428 case UHF_C_PORT_CONNECTION: 2429 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2430 break; 2431 case UHF_C_PORT_ENABLE: 2432 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2433 break; 2434 case UHF_C_PORT_SUSPEND: 2435 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2436 break; 2437 case UHF_C_PORT_OVER_CURRENT: 2438 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2439 break; 2440 case UHF_C_PORT_RESET: 2441 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2442 break; 2443 default: 2444 return -1; 2445 } 2446 switch(value) { 2447 case UHF_C_PORT_CONNECTION: 2448 case UHF_C_PORT_ENABLE: 2449 case UHF_C_PORT_SUSPEND: 2450 case UHF_C_PORT_OVER_CURRENT: 2451 case UHF_C_PORT_RESET: 2452 /* Enable RHSC interrupt if condition is cleared. */ 2453 if ((OREAD4(sc, port) >> 16) == 0) 2454 ohci_rhsc_enable(sc); 2455 break; 2456 default: 2457 break; 2458 } 2459 break; 2460 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2461 if (len == 0) 2462 break; 2463 if ((value & 0xff) != 0) { 2464 return -1; 2465 } 2466 usb_hub_descriptor_t hubd; 2467 2468 totlen = min(buflen, sizeof(hubd)); 2469 memcpy(&hubd, buf, totlen); 2470 2471 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2472 hubd.bNbrPorts = sc->sc_noport; 2473 USETW(hubd.wHubCharacteristics, 2474 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2475 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2476 /* XXX overcurrent */ 2477 ); 2478 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2479 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2480 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2481 hubd.DeviceRemovable[i++] = (uint8_t)v; 2482 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2483 totlen = min(totlen, hubd.bDescLength); 2484 memcpy(buf, &hubd, totlen); 2485 break; 2486 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2487 if (len != 4) { 2488 return -1; 2489 } 2490 memset(buf, 0, len); /* ? XXX */ 2491 totlen = len; 2492 break; 2493 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2494 DPRINTFN(8, "get port status i=%jd", index, 0, 0, 0); 2495 if (index < 1 || index > sc->sc_noport) { 2496 return -1; 2497 } 2498 if (len != 4) { 2499 return -1; 2500 } 2501 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2502 DPRINTFN(8, "port status=0x%04jx", v, 0, 0, 0); 2503 USETW(ps.wPortStatus, v); 2504 USETW(ps.wPortChange, v >> 16); 2505 totlen = min(len, sizeof(ps)); 2506 memcpy(buf, &ps, totlen); 2507 break; 2508 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2509 return -1; 2510 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2511 break; 2512 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2513 if (index < 1 || index > sc->sc_noport) { 2514 return -1; 2515 } 2516 port = OHCI_RH_PORT_STATUS(index); 2517 switch(value) { 2518 case UHF_PORT_ENABLE: 2519 OWRITE4(sc, port, UPS_PORT_ENABLED); 2520 break; 2521 case UHF_PORT_SUSPEND: 2522 OWRITE4(sc, port, UPS_SUSPEND); 2523 break; 2524 case UHF_PORT_RESET: 2525 DPRINTFN(5, "reset port %jd", index, 0, 0, 0); 2526 OWRITE4(sc, port, UPS_RESET); 2527 for (i = 0; i < 5; i++) { 2528 usb_delay_ms(&sc->sc_bus, 2529 USB_PORT_ROOT_RESET_DELAY); 2530 if (sc->sc_dying) { 2531 return -1; 2532 } 2533 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2534 break; 2535 } 2536 DPRINTFN(8, "port %jd reset, status = 0x%04jx", index, 2537 OREAD4(sc, port), 0, 0); 2538 break; 2539 case UHF_PORT_POWER: 2540 DPRINTFN(2, "set port power %jd", index, 0, 0, 0); 2541 OWRITE4(sc, port, UPS_PORT_POWER); 2542 break; 2543 default: 2544 return -1; 2545 } 2546 break; 2547 default: 2548 /* default from usbroothub */ 2549 return buflen; 2550 } 2551 2552 return totlen; 2553 } 2554 2555 Static usbd_status 2556 ohci_root_intr_transfer(struct usbd_xfer *xfer) 2557 { 2558 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2559 usbd_status err; 2560 2561 /* Insert last in queue. */ 2562 mutex_enter(&sc->sc_lock); 2563 err = usb_insert_transfer(xfer); 2564 mutex_exit(&sc->sc_lock); 2565 if (err) 2566 return err; 2567 2568 /* Pipe isn't running, start first */ 2569 return ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2570 } 2571 2572 Static usbd_status 2573 ohci_root_intr_start(struct usbd_xfer *xfer) 2574 { 2575 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2576 2577 if (sc->sc_dying) 2578 return USBD_IOERROR; 2579 2580 mutex_enter(&sc->sc_lock); 2581 KASSERT(sc->sc_intrxfer == NULL); 2582 sc->sc_intrxfer = xfer; 2583 mutex_exit(&sc->sc_lock); 2584 2585 return USBD_IN_PROGRESS; 2586 } 2587 2588 /* Abort a root interrupt request. */ 2589 Static void 2590 ohci_root_intr_abort(struct usbd_xfer *xfer) 2591 { 2592 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2593 2594 KASSERT(mutex_owned(&sc->sc_lock)); 2595 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2596 2597 sc->sc_intrxfer = NULL; 2598 2599 xfer->ux_status = USBD_CANCELLED; 2600 usb_transfer_complete(xfer); 2601 } 2602 2603 /* Close the root pipe. */ 2604 Static void 2605 ohci_root_intr_close(struct usbd_pipe *pipe) 2606 { 2607 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2608 2609 KASSERT(mutex_owned(&sc->sc_lock)); 2610 2611 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2612 2613 sc->sc_intrxfer = NULL; 2614 } 2615 2616 /************************/ 2617 2618 int 2619 ohci_device_ctrl_init(struct usbd_xfer *xfer) 2620 { 2621 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2622 usb_device_request_t *req = &xfer->ux_request; 2623 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2624 ohci_soft_td_t *stat, *setup; 2625 int isread = req->bmRequestType & UT_READ; 2626 int len = xfer->ux_bufsize; 2627 int err = ENOMEM; 2628 2629 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2630 2631 setup = ohci_alloc_std(sc); 2632 if (setup == NULL) { 2633 goto bad1; 2634 } 2635 stat = ohci_alloc_std(sc); 2636 if (stat == NULL) { 2637 goto bad2; 2638 } 2639 2640 ox->ox_setup = setup; 2641 ox->ox_stat = stat; 2642 ox->ox_nstd = 0; 2643 2644 /* Set up data transaction */ 2645 if (len != 0) { 2646 err = ohci_alloc_std_chain(sc, xfer, len, isread); 2647 if (err) { 2648 goto bad3; 2649 } 2650 } 2651 return 0; 2652 2653 bad3: 2654 ohci_free_std(sc, stat); 2655 bad2: 2656 ohci_free_std(sc, setup); 2657 bad1: 2658 return err; 2659 } 2660 2661 void 2662 ohci_device_ctrl_fini(struct usbd_xfer *xfer) 2663 { 2664 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2665 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2666 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2667 2668 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2669 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 2670 2671 mutex_enter(&sc->sc_lock); 2672 if (ox->ox_setup != opipe->tail.td) { 2673 ohci_free_std_locked(sc, ox->ox_setup); 2674 } 2675 for (size_t i = 0; i < ox->ox_nstd; i++) { 2676 ohci_soft_td_t *std = ox->ox_stds[i]; 2677 if (std == NULL) 2678 break; 2679 ohci_free_std_locked(sc, std); 2680 } 2681 ohci_free_std_locked(sc, ox->ox_stat); 2682 mutex_exit(&sc->sc_lock); 2683 2684 if (ox->ox_nstd) { 2685 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 2686 kmem_free(ox->ox_stds, sz); 2687 } 2688 } 2689 2690 Static usbd_status 2691 ohci_device_ctrl_transfer(struct usbd_xfer *xfer) 2692 { 2693 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2694 usbd_status err; 2695 2696 /* Insert last in queue. */ 2697 mutex_enter(&sc->sc_lock); 2698 err = usb_insert_transfer(xfer); 2699 mutex_exit(&sc->sc_lock); 2700 if (err) 2701 return err; 2702 2703 /* Pipe isn't running, start first */ 2704 return ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2705 } 2706 2707 Static usbd_status 2708 ohci_device_ctrl_start(struct usbd_xfer *xfer) 2709 { 2710 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2711 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2712 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2713 usb_device_request_t *req = &xfer->ux_request; 2714 struct usbd_device *dev __diagused = opipe->pipe.up_dev; 2715 ohci_soft_td_t *setup, *stat, *next, *tail; 2716 ohci_soft_ed_t *sed; 2717 int isread; 2718 int len; 2719 2720 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2721 2722 if (sc->sc_dying) 2723 return USBD_IOERROR; 2724 2725 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2726 2727 isread = req->bmRequestType & UT_READ; 2728 len = UGETW(req->wLength); 2729 2730 DPRINTF("xfer=%#jx len=%jd, addr=%jd, endpt=%jd", (uintptr_t)xfer, len, 2731 dev->ud_addr, opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress); 2732 DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx", 2733 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2734 UGETW(req->wIndex)); 2735 2736 /* Need to take lock here for pipe->tail.td */ 2737 mutex_enter(&sc->sc_lock); 2738 2739 /* 2740 * Use the pipe "tail" TD as our first and loan our first TD to the 2741 * next transfer 2742 */ 2743 setup = opipe->tail.td; 2744 opipe->tail.td = ox->ox_setup; 2745 ox->ox_setup = setup; 2746 2747 stat = ox->ox_stat; 2748 2749 /* point at sentinel */ 2750 tail = opipe->tail.td; 2751 sed = opipe->sed; 2752 2753 KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->ud_addr, 2754 "address ED %d pipe %d\n", 2755 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->ud_addr); 2756 KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) == 2757 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 2758 "MPL ED %d pipe %d\n", 2759 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), 2760 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 2761 2762 /* next will point to data if len != 0 */ 2763 next = stat; 2764 2765 /* Set up data transaction */ 2766 if (len != 0) { 2767 ohci_soft_td_t *std; 2768 ohci_soft_td_t *end; 2769 2770 next = ox->ox_stds[0]; 2771 ohci_reset_std_chain(sc, xfer, len, isread, next, &end); 2772 2773 end->td.td_nexttd = HTOO32(stat->physaddr); 2774 end->nexttd = stat; 2775 2776 usb_syncmem(&end->dma, end->offs, sizeof(end->td), 2777 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2778 2779 usb_syncmem(&xfer->ux_dmabuf, 0, len, 2780 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2781 std = ox->ox_stds[0]; 2782 /* Start toggle at 1 and then use the carried toggle. */ 2783 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 2784 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 2785 usb_syncmem(&std->dma, 2786 std->offs + offsetof(ohci_td_t, td_flags), 2787 sizeof(std->td.td_flags), 2788 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2789 } 2790 2791 DPRINTFN(8, "setup %#jx data %#jx stat %#jx tail %#jx", 2792 (uintptr_t)setup, 2793 (uintptr_t)(len != 0 ? ox->ox_stds[0] : NULL), (uintptr_t)stat, 2794 (uintptr_t)tail); 2795 KASSERT(opipe->tail.td == tail); 2796 2797 memcpy(KERNADDR(&opipe->ctrl.reqdma, 0), req, sizeof(*req)); 2798 usb_syncmem(&opipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2799 2800 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 2801 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 2802 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->ctrl.reqdma, 0)); 2803 setup->td.td_nexttd = HTOO32(next->physaddr); 2804 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof(*req) - 1); 2805 setup->nexttd = next; 2806 setup->len = 0; 2807 setup->xfer = xfer; 2808 setup->flags = 0; 2809 ohci_hash_add_td(sc, setup); 2810 2811 xfer->ux_hcpriv = setup; 2812 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2813 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2814 2815 stat->td.td_flags = HTOO32( 2816 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 2817 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 2818 stat->td.td_cbp = 0; 2819 stat->td.td_nexttd = HTOO32(tail->physaddr); 2820 stat->td.td_be = 0; 2821 stat->nexttd = tail; 2822 stat->flags = OHCI_CALL_DONE; 2823 stat->len = 0; 2824 stat->xfer = xfer; 2825 ohci_hash_add_td(sc, stat); 2826 2827 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2828 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2829 2830 memset(&tail->td, 0, sizeof(tail->td)); 2831 tail->nexttd = NULL; 2832 tail->xfer = NULL; 2833 2834 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 2835 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2836 2837 #ifdef OHCI_DEBUG 2838 USBHIST_LOGN(ohcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2839 if (ohcidebug >= 5) { 2840 ohci_dump_ed(sc, sed); 2841 ohci_dump_tds(sc, setup); 2842 } 2843 USBHIST_LOGN(ohcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2844 #endif 2845 2846 /* Insert ED in schedule */ 2847 sed->ed.ed_tailp = HTOO32(tail->physaddr); 2848 usb_syncmem(&sed->dma, 2849 sed->offs + offsetof(ohci_ed_t, ed_tailp), 2850 sizeof(sed->ed.ed_tailp), 2851 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2852 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2853 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2854 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2855 ohci_timeout, xfer); 2856 } 2857 2858 DPRINTF("done", 0, 0, 0, 0); 2859 2860 mutex_exit(&sc->sc_lock); 2861 2862 return USBD_IN_PROGRESS; 2863 } 2864 2865 /* Abort a device control request. */ 2866 Static void 2867 ohci_device_ctrl_abort(struct usbd_xfer *xfer) 2868 { 2869 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 2870 2871 KASSERT(mutex_owned(&sc->sc_lock)); 2872 2873 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2874 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 2875 ohci_abort_xfer(xfer, USBD_CANCELLED); 2876 } 2877 2878 /* Close a device control pipe. */ 2879 Static void 2880 ohci_device_ctrl_close(struct usbd_pipe *pipe) 2881 { 2882 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2883 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2884 2885 KASSERT(mutex_owned(&sc->sc_lock)); 2886 2887 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2888 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 2889 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2890 ohci_free_std_locked(sc, opipe->tail.td); 2891 } 2892 2893 /************************/ 2894 2895 Static void 2896 ohci_device_clear_toggle(struct usbd_pipe *pipe) 2897 { 2898 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2899 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2900 2901 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2902 } 2903 2904 Static void 2905 ohci_noop(struct usbd_pipe *pipe) 2906 { 2907 } 2908 2909 Static int 2910 ohci_device_bulk_init(struct usbd_xfer *xfer) 2911 { 2912 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2913 int len = xfer->ux_bufsize; 2914 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;; 2915 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2916 int err; 2917 2918 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2919 2920 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2921 2922 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 2923 len, isread, xfer->ux_flags); 2924 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 2925 2926 /* Allocate a chain of new TDs (including a new tail). */ 2927 err = ohci_alloc_std_chain(sc, xfer, len, isread); 2928 if (err) 2929 return err; 2930 2931 return 0; 2932 } 2933 2934 Static void 2935 ohci_device_bulk_fini(struct usbd_xfer *xfer) 2936 { 2937 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2938 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2939 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2940 2941 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2942 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 2943 2944 mutex_enter(&sc->sc_lock); 2945 for (size_t i = 0; i < ox->ox_nstd; i++) { 2946 ohci_soft_td_t *std = ox->ox_stds[i]; 2947 if (std == NULL) 2948 break; 2949 if (std != opipe->tail.td) 2950 ohci_free_std_locked(sc, std); 2951 } 2952 mutex_exit(&sc->sc_lock); 2953 2954 if (ox->ox_nstd) { 2955 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 2956 kmem_free(ox->ox_stds, sz); 2957 } 2958 } 2959 2960 Static usbd_status 2961 ohci_device_bulk_transfer(struct usbd_xfer *xfer) 2962 { 2963 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2964 usbd_status err; 2965 2966 /* Insert last in queue. */ 2967 mutex_enter(&sc->sc_lock); 2968 err = usb_insert_transfer(xfer); 2969 mutex_exit(&sc->sc_lock); 2970 if (err) 2971 return err; 2972 2973 /* Pipe isn't running, start first */ 2974 return ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2975 } 2976 2977 Static usbd_status 2978 ohci_device_bulk_start(struct usbd_xfer *xfer) 2979 { 2980 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2981 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2982 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2983 ohci_soft_td_t *last; 2984 ohci_soft_td_t *data, *tail, *tdp; 2985 ohci_soft_ed_t *sed; 2986 int len, isread, endpt; 2987 2988 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2989 2990 if (sc->sc_dying) 2991 return USBD_IOERROR; 2992 2993 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2994 2995 len = xfer->ux_length; 2996 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2997 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2998 sed = opipe->sed; 2999 3000 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 3001 len, isread, xfer->ux_flags); 3002 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 3003 3004 mutex_enter(&sc->sc_lock); 3005 3006 /* 3007 * Use the pipe "tail" TD as our first and loan our first TD to the 3008 * next transfer 3009 */ 3010 data = opipe->tail.td; 3011 opipe->tail.td = ox->ox_stds[0]; 3012 ox->ox_stds[0] = data; 3013 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3014 3015 /* point at sentinel */ 3016 tail = opipe->tail.td; 3017 memset(&tail->td, 0, sizeof(tail->td)); 3018 tail->nexttd = NULL; 3019 tail->xfer = NULL; 3020 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3021 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3022 xfer->ux_hcpriv = data; 3023 3024 DPRINTFN(8, "xfer %#jx data %#jx tail %#jx", (uintptr_t)xfer, 3025 (uintptr_t)ox->ox_stds[0], (uintptr_t)tail, 0); 3026 KASSERT(opipe->tail.td == tail); 3027 3028 /* We want interrupt at the end of the transfer. */ 3029 last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3030 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3031 last->td.td_nexttd = HTOO32(tail->physaddr); 3032 last->nexttd = tail; 3033 last->flags |= OHCI_CALL_DONE; 3034 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3035 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3036 3037 DPRINTFN(4, "ed_flags=0x%08jx td_flags=0x%08jx " 3038 "td_cbp=0x%08jx td_be=0x%08jx", 3039 (int)O32TOH(sed->ed.ed_flags), 3040 (int)O32TOH(data->td.td_flags), 3041 (int)O32TOH(data->td.td_cbp), 3042 (int)O32TOH(data->td.td_be)); 3043 3044 #ifdef OHCI_DEBUG 3045 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3046 if (ohcidebug >= 5) { 3047 ohci_dump_ed(sc, sed); 3048 ohci_dump_tds(sc, data); 3049 } 3050 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3051 #endif 3052 3053 /* Insert ED in schedule */ 3054 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3055 KASSERT(tdp->xfer == xfer); 3056 } 3057 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3058 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3059 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3060 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3061 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3062 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3063 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3064 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3065 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3066 ohci_timeout, xfer); 3067 } 3068 mutex_exit(&sc->sc_lock); 3069 3070 return USBD_IN_PROGRESS; 3071 } 3072 3073 Static void 3074 ohci_device_bulk_abort(struct usbd_xfer *xfer) 3075 { 3076 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3077 3078 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3079 3080 KASSERT(mutex_owned(&sc->sc_lock)); 3081 3082 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3083 ohci_abort_xfer(xfer, USBD_CANCELLED); 3084 } 3085 3086 /* 3087 * Close a device bulk pipe. 3088 */ 3089 Static void 3090 ohci_device_bulk_close(struct usbd_pipe *pipe) 3091 { 3092 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3093 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3094 3095 KASSERT(mutex_owned(&sc->sc_lock)); 3096 3097 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3098 3099 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3100 ohci_close_pipe(pipe, sc->sc_bulk_head); 3101 ohci_free_std_locked(sc, opipe->tail.td); 3102 } 3103 3104 /************************/ 3105 3106 Static int 3107 ohci_device_intr_init(struct usbd_xfer *xfer) 3108 { 3109 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3110 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3111 int len = xfer->ux_bufsize; 3112 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;; 3113 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3114 int err; 3115 3116 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3117 3118 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3119 KASSERT(len != 0); 3120 3121 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 3122 len, isread, xfer->ux_flags); 3123 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 3124 3125 ox->ox_nstd = 0; 3126 3127 err = ohci_alloc_std_chain(sc, xfer, len, isread); 3128 if (err) { 3129 return err; 3130 } 3131 3132 return 0; 3133 } 3134 3135 Static void 3136 ohci_device_intr_fini(struct usbd_xfer *xfer) 3137 { 3138 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3139 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3140 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3141 3142 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3143 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 3144 3145 mutex_enter(&sc->sc_lock); 3146 for (size_t i = 0; i < ox->ox_nstd; i++) { 3147 ohci_soft_td_t *std = ox->ox_stds[i]; 3148 if (std != NULL) 3149 break; 3150 if (std != opipe->tail.td) 3151 ohci_free_std_locked(sc, std); 3152 } 3153 mutex_exit(&sc->sc_lock); 3154 3155 if (ox->ox_nstd) { 3156 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 3157 kmem_free(ox->ox_stds, sz); 3158 } 3159 } 3160 3161 Static usbd_status 3162 ohci_device_intr_transfer(struct usbd_xfer *xfer) 3163 { 3164 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3165 usbd_status err; 3166 3167 /* Insert last in queue. */ 3168 mutex_enter(&sc->sc_lock); 3169 err = usb_insert_transfer(xfer); 3170 mutex_exit(&sc->sc_lock); 3171 if (err) 3172 return err; 3173 3174 /* Pipe isn't running, start first */ 3175 return ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3176 } 3177 3178 Static usbd_status 3179 ohci_device_intr_start(struct usbd_xfer *xfer) 3180 { 3181 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3182 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3183 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3184 ohci_soft_ed_t *sed = opipe->sed; 3185 ohci_soft_td_t *data, *last, *tail; 3186 int len, isread, endpt; 3187 3188 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3189 3190 if (sc->sc_dying) 3191 return USBD_IOERROR; 3192 3193 DPRINTFN(3, "xfer=%#jx len=%jd flags=%jd priv=%#jx", (uintptr_t)xfer, 3194 xfer->ux_length, xfer->ux_flags, (uintptr_t)xfer->ux_priv); 3195 3196 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3197 3198 len = xfer->ux_length; 3199 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3200 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3201 3202 mutex_enter(&sc->sc_lock); 3203 3204 /* 3205 * Use the pipe "tail" TD as our first and loan our first TD to the 3206 * next transfer. 3207 */ 3208 data = opipe->tail.td; 3209 opipe->tail.td = ox->ox_stds[0]; 3210 ox->ox_stds[0] = data; 3211 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3212 3213 /* point at sentinel */ 3214 tail = opipe->tail.td; 3215 memset(&tail->td, 0, sizeof(tail->td)); 3216 tail->nexttd = NULL; 3217 tail->xfer = NULL; 3218 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3219 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3220 xfer->ux_hcpriv = data; 3221 3222 DPRINTFN(8, "data %#jx tail %#jx", (uintptr_t)ox->ox_stds[0], 3223 (uintptr_t)tail, 0, 0); 3224 KASSERT(opipe->tail.td == tail); 3225 3226 /* We want interrupt at the end of the transfer. */ 3227 last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3228 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3229 3230 last->td.td_nexttd = HTOO32(tail->physaddr); 3231 last->nexttd = tail; 3232 last->flags |= OHCI_CALL_DONE; 3233 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3234 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3235 3236 #ifdef OHCI_DEBUG 3237 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3238 if (ohcidebug >= 5) { 3239 ohci_dump_ed(sc, sed); 3240 ohci_dump_tds(sc, data); 3241 } 3242 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3243 #endif 3244 3245 /* Insert ED in schedule */ 3246 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3247 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3248 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3249 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3250 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3251 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3252 3253 mutex_exit(&sc->sc_lock); 3254 3255 return USBD_IN_PROGRESS; 3256 } 3257 3258 /* Abort a device interrupt request. */ 3259 Static void 3260 ohci_device_intr_abort(struct usbd_xfer *xfer) 3261 { 3262 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3263 3264 KASSERT(mutex_owned(&sc->sc_lock)); 3265 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3266 3267 ohci_abort_xfer(xfer, USBD_CANCELLED); 3268 } 3269 3270 /* Close a device interrupt pipe. */ 3271 Static void 3272 ohci_device_intr_close(struct usbd_pipe *pipe) 3273 { 3274 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3275 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3276 int nslots = opipe->intr.nslots; 3277 int pos = opipe->intr.pos; 3278 int j; 3279 ohci_soft_ed_t *p, *sed = opipe->sed; 3280 3281 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3282 3283 KASSERT(mutex_owned(&sc->sc_lock)); 3284 3285 DPRINTFN(1, "pipe=%#jx nslots=%jd pos=%jd", (uintptr_t)pipe, nslots, 3286 pos, 0); 3287 usb_syncmem(&sed->dma, sed->offs, 3288 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3289 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3290 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3291 sizeof(sed->ed.ed_flags), 3292 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3293 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3294 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3295 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3296 3297 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3298 continue; 3299 KASSERT(p); 3300 p->next = sed->next; 3301 p->ed.ed_nexted = sed->ed.ed_nexted; 3302 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3303 sizeof(p->ed.ed_nexted), 3304 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3305 3306 for (j = 0; j < nslots; j++) 3307 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3308 3309 ohci_free_std_locked(sc, opipe->tail.td); 3310 ohci_free_sed_locked(sc, opipe->sed); 3311 } 3312 3313 Static usbd_status 3314 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3315 { 3316 int i, j, best; 3317 u_int npoll, slow, shigh, nslots; 3318 u_int bestbw, bw; 3319 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3320 3321 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3322 3323 DPRINTFN(2, "pipe=%#jx", (uintptr_t)opipe, 0, 0, 0); 3324 if (ival == 0) { 3325 printf("ohci_setintr: 0 interval\n"); 3326 return USBD_INVAL; 3327 } 3328 3329 npoll = OHCI_NO_INTRS; 3330 while (npoll > ival) 3331 npoll /= 2; 3332 DPRINTFN(2, "ival=%jd npoll=%jd", ival, npoll, 0, 0); 3333 3334 /* 3335 * We now know which level in the tree the ED must go into. 3336 * Figure out which slot has most bandwidth left over. 3337 * Slots to examine: 3338 * npoll 3339 * 1 0 3340 * 2 1 2 3341 * 4 3 4 5 6 3342 * 8 7 8 9 10 11 12 13 14 3343 * N (N-1) .. (N-1+N-1) 3344 */ 3345 slow = npoll-1; 3346 shigh = slow + npoll; 3347 nslots = OHCI_NO_INTRS / npoll; 3348 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3349 bw = 0; 3350 for (j = 0; j < nslots; j++) 3351 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3352 if (bw < bestbw) { 3353 best = i; 3354 bestbw = bw; 3355 } 3356 } 3357 DPRINTFN(2, "best=%jd(%jd..%jd) bestbw=%jd", best, slow, shigh, bestbw); 3358 3359 mutex_enter(&sc->sc_lock); 3360 hsed = sc->sc_eds[best]; 3361 sed->next = hsed->next; 3362 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3363 sizeof(hsed->ed.ed_flags), 3364 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3365 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3366 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3367 sizeof(sed->ed.ed_flags), 3368 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3369 hsed->next = sed; 3370 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3371 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3372 sizeof(hsed->ed.ed_flags), 3373 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3374 mutex_exit(&sc->sc_lock); 3375 3376 for (j = 0; j < nslots; j++) 3377 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3378 opipe->intr.nslots = nslots; 3379 opipe->intr.pos = best; 3380 3381 DPRINTFN(5, "returns %#jx", (uintptr_t)opipe, 0, 0, 0); 3382 return USBD_NORMAL_COMPLETION; 3383 } 3384 3385 /***********************/ 3386 3387 Static int 3388 ohci_device_isoc_init(struct usbd_xfer *xfer) 3389 { 3390 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3391 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3392 ohci_soft_itd_t *sitd; 3393 size_t i; 3394 int err; 3395 3396 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3397 3398 DPRINTFN(1, "xfer %#jx len %jd flags %jd", (uintptr_t)xfer, 3399 xfer->ux_length, xfer->ux_flags, 0); 3400 3401 const size_t nfsitd = 3402 (xfer->ux_nframes + OHCI_ITD_NOFFSET - 1) / OHCI_ITD_NOFFSET; 3403 const size_t nbsitd = xfer->ux_bufsize / OHCI_PAGE_SIZE; 3404 const size_t nsitd = MAX(nfsitd, nbsitd) + 1; 3405 3406 ox->ox_sitds = kmem_zalloc(sizeof(ohci_soft_itd_t *) * nsitd, 3407 KM_SLEEP); 3408 ox->ox_nsitd = nsitd; 3409 3410 for (i = 0; i < nsitd; i++) { 3411 /* Allocate next ITD */ 3412 sitd = ohci_alloc_sitd(sc); 3413 if (sitd == NULL) { 3414 err = ENOMEM; 3415 goto fail; 3416 } 3417 ox->ox_sitds[i] = sitd; 3418 sitd->xfer = xfer; 3419 sitd->flags = 0; 3420 } 3421 3422 return 0; 3423 fail: 3424 for (; i > 0;) { 3425 ohci_free_sitd(sc, ox->ox_sitds[--i]); 3426 } 3427 return err; 3428 } 3429 3430 Static void 3431 ohci_device_isoc_fini(struct usbd_xfer *xfer) 3432 { 3433 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3434 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3435 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3436 3437 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3438 3439 mutex_enter(&sc->sc_lock); 3440 for (size_t i = 0; i < ox->ox_nsitd; i++) { 3441 if (ox->ox_sitds[i] != opipe->tail.itd) { 3442 ohci_free_sitd_locked(sc, ox->ox_sitds[i]); 3443 } 3444 } 3445 mutex_exit(&sc->sc_lock); 3446 3447 if (ox->ox_nsitd) { 3448 const size_t sz = sizeof(ohci_soft_itd_t *) * ox->ox_nsitd; 3449 kmem_free(ox->ox_sitds, sz); 3450 } 3451 } 3452 3453 3454 usbd_status 3455 ohci_device_isoc_transfer(struct usbd_xfer *xfer) 3456 { 3457 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3458 usbd_status __diagused err; 3459 3460 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3461 3462 DPRINTFN(5, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3463 3464 /* Put it on our queue, */ 3465 mutex_enter(&sc->sc_lock); 3466 err = usb_insert_transfer(xfer); 3467 mutex_exit(&sc->sc_lock); 3468 3469 KASSERT(err == USBD_NORMAL_COMPLETION); 3470 3471 /* insert into schedule, */ 3472 ohci_device_isoc_enter(xfer); 3473 3474 /* and start if the pipe wasn't running */ 3475 return USBD_IN_PROGRESS; 3476 } 3477 3478 void 3479 ohci_device_isoc_enter(struct usbd_xfer *xfer) 3480 { 3481 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3482 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3483 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3484 ohci_soft_ed_t *sed = opipe->sed; 3485 ohci_soft_itd_t *sitd, *nsitd, *tail; 3486 ohci_physaddr_t buf, offs, noffs, bp0; 3487 int i, ncur, nframes; 3488 3489 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3490 DPRINTFN(5, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3491 3492 mutex_enter(&sc->sc_lock); 3493 3494 if (sc->sc_dying) { 3495 mutex_exit(&sc->sc_lock); 3496 return; 3497 } 3498 3499 struct isoc *isoc = &opipe->isoc; 3500 3501 DPRINTFN(1, "used=%jd next=%jd xfer=%#jx nframes=%jd", 3502 isoc->inuse, isoc->next, (uintptr_t)xfer, xfer->ux_nframes); 3503 3504 if (isoc->next == -1) { 3505 /* Not in use yet, schedule it a few frames ahead. */ 3506 isoc->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3507 DPRINTFN(2,"start next=%jd", isoc->next, 0, 0, 0); 3508 } 3509 3510 sitd = opipe->tail.itd; 3511 opipe->tail.itd = ox->ox_sitds[0]; 3512 ox->ox_sitds[0] = sitd; 3513 3514 buf = DMAADDR(&xfer->ux_dmabuf, 0); 3515 bp0 = OHCI_PAGE(buf); 3516 offs = OHCI_PAGE_OFFSET(buf); 3517 nframes = xfer->ux_nframes; 3518 xfer->ux_hcpriv = sitd; 3519 size_t j = 1; 3520 for (i = ncur = 0; i < nframes; i++, ncur++) { 3521 noffs = offs + xfer->ux_frlengths[i]; 3522 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3523 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3524 3525 /* Allocate next ITD */ 3526 nsitd = ox->ox_sitds[j++]; 3527 KASSERT(nsitd != NULL); 3528 KASSERT(j < ox->ox_nsitd); 3529 3530 /* Fill current ITD */ 3531 sitd->itd.itd_flags = HTOO32( 3532 OHCI_ITD_NOCC | 3533 OHCI_ITD_SET_SF(isoc->next) | 3534 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3535 OHCI_ITD_SET_FC(ncur)); 3536 sitd->itd.itd_bp0 = HTOO32(bp0); 3537 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3538 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3539 sitd->nextitd = nsitd; 3540 sitd->xfer = xfer; 3541 sitd->flags = 0; 3542 #ifdef DIAGNOSTIC 3543 sitd->isdone = false; 3544 #endif 3545 ohci_hash_add_itd(sc, sitd); 3546 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3547 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3548 3549 sitd = nsitd; 3550 isoc->next = isoc->next + ncur; 3551 bp0 = OHCI_PAGE(buf + offs); 3552 ncur = 0; 3553 } 3554 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3555 /* XXX Sync */ 3556 offs = noffs; 3557 } 3558 KASSERT(j <= ox->ox_nsitd); 3559 3560 /* point at sentinel */ 3561 tail = opipe->tail.itd; 3562 memset(&tail->itd, 0, sizeof(tail->itd)); 3563 tail->nextitd = NULL; 3564 tail->xfer = NULL; 3565 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->itd), 3566 BUS_DMASYNC_PREWRITE); 3567 3568 /* Fixup last used ITD */ 3569 sitd->itd.itd_flags = HTOO32( 3570 OHCI_ITD_NOCC | 3571 OHCI_ITD_SET_SF(isoc->next) | 3572 OHCI_ITD_SET_DI(0) | 3573 OHCI_ITD_SET_FC(ncur)); 3574 sitd->itd.itd_bp0 = HTOO32(bp0); 3575 sitd->itd.itd_nextitd = HTOO32(tail->physaddr); 3576 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3577 sitd->nextitd = tail; 3578 sitd->xfer = xfer; 3579 sitd->flags = OHCI_CALL_DONE; 3580 #ifdef DIAGNOSTIC 3581 sitd->isdone = false; 3582 #endif 3583 ohci_hash_add_itd(sc, sitd); 3584 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3585 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3586 3587 isoc->next = isoc->next + ncur; 3588 isoc->inuse += nframes; 3589 3590 /* XXX pretend we did it all */ 3591 xfer->ux_actlen = offs; 3592 xfer->ux_status = USBD_IN_PROGRESS; 3593 3594 #ifdef OHCI_DEBUG 3595 if (ohcidebug >= 5) { 3596 DPRINTF("frame=%jd", O32TOH(sc->sc_hcca->hcca_frame_number), 3597 0, 0, 0); 3598 ohci_dump_itds(sc, xfer->ux_hcpriv); 3599 ohci_dump_ed(sc, sed); 3600 } 3601 #endif 3602 3603 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3604 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3605 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3606 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3607 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3608 sizeof(sed->ed.ed_flags), 3609 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3610 mutex_exit(&sc->sc_lock); 3611 } 3612 3613 void 3614 ohci_device_isoc_abort(struct usbd_xfer *xfer) 3615 { 3616 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3617 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3618 ohci_soft_ed_t *sed; 3619 ohci_soft_itd_t *sitd; 3620 3621 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3622 DPRINTFN(1, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3623 3624 KASSERT(mutex_owned(&sc->sc_lock)); 3625 3626 /* Transfer is already done. */ 3627 if (xfer->ux_status != USBD_NOT_STARTED && 3628 xfer->ux_status != USBD_IN_PROGRESS) { 3629 printf("ohci_device_isoc_abort: early return\n"); 3630 goto done; 3631 } 3632 3633 /* Give xfer the requested abort code. */ 3634 xfer->ux_status = USBD_CANCELLED; 3635 3636 sed = opipe->sed; 3637 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3638 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3639 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3640 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3641 sizeof(sed->ed.ed_flags), 3642 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3643 3644 sitd = xfer->ux_hcpriv; 3645 KASSERT(sitd); 3646 3647 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3648 3649 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3650 ohci_hash_rem_itd(sc, sitd); 3651 #ifdef DIAGNOSTIC 3652 DPRINTFN(1, "abort sets done sitd=%#jx", (uintptr_t)sitd, 3653 0, 0, 0); 3654 sitd->isdone = true; 3655 #endif 3656 } 3657 3658 /* Run callback. */ 3659 usb_transfer_complete(xfer); 3660 3661 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3662 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3663 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3664 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3665 3666 done: 3667 KASSERT(mutex_owned(&sc->sc_lock)); 3668 } 3669 3670 void 3671 ohci_device_isoc_done(struct usbd_xfer *xfer) 3672 { 3673 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3674 DPRINTFN(1, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3675 } 3676 3677 usbd_status 3678 ohci_setup_isoc(struct usbd_pipe *pipe) 3679 { 3680 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3681 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3682 struct isoc *isoc = &opipe->isoc; 3683 3684 isoc->next = -1; 3685 isoc->inuse = 0; 3686 3687 mutex_enter(&sc->sc_lock); 3688 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3689 mutex_exit(&sc->sc_lock); 3690 3691 return USBD_NORMAL_COMPLETION; 3692 } 3693 3694 void 3695 ohci_device_isoc_close(struct usbd_pipe *pipe) 3696 { 3697 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3698 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3699 3700 KASSERT(mutex_owned(&sc->sc_lock)); 3701 3702 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3703 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3704 ohci_close_pipe(pipe, sc->sc_isoc_head); 3705 #ifdef DIAGNOSTIC 3706 opipe->tail.itd->isdone = true; 3707 #endif 3708 ohci_free_sitd_locked(sc, opipe->tail.itd); 3709 } 3710
Indexes created Fri Sep 26 20:09:58 GMT 2025