ohci.c revision 1.278
1 /* $NetBSD: ohci.c,v 1.278 2018/02/01 09:55:37 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * USB Open Host Controller driver. 38 * 39 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 40 * USB spec: http://www.usb.org/developers/docs/ 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.278 2018/02/01 09:55:37 msaitoh Exp $"); 45 46 #ifdef _KERNEL_OPT 47 #include "opt_usb.h" 48 #endif 49 50 #include <sys/param.h> 51 52 #include <sys/cpu.h> 53 #include <sys/device.h> 54 #include <sys/kernel.h> 55 #include <sys/kmem.h> 56 #include <sys/proc.h> 57 #include <sys/queue.h> 58 #include <sys/select.h> 59 #include <sys/sysctl.h> 60 #include <sys/systm.h> 61 62 #include <machine/endian.h> 63 64 #include <dev/usb/usb.h> 65 #include <dev/usb/usbdi.h> 66 #include <dev/usb/usbdivar.h> 67 #include <dev/usb/usb_mem.h> 68 #include <dev/usb/usb_quirks.h> 69 70 #include <dev/usb/ohcireg.h> 71 #include <dev/usb/ohcivar.h> 72 #include <dev/usb/usbroothub.h> 73 #include <dev/usb/usbhist.h> 74 75 #ifdef USB_DEBUG 76 #ifndef OHCI_DEBUG 77 #define ohcidebug 0 78 #else 79 static int ohcidebug = 10; 80 81 SYSCTL_SETUP(sysctl_hw_ohci_setup, "sysctl hw.ohci setup") 82 { 83 int err; 84 const struct sysctlnode *rnode; 85 const struct sysctlnode *cnode; 86 87 err = sysctl_createv(clog, 0, NULL, &rnode, 88 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ohci", 89 SYSCTL_DESCR("ohci global controls"), 90 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 91 92 if (err) 93 goto fail; 94 95 /* control debugging printfs */ 96 err = sysctl_createv(clog, 0, &rnode, &cnode, 97 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 98 "debug", SYSCTL_DESCR("Enable debugging output"), 99 NULL, 0, &ohcidebug, sizeof(ohcidebug), CTL_CREATE, CTL_EOL); 100 if (err) 101 goto fail; 102 103 return; 104 fail: 105 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 106 } 107 108 #endif /* OHCI_DEBUG */ 109 #endif /* USB_DEBUG */ 110 111 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ohcidebug,FMT,A,B,C,D) 112 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ohcidebug,N,FMT,A,B,C,D) 113 #define OHCIHIST_FUNC() USBHIST_FUNC() 114 #define OHCIHIST_CALLED(name) USBHIST_CALLED(ohcidebug) 115 116 #if BYTE_ORDER == BIG_ENDIAN 117 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 118 #else 119 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 120 #endif 121 122 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 123 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 124 #define HTOO16(val) O16TOH(val) 125 #define HTOO32(val) O32TOH(val) 126 127 struct ohci_pipe; 128 129 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 130 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 131 132 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 133 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 134 Static void ohci_free_std_locked(ohci_softc_t *, ohci_soft_td_t *); 135 136 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 137 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 138 Static void ohci_free_sitd_locked(ohci_softc_t *, 139 ohci_soft_itd_t *); 140 141 Static int ohci_alloc_std_chain(ohci_softc_t *, struct usbd_xfer *, 142 int, int); 143 Static void ohci_free_stds(ohci_softc_t *, struct ohci_xfer *); 144 145 Static void ohci_reset_std_chain(ohci_softc_t *, struct usbd_xfer *, 146 int, int, ohci_soft_td_t *, ohci_soft_td_t **); 147 148 Static usbd_status ohci_open(struct usbd_pipe *); 149 Static void ohci_poll(struct usbd_bus *); 150 Static void ohci_softintr(void *); 151 Static void ohci_rhsc(ohci_softc_t *, struct usbd_xfer *); 152 Static void ohci_rhsc_softint(void *); 153 154 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 155 ohci_soft_ed_t *); 156 157 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 158 ohci_soft_ed_t *); 159 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 160 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 161 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 162 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 163 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 164 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 165 166 Static usbd_status ohci_setup_isoc(struct usbd_pipe *); 167 Static void ohci_device_isoc_enter(struct usbd_xfer *); 168 169 Static struct usbd_xfer * 170 ohci_allocx(struct usbd_bus *, unsigned int); 171 Static void ohci_freex(struct usbd_bus *, struct usbd_xfer *); 172 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 173 Static int ohci_roothub_ctrl(struct usbd_bus *, 174 usb_device_request_t *, void *, int); 175 176 Static usbd_status ohci_root_intr_transfer(struct usbd_xfer *); 177 Static usbd_status ohci_root_intr_start(struct usbd_xfer *); 178 Static void ohci_root_intr_abort(struct usbd_xfer *); 179 Static void ohci_root_intr_close(struct usbd_pipe *); 180 Static void ohci_root_intr_done(struct usbd_xfer *); 181 182 Static int ohci_device_ctrl_init(struct usbd_xfer *); 183 Static void ohci_device_ctrl_fini(struct usbd_xfer *); 184 Static usbd_status ohci_device_ctrl_transfer(struct usbd_xfer *); 185 Static usbd_status ohci_device_ctrl_start(struct usbd_xfer *); 186 Static void ohci_device_ctrl_abort(struct usbd_xfer *); 187 Static void ohci_device_ctrl_close(struct usbd_pipe *); 188 Static void ohci_device_ctrl_done(struct usbd_xfer *); 189 190 Static int ohci_device_bulk_init(struct usbd_xfer *); 191 Static void ohci_device_bulk_fini(struct usbd_xfer *); 192 Static usbd_status ohci_device_bulk_transfer(struct usbd_xfer *); 193 Static usbd_status ohci_device_bulk_start(struct usbd_xfer *); 194 Static void ohci_device_bulk_abort(struct usbd_xfer *); 195 Static void ohci_device_bulk_close(struct usbd_pipe *); 196 Static void ohci_device_bulk_done(struct usbd_xfer *); 197 198 Static int ohci_device_intr_init(struct usbd_xfer *); 199 Static void ohci_device_intr_fini(struct usbd_xfer *); 200 Static usbd_status ohci_device_intr_transfer(struct usbd_xfer *); 201 Static usbd_status ohci_device_intr_start(struct usbd_xfer *); 202 Static void ohci_device_intr_abort(struct usbd_xfer *); 203 Static void ohci_device_intr_close(struct usbd_pipe *); 204 Static void ohci_device_intr_done(struct usbd_xfer *); 205 206 Static int ohci_device_isoc_init(struct usbd_xfer *); 207 Static void ohci_device_isoc_fini(struct usbd_xfer *); 208 Static usbd_status ohci_device_isoc_transfer(struct usbd_xfer *); 209 Static void ohci_device_isoc_abort(struct usbd_xfer *); 210 Static void ohci_device_isoc_close(struct usbd_pipe *); 211 Static void ohci_device_isoc_done(struct usbd_xfer *); 212 213 Static usbd_status ohci_device_setintr(ohci_softc_t *, 214 struct ohci_pipe *, int); 215 216 Static void ohci_timeout(void *); 217 Static void ohci_timeout_task(void *); 218 Static void ohci_rhsc_enable(void *); 219 220 Static void ohci_close_pipe(struct usbd_pipe *, ohci_soft_ed_t *); 221 Static void ohci_abort_xfer(struct usbd_xfer *, usbd_status); 222 223 Static void ohci_device_clear_toggle(struct usbd_pipe *); 224 Static void ohci_noop(struct usbd_pipe *); 225 226 #ifdef OHCI_DEBUG 227 Static void ohci_dumpregs(ohci_softc_t *); 228 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 229 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 230 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 231 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 232 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 233 #endif 234 235 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 236 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 237 #define OWRITE1(sc, r, x) \ 238 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 239 #define OWRITE2(sc, r, x) \ 240 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 241 #define OWRITE4(sc, r, x) \ 242 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 243 244 static __inline uint32_t 245 OREAD4(ohci_softc_t *sc, bus_size_t r) 246 { 247 248 OBARR(sc); 249 return bus_space_read_4(sc->iot, sc->ioh, r); 250 } 251 252 /* Reverse the bits in a value 0 .. 31 */ 253 Static uint8_t revbits[OHCI_NO_INTRS] = 254 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 255 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 256 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 257 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 258 259 struct ohci_pipe { 260 struct usbd_pipe pipe; 261 ohci_soft_ed_t *sed; 262 union { 263 ohci_soft_td_t *td; 264 ohci_soft_itd_t *itd; 265 } tail; 266 /* Info needed for different pipe kinds. */ 267 union { 268 /* Control pipe */ 269 struct { 270 usb_dma_t reqdma; 271 } ctrl; 272 /* Interrupt pipe */ 273 struct { 274 int nslots; 275 int pos; 276 } intr; 277 /* Isochronous pipe */ 278 struct isoc { 279 int next, inuse; 280 } isoc; 281 }; 282 }; 283 284 Static const struct usbd_bus_methods ohci_bus_methods = { 285 .ubm_open = ohci_open, 286 .ubm_softint = ohci_softintr, 287 .ubm_dopoll = ohci_poll, 288 .ubm_allocx = ohci_allocx, 289 .ubm_freex = ohci_freex, 290 .ubm_getlock = ohci_get_lock, 291 .ubm_rhctrl = ohci_roothub_ctrl, 292 }; 293 294 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 295 .upm_transfer = ohci_root_intr_transfer, 296 .upm_start = ohci_root_intr_start, 297 .upm_abort = ohci_root_intr_abort, 298 .upm_close = ohci_root_intr_close, 299 .upm_cleartoggle = ohci_noop, 300 .upm_done = ohci_root_intr_done, 301 }; 302 303 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 304 .upm_init = ohci_device_ctrl_init, 305 .upm_fini = ohci_device_ctrl_fini, 306 .upm_transfer = ohci_device_ctrl_transfer, 307 .upm_start = ohci_device_ctrl_start, 308 .upm_abort = ohci_device_ctrl_abort, 309 .upm_close = ohci_device_ctrl_close, 310 .upm_cleartoggle = ohci_noop, 311 .upm_done = ohci_device_ctrl_done, 312 }; 313 314 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 315 .upm_init = ohci_device_intr_init, 316 .upm_fini = ohci_device_intr_fini, 317 .upm_transfer = ohci_device_intr_transfer, 318 .upm_start = ohci_device_intr_start, 319 .upm_abort = ohci_device_intr_abort, 320 .upm_close = ohci_device_intr_close, 321 .upm_cleartoggle = ohci_device_clear_toggle, 322 .upm_done = ohci_device_intr_done, 323 }; 324 325 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 326 .upm_init = ohci_device_bulk_init, 327 .upm_fini = ohci_device_bulk_fini, 328 .upm_transfer = ohci_device_bulk_transfer, 329 .upm_start = ohci_device_bulk_start, 330 .upm_abort = ohci_device_bulk_abort, 331 .upm_close = ohci_device_bulk_close, 332 .upm_cleartoggle = ohci_device_clear_toggle, 333 .upm_done = ohci_device_bulk_done, 334 }; 335 336 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 337 .upm_init = ohci_device_isoc_init, 338 .upm_fini = ohci_device_isoc_fini, 339 .upm_transfer = ohci_device_isoc_transfer, 340 .upm_abort = ohci_device_isoc_abort, 341 .upm_close = ohci_device_isoc_close, 342 .upm_cleartoggle = ohci_noop, 343 .upm_done = ohci_device_isoc_done, 344 }; 345 346 int 347 ohci_activate(device_t self, enum devact act) 348 { 349 struct ohci_softc *sc = device_private(self); 350 351 switch (act) { 352 case DVACT_DEACTIVATE: 353 sc->sc_dying = 1; 354 return 0; 355 default: 356 return EOPNOTSUPP; 357 } 358 } 359 360 void 361 ohci_childdet(device_t self, device_t child) 362 { 363 struct ohci_softc *sc = device_private(self); 364 365 KASSERT(sc->sc_child == child); 366 sc->sc_child = NULL; 367 } 368 369 int 370 ohci_detach(struct ohci_softc *sc, int flags) 371 { 372 int rv = 0; 373 374 if (sc->sc_child != NULL) 375 rv = config_detach(sc->sc_child, flags); 376 377 if (rv != 0) 378 return rv; 379 380 softint_disestablish(sc->sc_rhsc_si); 381 382 callout_halt(&sc->sc_tmo_rhsc, NULL); 383 callout_destroy(&sc->sc_tmo_rhsc); 384 385 cv_destroy(&sc->sc_softwake_cv); 386 387 mutex_destroy(&sc->sc_lock); 388 mutex_destroy(&sc->sc_intr_lock); 389 390 if (sc->sc_hcca != NULL) 391 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 392 pool_cache_destroy(sc->sc_xferpool); 393 394 return rv; 395 } 396 397 ohci_soft_ed_t * 398 ohci_alloc_sed(ohci_softc_t *sc) 399 { 400 ohci_soft_ed_t *sed; 401 usbd_status err; 402 int i, offs; 403 usb_dma_t dma; 404 405 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 406 407 mutex_enter(&sc->sc_lock); 408 if (sc->sc_freeeds == NULL) { 409 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 410 mutex_exit(&sc->sc_lock); 411 412 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 413 OHCI_ED_ALIGN, &dma); 414 if (err) 415 return 0; 416 417 mutex_enter(&sc->sc_lock); 418 for (i = 0; i < OHCI_SED_CHUNK; i++) { 419 offs = i * OHCI_SED_SIZE; 420 sed = KERNADDR(&dma, offs); 421 sed->physaddr = DMAADDR(&dma, offs); 422 sed->dma = dma; 423 sed->offs = offs; 424 sed->next = sc->sc_freeeds; 425 sc->sc_freeeds = sed; 426 } 427 } 428 sed = sc->sc_freeeds; 429 sc->sc_freeeds = sed->next; 430 mutex_exit(&sc->sc_lock); 431 432 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 433 sed->next = 0; 434 return sed; 435 } 436 437 static inline void 438 ohci_free_sed_locked(ohci_softc_t *sc, ohci_soft_ed_t *sed) 439 { 440 441 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 442 443 sed->next = sc->sc_freeeds; 444 sc->sc_freeeds = sed; 445 } 446 447 void 448 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 449 { 450 451 mutex_enter(&sc->sc_lock); 452 ohci_free_sed_locked(sc, sed); 453 mutex_exit(&sc->sc_lock); 454 } 455 456 ohci_soft_td_t * 457 ohci_alloc_std(ohci_softc_t *sc) 458 { 459 ohci_soft_td_t *std; 460 usbd_status err; 461 int i, offs; 462 usb_dma_t dma; 463 464 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 465 466 mutex_enter(&sc->sc_lock); 467 if (sc->sc_freetds == NULL) { 468 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 469 mutex_exit(&sc->sc_lock); 470 471 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 472 OHCI_TD_ALIGN, &dma); 473 if (err) 474 return NULL; 475 476 mutex_enter(&sc->sc_lock); 477 for (i = 0; i < OHCI_STD_CHUNK; i++) { 478 offs = i * OHCI_STD_SIZE; 479 std = KERNADDR(&dma, offs); 480 std->physaddr = DMAADDR(&dma, offs); 481 std->dma = dma; 482 std->offs = offs; 483 std->nexttd = sc->sc_freetds; 484 sc->sc_freetds = std; 485 } 486 } 487 488 std = sc->sc_freetds; 489 sc->sc_freetds = std->nexttd; 490 mutex_exit(&sc->sc_lock); 491 492 memset(&std->td, 0, sizeof(ohci_td_t)); 493 std->nexttd = NULL; 494 std->xfer = NULL; 495 496 return std; 497 } 498 499 void 500 ohci_free_std_locked(ohci_softc_t *sc, ohci_soft_td_t *std) 501 { 502 503 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 504 505 std->nexttd = sc->sc_freetds; 506 sc->sc_freetds = std; 507 } 508 509 void 510 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 511 { 512 513 mutex_enter(&sc->sc_lock); 514 ohci_free_std_locked(sc, std); 515 mutex_exit(&sc->sc_lock); 516 } 517 518 Static int 519 ohci_alloc_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, int length, int rd) 520 { 521 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 522 uint16_t flags = xfer->ux_flags; 523 524 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 525 526 DPRINTFN(8, "addr=%jd endpt=%jd len=%jd speed=%jd", 527 xfer->ux_pipe->up_dev->ud_addr, 528 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 529 length, xfer->ux_pipe->up_dev->ud_speed); 530 531 ASSERT_SLEEPABLE(); 532 KASSERT(length != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 533 534 size_t nstd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 535 nstd += ((length + OHCI_PAGE_SIZE - 1) / OHCI_PAGE_SIZE); 536 ox->ox_stds = kmem_zalloc(sizeof(ohci_soft_td_t *) * nstd, 537 KM_SLEEP); 538 ox->ox_nstd = nstd; 539 540 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, nstd, 0, 0); 541 542 for (size_t j = 0; j < ox->ox_nstd;) { 543 ohci_soft_td_t *cur = ohci_alloc_std(sc); 544 if (cur == NULL) 545 goto nomem; 546 547 ox->ox_stds[j++] = cur; 548 cur->xfer = xfer; 549 cur->flags = 0; 550 } 551 552 return 0; 553 554 nomem: 555 ohci_free_stds(sc, ox); 556 kmem_free(ox->ox_stds, sizeof(ohci_soft_td_t *) * nstd); 557 558 return ENOMEM; 559 } 560 561 Static void 562 ohci_free_stds(ohci_softc_t *sc, struct ohci_xfer *ox) 563 { 564 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 565 DPRINTF("ox=%#jx", (uintptr_t)ox, 0, 0, 0); 566 567 mutex_enter(&sc->sc_lock); 568 for (size_t i = 0; i < ox->ox_nstd; i++) { 569 ohci_soft_td_t *std = ox->ox_stds[i]; 570 if (std == NULL) 571 break; 572 ohci_free_std_locked(sc, std); 573 } 574 mutex_exit(&sc->sc_lock); 575 } 576 577 void 578 ohci_reset_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, 579 int alen, int rd, ohci_soft_td_t *sp, ohci_soft_td_t **ep) 580 { 581 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 582 ohci_soft_td_t *next, *cur; 583 int len, curlen; 584 usb_dma_t *dma = &xfer->ux_dmabuf; 585 uint16_t flags = xfer->ux_flags; 586 587 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 588 DPRINTF("start len=%jd", alen, 0, 0, 0); 589 590 KASSERT(mutex_owned(&sc->sc_lock)); 591 592 DPRINTFN(8, "addr=%jd endpt=%jd len=%jd speed=%jd", 593 xfer->ux_pipe->up_dev->ud_addr, 594 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 595 alen, xfer->ux_pipe->up_dev->ud_speed); 596 597 KASSERT(sp); 598 599 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 600 601 /* 602 * Assign next for the len == 0 case where we don't go through the 603 * main loop. 604 */ 605 len = alen; 606 cur = next = sp; 607 608 usb_syncmem(dma, 0, len, 609 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 610 const uint32_t tdflags = HTOO32( 611 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 612 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 613 614 size_t curoffs = 0; 615 for (size_t j = 1; len != 0;) { 616 if (j == ox->ox_nstd) 617 next = NULL; 618 else 619 next = ox->ox_stds[j++]; 620 KASSERT(next != cur); 621 622 curlen = 0; 623 const ohci_physaddr_t sdataphys = DMAADDR(dma, curoffs); 624 ohci_physaddr_t edataphys = DMAADDR(dma, curoffs + len - 1); 625 626 const ohci_physaddr_t sphyspg = OHCI_PAGE(sdataphys); 627 ohci_physaddr_t ephyspg = OHCI_PAGE(edataphys); 628 /* 629 * The OHCI hardware can handle at most one page 630 * crossing per TD 631 */ 632 curlen = len; 633 if (sphyspg != ephyspg && 634 sphyspg + OHCI_PAGE_SIZE != ephyspg) { 635 /* must use multiple TDs, fill as much as possible. */ 636 curlen = 2 * OHCI_PAGE_SIZE - 637 OHCI_PAGE_OFFSET(sdataphys); 638 /* the length must be a multiple of the max size */ 639 curlen -= curlen % mps; 640 edataphys = DMAADDR(dma, curoffs + curlen - 1); 641 } 642 KASSERT(curlen != 0); 643 DPRINTFN(4, "sdataphys=0x%08jx edataphys=0x%08jx " 644 "len=%jd curlen=%jd", sdataphys, edataphys, len, curlen); 645 646 cur->td.td_flags = tdflags; 647 cur->td.td_cbp = HTOO32(sdataphys); 648 cur->td.td_be = HTOO32(edataphys); 649 cur->td.td_nexttd = (next != NULL) ? HTOO32(next->physaddr) : 0; 650 cur->nexttd = next; 651 cur->len = curlen; 652 cur->flags = OHCI_ADD_LEN; 653 cur->xfer = xfer; 654 ohci_hash_add_td(sc, cur); 655 656 curoffs += curlen; 657 len -= curlen; 658 659 if (len != 0) { 660 KASSERT(next != NULL); 661 DPRINTFN(10, "extend chain", 0, 0, 0, 0); 662 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 663 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 664 665 cur = next; 666 } 667 } 668 cur->td.td_flags |= 669 HTOO32(xfer->ux_flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0); 670 671 if (!rd && 672 (flags & USBD_FORCE_SHORT_XFER) && 673 alen % mps == 0) { 674 /* We're adding a ZLP so sync the previous TD */ 675 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 676 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 677 678 /* Force a 0 length transfer at the end. */ 679 680 KASSERT(next != NULL); 681 cur = next; 682 683 cur->td.td_flags = tdflags; 684 cur->td.td_cbp = 0; /* indicate 0 length packet */ 685 cur->td.td_nexttd = 0; 686 cur->td.td_be = ~0; 687 cur->nexttd = NULL; 688 cur->len = 0; 689 cur->flags = 0; 690 cur->xfer = xfer; 691 ohci_hash_add_td(sc, cur); 692 693 DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0); 694 } 695 696 /* Last TD gets usb_syncmem'ed by caller */ 697 *ep = cur; 698 } 699 700 ohci_soft_itd_t * 701 ohci_alloc_sitd(ohci_softc_t *sc) 702 { 703 ohci_soft_itd_t *sitd; 704 usbd_status err; 705 int i, offs; 706 usb_dma_t dma; 707 708 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 709 710 mutex_enter(&sc->sc_lock); 711 if (sc->sc_freeitds == NULL) { 712 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 713 mutex_exit(&sc->sc_lock); 714 715 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 716 OHCI_ITD_ALIGN, &dma); 717 if (err) 718 return NULL; 719 mutex_enter(&sc->sc_lock); 720 for (i = 0; i < OHCI_SITD_CHUNK; i++) { 721 offs = i * OHCI_SITD_SIZE; 722 sitd = KERNADDR(&dma, offs); 723 sitd->physaddr = DMAADDR(&dma, offs); 724 sitd->dma = dma; 725 sitd->offs = offs; 726 sitd->nextitd = sc->sc_freeitds; 727 sc->sc_freeitds = sitd; 728 } 729 } 730 731 sitd = sc->sc_freeitds; 732 sc->sc_freeitds = sitd->nextitd; 733 mutex_exit(&sc->sc_lock); 734 735 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 736 sitd->nextitd = NULL; 737 sitd->xfer = NULL; 738 739 #ifdef DIAGNOSTIC 740 sitd->isdone = true; 741 #endif 742 743 return sitd; 744 } 745 746 Static void 747 ohci_free_sitd_locked(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 748 { 749 750 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 751 DPRINTFN(10, "sitd=%#jx", (uintptr_t)sitd, 0, 0, 0); 752 753 KASSERT(sitd->isdone); 754 #ifdef DIAGNOSTIC 755 /* Warn double free */ 756 sitd->isdone = false; 757 #endif 758 759 sitd->nextitd = sc->sc_freeitds; 760 sc->sc_freeitds = sitd; 761 } 762 763 void 764 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 765 { 766 767 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 768 769 mutex_enter(&sc->sc_lock); 770 ohci_free_sitd_locked(sc, sitd); 771 mutex_exit(&sc->sc_lock); 772 } 773 774 int 775 ohci_init(ohci_softc_t *sc) 776 { 777 ohci_soft_ed_t *sed, *psed; 778 usbd_status err; 779 int i; 780 uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */; 781 782 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 783 784 aprint_normal_dev(sc->sc_dev, ""); 785 786 sc->sc_hcca = NULL; 787 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 788 789 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 790 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 791 cv_init(&sc->sc_softwake_cv, "ohciab"); 792 793 sc->sc_rhsc_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 794 ohci_rhsc_softint, sc); 795 796 for (i = 0; i < OHCI_HASH_SIZE; i++) 797 LIST_INIT(&sc->sc_hash_tds[i]); 798 for (i = 0; i < OHCI_HASH_SIZE; i++) 799 LIST_INIT(&sc->sc_hash_itds[i]); 800 801 sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0, 802 "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL); 803 804 rev = OREAD4(sc, OHCI_REVISION); 805 aprint_normal("OHCI version %d.%d%s\n", 806 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 807 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 808 809 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 810 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 811 sc->sc_bus.ub_revision = USBREV_UNKNOWN; 812 return -1; 813 } 814 sc->sc_bus.ub_revision = USBREV_1_0; 815 sc->sc_bus.ub_usedma = true; 816 817 /* XXX determine alignment by R/W */ 818 /* Allocate the HCCA area. */ 819 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 820 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 821 if (err) { 822 sc->sc_hcca = NULL; 823 return err; 824 } 825 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 826 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 827 828 sc->sc_eintrs = OHCI_NORMAL_INTRS; 829 830 /* Allocate dummy ED that starts the control list. */ 831 sc->sc_ctrl_head = ohci_alloc_sed(sc); 832 if (sc->sc_ctrl_head == NULL) { 833 err = ENOMEM; 834 goto bad1; 835 } 836 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 837 838 /* Allocate dummy ED that starts the bulk list. */ 839 sc->sc_bulk_head = ohci_alloc_sed(sc); 840 if (sc->sc_bulk_head == NULL) { 841 err = ENOMEM; 842 goto bad2; 843 } 844 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 845 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 846 sizeof(sc->sc_bulk_head->ed), 847 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 848 849 /* Allocate dummy ED that starts the isochronous list. */ 850 sc->sc_isoc_head = ohci_alloc_sed(sc); 851 if (sc->sc_isoc_head == NULL) { 852 err = ENOMEM; 853 goto bad3; 854 } 855 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 856 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 857 sizeof(sc->sc_isoc_head->ed), 858 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 859 860 /* Allocate all the dummy EDs that make up the interrupt tree. */ 861 for (i = 0; i < OHCI_NO_EDS; i++) { 862 sed = ohci_alloc_sed(sc); 863 if (sed == NULL) { 864 while (--i >= 0) 865 ohci_free_sed(sc, sc->sc_eds[i]); 866 err = ENOMEM; 867 goto bad4; 868 } 869 /* All ED fields are set to 0. */ 870 sc->sc_eds[i] = sed; 871 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 872 if (i != 0) 873 psed = sc->sc_eds[(i-1) / 2]; 874 else 875 psed= sc->sc_isoc_head; 876 sed->next = psed; 877 sed->ed.ed_nexted = HTOO32(psed->physaddr); 878 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 879 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 880 } 881 /* 882 * Fill HCCA interrupt table. The bit reversal is to get 883 * the tree set up properly to spread the interrupts. 884 */ 885 for (i = 0; i < OHCI_NO_INTRS; i++) 886 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 887 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 888 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 889 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 890 891 #ifdef OHCI_DEBUG 892 DPRINTFN(15, "--- dump start ---", 0, 0, 0 ,0); 893 if (ohcidebug >= 15) { 894 for (i = 0; i < OHCI_NO_EDS; i++) { 895 DPRINTFN(15, "ed#%jd ", i, 0, 0, 0); 896 ohci_dump_ed(sc, sc->sc_eds[i]); 897 } 898 DPRINTFN(15, "iso", 0, 0, 0 ,0); 899 ohci_dump_ed(sc, sc->sc_isoc_head); 900 } 901 DPRINTFN(15, "--- dump end ---", 0, 0, 0 ,0); 902 #endif 903 904 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 905 ctl = OREAD4(sc, OHCI_CONTROL); 906 rwc = ctl & OHCI_RWC; 907 fm = OREAD4(sc, OHCI_FM_INTERVAL); 908 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 909 /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */ 910 911 /* Determine in what context we are running. */ 912 if (ctl & OHCI_IR) { 913 /* SMM active, request change */ 914 DPRINTF("SMM active, request owner change", 0, 0, 0, 0); 915 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 916 (OHCI_OC | OHCI_MIE)) 917 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 918 s = OREAD4(sc, OHCI_COMMAND_STATUS); 919 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 920 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 921 usb_delay_ms(&sc->sc_bus, 1); 922 ctl = OREAD4(sc, OHCI_CONTROL); 923 } 924 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 925 if ((ctl & OHCI_IR) == 0) { 926 aprint_error_dev(sc->sc_dev, 927 "SMM does not respond, resetting\n"); 928 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 929 goto reset; 930 } 931 #if 0 932 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 933 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 934 /* BIOS started controller. */ 935 DPRINTF("BIOS active", 0, 0, 0, 0); 936 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 937 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 938 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 939 } 940 #endif 941 } else { 942 DPRINTF("cold started", 0 ,0 ,0 ,0); 943 reset: 944 /* Controller was cold started. */ 945 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 946 } 947 948 /* 949 * This reset should not be necessary according to the OHCI spec, but 950 * without it some controllers do not start. 951 */ 952 DPRINTF("sc %#jx: resetting", (uintptr_t)sc, 0, 0, 0); 953 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 954 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 955 956 /* We now own the host controller and the bus has been reset. */ 957 958 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 959 /* Nominal time for a reset is 10 us. */ 960 for (i = 0; i < 10; i++) { 961 delay(10); 962 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 963 if (!hcr) 964 break; 965 } 966 if (hcr) { 967 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 968 err = EIO; 969 goto bad5; 970 } 971 #ifdef OHCI_DEBUG 972 if (ohcidebug >= 15) 973 ohci_dumpregs(sc); 974 #endif 975 976 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 977 978 /* Set up HC registers. */ 979 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 980 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 981 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 982 /* disable all interrupts and then switch on all desired interrupts */ 983 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 984 /* switch on desired functional features */ 985 ctl = OREAD4(sc, OHCI_CONTROL); 986 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 987 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 988 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 989 /* And finally start it! */ 990 OWRITE4(sc, OHCI_CONTROL, ctl); 991 992 /* 993 * The controller is now OPERATIONAL. Set a some final 994 * registers that should be set earlier, but that the 995 * controller ignores when in the SUSPEND state. 996 */ 997 ival = OHCI_GET_IVAL(fm); 998 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 999 fm |= OHCI_FSMPS(ival) | ival; 1000 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 1001 per = OHCI_PERIODIC(ival); /* 90% periodic */ 1002 OWRITE4(sc, OHCI_PERIODIC_START, per); 1003 1004 if (sc->sc_flags & OHCIF_SUPERIO) { 1005 /* no overcurrent protection */ 1006 desca |= OHCI_NOCP; 1007 /* 1008 * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning 1009 * that 1010 * - ports are always power switched 1011 * - don't wait for powered root hub port 1012 */ 1013 desca &= ~(__SHIFTIN(0xff, OHCI_POTPGT_MASK) | OHCI_NPS); 1014 } 1015 1016 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 1017 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 1018 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 1019 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 1020 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 1021 1022 /* 1023 * The AMD756 requires a delay before re-reading the register, 1024 * otherwise it will occasionally report 0 ports. 1025 */ 1026 sc->sc_noport = 0; 1027 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 1028 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 1029 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 1030 } 1031 1032 #ifdef OHCI_DEBUG 1033 if (ohcidebug >= 5) 1034 ohci_dumpregs(sc); 1035 #endif 1036 1037 /* Set up the bus struct. */ 1038 sc->sc_bus.ub_methods = &ohci_bus_methods; 1039 sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe); 1040 1041 sc->sc_control = sc->sc_intre = 0; 1042 1043 /* Finally, turn on interrupts. */ 1044 DPRINTF("enabling %#jx", sc->sc_eintrs | OHCI_MIE, 0, 0, 0); 1045 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 1046 1047 return 0; 1048 1049 bad5: 1050 for (i = 0; i < OHCI_NO_EDS; i++) 1051 ohci_free_sed(sc, sc->sc_eds[i]); 1052 bad4: 1053 ohci_free_sed(sc, sc->sc_isoc_head); 1054 bad3: 1055 ohci_free_sed(sc, sc->sc_bulk_head); 1056 bad2: 1057 ohci_free_sed(sc, sc->sc_ctrl_head); 1058 bad1: 1059 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 1060 sc->sc_hcca = NULL; 1061 return err; 1062 } 1063 1064 struct usbd_xfer * 1065 ohci_allocx(struct usbd_bus *bus, unsigned int nframes) 1066 { 1067 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1068 struct usbd_xfer *xfer; 1069 1070 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 1071 if (xfer != NULL) { 1072 memset(xfer, 0, sizeof(struct ohci_xfer)); 1073 #ifdef DIAGNOSTIC 1074 xfer->ux_state = XFER_BUSY; 1075 #endif 1076 } 1077 return xfer; 1078 } 1079 1080 void 1081 ohci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1082 { 1083 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1084 1085 KASSERTMSG(xfer->ux_state == XFER_BUSY, 1086 "xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state); 1087 #ifdef DIAGNOSTIC 1088 xfer->ux_state = XFER_FREE; 1089 #endif 1090 pool_cache_put(sc->sc_xferpool, xfer); 1091 } 1092 1093 Static void 1094 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1095 { 1096 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1097 1098 *lock = &sc->sc_lock; 1099 } 1100 1101 /* 1102 * Shut down the controller when the system is going down. 1103 */ 1104 bool 1105 ohci_shutdown(device_t self, int flags) 1106 { 1107 ohci_softc_t *sc = device_private(self); 1108 1109 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1110 1111 DPRINTF("stopping the HC", 0, 0, 0, 0); 1112 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 1113 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1114 return true; 1115 } 1116 1117 bool 1118 ohci_resume(device_t dv, const pmf_qual_t *qual) 1119 { 1120 ohci_softc_t *sc = device_private(dv); 1121 uint32_t ctl; 1122 1123 mutex_spin_enter(&sc->sc_intr_lock); 1124 sc->sc_bus.ub_usepolling++; 1125 mutex_spin_exit(&sc->sc_intr_lock); 1126 1127 /* Some broken BIOSes do not recover these values */ 1128 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1129 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1130 sc->sc_ctrl_head->physaddr); 1131 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1132 sc->sc_bulk_head->physaddr); 1133 if (sc->sc_intre) 1134 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1135 (OHCI_ALL_INTRS | OHCI_MIE)); 1136 if (sc->sc_control) 1137 ctl = sc->sc_control; 1138 else 1139 ctl = OREAD4(sc, OHCI_CONTROL); 1140 ctl |= OHCI_HCFS_RESUME; 1141 OWRITE4(sc, OHCI_CONTROL, ctl); 1142 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1143 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1144 OWRITE4(sc, OHCI_CONTROL, ctl); 1145 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1146 sc->sc_control = sc->sc_intre = 0; 1147 1148 mutex_spin_enter(&sc->sc_intr_lock); 1149 sc->sc_bus.ub_usepolling--; 1150 mutex_spin_exit(&sc->sc_intr_lock); 1151 1152 return true; 1153 } 1154 1155 bool 1156 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1157 { 1158 ohci_softc_t *sc = device_private(dv); 1159 uint32_t ctl; 1160 1161 mutex_spin_enter(&sc->sc_intr_lock); 1162 sc->sc_bus.ub_usepolling++; 1163 mutex_spin_exit(&sc->sc_intr_lock); 1164 1165 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1166 if (sc->sc_control == 0) { 1167 /* 1168 * Preserve register values, in case that BIOS 1169 * does not recover them. 1170 */ 1171 sc->sc_control = ctl; 1172 sc->sc_intre = OREAD4(sc, 1173 OHCI_INTERRUPT_ENABLE); 1174 } 1175 ctl |= OHCI_HCFS_SUSPEND; 1176 OWRITE4(sc, OHCI_CONTROL, ctl); 1177 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1178 1179 mutex_spin_enter(&sc->sc_intr_lock); 1180 sc->sc_bus.ub_usepolling--; 1181 mutex_spin_exit(&sc->sc_intr_lock); 1182 1183 return true; 1184 } 1185 1186 #ifdef OHCI_DEBUG 1187 void 1188 ohci_dumpregs(ohci_softc_t *sc) 1189 { 1190 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1191 1192 DPRINTF("rev=0x%08jx control=0x%08jx command=0x%08jx", 1193 OREAD4(sc, OHCI_REVISION), 1194 OREAD4(sc, OHCI_CONTROL), 1195 OREAD4(sc, OHCI_COMMAND_STATUS), 0); 1196 DPRINTF(" intrstat=0x%08jx intre=0x%08jx intrd=0x%08jx", 1197 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1198 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1199 OREAD4(sc, OHCI_INTERRUPT_DISABLE), 0); 1200 DPRINTF(" hcca=0x%08jx percur=0x%08jx ctrlhd=0x%08jx", 1201 OREAD4(sc, OHCI_HCCA), 1202 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1203 OREAD4(sc, OHCI_CONTROL_HEAD_ED), 0); 1204 DPRINTF(" ctrlcur=0x%08jx bulkhd=0x%08jx bulkcur=0x%08jx", 1205 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1206 OREAD4(sc, OHCI_BULK_HEAD_ED), 1207 OREAD4(sc, OHCI_BULK_CURRENT_ED) ,0); 1208 DPRINTF(" done=0x%08jx fmival=0x%08jx fmrem=0x%08jx", 1209 OREAD4(sc, OHCI_DONE_HEAD), 1210 OREAD4(sc, OHCI_FM_INTERVAL), 1211 OREAD4(sc, OHCI_FM_REMAINING), 0); 1212 DPRINTF(" fmnum=0x%08jx perst=0x%08jx lsthrs=0x%08jx", 1213 OREAD4(sc, OHCI_FM_NUMBER), 1214 OREAD4(sc, OHCI_PERIODIC_START), 1215 OREAD4(sc, OHCI_LS_THRESHOLD), 0); 1216 DPRINTF(" desca=0x%08jx descb=0x%08jx stat=0x%08jx", 1217 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1218 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1219 OREAD4(sc, OHCI_RH_STATUS), 0); 1220 DPRINTF(" port1=0x%08jx port2=0x%08jx", 1221 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1222 OREAD4(sc, OHCI_RH_PORT_STATUS(2)), 0, 0); 1223 DPRINTF(" HCCA: frame_number=0x%04jx done_head=0x%08jx", 1224 O32TOH(sc->sc_hcca->hcca_frame_number), 1225 O32TOH(sc->sc_hcca->hcca_done_head), 0, 0); 1226 } 1227 #endif 1228 1229 Static int ohci_intr1(ohci_softc_t *); 1230 1231 int 1232 ohci_intr(void *p) 1233 { 1234 ohci_softc_t *sc = p; 1235 int ret = 0; 1236 1237 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1238 1239 if (sc == NULL) 1240 return 0; 1241 1242 mutex_spin_enter(&sc->sc_intr_lock); 1243 1244 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1245 goto done; 1246 1247 /* If we get an interrupt while polling, then just ignore it. */ 1248 if (sc->sc_bus.ub_usepolling) { 1249 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1250 /* for level triggered intrs, should do something to ack */ 1251 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1252 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1253 1254 goto done; 1255 } 1256 1257 ret = ohci_intr1(sc); 1258 1259 done: 1260 mutex_spin_exit(&sc->sc_intr_lock); 1261 return ret; 1262 } 1263 1264 Static int 1265 ohci_intr1(ohci_softc_t *sc) 1266 { 1267 uint32_t intrs, eintrs; 1268 1269 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1270 1271 /* In case the interrupt occurs before initialization has completed. */ 1272 if (sc == NULL || sc->sc_hcca == NULL) { 1273 #ifdef DIAGNOSTIC 1274 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1275 #endif 1276 return 0; 1277 } 1278 1279 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1280 1281 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1282 if (!intrs) 1283 return 0; 1284 1285 /* Acknowledge */ 1286 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); 1287 eintrs = intrs & sc->sc_eintrs; 1288 DPRINTFN(7, "sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1289 DPRINTFN(7, "intrs=%#jx(%#jx) eintrs=%#jx(%#jx)", 1290 intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), eintrs, 1291 sc->sc_eintrs); 1292 1293 if (!eintrs) { 1294 return 0; 1295 } 1296 1297 if (eintrs & OHCI_SO) { 1298 sc->sc_overrun_cnt++; 1299 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1300 printf("%s: %u scheduling overruns\n", 1301 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1302 sc->sc_overrun_cnt = 0; 1303 } 1304 /* XXX do what */ 1305 eintrs &= ~OHCI_SO; 1306 } 1307 if (eintrs & OHCI_WDH) { 1308 /* 1309 * We block the interrupt below, and reenable it later from 1310 * ohci_softintr(). 1311 */ 1312 usb_schedsoftintr(&sc->sc_bus); 1313 } 1314 if (eintrs & OHCI_RD) { 1315 DPRINTFN(5, "resume detect sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1316 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1317 /* XXX process resume detect */ 1318 } 1319 if (eintrs & OHCI_UE) { 1320 DPRINTFN(5, "unrecoverable error sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1321 printf("%s: unrecoverable error, controller halted\n", 1322 device_xname(sc->sc_dev)); 1323 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1324 /* XXX what else */ 1325 } 1326 if (eintrs & OHCI_RHSC) { 1327 /* 1328 * We block the interrupt below, and reenable it later from 1329 * a timeout. 1330 */ 1331 softint_schedule(sc->sc_rhsc_si); 1332 } 1333 1334 if (eintrs != 0) { 1335 /* Block unprocessed interrupts. */ 1336 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1337 sc->sc_eintrs &= ~eintrs; 1338 DPRINTF("sc %#jx blocking intrs 0x%jx", (uintptr_t)sc, 1339 eintrs, 0, 0); 1340 } 1341 1342 return 1; 1343 } 1344 1345 void 1346 ohci_rhsc_enable(void *v_sc) 1347 { 1348 ohci_softc_t *sc = v_sc; 1349 1350 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1351 DPRINTF("sc %#jx", (uintptr_t)sc, 0, 0, 0); 1352 mutex_spin_enter(&sc->sc_intr_lock); 1353 sc->sc_eintrs |= OHCI_RHSC; 1354 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1355 mutex_spin_exit(&sc->sc_intr_lock); 1356 } 1357 1358 #ifdef OHCI_DEBUG 1359 const char *ohci_cc_strs[] = { 1360 "NO_ERROR", 1361 "CRC", 1362 "BIT_STUFFING", 1363 "DATA_TOGGLE_MISMATCH", 1364 "STALL", 1365 "DEVICE_NOT_RESPONDING", 1366 "PID_CHECK_FAILURE", 1367 "UNEXPECTED_PID", 1368 "DATA_OVERRUN", 1369 "DATA_UNDERRUN", 1370 "BUFFER_OVERRUN", 1371 "BUFFER_UNDERRUN", 1372 "reserved", 1373 "reserved", 1374 "NOT_ACCESSED", 1375 "NOT_ACCESSED", 1376 }; 1377 #endif 1378 1379 void 1380 ohci_softintr(void *v) 1381 { 1382 struct usbd_bus *bus = v; 1383 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1384 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1385 ohci_soft_td_t *std, *sdone, *stdnext; 1386 struct usbd_xfer *xfer; 1387 struct ohci_pipe *opipe; 1388 int len, cc; 1389 int i, j, actlen, iframes, uedir; 1390 ohci_physaddr_t done; 1391 1392 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1393 1394 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1395 1396 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1397 sizeof(sc->sc_hcca->hcca_done_head), 1398 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1399 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1400 sc->sc_hcca->hcca_done_head = 0; 1401 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1402 sizeof(sc->sc_hcca->hcca_done_head), 1403 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1404 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1405 sc->sc_eintrs |= OHCI_WDH; 1406 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1407 1408 /* Reverse the done list. */ 1409 for (sdone = NULL, sidone = NULL; done != 0; ) { 1410 std = ohci_hash_find_td(sc, done); 1411 if (std != NULL) { 1412 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1413 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1414 std->dnext = sdone; 1415 done = O32TOH(std->td.td_nexttd); 1416 sdone = std; 1417 DPRINTFN(10, "add TD %#jx", (uintptr_t)std, 0, 0, 0); 1418 continue; 1419 } 1420 sitd = ohci_hash_find_itd(sc, done); 1421 if (sitd != NULL) { 1422 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1423 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1424 sitd->dnext = sidone; 1425 done = O32TOH(sitd->itd.itd_nextitd); 1426 sidone = sitd; 1427 DPRINTFN(5, "add ITD %#jx", (uintptr_t)sitd, 0, 0, 0); 1428 continue; 1429 } 1430 DPRINTFN(10, "addr %#jx not found", (uintptr_t)done, 0, 0, 0); 1431 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1432 (u_long)done); 1433 break; 1434 } 1435 1436 DPRINTFN(10, "sdone=%#jx sidone=%#jx", (uintptr_t)sdone, 1437 (uintptr_t)sidone, 0, 0); 1438 DPRINTFN(10, "--- TD dump start ---", 0, 0, 0, 0); 1439 #ifdef OHCI_DEBUG 1440 if (ohcidebug >= 10) { 1441 for (std = sdone; std; std = std->dnext) 1442 ohci_dump_td(sc, std); 1443 } 1444 #endif 1445 DPRINTFN(10, "--- TD dump end ---", 0, 0, 0, 0); 1446 1447 for (std = sdone; std; std = stdnext) { 1448 xfer = std->xfer; 1449 stdnext = std->dnext; 1450 DPRINTFN(10, "std=%#jx xfer=%#jx hcpriv=%#jx", (uintptr_t)std, 1451 (uintptr_t)xfer, (uintptr_t)(xfer ? xfer->ux_hcpriv : 0), 1452 0); 1453 if (xfer == NULL) { 1454 /* 1455 * xfer == NULL: There seems to be no xfer associated 1456 * with this TD. It is tailp that happened to end up on 1457 * the done queue. 1458 * Shouldn't happen, but some chips are broken(?). 1459 */ 1460 continue; 1461 } 1462 if (xfer->ux_status == USBD_CANCELLED || 1463 xfer->ux_status == USBD_TIMEOUT) { 1464 DPRINTF("cancel/timeout %#jx", (uintptr_t)xfer, 0, 0, 1465 0); 1466 /* Handled by abort routine. */ 1467 continue; 1468 } 1469 callout_stop(&xfer->ux_callout); 1470 1471 len = std->len; 1472 if (std->td.td_cbp != 0) 1473 len -= O32TOH(std->td.td_be) - 1474 O32TOH(std->td.td_cbp) + 1; 1475 DPRINTFN(10, "len=%jd, flags=0x%jx", len, std->flags, 0, 0); 1476 if (std->flags & OHCI_ADD_LEN) 1477 xfer->ux_actlen += len; 1478 1479 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1480 if (cc == OHCI_CC_NO_ERROR) { 1481 ohci_hash_rem_td(sc, std); 1482 if (std->flags & OHCI_CALL_DONE) { 1483 xfer->ux_status = USBD_NORMAL_COMPLETION; 1484 usb_transfer_complete(xfer); 1485 } 1486 } else { 1487 /* 1488 * Endpoint is halted. First unlink all the TDs 1489 * belonging to the failed transfer, and then restart 1490 * the endpoint. 1491 */ 1492 ohci_soft_td_t *p, *n; 1493 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1494 1495 DPRINTFN(10, "error cc=%jd", cc, 0, 0, 0); 1496 1497 /* remove xfer's TDs from the hash */ 1498 for (p = std; p->xfer == xfer; p = n) { 1499 n = p->nexttd; 1500 ohci_hash_rem_td(sc, p); 1501 } 1502 1503 ohci_soft_ed_t *sed = opipe->sed; 1504 1505 /* clear halt and TD chain */ 1506 sed->ed.ed_headp = HTOO32(p->physaddr); 1507 usb_syncmem(&sed->dma, 1508 sed->offs + offsetof(ohci_ed_t, ed_headp), 1509 sizeof(sed->ed.ed_headp), 1510 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1511 1512 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1513 1514 if (cc == OHCI_CC_DATA_UNDERRUN) 1515 xfer->ux_status = USBD_NORMAL_COMPLETION; 1516 else if (cc == OHCI_CC_STALL) 1517 xfer->ux_status = USBD_STALLED; 1518 else 1519 xfer->ux_status = USBD_IOERROR; 1520 usb_transfer_complete(xfer); 1521 } 1522 } 1523 DPRINTFN(10, "--- ITD dump start ---", 0, 0, 0, 0); 1524 #ifdef OHCI_DEBUG 1525 if (ohcidebug >= 10) { 1526 for (sitd = sidone; sitd; sitd = sitd->dnext) 1527 ohci_dump_itd(sc, sitd); 1528 } 1529 #endif 1530 DPRINTFN(10, "--- ITD dump end ---", 0, 0, 0, 0); 1531 1532 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1533 xfer = sitd->xfer; 1534 sitdnext = sitd->dnext; 1535 DPRINTFN(1, "sitd=%#jx xfer=%#jx hcpriv=%#jx", (uintptr_t)sitd, 1536 (uintptr_t)xfer, (uintptr_t)(xfer ? xfer->ux_hcpriv : 0), 1537 0); 1538 if (xfer == NULL) 1539 continue; 1540 if (xfer->ux_status == USBD_CANCELLED || 1541 xfer->ux_status == USBD_TIMEOUT) { 1542 DPRINTF("cancel/timeout %#jx", 1543 (uintptr_t)xfer, 0, 0, 0); 1544 /* Handled by abort routine. */ 1545 continue; 1546 } 1547 KASSERT(!sitd->isdone); 1548 #ifdef DIAGNOSTIC 1549 sitd->isdone = true; 1550 #endif 1551 if (sitd->flags & OHCI_CALL_DONE) { 1552 ohci_soft_itd_t *next; 1553 1554 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1555 opipe->isoc.inuse -= xfer->ux_nframes; 1556 uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc-> 1557 bEndpointAddress); 1558 xfer->ux_status = USBD_NORMAL_COMPLETION; 1559 actlen = 0; 1560 for (i = 0, sitd = xfer->ux_hcpriv;; 1561 sitd = next) { 1562 next = sitd->nextitd; 1563 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1564 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1565 xfer->ux_status = USBD_IOERROR; 1566 /* For input, update frlengths with actual */ 1567 /* XXX anything necessary for output? */ 1568 if (uedir == UE_DIR_IN && 1569 xfer->ux_status == USBD_NORMAL_COMPLETION) { 1570 iframes = OHCI_ITD_GET_FC(O32TOH( 1571 sitd->itd.itd_flags)); 1572 for (j = 0; j < iframes; i++, j++) { 1573 len = O16TOH(sitd-> 1574 itd.itd_offset[j]); 1575 if ((OHCI_ITD_PSW_GET_CC(len) & 1576 OHCI_CC_NOT_ACCESSED_MASK) 1577 == OHCI_CC_NOT_ACCESSED) 1578 len = 0; 1579 else 1580 len = OHCI_ITD_PSW_LENGTH(len); 1581 xfer->ux_frlengths[i] = len; 1582 actlen += len; 1583 } 1584 } 1585 if (sitd->flags & OHCI_CALL_DONE) 1586 break; 1587 ohci_hash_rem_itd(sc, sitd); 1588 1589 } 1590 ohci_hash_rem_itd(sc, sitd); 1591 if (uedir == UE_DIR_IN && 1592 xfer->ux_status == USBD_NORMAL_COMPLETION) 1593 xfer->ux_actlen = actlen; 1594 xfer->ux_hcpriv = NULL; 1595 1596 usb_transfer_complete(xfer); 1597 } 1598 } 1599 1600 if (sc->sc_softwake) { 1601 sc->sc_softwake = 0; 1602 cv_broadcast(&sc->sc_softwake_cv); 1603 } 1604 1605 DPRINTFN(10, "done", 0, 0, 0, 0); 1606 } 1607 1608 void 1609 ohci_device_ctrl_done(struct usbd_xfer *xfer) 1610 { 1611 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1612 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1613 int len = UGETW(xfer->ux_request.wLength); 1614 int isread = (xfer->ux_request.bmRequestType & UT_READ); 1615 1616 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1617 DPRINTFN(10, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 1618 1619 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1620 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 1621 1622 if (len) 1623 usb_syncmem(&xfer->ux_dmabuf, 0, len, 1624 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1625 usb_syncmem(&opipe->ctrl.reqdma, 0, 1626 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1627 } 1628 1629 void 1630 ohci_device_intr_done(struct usbd_xfer *xfer) 1631 { 1632 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1633 int isread = 1634 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1635 1636 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1637 DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, 1638 xfer->ux_actlen, 0, 0); 1639 1640 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1641 1642 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1643 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1644 } 1645 1646 void 1647 ohci_device_bulk_done(struct usbd_xfer *xfer) 1648 { 1649 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1650 1651 int isread = 1652 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1653 1654 KASSERT(mutex_owned(&sc->sc_lock)); 1655 1656 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1657 DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 1658 0, 0); 1659 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1660 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1661 } 1662 1663 Static void 1664 ohci_rhsc_softint(void *arg) 1665 { 1666 ohci_softc_t *sc = arg; 1667 1668 mutex_enter(&sc->sc_lock); 1669 1670 ohci_rhsc(sc, sc->sc_intrxfer); 1671 1672 /* Do not allow RHSC interrupts > 1 per second */ 1673 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1674 1675 mutex_exit(&sc->sc_lock); 1676 } 1677 1678 void 1679 ohci_rhsc(ohci_softc_t *sc, struct usbd_xfer *xfer) 1680 { 1681 u_char *p; 1682 int i, m; 1683 int hstatus __unused; 1684 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1685 1686 KASSERT(mutex_owned(&sc->sc_lock)); 1687 1688 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1689 DPRINTF("sc=%#jx xfer=%#jx hstatus=0x%08jx", (uintptr_t)sc, 1690 (uintptr_t)xfer, hstatus, 0); 1691 1692 if (xfer == NULL) { 1693 /* Just ignore the change. */ 1694 return; 1695 } 1696 1697 p = xfer->ux_buf; 1698 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 1699 memset(p, 0, xfer->ux_length); 1700 for (i = 1; i <= m; i++) { 1701 /* Pick out CHANGE bits from the status reg. */ 1702 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1703 p[i/8] |= 1 << (i%8); 1704 } 1705 DPRINTF("change=0x%02jx", *p, 0, 0, 0); 1706 xfer->ux_actlen = xfer->ux_length; 1707 xfer->ux_status = USBD_NORMAL_COMPLETION; 1708 1709 usb_transfer_complete(xfer); 1710 } 1711 1712 void 1713 ohci_root_intr_done(struct usbd_xfer *xfer) 1714 { 1715 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1716 1717 KASSERT(mutex_owned(&sc->sc_lock)); 1718 1719 KASSERT(sc->sc_intrxfer == xfer); 1720 sc->sc_intrxfer = NULL; 1721 } 1722 1723 void 1724 ohci_poll(struct usbd_bus *bus) 1725 { 1726 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1727 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1728 1729 #ifdef OHCI_DEBUG 1730 static int last; 1731 int new; 1732 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1733 if (new != last) { 1734 DPRINTFN(10, "intrs=0x%04jx", new, 0, 0, 0); 1735 last = new; 1736 } 1737 #endif 1738 sc->sc_eintrs |= OHCI_WDH; 1739 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1740 mutex_spin_enter(&sc->sc_intr_lock); 1741 ohci_intr1(sc); 1742 mutex_spin_exit(&sc->sc_intr_lock); 1743 } 1744 } 1745 1746 /* 1747 * Add an ED to the schedule. Called with USB lock held. 1748 */ 1749 Static void 1750 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1751 { 1752 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1753 DPRINTFN(8, "sed=%#jx head=%#jx", (uintptr_t)sed, (uintptr_t)head, 0, 1754 0); 1755 1756 KASSERT(mutex_owned(&sc->sc_lock)); 1757 1758 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1759 sizeof(head->ed.ed_nexted), 1760 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1761 sed->next = head->next; 1762 sed->ed.ed_nexted = head->ed.ed_nexted; 1763 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1764 sizeof(sed->ed.ed_nexted), 1765 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1766 head->next = sed; 1767 head->ed.ed_nexted = HTOO32(sed->physaddr); 1768 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1769 sizeof(head->ed.ed_nexted), 1770 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1771 } 1772 1773 /* 1774 * Remove an ED from the schedule. Called with USB lock held. 1775 */ 1776 Static void 1777 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1778 { 1779 ohci_soft_ed_t *p; 1780 1781 KASSERT(mutex_owned(&sc->sc_lock)); 1782 1783 /* XXX */ 1784 for (p = head; p != NULL && p->next != sed; p = p->next) 1785 ; 1786 KASSERT(p != NULL); 1787 1788 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1789 sizeof(sed->ed.ed_nexted), 1790 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1791 p->next = sed->next; 1792 p->ed.ed_nexted = sed->ed.ed_nexted; 1793 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1794 sizeof(p->ed.ed_nexted), 1795 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1796 } 1797 1798 /* 1799 * When a transfer is completed the TD is added to the done queue by 1800 * the host controller. This queue is the processed by software. 1801 * Unfortunately the queue contains the physical address of the TD 1802 * and we have no simple way to translate this back to a kernel address. 1803 * To make the translation possible (and fast) we use a hash table of 1804 * TDs currently in the schedule. The physical address is used as the 1805 * hash value. 1806 */ 1807 1808 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1809 /* Called with USB lock held. */ 1810 void 1811 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1812 { 1813 int h = HASH(std->physaddr); 1814 1815 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1816 1817 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1818 } 1819 1820 /* Called with USB lock held. */ 1821 void 1822 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1823 { 1824 1825 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1826 1827 LIST_REMOVE(std, hnext); 1828 } 1829 1830 ohci_soft_td_t * 1831 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1832 { 1833 int h = HASH(a); 1834 ohci_soft_td_t *std; 1835 1836 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1837 std != NULL; 1838 std = LIST_NEXT(std, hnext)) 1839 if (std->physaddr == a) 1840 return std; 1841 return NULL; 1842 } 1843 1844 /* Called with USB lock held. */ 1845 void 1846 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1847 { 1848 int h = HASH(sitd->physaddr); 1849 1850 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1851 1852 KASSERT(mutex_owned(&sc->sc_lock)); 1853 1854 DPRINTFN(10, "sitd=%#jx physaddr=0x%08jx", 1855 (uintptr_t)sitd, (u_long)sitd->physaddr, 0, 0); 1856 1857 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1858 } 1859 1860 /* Called with USB lock held. */ 1861 void 1862 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1863 { 1864 1865 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1866 1867 KASSERT(mutex_owned(&sc->sc_lock)); 1868 1869 DPRINTFN(10, "sitd=%#jx physaddr=0x%08jx", (uintptr_t)sitd, 1870 sitd->physaddr, 0, 0); 1871 1872 LIST_REMOVE(sitd, hnext); 1873 } 1874 1875 ohci_soft_itd_t * 1876 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1877 { 1878 int h = HASH(a); 1879 ohci_soft_itd_t *sitd; 1880 1881 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1882 sitd != NULL; 1883 sitd = LIST_NEXT(sitd, hnext)) 1884 if (sitd->physaddr == a) 1885 return sitd; 1886 return NULL; 1887 } 1888 1889 void 1890 ohci_timeout(void *addr) 1891 { 1892 struct usbd_xfer *xfer = addr; 1893 struct ohci_xfer *oxfer = OHCI_XFER2OXFER(xfer); 1894 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1895 1896 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1897 DPRINTF("oxfer=%#jx", (uintptr_t)oxfer, 0, 0, 0); 1898 1899 if (sc->sc_dying) { 1900 mutex_enter(&sc->sc_lock); 1901 ohci_abort_xfer(xfer, USBD_TIMEOUT); 1902 mutex_exit(&sc->sc_lock); 1903 return; 1904 } 1905 1906 /* Execute the abort in a process context. */ 1907 usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr, 1908 USB_TASKQ_MPSAFE); 1909 usb_add_task(xfer->ux_pipe->up_dev, &oxfer->abort_task, 1910 USB_TASKQ_HC); 1911 } 1912 1913 void 1914 ohci_timeout_task(void *addr) 1915 { 1916 struct usbd_xfer *xfer = addr; 1917 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1918 1919 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1920 1921 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 1922 1923 mutex_enter(&sc->sc_lock); 1924 ohci_abort_xfer(xfer, USBD_TIMEOUT); 1925 mutex_exit(&sc->sc_lock); 1926 } 1927 1928 #ifdef OHCI_DEBUG 1929 void 1930 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 1931 { 1932 for (; std; std = std->nexttd) { 1933 ohci_dump_td(sc, std); 1934 KASSERTMSG(std->nexttd == NULL || std != std->nexttd, 1935 "std %p next %p", std, std->nexttd); 1936 } 1937 } 1938 1939 void 1940 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1941 { 1942 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1943 1944 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1945 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1946 1947 uint32_t flags = O32TOH(std->td.td_flags); 1948 DPRINTF("TD(%#jx) at 0x%08jx:", (uintptr_t)std, std->physaddr, 0, 0); 1949 DPRINTF(" round=%jd DP=%jx DI=%jx T=%jx", 1950 !!(flags & OHCI_TD_R), 1951 __SHIFTOUT(flags, OHCI_TD_DP_MASK), 1952 OHCI_TD_GET_DI(flags), 1953 __SHIFTOUT(flags, OHCI_TD_TOGGLE_MASK)); 1954 DPRINTF(" EC=%jd CC=%jd", OHCI_TD_GET_EC(flags), 1955 OHCI_TD_GET_CC(flags), 0, 0); 1956 DPRINTF(" td_cbp=0x%08jx td_nexttd=0x%08jx td_be=0x%08jx", 1957 (u_long)O32TOH(std->td.td_cbp), 1958 (u_long)O32TOH(std->td.td_nexttd), 1959 (u_long)O32TOH(std->td.td_be), 0); 1960 } 1961 1962 void 1963 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1964 { 1965 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1966 1967 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1968 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1969 1970 uint32_t flags = O32TOH(sitd->itd.itd_flags); 1971 DPRINTF("ITD(%#jx) at 0x%08jx", (uintptr_t)sitd, sitd->physaddr, 0, 0); 1972 DPRINTF(" sf=%jd di=%jd fc=%jd cc=%jd", 1973 OHCI_ITD_GET_SF(flags), OHCI_ITD_GET_DI(flags), 1974 OHCI_ITD_GET_FC(flags), OHCI_ITD_GET_CC(flags)); 1975 DPRINTF(" bp0=0x%08jx next=0x%08jx be=0x%08jx", 1976 O32TOH(sitd->itd.itd_bp0), 1977 O32TOH(sitd->itd.itd_nextitd), 1978 O32TOH(sitd->itd.itd_be), 0); 1979 CTASSERT(OHCI_ITD_NOFFSET == 8); 1980 DPRINTF(" offs[0] = 0x%04jx offs[1] = 0x%04jx " 1981 "offs[2] = 0x%04jx offs[3] = 0x%04jx", 1982 O16TOH(sitd->itd.itd_offset[0]), 1983 O16TOH(sitd->itd.itd_offset[1]), 1984 O16TOH(sitd->itd.itd_offset[2]), 1985 O16TOH(sitd->itd.itd_offset[3])); 1986 DPRINTF(" offs[4] = 0x%04jx offs[5] = 0x%04jx " 1987 "offs[6] = 0x%04jx offs[7] = 0x%04jx", 1988 O16TOH(sitd->itd.itd_offset[4]), 1989 O16TOH(sitd->itd.itd_offset[5]), 1990 O16TOH(sitd->itd.itd_offset[6]), 1991 O16TOH(sitd->itd.itd_offset[7])); 1992 } 1993 1994 void 1995 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1996 { 1997 for (; sitd; sitd = sitd->nextitd) 1998 ohci_dump_itd(sc, sitd); 1999 } 2000 2001 void 2002 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2003 { 2004 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2005 2006 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2007 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2008 2009 uint32_t flags = O32TOH(sed->ed.ed_flags); 2010 DPRINTF("ED(%#jx) at 0x%08jx:", (uintptr_t)sed, sed->physaddr, 0, 0); 2011 DPRINTF(" addr=%jd endpt=%jd maxp=%jd", 2012 OHCI_ED_GET_FA(flags), 2013 OHCI_ED_GET_EN(flags), 2014 OHCI_ED_GET_MAXP(flags), 2015 0); 2016 DPRINTF(" dir=%jd speed=%jd skip=%jd iso=%jd", 2017 __SHIFTOUT(flags, OHCI_ED_DIR_MASK), 2018 !!(flags & OHCI_ED_SPEED), 2019 !!(flags & OHCI_ED_SKIP), 2020 !!(flags & OHCI_ED_FORMAT_ISO)); 2021 DPRINTF(" tailp=0x%08jx", (u_long)O32TOH(sed->ed.ed_tailp), 2022 0, 0, 0); 2023 DPRINTF(" headp=0x%08jx nexted=0x%08jx halted=%jd carry=%jd", 2024 O32TOH(sed->ed.ed_headp), O32TOH(sed->ed.ed_nexted), 2025 !!(O32TOH(sed->ed.ed_headp) & OHCI_HALTED), 2026 !!(O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 2027 } 2028 #endif 2029 2030 usbd_status 2031 ohci_open(struct usbd_pipe *pipe) 2032 { 2033 struct usbd_device *dev = pipe->up_dev; 2034 struct usbd_bus *bus = dev->ud_bus; 2035 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2036 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 2037 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2038 uint8_t addr = dev->ud_addr; 2039 uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2040 ohci_soft_ed_t *sed; 2041 ohci_soft_td_t *std; 2042 ohci_soft_itd_t *sitd; 2043 ohci_physaddr_t tdphys; 2044 uint32_t fmt; 2045 usbd_status err = USBD_NOMEM; 2046 int ival; 2047 2048 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2049 DPRINTFN(1, "pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, 2050 addr, ed->bEndpointAddress, bus->ub_rhaddr); 2051 2052 if (sc->sc_dying) { 2053 return USBD_IOERROR; 2054 } 2055 2056 std = NULL; 2057 sed = NULL; 2058 2059 if (addr == bus->ub_rhaddr) { 2060 switch (ed->bEndpointAddress) { 2061 case USB_CONTROL_ENDPOINT: 2062 pipe->up_methods = &roothub_ctrl_methods; 2063 break; 2064 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 2065 pipe->up_methods = &ohci_root_intr_methods; 2066 break; 2067 default: 2068 err = USBD_INVAL; 2069 goto bad; 2070 } 2071 } else { 2072 sed = ohci_alloc_sed(sc); 2073 if (sed == NULL) 2074 goto bad; 2075 opipe->sed = sed; 2076 if (xfertype == UE_ISOCHRONOUS) { 2077 sitd = ohci_alloc_sitd(sc); 2078 if (sitd == NULL) 2079 goto bad; 2080 2081 opipe->tail.itd = sitd; 2082 tdphys = sitd->physaddr; 2083 fmt = OHCI_ED_FORMAT_ISO; 2084 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2085 fmt |= OHCI_ED_DIR_IN; 2086 else 2087 fmt |= OHCI_ED_DIR_OUT; 2088 } else { 2089 std = ohci_alloc_std(sc); 2090 if (std == NULL) 2091 goto bad; 2092 2093 opipe->tail.td = std; 2094 tdphys = std->physaddr; 2095 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2096 } 2097 sed->ed.ed_flags = HTOO32( 2098 OHCI_ED_SET_FA(addr) | 2099 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2100 (dev->ud_speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2101 fmt | 2102 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2103 sed->ed.ed_headp = HTOO32(tdphys | 2104 (pipe->up_endpoint->ue_toggle ? OHCI_TOGGLECARRY : 0)); 2105 sed->ed.ed_tailp = HTOO32(tdphys); 2106 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2107 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2108 2109 switch (xfertype) { 2110 case UE_CONTROL: 2111 pipe->up_methods = &ohci_device_ctrl_methods; 2112 err = usb_allocmem(&sc->sc_bus, 2113 sizeof(usb_device_request_t), 2114 0, &opipe->ctrl.reqdma); 2115 if (err) 2116 goto bad; 2117 mutex_enter(&sc->sc_lock); 2118 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2119 mutex_exit(&sc->sc_lock); 2120 break; 2121 case UE_INTERRUPT: 2122 pipe->up_methods = &ohci_device_intr_methods; 2123 ival = pipe->up_interval; 2124 if (ival == USBD_DEFAULT_INTERVAL) 2125 ival = ed->bInterval; 2126 err = ohci_device_setintr(sc, opipe, ival); 2127 if (err) 2128 goto bad; 2129 break; 2130 case UE_ISOCHRONOUS: 2131 pipe->up_serialise = false; 2132 pipe->up_methods = &ohci_device_isoc_methods; 2133 return ohci_setup_isoc(pipe); 2134 case UE_BULK: 2135 pipe->up_methods = &ohci_device_bulk_methods; 2136 mutex_enter(&sc->sc_lock); 2137 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2138 mutex_exit(&sc->sc_lock); 2139 break; 2140 } 2141 } 2142 2143 return USBD_NORMAL_COMPLETION; 2144 2145 bad: 2146 if (std != NULL) { 2147 ohci_free_std(sc, std); 2148 } 2149 if (sed != NULL) 2150 ohci_free_sed(sc, sed); 2151 return err; 2152 2153 } 2154 2155 /* 2156 * Close a reqular pipe. 2157 * Assumes that there are no pending transactions. 2158 */ 2159 void 2160 ohci_close_pipe(struct usbd_pipe *pipe, ohci_soft_ed_t *head) 2161 { 2162 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2163 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2164 ohci_soft_ed_t *sed = opipe->sed; 2165 2166 KASSERT(mutex_owned(&sc->sc_lock)); 2167 2168 #ifdef DIAGNOSTIC 2169 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2170 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2171 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2172 ohci_soft_td_t *std; 2173 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2174 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2175 "tl=0x%x pipe=%p, std=%p\n", sed, 2176 (int)O32TOH(sed->ed.ed_headp), 2177 (int)O32TOH(sed->ed.ed_tailp), 2178 pipe, std); 2179 #ifdef OHCI_DEBUG 2180 usbd_dump_pipe(&opipe->pipe); 2181 ohci_dump_ed(sc, sed); 2182 if (std) 2183 ohci_dump_td(sc, std); 2184 #endif 2185 usb_delay_ms(&sc->sc_bus, 2); 2186 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2187 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2188 printf("ohci_close_pipe: pipe still not empty\n"); 2189 } 2190 #endif 2191 ohci_rem_ed(sc, sed, head); 2192 /* Make sure the host controller is not touching this ED */ 2193 usb_delay_ms(&sc->sc_bus, 1); 2194 pipe->up_endpoint->ue_toggle = 2195 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2196 ohci_free_sed_locked(sc, opipe->sed); 2197 } 2198 2199 /* 2200 * Abort a device request. 2201 * If this routine is called at splusb() it guarantees that the request 2202 * will be removed from the hardware scheduling and that the callback 2203 * for it will be called with USBD_CANCELLED status. 2204 * It's impossible to guarantee that the requested transfer will not 2205 * have happened since the hardware runs concurrently. 2206 * If the transaction has already happened we rely on the ordinary 2207 * interrupt processing to process it. 2208 * XXX This is most probably wrong. 2209 * XXXMRG this doesn't make sense anymore. 2210 */ 2211 void 2212 ohci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2213 { 2214 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2215 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2216 ohci_soft_ed_t *sed = opipe->sed; 2217 ohci_soft_td_t *p, *n; 2218 ohci_physaddr_t headp; 2219 int hit; 2220 int wake; 2221 2222 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2223 DPRINTF("xfer=%#jx pipe=%#jx sed=%#jx", (uintptr_t)xfer, 2224 (uintptr_t)opipe, (uintptr_t)sed, 0); 2225 2226 KASSERT(mutex_owned(&sc->sc_lock)); 2227 ASSERT_SLEEPABLE(); 2228 2229 if (sc->sc_dying) { 2230 /* If we're dying, just do the software part. */ 2231 xfer->ux_status = status; /* make software ignore it */ 2232 callout_halt(&xfer->ux_callout, &sc->sc_lock); 2233 usb_transfer_complete(xfer); 2234 return; 2235 } 2236 2237 /* 2238 * If an abort is already in progress then just wait for it to 2239 * complete and return. 2240 */ 2241 if (xfer->ux_hcflags & UXFER_ABORTING) { 2242 DPRINTFN(2, "already aborting", 0, 0, 0, 0); 2243 #ifdef DIAGNOSTIC 2244 if (status == USBD_TIMEOUT) 2245 printf("%s: TIMEOUT while aborting\n", __func__); 2246 #endif 2247 /* Override the status which might be USBD_TIMEOUT. */ 2248 xfer->ux_status = status; 2249 DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0); 2250 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2251 while (xfer->ux_hcflags & UXFER_ABORTING) 2252 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2253 goto done; 2254 } 2255 xfer->ux_hcflags |= UXFER_ABORTING; 2256 2257 /* 2258 * Step 1: Make interrupt routine and hardware ignore xfer. 2259 */ 2260 xfer->ux_status = status; /* make software ignore it */ 2261 callout_stop(&xfer->ux_callout); 2262 DPRINTFN(1, "stop ed=%#jx", (uintptr_t)sed, 0, 0, 0); 2263 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2264 sizeof(sed->ed.ed_flags), 2265 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2266 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2267 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2268 sizeof(sed->ed.ed_flags), 2269 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2270 2271 /* 2272 * Step 2: Wait until we know hardware has finished any possible 2273 * use of the xfer. Also make sure the soft interrupt routine 2274 * has run. 2275 */ 2276 /* Hardware finishes in 1ms */ 2277 usb_delay_ms_locked(opipe->pipe.up_dev->ud_bus, 20, &sc->sc_lock); 2278 sc->sc_softwake = 1; 2279 usb_schedsoftintr(&sc->sc_bus); 2280 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2281 2282 /* 2283 * Step 3: Remove any vestiges of the xfer from the hardware. 2284 * The complication here is that the hardware may have executed 2285 * beyond the xfer we're trying to abort. So as we're scanning 2286 * the TDs of this xfer we check if the hardware points to 2287 * any of them. 2288 */ 2289 p = xfer->ux_hcpriv; 2290 KASSERT(p); 2291 2292 #ifdef OHCI_DEBUG 2293 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2294 2295 if (ohcidebug >= 2) { 2296 DPRINTF("sed:", 0, 0, 0, 0); 2297 ohci_dump_ed(sc, sed); 2298 ohci_dump_tds(sc, p); 2299 } 2300 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2301 #endif 2302 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2303 hit = 0; 2304 for (; p->xfer == xfer; p = n) { 2305 hit |= headp == p->physaddr; 2306 n = p->nexttd; 2307 ohci_hash_rem_td(sc, p); 2308 } 2309 /* Zap headp register if hardware pointed inside the xfer. */ 2310 if (hit) { 2311 DPRINTFN(1, "set hd=0x%08jx, tl=0x%08jx", (int)p->physaddr, 2312 (int)O32TOH(sed->ed.ed_tailp), 0, 0); 2313 sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */ 2314 usb_syncmem(&sed->dma, 2315 sed->offs + offsetof(ohci_ed_t, ed_headp), 2316 sizeof(sed->ed.ed_headp), 2317 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2318 } else { 2319 DPRINTFN(1, "no hit", 0, 0, 0, 0); 2320 } 2321 2322 /* 2323 * Step 4: Turn on hardware again. 2324 */ 2325 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2326 sizeof(sed->ed.ed_flags), 2327 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2328 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2329 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2330 sizeof(sed->ed.ed_flags), 2331 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2332 2333 /* 2334 * Step 5: Execute callback. 2335 */ 2336 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2337 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2338 usb_transfer_complete(xfer); 2339 if (wake) 2340 cv_broadcast(&xfer->ux_hccv); 2341 2342 done: 2343 KASSERT(mutex_owned(&sc->sc_lock)); 2344 } 2345 2346 /* 2347 * Data structures and routines to emulate the root hub. 2348 */ 2349 Static int 2350 ohci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2351 void *buf, int buflen) 2352 { 2353 ohci_softc_t *sc = OHCI_BUS2SC(bus); 2354 usb_port_status_t ps; 2355 uint16_t len, value, index; 2356 int l, totlen = 0; 2357 int port, i; 2358 uint32_t v; 2359 2360 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2361 2362 if (sc->sc_dying) 2363 return -1; 2364 2365 DPRINTFN(4, "type=0x%02jx request=%02jx", req->bmRequestType, 2366 req->bRequest, 0, 0); 2367 2368 len = UGETW(req->wLength); 2369 value = UGETW(req->wValue); 2370 index = UGETW(req->wIndex); 2371 2372 #define C(x,y) ((x) | ((y) << 8)) 2373 switch (C(req->bRequest, req->bmRequestType)) { 2374 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2375 DPRINTFN(8, "wValue=0x%04jx", value, 0, 0, 0); 2376 if (len == 0) 2377 break; 2378 switch (value) { 2379 case C(0, UDESC_DEVICE): { 2380 usb_device_descriptor_t devd; 2381 2382 totlen = min(buflen, sizeof(devd)); 2383 memcpy(&devd, buf, totlen); 2384 USETW(devd.idVendor, sc->sc_id_vendor); 2385 memcpy(buf, &devd, totlen); 2386 break; 2387 } 2388 case C(1, UDESC_STRING): 2389 #define sd ((usb_string_descriptor_t *)buf) 2390 /* Vendor */ 2391 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2392 break; 2393 case C(2, UDESC_STRING): 2394 /* Product */ 2395 totlen = usb_makestrdesc(sd, len, "OHCI root hub"); 2396 break; 2397 #undef sd 2398 default: 2399 /* default from usbroothub */ 2400 return buflen; 2401 } 2402 break; 2403 2404 /* Hub requests */ 2405 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2406 break; 2407 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2408 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", 2409 index, value, 0, 0); 2410 if (index < 1 || index > sc->sc_noport) { 2411 return -1; 2412 } 2413 port = OHCI_RH_PORT_STATUS(index); 2414 switch(value) { 2415 case UHF_PORT_ENABLE: 2416 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2417 break; 2418 case UHF_PORT_SUSPEND: 2419 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2420 break; 2421 case UHF_PORT_POWER: 2422 /* Yes, writing to the LOW_SPEED bit clears power. */ 2423 OWRITE4(sc, port, UPS_LOW_SPEED); 2424 break; 2425 case UHF_C_PORT_CONNECTION: 2426 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2427 break; 2428 case UHF_C_PORT_ENABLE: 2429 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2430 break; 2431 case UHF_C_PORT_SUSPEND: 2432 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2433 break; 2434 case UHF_C_PORT_OVER_CURRENT: 2435 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2436 break; 2437 case UHF_C_PORT_RESET: 2438 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2439 break; 2440 default: 2441 return -1; 2442 } 2443 switch(value) { 2444 case UHF_C_PORT_CONNECTION: 2445 case UHF_C_PORT_ENABLE: 2446 case UHF_C_PORT_SUSPEND: 2447 case UHF_C_PORT_OVER_CURRENT: 2448 case UHF_C_PORT_RESET: 2449 /* Enable RHSC interrupt if condition is cleared. */ 2450 if ((OREAD4(sc, port) >> 16) == 0) 2451 ohci_rhsc_enable(sc); 2452 break; 2453 default: 2454 break; 2455 } 2456 break; 2457 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2458 if (len == 0) 2459 break; 2460 if ((value & 0xff) != 0) { 2461 return -1; 2462 } 2463 usb_hub_descriptor_t hubd; 2464 2465 totlen = min(buflen, sizeof(hubd)); 2466 memcpy(&hubd, buf, totlen); 2467 2468 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2469 hubd.bNbrPorts = sc->sc_noport; 2470 USETW(hubd.wHubCharacteristics, 2471 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2472 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2473 /* XXX overcurrent */ 2474 ); 2475 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2476 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2477 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2478 hubd.DeviceRemovable[i++] = (uint8_t)v; 2479 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2480 totlen = min(totlen, hubd.bDescLength); 2481 memcpy(buf, &hubd, totlen); 2482 break; 2483 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2484 if (len != 4) { 2485 return -1; 2486 } 2487 memset(buf, 0, len); /* ? XXX */ 2488 totlen = len; 2489 break; 2490 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2491 DPRINTFN(8, "get port status i=%jd", index, 0, 0, 0); 2492 if (index < 1 || index > sc->sc_noport) { 2493 return -1; 2494 } 2495 if (len != 4) { 2496 return -1; 2497 } 2498 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2499 DPRINTFN(8, "port status=0x%04jx", v, 0, 0, 0); 2500 USETW(ps.wPortStatus, v); 2501 USETW(ps.wPortChange, v >> 16); 2502 totlen = min(len, sizeof(ps)); 2503 memcpy(buf, &ps, totlen); 2504 break; 2505 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2506 return -1; 2507 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2508 break; 2509 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2510 if (index < 1 || index > sc->sc_noport) { 2511 return -1; 2512 } 2513 port = OHCI_RH_PORT_STATUS(index); 2514 switch(value) { 2515 case UHF_PORT_ENABLE: 2516 OWRITE4(sc, port, UPS_PORT_ENABLED); 2517 break; 2518 case UHF_PORT_SUSPEND: 2519 OWRITE4(sc, port, UPS_SUSPEND); 2520 break; 2521 case UHF_PORT_RESET: 2522 DPRINTFN(5, "reset port %jd", index, 0, 0, 0); 2523 OWRITE4(sc, port, UPS_RESET); 2524 for (i = 0; i < 5; i++) { 2525 usb_delay_ms(&sc->sc_bus, 2526 USB_PORT_ROOT_RESET_DELAY); 2527 if (sc->sc_dying) { 2528 return -1; 2529 } 2530 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2531 break; 2532 } 2533 DPRINTFN(8, "port %jd reset, status = 0x%04jx", index, 2534 OREAD4(sc, port), 0, 0); 2535 break; 2536 case UHF_PORT_POWER: 2537 DPRINTFN(2, "set port power %jd", index, 0, 0, 0); 2538 OWRITE4(sc, port, UPS_PORT_POWER); 2539 break; 2540 default: 2541 return -1; 2542 } 2543 break; 2544 default: 2545 /* default from usbroothub */ 2546 return buflen; 2547 } 2548 2549 return totlen; 2550 } 2551 2552 Static usbd_status 2553 ohci_root_intr_transfer(struct usbd_xfer *xfer) 2554 { 2555 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2556 usbd_status err; 2557 2558 /* Insert last in queue. */ 2559 mutex_enter(&sc->sc_lock); 2560 err = usb_insert_transfer(xfer); 2561 mutex_exit(&sc->sc_lock); 2562 if (err) 2563 return err; 2564 2565 /* Pipe isn't running, start first */ 2566 return ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2567 } 2568 2569 Static usbd_status 2570 ohci_root_intr_start(struct usbd_xfer *xfer) 2571 { 2572 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2573 2574 if (sc->sc_dying) 2575 return USBD_IOERROR; 2576 2577 mutex_enter(&sc->sc_lock); 2578 KASSERT(sc->sc_intrxfer == NULL); 2579 sc->sc_intrxfer = xfer; 2580 mutex_exit(&sc->sc_lock); 2581 2582 return USBD_IN_PROGRESS; 2583 } 2584 2585 /* Abort a root interrupt request. */ 2586 Static void 2587 ohci_root_intr_abort(struct usbd_xfer *xfer) 2588 { 2589 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2590 2591 KASSERT(mutex_owned(&sc->sc_lock)); 2592 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2593 2594 xfer->ux_status = USBD_CANCELLED; 2595 usb_transfer_complete(xfer); 2596 } 2597 2598 /* Close the root pipe. */ 2599 Static void 2600 ohci_root_intr_close(struct usbd_pipe *pipe) 2601 { 2602 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2603 2604 KASSERT(mutex_owned(&sc->sc_lock)); 2605 2606 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2607 2608 sc->sc_intrxfer = NULL; 2609 } 2610 2611 /************************/ 2612 2613 int 2614 ohci_device_ctrl_init(struct usbd_xfer *xfer) 2615 { 2616 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2617 usb_device_request_t *req = &xfer->ux_request; 2618 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2619 ohci_soft_td_t *stat, *setup; 2620 int isread = req->bmRequestType & UT_READ; 2621 int len = xfer->ux_bufsize; 2622 int err = ENOMEM; 2623 2624 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2625 2626 setup = ohci_alloc_std(sc); 2627 if (setup == NULL) { 2628 goto bad1; 2629 } 2630 stat = ohci_alloc_std(sc); 2631 if (stat == NULL) { 2632 goto bad2; 2633 } 2634 2635 ox->ox_setup = setup; 2636 ox->ox_stat = stat; 2637 ox->ox_nstd = 0; 2638 2639 /* Set up data transaction */ 2640 if (len != 0) { 2641 err = ohci_alloc_std_chain(sc, xfer, len, isread); 2642 if (err) { 2643 goto bad3; 2644 } 2645 } 2646 return 0; 2647 2648 bad3: 2649 ohci_free_std(sc, stat); 2650 bad2: 2651 ohci_free_std(sc, setup); 2652 bad1: 2653 return err; 2654 } 2655 2656 void 2657 ohci_device_ctrl_fini(struct usbd_xfer *xfer) 2658 { 2659 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2660 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2661 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2662 2663 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2664 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 2665 2666 mutex_enter(&sc->sc_lock); 2667 if (ox->ox_setup != opipe->tail.td) { 2668 ohci_free_std_locked(sc, ox->ox_setup); 2669 } 2670 for (size_t i = 0; i < ox->ox_nstd; i++) { 2671 ohci_soft_td_t *std = ox->ox_stds[i]; 2672 if (std == NULL) 2673 break; 2674 ohci_free_std_locked(sc, std); 2675 } 2676 ohci_free_std_locked(sc, ox->ox_stat); 2677 mutex_exit(&sc->sc_lock); 2678 2679 if (ox->ox_nstd) { 2680 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 2681 kmem_free(ox->ox_stds, sz); 2682 } 2683 } 2684 2685 Static usbd_status 2686 ohci_device_ctrl_transfer(struct usbd_xfer *xfer) 2687 { 2688 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2689 usbd_status err; 2690 2691 /* Insert last in queue. */ 2692 mutex_enter(&sc->sc_lock); 2693 err = usb_insert_transfer(xfer); 2694 mutex_exit(&sc->sc_lock); 2695 if (err) 2696 return err; 2697 2698 /* Pipe isn't running, start first */ 2699 return ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2700 } 2701 2702 Static usbd_status 2703 ohci_device_ctrl_start(struct usbd_xfer *xfer) 2704 { 2705 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2706 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2707 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2708 usb_device_request_t *req = &xfer->ux_request; 2709 struct usbd_device *dev __diagused = opipe->pipe.up_dev; 2710 ohci_soft_td_t *setup, *stat, *next, *tail; 2711 ohci_soft_ed_t *sed; 2712 int isread; 2713 int len; 2714 2715 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2716 2717 if (sc->sc_dying) 2718 return USBD_IOERROR; 2719 2720 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2721 2722 isread = req->bmRequestType & UT_READ; 2723 len = UGETW(req->wLength); 2724 2725 DPRINTF("xfer=%#jx len=%jd, addr=%jd, endpt=%jd", (uintptr_t)xfer, len, 2726 dev->ud_addr, opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress); 2727 DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx", 2728 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2729 UGETW(req->wIndex)); 2730 2731 /* Need to take lock here for pipe->tail.td */ 2732 mutex_enter(&sc->sc_lock); 2733 2734 /* 2735 * Use the pipe "tail" TD as our first and loan our first TD to the 2736 * next transfer 2737 */ 2738 setup = opipe->tail.td; 2739 opipe->tail.td = ox->ox_setup; 2740 ox->ox_setup = setup; 2741 2742 stat = ox->ox_stat; 2743 2744 /* point at sentinel */ 2745 tail = opipe->tail.td; 2746 sed = opipe->sed; 2747 2748 KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->ud_addr, 2749 "address ED %d pipe %d\n", 2750 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->ud_addr); 2751 KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) == 2752 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 2753 "MPL ED %d pipe %d\n", 2754 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), 2755 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 2756 2757 /* next will point to data if len != 0 */ 2758 next = stat; 2759 2760 /* Set up data transaction */ 2761 if (len != 0) { 2762 ohci_soft_td_t *std; 2763 ohci_soft_td_t *end; 2764 2765 next = ox->ox_stds[0]; 2766 ohci_reset_std_chain(sc, xfer, len, isread, next, &end); 2767 2768 end->td.td_nexttd = HTOO32(stat->physaddr); 2769 end->nexttd = stat; 2770 2771 usb_syncmem(&end->dma, end->offs, sizeof(end->td), 2772 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2773 2774 usb_syncmem(&xfer->ux_dmabuf, 0, len, 2775 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2776 std = ox->ox_stds[0]; 2777 /* Start toggle at 1 and then use the carried toggle. */ 2778 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 2779 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 2780 usb_syncmem(&std->dma, 2781 std->offs + offsetof(ohci_td_t, td_flags), 2782 sizeof(std->td.td_flags), 2783 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2784 } 2785 2786 DPRINTFN(8, "setup %#jx data %#jx stat %#jx tail %#jx", 2787 (uintptr_t)setup, 2788 (uintptr_t)(len != 0 ? ox->ox_stds[0] : NULL), (uintptr_t)stat, 2789 (uintptr_t)tail); 2790 KASSERT(opipe->tail.td == tail); 2791 2792 memcpy(KERNADDR(&opipe->ctrl.reqdma, 0), req, sizeof(*req)); 2793 usb_syncmem(&opipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2794 2795 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 2796 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 2797 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->ctrl.reqdma, 0)); 2798 setup->td.td_nexttd = HTOO32(next->physaddr); 2799 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof(*req) - 1); 2800 setup->nexttd = next; 2801 setup->len = 0; 2802 setup->xfer = xfer; 2803 setup->flags = 0; 2804 ohci_hash_add_td(sc, setup); 2805 2806 xfer->ux_hcpriv = setup; 2807 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2808 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2809 2810 stat->td.td_flags = HTOO32( 2811 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 2812 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 2813 stat->td.td_cbp = 0; 2814 stat->td.td_nexttd = HTOO32(tail->physaddr); 2815 stat->td.td_be = 0; 2816 stat->nexttd = tail; 2817 stat->flags = OHCI_CALL_DONE; 2818 stat->len = 0; 2819 stat->xfer = xfer; 2820 ohci_hash_add_td(sc, stat); 2821 2822 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2823 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2824 2825 memset(&tail->td, 0, sizeof(tail->td)); 2826 tail->nexttd = NULL; 2827 tail->xfer = NULL; 2828 2829 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 2830 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2831 2832 #ifdef OHCI_DEBUG 2833 USBHIST_LOGN(ohcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2834 if (ohcidebug >= 5) { 2835 ohci_dump_ed(sc, sed); 2836 ohci_dump_tds(sc, setup); 2837 } 2838 USBHIST_LOGN(ohcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2839 #endif 2840 2841 /* Insert ED in schedule */ 2842 sed->ed.ed_tailp = HTOO32(tail->physaddr); 2843 usb_syncmem(&sed->dma, 2844 sed->offs + offsetof(ohci_ed_t, ed_tailp), 2845 sizeof(sed->ed.ed_tailp), 2846 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2847 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2848 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2849 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2850 ohci_timeout, xfer); 2851 } 2852 2853 DPRINTF("done", 0, 0, 0, 0); 2854 2855 mutex_exit(&sc->sc_lock); 2856 2857 return USBD_IN_PROGRESS; 2858 } 2859 2860 /* Abort a device control request. */ 2861 Static void 2862 ohci_device_ctrl_abort(struct usbd_xfer *xfer) 2863 { 2864 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 2865 2866 KASSERT(mutex_owned(&sc->sc_lock)); 2867 2868 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2869 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 2870 ohci_abort_xfer(xfer, USBD_CANCELLED); 2871 } 2872 2873 /* Close a device control pipe. */ 2874 Static void 2875 ohci_device_ctrl_close(struct usbd_pipe *pipe) 2876 { 2877 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2878 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2879 2880 KASSERT(mutex_owned(&sc->sc_lock)); 2881 2882 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2883 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 2884 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2885 ohci_free_std_locked(sc, opipe->tail.td); 2886 } 2887 2888 /************************/ 2889 2890 Static void 2891 ohci_device_clear_toggle(struct usbd_pipe *pipe) 2892 { 2893 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2894 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2895 2896 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2897 } 2898 2899 Static void 2900 ohci_noop(struct usbd_pipe *pipe) 2901 { 2902 } 2903 2904 Static int 2905 ohci_device_bulk_init(struct usbd_xfer *xfer) 2906 { 2907 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2908 int len = xfer->ux_bufsize; 2909 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;; 2910 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2911 int err; 2912 2913 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2914 2915 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2916 2917 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 2918 len, isread, xfer->ux_flags); 2919 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 2920 2921 /* Allocate a chain of new TDs (including a new tail). */ 2922 err = ohci_alloc_std_chain(sc, xfer, len, isread); 2923 if (err) 2924 return err; 2925 2926 return 0; 2927 } 2928 2929 Static void 2930 ohci_device_bulk_fini(struct usbd_xfer *xfer) 2931 { 2932 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2933 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2934 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2935 2936 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2937 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 2938 2939 mutex_enter(&sc->sc_lock); 2940 for (size_t i = 0; i < ox->ox_nstd; i++) { 2941 ohci_soft_td_t *std = ox->ox_stds[i]; 2942 if (std == NULL) 2943 break; 2944 if (std != opipe->tail.td) 2945 ohci_free_std_locked(sc, std); 2946 } 2947 mutex_exit(&sc->sc_lock); 2948 2949 if (ox->ox_nstd) { 2950 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 2951 kmem_free(ox->ox_stds, sz); 2952 } 2953 } 2954 2955 Static usbd_status 2956 ohci_device_bulk_transfer(struct usbd_xfer *xfer) 2957 { 2958 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2959 usbd_status err; 2960 2961 /* Insert last in queue. */ 2962 mutex_enter(&sc->sc_lock); 2963 err = usb_insert_transfer(xfer); 2964 mutex_exit(&sc->sc_lock); 2965 if (err) 2966 return err; 2967 2968 /* Pipe isn't running, start first */ 2969 return ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2970 } 2971 2972 Static usbd_status 2973 ohci_device_bulk_start(struct usbd_xfer *xfer) 2974 { 2975 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2976 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2977 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2978 ohci_soft_td_t *last; 2979 ohci_soft_td_t *data, *tail, *tdp; 2980 ohci_soft_ed_t *sed; 2981 int len, isread, endpt; 2982 2983 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2984 2985 if (sc->sc_dying) 2986 return USBD_IOERROR; 2987 2988 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2989 2990 len = xfer->ux_length; 2991 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2992 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2993 sed = opipe->sed; 2994 2995 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 2996 len, isread, xfer->ux_flags); 2997 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 2998 2999 mutex_enter(&sc->sc_lock); 3000 3001 /* 3002 * Use the pipe "tail" TD as our first and loan our first TD to the 3003 * next transfer 3004 */ 3005 data = opipe->tail.td; 3006 opipe->tail.td = ox->ox_stds[0]; 3007 ox->ox_stds[0] = data; 3008 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3009 3010 /* point at sentinel */ 3011 tail = opipe->tail.td; 3012 memset(&tail->td, 0, sizeof(tail->td)); 3013 tail->nexttd = NULL; 3014 tail->xfer = NULL; 3015 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3016 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3017 xfer->ux_hcpriv = data; 3018 3019 DPRINTFN(8, "xfer %#jx data %#jx tail %#jx", (uintptr_t)xfer, 3020 (uintptr_t)ox->ox_stds[0], (uintptr_t)tail, 0); 3021 KASSERT(opipe->tail.td == tail); 3022 3023 /* We want interrupt at the end of the transfer. */ 3024 last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3025 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3026 last->td.td_nexttd = HTOO32(tail->physaddr); 3027 last->nexttd = tail; 3028 last->flags |= OHCI_CALL_DONE; 3029 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3030 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3031 3032 DPRINTFN(4, "ed_flags=0x%08jx td_flags=0x%08jx " 3033 "td_cbp=0x%08jx td_be=0x%08jx", 3034 (int)O32TOH(sed->ed.ed_flags), 3035 (int)O32TOH(data->td.td_flags), 3036 (int)O32TOH(data->td.td_cbp), 3037 (int)O32TOH(data->td.td_be)); 3038 3039 #ifdef OHCI_DEBUG 3040 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3041 if (ohcidebug >= 5) { 3042 ohci_dump_ed(sc, sed); 3043 ohci_dump_tds(sc, data); 3044 } 3045 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3046 #endif 3047 3048 /* Insert ED in schedule */ 3049 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3050 KASSERT(tdp->xfer == xfer); 3051 } 3052 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3053 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3054 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3055 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3056 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3057 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3058 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3059 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3060 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3061 ohci_timeout, xfer); 3062 } 3063 mutex_exit(&sc->sc_lock); 3064 3065 return USBD_IN_PROGRESS; 3066 } 3067 3068 Static void 3069 ohci_device_bulk_abort(struct usbd_xfer *xfer) 3070 { 3071 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3072 3073 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3074 3075 KASSERT(mutex_owned(&sc->sc_lock)); 3076 3077 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3078 ohci_abort_xfer(xfer, USBD_CANCELLED); 3079 } 3080 3081 /* 3082 * Close a device bulk pipe. 3083 */ 3084 Static void 3085 ohci_device_bulk_close(struct usbd_pipe *pipe) 3086 { 3087 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3088 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3089 3090 KASSERT(mutex_owned(&sc->sc_lock)); 3091 3092 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3093 3094 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3095 ohci_close_pipe(pipe, sc->sc_bulk_head); 3096 ohci_free_std_locked(sc, opipe->tail.td); 3097 } 3098 3099 /************************/ 3100 3101 Static int 3102 ohci_device_intr_init(struct usbd_xfer *xfer) 3103 { 3104 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3105 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3106 int len = xfer->ux_bufsize; 3107 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;; 3108 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3109 int err; 3110 3111 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3112 3113 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3114 KASSERT(len != 0); 3115 3116 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 3117 len, isread, xfer->ux_flags); 3118 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 3119 3120 ox->ox_nstd = 0; 3121 3122 err = ohci_alloc_std_chain(sc, xfer, len, isread); 3123 if (err) { 3124 return err; 3125 } 3126 3127 return 0; 3128 } 3129 3130 Static void 3131 ohci_device_intr_fini(struct usbd_xfer *xfer) 3132 { 3133 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3134 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3135 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3136 3137 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3138 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 3139 3140 mutex_enter(&sc->sc_lock); 3141 for (size_t i = 0; i < ox->ox_nstd; i++) { 3142 ohci_soft_td_t *std = ox->ox_stds[i]; 3143 if (std != NULL) 3144 break; 3145 if (std != opipe->tail.td) 3146 ohci_free_std_locked(sc, std); 3147 } 3148 mutex_exit(&sc->sc_lock); 3149 3150 if (ox->ox_nstd) { 3151 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 3152 kmem_free(ox->ox_stds, sz); 3153 } 3154 } 3155 3156 Static usbd_status 3157 ohci_device_intr_transfer(struct usbd_xfer *xfer) 3158 { 3159 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3160 usbd_status err; 3161 3162 /* Insert last in queue. */ 3163 mutex_enter(&sc->sc_lock); 3164 err = usb_insert_transfer(xfer); 3165 mutex_exit(&sc->sc_lock); 3166 if (err) 3167 return err; 3168 3169 /* Pipe isn't running, start first */ 3170 return ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3171 } 3172 3173 Static usbd_status 3174 ohci_device_intr_start(struct usbd_xfer *xfer) 3175 { 3176 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3177 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3178 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3179 ohci_soft_ed_t *sed = opipe->sed; 3180 ohci_soft_td_t *data, *last, *tail; 3181 int len, isread, endpt; 3182 3183 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3184 3185 if (sc->sc_dying) 3186 return USBD_IOERROR; 3187 3188 DPRINTFN(3, "xfer=%#jx len=%jd flags=%jd priv=%#jx", (uintptr_t)xfer, 3189 xfer->ux_length, xfer->ux_flags, (uintptr_t)xfer->ux_priv); 3190 3191 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3192 3193 len = xfer->ux_length; 3194 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3195 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3196 3197 mutex_enter(&sc->sc_lock); 3198 3199 /* 3200 * Use the pipe "tail" TD as our first and loan our first TD to the 3201 * next transfer. 3202 */ 3203 data = opipe->tail.td; 3204 opipe->tail.td = ox->ox_stds[0]; 3205 ox->ox_stds[0] = data; 3206 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3207 3208 /* point at sentinel */ 3209 tail = opipe->tail.td; 3210 memset(&tail->td, 0, sizeof(tail->td)); 3211 tail->nexttd = NULL; 3212 tail->xfer = NULL; 3213 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3214 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3215 xfer->ux_hcpriv = data; 3216 3217 DPRINTFN(8, "data %#jx tail %#jx", (uintptr_t)ox->ox_stds[0], 3218 (uintptr_t)tail, 0, 0); 3219 KASSERT(opipe->tail.td == tail); 3220 3221 /* We want interrupt at the end of the transfer. */ 3222 last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3223 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3224 3225 last->td.td_nexttd = HTOO32(tail->physaddr); 3226 last->nexttd = tail; 3227 last->flags |= OHCI_CALL_DONE; 3228 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3229 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3230 3231 #ifdef OHCI_DEBUG 3232 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3233 if (ohcidebug >= 5) { 3234 ohci_dump_ed(sc, sed); 3235 ohci_dump_tds(sc, data); 3236 } 3237 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3238 #endif 3239 3240 /* Insert ED in schedule */ 3241 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3242 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3243 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3244 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3245 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3246 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3247 3248 mutex_exit(&sc->sc_lock); 3249 3250 return USBD_IN_PROGRESS; 3251 } 3252 3253 /* Abort a device interrupt request. */ 3254 Static void 3255 ohci_device_intr_abort(struct usbd_xfer *xfer) 3256 { 3257 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3258 3259 KASSERT(mutex_owned(&sc->sc_lock)); 3260 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3261 3262 ohci_abort_xfer(xfer, USBD_CANCELLED); 3263 } 3264 3265 /* Close a device interrupt pipe. */ 3266 Static void 3267 ohci_device_intr_close(struct usbd_pipe *pipe) 3268 { 3269 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3270 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3271 int nslots = opipe->intr.nslots; 3272 int pos = opipe->intr.pos; 3273 int j; 3274 ohci_soft_ed_t *p, *sed = opipe->sed; 3275 3276 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3277 3278 KASSERT(mutex_owned(&sc->sc_lock)); 3279 3280 DPRINTFN(1, "pipe=%#jx nslots=%jd pos=%jd", (uintptr_t)pipe, nslots, 3281 pos, 0); 3282 usb_syncmem(&sed->dma, sed->offs, 3283 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3284 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3285 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3286 sizeof(sed->ed.ed_flags), 3287 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3288 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3289 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3290 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3291 3292 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3293 continue; 3294 KASSERT(p); 3295 p->next = sed->next; 3296 p->ed.ed_nexted = sed->ed.ed_nexted; 3297 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3298 sizeof(p->ed.ed_nexted), 3299 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3300 3301 for (j = 0; j < nslots; j++) 3302 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3303 3304 ohci_free_std_locked(sc, opipe->tail.td); 3305 ohci_free_sed_locked(sc, opipe->sed); 3306 } 3307 3308 Static usbd_status 3309 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3310 { 3311 int i, j, best; 3312 u_int npoll, slow, shigh, nslots; 3313 u_int bestbw, bw; 3314 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3315 3316 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3317 3318 DPRINTFN(2, "pipe=%#jx", (uintptr_t)opipe, 0, 0, 0); 3319 if (ival == 0) { 3320 printf("ohci_setintr: 0 interval\n"); 3321 return USBD_INVAL; 3322 } 3323 3324 npoll = OHCI_NO_INTRS; 3325 while (npoll > ival) 3326 npoll /= 2; 3327 DPRINTFN(2, "ival=%jd npoll=%jd", ival, npoll, 0, 0); 3328 3329 /* 3330 * We now know which level in the tree the ED must go into. 3331 * Figure out which slot has most bandwidth left over. 3332 * Slots to examine: 3333 * npoll 3334 * 1 0 3335 * 2 1 2 3336 * 4 3 4 5 6 3337 * 8 7 8 9 10 11 12 13 14 3338 * N (N-1) .. (N-1+N-1) 3339 */ 3340 slow = npoll-1; 3341 shigh = slow + npoll; 3342 nslots = OHCI_NO_INTRS / npoll; 3343 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3344 bw = 0; 3345 for (j = 0; j < nslots; j++) 3346 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3347 if (bw < bestbw) { 3348 best = i; 3349 bestbw = bw; 3350 } 3351 } 3352 DPRINTFN(2, "best=%jd(%jd..%jd) bestbw=%jd", best, slow, shigh, bestbw); 3353 3354 mutex_enter(&sc->sc_lock); 3355 hsed = sc->sc_eds[best]; 3356 sed->next = hsed->next; 3357 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3358 sizeof(hsed->ed.ed_flags), 3359 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3360 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3361 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3362 sizeof(sed->ed.ed_flags), 3363 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3364 hsed->next = sed; 3365 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3366 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3367 sizeof(hsed->ed.ed_flags), 3368 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3369 mutex_exit(&sc->sc_lock); 3370 3371 for (j = 0; j < nslots; j++) 3372 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3373 opipe->intr.nslots = nslots; 3374 opipe->intr.pos = best; 3375 3376 DPRINTFN(5, "returns %#jx", (uintptr_t)opipe, 0, 0, 0); 3377 return USBD_NORMAL_COMPLETION; 3378 } 3379 3380 /***********************/ 3381 3382 Static int 3383 ohci_device_isoc_init(struct usbd_xfer *xfer) 3384 { 3385 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3386 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3387 ohci_soft_itd_t *sitd; 3388 size_t i; 3389 int err; 3390 3391 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3392 3393 DPRINTFN(1, "xfer %#jx len %jd flags %jd", (uintptr_t)xfer, 3394 xfer->ux_length, xfer->ux_flags, 0); 3395 3396 const size_t nfsitd = 3397 (xfer->ux_nframes + OHCI_ITD_NOFFSET - 1) / OHCI_ITD_NOFFSET; 3398 const size_t nbsitd = xfer->ux_bufsize / OHCI_PAGE_SIZE; 3399 const size_t nsitd = MAX(nfsitd, nbsitd) + 1; 3400 3401 ox->ox_sitds = kmem_zalloc(sizeof(ohci_soft_itd_t *) * nsitd, 3402 KM_SLEEP); 3403 ox->ox_nsitd = nsitd; 3404 3405 for (i = 0; i < nsitd; i++) { 3406 /* Allocate next ITD */ 3407 sitd = ohci_alloc_sitd(sc); 3408 if (sitd == NULL) { 3409 err = ENOMEM; 3410 goto fail; 3411 } 3412 ox->ox_sitds[i] = sitd; 3413 sitd->xfer = xfer; 3414 sitd->flags = 0; 3415 } 3416 3417 return 0; 3418 fail: 3419 for (; i > 0;) { 3420 ohci_free_sitd(sc, ox->ox_sitds[--i]); 3421 } 3422 return err; 3423 } 3424 3425 Static void 3426 ohci_device_isoc_fini(struct usbd_xfer *xfer) 3427 { 3428 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3429 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3430 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3431 3432 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3433 3434 mutex_enter(&sc->sc_lock); 3435 for (size_t i = 0; i < ox->ox_nsitd; i++) { 3436 if (ox->ox_sitds[i] != opipe->tail.itd) { 3437 ohci_free_sitd_locked(sc, ox->ox_sitds[i]); 3438 } 3439 } 3440 mutex_exit(&sc->sc_lock); 3441 3442 if (ox->ox_nsitd) { 3443 const size_t sz = sizeof(ohci_soft_itd_t *) * ox->ox_nsitd; 3444 kmem_free(ox->ox_sitds, sz); 3445 } 3446 } 3447 3448 3449 usbd_status 3450 ohci_device_isoc_transfer(struct usbd_xfer *xfer) 3451 { 3452 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3453 usbd_status __diagused err; 3454 3455 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3456 3457 DPRINTFN(5, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3458 3459 /* Put it on our queue, */ 3460 mutex_enter(&sc->sc_lock); 3461 err = usb_insert_transfer(xfer); 3462 mutex_exit(&sc->sc_lock); 3463 3464 KASSERT(err == USBD_NORMAL_COMPLETION); 3465 3466 /* insert into schedule, */ 3467 ohci_device_isoc_enter(xfer); 3468 3469 /* and start if the pipe wasn't running */ 3470 return USBD_IN_PROGRESS; 3471 } 3472 3473 void 3474 ohci_device_isoc_enter(struct usbd_xfer *xfer) 3475 { 3476 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3477 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3478 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3479 ohci_soft_ed_t *sed = opipe->sed; 3480 ohci_soft_itd_t *sitd, *nsitd, *tail; 3481 ohci_physaddr_t buf, offs, noffs, bp0; 3482 int i, ncur, nframes; 3483 3484 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3485 DPRINTFN(5, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3486 3487 mutex_enter(&sc->sc_lock); 3488 3489 if (sc->sc_dying) { 3490 mutex_exit(&sc->sc_lock); 3491 return; 3492 } 3493 3494 struct isoc *isoc = &opipe->isoc; 3495 3496 DPRINTFN(1, "used=%jd next=%jd xfer=%#jx nframes=%jd", 3497 isoc->inuse, isoc->next, (uintptr_t)xfer, xfer->ux_nframes); 3498 3499 if (isoc->next == -1) { 3500 /* Not in use yet, schedule it a few frames ahead. */ 3501 isoc->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3502 DPRINTFN(2,"start next=%jd", isoc->next, 0, 0, 0); 3503 } 3504 3505 sitd = opipe->tail.itd; 3506 opipe->tail.itd = ox->ox_sitds[0]; 3507 ox->ox_sitds[0] = sitd; 3508 3509 buf = DMAADDR(&xfer->ux_dmabuf, 0); 3510 bp0 = OHCI_PAGE(buf); 3511 offs = OHCI_PAGE_OFFSET(buf); 3512 nframes = xfer->ux_nframes; 3513 xfer->ux_hcpriv = sitd; 3514 size_t j = 1; 3515 for (i = ncur = 0; i < nframes; i++, ncur++) { 3516 noffs = offs + xfer->ux_frlengths[i]; 3517 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3518 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3519 3520 /* Allocate next ITD */ 3521 nsitd = ox->ox_sitds[j++]; 3522 KASSERT(nsitd != NULL); 3523 KASSERT(j < ox->ox_nsitd); 3524 3525 /* Fill current ITD */ 3526 sitd->itd.itd_flags = HTOO32( 3527 OHCI_ITD_NOCC | 3528 OHCI_ITD_SET_SF(isoc->next) | 3529 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3530 OHCI_ITD_SET_FC(ncur)); 3531 sitd->itd.itd_bp0 = HTOO32(bp0); 3532 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3533 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3534 sitd->nextitd = nsitd; 3535 sitd->xfer = xfer; 3536 sitd->flags = 0; 3537 #ifdef DIAGNOSTIC 3538 sitd->isdone = false; 3539 #endif 3540 ohci_hash_add_itd(sc, sitd); 3541 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3542 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3543 3544 sitd = nsitd; 3545 isoc->next = isoc->next + ncur; 3546 bp0 = OHCI_PAGE(buf + offs); 3547 ncur = 0; 3548 } 3549 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3550 /* XXX Sync */ 3551 offs = noffs; 3552 } 3553 KASSERT(j <= ox->ox_nsitd); 3554 3555 /* point at sentinel */ 3556 tail = opipe->tail.itd; 3557 memset(&tail->itd, 0, sizeof(tail->itd)); 3558 tail->nextitd = NULL; 3559 tail->xfer = NULL; 3560 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->itd), 3561 BUS_DMASYNC_PREWRITE); 3562 3563 /* Fixup last used ITD */ 3564 sitd->itd.itd_flags = HTOO32( 3565 OHCI_ITD_NOCC | 3566 OHCI_ITD_SET_SF(isoc->next) | 3567 OHCI_ITD_SET_DI(0) | 3568 OHCI_ITD_SET_FC(ncur)); 3569 sitd->itd.itd_bp0 = HTOO32(bp0); 3570 sitd->itd.itd_nextitd = HTOO32(tail->physaddr); 3571 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3572 sitd->nextitd = tail; 3573 sitd->xfer = xfer; 3574 sitd->flags = OHCI_CALL_DONE; 3575 #ifdef DIAGNOSTIC 3576 sitd->isdone = false; 3577 #endif 3578 ohci_hash_add_itd(sc, sitd); 3579 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3580 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3581 3582 isoc->next = isoc->next + ncur; 3583 isoc->inuse += nframes; 3584 3585 /* XXX pretend we did it all */ 3586 xfer->ux_actlen = offs; 3587 xfer->ux_status = USBD_IN_PROGRESS; 3588 3589 #ifdef OHCI_DEBUG 3590 if (ohcidebug >= 5) { 3591 DPRINTF("frame=%jd", O32TOH(sc->sc_hcca->hcca_frame_number), 3592 0, 0, 0); 3593 ohci_dump_itds(sc, xfer->ux_hcpriv); 3594 ohci_dump_ed(sc, sed); 3595 } 3596 #endif 3597 3598 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3599 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3600 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3601 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3602 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3603 sizeof(sed->ed.ed_flags), 3604 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3605 mutex_exit(&sc->sc_lock); 3606 } 3607 3608 void 3609 ohci_device_isoc_abort(struct usbd_xfer *xfer) 3610 { 3611 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3612 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3613 ohci_soft_ed_t *sed; 3614 ohci_soft_itd_t *sitd; 3615 3616 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3617 DPRINTFN(1, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3618 3619 KASSERT(mutex_owned(&sc->sc_lock)); 3620 3621 /* Transfer is already done. */ 3622 if (xfer->ux_status != USBD_NOT_STARTED && 3623 xfer->ux_status != USBD_IN_PROGRESS) { 3624 printf("ohci_device_isoc_abort: early return\n"); 3625 goto done; 3626 } 3627 3628 /* Give xfer the requested abort code. */ 3629 xfer->ux_status = USBD_CANCELLED; 3630 3631 sed = opipe->sed; 3632 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3633 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3634 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3635 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3636 sizeof(sed->ed.ed_flags), 3637 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3638 3639 sitd = xfer->ux_hcpriv; 3640 KASSERT(sitd); 3641 3642 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3643 3644 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3645 ohci_hash_rem_itd(sc, sitd); 3646 #ifdef DIAGNOSTIC 3647 DPRINTFN(1, "abort sets done sitd=%#jx", (uintptr_t)sitd, 3648 0, 0, 0); 3649 sitd->isdone = true; 3650 #endif 3651 } 3652 3653 /* Run callback. */ 3654 usb_transfer_complete(xfer); 3655 3656 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3657 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3658 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3659 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3660 3661 done: 3662 KASSERT(mutex_owned(&sc->sc_lock)); 3663 } 3664 3665 void 3666 ohci_device_isoc_done(struct usbd_xfer *xfer) 3667 { 3668 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3669 DPRINTFN(1, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3670 } 3671 3672 usbd_status 3673 ohci_setup_isoc(struct usbd_pipe *pipe) 3674 { 3675 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3676 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3677 struct isoc *isoc = &opipe->isoc; 3678 3679 isoc->next = -1; 3680 isoc->inuse = 0; 3681 3682 mutex_enter(&sc->sc_lock); 3683 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3684 mutex_exit(&sc->sc_lock); 3685 3686 return USBD_NORMAL_COMPLETION; 3687 } 3688 3689 void 3690 ohci_device_isoc_close(struct usbd_pipe *pipe) 3691 { 3692 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3693 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3694 3695 KASSERT(mutex_owned(&sc->sc_lock)); 3696 3697 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3698 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3699 ohci_close_pipe(pipe, sc->sc_isoc_head); 3700 #ifdef DIAGNOSTIC 3701 opipe->tail.itd->isdone = true; 3702 #endif 3703 ohci_free_sitd_locked(sc, opipe->tail.itd); 3704 } 3705
Indexes created Fri Oct 03 02:09:57 GMT 2025