ohci.c revision 1.289.4.6
1 /* $NetBSD: ohci.c,v 1.289.4.6 2020/12/12 20:29:11 martin Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * USB Open Host Controller driver. 38 * 39 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 40 * USB spec: http://www.usb.org/developers/docs/ 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.289.4.6 2020/12/12 20:29:11 martin Exp $"); 45 46 #ifdef _KERNEL_OPT 47 #include "opt_usb.h" 48 #endif 49 50 #include <sys/param.h> 51 52 #include <sys/cpu.h> 53 #include <sys/device.h> 54 #include <sys/kernel.h> 55 #include <sys/kmem.h> 56 #include <sys/proc.h> 57 #include <sys/queue.h> 58 #include <sys/select.h> 59 #include <sys/sysctl.h> 60 #include <sys/systm.h> 61 62 #include <machine/endian.h> 63 64 #include <dev/usb/usb.h> 65 #include <dev/usb/usbdi.h> 66 #include <dev/usb/usbdivar.h> 67 #include <dev/usb/usb_mem.h> 68 #include <dev/usb/usb_quirks.h> 69 70 #include <dev/usb/ohcireg.h> 71 #include <dev/usb/ohcivar.h> 72 #include <dev/usb/usbroothub.h> 73 #include <dev/usb/usbhist.h> 74 75 #ifdef USB_DEBUG 76 #ifndef OHCI_DEBUG 77 #define ohcidebug 0 78 #else 79 static int ohcidebug = 10; 80 81 SYSCTL_SETUP(sysctl_hw_ohci_setup, "sysctl hw.ohci setup") 82 { 83 int err; 84 const struct sysctlnode *rnode; 85 const struct sysctlnode *cnode; 86 87 err = sysctl_createv(clog, 0, NULL, &rnode, 88 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ohci", 89 SYSCTL_DESCR("ohci global controls"), 90 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 91 92 if (err) 93 goto fail; 94 95 /* control debugging printfs */ 96 err = sysctl_createv(clog, 0, &rnode, &cnode, 97 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 98 "debug", SYSCTL_DESCR("Enable debugging output"), 99 NULL, 0, &ohcidebug, sizeof(ohcidebug), CTL_CREATE, CTL_EOL); 100 if (err) 101 goto fail; 102 103 return; 104 fail: 105 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 106 } 107 108 #endif /* OHCI_DEBUG */ 109 #endif /* USB_DEBUG */ 110 111 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ohcidebug,FMT,A,B,C,D) 112 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ohcidebug,N,FMT,A,B,C,D) 113 #define OHCIHIST_FUNC() USBHIST_FUNC() 114 #define OHCIHIST_CALLED(name) USBHIST_CALLED(ohcidebug) 115 116 #if BYTE_ORDER == BIG_ENDIAN 117 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 118 #else 119 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 120 #endif 121 122 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 123 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 124 #define HTOO16(val) O16TOH(val) 125 #define HTOO32(val) O32TOH(val) 126 127 struct ohci_pipe; 128 129 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 130 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 131 132 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 133 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 134 Static void ohci_free_std_locked(ohci_softc_t *, ohci_soft_td_t *); 135 136 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 137 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 138 Static void ohci_free_sitd_locked(ohci_softc_t *, 139 ohci_soft_itd_t *); 140 141 Static int ohci_alloc_std_chain(ohci_softc_t *, struct usbd_xfer *, 142 int, int); 143 Static void ohci_free_stds(ohci_softc_t *, struct ohci_xfer *); 144 145 Static void ohci_reset_std_chain(ohci_softc_t *, struct usbd_xfer *, 146 int, int, ohci_soft_td_t *, ohci_soft_td_t **); 147 148 Static usbd_status ohci_open(struct usbd_pipe *); 149 Static void ohci_poll(struct usbd_bus *); 150 Static void ohci_softintr(void *); 151 Static void ohci_rhsc(ohci_softc_t *, struct usbd_xfer *); 152 Static void ohci_rhsc_softint(void *); 153 154 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 155 ohci_soft_ed_t *); 156 157 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 158 ohci_soft_ed_t *); 159 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 160 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 161 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 162 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 163 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 164 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 165 166 Static usbd_status ohci_setup_isoc(struct usbd_pipe *); 167 Static void ohci_device_isoc_enter(struct usbd_xfer *); 168 169 Static struct usbd_xfer * 170 ohci_allocx(struct usbd_bus *, unsigned int); 171 Static void ohci_freex(struct usbd_bus *, struct usbd_xfer *); 172 Static bool ohci_dying(struct usbd_bus *); 173 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 174 Static int ohci_roothub_ctrl(struct usbd_bus *, 175 usb_device_request_t *, void *, int); 176 177 Static usbd_status ohci_root_intr_transfer(struct usbd_xfer *); 178 Static usbd_status ohci_root_intr_start(struct usbd_xfer *); 179 Static void ohci_root_intr_abort(struct usbd_xfer *); 180 Static void ohci_root_intr_close(struct usbd_pipe *); 181 Static void ohci_root_intr_done(struct usbd_xfer *); 182 183 Static int ohci_device_ctrl_init(struct usbd_xfer *); 184 Static void ohci_device_ctrl_fini(struct usbd_xfer *); 185 Static usbd_status ohci_device_ctrl_transfer(struct usbd_xfer *); 186 Static usbd_status ohci_device_ctrl_start(struct usbd_xfer *); 187 Static void ohci_device_ctrl_abort(struct usbd_xfer *); 188 Static void ohci_device_ctrl_close(struct usbd_pipe *); 189 Static void ohci_device_ctrl_done(struct usbd_xfer *); 190 191 Static int ohci_device_bulk_init(struct usbd_xfer *); 192 Static void ohci_device_bulk_fini(struct usbd_xfer *); 193 Static usbd_status ohci_device_bulk_transfer(struct usbd_xfer *); 194 Static usbd_status ohci_device_bulk_start(struct usbd_xfer *); 195 Static void ohci_device_bulk_abort(struct usbd_xfer *); 196 Static void ohci_device_bulk_close(struct usbd_pipe *); 197 Static void ohci_device_bulk_done(struct usbd_xfer *); 198 199 Static int ohci_device_intr_init(struct usbd_xfer *); 200 Static void ohci_device_intr_fini(struct usbd_xfer *); 201 Static usbd_status ohci_device_intr_transfer(struct usbd_xfer *); 202 Static usbd_status ohci_device_intr_start(struct usbd_xfer *); 203 Static void ohci_device_intr_abort(struct usbd_xfer *); 204 Static void ohci_device_intr_close(struct usbd_pipe *); 205 Static void ohci_device_intr_done(struct usbd_xfer *); 206 207 Static int ohci_device_isoc_init(struct usbd_xfer *); 208 Static void ohci_device_isoc_fini(struct usbd_xfer *); 209 Static usbd_status ohci_device_isoc_transfer(struct usbd_xfer *); 210 Static void ohci_device_isoc_abort(struct usbd_xfer *); 211 Static void ohci_device_isoc_close(struct usbd_pipe *); 212 Static void ohci_device_isoc_done(struct usbd_xfer *); 213 214 Static usbd_status ohci_device_setintr(ohci_softc_t *, 215 struct ohci_pipe *, int); 216 217 Static void ohci_rhsc_enable(void *); 218 219 Static void ohci_close_pipe(struct usbd_pipe *, ohci_soft_ed_t *); 220 Static void ohci_abortx(struct usbd_xfer *); 221 222 Static void ohci_device_clear_toggle(struct usbd_pipe *); 223 Static void ohci_noop(struct usbd_pipe *); 224 225 #ifdef OHCI_DEBUG 226 Static void ohci_dumpregs(ohci_softc_t *); 227 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 228 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 229 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 230 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 231 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 232 #endif 233 234 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 235 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 236 #define OWRITE1(sc, r, x) \ 237 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 238 #define OWRITE2(sc, r, x) \ 239 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 240 #define OWRITE4(sc, r, x) \ 241 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 242 243 static __inline uint32_t 244 OREAD4(ohci_softc_t *sc, bus_size_t r) 245 { 246 247 OBARR(sc); 248 return bus_space_read_4(sc->iot, sc->ioh, r); 249 } 250 251 /* Reverse the bits in a value 0 .. 31 */ 252 Static uint8_t revbits[OHCI_NO_INTRS] = 253 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 254 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 255 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 256 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 257 258 struct ohci_pipe { 259 struct usbd_pipe pipe; 260 ohci_soft_ed_t *sed; 261 union { 262 ohci_soft_td_t *td; 263 ohci_soft_itd_t *itd; 264 } tail; 265 /* Info needed for different pipe kinds. */ 266 union { 267 /* Control pipe */ 268 struct { 269 usb_dma_t reqdma; 270 } ctrl; 271 /* Interrupt pipe */ 272 struct { 273 int nslots; 274 int pos; 275 } intr; 276 /* Isochronous pipe */ 277 struct isoc { 278 int next, inuse; 279 } isoc; 280 }; 281 }; 282 283 Static const struct usbd_bus_methods ohci_bus_methods = { 284 .ubm_open = ohci_open, 285 .ubm_softint = ohci_softintr, 286 .ubm_dopoll = ohci_poll, 287 .ubm_allocx = ohci_allocx, 288 .ubm_freex = ohci_freex, 289 .ubm_abortx = ohci_abortx, 290 .ubm_dying = ohci_dying, 291 .ubm_getlock = ohci_get_lock, 292 .ubm_rhctrl = ohci_roothub_ctrl, 293 }; 294 295 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 296 .upm_transfer = ohci_root_intr_transfer, 297 .upm_start = ohci_root_intr_start, 298 .upm_abort = ohci_root_intr_abort, 299 .upm_close = ohci_root_intr_close, 300 .upm_cleartoggle = ohci_noop, 301 .upm_done = ohci_root_intr_done, 302 }; 303 304 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 305 .upm_init = ohci_device_ctrl_init, 306 .upm_fini = ohci_device_ctrl_fini, 307 .upm_transfer = ohci_device_ctrl_transfer, 308 .upm_start = ohci_device_ctrl_start, 309 .upm_abort = ohci_device_ctrl_abort, 310 .upm_close = ohci_device_ctrl_close, 311 .upm_cleartoggle = ohci_noop, 312 .upm_done = ohci_device_ctrl_done, 313 }; 314 315 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 316 .upm_init = ohci_device_intr_init, 317 .upm_fini = ohci_device_intr_fini, 318 .upm_transfer = ohci_device_intr_transfer, 319 .upm_start = ohci_device_intr_start, 320 .upm_abort = ohci_device_intr_abort, 321 .upm_close = ohci_device_intr_close, 322 .upm_cleartoggle = ohci_device_clear_toggle, 323 .upm_done = ohci_device_intr_done, 324 }; 325 326 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 327 .upm_init = ohci_device_bulk_init, 328 .upm_fini = ohci_device_bulk_fini, 329 .upm_transfer = ohci_device_bulk_transfer, 330 .upm_start = ohci_device_bulk_start, 331 .upm_abort = ohci_device_bulk_abort, 332 .upm_close = ohci_device_bulk_close, 333 .upm_cleartoggle = ohci_device_clear_toggle, 334 .upm_done = ohci_device_bulk_done, 335 }; 336 337 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 338 .upm_init = ohci_device_isoc_init, 339 .upm_fini = ohci_device_isoc_fini, 340 .upm_transfer = ohci_device_isoc_transfer, 341 .upm_abort = ohci_device_isoc_abort, 342 .upm_close = ohci_device_isoc_close, 343 .upm_cleartoggle = ohci_noop, 344 .upm_done = ohci_device_isoc_done, 345 }; 346 347 int 348 ohci_activate(device_t self, enum devact act) 349 { 350 struct ohci_softc *sc = device_private(self); 351 352 switch (act) { 353 case DVACT_DEACTIVATE: 354 sc->sc_dying = 1; 355 return 0; 356 default: 357 return EOPNOTSUPP; 358 } 359 } 360 361 void 362 ohci_childdet(device_t self, device_t child) 363 { 364 struct ohci_softc *sc = device_private(self); 365 366 KASSERT(sc->sc_child == child); 367 sc->sc_child = NULL; 368 } 369 370 int 371 ohci_detach(struct ohci_softc *sc, int flags) 372 { 373 int rv = 0; 374 375 if (sc->sc_child != NULL) 376 rv = config_detach(sc->sc_child, flags); 377 378 if (rv != 0) 379 return rv; 380 381 softint_disestablish(sc->sc_rhsc_si); 382 383 callout_halt(&sc->sc_tmo_rhsc, NULL); 384 callout_destroy(&sc->sc_tmo_rhsc); 385 386 mutex_destroy(&sc->sc_lock); 387 mutex_destroy(&sc->sc_intr_lock); 388 389 if (sc->sc_hcca != NULL) 390 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 391 pool_cache_destroy(sc->sc_xferpool); 392 cv_destroy(&sc->sc_abort_cv); 393 394 return rv; 395 } 396 397 ohci_soft_ed_t * 398 ohci_alloc_sed(ohci_softc_t *sc) 399 { 400 ohci_soft_ed_t *sed; 401 usbd_status err; 402 int i, offs; 403 usb_dma_t dma; 404 405 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 406 407 mutex_enter(&sc->sc_lock); 408 if (sc->sc_freeeds == NULL) { 409 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 410 mutex_exit(&sc->sc_lock); 411 412 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 413 OHCI_ED_ALIGN, &dma); 414 if (err) 415 return 0; 416 417 mutex_enter(&sc->sc_lock); 418 for (i = 0; i < OHCI_SED_CHUNK; i++) { 419 offs = i * OHCI_SED_SIZE; 420 sed = KERNADDR(&dma, offs); 421 sed->physaddr = DMAADDR(&dma, offs); 422 sed->dma = dma; 423 sed->offs = offs; 424 sed->next = sc->sc_freeeds; 425 sc->sc_freeeds = sed; 426 } 427 } 428 sed = sc->sc_freeeds; 429 sc->sc_freeeds = sed->next; 430 mutex_exit(&sc->sc_lock); 431 432 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 433 sed->next = 0; 434 return sed; 435 } 436 437 static inline void 438 ohci_free_sed_locked(ohci_softc_t *sc, ohci_soft_ed_t *sed) 439 { 440 441 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 442 443 sed->next = sc->sc_freeeds; 444 sc->sc_freeeds = sed; 445 } 446 447 void 448 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 449 { 450 451 mutex_enter(&sc->sc_lock); 452 ohci_free_sed_locked(sc, sed); 453 mutex_exit(&sc->sc_lock); 454 } 455 456 ohci_soft_td_t * 457 ohci_alloc_std(ohci_softc_t *sc) 458 { 459 ohci_soft_td_t *std; 460 usbd_status err; 461 int i, offs; 462 usb_dma_t dma; 463 464 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 465 466 mutex_enter(&sc->sc_lock); 467 if (sc->sc_freetds == NULL) { 468 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 469 mutex_exit(&sc->sc_lock); 470 471 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 472 OHCI_TD_ALIGN, &dma); 473 if (err) 474 return NULL; 475 476 mutex_enter(&sc->sc_lock); 477 for (i = 0; i < OHCI_STD_CHUNK; i++) { 478 offs = i * OHCI_STD_SIZE; 479 std = KERNADDR(&dma, offs); 480 std->physaddr = DMAADDR(&dma, offs); 481 std->dma = dma; 482 std->offs = offs; 483 std->nexttd = sc->sc_freetds; 484 sc->sc_freetds = std; 485 } 486 } 487 488 std = sc->sc_freetds; 489 sc->sc_freetds = std->nexttd; 490 mutex_exit(&sc->sc_lock); 491 492 memset(&std->td, 0, sizeof(ohci_td_t)); 493 std->nexttd = NULL; 494 std->xfer = NULL; 495 std->held = NULL; 496 497 return std; 498 } 499 500 void 501 ohci_free_std_locked(ohci_softc_t *sc, ohci_soft_td_t *std) 502 { 503 504 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 505 506 std->nexttd = sc->sc_freetds; 507 sc->sc_freetds = std; 508 } 509 510 void 511 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 512 { 513 514 mutex_enter(&sc->sc_lock); 515 ohci_free_std_locked(sc, std); 516 mutex_exit(&sc->sc_lock); 517 } 518 519 Static int 520 ohci_alloc_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, int length, int rd) 521 { 522 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 523 uint16_t flags = xfer->ux_flags; 524 525 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 526 527 DPRINTFN(8, "addr=%jd endpt=%jd len=%jd speed=%jd", 528 xfer->ux_pipe->up_dev->ud_addr, 529 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 530 length, xfer->ux_pipe->up_dev->ud_speed); 531 532 ASSERT_SLEEPABLE(); 533 KASSERT(length != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 534 535 size_t nstd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 536 nstd += ((length + OHCI_PAGE_SIZE - 1) / OHCI_PAGE_SIZE); 537 ox->ox_stds = kmem_zalloc(sizeof(ohci_soft_td_t *) * nstd, 538 KM_SLEEP); 539 ox->ox_nstd = nstd; 540 541 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, nstd, 0, 0); 542 543 for (size_t j = 0; j < ox->ox_nstd; j++) { 544 ohci_soft_td_t *cur = ohci_alloc_std(sc); 545 if (cur == NULL) 546 goto nomem; 547 548 ox->ox_stds[j] = cur; 549 cur->held = &ox->ox_stds[j]; 550 cur->xfer = xfer; 551 cur->flags = 0; 552 DPRINTFN(10, "xfer=%#jx new std=%#jx held at %#jx", (uintptr_t)ox, 553 (uintptr_t)cur, (uintptr_t)cur->held, 0); 554 } 555 556 return 0; 557 558 nomem: 559 ohci_free_stds(sc, ox); 560 kmem_free(ox->ox_stds, sizeof(ohci_soft_td_t *) * nstd); 561 562 return ENOMEM; 563 } 564 565 Static void 566 ohci_free_stds(ohci_softc_t *sc, struct ohci_xfer *ox) 567 { 568 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 569 DPRINTF("ox=%#jx", (uintptr_t)ox, 0, 0, 0); 570 571 mutex_enter(&sc->sc_lock); 572 for (size_t i = 0; i < ox->ox_nstd; i++) { 573 ohci_soft_td_t *std = ox->ox_stds[i]; 574 if (std == NULL) 575 break; 576 ohci_free_std_locked(sc, std); 577 } 578 mutex_exit(&sc->sc_lock); 579 } 580 581 void 582 ohci_reset_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, 583 int alen, int rd, ohci_soft_td_t *sp, ohci_soft_td_t **ep) 584 { 585 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 586 ohci_soft_td_t *next, *cur; 587 int len, curlen; 588 usb_dma_t *dma = &xfer->ux_dmabuf; 589 uint16_t flags = xfer->ux_flags; 590 591 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 592 DPRINTF("start len=%jd", alen, 0, 0, 0); 593 594 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 595 596 DPRINTFN(8, "addr=%jd endpt=%jd len=%jd speed=%jd", 597 xfer->ux_pipe->up_dev->ud_addr, 598 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 599 alen, xfer->ux_pipe->up_dev->ud_speed); 600 601 KASSERT(sp); 602 603 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 604 605 /* 606 * Assign next for the len == 0 case where we don't go through the 607 * main loop. 608 */ 609 len = alen; 610 cur = next = sp; 611 612 usb_syncmem(dma, 0, len, 613 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 614 const uint32_t tdflags = HTOO32( 615 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 616 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 617 618 size_t curoffs = 0; 619 for (size_t j = 1; len != 0;) { 620 if (j == ox->ox_nstd) 621 next = NULL; 622 else 623 next = ox->ox_stds[j++]; 624 KASSERT(next != cur); 625 626 curlen = 0; 627 const ohci_physaddr_t sdataphys = DMAADDR(dma, curoffs); 628 ohci_physaddr_t edataphys = DMAADDR(dma, curoffs + len - 1); 629 630 const ohci_physaddr_t sphyspg = OHCI_PAGE(sdataphys); 631 ohci_physaddr_t ephyspg = OHCI_PAGE(edataphys); 632 /* 633 * The OHCI hardware can handle at most one page 634 * crossing per TD 635 */ 636 curlen = len; 637 if (sphyspg != ephyspg && 638 sphyspg + OHCI_PAGE_SIZE != ephyspg) { 639 /* must use multiple TDs, fill as much as possible. */ 640 curlen = 2 * OHCI_PAGE_SIZE - 641 OHCI_PAGE_OFFSET(sdataphys); 642 /* the length must be a multiple of the max size */ 643 curlen -= curlen % mps; 644 edataphys = DMAADDR(dma, curoffs + curlen - 1); 645 } 646 KASSERT(curlen != 0); 647 DPRINTFN(4, "sdataphys=0x%08jx edataphys=0x%08jx " 648 "len=%jd curlen=%jd", sdataphys, edataphys, len, curlen); 649 650 cur->td.td_flags = tdflags; 651 cur->td.td_cbp = HTOO32(sdataphys); 652 cur->td.td_be = HTOO32(edataphys); 653 cur->td.td_nexttd = (next != NULL) ? HTOO32(next->physaddr) : 0; 654 cur->nexttd = next; 655 cur->len = curlen; 656 cur->flags = OHCI_ADD_LEN; 657 cur->xfer = xfer; 658 ohci_hash_add_td(sc, cur); 659 660 curoffs += curlen; 661 len -= curlen; 662 663 if (len != 0) { 664 KASSERT(next != NULL); 665 DPRINTFN(10, "extend chain", 0, 0, 0, 0); 666 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 667 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 668 669 cur = next; 670 } 671 } 672 cur->td.td_flags |= 673 HTOO32(xfer->ux_flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0); 674 675 if (!rd && 676 (flags & USBD_FORCE_SHORT_XFER) && 677 alen % mps == 0) { 678 /* We're adding a ZLP so sync the previous TD */ 679 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 680 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 681 682 /* Force a 0 length transfer at the end. */ 683 684 KASSERT(next != NULL); 685 cur = next; 686 687 cur->td.td_flags = tdflags; 688 cur->td.td_cbp = 0; /* indicate 0 length packet */ 689 cur->td.td_nexttd = 0; 690 cur->td.td_be = ~0; 691 cur->nexttd = NULL; 692 cur->len = 0; 693 cur->flags = 0; 694 cur->xfer = xfer; 695 ohci_hash_add_td(sc, cur); 696 697 DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0); 698 } 699 700 /* Last TD gets usb_syncmem'ed by caller */ 701 *ep = cur; 702 } 703 704 ohci_soft_itd_t * 705 ohci_alloc_sitd(ohci_softc_t *sc) 706 { 707 ohci_soft_itd_t *sitd; 708 usbd_status err; 709 int i, offs; 710 usb_dma_t dma; 711 712 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 713 714 mutex_enter(&sc->sc_lock); 715 if (sc->sc_freeitds == NULL) { 716 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 717 mutex_exit(&sc->sc_lock); 718 719 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 720 OHCI_ITD_ALIGN, &dma); 721 if (err) 722 return NULL; 723 mutex_enter(&sc->sc_lock); 724 for (i = 0; i < OHCI_SITD_CHUNK; i++) { 725 offs = i * OHCI_SITD_SIZE; 726 sitd = KERNADDR(&dma, offs); 727 sitd->physaddr = DMAADDR(&dma, offs); 728 sitd->dma = dma; 729 sitd->offs = offs; 730 sitd->nextitd = sc->sc_freeitds; 731 sc->sc_freeitds = sitd; 732 } 733 } 734 735 sitd = sc->sc_freeitds; 736 sc->sc_freeitds = sitd->nextitd; 737 mutex_exit(&sc->sc_lock); 738 739 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 740 sitd->nextitd = NULL; 741 sitd->xfer = NULL; 742 743 #ifdef DIAGNOSTIC 744 sitd->isdone = true; 745 #endif 746 747 return sitd; 748 } 749 750 Static void 751 ohci_free_sitd_locked(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 752 { 753 754 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 755 DPRINTFN(10, "sitd=%#jx", (uintptr_t)sitd, 0, 0, 0); 756 757 KASSERT(sitd->isdone); 758 #ifdef DIAGNOSTIC 759 /* Warn double free */ 760 sitd->isdone = false; 761 #endif 762 763 sitd->nextitd = sc->sc_freeitds; 764 sc->sc_freeitds = sitd; 765 } 766 767 void 768 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 769 { 770 771 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 772 773 mutex_enter(&sc->sc_lock); 774 ohci_free_sitd_locked(sc, sitd); 775 mutex_exit(&sc->sc_lock); 776 } 777 778 int 779 ohci_init(ohci_softc_t *sc) 780 { 781 ohci_soft_ed_t *sed, *psed; 782 usbd_status err; 783 int i; 784 uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */; 785 786 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 787 788 aprint_normal_dev(sc->sc_dev, ""); 789 790 sc->sc_hcca = NULL; 791 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 792 793 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 794 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 795 796 sc->sc_rhsc_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 797 ohci_rhsc_softint, sc); 798 799 for (i = 0; i < OHCI_HASH_SIZE; i++) 800 LIST_INIT(&sc->sc_hash_tds[i]); 801 for (i = 0; i < OHCI_HASH_SIZE; i++) 802 LIST_INIT(&sc->sc_hash_itds[i]); 803 804 TAILQ_INIT(&sc->sc_abortingxfers); 805 cv_init(&sc->sc_abort_cv, "ohciabt"); 806 807 sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0, 808 "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL); 809 810 rev = OREAD4(sc, OHCI_REVISION); 811 aprint_normal("OHCI version %d.%d%s\n", 812 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 813 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 814 815 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 816 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 817 sc->sc_bus.ub_revision = USBREV_UNKNOWN; 818 return -1; 819 } 820 sc->sc_bus.ub_revision = USBREV_1_0; 821 sc->sc_bus.ub_usedma = true; 822 823 /* XXX determine alignment by R/W */ 824 /* Allocate the HCCA area. */ 825 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 826 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 827 if (err) { 828 sc->sc_hcca = NULL; 829 return err; 830 } 831 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 832 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 833 834 sc->sc_eintrs = OHCI_NORMAL_INTRS; 835 836 /* Allocate dummy ED that starts the control list. */ 837 sc->sc_ctrl_head = ohci_alloc_sed(sc); 838 if (sc->sc_ctrl_head == NULL) { 839 err = ENOMEM; 840 goto bad1; 841 } 842 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 843 844 /* Allocate dummy ED that starts the bulk list. */ 845 sc->sc_bulk_head = ohci_alloc_sed(sc); 846 if (sc->sc_bulk_head == NULL) { 847 err = ENOMEM; 848 goto bad2; 849 } 850 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 851 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 852 sizeof(sc->sc_bulk_head->ed), 853 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 854 855 /* Allocate dummy ED that starts the isochronous list. */ 856 sc->sc_isoc_head = ohci_alloc_sed(sc); 857 if (sc->sc_isoc_head == NULL) { 858 err = ENOMEM; 859 goto bad3; 860 } 861 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 862 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 863 sizeof(sc->sc_isoc_head->ed), 864 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 865 866 /* Allocate all the dummy EDs that make up the interrupt tree. */ 867 for (i = 0; i < OHCI_NO_EDS; i++) { 868 sed = ohci_alloc_sed(sc); 869 if (sed == NULL) { 870 while (--i >= 0) 871 ohci_free_sed(sc, sc->sc_eds[i]); 872 err = ENOMEM; 873 goto bad4; 874 } 875 /* All ED fields are set to 0. */ 876 sc->sc_eds[i] = sed; 877 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 878 if (i != 0) 879 psed = sc->sc_eds[(i-1) / 2]; 880 else 881 psed= sc->sc_isoc_head; 882 sed->next = psed; 883 sed->ed.ed_nexted = HTOO32(psed->physaddr); 884 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 885 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 886 } 887 /* 888 * Fill HCCA interrupt table. The bit reversal is to get 889 * the tree set up properly to spread the interrupts. 890 */ 891 for (i = 0; i < OHCI_NO_INTRS; i++) 892 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 893 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 894 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 895 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 896 897 #ifdef OHCI_DEBUG 898 DPRINTFN(15, "--- dump start ---", 0, 0, 0 ,0); 899 if (ohcidebug >= 15) { 900 for (i = 0; i < OHCI_NO_EDS; i++) { 901 DPRINTFN(15, "ed#%jd ", i, 0, 0, 0); 902 ohci_dump_ed(sc, sc->sc_eds[i]); 903 } 904 DPRINTFN(15, "iso", 0, 0, 0 ,0); 905 ohci_dump_ed(sc, sc->sc_isoc_head); 906 } 907 DPRINTFN(15, "--- dump end ---", 0, 0, 0 ,0); 908 #endif 909 910 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 911 ctl = OREAD4(sc, OHCI_CONTROL); 912 rwc = ctl & OHCI_RWC; 913 fm = OREAD4(sc, OHCI_FM_INTERVAL); 914 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 915 /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */ 916 917 /* Determine in what context we are running. */ 918 if (ctl & OHCI_IR) { 919 /* SMM active, request change */ 920 DPRINTF("SMM active, request owner change", 0, 0, 0, 0); 921 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 922 (OHCI_OC | OHCI_MIE)) 923 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 924 s = OREAD4(sc, OHCI_COMMAND_STATUS); 925 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 926 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 927 usb_delay_ms(&sc->sc_bus, 1); 928 ctl = OREAD4(sc, OHCI_CONTROL); 929 } 930 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 931 if ((ctl & OHCI_IR) == 0) { 932 aprint_error_dev(sc->sc_dev, 933 "SMM does not respond, resetting\n"); 934 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 935 goto reset; 936 } 937 #if 0 938 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 939 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 940 /* BIOS started controller. */ 941 DPRINTF("BIOS active", 0, 0, 0, 0); 942 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 943 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 944 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 945 } 946 #endif 947 } else { 948 DPRINTF("cold started", 0 ,0 ,0 ,0); 949 reset: 950 /* Controller was cold started. */ 951 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 952 } 953 954 /* 955 * This reset should not be necessary according to the OHCI spec, but 956 * without it some controllers do not start. 957 */ 958 DPRINTF("sc %#jx: resetting", (uintptr_t)sc, 0, 0, 0); 959 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 960 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 961 962 /* We now own the host controller and the bus has been reset. */ 963 964 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 965 /* Nominal time for a reset is 10 us. */ 966 for (i = 0; i < 10; i++) { 967 delay(10); 968 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 969 if (!hcr) 970 break; 971 } 972 if (hcr) { 973 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 974 err = EIO; 975 goto bad5; 976 } 977 #ifdef OHCI_DEBUG 978 if (ohcidebug >= 15) 979 ohci_dumpregs(sc); 980 #endif 981 982 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 983 984 /* Set up HC registers. */ 985 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 986 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 987 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 988 /* disable all interrupts and then switch on all desired interrupts */ 989 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 990 /* switch on desired functional features */ 991 ctl = OREAD4(sc, OHCI_CONTROL); 992 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 993 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 994 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 995 /* And finally start it! */ 996 OWRITE4(sc, OHCI_CONTROL, ctl); 997 998 /* 999 * The controller is now OPERATIONAL. Set a some final 1000 * registers that should be set earlier, but that the 1001 * controller ignores when in the SUSPEND state. 1002 */ 1003 ival = OHCI_GET_IVAL(fm); 1004 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 1005 fm |= OHCI_FSMPS(ival) | ival; 1006 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 1007 per = OHCI_PERIODIC(ival); /* 90% periodic */ 1008 OWRITE4(sc, OHCI_PERIODIC_START, per); 1009 1010 if (sc->sc_flags & OHCIF_SUPERIO) { 1011 /* no overcurrent protection */ 1012 desca |= OHCI_NOCP; 1013 /* 1014 * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning 1015 * that 1016 * - ports are always power switched 1017 * - don't wait for powered root hub port 1018 */ 1019 desca &= ~(__SHIFTIN(0xff, OHCI_POTPGT_MASK) | OHCI_NPS); 1020 } 1021 1022 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 1023 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 1024 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 1025 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 1026 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 1027 1028 /* 1029 * The AMD756 requires a delay before re-reading the register, 1030 * otherwise it will occasionally report 0 ports. 1031 */ 1032 sc->sc_noport = 0; 1033 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 1034 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 1035 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 1036 } 1037 1038 #ifdef OHCI_DEBUG 1039 if (ohcidebug >= 5) 1040 ohci_dumpregs(sc); 1041 #endif 1042 1043 /* Set up the bus struct. */ 1044 sc->sc_bus.ub_methods = &ohci_bus_methods; 1045 sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe); 1046 1047 sc->sc_control = sc->sc_intre = 0; 1048 1049 /* Finally, turn on interrupts. */ 1050 DPRINTF("enabling %#jx", sc->sc_eintrs | OHCI_MIE, 0, 0, 0); 1051 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 1052 1053 return 0; 1054 1055 bad5: 1056 for (i = 0; i < OHCI_NO_EDS; i++) 1057 ohci_free_sed(sc, sc->sc_eds[i]); 1058 bad4: 1059 ohci_free_sed(sc, sc->sc_isoc_head); 1060 bad3: 1061 ohci_free_sed(sc, sc->sc_bulk_head); 1062 bad2: 1063 ohci_free_sed(sc, sc->sc_ctrl_head); 1064 bad1: 1065 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 1066 sc->sc_hcca = NULL; 1067 return err; 1068 } 1069 1070 struct usbd_xfer * 1071 ohci_allocx(struct usbd_bus *bus, unsigned int nframes) 1072 { 1073 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1074 struct usbd_xfer *xfer; 1075 1076 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 1077 if (xfer != NULL) { 1078 memset(xfer, 0, sizeof(struct ohci_xfer)); 1079 1080 #ifdef DIAGNOSTIC 1081 xfer->ux_state = XFER_BUSY; 1082 #endif 1083 } 1084 return xfer; 1085 } 1086 1087 void 1088 ohci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1089 { 1090 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1091 1092 KASSERTMSG(xfer->ux_state == XFER_BUSY || 1093 xfer->ux_status == USBD_NOT_STARTED, 1094 "xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state); 1095 #ifdef DIAGNOSTIC 1096 xfer->ux_state = XFER_FREE; 1097 #endif 1098 pool_cache_put(sc->sc_xferpool, xfer); 1099 } 1100 1101 Static bool 1102 ohci_dying(struct usbd_bus *bus) 1103 { 1104 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1105 1106 return sc->sc_dying; 1107 } 1108 1109 Static void 1110 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1111 { 1112 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1113 1114 *lock = &sc->sc_lock; 1115 } 1116 1117 /* 1118 * Shut down the controller when the system is going down. 1119 */ 1120 bool 1121 ohci_shutdown(device_t self, int flags) 1122 { 1123 ohci_softc_t *sc = device_private(self); 1124 1125 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1126 1127 DPRINTF("stopping the HC", 0, 0, 0, 0); 1128 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 1129 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1130 return true; 1131 } 1132 1133 bool 1134 ohci_resume(device_t dv, const pmf_qual_t *qual) 1135 { 1136 ohci_softc_t *sc = device_private(dv); 1137 uint32_t ctl; 1138 1139 mutex_spin_enter(&sc->sc_intr_lock); 1140 sc->sc_bus.ub_usepolling++; 1141 mutex_spin_exit(&sc->sc_intr_lock); 1142 1143 /* Some broken BIOSes do not recover these values */ 1144 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1145 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1146 sc->sc_ctrl_head->physaddr); 1147 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1148 sc->sc_bulk_head->physaddr); 1149 if (sc->sc_intre) 1150 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1151 (OHCI_ALL_INTRS | OHCI_MIE)); 1152 if (sc->sc_control) 1153 ctl = sc->sc_control; 1154 else 1155 ctl = OREAD4(sc, OHCI_CONTROL); 1156 ctl |= OHCI_HCFS_RESUME; 1157 OWRITE4(sc, OHCI_CONTROL, ctl); 1158 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1159 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1160 OWRITE4(sc, OHCI_CONTROL, ctl); 1161 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1162 sc->sc_control = sc->sc_intre = 0; 1163 1164 mutex_spin_enter(&sc->sc_intr_lock); 1165 sc->sc_bus.ub_usepolling--; 1166 mutex_spin_exit(&sc->sc_intr_lock); 1167 1168 return true; 1169 } 1170 1171 bool 1172 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1173 { 1174 ohci_softc_t *sc = device_private(dv); 1175 uint32_t ctl; 1176 1177 mutex_spin_enter(&sc->sc_intr_lock); 1178 sc->sc_bus.ub_usepolling++; 1179 mutex_spin_exit(&sc->sc_intr_lock); 1180 1181 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1182 if (sc->sc_control == 0) { 1183 /* 1184 * Preserve register values, in case that BIOS 1185 * does not recover them. 1186 */ 1187 sc->sc_control = ctl; 1188 sc->sc_intre = OREAD4(sc, 1189 OHCI_INTERRUPT_ENABLE); 1190 } 1191 ctl |= OHCI_HCFS_SUSPEND; 1192 OWRITE4(sc, OHCI_CONTROL, ctl); 1193 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1194 1195 mutex_spin_enter(&sc->sc_intr_lock); 1196 sc->sc_bus.ub_usepolling--; 1197 mutex_spin_exit(&sc->sc_intr_lock); 1198 1199 return true; 1200 } 1201 1202 #ifdef OHCI_DEBUG 1203 void 1204 ohci_dumpregs(ohci_softc_t *sc) 1205 { 1206 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1207 1208 DPRINTF("rev=0x%08jx control=0x%08jx command=0x%08jx", 1209 OREAD4(sc, OHCI_REVISION), 1210 OREAD4(sc, OHCI_CONTROL), 1211 OREAD4(sc, OHCI_COMMAND_STATUS), 0); 1212 DPRINTF(" intrstat=0x%08jx intre=0x%08jx intrd=0x%08jx", 1213 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1214 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1215 OREAD4(sc, OHCI_INTERRUPT_DISABLE), 0); 1216 DPRINTF(" hcca=0x%08jx percur=0x%08jx ctrlhd=0x%08jx", 1217 OREAD4(sc, OHCI_HCCA), 1218 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1219 OREAD4(sc, OHCI_CONTROL_HEAD_ED), 0); 1220 DPRINTF(" ctrlcur=0x%08jx bulkhd=0x%08jx bulkcur=0x%08jx", 1221 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1222 OREAD4(sc, OHCI_BULK_HEAD_ED), 1223 OREAD4(sc, OHCI_BULK_CURRENT_ED) ,0); 1224 DPRINTF(" done=0x%08jx fmival=0x%08jx fmrem=0x%08jx", 1225 OREAD4(sc, OHCI_DONE_HEAD), 1226 OREAD4(sc, OHCI_FM_INTERVAL), 1227 OREAD4(sc, OHCI_FM_REMAINING), 0); 1228 DPRINTF(" fmnum=0x%08jx perst=0x%08jx lsthrs=0x%08jx", 1229 OREAD4(sc, OHCI_FM_NUMBER), 1230 OREAD4(sc, OHCI_PERIODIC_START), 1231 OREAD4(sc, OHCI_LS_THRESHOLD), 0); 1232 DPRINTF(" desca=0x%08jx descb=0x%08jx stat=0x%08jx", 1233 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1234 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1235 OREAD4(sc, OHCI_RH_STATUS), 0); 1236 DPRINTF(" port1=0x%08jx port2=0x%08jx", 1237 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1238 OREAD4(sc, OHCI_RH_PORT_STATUS(2)), 0, 0); 1239 DPRINTF(" HCCA: frame_number=0x%04jx done_head=0x%08jx", 1240 O32TOH(sc->sc_hcca->hcca_frame_number), 1241 O32TOH(sc->sc_hcca->hcca_done_head), 0, 0); 1242 } 1243 #endif 1244 1245 Static int ohci_intr1(ohci_softc_t *); 1246 1247 int 1248 ohci_intr(void *p) 1249 { 1250 ohci_softc_t *sc = p; 1251 int ret = 0; 1252 1253 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1254 1255 if (sc == NULL) 1256 return 0; 1257 1258 mutex_spin_enter(&sc->sc_intr_lock); 1259 1260 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1261 goto done; 1262 1263 /* If we get an interrupt while polling, then just ignore it. */ 1264 if (sc->sc_bus.ub_usepolling) { 1265 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1266 /* for level triggered intrs, should do something to ack */ 1267 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1268 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1269 1270 goto done; 1271 } 1272 1273 ret = ohci_intr1(sc); 1274 1275 done: 1276 mutex_spin_exit(&sc->sc_intr_lock); 1277 return ret; 1278 } 1279 1280 Static int 1281 ohci_intr1(ohci_softc_t *sc) 1282 { 1283 uint32_t intrs, eintrs; 1284 1285 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1286 1287 /* In case the interrupt occurs before initialization has completed. */ 1288 if (sc == NULL || sc->sc_hcca == NULL) { 1289 #ifdef DIAGNOSTIC 1290 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1291 #endif 1292 return 0; 1293 } 1294 1295 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1296 1297 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1298 if (!intrs) 1299 return 0; 1300 1301 /* Acknowledge */ 1302 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); 1303 eintrs = intrs & sc->sc_eintrs; 1304 DPRINTFN(7, "sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1305 DPRINTFN(7, "intrs=%#jx(%#jx) eintrs=%#jx(%#jx)", 1306 intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), eintrs, 1307 sc->sc_eintrs); 1308 1309 if (!eintrs) { 1310 return 0; 1311 } 1312 1313 if (eintrs & OHCI_SO) { 1314 sc->sc_overrun_cnt++; 1315 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1316 printf("%s: %u scheduling overruns\n", 1317 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1318 sc->sc_overrun_cnt = 0; 1319 } 1320 /* XXX do what */ 1321 eintrs &= ~OHCI_SO; 1322 } 1323 if (eintrs & OHCI_WDH) { 1324 /* 1325 * We block the interrupt below, and reenable it later from 1326 * ohci_softintr(). 1327 */ 1328 usb_schedsoftintr(&sc->sc_bus); 1329 } 1330 if (eintrs & OHCI_SF) { 1331 struct ohci_xfer *ox, *tmp; 1332 TAILQ_FOREACH_SAFE(ox, &sc->sc_abortingxfers, ox_abnext, tmp) { 1333 DPRINTFN(10, "SF %#jx xfer %#jx", (uintptr_t)sc, 1334 (uintptr_t)ox, 0, 0); 1335 ox->ox_abintrs &= ~OHCI_SF; 1336 KASSERT(ox->ox_abintrs == 0); 1337 TAILQ_REMOVE(&sc->sc_abortingxfers, ox, ox_abnext); 1338 } 1339 cv_broadcast(&sc->sc_abort_cv); 1340 1341 KASSERT(TAILQ_EMPTY(&sc->sc_abortingxfers)); 1342 DPRINTFN(10, "end SOF %#jx", (uintptr_t)sc, 0, 0, 0); 1343 /* Don't remove OHIC_SF from eintrs so it is blocked below */ 1344 } 1345 if (eintrs & OHCI_RD) { 1346 DPRINTFN(5, "resume detect sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1347 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1348 /* XXX process resume detect */ 1349 } 1350 if (eintrs & OHCI_UE) { 1351 DPRINTFN(5, "unrecoverable error sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1352 printf("%s: unrecoverable error, controller halted\n", 1353 device_xname(sc->sc_dev)); 1354 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1355 /* XXX what else */ 1356 } 1357 if (eintrs & OHCI_RHSC) { 1358 /* 1359 * We block the interrupt below, and reenable it later from 1360 * a timeout. 1361 */ 1362 softint_schedule(sc->sc_rhsc_si); 1363 } 1364 1365 if (eintrs != 0) { 1366 /* Block unprocessed interrupts. */ 1367 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1368 sc->sc_eintrs &= ~eintrs; 1369 DPRINTF("sc %#jx blocking intrs 0x%jx", (uintptr_t)sc, 1370 eintrs, 0, 0); 1371 } 1372 1373 return 1; 1374 } 1375 1376 void 1377 ohci_rhsc_enable(void *v_sc) 1378 { 1379 ohci_softc_t *sc = v_sc; 1380 1381 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1382 DPRINTF("sc %#jx", (uintptr_t)sc, 0, 0, 0); 1383 mutex_spin_enter(&sc->sc_intr_lock); 1384 sc->sc_eintrs |= OHCI_RHSC; 1385 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1386 mutex_spin_exit(&sc->sc_intr_lock); 1387 } 1388 1389 #ifdef OHCI_DEBUG 1390 const char *ohci_cc_strs[] = { 1391 "NO_ERROR", 1392 "CRC", 1393 "BIT_STUFFING", 1394 "DATA_TOGGLE_MISMATCH", 1395 "STALL", 1396 "DEVICE_NOT_RESPONDING", 1397 "PID_CHECK_FAILURE", 1398 "UNEXPECTED_PID", 1399 "DATA_OVERRUN", 1400 "DATA_UNDERRUN", 1401 "BUFFER_OVERRUN", 1402 "BUFFER_UNDERRUN", 1403 "reserved", 1404 "reserved", 1405 "NOT_ACCESSED", 1406 "NOT_ACCESSED", 1407 }; 1408 #endif 1409 1410 void 1411 ohci_softintr(void *v) 1412 { 1413 struct usbd_bus *bus = v; 1414 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1415 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1416 ohci_soft_td_t *std, *sdone, *stdnext; 1417 struct usbd_xfer *xfer; 1418 struct ohci_pipe *opipe; 1419 int len, cc; 1420 int i, j, actlen, iframes, uedir; 1421 ohci_physaddr_t done = 0; 1422 1423 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1424 1425 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1426 1427 /* 1428 * Only read hccadone if WDH is set - we might get here from places 1429 * other than an interrupt 1430 */ 1431 if (!(OREAD4(sc, OHCI_INTERRUPT_STATUS) & OHCI_WDH)) { 1432 DPRINTFN(10, "no WDH %#jx", (uintptr_t)sc, 0, 0, 0); 1433 return; 1434 } 1435 1436 DPRINTFN(10, "WDH %#jx", (uintptr_t)sc, 0, 0, 0); 1437 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1438 sizeof(sc->sc_hcca->hcca_done_head), 1439 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1440 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1441 sc->sc_hcca->hcca_done_head = 0; 1442 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1443 sizeof(sc->sc_hcca->hcca_done_head), 1444 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1445 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1446 sc->sc_eintrs |= OHCI_WDH; 1447 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1448 1449 /* Reverse the done list. */ 1450 for (sdone = NULL, sidone = NULL; done != 0; ) { 1451 std = ohci_hash_find_td(sc, done); 1452 if (std != NULL) { 1453 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1454 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1455 std->dnext = sdone; 1456 done = O32TOH(std->td.td_nexttd); 1457 sdone = std; 1458 DPRINTFN(10, "add TD %#jx", (uintptr_t)std, 0, 0, 0); 1459 continue; 1460 } 1461 sitd = ohci_hash_find_itd(sc, done); 1462 if (sitd != NULL) { 1463 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1464 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1465 sitd->dnext = sidone; 1466 done = O32TOH(sitd->itd.itd_nextitd); 1467 sidone = sitd; 1468 DPRINTFN(5, "add ITD %#jx", (uintptr_t)sitd, 0, 0, 0); 1469 continue; 1470 } 1471 DPRINTFN(10, "addr %#jx not found", (uintptr_t)done, 0, 0, 0); 1472 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1473 (u_long)done); 1474 break; 1475 } 1476 1477 DPRINTFN(10, "sdone=%#jx sidone=%#jx", (uintptr_t)sdone, 1478 (uintptr_t)sidone, 0, 0); 1479 DPRINTFN(10, "--- TD dump start ---", 0, 0, 0, 0); 1480 #ifdef OHCI_DEBUG 1481 if (ohcidebug >= 10) { 1482 for (std = sdone; std; std = std->dnext) 1483 ohci_dump_td(sc, std); 1484 } 1485 #endif 1486 DPRINTFN(10, "--- TD dump end ---", 0, 0, 0, 0); 1487 1488 for (std = sdone; std; std = stdnext) { 1489 stdnext = std->dnext; 1490 if (std->held == NULL) { 1491 DPRINTFN(10, "std=%#jx held is null", (uintptr_t)std, 1492 0, 0, 0); 1493 ohci_hash_rem_td(sc, std); 1494 ohci_free_std_locked(sc, std); 1495 continue; 1496 } 1497 1498 xfer = std->xfer; 1499 DPRINTFN(10, "std=%#jx xfer=%#jx hcpriv=%#jx dnext=%#jx", 1500 (uintptr_t)std, (uintptr_t)xfer, 1501 (uintptr_t)(xfer ? xfer->ux_hcpriv : 0), (uintptr_t)stdnext); 1502 if (xfer == NULL) { 1503 /* 1504 * xfer == NULL: There seems to be no xfer associated 1505 * with this TD. It is tailp that happened to end up on 1506 * the done queue. 1507 * Shouldn't happen, but some chips are broken(?). 1508 */ 1509 continue; 1510 } 1511 /* 1512 * Try to claim this xfer for completion. If it has 1513 * already completed or aborted, drop it on the floor. 1514 */ 1515 if (!usbd_xfer_trycomplete(xfer)) 1516 continue; 1517 1518 len = std->len; 1519 if (std->td.td_cbp != 0) 1520 len -= O32TOH(std->td.td_be) - 1521 O32TOH(std->td.td_cbp) + 1; 1522 DPRINTFN(10, "len=%jd, flags=0x%jx", len, std->flags, 0, 0); 1523 if (std->flags & OHCI_ADD_LEN) 1524 xfer->ux_actlen += len; 1525 1526 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1527 if (cc == OHCI_CC_NO_ERROR) { 1528 ohci_hash_rem_td(sc, std); 1529 if (std->flags & OHCI_CALL_DONE) { 1530 xfer->ux_status = USBD_NORMAL_COMPLETION; 1531 usb_transfer_complete(xfer); 1532 } 1533 } else { 1534 /* 1535 * Endpoint is halted. First unlink all the TDs 1536 * belonging to the failed transfer, and then restart 1537 * the endpoint. 1538 */ 1539 ohci_soft_td_t *p, *n; 1540 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1541 1542 DPRINTFN(10, "error cc=%jd", cc, 0, 0, 0); 1543 1544 /* remove xfer's TDs from the hash */ 1545 for (p = std; p->xfer == xfer; p = n) { 1546 n = p->nexttd; 1547 ohci_hash_rem_td(sc, p); 1548 } 1549 1550 ohci_soft_ed_t *sed = opipe->sed; 1551 1552 /* clear halt and TD chain, preserving toggle carry */ 1553 sed->ed.ed_headp = HTOO32(p->physaddr | 1554 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 1555 usb_syncmem(&sed->dma, 1556 sed->offs + offsetof(ohci_ed_t, ed_headp), 1557 sizeof(sed->ed.ed_headp), 1558 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1559 1560 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1561 1562 if (cc == OHCI_CC_DATA_UNDERRUN) 1563 xfer->ux_status = USBD_NORMAL_COMPLETION; 1564 else if (cc == OHCI_CC_STALL) 1565 xfer->ux_status = USBD_STALLED; 1566 else 1567 xfer->ux_status = USBD_IOERROR; 1568 usb_transfer_complete(xfer); 1569 } 1570 } 1571 DPRINTFN(10, "--- ITD dump start ---", 0, 0, 0, 0); 1572 #ifdef OHCI_DEBUG 1573 if (ohcidebug >= 10) { 1574 for (sitd = sidone; sitd; sitd = sitd->dnext) 1575 ohci_dump_itd(sc, sitd); 1576 } 1577 #endif 1578 DPRINTFN(10, "--- ITD dump end ---", 0, 0, 0, 0); 1579 1580 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1581 xfer = sitd->xfer; 1582 sitdnext = sitd->dnext; 1583 DPRINTFN(1, "sitd=%#jx xfer=%#jx hcpriv=%#jx", (uintptr_t)sitd, 1584 (uintptr_t)xfer, (uintptr_t)(xfer ? xfer->ux_hcpriv : 0), 1585 0); 1586 if (xfer == NULL) 1587 continue; 1588 1589 /* 1590 * Try to claim this xfer for completion. If it has 1591 * already completed or aborted, drop it on the floor. 1592 */ 1593 if (!usbd_xfer_trycomplete(xfer)) 1594 continue; 1595 1596 KASSERT(!sitd->isdone); 1597 #ifdef DIAGNOSTIC 1598 sitd->isdone = true; 1599 #endif 1600 if (sitd->flags & OHCI_CALL_DONE) { 1601 ohci_soft_itd_t *next; 1602 1603 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1604 opipe->isoc.inuse -= xfer->ux_nframes; 1605 uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc-> 1606 bEndpointAddress); 1607 xfer->ux_status = USBD_NORMAL_COMPLETION; 1608 actlen = 0; 1609 for (i = 0, sitd = xfer->ux_hcpriv;; 1610 sitd = next) { 1611 next = sitd->nextitd; 1612 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1613 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1614 xfer->ux_status = USBD_IOERROR; 1615 /* For input, update frlengths with actual */ 1616 /* XXX anything necessary for output? */ 1617 if (uedir == UE_DIR_IN && 1618 xfer->ux_status == USBD_NORMAL_COMPLETION) { 1619 iframes = OHCI_ITD_GET_FC(O32TOH( 1620 sitd->itd.itd_flags)); 1621 for (j = 0; j < iframes; i++, j++) { 1622 len = O16TOH(sitd-> 1623 itd.itd_offset[j]); 1624 if ((OHCI_ITD_PSW_GET_CC(len) & 1625 OHCI_CC_NOT_ACCESSED_MASK) 1626 == OHCI_CC_NOT_ACCESSED) 1627 len = 0; 1628 else 1629 len = OHCI_ITD_PSW_LENGTH(len); 1630 xfer->ux_frlengths[i] = len; 1631 actlen += len; 1632 } 1633 } 1634 if (sitd->flags & OHCI_CALL_DONE) 1635 break; 1636 ohci_hash_rem_itd(sc, sitd); 1637 1638 } 1639 ohci_hash_rem_itd(sc, sitd); 1640 if (uedir == UE_DIR_IN && 1641 xfer->ux_status == USBD_NORMAL_COMPLETION) 1642 xfer->ux_actlen = actlen; 1643 xfer->ux_hcpriv = NULL; 1644 1645 usb_transfer_complete(xfer); 1646 } 1647 } 1648 1649 DPRINTFN(10, "done", 0, 0, 0, 0); 1650 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1651 } 1652 1653 void 1654 ohci_device_ctrl_done(struct usbd_xfer *xfer) 1655 { 1656 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1657 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1658 int len = UGETW(xfer->ux_request.wLength); 1659 int isread = (xfer->ux_request.bmRequestType & UT_READ); 1660 1661 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1662 DPRINTFN(10, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 1663 1664 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1665 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 1666 1667 if (len) 1668 usb_syncmem(&xfer->ux_dmabuf, 0, len, 1669 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1670 usb_syncmem(&opipe->ctrl.reqdma, 0, 1671 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1672 } 1673 1674 void 1675 ohci_device_intr_done(struct usbd_xfer *xfer) 1676 { 1677 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1678 int isread = 1679 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1680 1681 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1682 DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, 1683 xfer->ux_actlen, 0, 0); 1684 1685 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1686 1687 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1688 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1689 } 1690 1691 void 1692 ohci_device_bulk_done(struct usbd_xfer *xfer) 1693 { 1694 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1695 1696 int isread = 1697 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1698 1699 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1700 1701 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1702 DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 1703 0, 0); 1704 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1705 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1706 } 1707 1708 Static void 1709 ohci_rhsc_softint(void *arg) 1710 { 1711 ohci_softc_t *sc = arg; 1712 1713 mutex_enter(&sc->sc_lock); 1714 1715 ohci_rhsc(sc, sc->sc_intrxfer); 1716 1717 /* Do not allow RHSC interrupts > 1 per second */ 1718 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1719 1720 mutex_exit(&sc->sc_lock); 1721 } 1722 1723 void 1724 ohci_rhsc(ohci_softc_t *sc, struct usbd_xfer *xfer) 1725 { 1726 u_char *p; 1727 int i, m; 1728 int hstatus __unused; 1729 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1730 1731 KASSERT(mutex_owned(&sc->sc_lock)); 1732 1733 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1734 DPRINTF("sc=%#jx xfer=%#jx hstatus=0x%08jx", (uintptr_t)sc, 1735 (uintptr_t)xfer, hstatus, 0); 1736 1737 if (xfer == NULL) { 1738 /* Just ignore the change. */ 1739 return; 1740 } 1741 KASSERT(xfer == sc->sc_intrxfer); 1742 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 1743 1744 p = xfer->ux_buf; 1745 m = uimin(sc->sc_noport, xfer->ux_length * 8 - 1); 1746 memset(p, 0, xfer->ux_length); 1747 for (i = 1; i <= m; i++) { 1748 /* Pick out CHANGE bits from the status reg. */ 1749 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1750 p[i/8] |= 1 << (i%8); 1751 } 1752 DPRINTF("change=0x%02jx", *p, 0, 0, 0); 1753 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 1754 xfer->ux_actlen = xfer->ux_length; 1755 xfer->ux_status = USBD_NORMAL_COMPLETION; 1756 1757 usb_transfer_complete(xfer); 1758 } 1759 1760 void 1761 ohci_root_intr_done(struct usbd_xfer *xfer) 1762 { 1763 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1764 1765 KASSERT(mutex_owned(&sc->sc_lock)); 1766 1767 /* Claim the xfer so it doesn't get completed again. */ 1768 KASSERT(sc->sc_intrxfer == xfer); 1769 KASSERT(xfer->ux_status != USBD_IN_PROGRESS); 1770 sc->sc_intrxfer = NULL; 1771 } 1772 1773 void 1774 ohci_poll(struct usbd_bus *bus) 1775 { 1776 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1777 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1778 1779 #ifdef OHCI_DEBUG 1780 static int last; 1781 int new; 1782 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1783 if (new != last) { 1784 DPRINTFN(10, "intrs=0x%04jx", new, 0, 0, 0); 1785 last = new; 1786 } 1787 #endif 1788 sc->sc_eintrs |= OHCI_WDH; 1789 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1790 mutex_spin_enter(&sc->sc_intr_lock); 1791 ohci_intr1(sc); 1792 mutex_spin_exit(&sc->sc_intr_lock); 1793 } 1794 } 1795 1796 /* 1797 * Add an ED to the schedule. Called with USB lock held. 1798 */ 1799 Static void 1800 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1801 { 1802 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1803 DPRINTFN(8, "sed=%#jx head=%#jx", (uintptr_t)sed, (uintptr_t)head, 0, 1804 0); 1805 1806 KASSERT(mutex_owned(&sc->sc_lock)); 1807 1808 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1809 sizeof(head->ed.ed_nexted), 1810 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1811 sed->next = head->next; 1812 sed->ed.ed_nexted = head->ed.ed_nexted; 1813 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1814 sizeof(sed->ed.ed_nexted), 1815 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1816 head->next = sed; 1817 head->ed.ed_nexted = HTOO32(sed->physaddr); 1818 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1819 sizeof(head->ed.ed_nexted), 1820 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1821 } 1822 1823 /* 1824 * Remove an ED from the schedule. Called with USB lock held. 1825 */ 1826 Static void 1827 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1828 { 1829 ohci_soft_ed_t *p; 1830 1831 KASSERT(mutex_owned(&sc->sc_lock)); 1832 1833 /* XXX */ 1834 for (p = head; p != NULL && p->next != sed; p = p->next) 1835 ; 1836 KASSERT(p != NULL); 1837 1838 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1839 sizeof(sed->ed.ed_nexted), 1840 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1841 p->next = sed->next; 1842 p->ed.ed_nexted = sed->ed.ed_nexted; 1843 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1844 sizeof(p->ed.ed_nexted), 1845 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1846 } 1847 1848 /* 1849 * When a transfer is completed the TD is added to the done queue by 1850 * the host controller. This queue is the processed by software. 1851 * Unfortunately the queue contains the physical address of the TD 1852 * and we have no simple way to translate this back to a kernel address. 1853 * To make the translation possible (and fast) we use a hash table of 1854 * TDs currently in the schedule. The physical address is used as the 1855 * hash value. 1856 */ 1857 1858 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1859 /* Called with USB lock held. */ 1860 void 1861 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1862 { 1863 int h = HASH(std->physaddr); 1864 1865 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1866 1867 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1868 } 1869 1870 /* Called with USB lock held. */ 1871 void 1872 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1873 { 1874 1875 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1876 1877 LIST_REMOVE(std, hnext); 1878 } 1879 1880 ohci_soft_td_t * 1881 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1882 { 1883 int h = HASH(a); 1884 ohci_soft_td_t *std; 1885 1886 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1887 std != NULL; 1888 std = LIST_NEXT(std, hnext)) 1889 if (std->physaddr == a) 1890 return std; 1891 return NULL; 1892 } 1893 1894 /* Called with USB lock held. */ 1895 void 1896 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1897 { 1898 int h = HASH(sitd->physaddr); 1899 1900 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1901 1902 KASSERT(mutex_owned(&sc->sc_lock)); 1903 1904 DPRINTFN(10, "sitd=%#jx physaddr=0x%08jx", 1905 (uintptr_t)sitd, (u_long)sitd->physaddr, 0, 0); 1906 1907 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1908 } 1909 1910 /* Called with USB lock held. */ 1911 void 1912 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1913 { 1914 1915 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1916 1917 KASSERT(mutex_owned(&sc->sc_lock)); 1918 1919 DPRINTFN(10, "sitd=%#jx physaddr=0x%08jx", (uintptr_t)sitd, 1920 sitd->physaddr, 0, 0); 1921 1922 LIST_REMOVE(sitd, hnext); 1923 } 1924 1925 ohci_soft_itd_t * 1926 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1927 { 1928 int h = HASH(a); 1929 ohci_soft_itd_t *sitd; 1930 1931 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1932 sitd != NULL; 1933 sitd = LIST_NEXT(sitd, hnext)) 1934 if (sitd->physaddr == a) 1935 return sitd; 1936 return NULL; 1937 } 1938 1939 #ifdef OHCI_DEBUG 1940 void 1941 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 1942 { 1943 for (; std; std = std->nexttd) { 1944 ohci_dump_td(sc, std); 1945 KASSERTMSG(std->nexttd == NULL || std != std->nexttd, 1946 "std %p next %p", std, std->nexttd); 1947 } 1948 } 1949 1950 void 1951 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1952 { 1953 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1954 1955 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1956 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1957 1958 uint32_t flags = O32TOH(std->td.td_flags); 1959 DPRINTF("TD(%#jx) at 0x%08jx:", (uintptr_t)std, std->physaddr, 0, 0); 1960 DPRINTF(" round=%jd DP=%jx DI=%jx T=%jx", 1961 !!(flags & OHCI_TD_R), 1962 __SHIFTOUT(flags, OHCI_TD_DP_MASK), 1963 OHCI_TD_GET_DI(flags), 1964 __SHIFTOUT(flags, OHCI_TD_TOGGLE_MASK)); 1965 DPRINTF(" EC=%jd CC=%jd", OHCI_TD_GET_EC(flags), 1966 OHCI_TD_GET_CC(flags), 0, 0); 1967 DPRINTF(" td_cbp=0x%08jx td_nexttd=0x%08jx td_be=0x%08jx", 1968 (u_long)O32TOH(std->td.td_cbp), 1969 (u_long)O32TOH(std->td.td_nexttd), 1970 (u_long)O32TOH(std->td.td_be), 0); 1971 } 1972 1973 void 1974 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1975 { 1976 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1977 1978 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1979 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1980 1981 uint32_t flags = O32TOH(sitd->itd.itd_flags); 1982 DPRINTF("ITD(%#jx) at 0x%08jx", (uintptr_t)sitd, sitd->physaddr, 0, 0); 1983 DPRINTF(" sf=%jd di=%jd fc=%jd cc=%jd", 1984 OHCI_ITD_GET_SF(flags), OHCI_ITD_GET_DI(flags), 1985 OHCI_ITD_GET_FC(flags), OHCI_ITD_GET_CC(flags)); 1986 DPRINTF(" bp0=0x%08jx next=0x%08jx be=0x%08jx", 1987 O32TOH(sitd->itd.itd_bp0), 1988 O32TOH(sitd->itd.itd_nextitd), 1989 O32TOH(sitd->itd.itd_be), 0); 1990 CTASSERT(OHCI_ITD_NOFFSET == 8); 1991 DPRINTF(" offs[0] = 0x%04jx offs[1] = 0x%04jx " 1992 "offs[2] = 0x%04jx offs[3] = 0x%04jx", 1993 O16TOH(sitd->itd.itd_offset[0]), 1994 O16TOH(sitd->itd.itd_offset[1]), 1995 O16TOH(sitd->itd.itd_offset[2]), 1996 O16TOH(sitd->itd.itd_offset[3])); 1997 DPRINTF(" offs[4] = 0x%04jx offs[5] = 0x%04jx " 1998 "offs[6] = 0x%04jx offs[7] = 0x%04jx", 1999 O16TOH(sitd->itd.itd_offset[4]), 2000 O16TOH(sitd->itd.itd_offset[5]), 2001 O16TOH(sitd->itd.itd_offset[6]), 2002 O16TOH(sitd->itd.itd_offset[7])); 2003 } 2004 2005 void 2006 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2007 { 2008 for (; sitd; sitd = sitd->nextitd) 2009 ohci_dump_itd(sc, sitd); 2010 } 2011 2012 void 2013 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2014 { 2015 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2016 2017 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2018 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2019 2020 uint32_t flags = O32TOH(sed->ed.ed_flags); 2021 DPRINTF("ED(%#jx) at 0x%08jx:", (uintptr_t)sed, sed->physaddr, 0, 0); 2022 DPRINTF(" addr=%jd endpt=%jd maxp=%jd", 2023 OHCI_ED_GET_FA(flags), 2024 OHCI_ED_GET_EN(flags), 2025 OHCI_ED_GET_MAXP(flags), 2026 0); 2027 DPRINTF(" dir=%jd speed=%jd skip=%jd iso=%jd", 2028 __SHIFTOUT(flags, OHCI_ED_DIR_MASK), 2029 !!(flags & OHCI_ED_SPEED), 2030 !!(flags & OHCI_ED_SKIP), 2031 !!(flags & OHCI_ED_FORMAT_ISO)); 2032 DPRINTF(" tailp=0x%08jx", (u_long)O32TOH(sed->ed.ed_tailp), 2033 0, 0, 0); 2034 DPRINTF(" headp=0x%08jx nexted=0x%08jx halted=%jd carry=%jd", 2035 O32TOH(sed->ed.ed_headp), O32TOH(sed->ed.ed_nexted), 2036 !!(O32TOH(sed->ed.ed_headp) & OHCI_HALTED), 2037 !!(O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 2038 } 2039 #endif 2040 2041 usbd_status 2042 ohci_open(struct usbd_pipe *pipe) 2043 { 2044 struct usbd_device *dev = pipe->up_dev; 2045 struct usbd_bus *bus = dev->ud_bus; 2046 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2047 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 2048 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2049 uint8_t addr = dev->ud_addr; 2050 uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2051 ohci_soft_ed_t *sed; 2052 ohci_soft_td_t *std; 2053 ohci_soft_itd_t *sitd; 2054 ohci_physaddr_t tdphys; 2055 uint32_t fmt; 2056 usbd_status err = USBD_NOMEM; 2057 int ival; 2058 2059 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2060 DPRINTFN(1, "pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, 2061 addr, ed->bEndpointAddress, bus->ub_rhaddr); 2062 2063 if (sc->sc_dying) { 2064 return USBD_IOERROR; 2065 } 2066 2067 std = NULL; 2068 sed = NULL; 2069 2070 if (addr == bus->ub_rhaddr) { 2071 switch (ed->bEndpointAddress) { 2072 case USB_CONTROL_ENDPOINT: 2073 pipe->up_methods = &roothub_ctrl_methods; 2074 break; 2075 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 2076 pipe->up_methods = &ohci_root_intr_methods; 2077 break; 2078 default: 2079 err = USBD_INVAL; 2080 goto bad; 2081 } 2082 } else { 2083 sed = ohci_alloc_sed(sc); 2084 if (sed == NULL) 2085 goto bad; 2086 opipe->sed = sed; 2087 if (xfertype == UE_ISOCHRONOUS) { 2088 sitd = ohci_alloc_sitd(sc); 2089 if (sitd == NULL) 2090 goto bad; 2091 2092 opipe->tail.itd = sitd; 2093 sitd->held = &opipe->tail.itd; 2094 tdphys = sitd->physaddr; 2095 fmt = OHCI_ED_FORMAT_ISO; 2096 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2097 fmt |= OHCI_ED_DIR_IN; 2098 else 2099 fmt |= OHCI_ED_DIR_OUT; 2100 } else { 2101 std = ohci_alloc_std(sc); 2102 if (std == NULL) 2103 goto bad; 2104 2105 opipe->tail.td = std; 2106 std->held = &opipe->tail.td; 2107 tdphys = std->physaddr; 2108 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2109 } 2110 sed->ed.ed_flags = HTOO32( 2111 OHCI_ED_SET_FA(addr) | 2112 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2113 (dev->ud_speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2114 fmt | 2115 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2116 sed->ed.ed_headp = HTOO32(tdphys | 2117 (pipe->up_endpoint->ue_toggle ? OHCI_TOGGLECARRY : 0)); 2118 sed->ed.ed_tailp = HTOO32(tdphys); 2119 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2120 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2121 2122 switch (xfertype) { 2123 case UE_CONTROL: 2124 pipe->up_methods = &ohci_device_ctrl_methods; 2125 err = usb_allocmem(&sc->sc_bus, 2126 sizeof(usb_device_request_t), 2127 0, &opipe->ctrl.reqdma); 2128 if (err) 2129 goto bad; 2130 mutex_enter(&sc->sc_lock); 2131 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2132 mutex_exit(&sc->sc_lock); 2133 break; 2134 case UE_INTERRUPT: 2135 pipe->up_methods = &ohci_device_intr_methods; 2136 ival = pipe->up_interval; 2137 if (ival == USBD_DEFAULT_INTERVAL) 2138 ival = ed->bInterval; 2139 err = ohci_device_setintr(sc, opipe, ival); 2140 if (err) 2141 goto bad; 2142 break; 2143 case UE_ISOCHRONOUS: 2144 pipe->up_serialise = false; 2145 pipe->up_methods = &ohci_device_isoc_methods; 2146 return ohci_setup_isoc(pipe); 2147 case UE_BULK: 2148 pipe->up_methods = &ohci_device_bulk_methods; 2149 mutex_enter(&sc->sc_lock); 2150 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2151 mutex_exit(&sc->sc_lock); 2152 break; 2153 } 2154 } 2155 2156 return USBD_NORMAL_COMPLETION; 2157 2158 bad: 2159 if (std != NULL) { 2160 ohci_free_std(sc, std); 2161 } 2162 if (sed != NULL) 2163 ohci_free_sed(sc, sed); 2164 return err; 2165 2166 } 2167 2168 /* 2169 * Close a reqular pipe. 2170 * Assumes that there are no pending transactions. 2171 */ 2172 void 2173 ohci_close_pipe(struct usbd_pipe *pipe, ohci_soft_ed_t *head) 2174 { 2175 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2176 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2177 ohci_soft_ed_t *sed = opipe->sed; 2178 2179 KASSERT(mutex_owned(&sc->sc_lock)); 2180 2181 #ifdef DIAGNOSTIC 2182 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2183 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2184 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2185 ohci_soft_td_t *std; 2186 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2187 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2188 "tl=0x%x pipe=%p, std=%p\n", sed, 2189 (int)O32TOH(sed->ed.ed_headp), 2190 (int)O32TOH(sed->ed.ed_tailp), 2191 pipe, std); 2192 #ifdef OHCI_DEBUG 2193 usbd_dump_pipe(&opipe->pipe); 2194 ohci_dump_ed(sc, sed); 2195 if (std) 2196 ohci_dump_td(sc, std); 2197 #endif 2198 usb_delay_ms(&sc->sc_bus, 2); 2199 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2200 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2201 printf("ohci_close_pipe: pipe still not empty\n"); 2202 } 2203 #endif 2204 ohci_rem_ed(sc, sed, head); 2205 /* Make sure the host controller is not touching this ED */ 2206 usb_delay_ms(&sc->sc_bus, 1); 2207 pipe->up_endpoint->ue_toggle = 2208 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2209 ohci_free_sed_locked(sc, opipe->sed); 2210 } 2211 2212 /* 2213 * Arrange for the hardware to tells us that it is not still processing 2214 * the TDs by setting the sKip bit and requesting a SOF interrupt 2215 * 2216 * Once we see the SOF interrupt we can check the transfer TDs/iTDs to see if 2217 * they've been processed and either 2218 * a) if they're unused recover them for later use, or 2219 * b) if they've been used allocate new TD/iTDs to replace those 2220 * used. The softint handler will free the old ones. 2221 */ 2222 void 2223 ohci_abortx(struct usbd_xfer *xfer) 2224 { 2225 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2226 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2227 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2228 ohci_soft_ed_t *sed = opipe->sed; 2229 ohci_soft_td_t *p, *n; 2230 ohci_physaddr_t headp; 2231 int hit; 2232 2233 DPRINTF("xfer=%#jx pipe=%#jx sed=%#jx", (uintptr_t)xfer, 2234 (uintptr_t)opipe, (uintptr_t)sed, 0); 2235 2236 KASSERT(mutex_owned(&sc->sc_lock)); 2237 ASSERT_SLEEPABLE(); 2238 2239 KASSERTMSG((xfer->ux_status == USBD_CANCELLED || 2240 xfer->ux_status == USBD_TIMEOUT), 2241 "bad abort status: %d", xfer->ux_status); 2242 2243 /* 2244 * If we're dying, skip the hardware action and just notify the 2245 * software that we're done. 2246 */ 2247 if (sc->sc_dying) { 2248 DPRINTFN(4, "xfer %#jx dying %ju", (uintptr_t)xfer, 2249 xfer->ux_status, 0, 0); 2250 goto dying; 2251 } 2252 2253 /* 2254 * HC Step 1: Unless the endpoint is already halted, we set the 2255 * endpoint descriptor sKip bit and wait for hardware to complete 2256 * processing. We ensure the HC stops processing the endpoint by 2257 * waiting for the next start of frame (OHCI_SF) 2258 */ 2259 DPRINTFN(1, "stop ed=%#jx", (uintptr_t)sed, 0, 0, 0); 2260 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2261 sizeof(sed->ed.ed_flags), 2262 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2263 if (!(sed->ed.ed_flags & OHCI_HALTED)) { 2264 /* force hardware skip */ 2265 DPRINTFN(1, "pausing ed=%#jx", (uintptr_t)sed, 0, 0, 0); 2266 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2267 usb_syncmem(&sed->dma, 2268 sed->offs + offsetof(ohci_ed_t, ed_flags), 2269 sizeof(sed->ed.ed_flags), 2270 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2271 2272 DPRINTFN(10, "SF %#jx xfer %#jx", (uintptr_t)sc, 2273 (uintptr_t)xfer, 0, 0); 2274 2275 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2276 ox->ox_abintrs = OHCI_SF; 2277 2278 mutex_enter(&sc->sc_intr_lock); 2279 TAILQ_INSERT_TAIL(&sc->sc_abortingxfers, ox, ox_abnext); 2280 2281 /* Clear any previous SF interrupt */ 2282 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_SF); 2283 2284 /* Tell interrupt handler and HC SF interrupt is requested */ 2285 sc->sc_eintrs |= OHCI_SF; 2286 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_SF); 2287 /* 2288 * Step 2: Wait until we know hardware has finished any 2289 * processing of the end-point. 2290 */ 2291 while (ox->ox_abintrs != 0) { 2292 DPRINTFN(10, "SF %#jx xfer %#jx intrs %#x", 2293 (uintptr_t)sc, (uintptr_t)xfer, 2294 (uintptr_t)ox->ox_abintrs, 0); 2295 cv_wait(&sc->sc_abort_cv, &sc->sc_intr_lock); 2296 } 2297 mutex_exit(&sc->sc_intr_lock); 2298 } else { 2299 DPRINTFN(1, "halted ed=%#jx", (uintptr_t)sed, 0, 0, 0); 2300 } 2301 2302 /* 2303 * HC Step 3: Remove any vestiges of the xfer from the hardware. 2304 * There are two complications here 2305 * 2306 * 1) the hardware may have executed beyond the xfer we're trying to 2307 * abort. So as we're scanning the TDs of this xfer we check if 2308 * the hardware points to any of them. 2309 * 2310 * 2) the hardware may have only partially excuted the transfer 2311 * which means some TDs will appear on the done list. Wait for 2312 * WDH so we can remove them safely. 2313 */ 2314 p = xfer->ux_hcpriv; 2315 KASSERT(p); 2316 2317 #ifdef OHCI_DEBUG 2318 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2319 2320 if (ohcidebug >= 2) { 2321 DPRINTF("sed:", 0, 0, 0, 0); 2322 ohci_dump_ed(sc, sed); 2323 ohci_dump_tds(sc, p); 2324 } 2325 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2326 #endif 2327 2328 2329 #define OHCI_CC_ACCESSED_P(x) \ 2330 (((x) & OHCI_CC_NOT_ACCESSED_MASK) != OHCI_CC_NOT_ACCESSED) 2331 2332 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2333 hit = 0; 2334 for (; p->xfer == xfer; p = n) { 2335 hit |= headp == p->physaddr; 2336 n = p->nexttd; 2337 2338 int cc = OHCI_TD_GET_CC(O32TOH(p->td.td_flags)); 2339 if (!OHCI_CC_ACCESSED_P(cc)) { 2340 ohci_hash_rem_td(sc, p); 2341 continue; 2342 } 2343 DPRINTFN(10, "xfer=%#jx has been touched by HC", (uintptr_t)p, 2344 0, 0, 0); 2345 2346 mutex_exit(&sc->sc_lock); 2347 ohci_soft_td_t *std; 2348 for (;;) { 2349 std = ohci_alloc_std(sc); 2350 if (std) 2351 break; 2352 kpause("ohciabt2", true, hz, NULL); 2353 } 2354 2355 mutex_enter(&sc->sc_lock); 2356 if (sc->sc_dying) { 2357 DPRINTFN(4, "xfer %#jx dying %ju", (uintptr_t)xfer, 2358 xfer->ux_status, 0, 0); 2359 goto dying; 2360 } 2361 2362 DPRINTFN(10, "new std=%#jx now held at %#jx", (uintptr_t)std, 2363 (uintptr_t)p->held, 0, 0); 2364 *(p->held) = std; 2365 std->held = p->held; 2366 std->xfer = xfer; 2367 p->held = NULL; 2368 } 2369 /* Zap headp register if hardware pointed inside the xfer. */ 2370 if (hit) { 2371 DPRINTFN(1, "set hd=0x%08jx, tl=0x%08jx", (int)p->physaddr, 2372 (int)O32TOH(sed->ed.ed_tailp), 0, 0); 2373 /* unlink TDs, preserving toggle carry */ 2374 sed->ed.ed_headp = HTOO32(p->physaddr | 2375 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 2376 usb_syncmem(&sed->dma, 2377 sed->offs + offsetof(ohci_ed_t, ed_headp), 2378 sizeof(sed->ed.ed_headp), 2379 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2380 } else { 2381 DPRINTFN(1, "no hit", 0, 0, 0, 0); 2382 } 2383 2384 /* 2385 * HC Step 4: Turn on hardware again. 2386 */ 2387 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2388 sizeof(sed->ed.ed_flags), 2389 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2390 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2391 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2392 sizeof(sed->ed.ed_flags), 2393 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2394 2395 /* 2396 * Final step: Notify completion to waiting xfers. 2397 */ 2398 dying: 2399 usb_transfer_complete(xfer); 2400 DPRINTFN(14, "end", 0, 0, 0, 0); 2401 2402 KASSERT(mutex_owned(&sc->sc_lock)); 2403 } 2404 2405 /* 2406 * Data structures and routines to emulate the root hub. 2407 */ 2408 Static int 2409 ohci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2410 void *buf, int buflen) 2411 { 2412 ohci_softc_t *sc = OHCI_BUS2SC(bus); 2413 usb_port_status_t ps; 2414 uint16_t len, value, index; 2415 int l, totlen = 0; 2416 int port, i; 2417 uint32_t v; 2418 2419 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2420 2421 if (sc->sc_dying) 2422 return -1; 2423 2424 DPRINTFN(4, "type=0x%02jx request=%02jx", req->bmRequestType, 2425 req->bRequest, 0, 0); 2426 2427 len = UGETW(req->wLength); 2428 value = UGETW(req->wValue); 2429 index = UGETW(req->wIndex); 2430 2431 #define C(x,y) ((x) | ((y) << 8)) 2432 switch (C(req->bRequest, req->bmRequestType)) { 2433 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2434 DPRINTFN(8, "wValue=0x%04jx", value, 0, 0, 0); 2435 if (len == 0) 2436 break; 2437 switch (value) { 2438 #define sd ((usb_string_descriptor_t *)buf) 2439 case C(2, UDESC_STRING): 2440 /* Product */ 2441 totlen = usb_makestrdesc(sd, len, "OHCI root hub"); 2442 break; 2443 #undef sd 2444 default: 2445 /* default from usbroothub */ 2446 return buflen; 2447 } 2448 break; 2449 2450 /* Hub requests */ 2451 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2452 break; 2453 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2454 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", 2455 index, value, 0, 0); 2456 if (index < 1 || index > sc->sc_noport) { 2457 return -1; 2458 } 2459 port = OHCI_RH_PORT_STATUS(index); 2460 switch(value) { 2461 case UHF_PORT_ENABLE: 2462 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2463 break; 2464 case UHF_PORT_SUSPEND: 2465 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2466 break; 2467 case UHF_PORT_POWER: 2468 /* Yes, writing to the LOW_SPEED bit clears power. */ 2469 OWRITE4(sc, port, UPS_LOW_SPEED); 2470 break; 2471 case UHF_C_PORT_CONNECTION: 2472 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2473 break; 2474 case UHF_C_PORT_ENABLE: 2475 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2476 break; 2477 case UHF_C_PORT_SUSPEND: 2478 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2479 break; 2480 case UHF_C_PORT_OVER_CURRENT: 2481 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2482 break; 2483 case UHF_C_PORT_RESET: 2484 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2485 break; 2486 default: 2487 return -1; 2488 } 2489 switch(value) { 2490 case UHF_C_PORT_CONNECTION: 2491 case UHF_C_PORT_ENABLE: 2492 case UHF_C_PORT_SUSPEND: 2493 case UHF_C_PORT_OVER_CURRENT: 2494 case UHF_C_PORT_RESET: 2495 /* Enable RHSC interrupt if condition is cleared. */ 2496 if ((OREAD4(sc, port) >> 16) == 0) 2497 ohci_rhsc_enable(sc); 2498 break; 2499 default: 2500 break; 2501 } 2502 break; 2503 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2504 if (len == 0) 2505 break; 2506 if ((value & 0xff) != 0) { 2507 return -1; 2508 } 2509 usb_hub_descriptor_t hubd; 2510 2511 totlen = uimin(buflen, sizeof(hubd)); 2512 memcpy(&hubd, buf, totlen); 2513 2514 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2515 hubd.bNbrPorts = sc->sc_noport; 2516 USETW(hubd.wHubCharacteristics, 2517 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2518 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2519 /* XXX overcurrent */ 2520 ); 2521 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2522 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2523 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2524 hubd.DeviceRemovable[i++] = (uint8_t)v; 2525 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2526 totlen = uimin(totlen, hubd.bDescLength); 2527 memcpy(buf, &hubd, totlen); 2528 break; 2529 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2530 if (len != 4) { 2531 return -1; 2532 } 2533 memset(buf, 0, len); /* ? XXX */ 2534 totlen = len; 2535 break; 2536 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2537 DPRINTFN(8, "get port status i=%jd", index, 0, 0, 0); 2538 if (index < 1 || index > sc->sc_noport) { 2539 return -1; 2540 } 2541 if (len != 4) { 2542 return -1; 2543 } 2544 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2545 DPRINTFN(8, "port status=0x%04jx", v, 0, 0, 0); 2546 USETW(ps.wPortStatus, v); 2547 USETW(ps.wPortChange, v >> 16); 2548 totlen = uimin(len, sizeof(ps)); 2549 memcpy(buf, &ps, totlen); 2550 break; 2551 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2552 return -1; 2553 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2554 break; 2555 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2556 if (index < 1 || index > sc->sc_noport) { 2557 return -1; 2558 } 2559 port = OHCI_RH_PORT_STATUS(index); 2560 switch(value) { 2561 case UHF_PORT_ENABLE: 2562 OWRITE4(sc, port, UPS_PORT_ENABLED); 2563 break; 2564 case UHF_PORT_SUSPEND: 2565 OWRITE4(sc, port, UPS_SUSPEND); 2566 break; 2567 case UHF_PORT_RESET: 2568 DPRINTFN(5, "reset port %jd", index, 0, 0, 0); 2569 OWRITE4(sc, port, UPS_RESET); 2570 for (i = 0; i < 5; i++) { 2571 usb_delay_ms(&sc->sc_bus, 2572 USB_PORT_ROOT_RESET_DELAY); 2573 if (sc->sc_dying) { 2574 return -1; 2575 } 2576 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2577 break; 2578 } 2579 DPRINTFN(8, "port %jd reset, status = 0x%04jx", index, 2580 OREAD4(sc, port), 0, 0); 2581 break; 2582 case UHF_PORT_POWER: 2583 DPRINTFN(2, "set port power %jd", index, 0, 0, 0); 2584 OWRITE4(sc, port, UPS_PORT_POWER); 2585 break; 2586 default: 2587 return -1; 2588 } 2589 break; 2590 default: 2591 /* default from usbroothub */ 2592 return buflen; 2593 } 2594 2595 return totlen; 2596 } 2597 2598 Static usbd_status 2599 ohci_root_intr_transfer(struct usbd_xfer *xfer) 2600 { 2601 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2602 usbd_status err; 2603 2604 /* Insert last in queue. */ 2605 mutex_enter(&sc->sc_lock); 2606 err = usb_insert_transfer(xfer); 2607 mutex_exit(&sc->sc_lock); 2608 if (err) 2609 return err; 2610 2611 /* Pipe isn't running, start first */ 2612 return ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2613 } 2614 2615 Static usbd_status 2616 ohci_root_intr_start(struct usbd_xfer *xfer) 2617 { 2618 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2619 const bool polling = sc->sc_bus.ub_usepolling; 2620 2621 if (sc->sc_dying) 2622 return USBD_IOERROR; 2623 2624 if (!polling) 2625 mutex_enter(&sc->sc_lock); 2626 KASSERT(sc->sc_intrxfer == NULL); 2627 sc->sc_intrxfer = xfer; 2628 xfer->ux_status = USBD_IN_PROGRESS; 2629 if (!polling) 2630 mutex_exit(&sc->sc_lock); 2631 2632 return USBD_IN_PROGRESS; 2633 } 2634 2635 /* Abort a root interrupt request. */ 2636 Static void 2637 ohci_root_intr_abort(struct usbd_xfer *xfer) 2638 { 2639 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2640 2641 KASSERT(mutex_owned(&sc->sc_lock)); 2642 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2643 2644 /* If xfer has already completed, nothing to do here. */ 2645 if (sc->sc_intrxfer == NULL) 2646 return; 2647 2648 /* 2649 * Otherwise, sc->sc_intrxfer had better be this transfer. 2650 * Cancel it. 2651 */ 2652 KASSERT(sc->sc_intrxfer == xfer); 2653 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 2654 xfer->ux_status = USBD_CANCELLED; 2655 usb_transfer_complete(xfer); 2656 } 2657 2658 /* Close the root pipe. */ 2659 Static void 2660 ohci_root_intr_close(struct usbd_pipe *pipe) 2661 { 2662 ohci_softc_t *sc __diagused = OHCI_PIPE2SC(pipe); 2663 2664 KASSERT(mutex_owned(&sc->sc_lock)); 2665 2666 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2667 2668 /* 2669 * Caller must guarantee the xfer has completed first, by 2670 * closing the pipe only after normal completion or an abort. 2671 */ 2672 KASSERT(sc->sc_intrxfer == NULL); 2673 } 2674 2675 /************************/ 2676 2677 int 2678 ohci_device_ctrl_init(struct usbd_xfer *xfer) 2679 { 2680 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2681 usb_device_request_t *req = &xfer->ux_request; 2682 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2683 ohci_soft_td_t *stat, *setup; 2684 int isread = req->bmRequestType & UT_READ; 2685 int len = xfer->ux_bufsize; 2686 int err = ENOMEM; 2687 2688 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2689 2690 setup = ohci_alloc_std(sc); 2691 if (setup == NULL) { 2692 goto bad1; 2693 } 2694 stat = ohci_alloc_std(sc); 2695 if (stat == NULL) { 2696 goto bad2; 2697 } 2698 2699 ox->ox_setup = setup; 2700 ox->ox_stat = stat; 2701 ox->ox_nstd = 0; 2702 setup->held = &ox->ox_setup; 2703 stat->held = &ox->ox_stat; 2704 2705 DPRINTFN(10, "xfer=%#jx setup=%#jx held at %#jx", (uintptr_t)ox, 2706 (uintptr_t)setup, (uintptr_t)setup->held, 0); 2707 DPRINTFN(10, "xfer=%#jx stat= %#jx held at %#jx", (uintptr_t)ox, 2708 (uintptr_t)stat, (uintptr_t)stat->held, 0); 2709 2710 /* Set up data transaction */ 2711 if (len != 0) { 2712 err = ohci_alloc_std_chain(sc, xfer, len, isread); 2713 if (err) { 2714 goto bad3; 2715 } 2716 } 2717 return 0; 2718 2719 bad3: 2720 ohci_free_std(sc, stat); 2721 bad2: 2722 ohci_free_std(sc, setup); 2723 bad1: 2724 return err; 2725 } 2726 2727 void 2728 ohci_device_ctrl_fini(struct usbd_xfer *xfer) 2729 { 2730 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2731 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2732 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2733 2734 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2735 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 2736 2737 mutex_enter(&sc->sc_lock); 2738 if (ox->ox_setup != opipe->tail.td) { 2739 ohci_free_std_locked(sc, ox->ox_setup); 2740 } 2741 for (size_t i = 0; i < ox->ox_nstd; i++) { 2742 ohci_soft_td_t *std = ox->ox_stds[i]; 2743 if (std == NULL) 2744 break; 2745 ohci_free_std_locked(sc, std); 2746 } 2747 ohci_free_std_locked(sc, ox->ox_stat); 2748 mutex_exit(&sc->sc_lock); 2749 2750 if (ox->ox_nstd) { 2751 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 2752 kmem_free(ox->ox_stds, sz); 2753 } 2754 } 2755 2756 Static usbd_status 2757 ohci_device_ctrl_transfer(struct usbd_xfer *xfer) 2758 { 2759 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2760 usbd_status err; 2761 2762 /* Insert last in queue. */ 2763 mutex_enter(&sc->sc_lock); 2764 err = usb_insert_transfer(xfer); 2765 mutex_exit(&sc->sc_lock); 2766 if (err) 2767 return err; 2768 2769 /* Pipe isn't running, start first */ 2770 return ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2771 } 2772 2773 Static usbd_status 2774 ohci_device_ctrl_start(struct usbd_xfer *xfer) 2775 { 2776 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2777 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2778 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2779 usb_device_request_t *req = &xfer->ux_request; 2780 struct usbd_device *dev __diagused = opipe->pipe.up_dev; 2781 ohci_soft_td_t *setup, *stat, *next, *tail; 2782 ohci_soft_ed_t *sed; 2783 int isread; 2784 int len; 2785 const bool polling = sc->sc_bus.ub_usepolling; 2786 2787 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2788 2789 if (sc->sc_dying) 2790 return USBD_IOERROR; 2791 2792 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2793 2794 isread = req->bmRequestType & UT_READ; 2795 len = UGETW(req->wLength); 2796 2797 DPRINTF("xfer=%#jx len=%jd, addr=%jd, endpt=%jd", (uintptr_t)xfer, len, 2798 dev->ud_addr, opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress); 2799 DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx", 2800 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2801 UGETW(req->wIndex)); 2802 2803 /* Need to take lock here for pipe->tail.td */ 2804 if (!polling) 2805 mutex_enter(&sc->sc_lock); 2806 2807 /* 2808 * Use the pipe "tail" TD as our first and loan our first TD to the 2809 * next transfer 2810 */ 2811 setup = opipe->tail.td; 2812 opipe->tail.td = ox->ox_setup; 2813 ox->ox_setup = setup; 2814 setup->held = &ox->ox_setup; 2815 2816 DPRINTFN(10, "xfer=%#jx new setup=%#jx held at %#jx", (uintptr_t)ox, 2817 (uintptr_t)setup, (uintptr_t)setup->held, 0); 2818 2819 stat = ox->ox_stat; 2820 2821 /* point at sentinel */ 2822 tail = opipe->tail.td; 2823 tail->held = &opipe->tail.td; 2824 sed = opipe->sed; 2825 2826 DPRINTFN(10, "xfer=%#jx new tail=%#jx held at %#jx", (uintptr_t)ox, 2827 (uintptr_t)tail, (uintptr_t)tail->held, 0); 2828 2829 KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->ud_addr, 2830 "address ED %d pipe %d\n", 2831 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->ud_addr); 2832 KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) == 2833 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 2834 "MPL ED %d pipe %d\n", 2835 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), 2836 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 2837 2838 /* next will point to data if len != 0 */ 2839 next = stat; 2840 2841 /* Set up data transaction */ 2842 if (len != 0) { 2843 ohci_soft_td_t *std; 2844 ohci_soft_td_t *end; 2845 2846 next = ox->ox_stds[0]; 2847 ohci_reset_std_chain(sc, xfer, len, isread, next, &end); 2848 2849 end->td.td_nexttd = HTOO32(stat->physaddr); 2850 end->nexttd = stat; 2851 2852 usb_syncmem(&end->dma, end->offs, sizeof(end->td), 2853 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2854 2855 usb_syncmem(&xfer->ux_dmabuf, 0, len, 2856 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2857 std = ox->ox_stds[0]; 2858 /* Start toggle at 1 and then use the carried toggle. */ 2859 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 2860 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 2861 usb_syncmem(&std->dma, 2862 std->offs + offsetof(ohci_td_t, td_flags), 2863 sizeof(std->td.td_flags), 2864 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2865 } 2866 2867 DPRINTFN(8, "setup %#jx data %#jx stat %#jx tail %#jx", 2868 (uintptr_t)setup, 2869 (uintptr_t)(len != 0 ? ox->ox_stds[0] : NULL), (uintptr_t)stat, 2870 (uintptr_t)tail); 2871 KASSERT(opipe->tail.td == tail); 2872 2873 memcpy(KERNADDR(&opipe->ctrl.reqdma, 0), req, sizeof(*req)); 2874 usb_syncmem(&opipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2875 2876 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 2877 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 2878 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->ctrl.reqdma, 0)); 2879 setup->td.td_nexttd = HTOO32(next->physaddr); 2880 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof(*req) - 1); 2881 setup->nexttd = next; 2882 setup->len = 0; 2883 setup->xfer = xfer; 2884 setup->flags = 0; 2885 ohci_hash_add_td(sc, setup); 2886 2887 xfer->ux_hcpriv = setup; 2888 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2889 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2890 2891 stat->td.td_flags = HTOO32( 2892 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 2893 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 2894 stat->td.td_cbp = 0; 2895 stat->td.td_nexttd = HTOO32(tail->physaddr); 2896 stat->td.td_be = 0; 2897 stat->nexttd = tail; 2898 stat->flags = OHCI_CALL_DONE; 2899 stat->len = 0; 2900 stat->xfer = xfer; 2901 ohci_hash_add_td(sc, stat); 2902 2903 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2904 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2905 2906 memset(&tail->td, 0, sizeof(tail->td)); 2907 tail->nexttd = NULL; 2908 tail->xfer = NULL; 2909 2910 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 2911 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2912 2913 #ifdef OHCI_DEBUG 2914 USBHIST_LOGN(ohcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2915 if (ohcidebug >= 5) { 2916 ohci_dump_ed(sc, sed); 2917 ohci_dump_tds(sc, setup); 2918 } 2919 USBHIST_LOGN(ohcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2920 #endif 2921 2922 /* Insert ED in schedule */ 2923 sed->ed.ed_tailp = HTOO32(tail->physaddr); 2924 usb_syncmem(&sed->dma, 2925 sed->offs + offsetof(ohci_ed_t, ed_tailp), 2926 sizeof(sed->ed.ed_tailp), 2927 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2928 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2929 usbd_xfer_schedule_timeout(xfer); 2930 2931 DPRINTF("done", 0, 0, 0, 0); 2932 2933 xfer->ux_status = USBD_IN_PROGRESS; 2934 if (!polling) 2935 mutex_exit(&sc->sc_lock); 2936 2937 return USBD_IN_PROGRESS; 2938 } 2939 2940 /* Abort a device control request. */ 2941 Static void 2942 ohci_device_ctrl_abort(struct usbd_xfer *xfer) 2943 { 2944 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 2945 2946 KASSERT(mutex_owned(&sc->sc_lock)); 2947 2948 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2949 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 2950 usbd_xfer_abort(xfer); 2951 } 2952 2953 /* Close a device control pipe. */ 2954 Static void 2955 ohci_device_ctrl_close(struct usbd_pipe *pipe) 2956 { 2957 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2958 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2959 2960 KASSERT(mutex_owned(&sc->sc_lock)); 2961 2962 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2963 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 2964 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2965 ohci_free_std_locked(sc, opipe->tail.td); 2966 2967 usb_freemem(&sc->sc_bus, &opipe->ctrl.reqdma); 2968 } 2969 2970 /************************/ 2971 2972 Static void 2973 ohci_device_clear_toggle(struct usbd_pipe *pipe) 2974 { 2975 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2976 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2977 2978 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2979 } 2980 2981 Static void 2982 ohci_noop(struct usbd_pipe *pipe) 2983 { 2984 } 2985 2986 Static int 2987 ohci_device_bulk_init(struct usbd_xfer *xfer) 2988 { 2989 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2990 int len = xfer->ux_bufsize; 2991 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2992 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2993 int err; 2994 2995 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2996 2997 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2998 2999 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 3000 len, isread, xfer->ux_flags); 3001 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 3002 3003 /* Allocate a chain of new TDs (including a new tail). */ 3004 err = ohci_alloc_std_chain(sc, xfer, len, isread); 3005 if (err) 3006 return err; 3007 3008 return 0; 3009 } 3010 3011 Static void 3012 ohci_device_bulk_fini(struct usbd_xfer *xfer) 3013 { 3014 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3015 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3016 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3017 3018 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3019 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 3020 3021 mutex_enter(&sc->sc_lock); 3022 for (size_t i = 0; i < ox->ox_nstd; i++) { 3023 ohci_soft_td_t *std = ox->ox_stds[i]; 3024 if (std == NULL) 3025 break; 3026 if (std != opipe->tail.td) 3027 ohci_free_std_locked(sc, std); 3028 } 3029 mutex_exit(&sc->sc_lock); 3030 3031 if (ox->ox_nstd) { 3032 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 3033 kmem_free(ox->ox_stds, sz); 3034 } 3035 } 3036 3037 Static usbd_status 3038 ohci_device_bulk_transfer(struct usbd_xfer *xfer) 3039 { 3040 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3041 usbd_status err; 3042 3043 /* Insert last in queue. */ 3044 mutex_enter(&sc->sc_lock); 3045 err = usb_insert_transfer(xfer); 3046 mutex_exit(&sc->sc_lock); 3047 if (err) 3048 return err; 3049 3050 /* Pipe isn't running, start first */ 3051 return ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3052 } 3053 3054 Static usbd_status 3055 ohci_device_bulk_start(struct usbd_xfer *xfer) 3056 { 3057 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3058 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3059 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3060 ohci_soft_td_t *last; 3061 ohci_soft_td_t *data, *tail, *tdp; 3062 ohci_soft_ed_t *sed; 3063 int len, isread, endpt; 3064 const bool polling = sc->sc_bus.ub_usepolling; 3065 3066 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3067 3068 if (sc->sc_dying) 3069 return USBD_IOERROR; 3070 3071 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3072 3073 len = xfer->ux_length; 3074 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3075 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3076 sed = opipe->sed; 3077 3078 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 3079 len, isread, xfer->ux_flags); 3080 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 3081 3082 if (!polling) 3083 mutex_enter(&sc->sc_lock); 3084 3085 /* 3086 * Use the pipe "tail" TD as our first and loan our first TD to the 3087 * next transfer 3088 */ 3089 data = opipe->tail.td; 3090 opipe->tail.td = ox->ox_stds[0]; 3091 ox->ox_stds[0] = data; 3092 data->held = &ox->ox_stds[0]; 3093 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3094 DPRINTFN(10, "xfer=%#jx new data=%#jx held at %#jx", 3095 (uintptr_t)ox, (uintptr_t)data, (uintptr_t)data->held, 0); 3096 3097 /* point at sentinel */ 3098 tail = opipe->tail.td; 3099 memset(&tail->td, 0, sizeof(tail->td)); 3100 tail->held = &opipe->tail.td; 3101 tail->nexttd = NULL; 3102 tail->xfer = NULL; 3103 DPRINTFN(10, "xfer=%#jx new tail=%#jx held at %#ux", 3104 (uintptr_t)ox, (uintptr_t)tail, (uintptr_t)tail->held, 0); 3105 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3106 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3107 xfer->ux_hcpriv = data; 3108 3109 DPRINTFN(8, "xfer %#jx data %#jx tail %#jx", (uintptr_t)xfer, 3110 (uintptr_t)ox->ox_stds[0], (uintptr_t)tail, 0); 3111 KASSERT(opipe->tail.td == tail); 3112 3113 /* We want interrupt at the end of the transfer. */ 3114 last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3115 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3116 last->td.td_nexttd = HTOO32(tail->physaddr); 3117 last->nexttd = tail; 3118 last->flags |= OHCI_CALL_DONE; 3119 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3120 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3121 3122 DPRINTFN(4, "ed_flags=0x%08jx td_flags=0x%08jx " 3123 "td_cbp=0x%08jx td_be=0x%08jx", 3124 (int)O32TOH(sed->ed.ed_flags), 3125 (int)O32TOH(data->td.td_flags), 3126 (int)O32TOH(data->td.td_cbp), 3127 (int)O32TOH(data->td.td_be)); 3128 3129 #ifdef OHCI_DEBUG 3130 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3131 if (ohcidebug >= 5) { 3132 ohci_dump_ed(sc, sed); 3133 ohci_dump_tds(sc, data); 3134 } 3135 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3136 #endif 3137 3138 /* Insert ED in schedule */ 3139 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3140 KASSERT(tdp->xfer == xfer); 3141 } 3142 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3143 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3144 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3145 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3146 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3147 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3148 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3149 usbd_xfer_schedule_timeout(xfer); 3150 xfer->ux_status = USBD_IN_PROGRESS; 3151 if (!polling) 3152 mutex_exit(&sc->sc_lock); 3153 3154 return USBD_IN_PROGRESS; 3155 } 3156 3157 Static void 3158 ohci_device_bulk_abort(struct usbd_xfer *xfer) 3159 { 3160 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3161 3162 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3163 3164 KASSERT(mutex_owned(&sc->sc_lock)); 3165 3166 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3167 usbd_xfer_abort(xfer); 3168 } 3169 3170 /* 3171 * Close a device bulk pipe. 3172 */ 3173 Static void 3174 ohci_device_bulk_close(struct usbd_pipe *pipe) 3175 { 3176 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3177 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3178 3179 KASSERT(mutex_owned(&sc->sc_lock)); 3180 3181 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3182 3183 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3184 ohci_close_pipe(pipe, sc->sc_bulk_head); 3185 ohci_free_std_locked(sc, opipe->tail.td); 3186 } 3187 3188 /************************/ 3189 3190 Static int 3191 ohci_device_intr_init(struct usbd_xfer *xfer) 3192 { 3193 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3194 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3195 int len = xfer->ux_bufsize; 3196 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3197 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3198 int err; 3199 3200 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3201 3202 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3203 KASSERT(len != 0); 3204 3205 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 3206 len, isread, xfer->ux_flags); 3207 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 3208 3209 ox->ox_nstd = 0; 3210 3211 err = ohci_alloc_std_chain(sc, xfer, len, isread); 3212 if (err) { 3213 return err; 3214 } 3215 3216 return 0; 3217 } 3218 3219 Static void 3220 ohci_device_intr_fini(struct usbd_xfer *xfer) 3221 { 3222 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3223 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3224 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3225 3226 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3227 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 3228 3229 mutex_enter(&sc->sc_lock); 3230 for (size_t i = 0; i < ox->ox_nstd; i++) { 3231 ohci_soft_td_t *std = ox->ox_stds[i]; 3232 if (std != NULL) 3233 break; 3234 if (std != opipe->tail.td) 3235 ohci_free_std_locked(sc, std); 3236 } 3237 mutex_exit(&sc->sc_lock); 3238 3239 if (ox->ox_nstd) { 3240 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 3241 kmem_free(ox->ox_stds, sz); 3242 } 3243 } 3244 3245 Static usbd_status 3246 ohci_device_intr_transfer(struct usbd_xfer *xfer) 3247 { 3248 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3249 usbd_status err; 3250 3251 /* Insert last in queue. */ 3252 mutex_enter(&sc->sc_lock); 3253 err = usb_insert_transfer(xfer); 3254 mutex_exit(&sc->sc_lock); 3255 if (err) 3256 return err; 3257 3258 /* Pipe isn't running, start first */ 3259 return ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3260 } 3261 3262 Static usbd_status 3263 ohci_device_intr_start(struct usbd_xfer *xfer) 3264 { 3265 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3266 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3267 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3268 ohci_soft_ed_t *sed = opipe->sed; 3269 ohci_soft_td_t *data, *last, *tail; 3270 int len, isread, endpt; 3271 const bool polling = sc->sc_bus.ub_usepolling; 3272 3273 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3274 3275 if (sc->sc_dying) 3276 return USBD_IOERROR; 3277 3278 DPRINTFN(3, "xfer=%#jx len=%jd flags=%jd priv=%#jx", (uintptr_t)xfer, 3279 xfer->ux_length, xfer->ux_flags, (uintptr_t)xfer->ux_priv); 3280 3281 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3282 3283 len = xfer->ux_length; 3284 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3285 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3286 3287 if (!polling) 3288 mutex_enter(&sc->sc_lock); 3289 3290 /* 3291 * Use the pipe "tail" TD as our first and loan our first TD to the 3292 * next transfer. 3293 */ 3294 data = opipe->tail.td; 3295 opipe->tail.td = ox->ox_stds[0]; 3296 ox->ox_stds[0] = data; 3297 data->held = &ox->ox_stds[0]; 3298 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3299 DPRINTFN(10, "xfer=%#jx new data=%#jx held at %#jx", 3300 (uintptr_t)ox, (uintptr_t)data, (uintptr_t)data->held, 0); 3301 3302 /* point at sentinel */ 3303 tail = opipe->tail.td; 3304 memset(&tail->td, 0, sizeof(tail->td)); 3305 tail->held = &opipe->tail.td; 3306 tail->nexttd = NULL; 3307 tail->xfer = NULL; 3308 DPRINTFN(10, "xfer=%#jx new tail=%#jx held at %#jx", 3309 (uintptr_t)ox, (uintptr_t)tail, (uintptr_t)tail->held, 0); 3310 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3311 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3312 xfer->ux_hcpriv = data; 3313 3314 DPRINTFN(8, "data %#jx tail %#jx", (uintptr_t)ox->ox_stds[0], 3315 (uintptr_t)tail, 0, 0); 3316 KASSERT(opipe->tail.td == tail); 3317 3318 /* We want interrupt at the end of the transfer. */ 3319 last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3320 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3321 3322 last->td.td_nexttd = HTOO32(tail->physaddr); 3323 last->nexttd = tail; 3324 last->flags |= OHCI_CALL_DONE; 3325 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3326 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3327 3328 #ifdef OHCI_DEBUG 3329 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3330 if (ohcidebug >= 5) { 3331 ohci_dump_ed(sc, sed); 3332 ohci_dump_tds(sc, data); 3333 } 3334 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3335 #endif 3336 3337 /* Insert ED in schedule */ 3338 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3339 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3340 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3341 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3342 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3343 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3344 3345 xfer->ux_status = USBD_IN_PROGRESS; 3346 if (!polling) 3347 mutex_exit(&sc->sc_lock); 3348 3349 return USBD_IN_PROGRESS; 3350 } 3351 3352 /* Abort a device interrupt request. */ 3353 Static void 3354 ohci_device_intr_abort(struct usbd_xfer *xfer) 3355 { 3356 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3357 3358 KASSERT(mutex_owned(&sc->sc_lock)); 3359 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3360 3361 usbd_xfer_abort(xfer); 3362 } 3363 3364 /* Close a device interrupt pipe. */ 3365 Static void 3366 ohci_device_intr_close(struct usbd_pipe *pipe) 3367 { 3368 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3369 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3370 int nslots = opipe->intr.nslots; 3371 int pos = opipe->intr.pos; 3372 int j; 3373 ohci_soft_ed_t *p, *sed = opipe->sed; 3374 3375 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3376 3377 KASSERT(mutex_owned(&sc->sc_lock)); 3378 3379 DPRINTFN(1, "pipe=%#jx nslots=%jd pos=%jd", (uintptr_t)pipe, nslots, 3380 pos, 0); 3381 usb_syncmem(&sed->dma, sed->offs, 3382 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3383 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3384 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3385 sizeof(sed->ed.ed_flags), 3386 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3387 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3388 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3389 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3390 3391 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3392 continue; 3393 KASSERT(p); 3394 p->next = sed->next; 3395 p->ed.ed_nexted = sed->ed.ed_nexted; 3396 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3397 sizeof(p->ed.ed_nexted), 3398 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3399 3400 for (j = 0; j < nslots; j++) 3401 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3402 3403 ohci_free_std_locked(sc, opipe->tail.td); 3404 ohci_free_sed_locked(sc, opipe->sed); 3405 } 3406 3407 Static usbd_status 3408 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3409 { 3410 int i, j, best; 3411 u_int npoll, slow, shigh, nslots; 3412 u_int bestbw, bw; 3413 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3414 3415 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3416 3417 DPRINTFN(2, "pipe=%#jx", (uintptr_t)opipe, 0, 0, 0); 3418 if (ival == 0) { 3419 printf("ohci_setintr: 0 interval\n"); 3420 return USBD_INVAL; 3421 } 3422 3423 npoll = OHCI_NO_INTRS; 3424 while (npoll > ival) 3425 npoll /= 2; 3426 DPRINTFN(2, "ival=%jd npoll=%jd", ival, npoll, 0, 0); 3427 3428 /* 3429 * We now know which level in the tree the ED must go into. 3430 * Figure out which slot has most bandwidth left over. 3431 * Slots to examine: 3432 * npoll 3433 * 1 0 3434 * 2 1 2 3435 * 4 3 4 5 6 3436 * 8 7 8 9 10 11 12 13 14 3437 * N (N-1) .. (N-1+N-1) 3438 */ 3439 slow = npoll-1; 3440 shigh = slow + npoll; 3441 nslots = OHCI_NO_INTRS / npoll; 3442 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3443 bw = 0; 3444 for (j = 0; j < nslots; j++) 3445 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3446 if (bw < bestbw) { 3447 best = i; 3448 bestbw = bw; 3449 } 3450 } 3451 DPRINTFN(2, "best=%jd(%jd..%jd) bestbw=%jd", best, slow, shigh, bestbw); 3452 3453 mutex_enter(&sc->sc_lock); 3454 hsed = sc->sc_eds[best]; 3455 sed->next = hsed->next; 3456 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3457 sizeof(hsed->ed.ed_flags), 3458 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3459 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3460 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3461 sizeof(sed->ed.ed_flags), 3462 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3463 hsed->next = sed; 3464 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3465 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3466 sizeof(hsed->ed.ed_flags), 3467 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3468 mutex_exit(&sc->sc_lock); 3469 3470 for (j = 0; j < nslots; j++) 3471 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3472 opipe->intr.nslots = nslots; 3473 opipe->intr.pos = best; 3474 3475 DPRINTFN(5, "returns %#jx", (uintptr_t)opipe, 0, 0, 0); 3476 return USBD_NORMAL_COMPLETION; 3477 } 3478 3479 /***********************/ 3480 3481 Static int 3482 ohci_device_isoc_init(struct usbd_xfer *xfer) 3483 { 3484 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3485 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3486 ohci_soft_itd_t *sitd; 3487 size_t i; 3488 int err; 3489 3490 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3491 3492 DPRINTFN(1, "xfer %#jx len %jd flags %jd", (uintptr_t)xfer, 3493 xfer->ux_length, xfer->ux_flags, 0); 3494 3495 const size_t nfsitd = 3496 (xfer->ux_nframes + OHCI_ITD_NOFFSET - 1) / OHCI_ITD_NOFFSET; 3497 const size_t nbsitd = xfer->ux_bufsize / OHCI_PAGE_SIZE; 3498 const size_t nsitd = MAX(nfsitd, nbsitd) + 1; 3499 3500 ox->ox_sitds = kmem_zalloc(sizeof(ohci_soft_itd_t *) * nsitd, 3501 KM_SLEEP); 3502 ox->ox_nsitd = nsitd; 3503 3504 for (i = 0; i < nsitd; i++) { 3505 /* Allocate next ITD */ 3506 sitd = ohci_alloc_sitd(sc); 3507 if (sitd == NULL) { 3508 err = ENOMEM; 3509 goto fail; 3510 } 3511 ox->ox_sitds[i] = sitd; 3512 sitd->held = &ox->ox_sitds[i]; 3513 sitd->xfer = xfer; 3514 sitd->flags = 0; 3515 // DPRINTFN(10, "xfer=%#jx new tail=%#jx held at %#jx", 3516 // (uintptr_t)ox, (uintptr_t)tail, (uintptr_t)tail->held, 0); 3517 } 3518 3519 return 0; 3520 fail: 3521 for (; i > 0;) { 3522 ohci_free_sitd(sc, ox->ox_sitds[--i]); 3523 } 3524 return err; 3525 } 3526 3527 Static void 3528 ohci_device_isoc_fini(struct usbd_xfer *xfer) 3529 { 3530 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3531 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3532 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3533 3534 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3535 3536 mutex_enter(&sc->sc_lock); 3537 for (size_t i = 0; i < ox->ox_nsitd; i++) { 3538 if (ox->ox_sitds[i] != opipe->tail.itd) { 3539 ohci_free_sitd_locked(sc, ox->ox_sitds[i]); 3540 } 3541 } 3542 mutex_exit(&sc->sc_lock); 3543 3544 if (ox->ox_nsitd) { 3545 const size_t sz = sizeof(ohci_soft_itd_t *) * ox->ox_nsitd; 3546 kmem_free(ox->ox_sitds, sz); 3547 } 3548 } 3549 3550 3551 usbd_status 3552 ohci_device_isoc_transfer(struct usbd_xfer *xfer) 3553 { 3554 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3555 usbd_status __diagused err; 3556 3557 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3558 3559 DPRINTFN(5, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3560 3561 /* Put it on our queue, */ 3562 mutex_enter(&sc->sc_lock); 3563 err = usb_insert_transfer(xfer); 3564 mutex_exit(&sc->sc_lock); 3565 3566 KASSERT(err == USBD_NORMAL_COMPLETION); 3567 3568 /* insert into schedule, */ 3569 ohci_device_isoc_enter(xfer); 3570 3571 /* and start if the pipe wasn't running */ 3572 return USBD_IN_PROGRESS; 3573 } 3574 3575 void 3576 ohci_device_isoc_enter(struct usbd_xfer *xfer) 3577 { 3578 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3579 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3580 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3581 ohci_soft_ed_t *sed = opipe->sed; 3582 ohci_soft_itd_t *sitd, *nsitd, *tail; 3583 ohci_physaddr_t buf, offs, noffs, bp0; 3584 int i, ncur, nframes; 3585 3586 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3587 DPRINTFN(5, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3588 3589 mutex_enter(&sc->sc_lock); 3590 3591 if (sc->sc_dying) { 3592 mutex_exit(&sc->sc_lock); 3593 return; 3594 } 3595 3596 struct isoc *isoc = &opipe->isoc; 3597 3598 DPRINTFN(1, "used=%jd next=%jd xfer=%#jx nframes=%jd", 3599 isoc->inuse, isoc->next, (uintptr_t)xfer, xfer->ux_nframes); 3600 3601 if (isoc->next == -1) { 3602 /* Not in use yet, schedule it a few frames ahead. */ 3603 isoc->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3604 DPRINTFN(2,"start next=%jd", isoc->next, 0, 0, 0); 3605 } 3606 3607 sitd = opipe->tail.itd; 3608 opipe->tail.itd = ox->ox_sitds[0]; 3609 ox->ox_sitds[0] = sitd; 3610 sitd->held = &ox->ox_sitds[0]; 3611 3612 buf = DMAADDR(&xfer->ux_dmabuf, 0); 3613 bp0 = OHCI_PAGE(buf); 3614 offs = OHCI_PAGE_OFFSET(buf); 3615 nframes = xfer->ux_nframes; 3616 xfer->ux_hcpriv = sitd; 3617 size_t j = 1; 3618 for (i = ncur = 0; i < nframes; i++, ncur++) { 3619 noffs = offs + xfer->ux_frlengths[i]; 3620 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3621 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3622 3623 /* Allocate next ITD */ 3624 nsitd = ox->ox_sitds[j++]; 3625 KASSERT(nsitd != NULL); 3626 KASSERT(j < ox->ox_nsitd); 3627 3628 /* Fill current ITD */ 3629 sitd->itd.itd_flags = HTOO32( 3630 OHCI_ITD_NOCC | 3631 OHCI_ITD_SET_SF(isoc->next) | 3632 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3633 OHCI_ITD_SET_FC(ncur)); 3634 sitd->itd.itd_bp0 = HTOO32(bp0); 3635 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3636 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3637 sitd->nextitd = nsitd; 3638 sitd->xfer = xfer; 3639 sitd->flags = 0; 3640 #ifdef DIAGNOSTIC 3641 sitd->isdone = false; 3642 #endif 3643 ohci_hash_add_itd(sc, sitd); 3644 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3645 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3646 3647 sitd = nsitd; 3648 isoc->next = isoc->next + ncur; 3649 bp0 = OHCI_PAGE(buf + offs); 3650 ncur = 0; 3651 } 3652 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3653 /* XXX Sync */ 3654 offs = noffs; 3655 } 3656 KASSERT(j <= ox->ox_nsitd); 3657 3658 /* point at sentinel */ 3659 tail = opipe->tail.itd; 3660 memset(&tail->itd, 0, sizeof(tail->itd)); 3661 tail->held = &opipe->tail.itd; 3662 tail->nextitd = NULL; 3663 tail->xfer = NULL; 3664 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->itd), 3665 BUS_DMASYNC_PREWRITE); 3666 3667 /* Fixup last used ITD */ 3668 sitd->itd.itd_flags = HTOO32( 3669 OHCI_ITD_NOCC | 3670 OHCI_ITD_SET_SF(isoc->next) | 3671 OHCI_ITD_SET_DI(0) | 3672 OHCI_ITD_SET_FC(ncur)); 3673 sitd->itd.itd_bp0 = HTOO32(bp0); 3674 sitd->itd.itd_nextitd = HTOO32(tail->physaddr); 3675 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3676 sitd->nextitd = tail; 3677 sitd->xfer = xfer; 3678 sitd->flags = OHCI_CALL_DONE; 3679 #ifdef DIAGNOSTIC 3680 sitd->isdone = false; 3681 #endif 3682 ohci_hash_add_itd(sc, sitd); 3683 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3684 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3685 3686 isoc->next = isoc->next + ncur; 3687 isoc->inuse += nframes; 3688 3689 /* XXX pretend we did it all */ 3690 xfer->ux_actlen = offs; 3691 xfer->ux_status = USBD_IN_PROGRESS; 3692 3693 #ifdef OHCI_DEBUG 3694 if (ohcidebug >= 5) { 3695 DPRINTF("frame=%jd", O32TOH(sc->sc_hcca->hcca_frame_number), 3696 0, 0, 0); 3697 ohci_dump_itds(sc, xfer->ux_hcpriv); 3698 ohci_dump_ed(sc, sed); 3699 } 3700 #endif 3701 3702 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3703 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3704 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3705 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3706 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3707 sizeof(sed->ed.ed_flags), 3708 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3709 mutex_exit(&sc->sc_lock); 3710 } 3711 3712 void 3713 ohci_device_isoc_abort(struct usbd_xfer *xfer) 3714 { 3715 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3716 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3717 ohci_soft_ed_t *sed; 3718 ohci_soft_itd_t *sitd; 3719 3720 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3721 DPRINTFN(1, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3722 3723 KASSERT(mutex_owned(&sc->sc_lock)); 3724 3725 /* Transfer is already done. */ 3726 if (xfer->ux_status != USBD_NOT_STARTED && 3727 xfer->ux_status != USBD_IN_PROGRESS) { 3728 printf("ohci_device_isoc_abort: early return\n"); 3729 goto done; 3730 } 3731 3732 /* Give xfer the requested abort code. */ 3733 xfer->ux_status = USBD_CANCELLED; 3734 3735 sed = opipe->sed; 3736 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3737 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3738 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3739 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3740 sizeof(sed->ed.ed_flags), 3741 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3742 3743 sitd = xfer->ux_hcpriv; 3744 KASSERT(sitd); 3745 3746 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3747 3748 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3749 ohci_hash_rem_itd(sc, sitd); 3750 #ifdef DIAGNOSTIC 3751 DPRINTFN(1, "abort sets done sitd=%#jx", (uintptr_t)sitd, 3752 0, 0, 0); 3753 sitd->isdone = true; 3754 #endif 3755 } 3756 3757 /* Run callback. */ 3758 usb_transfer_complete(xfer); 3759 3760 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3761 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3762 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3763 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3764 3765 done: 3766 KASSERT(mutex_owned(&sc->sc_lock)); 3767 } 3768 3769 void 3770 ohci_device_isoc_done(struct usbd_xfer *xfer) 3771 { 3772 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3773 DPRINTFN(1, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3774 } 3775 3776 usbd_status 3777 ohci_setup_isoc(struct usbd_pipe *pipe) 3778 { 3779 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3780 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3781 struct isoc *isoc = &opipe->isoc; 3782 3783 isoc->next = -1; 3784 isoc->inuse = 0; 3785 3786 mutex_enter(&sc->sc_lock); 3787 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3788 mutex_exit(&sc->sc_lock); 3789 3790 return USBD_NORMAL_COMPLETION; 3791 } 3792 3793 void 3794 ohci_device_isoc_close(struct usbd_pipe *pipe) 3795 { 3796 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3797 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3798 3799 KASSERT(mutex_owned(&sc->sc_lock)); 3800 3801 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3802 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3803 ohci_close_pipe(pipe, sc->sc_isoc_head); 3804 #ifdef DIAGNOSTIC 3805 opipe->tail.itd->isdone = true; 3806 #endif 3807 ohci_free_sitd_locked(sc, opipe->tail.itd); 3808 } 3809
Indexes created Fri Oct 03 02:09:57 GMT 2025