ohci.c revision 1.293
1 /* $NetBSD: ohci.c,v 1.293 2020/02/12 16:01:00 riastradh Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * USB Open Host Controller driver. 38 * 39 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 40 * USB spec: http://www.usb.org/developers/docs/ 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.293 2020/02/12 16:01:00 riastradh Exp $"); 45 46 #ifdef _KERNEL_OPT 47 #include "opt_usb.h" 48 #endif 49 50 #include <sys/param.h> 51 52 #include <sys/cpu.h> 53 #include <sys/device.h> 54 #include <sys/kernel.h> 55 #include <sys/kmem.h> 56 #include <sys/proc.h> 57 #include <sys/queue.h> 58 #include <sys/select.h> 59 #include <sys/sysctl.h> 60 #include <sys/systm.h> 61 62 #include <machine/endian.h> 63 64 #include <dev/usb/usb.h> 65 #include <dev/usb/usbdi.h> 66 #include <dev/usb/usbdivar.h> 67 #include <dev/usb/usb_mem.h> 68 #include <dev/usb/usb_quirks.h> 69 70 #include <dev/usb/ohcireg.h> 71 #include <dev/usb/ohcivar.h> 72 #include <dev/usb/usbroothub.h> 73 #include <dev/usb/usbhist.h> 74 75 #ifdef USB_DEBUG 76 #ifndef OHCI_DEBUG 77 #define ohcidebug 0 78 #else 79 static int ohcidebug = 10; 80 81 SYSCTL_SETUP(sysctl_hw_ohci_setup, "sysctl hw.ohci setup") 82 { 83 int err; 84 const struct sysctlnode *rnode; 85 const struct sysctlnode *cnode; 86 87 err = sysctl_createv(clog, 0, NULL, &rnode, 88 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ohci", 89 SYSCTL_DESCR("ohci global controls"), 90 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 91 92 if (err) 93 goto fail; 94 95 /* control debugging printfs */ 96 err = sysctl_createv(clog, 0, &rnode, &cnode, 97 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 98 "debug", SYSCTL_DESCR("Enable debugging output"), 99 NULL, 0, &ohcidebug, sizeof(ohcidebug), CTL_CREATE, CTL_EOL); 100 if (err) 101 goto fail; 102 103 return; 104 fail: 105 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 106 } 107 108 #endif /* OHCI_DEBUG */ 109 #endif /* USB_DEBUG */ 110 111 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ohcidebug,FMT,A,B,C,D) 112 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ohcidebug,N,FMT,A,B,C,D) 113 #define OHCIHIST_FUNC() USBHIST_FUNC() 114 #define OHCIHIST_CALLED(name) USBHIST_CALLED(ohcidebug) 115 116 #if BYTE_ORDER == BIG_ENDIAN 117 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 118 #else 119 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 120 #endif 121 122 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 123 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 124 #define HTOO16(val) O16TOH(val) 125 #define HTOO32(val) O32TOH(val) 126 127 struct ohci_pipe; 128 129 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 130 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 131 132 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 133 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 134 Static void ohci_free_std_locked(ohci_softc_t *, ohci_soft_td_t *); 135 136 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 137 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 138 Static void ohci_free_sitd_locked(ohci_softc_t *, 139 ohci_soft_itd_t *); 140 141 Static int ohci_alloc_std_chain(ohci_softc_t *, struct usbd_xfer *, 142 int, int); 143 Static void ohci_free_stds(ohci_softc_t *, struct ohci_xfer *); 144 145 Static void ohci_reset_std_chain(ohci_softc_t *, struct usbd_xfer *, 146 int, int, ohci_soft_td_t *, ohci_soft_td_t **); 147 148 Static usbd_status ohci_open(struct usbd_pipe *); 149 Static void ohci_poll(struct usbd_bus *); 150 Static void ohci_softintr(void *); 151 Static void ohci_rhsc(ohci_softc_t *, struct usbd_xfer *); 152 Static void ohci_rhsc_softint(void *); 153 154 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 155 ohci_soft_ed_t *); 156 157 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 158 ohci_soft_ed_t *); 159 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 160 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 161 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 162 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 163 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 164 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 165 166 Static usbd_status ohci_setup_isoc(struct usbd_pipe *); 167 Static void ohci_device_isoc_enter(struct usbd_xfer *); 168 169 Static struct usbd_xfer * 170 ohci_allocx(struct usbd_bus *, unsigned int); 171 Static void ohci_freex(struct usbd_bus *, struct usbd_xfer *); 172 Static bool ohci_dying(struct usbd_bus *); 173 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 174 Static int ohci_roothub_ctrl(struct usbd_bus *, 175 usb_device_request_t *, void *, int); 176 177 Static usbd_status ohci_root_intr_transfer(struct usbd_xfer *); 178 Static usbd_status ohci_root_intr_start(struct usbd_xfer *); 179 Static void ohci_root_intr_abort(struct usbd_xfer *); 180 Static void ohci_root_intr_close(struct usbd_pipe *); 181 Static void ohci_root_intr_done(struct usbd_xfer *); 182 183 Static int ohci_device_ctrl_init(struct usbd_xfer *); 184 Static void ohci_device_ctrl_fini(struct usbd_xfer *); 185 Static usbd_status ohci_device_ctrl_transfer(struct usbd_xfer *); 186 Static usbd_status ohci_device_ctrl_start(struct usbd_xfer *); 187 Static void ohci_device_ctrl_abort(struct usbd_xfer *); 188 Static void ohci_device_ctrl_close(struct usbd_pipe *); 189 Static void ohci_device_ctrl_done(struct usbd_xfer *); 190 191 Static int ohci_device_bulk_init(struct usbd_xfer *); 192 Static void ohci_device_bulk_fini(struct usbd_xfer *); 193 Static usbd_status ohci_device_bulk_transfer(struct usbd_xfer *); 194 Static usbd_status ohci_device_bulk_start(struct usbd_xfer *); 195 Static void ohci_device_bulk_abort(struct usbd_xfer *); 196 Static void ohci_device_bulk_close(struct usbd_pipe *); 197 Static void ohci_device_bulk_done(struct usbd_xfer *); 198 199 Static int ohci_device_intr_init(struct usbd_xfer *); 200 Static void ohci_device_intr_fini(struct usbd_xfer *); 201 Static usbd_status ohci_device_intr_transfer(struct usbd_xfer *); 202 Static usbd_status ohci_device_intr_start(struct usbd_xfer *); 203 Static void ohci_device_intr_abort(struct usbd_xfer *); 204 Static void ohci_device_intr_close(struct usbd_pipe *); 205 Static void ohci_device_intr_done(struct usbd_xfer *); 206 207 Static int ohci_device_isoc_init(struct usbd_xfer *); 208 Static void ohci_device_isoc_fini(struct usbd_xfer *); 209 Static usbd_status ohci_device_isoc_transfer(struct usbd_xfer *); 210 Static void ohci_device_isoc_abort(struct usbd_xfer *); 211 Static void ohci_device_isoc_close(struct usbd_pipe *); 212 Static void ohci_device_isoc_done(struct usbd_xfer *); 213 214 Static usbd_status ohci_device_setintr(ohci_softc_t *, 215 struct ohci_pipe *, int); 216 217 Static void ohci_rhsc_enable(void *); 218 219 Static void ohci_close_pipe(struct usbd_pipe *, ohci_soft_ed_t *); 220 Static void ohci_abortx(struct usbd_xfer *); 221 222 Static void ohci_device_clear_toggle(struct usbd_pipe *); 223 Static void ohci_noop(struct usbd_pipe *); 224 225 #ifdef OHCI_DEBUG 226 Static void ohci_dumpregs(ohci_softc_t *); 227 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 228 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 229 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 230 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 231 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 232 #endif 233 234 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 235 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 236 #define OWRITE1(sc, r, x) \ 237 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 238 #define OWRITE2(sc, r, x) \ 239 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 240 #define OWRITE4(sc, r, x) \ 241 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 242 243 static __inline uint32_t 244 OREAD4(ohci_softc_t *sc, bus_size_t r) 245 { 246 247 OBARR(sc); 248 return bus_space_read_4(sc->iot, sc->ioh, r); 249 } 250 251 /* Reverse the bits in a value 0 .. 31 */ 252 Static uint8_t revbits[OHCI_NO_INTRS] = 253 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 254 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 255 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 256 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 257 258 struct ohci_pipe { 259 struct usbd_pipe pipe; 260 ohci_soft_ed_t *sed; 261 union { 262 ohci_soft_td_t *td; 263 ohci_soft_itd_t *itd; 264 } tail; 265 /* Info needed for different pipe kinds. */ 266 union { 267 /* Control pipe */ 268 struct { 269 usb_dma_t reqdma; 270 } ctrl; 271 /* Interrupt pipe */ 272 struct { 273 int nslots; 274 int pos; 275 } intr; 276 /* Isochronous pipe */ 277 struct isoc { 278 int next, inuse; 279 } isoc; 280 }; 281 }; 282 283 Static const struct usbd_bus_methods ohci_bus_methods = { 284 .ubm_open = ohci_open, 285 .ubm_softint = ohci_softintr, 286 .ubm_dopoll = ohci_poll, 287 .ubm_allocx = ohci_allocx, 288 .ubm_freex = ohci_freex, 289 .ubm_abortx = ohci_abortx, 290 .ubm_dying = ohci_dying, 291 .ubm_getlock = ohci_get_lock, 292 .ubm_rhctrl = ohci_roothub_ctrl, 293 }; 294 295 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 296 .upm_transfer = ohci_root_intr_transfer, 297 .upm_start = ohci_root_intr_start, 298 .upm_abort = ohci_root_intr_abort, 299 .upm_close = ohci_root_intr_close, 300 .upm_cleartoggle = ohci_noop, 301 .upm_done = ohci_root_intr_done, 302 }; 303 304 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 305 .upm_init = ohci_device_ctrl_init, 306 .upm_fini = ohci_device_ctrl_fini, 307 .upm_transfer = ohci_device_ctrl_transfer, 308 .upm_start = ohci_device_ctrl_start, 309 .upm_abort = ohci_device_ctrl_abort, 310 .upm_close = ohci_device_ctrl_close, 311 .upm_cleartoggle = ohci_noop, 312 .upm_done = ohci_device_ctrl_done, 313 }; 314 315 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 316 .upm_init = ohci_device_intr_init, 317 .upm_fini = ohci_device_intr_fini, 318 .upm_transfer = ohci_device_intr_transfer, 319 .upm_start = ohci_device_intr_start, 320 .upm_abort = ohci_device_intr_abort, 321 .upm_close = ohci_device_intr_close, 322 .upm_cleartoggle = ohci_device_clear_toggle, 323 .upm_done = ohci_device_intr_done, 324 }; 325 326 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 327 .upm_init = ohci_device_bulk_init, 328 .upm_fini = ohci_device_bulk_fini, 329 .upm_transfer = ohci_device_bulk_transfer, 330 .upm_start = ohci_device_bulk_start, 331 .upm_abort = ohci_device_bulk_abort, 332 .upm_close = ohci_device_bulk_close, 333 .upm_cleartoggle = ohci_device_clear_toggle, 334 .upm_done = ohci_device_bulk_done, 335 }; 336 337 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 338 .upm_init = ohci_device_isoc_init, 339 .upm_fini = ohci_device_isoc_fini, 340 .upm_transfer = ohci_device_isoc_transfer, 341 .upm_abort = ohci_device_isoc_abort, 342 .upm_close = ohci_device_isoc_close, 343 .upm_cleartoggle = ohci_noop, 344 .upm_done = ohci_device_isoc_done, 345 }; 346 347 int 348 ohci_activate(device_t self, enum devact act) 349 { 350 struct ohci_softc *sc = device_private(self); 351 352 switch (act) { 353 case DVACT_DEACTIVATE: 354 sc->sc_dying = 1; 355 return 0; 356 default: 357 return EOPNOTSUPP; 358 } 359 } 360 361 void 362 ohci_childdet(device_t self, device_t child) 363 { 364 struct ohci_softc *sc = device_private(self); 365 366 KASSERT(sc->sc_child == child); 367 sc->sc_child = NULL; 368 } 369 370 int 371 ohci_detach(struct ohci_softc *sc, int flags) 372 { 373 int rv = 0; 374 375 if (sc->sc_child != NULL) 376 rv = config_detach(sc->sc_child, flags); 377 378 if (rv != 0) 379 return rv; 380 381 softint_disestablish(sc->sc_rhsc_si); 382 383 callout_halt(&sc->sc_tmo_rhsc, NULL); 384 callout_destroy(&sc->sc_tmo_rhsc); 385 386 mutex_destroy(&sc->sc_lock); 387 mutex_destroy(&sc->sc_intr_lock); 388 389 if (sc->sc_hcca != NULL) 390 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 391 pool_cache_destroy(sc->sc_xferpool); 392 393 return rv; 394 } 395 396 ohci_soft_ed_t * 397 ohci_alloc_sed(ohci_softc_t *sc) 398 { 399 ohci_soft_ed_t *sed; 400 usbd_status err; 401 int i, offs; 402 usb_dma_t dma; 403 404 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 405 406 mutex_enter(&sc->sc_lock); 407 if (sc->sc_freeeds == NULL) { 408 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 409 mutex_exit(&sc->sc_lock); 410 411 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 412 OHCI_ED_ALIGN, &dma); 413 if (err) 414 return 0; 415 416 mutex_enter(&sc->sc_lock); 417 for (i = 0; i < OHCI_SED_CHUNK; i++) { 418 offs = i * OHCI_SED_SIZE; 419 sed = KERNADDR(&dma, offs); 420 sed->physaddr = DMAADDR(&dma, offs); 421 sed->dma = dma; 422 sed->offs = offs; 423 sed->next = sc->sc_freeeds; 424 sc->sc_freeeds = sed; 425 } 426 } 427 sed = sc->sc_freeeds; 428 sc->sc_freeeds = sed->next; 429 mutex_exit(&sc->sc_lock); 430 431 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 432 sed->next = 0; 433 return sed; 434 } 435 436 static inline void 437 ohci_free_sed_locked(ohci_softc_t *sc, ohci_soft_ed_t *sed) 438 { 439 440 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 441 442 sed->next = sc->sc_freeeds; 443 sc->sc_freeeds = sed; 444 } 445 446 void 447 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 448 { 449 450 mutex_enter(&sc->sc_lock); 451 ohci_free_sed_locked(sc, sed); 452 mutex_exit(&sc->sc_lock); 453 } 454 455 ohci_soft_td_t * 456 ohci_alloc_std(ohci_softc_t *sc) 457 { 458 ohci_soft_td_t *std; 459 usbd_status err; 460 int i, offs; 461 usb_dma_t dma; 462 463 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 464 465 mutex_enter(&sc->sc_lock); 466 if (sc->sc_freetds == NULL) { 467 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 468 mutex_exit(&sc->sc_lock); 469 470 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 471 OHCI_TD_ALIGN, &dma); 472 if (err) 473 return NULL; 474 475 mutex_enter(&sc->sc_lock); 476 for (i = 0; i < OHCI_STD_CHUNK; i++) { 477 offs = i * OHCI_STD_SIZE; 478 std = KERNADDR(&dma, offs); 479 std->physaddr = DMAADDR(&dma, offs); 480 std->dma = dma; 481 std->offs = offs; 482 std->nexttd = sc->sc_freetds; 483 sc->sc_freetds = std; 484 } 485 } 486 487 std = sc->sc_freetds; 488 sc->sc_freetds = std->nexttd; 489 mutex_exit(&sc->sc_lock); 490 491 memset(&std->td, 0, sizeof(ohci_td_t)); 492 std->nexttd = NULL; 493 std->xfer = NULL; 494 495 return std; 496 } 497 498 void 499 ohci_free_std_locked(ohci_softc_t *sc, ohci_soft_td_t *std) 500 { 501 502 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 503 504 std->nexttd = sc->sc_freetds; 505 sc->sc_freetds = std; 506 } 507 508 void 509 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 510 { 511 512 mutex_enter(&sc->sc_lock); 513 ohci_free_std_locked(sc, std); 514 mutex_exit(&sc->sc_lock); 515 } 516 517 Static int 518 ohci_alloc_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, int length, int rd) 519 { 520 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 521 uint16_t flags = xfer->ux_flags; 522 523 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 524 525 DPRINTFN(8, "addr=%jd endpt=%jd len=%jd speed=%jd", 526 xfer->ux_pipe->up_dev->ud_addr, 527 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 528 length, xfer->ux_pipe->up_dev->ud_speed); 529 530 ASSERT_SLEEPABLE(); 531 KASSERT(length != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 532 533 size_t nstd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 534 nstd += ((length + OHCI_PAGE_SIZE - 1) / OHCI_PAGE_SIZE); 535 ox->ox_stds = kmem_zalloc(sizeof(ohci_soft_td_t *) * nstd, 536 KM_SLEEP); 537 ox->ox_nstd = nstd; 538 539 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, nstd, 0, 0); 540 541 for (size_t j = 0; j < ox->ox_nstd;) { 542 ohci_soft_td_t *cur = ohci_alloc_std(sc); 543 if (cur == NULL) 544 goto nomem; 545 546 ox->ox_stds[j++] = cur; 547 cur->xfer = xfer; 548 cur->flags = 0; 549 } 550 551 return 0; 552 553 nomem: 554 ohci_free_stds(sc, ox); 555 kmem_free(ox->ox_stds, sizeof(ohci_soft_td_t *) * nstd); 556 557 return ENOMEM; 558 } 559 560 Static void 561 ohci_free_stds(ohci_softc_t *sc, struct ohci_xfer *ox) 562 { 563 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 564 DPRINTF("ox=%#jx", (uintptr_t)ox, 0, 0, 0); 565 566 mutex_enter(&sc->sc_lock); 567 for (size_t i = 0; i < ox->ox_nstd; i++) { 568 ohci_soft_td_t *std = ox->ox_stds[i]; 569 if (std == NULL) 570 break; 571 ohci_free_std_locked(sc, std); 572 } 573 mutex_exit(&sc->sc_lock); 574 } 575 576 void 577 ohci_reset_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, 578 int alen, int rd, ohci_soft_td_t *sp, ohci_soft_td_t **ep) 579 { 580 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 581 ohci_soft_td_t *next, *cur; 582 int len, curlen; 583 usb_dma_t *dma = &xfer->ux_dmabuf; 584 uint16_t flags = xfer->ux_flags; 585 586 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 587 DPRINTF("start len=%jd", alen, 0, 0, 0); 588 589 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 590 591 DPRINTFN(8, "addr=%jd endpt=%jd len=%jd speed=%jd", 592 xfer->ux_pipe->up_dev->ud_addr, 593 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 594 alen, xfer->ux_pipe->up_dev->ud_speed); 595 596 KASSERT(sp); 597 598 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 599 600 /* 601 * Assign next for the len == 0 case where we don't go through the 602 * main loop. 603 */ 604 len = alen; 605 cur = next = sp; 606 607 usb_syncmem(dma, 0, len, 608 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 609 const uint32_t tdflags = HTOO32( 610 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 611 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 612 613 size_t curoffs = 0; 614 for (size_t j = 1; len != 0;) { 615 if (j == ox->ox_nstd) 616 next = NULL; 617 else 618 next = ox->ox_stds[j++]; 619 KASSERT(next != cur); 620 621 curlen = 0; 622 const ohci_physaddr_t sdataphys = DMAADDR(dma, curoffs); 623 ohci_physaddr_t edataphys = DMAADDR(dma, curoffs + len - 1); 624 625 const ohci_physaddr_t sphyspg = OHCI_PAGE(sdataphys); 626 ohci_physaddr_t ephyspg = OHCI_PAGE(edataphys); 627 /* 628 * The OHCI hardware can handle at most one page 629 * crossing per TD 630 */ 631 curlen = len; 632 if (sphyspg != ephyspg && 633 sphyspg + OHCI_PAGE_SIZE != ephyspg) { 634 /* must use multiple TDs, fill as much as possible. */ 635 curlen = 2 * OHCI_PAGE_SIZE - 636 OHCI_PAGE_OFFSET(sdataphys); 637 /* the length must be a multiple of the max size */ 638 curlen -= curlen % mps; 639 edataphys = DMAADDR(dma, curoffs + curlen - 1); 640 } 641 KASSERT(curlen != 0); 642 DPRINTFN(4, "sdataphys=0x%08jx edataphys=0x%08jx " 643 "len=%jd curlen=%jd", sdataphys, edataphys, len, curlen); 644 645 cur->td.td_flags = tdflags; 646 cur->td.td_cbp = HTOO32(sdataphys); 647 cur->td.td_be = HTOO32(edataphys); 648 cur->td.td_nexttd = (next != NULL) ? HTOO32(next->physaddr) : 0; 649 cur->nexttd = next; 650 cur->len = curlen; 651 cur->flags = OHCI_ADD_LEN; 652 cur->xfer = xfer; 653 ohci_hash_add_td(sc, cur); 654 655 curoffs += curlen; 656 len -= curlen; 657 658 if (len != 0) { 659 KASSERT(next != NULL); 660 DPRINTFN(10, "extend chain", 0, 0, 0, 0); 661 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 662 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 663 664 cur = next; 665 } 666 } 667 cur->td.td_flags |= 668 HTOO32(xfer->ux_flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0); 669 670 if (!rd && 671 (flags & USBD_FORCE_SHORT_XFER) && 672 alen % mps == 0) { 673 /* We're adding a ZLP so sync the previous TD */ 674 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 675 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 676 677 /* Force a 0 length transfer at the end. */ 678 679 KASSERT(next != NULL); 680 cur = next; 681 682 cur->td.td_flags = tdflags; 683 cur->td.td_cbp = 0; /* indicate 0 length packet */ 684 cur->td.td_nexttd = 0; 685 cur->td.td_be = ~0; 686 cur->nexttd = NULL; 687 cur->len = 0; 688 cur->flags = 0; 689 cur->xfer = xfer; 690 ohci_hash_add_td(sc, cur); 691 692 DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0); 693 } 694 695 /* Last TD gets usb_syncmem'ed by caller */ 696 *ep = cur; 697 } 698 699 ohci_soft_itd_t * 700 ohci_alloc_sitd(ohci_softc_t *sc) 701 { 702 ohci_soft_itd_t *sitd; 703 usbd_status err; 704 int i, offs; 705 usb_dma_t dma; 706 707 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 708 709 mutex_enter(&sc->sc_lock); 710 if (sc->sc_freeitds == NULL) { 711 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 712 mutex_exit(&sc->sc_lock); 713 714 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 715 OHCI_ITD_ALIGN, &dma); 716 if (err) 717 return NULL; 718 mutex_enter(&sc->sc_lock); 719 for (i = 0; i < OHCI_SITD_CHUNK; i++) { 720 offs = i * OHCI_SITD_SIZE; 721 sitd = KERNADDR(&dma, offs); 722 sitd->physaddr = DMAADDR(&dma, offs); 723 sitd->dma = dma; 724 sitd->offs = offs; 725 sitd->nextitd = sc->sc_freeitds; 726 sc->sc_freeitds = sitd; 727 } 728 } 729 730 sitd = sc->sc_freeitds; 731 sc->sc_freeitds = sitd->nextitd; 732 mutex_exit(&sc->sc_lock); 733 734 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 735 sitd->nextitd = NULL; 736 sitd->xfer = NULL; 737 738 #ifdef DIAGNOSTIC 739 sitd->isdone = true; 740 #endif 741 742 return sitd; 743 } 744 745 Static void 746 ohci_free_sitd_locked(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 747 { 748 749 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 750 DPRINTFN(10, "sitd=%#jx", (uintptr_t)sitd, 0, 0, 0); 751 752 KASSERT(sitd->isdone); 753 #ifdef DIAGNOSTIC 754 /* Warn double free */ 755 sitd->isdone = false; 756 #endif 757 758 sitd->nextitd = sc->sc_freeitds; 759 sc->sc_freeitds = sitd; 760 } 761 762 void 763 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 764 { 765 766 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 767 768 mutex_enter(&sc->sc_lock); 769 ohci_free_sitd_locked(sc, sitd); 770 mutex_exit(&sc->sc_lock); 771 } 772 773 int 774 ohci_init(ohci_softc_t *sc) 775 { 776 ohci_soft_ed_t *sed, *psed; 777 usbd_status err; 778 int i; 779 uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */; 780 781 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 782 783 aprint_normal_dev(sc->sc_dev, ""); 784 785 sc->sc_hcca = NULL; 786 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 787 788 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 789 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 790 791 sc->sc_rhsc_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 792 ohci_rhsc_softint, sc); 793 794 for (i = 0; i < OHCI_HASH_SIZE; i++) 795 LIST_INIT(&sc->sc_hash_tds[i]); 796 for (i = 0; i < OHCI_HASH_SIZE; i++) 797 LIST_INIT(&sc->sc_hash_itds[i]); 798 799 sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0, 800 "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL); 801 802 rev = OREAD4(sc, OHCI_REVISION); 803 aprint_normal("OHCI version %d.%d%s\n", 804 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 805 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 806 807 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 808 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 809 sc->sc_bus.ub_revision = USBREV_UNKNOWN; 810 return -1; 811 } 812 sc->sc_bus.ub_revision = USBREV_1_0; 813 sc->sc_bus.ub_usedma = true; 814 815 /* XXX determine alignment by R/W */ 816 /* Allocate the HCCA area. */ 817 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 818 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 819 if (err) { 820 sc->sc_hcca = NULL; 821 return err; 822 } 823 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 824 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 825 826 sc->sc_eintrs = OHCI_NORMAL_INTRS; 827 828 /* Allocate dummy ED that starts the control list. */ 829 sc->sc_ctrl_head = ohci_alloc_sed(sc); 830 if (sc->sc_ctrl_head == NULL) { 831 err = ENOMEM; 832 goto bad1; 833 } 834 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 835 836 /* Allocate dummy ED that starts the bulk list. */ 837 sc->sc_bulk_head = ohci_alloc_sed(sc); 838 if (sc->sc_bulk_head == NULL) { 839 err = ENOMEM; 840 goto bad2; 841 } 842 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 843 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 844 sizeof(sc->sc_bulk_head->ed), 845 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 846 847 /* Allocate dummy ED that starts the isochronous list. */ 848 sc->sc_isoc_head = ohci_alloc_sed(sc); 849 if (sc->sc_isoc_head == NULL) { 850 err = ENOMEM; 851 goto bad3; 852 } 853 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 854 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 855 sizeof(sc->sc_isoc_head->ed), 856 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 857 858 /* Allocate all the dummy EDs that make up the interrupt tree. */ 859 for (i = 0; i < OHCI_NO_EDS; i++) { 860 sed = ohci_alloc_sed(sc); 861 if (sed == NULL) { 862 while (--i >= 0) 863 ohci_free_sed(sc, sc->sc_eds[i]); 864 err = ENOMEM; 865 goto bad4; 866 } 867 /* All ED fields are set to 0. */ 868 sc->sc_eds[i] = sed; 869 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 870 if (i != 0) 871 psed = sc->sc_eds[(i-1) / 2]; 872 else 873 psed= sc->sc_isoc_head; 874 sed->next = psed; 875 sed->ed.ed_nexted = HTOO32(psed->physaddr); 876 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 877 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 878 } 879 /* 880 * Fill HCCA interrupt table. The bit reversal is to get 881 * the tree set up properly to spread the interrupts. 882 */ 883 for (i = 0; i < OHCI_NO_INTRS; i++) 884 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 885 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 886 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 887 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 888 889 #ifdef OHCI_DEBUG 890 DPRINTFN(15, "--- dump start ---", 0, 0, 0 ,0); 891 if (ohcidebug >= 15) { 892 for (i = 0; i < OHCI_NO_EDS; i++) { 893 DPRINTFN(15, "ed#%jd ", i, 0, 0, 0); 894 ohci_dump_ed(sc, sc->sc_eds[i]); 895 } 896 DPRINTFN(15, "iso", 0, 0, 0 ,0); 897 ohci_dump_ed(sc, sc->sc_isoc_head); 898 } 899 DPRINTFN(15, "--- dump end ---", 0, 0, 0 ,0); 900 #endif 901 902 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 903 ctl = OREAD4(sc, OHCI_CONTROL); 904 rwc = ctl & OHCI_RWC; 905 fm = OREAD4(sc, OHCI_FM_INTERVAL); 906 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 907 /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */ 908 909 /* Determine in what context we are running. */ 910 if (ctl & OHCI_IR) { 911 /* SMM active, request change */ 912 DPRINTF("SMM active, request owner change", 0, 0, 0, 0); 913 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 914 (OHCI_OC | OHCI_MIE)) 915 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 916 s = OREAD4(sc, OHCI_COMMAND_STATUS); 917 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 918 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 919 usb_delay_ms(&sc->sc_bus, 1); 920 ctl = OREAD4(sc, OHCI_CONTROL); 921 } 922 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 923 if ((ctl & OHCI_IR) == 0) { 924 aprint_error_dev(sc->sc_dev, 925 "SMM does not respond, resetting\n"); 926 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 927 goto reset; 928 } 929 #if 0 930 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 931 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 932 /* BIOS started controller. */ 933 DPRINTF("BIOS active", 0, 0, 0, 0); 934 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 935 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 936 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 937 } 938 #endif 939 } else { 940 DPRINTF("cold started", 0 ,0 ,0 ,0); 941 reset: 942 /* Controller was cold started. */ 943 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 944 } 945 946 /* 947 * This reset should not be necessary according to the OHCI spec, but 948 * without it some controllers do not start. 949 */ 950 DPRINTF("sc %#jx: resetting", (uintptr_t)sc, 0, 0, 0); 951 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 952 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 953 954 /* We now own the host controller and the bus has been reset. */ 955 956 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 957 /* Nominal time for a reset is 10 us. */ 958 for (i = 0; i < 10; i++) { 959 delay(10); 960 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 961 if (!hcr) 962 break; 963 } 964 if (hcr) { 965 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 966 err = EIO; 967 goto bad5; 968 } 969 #ifdef OHCI_DEBUG 970 if (ohcidebug >= 15) 971 ohci_dumpregs(sc); 972 #endif 973 974 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 975 976 /* Set up HC registers. */ 977 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 978 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 979 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 980 /* disable all interrupts and then switch on all desired interrupts */ 981 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 982 /* switch on desired functional features */ 983 ctl = OREAD4(sc, OHCI_CONTROL); 984 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 985 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 986 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 987 /* And finally start it! */ 988 OWRITE4(sc, OHCI_CONTROL, ctl); 989 990 /* 991 * The controller is now OPERATIONAL. Set a some final 992 * registers that should be set earlier, but that the 993 * controller ignores when in the SUSPEND state. 994 */ 995 ival = OHCI_GET_IVAL(fm); 996 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 997 fm |= OHCI_FSMPS(ival) | ival; 998 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 999 per = OHCI_PERIODIC(ival); /* 90% periodic */ 1000 OWRITE4(sc, OHCI_PERIODIC_START, per); 1001 1002 if (sc->sc_flags & OHCIF_SUPERIO) { 1003 /* no overcurrent protection */ 1004 desca |= OHCI_NOCP; 1005 /* 1006 * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning 1007 * that 1008 * - ports are always power switched 1009 * - don't wait for powered root hub port 1010 */ 1011 desca &= ~(__SHIFTIN(0xff, OHCI_POTPGT_MASK) | OHCI_NPS); 1012 } 1013 1014 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 1015 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 1016 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 1017 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 1018 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 1019 1020 /* 1021 * The AMD756 requires a delay before re-reading the register, 1022 * otherwise it will occasionally report 0 ports. 1023 */ 1024 sc->sc_noport = 0; 1025 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 1026 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 1027 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 1028 } 1029 1030 #ifdef OHCI_DEBUG 1031 if (ohcidebug >= 5) 1032 ohci_dumpregs(sc); 1033 #endif 1034 1035 /* Set up the bus struct. */ 1036 sc->sc_bus.ub_methods = &ohci_bus_methods; 1037 sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe); 1038 1039 sc->sc_control = sc->sc_intre = 0; 1040 1041 /* Finally, turn on interrupts. */ 1042 DPRINTF("enabling %#jx", sc->sc_eintrs | OHCI_MIE, 0, 0, 0); 1043 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 1044 1045 return 0; 1046 1047 bad5: 1048 for (i = 0; i < OHCI_NO_EDS; i++) 1049 ohci_free_sed(sc, sc->sc_eds[i]); 1050 bad4: 1051 ohci_free_sed(sc, sc->sc_isoc_head); 1052 bad3: 1053 ohci_free_sed(sc, sc->sc_bulk_head); 1054 bad2: 1055 ohci_free_sed(sc, sc->sc_ctrl_head); 1056 bad1: 1057 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 1058 sc->sc_hcca = NULL; 1059 return err; 1060 } 1061 1062 struct usbd_xfer * 1063 ohci_allocx(struct usbd_bus *bus, unsigned int nframes) 1064 { 1065 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1066 struct usbd_xfer *xfer; 1067 1068 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 1069 if (xfer != NULL) { 1070 memset(xfer, 0, sizeof(struct ohci_xfer)); 1071 1072 #ifdef DIAGNOSTIC 1073 xfer->ux_state = XFER_BUSY; 1074 #endif 1075 } 1076 return xfer; 1077 } 1078 1079 void 1080 ohci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1081 { 1082 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1083 1084 KASSERTMSG(xfer->ux_state == XFER_BUSY || 1085 xfer->ux_status == USBD_NOT_STARTED, 1086 "xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state); 1087 #ifdef DIAGNOSTIC 1088 xfer->ux_state = XFER_FREE; 1089 #endif 1090 pool_cache_put(sc->sc_xferpool, xfer); 1091 } 1092 1093 Static bool 1094 ohci_dying(struct usbd_bus *bus) 1095 { 1096 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1097 1098 return sc->sc_dying; 1099 } 1100 1101 Static void 1102 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1103 { 1104 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1105 1106 *lock = &sc->sc_lock; 1107 } 1108 1109 /* 1110 * Shut down the controller when the system is going down. 1111 */ 1112 bool 1113 ohci_shutdown(device_t self, int flags) 1114 { 1115 ohci_softc_t *sc = device_private(self); 1116 1117 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1118 1119 DPRINTF("stopping the HC", 0, 0, 0, 0); 1120 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 1121 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1122 return true; 1123 } 1124 1125 bool 1126 ohci_resume(device_t dv, const pmf_qual_t *qual) 1127 { 1128 ohci_softc_t *sc = device_private(dv); 1129 uint32_t ctl; 1130 1131 mutex_spin_enter(&sc->sc_intr_lock); 1132 sc->sc_bus.ub_usepolling++; 1133 mutex_spin_exit(&sc->sc_intr_lock); 1134 1135 /* Some broken BIOSes do not recover these values */ 1136 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1137 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1138 sc->sc_ctrl_head->physaddr); 1139 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1140 sc->sc_bulk_head->physaddr); 1141 if (sc->sc_intre) 1142 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1143 (OHCI_ALL_INTRS | OHCI_MIE)); 1144 if (sc->sc_control) 1145 ctl = sc->sc_control; 1146 else 1147 ctl = OREAD4(sc, OHCI_CONTROL); 1148 ctl |= OHCI_HCFS_RESUME; 1149 OWRITE4(sc, OHCI_CONTROL, ctl); 1150 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1151 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1152 OWRITE4(sc, OHCI_CONTROL, ctl); 1153 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1154 sc->sc_control = sc->sc_intre = 0; 1155 1156 mutex_spin_enter(&sc->sc_intr_lock); 1157 sc->sc_bus.ub_usepolling--; 1158 mutex_spin_exit(&sc->sc_intr_lock); 1159 1160 return true; 1161 } 1162 1163 bool 1164 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1165 { 1166 ohci_softc_t *sc = device_private(dv); 1167 uint32_t ctl; 1168 1169 mutex_spin_enter(&sc->sc_intr_lock); 1170 sc->sc_bus.ub_usepolling++; 1171 mutex_spin_exit(&sc->sc_intr_lock); 1172 1173 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1174 if (sc->sc_control == 0) { 1175 /* 1176 * Preserve register values, in case that BIOS 1177 * does not recover them. 1178 */ 1179 sc->sc_control = ctl; 1180 sc->sc_intre = OREAD4(sc, 1181 OHCI_INTERRUPT_ENABLE); 1182 } 1183 ctl |= OHCI_HCFS_SUSPEND; 1184 OWRITE4(sc, OHCI_CONTROL, ctl); 1185 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1186 1187 mutex_spin_enter(&sc->sc_intr_lock); 1188 sc->sc_bus.ub_usepolling--; 1189 mutex_spin_exit(&sc->sc_intr_lock); 1190 1191 return true; 1192 } 1193 1194 #ifdef OHCI_DEBUG 1195 void 1196 ohci_dumpregs(ohci_softc_t *sc) 1197 { 1198 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1199 1200 DPRINTF("rev=0x%08jx control=0x%08jx command=0x%08jx", 1201 OREAD4(sc, OHCI_REVISION), 1202 OREAD4(sc, OHCI_CONTROL), 1203 OREAD4(sc, OHCI_COMMAND_STATUS), 0); 1204 DPRINTF(" intrstat=0x%08jx intre=0x%08jx intrd=0x%08jx", 1205 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1206 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1207 OREAD4(sc, OHCI_INTERRUPT_DISABLE), 0); 1208 DPRINTF(" hcca=0x%08jx percur=0x%08jx ctrlhd=0x%08jx", 1209 OREAD4(sc, OHCI_HCCA), 1210 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1211 OREAD4(sc, OHCI_CONTROL_HEAD_ED), 0); 1212 DPRINTF(" ctrlcur=0x%08jx bulkhd=0x%08jx bulkcur=0x%08jx", 1213 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1214 OREAD4(sc, OHCI_BULK_HEAD_ED), 1215 OREAD4(sc, OHCI_BULK_CURRENT_ED) ,0); 1216 DPRINTF(" done=0x%08jx fmival=0x%08jx fmrem=0x%08jx", 1217 OREAD4(sc, OHCI_DONE_HEAD), 1218 OREAD4(sc, OHCI_FM_INTERVAL), 1219 OREAD4(sc, OHCI_FM_REMAINING), 0); 1220 DPRINTF(" fmnum=0x%08jx perst=0x%08jx lsthrs=0x%08jx", 1221 OREAD4(sc, OHCI_FM_NUMBER), 1222 OREAD4(sc, OHCI_PERIODIC_START), 1223 OREAD4(sc, OHCI_LS_THRESHOLD), 0); 1224 DPRINTF(" desca=0x%08jx descb=0x%08jx stat=0x%08jx", 1225 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1226 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1227 OREAD4(sc, OHCI_RH_STATUS), 0); 1228 DPRINTF(" port1=0x%08jx port2=0x%08jx", 1229 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1230 OREAD4(sc, OHCI_RH_PORT_STATUS(2)), 0, 0); 1231 DPRINTF(" HCCA: frame_number=0x%04jx done_head=0x%08jx", 1232 O32TOH(sc->sc_hcca->hcca_frame_number), 1233 O32TOH(sc->sc_hcca->hcca_done_head), 0, 0); 1234 } 1235 #endif 1236 1237 Static int ohci_intr1(ohci_softc_t *); 1238 1239 int 1240 ohci_intr(void *p) 1241 { 1242 ohci_softc_t *sc = p; 1243 int ret = 0; 1244 1245 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1246 1247 if (sc == NULL) 1248 return 0; 1249 1250 mutex_spin_enter(&sc->sc_intr_lock); 1251 1252 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1253 goto done; 1254 1255 /* If we get an interrupt while polling, then just ignore it. */ 1256 if (sc->sc_bus.ub_usepolling) { 1257 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1258 /* for level triggered intrs, should do something to ack */ 1259 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1260 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1261 1262 goto done; 1263 } 1264 1265 ret = ohci_intr1(sc); 1266 1267 done: 1268 mutex_spin_exit(&sc->sc_intr_lock); 1269 return ret; 1270 } 1271 1272 Static int 1273 ohci_intr1(ohci_softc_t *sc) 1274 { 1275 uint32_t intrs, eintrs; 1276 1277 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1278 1279 /* In case the interrupt occurs before initialization has completed. */ 1280 if (sc == NULL || sc->sc_hcca == NULL) { 1281 #ifdef DIAGNOSTIC 1282 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1283 #endif 1284 return 0; 1285 } 1286 1287 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1288 1289 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1290 if (!intrs) 1291 return 0; 1292 1293 /* Acknowledge */ 1294 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); 1295 eintrs = intrs & sc->sc_eintrs; 1296 DPRINTFN(7, "sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1297 DPRINTFN(7, "intrs=%#jx(%#jx) eintrs=%#jx(%#jx)", 1298 intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), eintrs, 1299 sc->sc_eintrs); 1300 1301 if (!eintrs) { 1302 return 0; 1303 } 1304 1305 if (eintrs & OHCI_SO) { 1306 sc->sc_overrun_cnt++; 1307 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1308 printf("%s: %u scheduling overruns\n", 1309 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1310 sc->sc_overrun_cnt = 0; 1311 } 1312 /* XXX do what */ 1313 eintrs &= ~OHCI_SO; 1314 } 1315 if (eintrs & OHCI_WDH) { 1316 /* 1317 * We block the interrupt below, and reenable it later from 1318 * ohci_softintr(). 1319 */ 1320 usb_schedsoftintr(&sc->sc_bus); 1321 } 1322 if (eintrs & OHCI_RD) { 1323 DPRINTFN(5, "resume detect sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1324 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1325 /* XXX process resume detect */ 1326 } 1327 if (eintrs & OHCI_UE) { 1328 DPRINTFN(5, "unrecoverable error sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1329 printf("%s: unrecoverable error, controller halted\n", 1330 device_xname(sc->sc_dev)); 1331 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1332 /* XXX what else */ 1333 } 1334 if (eintrs & OHCI_RHSC) { 1335 /* 1336 * We block the interrupt below, and reenable it later from 1337 * a timeout. 1338 */ 1339 softint_schedule(sc->sc_rhsc_si); 1340 } 1341 1342 if (eintrs != 0) { 1343 /* Block unprocessed interrupts. */ 1344 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1345 sc->sc_eintrs &= ~eintrs; 1346 DPRINTF("sc %#jx blocking intrs 0x%jx", (uintptr_t)sc, 1347 eintrs, 0, 0); 1348 } 1349 1350 return 1; 1351 } 1352 1353 void 1354 ohci_rhsc_enable(void *v_sc) 1355 { 1356 ohci_softc_t *sc = v_sc; 1357 1358 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1359 DPRINTF("sc %#jx", (uintptr_t)sc, 0, 0, 0); 1360 mutex_spin_enter(&sc->sc_intr_lock); 1361 sc->sc_eintrs |= OHCI_RHSC; 1362 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1363 mutex_spin_exit(&sc->sc_intr_lock); 1364 } 1365 1366 #ifdef OHCI_DEBUG 1367 const char *ohci_cc_strs[] = { 1368 "NO_ERROR", 1369 "CRC", 1370 "BIT_STUFFING", 1371 "DATA_TOGGLE_MISMATCH", 1372 "STALL", 1373 "DEVICE_NOT_RESPONDING", 1374 "PID_CHECK_FAILURE", 1375 "UNEXPECTED_PID", 1376 "DATA_OVERRUN", 1377 "DATA_UNDERRUN", 1378 "BUFFER_OVERRUN", 1379 "BUFFER_UNDERRUN", 1380 "reserved", 1381 "reserved", 1382 "NOT_ACCESSED", 1383 "NOT_ACCESSED", 1384 }; 1385 #endif 1386 1387 void 1388 ohci_softintr(void *v) 1389 { 1390 struct usbd_bus *bus = v; 1391 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1392 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1393 ohci_soft_td_t *std, *sdone, *stdnext; 1394 struct usbd_xfer *xfer; 1395 struct ohci_pipe *opipe; 1396 int len, cc; 1397 int i, j, actlen, iframes, uedir; 1398 ohci_physaddr_t done; 1399 1400 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1401 1402 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1403 1404 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1405 sizeof(sc->sc_hcca->hcca_done_head), 1406 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1407 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1408 sc->sc_hcca->hcca_done_head = 0; 1409 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1410 sizeof(sc->sc_hcca->hcca_done_head), 1411 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1412 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1413 sc->sc_eintrs |= OHCI_WDH; 1414 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1415 1416 /* Reverse the done list. */ 1417 for (sdone = NULL, sidone = NULL; done != 0; ) { 1418 std = ohci_hash_find_td(sc, done); 1419 if (std != NULL) { 1420 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1421 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1422 std->dnext = sdone; 1423 done = O32TOH(std->td.td_nexttd); 1424 sdone = std; 1425 DPRINTFN(10, "add TD %#jx", (uintptr_t)std, 0, 0, 0); 1426 continue; 1427 } 1428 sitd = ohci_hash_find_itd(sc, done); 1429 if (sitd != NULL) { 1430 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1431 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1432 sitd->dnext = sidone; 1433 done = O32TOH(sitd->itd.itd_nextitd); 1434 sidone = sitd; 1435 DPRINTFN(5, "add ITD %#jx", (uintptr_t)sitd, 0, 0, 0); 1436 continue; 1437 } 1438 DPRINTFN(10, "addr %#jx not found", (uintptr_t)done, 0, 0, 0); 1439 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1440 (u_long)done); 1441 break; 1442 } 1443 1444 DPRINTFN(10, "sdone=%#jx sidone=%#jx", (uintptr_t)sdone, 1445 (uintptr_t)sidone, 0, 0); 1446 DPRINTFN(10, "--- TD dump start ---", 0, 0, 0, 0); 1447 #ifdef OHCI_DEBUG 1448 if (ohcidebug >= 10) { 1449 for (std = sdone; std; std = std->dnext) 1450 ohci_dump_td(sc, std); 1451 } 1452 #endif 1453 DPRINTFN(10, "--- TD dump end ---", 0, 0, 0, 0); 1454 1455 for (std = sdone; std; std = stdnext) { 1456 xfer = std->xfer; 1457 stdnext = std->dnext; 1458 DPRINTFN(10, "std=%#jx xfer=%#jx hcpriv=%#jx", (uintptr_t)std, 1459 (uintptr_t)xfer, (uintptr_t)(xfer ? xfer->ux_hcpriv : 0), 1460 0); 1461 if (xfer == NULL) { 1462 /* 1463 * xfer == NULL: There seems to be no xfer associated 1464 * with this TD. It is tailp that happened to end up on 1465 * the done queue. 1466 * Shouldn't happen, but some chips are broken(?). 1467 */ 1468 continue; 1469 } 1470 1471 /* 1472 * Try to claim this xfer for completion. If it has 1473 * already completed or aborted, drop it on the floor. 1474 */ 1475 if (!usbd_xfer_trycomplete(xfer)) 1476 continue; 1477 1478 len = std->len; 1479 if (std->td.td_cbp != 0) 1480 len -= O32TOH(std->td.td_be) - 1481 O32TOH(std->td.td_cbp) + 1; 1482 DPRINTFN(10, "len=%jd, flags=0x%jx", len, std->flags, 0, 0); 1483 if (std->flags & OHCI_ADD_LEN) 1484 xfer->ux_actlen += len; 1485 1486 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1487 if (cc == OHCI_CC_NO_ERROR) { 1488 ohci_hash_rem_td(sc, std); 1489 if (std->flags & OHCI_CALL_DONE) { 1490 xfer->ux_status = USBD_NORMAL_COMPLETION; 1491 usb_transfer_complete(xfer); 1492 } 1493 } else { 1494 /* 1495 * Endpoint is halted. First unlink all the TDs 1496 * belonging to the failed transfer, and then restart 1497 * the endpoint. 1498 */ 1499 ohci_soft_td_t *p, *n; 1500 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1501 1502 DPRINTFN(10, "error cc=%jd", cc, 0, 0, 0); 1503 1504 /* remove xfer's TDs from the hash */ 1505 for (p = std; p->xfer == xfer; p = n) { 1506 n = p->nexttd; 1507 ohci_hash_rem_td(sc, p); 1508 } 1509 1510 ohci_soft_ed_t *sed = opipe->sed; 1511 1512 /* clear halt and TD chain, preserving toggle carry */ 1513 sed->ed.ed_headp = HTOO32(p->physaddr | 1514 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 1515 usb_syncmem(&sed->dma, 1516 sed->offs + offsetof(ohci_ed_t, ed_headp), 1517 sizeof(sed->ed.ed_headp), 1518 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1519 1520 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1521 1522 if (cc == OHCI_CC_DATA_UNDERRUN) 1523 xfer->ux_status = USBD_NORMAL_COMPLETION; 1524 else if (cc == OHCI_CC_STALL) 1525 xfer->ux_status = USBD_STALLED; 1526 else 1527 xfer->ux_status = USBD_IOERROR; 1528 usb_transfer_complete(xfer); 1529 } 1530 } 1531 DPRINTFN(10, "--- ITD dump start ---", 0, 0, 0, 0); 1532 #ifdef OHCI_DEBUG 1533 if (ohcidebug >= 10) { 1534 for (sitd = sidone; sitd; sitd = sitd->dnext) 1535 ohci_dump_itd(sc, sitd); 1536 } 1537 #endif 1538 DPRINTFN(10, "--- ITD dump end ---", 0, 0, 0, 0); 1539 1540 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1541 xfer = sitd->xfer; 1542 sitdnext = sitd->dnext; 1543 DPRINTFN(1, "sitd=%#jx xfer=%#jx hcpriv=%#jx", (uintptr_t)sitd, 1544 (uintptr_t)xfer, (uintptr_t)(xfer ? xfer->ux_hcpriv : 0), 1545 0); 1546 if (xfer == NULL) 1547 continue; 1548 1549 /* 1550 * Try to claim this xfer for completion. If it has 1551 * already completed or aborted, drop it on the floor. 1552 */ 1553 if (!usbd_xfer_trycomplete(xfer)) 1554 continue; 1555 1556 KASSERT(!sitd->isdone); 1557 #ifdef DIAGNOSTIC 1558 sitd->isdone = true; 1559 #endif 1560 if (sitd->flags & OHCI_CALL_DONE) { 1561 ohci_soft_itd_t *next; 1562 1563 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1564 opipe->isoc.inuse -= xfer->ux_nframes; 1565 uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc-> 1566 bEndpointAddress); 1567 xfer->ux_status = USBD_NORMAL_COMPLETION; 1568 actlen = 0; 1569 for (i = 0, sitd = xfer->ux_hcpriv;; 1570 sitd = next) { 1571 next = sitd->nextitd; 1572 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1573 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1574 xfer->ux_status = USBD_IOERROR; 1575 /* For input, update frlengths with actual */ 1576 /* XXX anything necessary for output? */ 1577 if (uedir == UE_DIR_IN && 1578 xfer->ux_status == USBD_NORMAL_COMPLETION) { 1579 iframes = OHCI_ITD_GET_FC(O32TOH( 1580 sitd->itd.itd_flags)); 1581 for (j = 0; j < iframes; i++, j++) { 1582 len = O16TOH(sitd-> 1583 itd.itd_offset[j]); 1584 if ((OHCI_ITD_PSW_GET_CC(len) & 1585 OHCI_CC_NOT_ACCESSED_MASK) 1586 == OHCI_CC_NOT_ACCESSED) 1587 len = 0; 1588 else 1589 len = OHCI_ITD_PSW_LENGTH(len); 1590 xfer->ux_frlengths[i] = len; 1591 actlen += len; 1592 } 1593 } 1594 if (sitd->flags & OHCI_CALL_DONE) 1595 break; 1596 ohci_hash_rem_itd(sc, sitd); 1597 1598 } 1599 ohci_hash_rem_itd(sc, sitd); 1600 if (uedir == UE_DIR_IN && 1601 xfer->ux_status == USBD_NORMAL_COMPLETION) 1602 xfer->ux_actlen = actlen; 1603 xfer->ux_hcpriv = NULL; 1604 1605 usb_transfer_complete(xfer); 1606 } 1607 } 1608 1609 DPRINTFN(10, "done", 0, 0, 0, 0); 1610 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1611 } 1612 1613 void 1614 ohci_device_ctrl_done(struct usbd_xfer *xfer) 1615 { 1616 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1617 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1618 int len = UGETW(xfer->ux_request.wLength); 1619 int isread = (xfer->ux_request.bmRequestType & UT_READ); 1620 1621 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1622 DPRINTFN(10, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 1623 1624 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1625 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 1626 1627 if (len) 1628 usb_syncmem(&xfer->ux_dmabuf, 0, len, 1629 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1630 usb_syncmem(&opipe->ctrl.reqdma, 0, 1631 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1632 } 1633 1634 void 1635 ohci_device_intr_done(struct usbd_xfer *xfer) 1636 { 1637 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1638 int isread = 1639 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1640 1641 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1642 DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, 1643 xfer->ux_actlen, 0, 0); 1644 1645 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1646 1647 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1648 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1649 } 1650 1651 void 1652 ohci_device_bulk_done(struct usbd_xfer *xfer) 1653 { 1654 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1655 1656 int isread = 1657 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1658 1659 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1660 1661 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1662 DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 1663 0, 0); 1664 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1665 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1666 } 1667 1668 Static void 1669 ohci_rhsc_softint(void *arg) 1670 { 1671 ohci_softc_t *sc = arg; 1672 1673 mutex_enter(&sc->sc_lock); 1674 1675 ohci_rhsc(sc, sc->sc_intrxfer); 1676 1677 /* Do not allow RHSC interrupts > 1 per second */ 1678 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1679 1680 mutex_exit(&sc->sc_lock); 1681 } 1682 1683 void 1684 ohci_rhsc(ohci_softc_t *sc, struct usbd_xfer *xfer) 1685 { 1686 u_char *p; 1687 int i, m; 1688 int hstatus __unused; 1689 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1690 1691 KASSERT(mutex_owned(&sc->sc_lock)); 1692 1693 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1694 DPRINTF("sc=%#jx xfer=%#jx hstatus=0x%08jx", (uintptr_t)sc, 1695 (uintptr_t)xfer, hstatus, 0); 1696 1697 if (xfer == NULL) { 1698 /* Just ignore the change. */ 1699 return; 1700 } 1701 1702 p = xfer->ux_buf; 1703 m = uimin(sc->sc_noport, xfer->ux_length * 8 - 1); 1704 memset(p, 0, xfer->ux_length); 1705 for (i = 1; i <= m; i++) { 1706 /* Pick out CHANGE bits from the status reg. */ 1707 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1708 p[i/8] |= 1 << (i%8); 1709 } 1710 DPRINTF("change=0x%02jx", *p, 0, 0, 0); 1711 xfer->ux_actlen = xfer->ux_length; 1712 xfer->ux_status = USBD_NORMAL_COMPLETION; 1713 1714 usb_transfer_complete(xfer); 1715 } 1716 1717 void 1718 ohci_root_intr_done(struct usbd_xfer *xfer) 1719 { 1720 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1721 1722 KASSERT(mutex_owned(&sc->sc_lock)); 1723 1724 KASSERT(sc->sc_intrxfer == xfer); 1725 sc->sc_intrxfer = NULL; 1726 } 1727 1728 void 1729 ohci_poll(struct usbd_bus *bus) 1730 { 1731 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1732 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1733 1734 #ifdef OHCI_DEBUG 1735 static int last; 1736 int new; 1737 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1738 if (new != last) { 1739 DPRINTFN(10, "intrs=0x%04jx", new, 0, 0, 0); 1740 last = new; 1741 } 1742 #endif 1743 sc->sc_eintrs |= OHCI_WDH; 1744 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1745 mutex_spin_enter(&sc->sc_intr_lock); 1746 ohci_intr1(sc); 1747 mutex_spin_exit(&sc->sc_intr_lock); 1748 } 1749 } 1750 1751 /* 1752 * Add an ED to the schedule. Called with USB lock held. 1753 */ 1754 Static void 1755 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1756 { 1757 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1758 DPRINTFN(8, "sed=%#jx head=%#jx", (uintptr_t)sed, (uintptr_t)head, 0, 1759 0); 1760 1761 KASSERT(mutex_owned(&sc->sc_lock)); 1762 1763 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1764 sizeof(head->ed.ed_nexted), 1765 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1766 sed->next = head->next; 1767 sed->ed.ed_nexted = head->ed.ed_nexted; 1768 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1769 sizeof(sed->ed.ed_nexted), 1770 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1771 head->next = sed; 1772 head->ed.ed_nexted = HTOO32(sed->physaddr); 1773 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1774 sizeof(head->ed.ed_nexted), 1775 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1776 } 1777 1778 /* 1779 * Remove an ED from the schedule. Called with USB lock held. 1780 */ 1781 Static void 1782 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1783 { 1784 ohci_soft_ed_t *p; 1785 1786 KASSERT(mutex_owned(&sc->sc_lock)); 1787 1788 /* XXX */ 1789 for (p = head; p != NULL && p->next != sed; p = p->next) 1790 ; 1791 KASSERT(p != NULL); 1792 1793 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1794 sizeof(sed->ed.ed_nexted), 1795 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1796 p->next = sed->next; 1797 p->ed.ed_nexted = sed->ed.ed_nexted; 1798 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1799 sizeof(p->ed.ed_nexted), 1800 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1801 } 1802 1803 /* 1804 * When a transfer is completed the TD is added to the done queue by 1805 * the host controller. This queue is the processed by software. 1806 * Unfortunately the queue contains the physical address of the TD 1807 * and we have no simple way to translate this back to a kernel address. 1808 * To make the translation possible (and fast) we use a hash table of 1809 * TDs currently in the schedule. The physical address is used as the 1810 * hash value. 1811 */ 1812 1813 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1814 /* Called with USB lock held. */ 1815 void 1816 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1817 { 1818 int h = HASH(std->physaddr); 1819 1820 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1821 1822 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1823 } 1824 1825 /* Called with USB lock held. */ 1826 void 1827 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1828 { 1829 1830 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1831 1832 LIST_REMOVE(std, hnext); 1833 } 1834 1835 ohci_soft_td_t * 1836 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1837 { 1838 int h = HASH(a); 1839 ohci_soft_td_t *std; 1840 1841 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1842 std != NULL; 1843 std = LIST_NEXT(std, hnext)) 1844 if (std->physaddr == a) 1845 return std; 1846 return NULL; 1847 } 1848 1849 /* Called with USB lock held. */ 1850 void 1851 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1852 { 1853 int h = HASH(sitd->physaddr); 1854 1855 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1856 1857 KASSERT(mutex_owned(&sc->sc_lock)); 1858 1859 DPRINTFN(10, "sitd=%#jx physaddr=0x%08jx", 1860 (uintptr_t)sitd, (u_long)sitd->physaddr, 0, 0); 1861 1862 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1863 } 1864 1865 /* Called with USB lock held. */ 1866 void 1867 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1868 { 1869 1870 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1871 1872 KASSERT(mutex_owned(&sc->sc_lock)); 1873 1874 DPRINTFN(10, "sitd=%#jx physaddr=0x%08jx", (uintptr_t)sitd, 1875 sitd->physaddr, 0, 0); 1876 1877 LIST_REMOVE(sitd, hnext); 1878 } 1879 1880 ohci_soft_itd_t * 1881 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1882 { 1883 int h = HASH(a); 1884 ohci_soft_itd_t *sitd; 1885 1886 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1887 sitd != NULL; 1888 sitd = LIST_NEXT(sitd, hnext)) 1889 if (sitd->physaddr == a) 1890 return sitd; 1891 return NULL; 1892 } 1893 1894 #ifdef OHCI_DEBUG 1895 void 1896 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 1897 { 1898 for (; std; std = std->nexttd) { 1899 ohci_dump_td(sc, std); 1900 KASSERTMSG(std->nexttd == NULL || std != std->nexttd, 1901 "std %p next %p", std, std->nexttd); 1902 } 1903 } 1904 1905 void 1906 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1907 { 1908 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1909 1910 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1911 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1912 1913 uint32_t flags = O32TOH(std->td.td_flags); 1914 DPRINTF("TD(%#jx) at 0x%08jx:", (uintptr_t)std, std->physaddr, 0, 0); 1915 DPRINTF(" round=%jd DP=%jx DI=%jx T=%jx", 1916 !!(flags & OHCI_TD_R), 1917 __SHIFTOUT(flags, OHCI_TD_DP_MASK), 1918 OHCI_TD_GET_DI(flags), 1919 __SHIFTOUT(flags, OHCI_TD_TOGGLE_MASK)); 1920 DPRINTF(" EC=%jd CC=%jd", OHCI_TD_GET_EC(flags), 1921 OHCI_TD_GET_CC(flags), 0, 0); 1922 DPRINTF(" td_cbp=0x%08jx td_nexttd=0x%08jx td_be=0x%08jx", 1923 (u_long)O32TOH(std->td.td_cbp), 1924 (u_long)O32TOH(std->td.td_nexttd), 1925 (u_long)O32TOH(std->td.td_be), 0); 1926 } 1927 1928 void 1929 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1930 { 1931 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1932 1933 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1934 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1935 1936 uint32_t flags = O32TOH(sitd->itd.itd_flags); 1937 DPRINTF("ITD(%#jx) at 0x%08jx", (uintptr_t)sitd, sitd->physaddr, 0, 0); 1938 DPRINTF(" sf=%jd di=%jd fc=%jd cc=%jd", 1939 OHCI_ITD_GET_SF(flags), OHCI_ITD_GET_DI(flags), 1940 OHCI_ITD_GET_FC(flags), OHCI_ITD_GET_CC(flags)); 1941 DPRINTF(" bp0=0x%08jx next=0x%08jx be=0x%08jx", 1942 O32TOH(sitd->itd.itd_bp0), 1943 O32TOH(sitd->itd.itd_nextitd), 1944 O32TOH(sitd->itd.itd_be), 0); 1945 CTASSERT(OHCI_ITD_NOFFSET == 8); 1946 DPRINTF(" offs[0] = 0x%04jx offs[1] = 0x%04jx " 1947 "offs[2] = 0x%04jx offs[3] = 0x%04jx", 1948 O16TOH(sitd->itd.itd_offset[0]), 1949 O16TOH(sitd->itd.itd_offset[1]), 1950 O16TOH(sitd->itd.itd_offset[2]), 1951 O16TOH(sitd->itd.itd_offset[3])); 1952 DPRINTF(" offs[4] = 0x%04jx offs[5] = 0x%04jx " 1953 "offs[6] = 0x%04jx offs[7] = 0x%04jx", 1954 O16TOH(sitd->itd.itd_offset[4]), 1955 O16TOH(sitd->itd.itd_offset[5]), 1956 O16TOH(sitd->itd.itd_offset[6]), 1957 O16TOH(sitd->itd.itd_offset[7])); 1958 } 1959 1960 void 1961 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1962 { 1963 for (; sitd; sitd = sitd->nextitd) 1964 ohci_dump_itd(sc, sitd); 1965 } 1966 1967 void 1968 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 1969 { 1970 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1971 1972 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 1973 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1974 1975 uint32_t flags = O32TOH(sed->ed.ed_flags); 1976 DPRINTF("ED(%#jx) at 0x%08jx:", (uintptr_t)sed, sed->physaddr, 0, 0); 1977 DPRINTF(" addr=%jd endpt=%jd maxp=%jd", 1978 OHCI_ED_GET_FA(flags), 1979 OHCI_ED_GET_EN(flags), 1980 OHCI_ED_GET_MAXP(flags), 1981 0); 1982 DPRINTF(" dir=%jd speed=%jd skip=%jd iso=%jd", 1983 __SHIFTOUT(flags, OHCI_ED_DIR_MASK), 1984 !!(flags & OHCI_ED_SPEED), 1985 !!(flags & OHCI_ED_SKIP), 1986 !!(flags & OHCI_ED_FORMAT_ISO)); 1987 DPRINTF(" tailp=0x%08jx", (u_long)O32TOH(sed->ed.ed_tailp), 1988 0, 0, 0); 1989 DPRINTF(" headp=0x%08jx nexted=0x%08jx halted=%jd carry=%jd", 1990 O32TOH(sed->ed.ed_headp), O32TOH(sed->ed.ed_nexted), 1991 !!(O32TOH(sed->ed.ed_headp) & OHCI_HALTED), 1992 !!(O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 1993 } 1994 #endif 1995 1996 usbd_status 1997 ohci_open(struct usbd_pipe *pipe) 1998 { 1999 struct usbd_device *dev = pipe->up_dev; 2000 struct usbd_bus *bus = dev->ud_bus; 2001 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2002 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 2003 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2004 uint8_t addr = dev->ud_addr; 2005 uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2006 ohci_soft_ed_t *sed; 2007 ohci_soft_td_t *std; 2008 ohci_soft_itd_t *sitd; 2009 ohci_physaddr_t tdphys; 2010 uint32_t fmt; 2011 usbd_status err = USBD_NOMEM; 2012 int ival; 2013 2014 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2015 DPRINTFN(1, "pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, 2016 addr, ed->bEndpointAddress, bus->ub_rhaddr); 2017 2018 if (sc->sc_dying) { 2019 return USBD_IOERROR; 2020 } 2021 2022 std = NULL; 2023 sed = NULL; 2024 2025 if (addr == bus->ub_rhaddr) { 2026 switch (ed->bEndpointAddress) { 2027 case USB_CONTROL_ENDPOINT: 2028 pipe->up_methods = &roothub_ctrl_methods; 2029 break; 2030 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 2031 pipe->up_methods = &ohci_root_intr_methods; 2032 break; 2033 default: 2034 err = USBD_INVAL; 2035 goto bad; 2036 } 2037 } else { 2038 sed = ohci_alloc_sed(sc); 2039 if (sed == NULL) 2040 goto bad; 2041 opipe->sed = sed; 2042 if (xfertype == UE_ISOCHRONOUS) { 2043 sitd = ohci_alloc_sitd(sc); 2044 if (sitd == NULL) 2045 goto bad; 2046 2047 opipe->tail.itd = sitd; 2048 tdphys = sitd->physaddr; 2049 fmt = OHCI_ED_FORMAT_ISO; 2050 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2051 fmt |= OHCI_ED_DIR_IN; 2052 else 2053 fmt |= OHCI_ED_DIR_OUT; 2054 } else { 2055 std = ohci_alloc_std(sc); 2056 if (std == NULL) 2057 goto bad; 2058 2059 opipe->tail.td = std; 2060 tdphys = std->physaddr; 2061 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2062 } 2063 sed->ed.ed_flags = HTOO32( 2064 OHCI_ED_SET_FA(addr) | 2065 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2066 (dev->ud_speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2067 fmt | 2068 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2069 sed->ed.ed_headp = HTOO32(tdphys | 2070 (pipe->up_endpoint->ue_toggle ? OHCI_TOGGLECARRY : 0)); 2071 sed->ed.ed_tailp = HTOO32(tdphys); 2072 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2073 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2074 2075 switch (xfertype) { 2076 case UE_CONTROL: 2077 pipe->up_methods = &ohci_device_ctrl_methods; 2078 err = usb_allocmem(&sc->sc_bus, 2079 sizeof(usb_device_request_t), 2080 0, &opipe->ctrl.reqdma); 2081 if (err) 2082 goto bad; 2083 mutex_enter(&sc->sc_lock); 2084 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2085 mutex_exit(&sc->sc_lock); 2086 break; 2087 case UE_INTERRUPT: 2088 pipe->up_methods = &ohci_device_intr_methods; 2089 ival = pipe->up_interval; 2090 if (ival == USBD_DEFAULT_INTERVAL) 2091 ival = ed->bInterval; 2092 err = ohci_device_setintr(sc, opipe, ival); 2093 if (err) 2094 goto bad; 2095 break; 2096 case UE_ISOCHRONOUS: 2097 pipe->up_serialise = false; 2098 pipe->up_methods = &ohci_device_isoc_methods; 2099 return ohci_setup_isoc(pipe); 2100 case UE_BULK: 2101 pipe->up_methods = &ohci_device_bulk_methods; 2102 mutex_enter(&sc->sc_lock); 2103 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2104 mutex_exit(&sc->sc_lock); 2105 break; 2106 } 2107 } 2108 2109 return USBD_NORMAL_COMPLETION; 2110 2111 bad: 2112 if (std != NULL) { 2113 ohci_free_std(sc, std); 2114 } 2115 if (sed != NULL) 2116 ohci_free_sed(sc, sed); 2117 return err; 2118 2119 } 2120 2121 /* 2122 * Close a reqular pipe. 2123 * Assumes that there are no pending transactions. 2124 */ 2125 void 2126 ohci_close_pipe(struct usbd_pipe *pipe, ohci_soft_ed_t *head) 2127 { 2128 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2129 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2130 ohci_soft_ed_t *sed = opipe->sed; 2131 2132 KASSERT(mutex_owned(&sc->sc_lock)); 2133 2134 #ifdef DIAGNOSTIC 2135 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2136 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2137 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2138 ohci_soft_td_t *std; 2139 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2140 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2141 "tl=0x%x pipe=%p, std=%p\n", sed, 2142 (int)O32TOH(sed->ed.ed_headp), 2143 (int)O32TOH(sed->ed.ed_tailp), 2144 pipe, std); 2145 #ifdef OHCI_DEBUG 2146 usbd_dump_pipe(&opipe->pipe); 2147 ohci_dump_ed(sc, sed); 2148 if (std) 2149 ohci_dump_td(sc, std); 2150 #endif 2151 usb_delay_ms(&sc->sc_bus, 2); 2152 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2153 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2154 printf("ohci_close_pipe: pipe still not empty\n"); 2155 } 2156 #endif 2157 ohci_rem_ed(sc, sed, head); 2158 /* Make sure the host controller is not touching this ED */ 2159 usb_delay_ms(&sc->sc_bus, 1); 2160 pipe->up_endpoint->ue_toggle = 2161 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2162 ohci_free_sed_locked(sc, opipe->sed); 2163 } 2164 2165 /* 2166 * Arrange for the hardware to tells us that it is not still processing 2167 * the TDs by setting the sKip bit and requesting a SOF interrupt 2168 * 2169 * Once we see the SOF interrupt we can check the transfer TDs/iTDs to see if 2170 * they've been processed and either 2171 * a) if they're unused recover them for later use, or 2172 * b) if they've been used allocate new TD/iTDs to replace those 2173 * used. The softint handler will free the old ones. 2174 */ 2175 void 2176 ohci_abortx(struct usbd_xfer *xfer) 2177 { 2178 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2179 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2180 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2181 ohci_soft_ed_t *sed = opipe->sed; 2182 ohci_soft_td_t *p, *n; 2183 ohci_physaddr_t headp; 2184 int hit; 2185 2186 DPRINTF("xfer=%#jx pipe=%#jx sed=%#jx", (uintptr_t)xfer, 2187 (uintptr_t)opipe, (uintptr_t)sed, 0); 2188 2189 KASSERT(mutex_owned(&sc->sc_lock)); 2190 ASSERT_SLEEPABLE(); 2191 2192 KASSERTMSG((xfer->ux_status == USBD_CANCELLED || 2193 xfer->ux_status == USBD_TIMEOUT), 2194 "bad abort status: %d", xfer->ux_status); 2195 2196 /* 2197 * If we're dying, skip the hardware action and just notify the 2198 * software that we're done. 2199 */ 2200 if (sc->sc_dying) { 2201 DPRINTFN(4, "xfer %#jx dying %ju", (uintptr_t)xfer, 2202 xfer->ux_status, 0, 0); 2203 goto dying; 2204 } 2205 2206 /* 2207 * HC Step 1: Unless the endpoint is already halted, we set the endpoint 2208 * descriptor sKip bit and wait for hardware to complete processing. 2209 * 2210 * This includes ensuring that any TDs of the transfer that got onto 2211 * the done list are also removed. We ensure this by waiting for 2212 * both a WDH and SOF interrupt. 2213 */ 2214 DPRINTFN(1, "stop ed=%#jx", (uintptr_t)sed, 0, 0, 0); 2215 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2216 sizeof(sed->ed.ed_flags), 2217 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2218 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2219 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2220 sizeof(sed->ed.ed_flags), 2221 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2222 2223 /* 2224 * HC Step 2: Wait until we know hardware has finished any possible 2225 * use of the xfer. 2226 */ 2227 /* Hardware finishes in 1ms */ 2228 usb_delay_ms_locked(opipe->pipe.up_dev->ud_bus, 20, &sc->sc_lock); 2229 2230 /* 2231 * HC Step 3: Remove any vestiges of the xfer from the hardware. 2232 * The complication here is that the hardware may have executed 2233 * beyond the xfer we're trying to abort. So as we're scanning 2234 * the TDs of this xfer we check if the hardware points to 2235 * any of them. 2236 */ 2237 p = xfer->ux_hcpriv; 2238 KASSERT(p); 2239 2240 #ifdef OHCI_DEBUG 2241 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2242 2243 if (ohcidebug >= 2) { 2244 DPRINTF("sed:", 0, 0, 0, 0); 2245 ohci_dump_ed(sc, sed); 2246 ohci_dump_tds(sc, p); 2247 } 2248 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2249 #endif 2250 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2251 hit = 0; 2252 for (; p->xfer == xfer; p = n) { 2253 hit |= headp == p->physaddr; 2254 n = p->nexttd; 2255 ohci_hash_rem_td(sc, p); 2256 } 2257 /* Zap headp register if hardware pointed inside the xfer. */ 2258 if (hit) { 2259 DPRINTFN(1, "set hd=0x%08jx, tl=0x%08jx", (int)p->physaddr, 2260 (int)O32TOH(sed->ed.ed_tailp), 0, 0); 2261 /* unlink TDs, preserving toggle carry */ 2262 sed->ed.ed_headp = HTOO32(p->physaddr | 2263 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 2264 usb_syncmem(&sed->dma, 2265 sed->offs + offsetof(ohci_ed_t, ed_headp), 2266 sizeof(sed->ed.ed_headp), 2267 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2268 } else { 2269 DPRINTFN(1, "no hit", 0, 0, 0, 0); 2270 } 2271 2272 /* 2273 * HC Step 4: Turn on hardware again. 2274 */ 2275 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2276 sizeof(sed->ed.ed_flags), 2277 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2278 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2279 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2280 sizeof(sed->ed.ed_flags), 2281 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2282 2283 /* 2284 * Final step: Notify completion to waiting xfers. 2285 */ 2286 dying: 2287 usb_transfer_complete(xfer); 2288 DPRINTFN(14, "end", 0, 0, 0, 0); 2289 2290 KASSERT(mutex_owned(&sc->sc_lock)); 2291 } 2292 2293 /* 2294 * Data structures and routines to emulate the root hub. 2295 */ 2296 Static int 2297 ohci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2298 void *buf, int buflen) 2299 { 2300 ohci_softc_t *sc = OHCI_BUS2SC(bus); 2301 usb_port_status_t ps; 2302 uint16_t len, value, index; 2303 int l, totlen = 0; 2304 int port, i; 2305 uint32_t v; 2306 2307 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2308 2309 if (sc->sc_dying) 2310 return -1; 2311 2312 DPRINTFN(4, "type=0x%02jx request=%02jx", req->bmRequestType, 2313 req->bRequest, 0, 0); 2314 2315 len = UGETW(req->wLength); 2316 value = UGETW(req->wValue); 2317 index = UGETW(req->wIndex); 2318 2319 #define C(x,y) ((x) | ((y) << 8)) 2320 switch (C(req->bRequest, req->bmRequestType)) { 2321 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2322 DPRINTFN(8, "wValue=0x%04jx", value, 0, 0, 0); 2323 if (len == 0) 2324 break; 2325 switch (value) { 2326 #define sd ((usb_string_descriptor_t *)buf) 2327 case C(2, UDESC_STRING): 2328 /* Product */ 2329 totlen = usb_makestrdesc(sd, len, "OHCI root hub"); 2330 break; 2331 #undef sd 2332 default: 2333 /* default from usbroothub */ 2334 return buflen; 2335 } 2336 break; 2337 2338 /* Hub requests */ 2339 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2340 break; 2341 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2342 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", 2343 index, value, 0, 0); 2344 if (index < 1 || index > sc->sc_noport) { 2345 return -1; 2346 } 2347 port = OHCI_RH_PORT_STATUS(index); 2348 switch(value) { 2349 case UHF_PORT_ENABLE: 2350 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2351 break; 2352 case UHF_PORT_SUSPEND: 2353 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2354 break; 2355 case UHF_PORT_POWER: 2356 /* Yes, writing to the LOW_SPEED bit clears power. */ 2357 OWRITE4(sc, port, UPS_LOW_SPEED); 2358 break; 2359 case UHF_C_PORT_CONNECTION: 2360 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2361 break; 2362 case UHF_C_PORT_ENABLE: 2363 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2364 break; 2365 case UHF_C_PORT_SUSPEND: 2366 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2367 break; 2368 case UHF_C_PORT_OVER_CURRENT: 2369 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2370 break; 2371 case UHF_C_PORT_RESET: 2372 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2373 break; 2374 default: 2375 return -1; 2376 } 2377 switch(value) { 2378 case UHF_C_PORT_CONNECTION: 2379 case UHF_C_PORT_ENABLE: 2380 case UHF_C_PORT_SUSPEND: 2381 case UHF_C_PORT_OVER_CURRENT: 2382 case UHF_C_PORT_RESET: 2383 /* Enable RHSC interrupt if condition is cleared. */ 2384 if ((OREAD4(sc, port) >> 16) == 0) 2385 ohci_rhsc_enable(sc); 2386 break; 2387 default: 2388 break; 2389 } 2390 break; 2391 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2392 if (len == 0) 2393 break; 2394 if ((value & 0xff) != 0) { 2395 return -1; 2396 } 2397 usb_hub_descriptor_t hubd; 2398 2399 totlen = uimin(buflen, sizeof(hubd)); 2400 memcpy(&hubd, buf, totlen); 2401 2402 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2403 hubd.bNbrPorts = sc->sc_noport; 2404 USETW(hubd.wHubCharacteristics, 2405 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2406 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2407 /* XXX overcurrent */ 2408 ); 2409 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2410 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2411 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2412 hubd.DeviceRemovable[i++] = (uint8_t)v; 2413 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2414 totlen = uimin(totlen, hubd.bDescLength); 2415 memcpy(buf, &hubd, totlen); 2416 break; 2417 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2418 if (len != 4) { 2419 return -1; 2420 } 2421 memset(buf, 0, len); /* ? XXX */ 2422 totlen = len; 2423 break; 2424 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2425 DPRINTFN(8, "get port status i=%jd", index, 0, 0, 0); 2426 if (index < 1 || index > sc->sc_noport) { 2427 return -1; 2428 } 2429 if (len != 4) { 2430 return -1; 2431 } 2432 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2433 DPRINTFN(8, "port status=0x%04jx", v, 0, 0, 0); 2434 USETW(ps.wPortStatus, v); 2435 USETW(ps.wPortChange, v >> 16); 2436 totlen = uimin(len, sizeof(ps)); 2437 memcpy(buf, &ps, totlen); 2438 break; 2439 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2440 return -1; 2441 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2442 break; 2443 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2444 if (index < 1 || index > sc->sc_noport) { 2445 return -1; 2446 } 2447 port = OHCI_RH_PORT_STATUS(index); 2448 switch(value) { 2449 case UHF_PORT_ENABLE: 2450 OWRITE4(sc, port, UPS_PORT_ENABLED); 2451 break; 2452 case UHF_PORT_SUSPEND: 2453 OWRITE4(sc, port, UPS_SUSPEND); 2454 break; 2455 case UHF_PORT_RESET: 2456 DPRINTFN(5, "reset port %jd", index, 0, 0, 0); 2457 OWRITE4(sc, port, UPS_RESET); 2458 for (i = 0; i < 5; i++) { 2459 usb_delay_ms(&sc->sc_bus, 2460 USB_PORT_ROOT_RESET_DELAY); 2461 if (sc->sc_dying) { 2462 return -1; 2463 } 2464 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2465 break; 2466 } 2467 DPRINTFN(8, "port %jd reset, status = 0x%04jx", index, 2468 OREAD4(sc, port), 0, 0); 2469 break; 2470 case UHF_PORT_POWER: 2471 DPRINTFN(2, "set port power %jd", index, 0, 0, 0); 2472 OWRITE4(sc, port, UPS_PORT_POWER); 2473 break; 2474 default: 2475 return -1; 2476 } 2477 break; 2478 default: 2479 /* default from usbroothub */ 2480 return buflen; 2481 } 2482 2483 return totlen; 2484 } 2485 2486 Static usbd_status 2487 ohci_root_intr_transfer(struct usbd_xfer *xfer) 2488 { 2489 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2490 usbd_status err; 2491 2492 /* Insert last in queue. */ 2493 mutex_enter(&sc->sc_lock); 2494 err = usb_insert_transfer(xfer); 2495 mutex_exit(&sc->sc_lock); 2496 if (err) 2497 return err; 2498 2499 /* Pipe isn't running, start first */ 2500 return ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2501 } 2502 2503 Static usbd_status 2504 ohci_root_intr_start(struct usbd_xfer *xfer) 2505 { 2506 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2507 const bool polling = sc->sc_bus.ub_usepolling; 2508 2509 if (sc->sc_dying) 2510 return USBD_IOERROR; 2511 2512 if (!polling) 2513 mutex_enter(&sc->sc_lock); 2514 KASSERT(sc->sc_intrxfer == NULL); 2515 sc->sc_intrxfer = xfer; 2516 if (!polling) 2517 mutex_exit(&sc->sc_lock); 2518 2519 return USBD_IN_PROGRESS; 2520 } 2521 2522 /* Abort a root interrupt request. */ 2523 Static void 2524 ohci_root_intr_abort(struct usbd_xfer *xfer) 2525 { 2526 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 2527 2528 KASSERT(mutex_owned(&sc->sc_lock)); 2529 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2530 2531 xfer->ux_status = USBD_CANCELLED; 2532 usb_transfer_complete(xfer); 2533 } 2534 2535 /* Close the root pipe. */ 2536 Static void 2537 ohci_root_intr_close(struct usbd_pipe *pipe) 2538 { 2539 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2540 2541 KASSERT(mutex_owned(&sc->sc_lock)); 2542 2543 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2544 2545 sc->sc_intrxfer = NULL; 2546 } 2547 2548 /************************/ 2549 2550 int 2551 ohci_device_ctrl_init(struct usbd_xfer *xfer) 2552 { 2553 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2554 usb_device_request_t *req = &xfer->ux_request; 2555 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2556 ohci_soft_td_t *stat, *setup; 2557 int isread = req->bmRequestType & UT_READ; 2558 int len = xfer->ux_bufsize; 2559 int err = ENOMEM; 2560 2561 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2562 2563 setup = ohci_alloc_std(sc); 2564 if (setup == NULL) { 2565 goto bad1; 2566 } 2567 stat = ohci_alloc_std(sc); 2568 if (stat == NULL) { 2569 goto bad2; 2570 } 2571 2572 ox->ox_setup = setup; 2573 ox->ox_stat = stat; 2574 ox->ox_nstd = 0; 2575 2576 /* Set up data transaction */ 2577 if (len != 0) { 2578 err = ohci_alloc_std_chain(sc, xfer, len, isread); 2579 if (err) { 2580 goto bad3; 2581 } 2582 } 2583 return 0; 2584 2585 bad3: 2586 ohci_free_std(sc, stat); 2587 bad2: 2588 ohci_free_std(sc, setup); 2589 bad1: 2590 return err; 2591 } 2592 2593 void 2594 ohci_device_ctrl_fini(struct usbd_xfer *xfer) 2595 { 2596 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2597 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2598 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2599 2600 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2601 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 2602 2603 mutex_enter(&sc->sc_lock); 2604 if (ox->ox_setup != opipe->tail.td) { 2605 ohci_free_std_locked(sc, ox->ox_setup); 2606 } 2607 for (size_t i = 0; i < ox->ox_nstd; i++) { 2608 ohci_soft_td_t *std = ox->ox_stds[i]; 2609 if (std == NULL) 2610 break; 2611 ohci_free_std_locked(sc, std); 2612 } 2613 ohci_free_std_locked(sc, ox->ox_stat); 2614 mutex_exit(&sc->sc_lock); 2615 2616 if (ox->ox_nstd) { 2617 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 2618 kmem_free(ox->ox_stds, sz); 2619 } 2620 } 2621 2622 Static usbd_status 2623 ohci_device_ctrl_transfer(struct usbd_xfer *xfer) 2624 { 2625 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2626 usbd_status err; 2627 2628 /* Insert last in queue. */ 2629 mutex_enter(&sc->sc_lock); 2630 err = usb_insert_transfer(xfer); 2631 mutex_exit(&sc->sc_lock); 2632 if (err) 2633 return err; 2634 2635 /* Pipe isn't running, start first */ 2636 return ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2637 } 2638 2639 Static usbd_status 2640 ohci_device_ctrl_start(struct usbd_xfer *xfer) 2641 { 2642 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2643 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2644 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2645 usb_device_request_t *req = &xfer->ux_request; 2646 struct usbd_device *dev __diagused = opipe->pipe.up_dev; 2647 ohci_soft_td_t *setup, *stat, *next, *tail; 2648 ohci_soft_ed_t *sed; 2649 int isread; 2650 int len; 2651 const bool polling = sc->sc_bus.ub_usepolling; 2652 2653 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2654 2655 if (sc->sc_dying) 2656 return USBD_IOERROR; 2657 2658 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2659 2660 isread = req->bmRequestType & UT_READ; 2661 len = UGETW(req->wLength); 2662 2663 DPRINTF("xfer=%#jx len=%jd, addr=%jd, endpt=%jd", (uintptr_t)xfer, len, 2664 dev->ud_addr, opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress); 2665 DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx", 2666 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2667 UGETW(req->wIndex)); 2668 2669 /* Need to take lock here for pipe->tail.td */ 2670 if (!polling) 2671 mutex_enter(&sc->sc_lock); 2672 2673 /* 2674 * Use the pipe "tail" TD as our first and loan our first TD to the 2675 * next transfer 2676 */ 2677 setup = opipe->tail.td; 2678 opipe->tail.td = ox->ox_setup; 2679 ox->ox_setup = setup; 2680 2681 stat = ox->ox_stat; 2682 2683 /* point at sentinel */ 2684 tail = opipe->tail.td; 2685 sed = opipe->sed; 2686 2687 KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->ud_addr, 2688 "address ED %d pipe %d\n", 2689 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->ud_addr); 2690 KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) == 2691 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 2692 "MPL ED %d pipe %d\n", 2693 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), 2694 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 2695 2696 /* next will point to data if len != 0 */ 2697 next = stat; 2698 2699 /* Set up data transaction */ 2700 if (len != 0) { 2701 ohci_soft_td_t *std; 2702 ohci_soft_td_t *end; 2703 2704 next = ox->ox_stds[0]; 2705 ohci_reset_std_chain(sc, xfer, len, isread, next, &end); 2706 2707 end->td.td_nexttd = HTOO32(stat->physaddr); 2708 end->nexttd = stat; 2709 2710 usb_syncmem(&end->dma, end->offs, sizeof(end->td), 2711 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2712 2713 usb_syncmem(&xfer->ux_dmabuf, 0, len, 2714 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2715 std = ox->ox_stds[0]; 2716 /* Start toggle at 1 and then use the carried toggle. */ 2717 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 2718 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 2719 usb_syncmem(&std->dma, 2720 std->offs + offsetof(ohci_td_t, td_flags), 2721 sizeof(std->td.td_flags), 2722 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2723 } 2724 2725 DPRINTFN(8, "setup %#jx data %#jx stat %#jx tail %#jx", 2726 (uintptr_t)setup, 2727 (uintptr_t)(len != 0 ? ox->ox_stds[0] : NULL), (uintptr_t)stat, 2728 (uintptr_t)tail); 2729 KASSERT(opipe->tail.td == tail); 2730 2731 memcpy(KERNADDR(&opipe->ctrl.reqdma, 0), req, sizeof(*req)); 2732 usb_syncmem(&opipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2733 2734 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 2735 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 2736 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->ctrl.reqdma, 0)); 2737 setup->td.td_nexttd = HTOO32(next->physaddr); 2738 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof(*req) - 1); 2739 setup->nexttd = next; 2740 setup->len = 0; 2741 setup->xfer = xfer; 2742 setup->flags = 0; 2743 ohci_hash_add_td(sc, setup); 2744 2745 xfer->ux_hcpriv = setup; 2746 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2747 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2748 2749 stat->td.td_flags = HTOO32( 2750 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 2751 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 2752 stat->td.td_cbp = 0; 2753 stat->td.td_nexttd = HTOO32(tail->physaddr); 2754 stat->td.td_be = 0; 2755 stat->nexttd = tail; 2756 stat->flags = OHCI_CALL_DONE; 2757 stat->len = 0; 2758 stat->xfer = xfer; 2759 ohci_hash_add_td(sc, stat); 2760 2761 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2762 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2763 2764 memset(&tail->td, 0, sizeof(tail->td)); 2765 tail->nexttd = NULL; 2766 tail->xfer = NULL; 2767 2768 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 2769 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2770 2771 #ifdef OHCI_DEBUG 2772 USBHIST_LOGN(ohcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2773 if (ohcidebug >= 5) { 2774 ohci_dump_ed(sc, sed); 2775 ohci_dump_tds(sc, setup); 2776 } 2777 USBHIST_LOGN(ohcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2778 #endif 2779 2780 /* Insert ED in schedule */ 2781 sed->ed.ed_tailp = HTOO32(tail->physaddr); 2782 usb_syncmem(&sed->dma, 2783 sed->offs + offsetof(ohci_ed_t, ed_tailp), 2784 sizeof(sed->ed.ed_tailp), 2785 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2786 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2787 usbd_xfer_schedule_timeout(xfer); 2788 2789 DPRINTF("done", 0, 0, 0, 0); 2790 2791 xfer->ux_status = USBD_IN_PROGRESS; 2792 if (!polling) 2793 mutex_exit(&sc->sc_lock); 2794 2795 return USBD_IN_PROGRESS; 2796 } 2797 2798 /* Abort a device control request. */ 2799 Static void 2800 ohci_device_ctrl_abort(struct usbd_xfer *xfer) 2801 { 2802 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 2803 2804 KASSERT(mutex_owned(&sc->sc_lock)); 2805 2806 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2807 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 2808 usbd_xfer_abort(xfer); 2809 } 2810 2811 /* Close a device control pipe. */ 2812 Static void 2813 ohci_device_ctrl_close(struct usbd_pipe *pipe) 2814 { 2815 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2816 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2817 2818 KASSERT(mutex_owned(&sc->sc_lock)); 2819 2820 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2821 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 2822 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2823 ohci_free_std_locked(sc, opipe->tail.td); 2824 } 2825 2826 /************************/ 2827 2828 Static void 2829 ohci_device_clear_toggle(struct usbd_pipe *pipe) 2830 { 2831 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2832 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2833 2834 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2835 } 2836 2837 Static void 2838 ohci_noop(struct usbd_pipe *pipe) 2839 { 2840 } 2841 2842 Static int 2843 ohci_device_bulk_init(struct usbd_xfer *xfer) 2844 { 2845 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2846 int len = xfer->ux_bufsize; 2847 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2848 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2849 int err; 2850 2851 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2852 2853 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2854 2855 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 2856 len, isread, xfer->ux_flags); 2857 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 2858 2859 /* Allocate a chain of new TDs (including a new tail). */ 2860 err = ohci_alloc_std_chain(sc, xfer, len, isread); 2861 if (err) 2862 return err; 2863 2864 return 0; 2865 } 2866 2867 Static void 2868 ohci_device_bulk_fini(struct usbd_xfer *xfer) 2869 { 2870 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2871 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2872 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2873 2874 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2875 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 2876 2877 mutex_enter(&sc->sc_lock); 2878 for (size_t i = 0; i < ox->ox_nstd; i++) { 2879 ohci_soft_td_t *std = ox->ox_stds[i]; 2880 if (std == NULL) 2881 break; 2882 if (std != opipe->tail.td) 2883 ohci_free_std_locked(sc, std); 2884 } 2885 mutex_exit(&sc->sc_lock); 2886 2887 if (ox->ox_nstd) { 2888 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 2889 kmem_free(ox->ox_stds, sz); 2890 } 2891 } 2892 2893 Static usbd_status 2894 ohci_device_bulk_transfer(struct usbd_xfer *xfer) 2895 { 2896 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2897 usbd_status err; 2898 2899 /* Insert last in queue. */ 2900 mutex_enter(&sc->sc_lock); 2901 err = usb_insert_transfer(xfer); 2902 mutex_exit(&sc->sc_lock); 2903 if (err) 2904 return err; 2905 2906 /* Pipe isn't running, start first */ 2907 return ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2908 } 2909 2910 Static usbd_status 2911 ohci_device_bulk_start(struct usbd_xfer *xfer) 2912 { 2913 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2914 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2915 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2916 ohci_soft_td_t *last; 2917 ohci_soft_td_t *data, *tail, *tdp; 2918 ohci_soft_ed_t *sed; 2919 int len, isread, endpt; 2920 const bool polling = sc->sc_bus.ub_usepolling; 2921 2922 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2923 2924 if (sc->sc_dying) 2925 return USBD_IOERROR; 2926 2927 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2928 2929 len = xfer->ux_length; 2930 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2931 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2932 sed = opipe->sed; 2933 2934 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 2935 len, isread, xfer->ux_flags); 2936 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 2937 2938 if (!polling) 2939 mutex_enter(&sc->sc_lock); 2940 2941 /* 2942 * Use the pipe "tail" TD as our first and loan our first TD to the 2943 * next transfer 2944 */ 2945 data = opipe->tail.td; 2946 opipe->tail.td = ox->ox_stds[0]; 2947 ox->ox_stds[0] = data; 2948 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 2949 2950 /* point at sentinel */ 2951 tail = opipe->tail.td; 2952 memset(&tail->td, 0, sizeof(tail->td)); 2953 tail->nexttd = NULL; 2954 tail->xfer = NULL; 2955 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 2956 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2957 xfer->ux_hcpriv = data; 2958 2959 DPRINTFN(8, "xfer %#jx data %#jx tail %#jx", (uintptr_t)xfer, 2960 (uintptr_t)ox->ox_stds[0], (uintptr_t)tail, 0); 2961 KASSERT(opipe->tail.td == tail); 2962 2963 /* We want interrupt at the end of the transfer. */ 2964 last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 2965 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 2966 last->td.td_nexttd = HTOO32(tail->physaddr); 2967 last->nexttd = tail; 2968 last->flags |= OHCI_CALL_DONE; 2969 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 2970 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2971 2972 DPRINTFN(4, "ed_flags=0x%08jx td_flags=0x%08jx " 2973 "td_cbp=0x%08jx td_be=0x%08jx", 2974 (int)O32TOH(sed->ed.ed_flags), 2975 (int)O32TOH(data->td.td_flags), 2976 (int)O32TOH(data->td.td_cbp), 2977 (int)O32TOH(data->td.td_be)); 2978 2979 #ifdef OHCI_DEBUG 2980 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2981 if (ohcidebug >= 5) { 2982 ohci_dump_ed(sc, sed); 2983 ohci_dump_tds(sc, data); 2984 } 2985 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2986 #endif 2987 2988 /* Insert ED in schedule */ 2989 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 2990 KASSERT(tdp->xfer == xfer); 2991 } 2992 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2993 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2994 sed->ed.ed_tailp = HTOO32(tail->physaddr); 2995 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 2996 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2997 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2998 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 2999 usbd_xfer_schedule_timeout(xfer); 3000 xfer->ux_status = USBD_IN_PROGRESS; 3001 if (!polling) 3002 mutex_exit(&sc->sc_lock); 3003 3004 return USBD_IN_PROGRESS; 3005 } 3006 3007 Static void 3008 ohci_device_bulk_abort(struct usbd_xfer *xfer) 3009 { 3010 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3011 3012 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3013 3014 KASSERT(mutex_owned(&sc->sc_lock)); 3015 3016 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3017 usbd_xfer_abort(xfer); 3018 } 3019 3020 /* 3021 * Close a device bulk pipe. 3022 */ 3023 Static void 3024 ohci_device_bulk_close(struct usbd_pipe *pipe) 3025 { 3026 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3027 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3028 3029 KASSERT(mutex_owned(&sc->sc_lock)); 3030 3031 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3032 3033 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3034 ohci_close_pipe(pipe, sc->sc_bulk_head); 3035 ohci_free_std_locked(sc, opipe->tail.td); 3036 } 3037 3038 /************************/ 3039 3040 Static int 3041 ohci_device_intr_init(struct usbd_xfer *xfer) 3042 { 3043 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3044 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3045 int len = xfer->ux_bufsize; 3046 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3047 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3048 int err; 3049 3050 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3051 3052 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3053 KASSERT(len != 0); 3054 3055 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 3056 len, isread, xfer->ux_flags); 3057 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 3058 3059 ox->ox_nstd = 0; 3060 3061 err = ohci_alloc_std_chain(sc, xfer, len, isread); 3062 if (err) { 3063 return err; 3064 } 3065 3066 return 0; 3067 } 3068 3069 Static void 3070 ohci_device_intr_fini(struct usbd_xfer *xfer) 3071 { 3072 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3073 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3074 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3075 3076 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3077 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 3078 3079 mutex_enter(&sc->sc_lock); 3080 for (size_t i = 0; i < ox->ox_nstd; i++) { 3081 ohci_soft_td_t *std = ox->ox_stds[i]; 3082 if (std != NULL) 3083 break; 3084 if (std != opipe->tail.td) 3085 ohci_free_std_locked(sc, std); 3086 } 3087 mutex_exit(&sc->sc_lock); 3088 3089 if (ox->ox_nstd) { 3090 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 3091 kmem_free(ox->ox_stds, sz); 3092 } 3093 } 3094 3095 Static usbd_status 3096 ohci_device_intr_transfer(struct usbd_xfer *xfer) 3097 { 3098 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3099 usbd_status err; 3100 3101 /* Insert last in queue. */ 3102 mutex_enter(&sc->sc_lock); 3103 err = usb_insert_transfer(xfer); 3104 mutex_exit(&sc->sc_lock); 3105 if (err) 3106 return err; 3107 3108 /* Pipe isn't running, start first */ 3109 return ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3110 } 3111 3112 Static usbd_status 3113 ohci_device_intr_start(struct usbd_xfer *xfer) 3114 { 3115 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3116 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3117 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3118 ohci_soft_ed_t *sed = opipe->sed; 3119 ohci_soft_td_t *data, *last, *tail; 3120 int len, isread, endpt; 3121 const bool polling = sc->sc_bus.ub_usepolling; 3122 3123 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3124 3125 if (sc->sc_dying) 3126 return USBD_IOERROR; 3127 3128 DPRINTFN(3, "xfer=%#jx len=%jd flags=%jd priv=%#jx", (uintptr_t)xfer, 3129 xfer->ux_length, xfer->ux_flags, (uintptr_t)xfer->ux_priv); 3130 3131 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3132 3133 len = xfer->ux_length; 3134 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3135 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3136 3137 if (!polling) 3138 mutex_enter(&sc->sc_lock); 3139 3140 /* 3141 * Use the pipe "tail" TD as our first and loan our first TD to the 3142 * next transfer. 3143 */ 3144 data = opipe->tail.td; 3145 opipe->tail.td = ox->ox_stds[0]; 3146 ox->ox_stds[0] = data; 3147 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3148 3149 /* point at sentinel */ 3150 tail = opipe->tail.td; 3151 memset(&tail->td, 0, sizeof(tail->td)); 3152 tail->nexttd = NULL; 3153 tail->xfer = NULL; 3154 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3155 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3156 xfer->ux_hcpriv = data; 3157 3158 DPRINTFN(8, "data %#jx tail %#jx", (uintptr_t)ox->ox_stds[0], 3159 (uintptr_t)tail, 0, 0); 3160 KASSERT(opipe->tail.td == tail); 3161 3162 /* We want interrupt at the end of the transfer. */ 3163 last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3164 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3165 3166 last->td.td_nexttd = HTOO32(tail->physaddr); 3167 last->nexttd = tail; 3168 last->flags |= OHCI_CALL_DONE; 3169 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3170 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3171 3172 #ifdef OHCI_DEBUG 3173 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3174 if (ohcidebug >= 5) { 3175 ohci_dump_ed(sc, sed); 3176 ohci_dump_tds(sc, data); 3177 } 3178 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3179 #endif 3180 3181 /* Insert ED in schedule */ 3182 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3183 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3184 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3185 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3186 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3187 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3188 3189 xfer->ux_status = USBD_IN_PROGRESS; 3190 if (!polling) 3191 mutex_exit(&sc->sc_lock); 3192 3193 return USBD_IN_PROGRESS; 3194 } 3195 3196 /* Abort a device interrupt request. */ 3197 Static void 3198 ohci_device_intr_abort(struct usbd_xfer *xfer) 3199 { 3200 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3201 3202 KASSERT(mutex_owned(&sc->sc_lock)); 3203 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3204 3205 usbd_xfer_abort(xfer); 3206 } 3207 3208 /* Close a device interrupt pipe. */ 3209 Static void 3210 ohci_device_intr_close(struct usbd_pipe *pipe) 3211 { 3212 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3213 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3214 int nslots = opipe->intr.nslots; 3215 int pos = opipe->intr.pos; 3216 int j; 3217 ohci_soft_ed_t *p, *sed = opipe->sed; 3218 3219 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3220 3221 KASSERT(mutex_owned(&sc->sc_lock)); 3222 3223 DPRINTFN(1, "pipe=%#jx nslots=%jd pos=%jd", (uintptr_t)pipe, nslots, 3224 pos, 0); 3225 usb_syncmem(&sed->dma, sed->offs, 3226 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3227 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3228 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3229 sizeof(sed->ed.ed_flags), 3230 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3231 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3232 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3233 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3234 3235 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3236 continue; 3237 KASSERT(p); 3238 p->next = sed->next; 3239 p->ed.ed_nexted = sed->ed.ed_nexted; 3240 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3241 sizeof(p->ed.ed_nexted), 3242 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3243 3244 for (j = 0; j < nslots; j++) 3245 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3246 3247 ohci_free_std_locked(sc, opipe->tail.td); 3248 ohci_free_sed_locked(sc, opipe->sed); 3249 } 3250 3251 Static usbd_status 3252 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3253 { 3254 int i, j, best; 3255 u_int npoll, slow, shigh, nslots; 3256 u_int bestbw, bw; 3257 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3258 3259 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3260 3261 DPRINTFN(2, "pipe=%#jx", (uintptr_t)opipe, 0, 0, 0); 3262 if (ival == 0) { 3263 printf("ohci_setintr: 0 interval\n"); 3264 return USBD_INVAL; 3265 } 3266 3267 npoll = OHCI_NO_INTRS; 3268 while (npoll > ival) 3269 npoll /= 2; 3270 DPRINTFN(2, "ival=%jd npoll=%jd", ival, npoll, 0, 0); 3271 3272 /* 3273 * We now know which level in the tree the ED must go into. 3274 * Figure out which slot has most bandwidth left over. 3275 * Slots to examine: 3276 * npoll 3277 * 1 0 3278 * 2 1 2 3279 * 4 3 4 5 6 3280 * 8 7 8 9 10 11 12 13 14 3281 * N (N-1) .. (N-1+N-1) 3282 */ 3283 slow = npoll-1; 3284 shigh = slow + npoll; 3285 nslots = OHCI_NO_INTRS / npoll; 3286 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3287 bw = 0; 3288 for (j = 0; j < nslots; j++) 3289 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3290 if (bw < bestbw) { 3291 best = i; 3292 bestbw = bw; 3293 } 3294 } 3295 DPRINTFN(2, "best=%jd(%jd..%jd) bestbw=%jd", best, slow, shigh, bestbw); 3296 3297 mutex_enter(&sc->sc_lock); 3298 hsed = sc->sc_eds[best]; 3299 sed->next = hsed->next; 3300 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3301 sizeof(hsed->ed.ed_flags), 3302 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3303 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3304 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3305 sizeof(sed->ed.ed_flags), 3306 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3307 hsed->next = sed; 3308 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3309 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3310 sizeof(hsed->ed.ed_flags), 3311 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3312 mutex_exit(&sc->sc_lock); 3313 3314 for (j = 0; j < nslots; j++) 3315 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3316 opipe->intr.nslots = nslots; 3317 opipe->intr.pos = best; 3318 3319 DPRINTFN(5, "returns %#jx", (uintptr_t)opipe, 0, 0, 0); 3320 return USBD_NORMAL_COMPLETION; 3321 } 3322 3323 /***********************/ 3324 3325 Static int 3326 ohci_device_isoc_init(struct usbd_xfer *xfer) 3327 { 3328 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3329 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3330 ohci_soft_itd_t *sitd; 3331 size_t i; 3332 int err; 3333 3334 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3335 3336 DPRINTFN(1, "xfer %#jx len %jd flags %jd", (uintptr_t)xfer, 3337 xfer->ux_length, xfer->ux_flags, 0); 3338 3339 const size_t nfsitd = 3340 (xfer->ux_nframes + OHCI_ITD_NOFFSET - 1) / OHCI_ITD_NOFFSET; 3341 const size_t nbsitd = xfer->ux_bufsize / OHCI_PAGE_SIZE; 3342 const size_t nsitd = MAX(nfsitd, nbsitd) + 1; 3343 3344 ox->ox_sitds = kmem_zalloc(sizeof(ohci_soft_itd_t *) * nsitd, 3345 KM_SLEEP); 3346 ox->ox_nsitd = nsitd; 3347 3348 for (i = 0; i < nsitd; i++) { 3349 /* Allocate next ITD */ 3350 sitd = ohci_alloc_sitd(sc); 3351 if (sitd == NULL) { 3352 err = ENOMEM; 3353 goto fail; 3354 } 3355 ox->ox_sitds[i] = sitd; 3356 sitd->xfer = xfer; 3357 sitd->flags = 0; 3358 } 3359 3360 return 0; 3361 fail: 3362 for (; i > 0;) { 3363 ohci_free_sitd(sc, ox->ox_sitds[--i]); 3364 } 3365 return err; 3366 } 3367 3368 Static void 3369 ohci_device_isoc_fini(struct usbd_xfer *xfer) 3370 { 3371 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3372 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3373 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3374 3375 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3376 3377 mutex_enter(&sc->sc_lock); 3378 for (size_t i = 0; i < ox->ox_nsitd; i++) { 3379 if (ox->ox_sitds[i] != opipe->tail.itd) { 3380 ohci_free_sitd_locked(sc, ox->ox_sitds[i]); 3381 } 3382 } 3383 mutex_exit(&sc->sc_lock); 3384 3385 if (ox->ox_nsitd) { 3386 const size_t sz = sizeof(ohci_soft_itd_t *) * ox->ox_nsitd; 3387 kmem_free(ox->ox_sitds, sz); 3388 } 3389 } 3390 3391 3392 usbd_status 3393 ohci_device_isoc_transfer(struct usbd_xfer *xfer) 3394 { 3395 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3396 usbd_status __diagused err; 3397 3398 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3399 3400 DPRINTFN(5, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3401 3402 /* Put it on our queue, */ 3403 mutex_enter(&sc->sc_lock); 3404 err = usb_insert_transfer(xfer); 3405 mutex_exit(&sc->sc_lock); 3406 3407 KASSERT(err == USBD_NORMAL_COMPLETION); 3408 3409 /* insert into schedule, */ 3410 ohci_device_isoc_enter(xfer); 3411 3412 /* and start if the pipe wasn't running */ 3413 return USBD_IN_PROGRESS; 3414 } 3415 3416 void 3417 ohci_device_isoc_enter(struct usbd_xfer *xfer) 3418 { 3419 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3420 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3421 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3422 ohci_soft_ed_t *sed = opipe->sed; 3423 ohci_soft_itd_t *sitd, *nsitd, *tail; 3424 ohci_physaddr_t buf, offs, noffs, bp0; 3425 int i, ncur, nframes; 3426 3427 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3428 DPRINTFN(5, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3429 3430 mutex_enter(&sc->sc_lock); 3431 3432 if (sc->sc_dying) { 3433 mutex_exit(&sc->sc_lock); 3434 return; 3435 } 3436 3437 struct isoc *isoc = &opipe->isoc; 3438 3439 DPRINTFN(1, "used=%jd next=%jd xfer=%#jx nframes=%jd", 3440 isoc->inuse, isoc->next, (uintptr_t)xfer, xfer->ux_nframes); 3441 3442 if (isoc->next == -1) { 3443 /* Not in use yet, schedule it a few frames ahead. */ 3444 isoc->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3445 DPRINTFN(2,"start next=%jd", isoc->next, 0, 0, 0); 3446 } 3447 3448 sitd = opipe->tail.itd; 3449 opipe->tail.itd = ox->ox_sitds[0]; 3450 ox->ox_sitds[0] = sitd; 3451 3452 buf = DMAADDR(&xfer->ux_dmabuf, 0); 3453 bp0 = OHCI_PAGE(buf); 3454 offs = OHCI_PAGE_OFFSET(buf); 3455 nframes = xfer->ux_nframes; 3456 xfer->ux_hcpriv = sitd; 3457 size_t j = 1; 3458 for (i = ncur = 0; i < nframes; i++, ncur++) { 3459 noffs = offs + xfer->ux_frlengths[i]; 3460 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3461 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3462 3463 /* Allocate next ITD */ 3464 nsitd = ox->ox_sitds[j++]; 3465 KASSERT(nsitd != NULL); 3466 KASSERT(j < ox->ox_nsitd); 3467 3468 /* Fill current ITD */ 3469 sitd->itd.itd_flags = HTOO32( 3470 OHCI_ITD_NOCC | 3471 OHCI_ITD_SET_SF(isoc->next) | 3472 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3473 OHCI_ITD_SET_FC(ncur)); 3474 sitd->itd.itd_bp0 = HTOO32(bp0); 3475 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3476 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3477 sitd->nextitd = nsitd; 3478 sitd->xfer = xfer; 3479 sitd->flags = 0; 3480 #ifdef DIAGNOSTIC 3481 sitd->isdone = false; 3482 #endif 3483 ohci_hash_add_itd(sc, sitd); 3484 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3485 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3486 3487 sitd = nsitd; 3488 isoc->next = isoc->next + ncur; 3489 bp0 = OHCI_PAGE(buf + offs); 3490 ncur = 0; 3491 } 3492 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3493 /* XXX Sync */ 3494 offs = noffs; 3495 } 3496 KASSERT(j <= ox->ox_nsitd); 3497 3498 /* point at sentinel */ 3499 tail = opipe->tail.itd; 3500 memset(&tail->itd, 0, sizeof(tail->itd)); 3501 tail->nextitd = NULL; 3502 tail->xfer = NULL; 3503 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->itd), 3504 BUS_DMASYNC_PREWRITE); 3505 3506 /* Fixup last used ITD */ 3507 sitd->itd.itd_flags = HTOO32( 3508 OHCI_ITD_NOCC | 3509 OHCI_ITD_SET_SF(isoc->next) | 3510 OHCI_ITD_SET_DI(0) | 3511 OHCI_ITD_SET_FC(ncur)); 3512 sitd->itd.itd_bp0 = HTOO32(bp0); 3513 sitd->itd.itd_nextitd = HTOO32(tail->physaddr); 3514 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3515 sitd->nextitd = tail; 3516 sitd->xfer = xfer; 3517 sitd->flags = OHCI_CALL_DONE; 3518 #ifdef DIAGNOSTIC 3519 sitd->isdone = false; 3520 #endif 3521 ohci_hash_add_itd(sc, sitd); 3522 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3523 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3524 3525 isoc->next = isoc->next + ncur; 3526 isoc->inuse += nframes; 3527 3528 /* XXX pretend we did it all */ 3529 xfer->ux_actlen = offs; 3530 xfer->ux_status = USBD_IN_PROGRESS; 3531 3532 #ifdef OHCI_DEBUG 3533 if (ohcidebug >= 5) { 3534 DPRINTF("frame=%jd", O32TOH(sc->sc_hcca->hcca_frame_number), 3535 0, 0, 0); 3536 ohci_dump_itds(sc, xfer->ux_hcpriv); 3537 ohci_dump_ed(sc, sed); 3538 } 3539 #endif 3540 3541 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3542 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3543 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3544 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3545 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3546 sizeof(sed->ed.ed_flags), 3547 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3548 mutex_exit(&sc->sc_lock); 3549 } 3550 3551 void 3552 ohci_device_isoc_abort(struct usbd_xfer *xfer) 3553 { 3554 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3555 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3556 ohci_soft_ed_t *sed; 3557 ohci_soft_itd_t *sitd; 3558 3559 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3560 DPRINTFN(1, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3561 3562 KASSERT(mutex_owned(&sc->sc_lock)); 3563 3564 /* Transfer is already done. */ 3565 if (xfer->ux_status != USBD_NOT_STARTED && 3566 xfer->ux_status != USBD_IN_PROGRESS) { 3567 printf("ohci_device_isoc_abort: early return\n"); 3568 goto done; 3569 } 3570 3571 /* Give xfer the requested abort code. */ 3572 xfer->ux_status = USBD_CANCELLED; 3573 3574 sed = opipe->sed; 3575 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3576 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3577 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3578 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3579 sizeof(sed->ed.ed_flags), 3580 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3581 3582 sitd = xfer->ux_hcpriv; 3583 KASSERT(sitd); 3584 3585 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3586 3587 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3588 ohci_hash_rem_itd(sc, sitd); 3589 #ifdef DIAGNOSTIC 3590 DPRINTFN(1, "abort sets done sitd=%#jx", (uintptr_t)sitd, 3591 0, 0, 0); 3592 sitd->isdone = true; 3593 #endif 3594 } 3595 3596 /* Run callback. */ 3597 usb_transfer_complete(xfer); 3598 3599 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3600 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3601 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3602 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3603 3604 done: 3605 KASSERT(mutex_owned(&sc->sc_lock)); 3606 } 3607 3608 void 3609 ohci_device_isoc_done(struct usbd_xfer *xfer) 3610 { 3611 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3612 DPRINTFN(1, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3613 } 3614 3615 usbd_status 3616 ohci_setup_isoc(struct usbd_pipe *pipe) 3617 { 3618 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3619 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3620 struct isoc *isoc = &opipe->isoc; 3621 3622 isoc->next = -1; 3623 isoc->inuse = 0; 3624 3625 mutex_enter(&sc->sc_lock); 3626 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3627 mutex_exit(&sc->sc_lock); 3628 3629 return USBD_NORMAL_COMPLETION; 3630 } 3631 3632 void 3633 ohci_device_isoc_close(struct usbd_pipe *pipe) 3634 { 3635 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3636 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3637 3638 KASSERT(mutex_owned(&sc->sc_lock)); 3639 3640 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3641 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3642 ohci_close_pipe(pipe, sc->sc_isoc_head); 3643 #ifdef DIAGNOSTIC 3644 opipe->tail.itd->isdone = true; 3645 #endif 3646 ohci_free_sitd_locked(sc, opipe->tail.itd); 3647 } 3648
Indexes created Thu Sep 25 16:09:42 GMT 2025