ohci.c revision 1.307
1 /* $NetBSD: ohci.c,v 1.307 2020/05/19 19:09:43 jakllsch Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * USB Open Host Controller driver. 38 * 39 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 40 * USB spec: http://www.usb.org/developers/docs/ 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.307 2020/05/19 19:09:43 jakllsch Exp $"); 45 46 #ifdef _KERNEL_OPT 47 #include "opt_usb.h" 48 #endif 49 50 #include <sys/param.h> 51 52 #include <sys/cpu.h> 53 #include <sys/device.h> 54 #include <sys/kernel.h> 55 #include <sys/kmem.h> 56 #include <sys/proc.h> 57 #include <sys/queue.h> 58 #include <sys/select.h> 59 #include <sys/sysctl.h> 60 #include <sys/systm.h> 61 62 #include <machine/endian.h> 63 64 #include <dev/usb/usb.h> 65 #include <dev/usb/usbdi.h> 66 #include <dev/usb/usbdivar.h> 67 #include <dev/usb/usb_mem.h> 68 #include <dev/usb/usb_quirks.h> 69 70 #include <dev/usb/ohcireg.h> 71 #include <dev/usb/ohcivar.h> 72 #include <dev/usb/usbroothub.h> 73 #include <dev/usb/usbhist.h> 74 75 #ifdef USB_DEBUG 76 #ifndef OHCI_DEBUG 77 #define ohcidebug 0 78 #else 79 static int ohcidebug = 10; 80 81 SYSCTL_SETUP(sysctl_hw_ohci_setup, "sysctl hw.ohci setup") 82 { 83 int err; 84 const struct sysctlnode *rnode; 85 const struct sysctlnode *cnode; 86 87 err = sysctl_createv(clog, 0, NULL, &rnode, 88 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ohci", 89 SYSCTL_DESCR("ohci global controls"), 90 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 91 92 if (err) 93 goto fail; 94 95 /* control debugging printfs */ 96 err = sysctl_createv(clog, 0, &rnode, &cnode, 97 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 98 "debug", SYSCTL_DESCR("Enable debugging output"), 99 NULL, 0, &ohcidebug, sizeof(ohcidebug), CTL_CREATE, CTL_EOL); 100 if (err) 101 goto fail; 102 103 return; 104 fail: 105 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 106 } 107 108 #endif /* OHCI_DEBUG */ 109 #endif /* USB_DEBUG */ 110 111 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ohcidebug,FMT,A,B,C,D) 112 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ohcidebug,N,FMT,A,B,C,D) 113 #define OHCIHIST_FUNC() USBHIST_FUNC() 114 #define OHCIHIST_CALLED(name) USBHIST_CALLED(ohcidebug) 115 116 #if BYTE_ORDER == BIG_ENDIAN 117 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 118 #else 119 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 120 #endif 121 122 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 123 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 124 #define HTOO16(val) O16TOH(val) 125 #define HTOO32(val) O32TOH(val) 126 127 struct ohci_pipe; 128 129 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 130 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 131 132 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 133 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 134 Static void ohci_free_std_locked(ohci_softc_t *, ohci_soft_td_t *); 135 136 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 137 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 138 Static void ohci_free_sitd_locked(ohci_softc_t *, 139 ohci_soft_itd_t *); 140 141 Static int ohci_alloc_std_chain(ohci_softc_t *, struct usbd_xfer *, 142 int, int); 143 Static void ohci_free_stds(ohci_softc_t *, struct ohci_xfer *); 144 145 Static void ohci_reset_std_chain(ohci_softc_t *, struct usbd_xfer *, 146 int, int, ohci_soft_td_t *, ohci_soft_td_t **); 147 148 Static usbd_status ohci_open(struct usbd_pipe *); 149 Static void ohci_poll(struct usbd_bus *); 150 Static void ohci_softintr(void *); 151 Static void ohci_rhsc(ohci_softc_t *, struct usbd_xfer *); 152 Static void ohci_rhsc_softint(void *); 153 154 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 155 ohci_soft_ed_t *); 156 157 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 158 ohci_soft_ed_t *); 159 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 160 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 161 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 162 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 163 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 164 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 165 166 Static usbd_status ohci_setup_isoc(struct usbd_pipe *); 167 Static void ohci_device_isoc_enter(struct usbd_xfer *); 168 169 Static struct usbd_xfer * 170 ohci_allocx(struct usbd_bus *, unsigned int); 171 Static void ohci_freex(struct usbd_bus *, struct usbd_xfer *); 172 Static bool ohci_dying(struct usbd_bus *); 173 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 174 Static int ohci_roothub_ctrl(struct usbd_bus *, 175 usb_device_request_t *, void *, int); 176 177 Static usbd_status ohci_root_intr_transfer(struct usbd_xfer *); 178 Static usbd_status ohci_root_intr_start(struct usbd_xfer *); 179 Static void ohci_root_intr_abort(struct usbd_xfer *); 180 Static void ohci_root_intr_close(struct usbd_pipe *); 181 Static void ohci_root_intr_done(struct usbd_xfer *); 182 183 Static int ohci_device_ctrl_init(struct usbd_xfer *); 184 Static void ohci_device_ctrl_fini(struct usbd_xfer *); 185 Static usbd_status ohci_device_ctrl_transfer(struct usbd_xfer *); 186 Static usbd_status ohci_device_ctrl_start(struct usbd_xfer *); 187 Static void ohci_device_ctrl_abort(struct usbd_xfer *); 188 Static void ohci_device_ctrl_close(struct usbd_pipe *); 189 Static void ohci_device_ctrl_done(struct usbd_xfer *); 190 191 Static int ohci_device_bulk_init(struct usbd_xfer *); 192 Static void ohci_device_bulk_fini(struct usbd_xfer *); 193 Static usbd_status ohci_device_bulk_transfer(struct usbd_xfer *); 194 Static usbd_status ohci_device_bulk_start(struct usbd_xfer *); 195 Static void ohci_device_bulk_abort(struct usbd_xfer *); 196 Static void ohci_device_bulk_close(struct usbd_pipe *); 197 Static void ohci_device_bulk_done(struct usbd_xfer *); 198 199 Static int ohci_device_intr_init(struct usbd_xfer *); 200 Static void ohci_device_intr_fini(struct usbd_xfer *); 201 Static usbd_status ohci_device_intr_transfer(struct usbd_xfer *); 202 Static usbd_status ohci_device_intr_start(struct usbd_xfer *); 203 Static void ohci_device_intr_abort(struct usbd_xfer *); 204 Static void ohci_device_intr_close(struct usbd_pipe *); 205 Static void ohci_device_intr_done(struct usbd_xfer *); 206 207 Static int ohci_device_isoc_init(struct usbd_xfer *); 208 Static void ohci_device_isoc_fini(struct usbd_xfer *); 209 Static usbd_status ohci_device_isoc_transfer(struct usbd_xfer *); 210 Static void ohci_device_isoc_abort(struct usbd_xfer *); 211 Static void ohci_device_isoc_close(struct usbd_pipe *); 212 Static void ohci_device_isoc_done(struct usbd_xfer *); 213 214 Static usbd_status ohci_device_setintr(ohci_softc_t *, 215 struct ohci_pipe *, int); 216 217 Static void ohci_rhsc_enable(void *); 218 219 Static void ohci_close_pipe(struct usbd_pipe *, ohci_soft_ed_t *); 220 Static void ohci_abortx(struct usbd_xfer *); 221 222 Static void ohci_device_clear_toggle(struct usbd_pipe *); 223 Static void ohci_noop(struct usbd_pipe *); 224 225 #ifdef OHCI_DEBUG 226 Static void ohci_dumpregs(ohci_softc_t *); 227 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 228 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 229 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 230 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 231 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 232 #endif 233 234 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 235 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 236 #define OWRITE1(sc, r, x) \ 237 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 238 #define OWRITE2(sc, r, x) \ 239 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 240 #define OWRITE4(sc, r, x) \ 241 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 242 243 static __inline uint32_t 244 OREAD4(ohci_softc_t *sc, bus_size_t r) 245 { 246 247 OBARR(sc); 248 return bus_space_read_4(sc->iot, sc->ioh, r); 249 } 250 251 /* Reverse the bits in a value 0 .. 31 */ 252 Static uint8_t revbits[OHCI_NO_INTRS] = 253 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 254 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 255 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 256 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 257 258 struct ohci_pipe { 259 struct usbd_pipe pipe; 260 ohci_soft_ed_t *sed; 261 union { 262 ohci_soft_td_t *td; 263 ohci_soft_itd_t *itd; 264 } tail; 265 /* Info needed for different pipe kinds. */ 266 union { 267 /* Control pipe */ 268 struct { 269 usb_dma_t reqdma; 270 } ctrl; 271 /* Interrupt pipe */ 272 struct { 273 int nslots; 274 int pos; 275 } intr; 276 /* Isochronous pipe */ 277 struct isoc { 278 int next, inuse; 279 } isoc; 280 }; 281 }; 282 283 Static const struct usbd_bus_methods ohci_bus_methods = { 284 .ubm_open = ohci_open, 285 .ubm_softint = ohci_softintr, 286 .ubm_dopoll = ohci_poll, 287 .ubm_allocx = ohci_allocx, 288 .ubm_freex = ohci_freex, 289 .ubm_abortx = ohci_abortx, 290 .ubm_dying = ohci_dying, 291 .ubm_getlock = ohci_get_lock, 292 .ubm_rhctrl = ohci_roothub_ctrl, 293 }; 294 295 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 296 .upm_transfer = ohci_root_intr_transfer, 297 .upm_start = ohci_root_intr_start, 298 .upm_abort = ohci_root_intr_abort, 299 .upm_close = ohci_root_intr_close, 300 .upm_cleartoggle = ohci_noop, 301 .upm_done = ohci_root_intr_done, 302 }; 303 304 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 305 .upm_init = ohci_device_ctrl_init, 306 .upm_fini = ohci_device_ctrl_fini, 307 .upm_transfer = ohci_device_ctrl_transfer, 308 .upm_start = ohci_device_ctrl_start, 309 .upm_abort = ohci_device_ctrl_abort, 310 .upm_close = ohci_device_ctrl_close, 311 .upm_cleartoggle = ohci_noop, 312 .upm_done = ohci_device_ctrl_done, 313 }; 314 315 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 316 .upm_init = ohci_device_intr_init, 317 .upm_fini = ohci_device_intr_fini, 318 .upm_transfer = ohci_device_intr_transfer, 319 .upm_start = ohci_device_intr_start, 320 .upm_abort = ohci_device_intr_abort, 321 .upm_close = ohci_device_intr_close, 322 .upm_cleartoggle = ohci_device_clear_toggle, 323 .upm_done = ohci_device_intr_done, 324 }; 325 326 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 327 .upm_init = ohci_device_bulk_init, 328 .upm_fini = ohci_device_bulk_fini, 329 .upm_transfer = ohci_device_bulk_transfer, 330 .upm_start = ohci_device_bulk_start, 331 .upm_abort = ohci_device_bulk_abort, 332 .upm_close = ohci_device_bulk_close, 333 .upm_cleartoggle = ohci_device_clear_toggle, 334 .upm_done = ohci_device_bulk_done, 335 }; 336 337 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 338 .upm_init = ohci_device_isoc_init, 339 .upm_fini = ohci_device_isoc_fini, 340 .upm_transfer = ohci_device_isoc_transfer, 341 .upm_abort = ohci_device_isoc_abort, 342 .upm_close = ohci_device_isoc_close, 343 .upm_cleartoggle = ohci_noop, 344 .upm_done = ohci_device_isoc_done, 345 }; 346 347 int 348 ohci_activate(device_t self, enum devact act) 349 { 350 struct ohci_softc *sc = device_private(self); 351 352 switch (act) { 353 case DVACT_DEACTIVATE: 354 sc->sc_dying = 1; 355 return 0; 356 default: 357 return EOPNOTSUPP; 358 } 359 } 360 361 void 362 ohci_childdet(device_t self, device_t child) 363 { 364 struct ohci_softc *sc = device_private(self); 365 366 KASSERT(sc->sc_child == child); 367 sc->sc_child = NULL; 368 } 369 370 int 371 ohci_detach(struct ohci_softc *sc, int flags) 372 { 373 int rv = 0; 374 375 if (sc->sc_child != NULL) 376 rv = config_detach(sc->sc_child, flags); 377 378 if (rv != 0) 379 return rv; 380 381 softint_disestablish(sc->sc_rhsc_si); 382 383 callout_halt(&sc->sc_tmo_rhsc, NULL); 384 callout_destroy(&sc->sc_tmo_rhsc); 385 386 mutex_destroy(&sc->sc_lock); 387 mutex_destroy(&sc->sc_intr_lock); 388 389 if (sc->sc_hcca != NULL) 390 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 391 pool_cache_destroy(sc->sc_xferpool); 392 393 return rv; 394 } 395 396 ohci_soft_ed_t * 397 ohci_alloc_sed(ohci_softc_t *sc) 398 { 399 ohci_soft_ed_t *sed; 400 usbd_status err; 401 int i, offs; 402 usb_dma_t dma; 403 404 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 405 406 mutex_enter(&sc->sc_lock); 407 if (sc->sc_freeeds == NULL) { 408 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 409 mutex_exit(&sc->sc_lock); 410 411 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 412 OHCI_ED_ALIGN, USBMALLOC_COHERENT, &dma); 413 if (err) 414 return NULL; 415 416 mutex_enter(&sc->sc_lock); 417 for (i = 0; i < OHCI_SED_CHUNK; i++) { 418 offs = i * OHCI_SED_SIZE; 419 sed = KERNADDR(&dma, offs); 420 sed->physaddr = DMAADDR(&dma, offs); 421 sed->dma = dma; 422 sed->offs = offs; 423 sed->next = sc->sc_freeeds; 424 sc->sc_freeeds = sed; 425 } 426 } 427 sed = sc->sc_freeeds; 428 sc->sc_freeeds = sed->next; 429 mutex_exit(&sc->sc_lock); 430 431 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 432 sed->next = 0; 433 return sed; 434 } 435 436 static inline void 437 ohci_free_sed_locked(ohci_softc_t *sc, ohci_soft_ed_t *sed) 438 { 439 440 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 441 442 sed->next = sc->sc_freeeds; 443 sc->sc_freeeds = sed; 444 } 445 446 void 447 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 448 { 449 450 mutex_enter(&sc->sc_lock); 451 ohci_free_sed_locked(sc, sed); 452 mutex_exit(&sc->sc_lock); 453 } 454 455 ohci_soft_td_t * 456 ohci_alloc_std(ohci_softc_t *sc) 457 { 458 ohci_soft_td_t *std; 459 usbd_status err; 460 int i, offs; 461 usb_dma_t dma; 462 463 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 464 465 mutex_enter(&sc->sc_lock); 466 if (sc->sc_freetds == NULL) { 467 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 468 mutex_exit(&sc->sc_lock); 469 470 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 471 OHCI_TD_ALIGN, USBMALLOC_COHERENT, &dma); 472 if (err) 473 return NULL; 474 475 mutex_enter(&sc->sc_lock); 476 for (i = 0; i < OHCI_STD_CHUNK; i++) { 477 offs = i * OHCI_STD_SIZE; 478 std = KERNADDR(&dma, offs); 479 std->physaddr = DMAADDR(&dma, offs); 480 std->dma = dma; 481 std->offs = offs; 482 std->nexttd = sc->sc_freetds; 483 sc->sc_freetds = std; 484 } 485 } 486 487 std = sc->sc_freetds; 488 sc->sc_freetds = std->nexttd; 489 mutex_exit(&sc->sc_lock); 490 491 memset(&std->td, 0, sizeof(ohci_td_t)); 492 std->nexttd = NULL; 493 std->xfer = NULL; 494 495 return std; 496 } 497 498 void 499 ohci_free_std_locked(ohci_softc_t *sc, ohci_soft_td_t *std) 500 { 501 502 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 503 504 std->nexttd = sc->sc_freetds; 505 sc->sc_freetds = std; 506 } 507 508 void 509 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 510 { 511 512 mutex_enter(&sc->sc_lock); 513 ohci_free_std_locked(sc, std); 514 mutex_exit(&sc->sc_lock); 515 } 516 517 Static int 518 ohci_alloc_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, int length, int rd) 519 { 520 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 521 uint16_t flags = xfer->ux_flags; 522 523 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 524 525 DPRINTFN(8, "addr=%jd endpt=%jd len=%jd speed=%jd", 526 xfer->ux_pipe->up_dev->ud_addr, 527 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 528 length, xfer->ux_pipe->up_dev->ud_speed); 529 530 ASSERT_SLEEPABLE(); 531 KASSERT(length != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 532 533 size_t nstd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 534 nstd += howmany(length, OHCI_PAGE_SIZE); 535 ox->ox_stds = kmem_zalloc(sizeof(ohci_soft_td_t *) * nstd, 536 KM_SLEEP); 537 ox->ox_nstd = nstd; 538 539 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, nstd, 0, 0); 540 541 for (size_t j = 0; j < ox->ox_nstd;) { 542 ohci_soft_td_t *cur = ohci_alloc_std(sc); 543 if (cur == NULL) 544 goto nomem; 545 546 ox->ox_stds[j++] = cur; 547 cur->xfer = xfer; 548 cur->flags = 0; 549 } 550 551 return 0; 552 553 nomem: 554 ohci_free_stds(sc, ox); 555 kmem_free(ox->ox_stds, sizeof(ohci_soft_td_t *) * nstd); 556 557 return ENOMEM; 558 } 559 560 Static void 561 ohci_free_stds(ohci_softc_t *sc, struct ohci_xfer *ox) 562 { 563 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 564 DPRINTF("ox=%#jx", (uintptr_t)ox, 0, 0, 0); 565 566 mutex_enter(&sc->sc_lock); 567 for (size_t i = 0; i < ox->ox_nstd; i++) { 568 ohci_soft_td_t *std = ox->ox_stds[i]; 569 if (std == NULL) 570 break; 571 ohci_free_std_locked(sc, std); 572 } 573 mutex_exit(&sc->sc_lock); 574 } 575 576 void 577 ohci_reset_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, 578 int alen, int rd, ohci_soft_td_t *sp, ohci_soft_td_t **ep) 579 { 580 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 581 ohci_soft_td_t *next, *cur; 582 int len, curlen; 583 usb_dma_t *dma = &xfer->ux_dmabuf; 584 uint16_t flags = xfer->ux_flags; 585 586 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 587 DPRINTF("start len=%jd", alen, 0, 0, 0); 588 589 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 590 591 DPRINTFN(8, "addr=%jd endpt=%jd len=%jd speed=%jd", 592 xfer->ux_pipe->up_dev->ud_addr, 593 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 594 alen, xfer->ux_pipe->up_dev->ud_speed); 595 596 KASSERT(sp); 597 598 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 599 600 /* 601 * Assign next for the len == 0 case where we don't go through the 602 * main loop. 603 */ 604 len = alen; 605 cur = next = sp; 606 607 usb_syncmem(dma, 0, len, 608 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 609 const uint32_t tdflags = HTOO32( 610 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 611 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 612 613 size_t curoffs = 0; 614 for (size_t j = 1; len != 0;) { 615 if (j == ox->ox_nstd) 616 next = NULL; 617 else 618 next = ox->ox_stds[j++]; 619 KASSERT(next != cur); 620 621 curlen = 0; 622 const ohci_physaddr_t sdataphys = DMAADDR(dma, curoffs); 623 ohci_physaddr_t edataphys = DMAADDR(dma, curoffs + len - 1); 624 625 const ohci_physaddr_t sphyspg = OHCI_PAGE(sdataphys); 626 ohci_physaddr_t ephyspg = OHCI_PAGE(edataphys); 627 /* 628 * The OHCI hardware can handle at most one page 629 * crossing per TD 630 */ 631 curlen = len; 632 if (sphyspg != ephyspg && 633 sphyspg + OHCI_PAGE_SIZE != ephyspg) { 634 /* must use multiple TDs, fill as much as possible. */ 635 curlen = 2 * OHCI_PAGE_SIZE - 636 OHCI_PAGE_OFFSET(sdataphys); 637 /* the length must be a multiple of the max size */ 638 curlen -= curlen % mps; 639 edataphys = DMAADDR(dma, curoffs + curlen - 1); 640 } 641 KASSERT(curlen != 0); 642 DPRINTFN(4, "sdataphys=0x%08jx edataphys=0x%08jx " 643 "len=%jd curlen=%jd", sdataphys, edataphys, len, curlen); 644 645 cur->td.td_flags = tdflags; 646 cur->td.td_cbp = HTOO32(sdataphys); 647 cur->td.td_be = HTOO32(edataphys); 648 cur->td.td_nexttd = (next != NULL) ? HTOO32(next->physaddr) : 0; 649 cur->nexttd = next; 650 cur->len = curlen; 651 cur->flags = OHCI_ADD_LEN; 652 cur->xfer = xfer; 653 ohci_hash_add_td(sc, cur); 654 655 curoffs += curlen; 656 len -= curlen; 657 658 if (len != 0) { 659 KASSERT(next != NULL); 660 DPRINTFN(10, "extend chain", 0, 0, 0, 0); 661 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 662 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 663 664 cur = next; 665 } 666 } 667 cur->td.td_flags |= 668 HTOO32(xfer->ux_flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0); 669 670 if (!rd && 671 (flags & USBD_FORCE_SHORT_XFER) && 672 alen % mps == 0) { 673 /* We're adding a ZLP so sync the previous TD */ 674 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 675 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 676 677 /* Force a 0 length transfer at the end. */ 678 679 KASSERT(next != NULL); 680 cur = next; 681 682 cur->td.td_flags = tdflags; 683 cur->td.td_cbp = 0; /* indicate 0 length packet */ 684 cur->td.td_nexttd = 0; 685 cur->td.td_be = ~0; 686 cur->nexttd = NULL; 687 cur->len = 0; 688 cur->flags = 0; 689 cur->xfer = xfer; 690 ohci_hash_add_td(sc, cur); 691 692 DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0); 693 } 694 695 /* Last TD gets usb_syncmem'ed by caller */ 696 *ep = cur; 697 } 698 699 ohci_soft_itd_t * 700 ohci_alloc_sitd(ohci_softc_t *sc) 701 { 702 ohci_soft_itd_t *sitd; 703 usbd_status err; 704 int i, offs; 705 usb_dma_t dma; 706 707 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 708 709 mutex_enter(&sc->sc_lock); 710 if (sc->sc_freeitds == NULL) { 711 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 712 mutex_exit(&sc->sc_lock); 713 714 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 715 OHCI_ITD_ALIGN, USBMALLOC_COHERENT, &dma); 716 if (err) 717 return NULL; 718 mutex_enter(&sc->sc_lock); 719 for (i = 0; i < OHCI_SITD_CHUNK; i++) { 720 offs = i * OHCI_SITD_SIZE; 721 sitd = KERNADDR(&dma, offs); 722 sitd->physaddr = DMAADDR(&dma, offs); 723 sitd->dma = dma; 724 sitd->offs = offs; 725 sitd->nextitd = sc->sc_freeitds; 726 sc->sc_freeitds = sitd; 727 } 728 } 729 730 sitd = sc->sc_freeitds; 731 sc->sc_freeitds = sitd->nextitd; 732 mutex_exit(&sc->sc_lock); 733 734 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 735 sitd->nextitd = NULL; 736 sitd->xfer = NULL; 737 738 #ifdef DIAGNOSTIC 739 sitd->isdone = true; 740 #endif 741 742 return sitd; 743 } 744 745 Static void 746 ohci_free_sitd_locked(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 747 { 748 749 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 750 DPRINTFN(10, "sitd=%#jx", (uintptr_t)sitd, 0, 0, 0); 751 752 KASSERT(sitd->isdone); 753 #ifdef DIAGNOSTIC 754 /* Warn double free */ 755 sitd->isdone = false; 756 #endif 757 758 sitd->nextitd = sc->sc_freeitds; 759 sc->sc_freeitds = sitd; 760 } 761 762 void 763 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 764 { 765 766 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 767 768 mutex_enter(&sc->sc_lock); 769 ohci_free_sitd_locked(sc, sitd); 770 mutex_exit(&sc->sc_lock); 771 } 772 773 int 774 ohci_init(ohci_softc_t *sc) 775 { 776 ohci_soft_ed_t *sed, *psed; 777 usbd_status err; 778 int i; 779 uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */; 780 781 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 782 783 aprint_normal_dev(sc->sc_dev, ""); 784 785 sc->sc_hcca = NULL; 786 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 787 788 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 789 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 790 791 sc->sc_rhsc_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 792 ohci_rhsc_softint, sc); 793 794 for (i = 0; i < OHCI_HASH_SIZE; i++) 795 LIST_INIT(&sc->sc_hash_tds[i]); 796 for (i = 0; i < OHCI_HASH_SIZE; i++) 797 LIST_INIT(&sc->sc_hash_itds[i]); 798 799 sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0, 800 "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL); 801 802 rev = OREAD4(sc, OHCI_REVISION); 803 aprint_normal("OHCI version %d.%d%s\n", 804 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 805 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 806 807 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 808 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 809 sc->sc_bus.ub_revision = USBREV_UNKNOWN; 810 return -1; 811 } 812 sc->sc_bus.ub_revision = USBREV_1_0; 813 sc->sc_bus.ub_usedma = true; 814 815 /* XXX determine alignment by R/W */ 816 /* Allocate the HCCA area. */ 817 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 818 OHCI_HCCA_ALIGN, USBMALLOC_COHERENT, &sc->sc_hccadma); 819 if (err) { 820 sc->sc_hcca = NULL; 821 return err; 822 } 823 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 824 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 825 826 sc->sc_eintrs = OHCI_NORMAL_INTRS; 827 828 /* Allocate dummy ED that starts the control list. */ 829 sc->sc_ctrl_head = ohci_alloc_sed(sc); 830 if (sc->sc_ctrl_head == NULL) { 831 err = ENOMEM; 832 goto bad1; 833 } 834 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 835 836 /* Allocate dummy ED that starts the bulk list. */ 837 sc->sc_bulk_head = ohci_alloc_sed(sc); 838 if (sc->sc_bulk_head == NULL) { 839 err = ENOMEM; 840 goto bad2; 841 } 842 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 843 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 844 sizeof(sc->sc_bulk_head->ed), 845 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 846 847 /* Allocate dummy ED that starts the isochronous list. */ 848 sc->sc_isoc_head = ohci_alloc_sed(sc); 849 if (sc->sc_isoc_head == NULL) { 850 err = ENOMEM; 851 goto bad3; 852 } 853 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 854 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 855 sizeof(sc->sc_isoc_head->ed), 856 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 857 858 /* Allocate all the dummy EDs that make up the interrupt tree. */ 859 for (i = 0; i < OHCI_NO_EDS; i++) { 860 sed = ohci_alloc_sed(sc); 861 if (sed == NULL) { 862 while (--i >= 0) 863 ohci_free_sed(sc, sc->sc_eds[i]); 864 err = ENOMEM; 865 goto bad4; 866 } 867 /* All ED fields are set to 0. */ 868 sc->sc_eds[i] = sed; 869 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 870 if (i != 0) 871 psed = sc->sc_eds[(i-1) / 2]; 872 else 873 psed= sc->sc_isoc_head; 874 sed->next = psed; 875 sed->ed.ed_nexted = HTOO32(psed->physaddr); 876 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 877 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 878 } 879 /* 880 * Fill HCCA interrupt table. The bit reversal is to get 881 * the tree set up properly to spread the interrupts. 882 */ 883 for (i = 0; i < OHCI_NO_INTRS; i++) 884 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 885 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 886 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 887 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 888 889 #ifdef OHCI_DEBUG 890 DPRINTFN(15, "--- dump start ---", 0, 0, 0 ,0); 891 if (ohcidebug >= 15) { 892 for (i = 0; i < OHCI_NO_EDS; i++) { 893 DPRINTFN(15, "ed#%jd ", i, 0, 0, 0); 894 ohci_dump_ed(sc, sc->sc_eds[i]); 895 } 896 DPRINTFN(15, "iso", 0, 0, 0 ,0); 897 ohci_dump_ed(sc, sc->sc_isoc_head); 898 } 899 DPRINTFN(15, "--- dump end ---", 0, 0, 0 ,0); 900 #endif 901 902 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 903 ctl = OREAD4(sc, OHCI_CONTROL); 904 rwc = ctl & OHCI_RWC; 905 fm = OREAD4(sc, OHCI_FM_INTERVAL); 906 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 907 /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */ 908 909 /* Determine in what context we are running. */ 910 if (ctl & OHCI_IR) { 911 /* SMM active, request change */ 912 DPRINTF("SMM active, request owner change", 0, 0, 0, 0); 913 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 914 (OHCI_OC | OHCI_MIE)) 915 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 916 s = OREAD4(sc, OHCI_COMMAND_STATUS); 917 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 918 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 919 usb_delay_ms(&sc->sc_bus, 1); 920 ctl = OREAD4(sc, OHCI_CONTROL); 921 } 922 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 923 if ((ctl & OHCI_IR) == 0) { 924 aprint_error_dev(sc->sc_dev, 925 "SMM does not respond, resetting\n"); 926 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 927 goto reset; 928 } 929 #if 0 930 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 931 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 932 /* BIOS started controller. */ 933 DPRINTF("BIOS active", 0, 0, 0, 0); 934 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 935 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 936 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 937 } 938 #endif 939 } else { 940 DPRINTF("cold started", 0 ,0 ,0 ,0); 941 reset: 942 /* Controller was cold started. */ 943 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 944 } 945 946 /* 947 * This reset should not be necessary according to the OHCI spec, but 948 * without it some controllers do not start. 949 */ 950 DPRINTF("sc %#jx: resetting", (uintptr_t)sc, 0, 0, 0); 951 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 952 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 953 954 /* We now own the host controller and the bus has been reset. */ 955 956 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 957 /* Nominal time for a reset is 10 us. */ 958 for (i = 0; i < 10; i++) { 959 delay(10); 960 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 961 if (!hcr) 962 break; 963 } 964 if (hcr) { 965 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 966 err = EIO; 967 goto bad5; 968 } 969 #ifdef OHCI_DEBUG 970 if (ohcidebug >= 15) 971 ohci_dumpregs(sc); 972 #endif 973 974 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 975 976 /* Set up HC registers. */ 977 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 978 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 979 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 980 /* disable all interrupts and then switch on all desired interrupts */ 981 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 982 /* switch on desired functional features */ 983 ctl = OREAD4(sc, OHCI_CONTROL); 984 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 985 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 986 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 987 /* And finally start it! */ 988 OWRITE4(sc, OHCI_CONTROL, ctl); 989 990 /* 991 * The controller is now OPERATIONAL. Set a some final 992 * registers that should be set earlier, but that the 993 * controller ignores when in the SUSPEND state. 994 */ 995 ival = OHCI_GET_IVAL(fm); 996 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 997 fm |= OHCI_FSMPS(ival) | ival; 998 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 999 per = OHCI_PERIODIC(ival); /* 90% periodic */ 1000 OWRITE4(sc, OHCI_PERIODIC_START, per); 1001 1002 if (sc->sc_flags & OHCIF_SUPERIO) { 1003 /* no overcurrent protection */ 1004 desca |= OHCI_NOCP; 1005 /* 1006 * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning 1007 * that 1008 * - ports are always power switched 1009 * - don't wait for powered root hub port 1010 */ 1011 desca &= ~(__SHIFTIN(0xff, OHCI_POTPGT_MASK) | OHCI_NPS); 1012 } 1013 1014 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 1015 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 1016 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 1017 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 1018 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 1019 1020 /* 1021 * The AMD756 requires a delay before re-reading the register, 1022 * otherwise it will occasionally report 0 ports. 1023 */ 1024 sc->sc_noport = 0; 1025 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 1026 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 1027 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 1028 } 1029 1030 #ifdef OHCI_DEBUG 1031 if (ohcidebug >= 5) 1032 ohci_dumpregs(sc); 1033 #endif 1034 1035 /* Set up the bus struct. */ 1036 sc->sc_bus.ub_methods = &ohci_bus_methods; 1037 sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe); 1038 1039 sc->sc_control = sc->sc_intre = 0; 1040 1041 /* Finally, turn on interrupts. */ 1042 DPRINTF("enabling %#jx", sc->sc_eintrs | OHCI_MIE, 0, 0, 0); 1043 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 1044 1045 return 0; 1046 1047 bad5: 1048 for (i = 0; i < OHCI_NO_EDS; i++) 1049 ohci_free_sed(sc, sc->sc_eds[i]); 1050 bad4: 1051 ohci_free_sed(sc, sc->sc_isoc_head); 1052 bad3: 1053 ohci_free_sed(sc, sc->sc_bulk_head); 1054 bad2: 1055 ohci_free_sed(sc, sc->sc_ctrl_head); 1056 bad1: 1057 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 1058 sc->sc_hcca = NULL; 1059 return err; 1060 } 1061 1062 struct usbd_xfer * 1063 ohci_allocx(struct usbd_bus *bus, unsigned int nframes) 1064 { 1065 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1066 struct usbd_xfer *xfer; 1067 1068 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 1069 if (xfer != NULL) { 1070 memset(xfer, 0, sizeof(struct ohci_xfer)); 1071 1072 #ifdef DIAGNOSTIC 1073 xfer->ux_state = XFER_BUSY; 1074 #endif 1075 } 1076 return xfer; 1077 } 1078 1079 void 1080 ohci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1081 { 1082 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1083 1084 KASSERTMSG(xfer->ux_state == XFER_BUSY || 1085 xfer->ux_status == USBD_NOT_STARTED, 1086 "xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state); 1087 #ifdef DIAGNOSTIC 1088 xfer->ux_state = XFER_FREE; 1089 #endif 1090 pool_cache_put(sc->sc_xferpool, xfer); 1091 } 1092 1093 Static bool 1094 ohci_dying(struct usbd_bus *bus) 1095 { 1096 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1097 1098 return sc->sc_dying; 1099 } 1100 1101 Static void 1102 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1103 { 1104 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1105 1106 *lock = &sc->sc_lock; 1107 } 1108 1109 /* 1110 * Shut down the controller when the system is going down. 1111 */ 1112 bool 1113 ohci_shutdown(device_t self, int flags) 1114 { 1115 ohci_softc_t *sc = device_private(self); 1116 1117 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1118 1119 DPRINTF("stopping the HC", 0, 0, 0, 0); 1120 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 1121 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1122 return true; 1123 } 1124 1125 bool 1126 ohci_resume(device_t dv, const pmf_qual_t *qual) 1127 { 1128 ohci_softc_t *sc = device_private(dv); 1129 uint32_t ctl; 1130 1131 mutex_spin_enter(&sc->sc_intr_lock); 1132 sc->sc_bus.ub_usepolling++; 1133 mutex_spin_exit(&sc->sc_intr_lock); 1134 1135 /* Some broken BIOSes do not recover these values */ 1136 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1137 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1138 sc->sc_ctrl_head->physaddr); 1139 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1140 sc->sc_bulk_head->physaddr); 1141 if (sc->sc_intre) 1142 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1143 (OHCI_ALL_INTRS | OHCI_MIE)); 1144 if (sc->sc_control) 1145 ctl = sc->sc_control; 1146 else 1147 ctl = OREAD4(sc, OHCI_CONTROL); 1148 ctl |= OHCI_HCFS_RESUME; 1149 OWRITE4(sc, OHCI_CONTROL, ctl); 1150 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1151 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1152 OWRITE4(sc, OHCI_CONTROL, ctl); 1153 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1154 sc->sc_control = sc->sc_intre = 0; 1155 1156 mutex_spin_enter(&sc->sc_intr_lock); 1157 sc->sc_bus.ub_usepolling--; 1158 mutex_spin_exit(&sc->sc_intr_lock); 1159 1160 return true; 1161 } 1162 1163 bool 1164 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1165 { 1166 ohci_softc_t *sc = device_private(dv); 1167 uint32_t ctl; 1168 1169 mutex_spin_enter(&sc->sc_intr_lock); 1170 sc->sc_bus.ub_usepolling++; 1171 mutex_spin_exit(&sc->sc_intr_lock); 1172 1173 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1174 if (sc->sc_control == 0) { 1175 /* 1176 * Preserve register values, in case that BIOS 1177 * does not recover them. 1178 */ 1179 sc->sc_control = ctl; 1180 sc->sc_intre = OREAD4(sc, 1181 OHCI_INTERRUPT_ENABLE); 1182 } 1183 ctl |= OHCI_HCFS_SUSPEND; 1184 OWRITE4(sc, OHCI_CONTROL, ctl); 1185 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1186 1187 mutex_spin_enter(&sc->sc_intr_lock); 1188 sc->sc_bus.ub_usepolling--; 1189 mutex_spin_exit(&sc->sc_intr_lock); 1190 1191 return true; 1192 } 1193 1194 #ifdef OHCI_DEBUG 1195 void 1196 ohci_dumpregs(ohci_softc_t *sc) 1197 { 1198 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1199 1200 DPRINTF("rev=0x%08jx control=0x%08jx command=0x%08jx", 1201 OREAD4(sc, OHCI_REVISION), 1202 OREAD4(sc, OHCI_CONTROL), 1203 OREAD4(sc, OHCI_COMMAND_STATUS), 0); 1204 DPRINTF(" intrstat=0x%08jx intre=0x%08jx intrd=0x%08jx", 1205 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1206 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1207 OREAD4(sc, OHCI_INTERRUPT_DISABLE), 0); 1208 DPRINTF(" hcca=0x%08jx percur=0x%08jx ctrlhd=0x%08jx", 1209 OREAD4(sc, OHCI_HCCA), 1210 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1211 OREAD4(sc, OHCI_CONTROL_HEAD_ED), 0); 1212 DPRINTF(" ctrlcur=0x%08jx bulkhd=0x%08jx bulkcur=0x%08jx", 1213 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1214 OREAD4(sc, OHCI_BULK_HEAD_ED), 1215 OREAD4(sc, OHCI_BULK_CURRENT_ED) ,0); 1216 DPRINTF(" done=0x%08jx fmival=0x%08jx fmrem=0x%08jx", 1217 OREAD4(sc, OHCI_DONE_HEAD), 1218 OREAD4(sc, OHCI_FM_INTERVAL), 1219 OREAD4(sc, OHCI_FM_REMAINING), 0); 1220 DPRINTF(" fmnum=0x%08jx perst=0x%08jx lsthrs=0x%08jx", 1221 OREAD4(sc, OHCI_FM_NUMBER), 1222 OREAD4(sc, OHCI_PERIODIC_START), 1223 OREAD4(sc, OHCI_LS_THRESHOLD), 0); 1224 DPRINTF(" desca=0x%08jx descb=0x%08jx stat=0x%08jx", 1225 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1226 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1227 OREAD4(sc, OHCI_RH_STATUS), 0); 1228 DPRINTF(" port1=0x%08jx port2=0x%08jx", 1229 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1230 OREAD4(sc, OHCI_RH_PORT_STATUS(2)), 0, 0); 1231 usb_syncmem(&sc->sc_hccadma, 1232 offsetof(struct ohci_hcca, hcca_frame_number), 1233 sizeof(sc->sc_hcca->hcca_frame_number) + 1234 sizeof(sc->sc_hcca->hcca_done_head), 1235 BUS_DMASYNC_POSTREAD); 1236 DPRINTF(" HCCA: frame_number=0x%04jx done_head=0x%08jx", 1237 O32TOH(sc->sc_hcca->hcca_frame_number), 1238 O32TOH(sc->sc_hcca->hcca_done_head), 0, 0); 1239 } 1240 #endif 1241 1242 Static int ohci_intr1(ohci_softc_t *); 1243 1244 int 1245 ohci_intr(void *p) 1246 { 1247 ohci_softc_t *sc = p; 1248 int ret = 0; 1249 1250 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1251 1252 if (sc == NULL) 1253 return 0; 1254 1255 mutex_spin_enter(&sc->sc_intr_lock); 1256 1257 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1258 goto done; 1259 1260 /* If we get an interrupt while polling, then just ignore it. */ 1261 if (sc->sc_bus.ub_usepolling) { 1262 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1263 /* for level triggered intrs, should do something to ack */ 1264 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1265 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1266 1267 goto done; 1268 } 1269 1270 ret = ohci_intr1(sc); 1271 1272 done: 1273 mutex_spin_exit(&sc->sc_intr_lock); 1274 return ret; 1275 } 1276 1277 Static int 1278 ohci_intr1(ohci_softc_t *sc) 1279 { 1280 uint32_t intrs, eintrs; 1281 1282 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1283 1284 /* In case the interrupt occurs before initialization has completed. */ 1285 if (sc == NULL || sc->sc_hcca == NULL) { 1286 #ifdef DIAGNOSTIC 1287 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1288 #endif 1289 return 0; 1290 } 1291 1292 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1293 1294 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1295 if (!intrs) 1296 return 0; 1297 1298 /* Acknowledge */ 1299 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); 1300 eintrs = intrs & sc->sc_eintrs; 1301 DPRINTFN(7, "sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1302 DPRINTFN(7, "intrs=%#jx(%#jx) eintrs=%#jx(%#jx)", 1303 intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), eintrs, 1304 sc->sc_eintrs); 1305 1306 if (!eintrs) { 1307 return 0; 1308 } 1309 1310 if (eintrs & OHCI_SO) { 1311 sc->sc_overrun_cnt++; 1312 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1313 printf("%s: %u scheduling overruns\n", 1314 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1315 sc->sc_overrun_cnt = 0; 1316 } 1317 /* XXX do what */ 1318 eintrs &= ~OHCI_SO; 1319 } 1320 if (eintrs & OHCI_WDH) { 1321 /* 1322 * We block the interrupt below, and reenable it later from 1323 * ohci_softintr(). 1324 */ 1325 usb_schedsoftintr(&sc->sc_bus); 1326 } 1327 if (eintrs & OHCI_RD) { 1328 DPRINTFN(5, "resume detect sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1329 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1330 /* XXX process resume detect */ 1331 } 1332 if (eintrs & OHCI_UE) { 1333 DPRINTFN(5, "unrecoverable error sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1334 printf("%s: unrecoverable error, controller halted\n", 1335 device_xname(sc->sc_dev)); 1336 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1337 /* XXX what else */ 1338 } 1339 if (eintrs & OHCI_RHSC) { 1340 /* 1341 * We block the interrupt below, and reenable it later from 1342 * a timeout. 1343 */ 1344 softint_schedule(sc->sc_rhsc_si); 1345 } 1346 1347 if (eintrs != 0) { 1348 /* Block unprocessed interrupts. */ 1349 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1350 sc->sc_eintrs &= ~eintrs; 1351 DPRINTF("sc %#jx blocking intrs %#jx", (uintptr_t)sc, 1352 eintrs, 0, 0); 1353 } 1354 1355 return 1; 1356 } 1357 1358 void 1359 ohci_rhsc_enable(void *v_sc) 1360 { 1361 ohci_softc_t *sc = v_sc; 1362 1363 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1364 DPRINTF("sc %#jx", (uintptr_t)sc, 0, 0, 0); 1365 mutex_spin_enter(&sc->sc_intr_lock); 1366 sc->sc_eintrs |= OHCI_RHSC; 1367 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1368 mutex_spin_exit(&sc->sc_intr_lock); 1369 } 1370 1371 #ifdef OHCI_DEBUG 1372 const char *ohci_cc_strs[] = { 1373 "NO_ERROR", 1374 "CRC", 1375 "BIT_STUFFING", 1376 "DATA_TOGGLE_MISMATCH", 1377 "STALL", 1378 "DEVICE_NOT_RESPONDING", 1379 "PID_CHECK_FAILURE", 1380 "UNEXPECTED_PID", 1381 "DATA_OVERRUN", 1382 "DATA_UNDERRUN", 1383 "BUFFER_OVERRUN", 1384 "BUFFER_UNDERRUN", 1385 "reserved", 1386 "reserved", 1387 "NOT_ACCESSED", 1388 "NOT_ACCESSED", 1389 }; 1390 #endif 1391 1392 void 1393 ohci_softintr(void *v) 1394 { 1395 struct usbd_bus *bus = v; 1396 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1397 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1398 ohci_soft_td_t *std, *sdone, *stdnext; 1399 struct usbd_xfer *xfer; 1400 struct ohci_pipe *opipe; 1401 int len, cc; 1402 int i, j, actlen, iframes, uedir; 1403 ohci_physaddr_t done; 1404 1405 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1406 1407 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1408 1409 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1410 sizeof(sc->sc_hcca->hcca_done_head), 1411 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1412 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1413 sc->sc_hcca->hcca_done_head = 0; 1414 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1415 sizeof(sc->sc_hcca->hcca_done_head), 1416 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1417 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1418 sc->sc_eintrs |= OHCI_WDH; 1419 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1420 1421 /* Reverse the done list. */ 1422 for (sdone = NULL, sidone = NULL; done != 0; ) { 1423 std = ohci_hash_find_td(sc, done); 1424 if (std != NULL) { 1425 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1426 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1427 std->dnext = sdone; 1428 done = O32TOH(std->td.td_nexttd); 1429 sdone = std; 1430 DPRINTFN(10, "add TD %#jx", (uintptr_t)std, 0, 0, 0); 1431 continue; 1432 } 1433 sitd = ohci_hash_find_itd(sc, done); 1434 if (sitd != NULL) { 1435 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1436 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1437 sitd->dnext = sidone; 1438 done = O32TOH(sitd->itd.itd_nextitd); 1439 sidone = sitd; 1440 DPRINTFN(5, "add ITD %#jx", (uintptr_t)sitd, 0, 0, 0); 1441 continue; 1442 } 1443 DPRINTFN(10, "addr %#jx not found", (uintptr_t)done, 0, 0, 0); 1444 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1445 (u_long)done); 1446 break; 1447 } 1448 1449 DPRINTFN(10, "sdone=%#jx sidone=%#jx", (uintptr_t)sdone, 1450 (uintptr_t)sidone, 0, 0); 1451 DPRINTFN(10, "--- TD dump start ---", 0, 0, 0, 0); 1452 #ifdef OHCI_DEBUG 1453 if (ohcidebug >= 10) { 1454 for (std = sdone; std; std = std->dnext) 1455 ohci_dump_td(sc, std); 1456 } 1457 #endif 1458 DPRINTFN(10, "--- TD dump end ---", 0, 0, 0, 0); 1459 1460 for (std = sdone; std; std = stdnext) { 1461 xfer = std->xfer; 1462 stdnext = std->dnext; 1463 DPRINTFN(10, "std=%#jx xfer=%#jx hcpriv=%#jx", (uintptr_t)std, 1464 (uintptr_t)xfer, (uintptr_t)(xfer ? xfer->ux_hcpriv : 0), 1465 0); 1466 if (xfer == NULL) { 1467 /* 1468 * xfer == NULL: There seems to be no xfer associated 1469 * with this TD. It is tailp that happened to end up on 1470 * the done queue. 1471 * Shouldn't happen, but some chips are broken(?). 1472 */ 1473 continue; 1474 } 1475 1476 /* 1477 * Try to claim this xfer for completion. If it has 1478 * already completed or aborted, drop it on the floor. 1479 */ 1480 if (!usbd_xfer_trycomplete(xfer)) 1481 continue; 1482 1483 len = std->len; 1484 if (std->td.td_cbp != 0) 1485 len -= O32TOH(std->td.td_be) - 1486 O32TOH(std->td.td_cbp) + 1; 1487 DPRINTFN(10, "len=%jd, flags=%#jx", len, std->flags, 0, 0); 1488 if (std->flags & OHCI_ADD_LEN) 1489 xfer->ux_actlen += len; 1490 1491 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1492 if (cc == OHCI_CC_NO_ERROR) { 1493 ohci_hash_rem_td(sc, std); 1494 if (std->flags & OHCI_CALL_DONE) { 1495 xfer->ux_status = USBD_NORMAL_COMPLETION; 1496 usb_transfer_complete(xfer); 1497 } 1498 } else { 1499 /* 1500 * Endpoint is halted. First unlink all the TDs 1501 * belonging to the failed transfer, and then restart 1502 * the endpoint. 1503 */ 1504 ohci_soft_td_t *p, *n; 1505 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1506 1507 DPRINTFN(10, "error cc=%jd", cc, 0, 0, 0); 1508 1509 /* remove xfer's TDs from the hash */ 1510 for (p = std; p->xfer == xfer; p = n) { 1511 n = p->nexttd; 1512 ohci_hash_rem_td(sc, p); 1513 } 1514 1515 ohci_soft_ed_t *sed = opipe->sed; 1516 1517 /* clear halt and TD chain, preserving toggle carry */ 1518 sed->ed.ed_headp = HTOO32(p->physaddr | 1519 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 1520 usb_syncmem(&sed->dma, 1521 sed->offs + offsetof(ohci_ed_t, ed_headp), 1522 sizeof(sed->ed.ed_headp), 1523 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1524 1525 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1526 1527 if (cc == OHCI_CC_DATA_UNDERRUN) 1528 xfer->ux_status = USBD_NORMAL_COMPLETION; 1529 else if (cc == OHCI_CC_STALL) 1530 xfer->ux_status = USBD_STALLED; 1531 else 1532 xfer->ux_status = USBD_IOERROR; 1533 usb_transfer_complete(xfer); 1534 } 1535 } 1536 DPRINTFN(10, "--- ITD dump start ---", 0, 0, 0, 0); 1537 #ifdef OHCI_DEBUG 1538 if (ohcidebug >= 10) { 1539 for (sitd = sidone; sitd; sitd = sitd->dnext) 1540 ohci_dump_itd(sc, sitd); 1541 } 1542 #endif 1543 DPRINTFN(10, "--- ITD dump end ---", 0, 0, 0, 0); 1544 1545 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1546 xfer = sitd->xfer; 1547 sitdnext = sitd->dnext; 1548 DPRINTFN(1, "sitd=%#jx xfer=%#jx hcpriv=%#jx", (uintptr_t)sitd, 1549 (uintptr_t)xfer, (uintptr_t)(xfer ? xfer->ux_hcpriv : 0), 1550 0); 1551 if (xfer == NULL) 1552 continue; 1553 1554 /* 1555 * Try to claim this xfer for completion. If it has 1556 * already completed or aborted, drop it on the floor. 1557 */ 1558 if (!usbd_xfer_trycomplete(xfer)) 1559 continue; 1560 1561 KASSERT(!sitd->isdone); 1562 #ifdef DIAGNOSTIC 1563 sitd->isdone = true; 1564 #endif 1565 if (sitd->flags & OHCI_CALL_DONE) { 1566 ohci_soft_itd_t *next; 1567 1568 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1569 opipe->isoc.inuse -= xfer->ux_nframes; 1570 uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc-> 1571 bEndpointAddress); 1572 xfer->ux_status = USBD_NORMAL_COMPLETION; 1573 actlen = 0; 1574 for (i = 0, sitd = xfer->ux_hcpriv;; 1575 sitd = next) { 1576 next = sitd->nextitd; 1577 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1578 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1579 xfer->ux_status = USBD_IOERROR; 1580 /* For input, update frlengths with actual */ 1581 /* XXX anything necessary for output? */ 1582 if (uedir == UE_DIR_IN && 1583 xfer->ux_status == USBD_NORMAL_COMPLETION) { 1584 iframes = OHCI_ITD_GET_FC(O32TOH( 1585 sitd->itd.itd_flags)); 1586 for (j = 0; j < iframes; i++, j++) { 1587 len = O16TOH(sitd-> 1588 itd.itd_offset[j]); 1589 if ((OHCI_ITD_PSW_GET_CC(len) & 1590 OHCI_CC_NOT_ACCESSED_MASK) 1591 == OHCI_CC_NOT_ACCESSED) 1592 len = 0; 1593 else 1594 len = OHCI_ITD_PSW_LENGTH(len); 1595 xfer->ux_frlengths[i] = len; 1596 actlen += len; 1597 } 1598 } 1599 if (sitd->flags & OHCI_CALL_DONE) 1600 break; 1601 ohci_hash_rem_itd(sc, sitd); 1602 1603 } 1604 ohci_hash_rem_itd(sc, sitd); 1605 if (uedir == UE_DIR_IN && 1606 xfer->ux_status == USBD_NORMAL_COMPLETION) 1607 xfer->ux_actlen = actlen; 1608 xfer->ux_hcpriv = NULL; 1609 1610 usb_transfer_complete(xfer); 1611 } 1612 } 1613 1614 DPRINTFN(10, "done", 0, 0, 0, 0); 1615 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1616 } 1617 1618 void 1619 ohci_device_ctrl_done(struct usbd_xfer *xfer) 1620 { 1621 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1622 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1623 int len = UGETW(xfer->ux_request.wLength); 1624 int isread = (xfer->ux_request.bmRequestType & UT_READ); 1625 1626 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1627 DPRINTFN(10, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 1628 1629 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1630 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 1631 1632 if (len) 1633 usb_syncmem(&xfer->ux_dmabuf, 0, len, 1634 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1635 usb_syncmem(&opipe->ctrl.reqdma, 0, 1636 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1637 } 1638 1639 void 1640 ohci_device_intr_done(struct usbd_xfer *xfer) 1641 { 1642 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1643 int isread = 1644 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1645 1646 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1647 DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, 1648 xfer->ux_actlen, 0, 0); 1649 1650 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1651 1652 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1653 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1654 } 1655 1656 void 1657 ohci_device_bulk_done(struct usbd_xfer *xfer) 1658 { 1659 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1660 1661 int isread = 1662 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1663 1664 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1665 1666 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1667 DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 1668 0, 0); 1669 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1670 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1671 } 1672 1673 Static void 1674 ohci_rhsc_softint(void *arg) 1675 { 1676 ohci_softc_t *sc = arg; 1677 1678 mutex_enter(&sc->sc_lock); 1679 1680 ohci_rhsc(sc, sc->sc_intrxfer); 1681 1682 /* Do not allow RHSC interrupts > 1 per second */ 1683 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1684 1685 mutex_exit(&sc->sc_lock); 1686 } 1687 1688 void 1689 ohci_rhsc(ohci_softc_t *sc, struct usbd_xfer *xfer) 1690 { 1691 u_char *p; 1692 int i, m; 1693 int hstatus __unused; 1694 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1695 1696 KASSERT(mutex_owned(&sc->sc_lock)); 1697 1698 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1699 DPRINTF("sc=%#jx xfer=%#jx hstatus=0x%08jx", (uintptr_t)sc, 1700 (uintptr_t)xfer, hstatus, 0); 1701 1702 if (xfer == NULL) { 1703 /* Just ignore the change. */ 1704 return; 1705 } 1706 KASSERT(xfer == sc->sc_intrxfer); 1707 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 1708 1709 p = xfer->ux_buf; 1710 m = uimin(sc->sc_noport, xfer->ux_length * 8 - 1); 1711 memset(p, 0, xfer->ux_length); 1712 for (i = 1; i <= m; i++) { 1713 /* Pick out CHANGE bits from the status reg. */ 1714 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1715 p[i/8] |= 1 << (i%8); 1716 } 1717 DPRINTF("change=0x%02jx", *p, 0, 0, 0); 1718 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 1719 xfer->ux_actlen = xfer->ux_length; 1720 xfer->ux_status = USBD_NORMAL_COMPLETION; 1721 1722 usb_transfer_complete(xfer); 1723 } 1724 1725 void 1726 ohci_root_intr_done(struct usbd_xfer *xfer) 1727 { 1728 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1729 1730 KASSERT(mutex_owned(&sc->sc_lock)); 1731 1732 /* Claim the xfer so it doesn't get completed again. */ 1733 KASSERT(sc->sc_intrxfer == xfer); 1734 KASSERT(xfer->ux_status != USBD_IN_PROGRESS); 1735 sc->sc_intrxfer = NULL; 1736 } 1737 1738 void 1739 ohci_poll(struct usbd_bus *bus) 1740 { 1741 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1742 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1743 1744 #ifdef OHCI_DEBUG 1745 static int last; 1746 int new; 1747 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1748 if (new != last) { 1749 DPRINTFN(10, "intrs=0x%04jx", new, 0, 0, 0); 1750 last = new; 1751 } 1752 #endif 1753 sc->sc_eintrs |= OHCI_WDH; 1754 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1755 mutex_spin_enter(&sc->sc_intr_lock); 1756 ohci_intr1(sc); 1757 mutex_spin_exit(&sc->sc_intr_lock); 1758 } 1759 } 1760 1761 /* 1762 * Add an ED to the schedule. Called with USB lock held. 1763 */ 1764 Static void 1765 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1766 { 1767 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1768 DPRINTFN(8, "sed=%#jx head=%#jx", (uintptr_t)sed, (uintptr_t)head, 0, 1769 0); 1770 1771 KASSERT(mutex_owned(&sc->sc_lock)); 1772 1773 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1774 sizeof(head->ed.ed_nexted), 1775 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1776 sed->next = head->next; 1777 sed->ed.ed_nexted = head->ed.ed_nexted; 1778 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1779 sizeof(sed->ed.ed_nexted), 1780 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1781 head->next = sed; 1782 head->ed.ed_nexted = HTOO32(sed->physaddr); 1783 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1784 sizeof(head->ed.ed_nexted), 1785 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1786 } 1787 1788 /* 1789 * Remove an ED from the schedule. Called with USB lock held. 1790 */ 1791 Static void 1792 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1793 { 1794 ohci_soft_ed_t *p; 1795 1796 KASSERT(mutex_owned(&sc->sc_lock)); 1797 1798 /* XXX */ 1799 for (p = head; p != NULL && p->next != sed; p = p->next) 1800 ; 1801 KASSERT(p != NULL); 1802 1803 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1804 sizeof(sed->ed.ed_nexted), 1805 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1806 p->next = sed->next; 1807 p->ed.ed_nexted = sed->ed.ed_nexted; 1808 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1809 sizeof(p->ed.ed_nexted), 1810 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1811 } 1812 1813 /* 1814 * When a transfer is completed the TD is added to the done queue by 1815 * the host controller. This queue is the processed by software. 1816 * Unfortunately the queue contains the physical address of the TD 1817 * and we have no simple way to translate this back to a kernel address. 1818 * To make the translation possible (and fast) we use a hash table of 1819 * TDs currently in the schedule. The physical address is used as the 1820 * hash value. 1821 */ 1822 1823 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1824 /* Called with USB lock held. */ 1825 void 1826 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1827 { 1828 int h = HASH(std->physaddr); 1829 1830 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1831 1832 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1833 } 1834 1835 /* Called with USB lock held. */ 1836 void 1837 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1838 { 1839 1840 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1841 1842 LIST_REMOVE(std, hnext); 1843 } 1844 1845 ohci_soft_td_t * 1846 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1847 { 1848 int h = HASH(a); 1849 ohci_soft_td_t *std; 1850 1851 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1852 std != NULL; 1853 std = LIST_NEXT(std, hnext)) 1854 if (std->physaddr == a) 1855 return std; 1856 return NULL; 1857 } 1858 1859 /* Called with USB lock held. */ 1860 void 1861 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1862 { 1863 int h = HASH(sitd->physaddr); 1864 1865 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1866 1867 KASSERT(mutex_owned(&sc->sc_lock)); 1868 1869 DPRINTFN(10, "sitd=%#jx physaddr=0x%08jx", 1870 (uintptr_t)sitd, (u_long)sitd->physaddr, 0, 0); 1871 1872 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1873 } 1874 1875 /* Called with USB lock held. */ 1876 void 1877 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1878 { 1879 1880 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1881 1882 KASSERT(mutex_owned(&sc->sc_lock)); 1883 1884 DPRINTFN(10, "sitd=%#jx physaddr=0x%08jx", (uintptr_t)sitd, 1885 sitd->physaddr, 0, 0); 1886 1887 LIST_REMOVE(sitd, hnext); 1888 } 1889 1890 ohci_soft_itd_t * 1891 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1892 { 1893 int h = HASH(a); 1894 ohci_soft_itd_t *sitd; 1895 1896 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1897 sitd != NULL; 1898 sitd = LIST_NEXT(sitd, hnext)) 1899 if (sitd->physaddr == a) 1900 return sitd; 1901 return NULL; 1902 } 1903 1904 #ifdef OHCI_DEBUG 1905 void 1906 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 1907 { 1908 for (; std; std = std->nexttd) { 1909 ohci_dump_td(sc, std); 1910 KASSERTMSG(std->nexttd == NULL || std != std->nexttd, 1911 "std %p next %p", std, std->nexttd); 1912 } 1913 } 1914 1915 void 1916 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1917 { 1918 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1919 1920 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1921 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1922 1923 uint32_t flags = O32TOH(std->td.td_flags); 1924 DPRINTF("TD(%#jx) at 0x%08jx:", (uintptr_t)std, std->physaddr, 0, 0); 1925 DPRINTF(" round=%jd DP=%jx DI=%jx T=%jx", 1926 !!(flags & OHCI_TD_R), 1927 __SHIFTOUT(flags, OHCI_TD_DP_MASK), 1928 OHCI_TD_GET_DI(flags), 1929 __SHIFTOUT(flags, OHCI_TD_TOGGLE_MASK)); 1930 DPRINTF(" EC=%jd CC=%jd", OHCI_TD_GET_EC(flags), 1931 OHCI_TD_GET_CC(flags), 0, 0); 1932 DPRINTF(" td_cbp=0x%08jx td_nexttd=0x%08jx td_be=0x%08jx", 1933 (u_long)O32TOH(std->td.td_cbp), 1934 (u_long)O32TOH(std->td.td_nexttd), 1935 (u_long)O32TOH(std->td.td_be), 0); 1936 } 1937 1938 void 1939 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1940 { 1941 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1942 1943 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1944 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1945 1946 uint32_t flags = O32TOH(sitd->itd.itd_flags); 1947 DPRINTF("ITD(%#jx) at 0x%08jx", (uintptr_t)sitd, sitd->physaddr, 0, 0); 1948 DPRINTF(" sf=%jd di=%jd fc=%jd cc=%jd", 1949 OHCI_ITD_GET_SF(flags), OHCI_ITD_GET_DI(flags), 1950 OHCI_ITD_GET_FC(flags), OHCI_ITD_GET_CC(flags)); 1951 DPRINTF(" bp0=0x%08jx next=0x%08jx be=0x%08jx", 1952 O32TOH(sitd->itd.itd_bp0), 1953 O32TOH(sitd->itd.itd_nextitd), 1954 O32TOH(sitd->itd.itd_be), 0); 1955 CTASSERT(OHCI_ITD_NOFFSET == 8); 1956 DPRINTF(" offs[0] = 0x%04jx offs[1] = 0x%04jx " 1957 "offs[2] = 0x%04jx offs[3] = 0x%04jx", 1958 O16TOH(sitd->itd.itd_offset[0]), 1959 O16TOH(sitd->itd.itd_offset[1]), 1960 O16TOH(sitd->itd.itd_offset[2]), 1961 O16TOH(sitd->itd.itd_offset[3])); 1962 DPRINTF(" offs[4] = 0x%04jx offs[5] = 0x%04jx " 1963 "offs[6] = 0x%04jx offs[7] = 0x%04jx", 1964 O16TOH(sitd->itd.itd_offset[4]), 1965 O16TOH(sitd->itd.itd_offset[5]), 1966 O16TOH(sitd->itd.itd_offset[6]), 1967 O16TOH(sitd->itd.itd_offset[7])); 1968 } 1969 1970 void 1971 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1972 { 1973 for (; sitd; sitd = sitd->nextitd) 1974 ohci_dump_itd(sc, sitd); 1975 } 1976 1977 void 1978 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 1979 { 1980 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1981 1982 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 1983 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1984 1985 uint32_t flags = O32TOH(sed->ed.ed_flags); 1986 DPRINTF("ED(%#jx) at 0x%08jx:", (uintptr_t)sed, sed->physaddr, 0, 0); 1987 DPRINTF(" addr=%jd endpt=%jd maxp=%jd", 1988 OHCI_ED_GET_FA(flags), 1989 OHCI_ED_GET_EN(flags), 1990 OHCI_ED_GET_MAXP(flags), 1991 0); 1992 DPRINTF(" dir=%jd speed=%jd skip=%jd iso=%jd", 1993 __SHIFTOUT(flags, OHCI_ED_DIR_MASK), 1994 !!(flags & OHCI_ED_SPEED), 1995 !!(flags & OHCI_ED_SKIP), 1996 !!(flags & OHCI_ED_FORMAT_ISO)); 1997 DPRINTF(" tailp=0x%08jx", (u_long)O32TOH(sed->ed.ed_tailp), 1998 0, 0, 0); 1999 DPRINTF(" headp=0x%08jx nexted=0x%08jx halted=%jd carry=%jd", 2000 O32TOH(sed->ed.ed_headp), O32TOH(sed->ed.ed_nexted), 2001 !!(O32TOH(sed->ed.ed_headp) & OHCI_HALTED), 2002 !!(O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 2003 } 2004 #endif 2005 2006 usbd_status 2007 ohci_open(struct usbd_pipe *pipe) 2008 { 2009 struct usbd_device *dev = pipe->up_dev; 2010 struct usbd_bus *bus = dev->ud_bus; 2011 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2012 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 2013 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2014 uint8_t addr = dev->ud_addr; 2015 uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2016 ohci_soft_ed_t *sed; 2017 ohci_soft_td_t *std; 2018 ohci_soft_itd_t *sitd; 2019 ohci_physaddr_t tdphys; 2020 uint32_t fmt; 2021 usbd_status err = USBD_NOMEM; 2022 int ival; 2023 2024 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2025 DPRINTFN(1, "pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, 2026 addr, ed->bEndpointAddress, bus->ub_rhaddr); 2027 2028 if (sc->sc_dying) { 2029 return USBD_IOERROR; 2030 } 2031 2032 std = NULL; 2033 sed = NULL; 2034 2035 if (addr == bus->ub_rhaddr) { 2036 switch (ed->bEndpointAddress) { 2037 case USB_CONTROL_ENDPOINT: 2038 pipe->up_methods = &roothub_ctrl_methods; 2039 break; 2040 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 2041 pipe->up_methods = &ohci_root_intr_methods; 2042 break; 2043 default: 2044 err = USBD_INVAL; 2045 goto bad; 2046 } 2047 } else { 2048 sed = ohci_alloc_sed(sc); 2049 if (sed == NULL) 2050 goto bad; 2051 opipe->sed = sed; 2052 if (xfertype == UE_ISOCHRONOUS) { 2053 sitd = ohci_alloc_sitd(sc); 2054 if (sitd == NULL) 2055 goto bad; 2056 2057 opipe->tail.itd = sitd; 2058 tdphys = sitd->physaddr; 2059 fmt = OHCI_ED_FORMAT_ISO; 2060 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2061 fmt |= OHCI_ED_DIR_IN; 2062 else 2063 fmt |= OHCI_ED_DIR_OUT; 2064 } else { 2065 std = ohci_alloc_std(sc); 2066 if (std == NULL) 2067 goto bad; 2068 2069 opipe->tail.td = std; 2070 tdphys = std->physaddr; 2071 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2072 } 2073 sed->ed.ed_flags = HTOO32( 2074 OHCI_ED_SET_FA(addr) | 2075 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2076 (dev->ud_speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2077 fmt | 2078 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2079 sed->ed.ed_headp = HTOO32(tdphys | 2080 (pipe->up_endpoint->ue_toggle ? OHCI_TOGGLECARRY : 0)); 2081 sed->ed.ed_tailp = HTOO32(tdphys); 2082 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2083 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2084 2085 switch (xfertype) { 2086 case UE_CONTROL: 2087 pipe->up_methods = &ohci_device_ctrl_methods; 2088 err = usb_allocmem(&sc->sc_bus, 2089 sizeof(usb_device_request_t), 0, 2090 USBMALLOC_COHERENT, &opipe->ctrl.reqdma); 2091 if (err) 2092 goto bad; 2093 mutex_enter(&sc->sc_lock); 2094 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2095 mutex_exit(&sc->sc_lock); 2096 break; 2097 case UE_INTERRUPT: 2098 pipe->up_methods = &ohci_device_intr_methods; 2099 ival = pipe->up_interval; 2100 if (ival == USBD_DEFAULT_INTERVAL) 2101 ival = ed->bInterval; 2102 err = ohci_device_setintr(sc, opipe, ival); 2103 if (err) 2104 goto bad; 2105 break; 2106 case UE_ISOCHRONOUS: 2107 pipe->up_serialise = false; 2108 pipe->up_methods = &ohci_device_isoc_methods; 2109 return ohci_setup_isoc(pipe); 2110 case UE_BULK: 2111 pipe->up_methods = &ohci_device_bulk_methods; 2112 mutex_enter(&sc->sc_lock); 2113 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2114 mutex_exit(&sc->sc_lock); 2115 break; 2116 } 2117 } 2118 2119 return USBD_NORMAL_COMPLETION; 2120 2121 bad: 2122 if (std != NULL) { 2123 ohci_free_std(sc, std); 2124 } 2125 if (sed != NULL) 2126 ohci_free_sed(sc, sed); 2127 return err; 2128 2129 } 2130 2131 /* 2132 * Close a reqular pipe. 2133 * Assumes that there are no pending transactions. 2134 */ 2135 void 2136 ohci_close_pipe(struct usbd_pipe *pipe, ohci_soft_ed_t *head) 2137 { 2138 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2139 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2140 ohci_soft_ed_t *sed = opipe->sed; 2141 2142 KASSERT(mutex_owned(&sc->sc_lock)); 2143 2144 #ifdef DIAGNOSTIC 2145 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2146 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2147 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2148 ohci_soft_td_t *std; 2149 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2150 printf("ohci_close_pipe: pipe not empty sed=%p hd=%#x " 2151 "tl=%#x pipe=%p, std=%p\n", sed, 2152 (int)O32TOH(sed->ed.ed_headp), 2153 (int)O32TOH(sed->ed.ed_tailp), 2154 pipe, std); 2155 #ifdef OHCI_DEBUG 2156 usbd_dump_pipe(&opipe->pipe); 2157 ohci_dump_ed(sc, sed); 2158 if (std) 2159 ohci_dump_td(sc, std); 2160 #endif 2161 usb_delay_ms(&sc->sc_bus, 2); 2162 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2163 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2164 printf("ohci_close_pipe: pipe still not empty\n"); 2165 } 2166 #endif 2167 ohci_rem_ed(sc, sed, head); 2168 /* Make sure the host controller is not touching this ED */ 2169 usb_delay_ms(&sc->sc_bus, 1); 2170 pipe->up_endpoint->ue_toggle = 2171 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2172 ohci_free_sed_locked(sc, opipe->sed); 2173 } 2174 2175 /* 2176 * Arrange for the hardware to tells us that it is not still processing 2177 * the TDs by setting the sKip bit and requesting a SOF interrupt 2178 * 2179 * Once we see the SOF interrupt we can check the transfer TDs/iTDs to see if 2180 * they've been processed and either 2181 * a) if they're unused recover them for later use, or 2182 * b) if they've been used allocate new TD/iTDs to replace those 2183 * used. The softint handler will free the old ones. 2184 */ 2185 void 2186 ohci_abortx(struct usbd_xfer *xfer) 2187 { 2188 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2189 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2190 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2191 ohci_soft_ed_t *sed = opipe->sed; 2192 ohci_soft_td_t *p, *n; 2193 ohci_physaddr_t headp; 2194 int hit; 2195 2196 DPRINTF("xfer=%#jx pipe=%#jx sed=%#jx", (uintptr_t)xfer, 2197 (uintptr_t)opipe, (uintptr_t)sed, 0); 2198 2199 KASSERT(mutex_owned(&sc->sc_lock)); 2200 ASSERT_SLEEPABLE(); 2201 2202 KASSERTMSG((xfer->ux_status == USBD_CANCELLED || 2203 xfer->ux_status == USBD_TIMEOUT), 2204 "bad abort status: %d", xfer->ux_status); 2205 2206 /* 2207 * If we're dying, skip the hardware action and just notify the 2208 * software that we're done. 2209 */ 2210 if (sc->sc_dying) { 2211 DPRINTFN(4, "xfer %#jx dying %ju", (uintptr_t)xfer, 2212 xfer->ux_status, 0, 0); 2213 goto dying; 2214 } 2215 2216 /* 2217 * HC Step 1: Unless the endpoint is already halted, we set the endpoint 2218 * descriptor sKip bit and wait for hardware to complete processing. 2219 * 2220 * This includes ensuring that any TDs of the transfer that got onto 2221 * the done list are also removed. We ensure this by waiting for 2222 * both a WDH and SOF interrupt. 2223 */ 2224 DPRINTFN(1, "stop ed=%#jx", (uintptr_t)sed, 0, 0, 0); 2225 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2226 sizeof(sed->ed.ed_flags), 2227 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2228 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2229 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2230 sizeof(sed->ed.ed_flags), 2231 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2232 2233 /* 2234 * HC Step 2: Wait until we know hardware has finished any possible 2235 * use of the xfer. 2236 */ 2237 /* Hardware finishes in 1ms */ 2238 usb_delay_ms_locked(opipe->pipe.up_dev->ud_bus, 20, &sc->sc_lock); 2239 2240 /* 2241 * HC Step 3: Remove any vestiges of the xfer from the hardware. 2242 * The complication here is that the hardware may have executed 2243 * beyond the xfer we're trying to abort. So as we're scanning 2244 * the TDs of this xfer we check if the hardware points to 2245 * any of them. 2246 */ 2247 p = xfer->ux_hcpriv; 2248 KASSERT(p); 2249 2250 #ifdef OHCI_DEBUG 2251 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2252 2253 if (ohcidebug >= 2) { 2254 DPRINTF("sed:", 0, 0, 0, 0); 2255 ohci_dump_ed(sc, sed); 2256 ohci_dump_tds(sc, p); 2257 } 2258 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2259 #endif 2260 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2261 hit = 0; 2262 for (; p->xfer == xfer; p = n) { 2263 hit |= headp == p->physaddr; 2264 n = p->nexttd; 2265 ohci_hash_rem_td(sc, p); 2266 } 2267 /* Zap headp register if hardware pointed inside the xfer. */ 2268 if (hit) { 2269 DPRINTFN(1, "set hd=0x%08jx, tl=0x%08jx", (int)p->physaddr, 2270 (int)O32TOH(sed->ed.ed_tailp), 0, 0); 2271 /* unlink TDs, preserving toggle carry */ 2272 sed->ed.ed_headp = HTOO32(p->physaddr | 2273 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 2274 usb_syncmem(&sed->dma, 2275 sed->offs + offsetof(ohci_ed_t, ed_headp), 2276 sizeof(sed->ed.ed_headp), 2277 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2278 } else { 2279 DPRINTFN(1, "no hit", 0, 0, 0, 0); 2280 } 2281 2282 /* 2283 * HC Step 4: Turn on hardware again. 2284 */ 2285 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2286 sizeof(sed->ed.ed_flags), 2287 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2288 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2289 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2290 sizeof(sed->ed.ed_flags), 2291 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2292 2293 /* 2294 * Final step: Notify completion to waiting xfers. 2295 */ 2296 dying: 2297 usb_transfer_complete(xfer); 2298 DPRINTFN(14, "end", 0, 0, 0, 0); 2299 2300 KASSERT(mutex_owned(&sc->sc_lock)); 2301 } 2302 2303 /* 2304 * Data structures and routines to emulate the root hub. 2305 */ 2306 Static int 2307 ohci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2308 void *buf, int buflen) 2309 { 2310 ohci_softc_t *sc = OHCI_BUS2SC(bus); 2311 usb_port_status_t ps; 2312 uint16_t len, value, index; 2313 int l, totlen = 0; 2314 int port, i; 2315 uint32_t v; 2316 2317 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2318 2319 if (sc->sc_dying) 2320 return -1; 2321 2322 DPRINTFN(4, "type=0x%02jx request=%02jx", req->bmRequestType, 2323 req->bRequest, 0, 0); 2324 2325 len = UGETW(req->wLength); 2326 value = UGETW(req->wValue); 2327 index = UGETW(req->wIndex); 2328 2329 #define C(x,y) ((x) | ((y) << 8)) 2330 switch (C(req->bRequest, req->bmRequestType)) { 2331 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2332 DPRINTFN(8, "wValue=0x%04jx", value, 0, 0, 0); 2333 if (len == 0) 2334 break; 2335 switch (value) { 2336 #define sd ((usb_string_descriptor_t *)buf) 2337 case C(2, UDESC_STRING): 2338 /* Product */ 2339 totlen = usb_makestrdesc(sd, len, "OHCI root hub"); 2340 break; 2341 #undef sd 2342 default: 2343 /* default from usbroothub */ 2344 return buflen; 2345 } 2346 break; 2347 2348 /* Hub requests */ 2349 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2350 break; 2351 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2352 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", 2353 index, value, 0, 0); 2354 if (index < 1 || index > sc->sc_noport) { 2355 return -1; 2356 } 2357 port = OHCI_RH_PORT_STATUS(index); 2358 switch(value) { 2359 case UHF_PORT_ENABLE: 2360 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2361 break; 2362 case UHF_PORT_SUSPEND: 2363 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2364 break; 2365 case UHF_PORT_POWER: 2366 /* Yes, writing to the LOW_SPEED bit clears power. */ 2367 OWRITE4(sc, port, UPS_LOW_SPEED); 2368 break; 2369 case UHF_C_PORT_CONNECTION: 2370 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2371 break; 2372 case UHF_C_PORT_ENABLE: 2373 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2374 break; 2375 case UHF_C_PORT_SUSPEND: 2376 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2377 break; 2378 case UHF_C_PORT_OVER_CURRENT: 2379 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2380 break; 2381 case UHF_C_PORT_RESET: 2382 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2383 break; 2384 default: 2385 return -1; 2386 } 2387 switch(value) { 2388 case UHF_C_PORT_CONNECTION: 2389 case UHF_C_PORT_ENABLE: 2390 case UHF_C_PORT_SUSPEND: 2391 case UHF_C_PORT_OVER_CURRENT: 2392 case UHF_C_PORT_RESET: 2393 /* Enable RHSC interrupt if condition is cleared. */ 2394 if ((OREAD4(sc, port) >> 16) == 0) 2395 ohci_rhsc_enable(sc); 2396 break; 2397 default: 2398 break; 2399 } 2400 break; 2401 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2402 if (len == 0) 2403 break; 2404 if ((value & 0xff) != 0) { 2405 return -1; 2406 } 2407 usb_hub_descriptor_t hubd; 2408 2409 totlen = uimin(buflen, sizeof(hubd)); 2410 memcpy(&hubd, buf, totlen); 2411 2412 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2413 hubd.bNbrPorts = sc->sc_noport; 2414 USETW(hubd.wHubCharacteristics, 2415 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2416 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2417 /* XXX overcurrent */ 2418 ); 2419 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2420 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2421 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2422 hubd.DeviceRemovable[i++] = (uint8_t)v; 2423 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2424 totlen = uimin(totlen, hubd.bDescLength); 2425 memcpy(buf, &hubd, totlen); 2426 break; 2427 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2428 if (len != 4) { 2429 return -1; 2430 } 2431 memset(buf, 0, len); /* ? XXX */ 2432 totlen = len; 2433 break; 2434 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2435 DPRINTFN(8, "get port status i=%jd", index, 0, 0, 0); 2436 if (index < 1 || index > sc->sc_noport) { 2437 return -1; 2438 } 2439 if (len != 4) { 2440 return -1; 2441 } 2442 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2443 DPRINTFN(8, "port status=0x%04jx", v, 0, 0, 0); 2444 USETW(ps.wPortStatus, v); 2445 USETW(ps.wPortChange, v >> 16); 2446 totlen = uimin(len, sizeof(ps)); 2447 memcpy(buf, &ps, totlen); 2448 break; 2449 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2450 return -1; 2451 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2452 break; 2453 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2454 if (index < 1 || index > sc->sc_noport) { 2455 return -1; 2456 } 2457 port = OHCI_RH_PORT_STATUS(index); 2458 switch(value) { 2459 case UHF_PORT_ENABLE: 2460 OWRITE4(sc, port, UPS_PORT_ENABLED); 2461 break; 2462 case UHF_PORT_SUSPEND: 2463 OWRITE4(sc, port, UPS_SUSPEND); 2464 break; 2465 case UHF_PORT_RESET: 2466 DPRINTFN(5, "reset port %jd", index, 0, 0, 0); 2467 OWRITE4(sc, port, UPS_RESET); 2468 for (i = 0; i < 5; i++) { 2469 usb_delay_ms(&sc->sc_bus, 2470 USB_PORT_ROOT_RESET_DELAY); 2471 if (sc->sc_dying) { 2472 return -1; 2473 } 2474 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2475 break; 2476 } 2477 DPRINTFN(8, "port %jd reset, status = 0x%04jx", index, 2478 OREAD4(sc, port), 0, 0); 2479 break; 2480 case UHF_PORT_POWER: 2481 DPRINTFN(2, "set port power %jd", index, 0, 0, 0); 2482 OWRITE4(sc, port, UPS_PORT_POWER); 2483 break; 2484 default: 2485 return -1; 2486 } 2487 break; 2488 default: 2489 /* default from usbroothub */ 2490 return buflen; 2491 } 2492 2493 return totlen; 2494 } 2495 2496 Static usbd_status 2497 ohci_root_intr_transfer(struct usbd_xfer *xfer) 2498 { 2499 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2500 usbd_status err; 2501 2502 /* Insert last in queue. */ 2503 mutex_enter(&sc->sc_lock); 2504 err = usb_insert_transfer(xfer); 2505 mutex_exit(&sc->sc_lock); 2506 if (err) 2507 return err; 2508 2509 /* Pipe isn't running, start first */ 2510 return ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2511 } 2512 2513 Static usbd_status 2514 ohci_root_intr_start(struct usbd_xfer *xfer) 2515 { 2516 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2517 const bool polling = sc->sc_bus.ub_usepolling; 2518 2519 if (sc->sc_dying) 2520 return USBD_IOERROR; 2521 2522 if (!polling) 2523 mutex_enter(&sc->sc_lock); 2524 KASSERT(sc->sc_intrxfer == NULL); 2525 sc->sc_intrxfer = xfer; 2526 xfer->ux_status = USBD_IN_PROGRESS; 2527 if (!polling) 2528 mutex_exit(&sc->sc_lock); 2529 2530 return USBD_IN_PROGRESS; 2531 } 2532 2533 /* Abort a root interrupt request. */ 2534 Static void 2535 ohci_root_intr_abort(struct usbd_xfer *xfer) 2536 { 2537 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2538 2539 KASSERT(mutex_owned(&sc->sc_lock)); 2540 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2541 2542 /* If xfer has already completed, nothing to do here. */ 2543 if (sc->sc_intrxfer == NULL) 2544 return; 2545 2546 /* 2547 * Otherwise, sc->sc_intrxfer had better be this transfer. 2548 * Cancel it. 2549 */ 2550 KASSERT(sc->sc_intrxfer == xfer); 2551 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 2552 xfer->ux_status = USBD_CANCELLED; 2553 usb_transfer_complete(xfer); 2554 } 2555 2556 /* Close the root pipe. */ 2557 Static void 2558 ohci_root_intr_close(struct usbd_pipe *pipe) 2559 { 2560 ohci_softc_t *sc __diagused = OHCI_PIPE2SC(pipe); 2561 2562 KASSERT(mutex_owned(&sc->sc_lock)); 2563 2564 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2565 2566 /* 2567 * Caller must guarantee the xfer has completed first, by 2568 * closing the pipe only after normal completion or an abort. 2569 */ 2570 KASSERT(sc->sc_intrxfer == NULL); 2571 } 2572 2573 /************************/ 2574 2575 int 2576 ohci_device_ctrl_init(struct usbd_xfer *xfer) 2577 { 2578 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2579 usb_device_request_t *req = &xfer->ux_request; 2580 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2581 ohci_soft_td_t *stat, *setup; 2582 int isread = req->bmRequestType & UT_READ; 2583 int len = xfer->ux_bufsize; 2584 int err = ENOMEM; 2585 2586 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2587 2588 setup = ohci_alloc_std(sc); 2589 if (setup == NULL) { 2590 goto bad1; 2591 } 2592 stat = ohci_alloc_std(sc); 2593 if (stat == NULL) { 2594 goto bad2; 2595 } 2596 2597 ox->ox_setup = setup; 2598 ox->ox_stat = stat; 2599 ox->ox_nstd = 0; 2600 2601 /* Set up data transaction */ 2602 if (len != 0) { 2603 err = ohci_alloc_std_chain(sc, xfer, len, isread); 2604 if (err) { 2605 goto bad3; 2606 } 2607 } 2608 return 0; 2609 2610 bad3: 2611 ohci_free_std(sc, stat); 2612 bad2: 2613 ohci_free_std(sc, setup); 2614 bad1: 2615 return err; 2616 } 2617 2618 void 2619 ohci_device_ctrl_fini(struct usbd_xfer *xfer) 2620 { 2621 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2622 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2623 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2624 2625 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2626 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 2627 2628 mutex_enter(&sc->sc_lock); 2629 if (ox->ox_setup != opipe->tail.td) { 2630 ohci_free_std_locked(sc, ox->ox_setup); 2631 } 2632 for (size_t i = 0; i < ox->ox_nstd; i++) { 2633 ohci_soft_td_t *std = ox->ox_stds[i]; 2634 if (std == NULL) 2635 break; 2636 ohci_free_std_locked(sc, std); 2637 } 2638 ohci_free_std_locked(sc, ox->ox_stat); 2639 mutex_exit(&sc->sc_lock); 2640 2641 if (ox->ox_nstd) { 2642 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 2643 kmem_free(ox->ox_stds, sz); 2644 } 2645 } 2646 2647 Static usbd_status 2648 ohci_device_ctrl_transfer(struct usbd_xfer *xfer) 2649 { 2650 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2651 usbd_status err; 2652 2653 /* Insert last in queue. */ 2654 mutex_enter(&sc->sc_lock); 2655 err = usb_insert_transfer(xfer); 2656 mutex_exit(&sc->sc_lock); 2657 if (err) 2658 return err; 2659 2660 /* Pipe isn't running, start first */ 2661 return ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2662 } 2663 2664 Static usbd_status 2665 ohci_device_ctrl_start(struct usbd_xfer *xfer) 2666 { 2667 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2668 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2669 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2670 usb_device_request_t *req = &xfer->ux_request; 2671 struct usbd_device *dev __diagused = opipe->pipe.up_dev; 2672 ohci_soft_td_t *setup, *stat, *next, *tail; 2673 ohci_soft_ed_t *sed; 2674 int isread; 2675 int len; 2676 const bool polling = sc->sc_bus.ub_usepolling; 2677 2678 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2679 2680 if (sc->sc_dying) 2681 return USBD_IOERROR; 2682 2683 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2684 2685 isread = req->bmRequestType & UT_READ; 2686 len = UGETW(req->wLength); 2687 2688 DPRINTF("xfer=%#jx len=%jd, addr=%jd, endpt=%jd", (uintptr_t)xfer, len, 2689 dev->ud_addr, opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress); 2690 DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx", 2691 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2692 UGETW(req->wIndex)); 2693 2694 /* Need to take lock here for pipe->tail.td */ 2695 if (!polling) 2696 mutex_enter(&sc->sc_lock); 2697 2698 /* 2699 * Use the pipe "tail" TD as our first and loan our first TD to the 2700 * next transfer 2701 */ 2702 setup = opipe->tail.td; 2703 opipe->tail.td = ox->ox_setup; 2704 ox->ox_setup = setup; 2705 2706 stat = ox->ox_stat; 2707 2708 /* point at sentinel */ 2709 tail = opipe->tail.td; 2710 sed = opipe->sed; 2711 2712 KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->ud_addr, 2713 "address ED %d pipe %d\n", 2714 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->ud_addr); 2715 KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) == 2716 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 2717 "MPL ED %d pipe %d\n", 2718 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), 2719 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 2720 2721 /* next will point to data if len != 0 */ 2722 next = stat; 2723 2724 /* Set up data transaction */ 2725 if (len != 0) { 2726 ohci_soft_td_t *std; 2727 ohci_soft_td_t *end; 2728 2729 next = ox->ox_stds[0]; 2730 ohci_reset_std_chain(sc, xfer, len, isread, next, &end); 2731 2732 end->td.td_nexttd = HTOO32(stat->physaddr); 2733 end->nexttd = stat; 2734 2735 usb_syncmem(&end->dma, end->offs, sizeof(end->td), 2736 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2737 2738 usb_syncmem(&xfer->ux_dmabuf, 0, len, 2739 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2740 std = ox->ox_stds[0]; 2741 /* Start toggle at 1 and then use the carried toggle. */ 2742 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 2743 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 2744 usb_syncmem(&std->dma, 2745 std->offs + offsetof(ohci_td_t, td_flags), 2746 sizeof(std->td.td_flags), 2747 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2748 } 2749 2750 DPRINTFN(8, "setup %#jx data %#jx stat %#jx tail %#jx", 2751 (uintptr_t)setup, 2752 (uintptr_t)(len != 0 ? ox->ox_stds[0] : NULL), (uintptr_t)stat, 2753 (uintptr_t)tail); 2754 KASSERT(opipe->tail.td == tail); 2755 2756 memcpy(KERNADDR(&opipe->ctrl.reqdma, 0), req, sizeof(*req)); 2757 usb_syncmem(&opipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2758 2759 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 2760 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 2761 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->ctrl.reqdma, 0)); 2762 setup->td.td_nexttd = HTOO32(next->physaddr); 2763 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof(*req) - 1); 2764 setup->nexttd = next; 2765 setup->len = 0; 2766 setup->xfer = xfer; 2767 setup->flags = 0; 2768 ohci_hash_add_td(sc, setup); 2769 2770 xfer->ux_hcpriv = setup; 2771 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2772 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2773 2774 stat->td.td_flags = HTOO32( 2775 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 2776 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 2777 stat->td.td_cbp = 0; 2778 stat->td.td_nexttd = HTOO32(tail->physaddr); 2779 stat->td.td_be = 0; 2780 stat->nexttd = tail; 2781 stat->flags = OHCI_CALL_DONE; 2782 stat->len = 0; 2783 stat->xfer = xfer; 2784 ohci_hash_add_td(sc, stat); 2785 2786 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2787 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2788 2789 memset(&tail->td, 0, sizeof(tail->td)); 2790 tail->nexttd = NULL; 2791 tail->xfer = NULL; 2792 2793 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 2794 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2795 2796 #ifdef OHCI_DEBUG 2797 USBHIST_LOGN(ohcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2798 if (ohcidebug >= 5) { 2799 ohci_dump_ed(sc, sed); 2800 ohci_dump_tds(sc, setup); 2801 } 2802 USBHIST_LOGN(ohcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2803 #endif 2804 2805 /* Insert ED in schedule */ 2806 sed->ed.ed_tailp = HTOO32(tail->physaddr); 2807 usb_syncmem(&sed->dma, 2808 sed->offs + offsetof(ohci_ed_t, ed_tailp), 2809 sizeof(sed->ed.ed_tailp), 2810 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2811 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2812 usbd_xfer_schedule_timeout(xfer); 2813 2814 DPRINTF("done", 0, 0, 0, 0); 2815 2816 xfer->ux_status = USBD_IN_PROGRESS; 2817 if (!polling) 2818 mutex_exit(&sc->sc_lock); 2819 2820 return USBD_IN_PROGRESS; 2821 } 2822 2823 /* Abort a device control request. */ 2824 Static void 2825 ohci_device_ctrl_abort(struct usbd_xfer *xfer) 2826 { 2827 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 2828 2829 KASSERT(mutex_owned(&sc->sc_lock)); 2830 2831 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2832 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 2833 usbd_xfer_abort(xfer); 2834 } 2835 2836 /* Close a device control pipe. */ 2837 Static void 2838 ohci_device_ctrl_close(struct usbd_pipe *pipe) 2839 { 2840 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2841 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2842 2843 KASSERT(mutex_owned(&sc->sc_lock)); 2844 2845 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2846 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 2847 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2848 ohci_free_std_locked(sc, opipe->tail.td); 2849 2850 usb_freemem(&sc->sc_bus, &opipe->ctrl.reqdma); 2851 } 2852 2853 /************************/ 2854 2855 Static void 2856 ohci_device_clear_toggle(struct usbd_pipe *pipe) 2857 { 2858 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2859 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2860 2861 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2862 } 2863 2864 Static void 2865 ohci_noop(struct usbd_pipe *pipe) 2866 { 2867 } 2868 2869 Static int 2870 ohci_device_bulk_init(struct usbd_xfer *xfer) 2871 { 2872 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2873 int len = xfer->ux_bufsize; 2874 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2875 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2876 int err; 2877 2878 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2879 2880 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2881 2882 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 2883 len, isread, xfer->ux_flags); 2884 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 2885 2886 /* Allocate a chain of new TDs (including a new tail). */ 2887 err = ohci_alloc_std_chain(sc, xfer, len, isread); 2888 if (err) 2889 return err; 2890 2891 return 0; 2892 } 2893 2894 Static void 2895 ohci_device_bulk_fini(struct usbd_xfer *xfer) 2896 { 2897 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2898 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2899 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2900 2901 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2902 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 2903 2904 mutex_enter(&sc->sc_lock); 2905 for (size_t i = 0; i < ox->ox_nstd; i++) { 2906 ohci_soft_td_t *std = ox->ox_stds[i]; 2907 if (std == NULL) 2908 break; 2909 if (std != opipe->tail.td) 2910 ohci_free_std_locked(sc, std); 2911 } 2912 mutex_exit(&sc->sc_lock); 2913 2914 if (ox->ox_nstd) { 2915 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 2916 kmem_free(ox->ox_stds, sz); 2917 } 2918 } 2919 2920 Static usbd_status 2921 ohci_device_bulk_transfer(struct usbd_xfer *xfer) 2922 { 2923 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2924 usbd_status err; 2925 2926 /* Insert last in queue. */ 2927 mutex_enter(&sc->sc_lock); 2928 err = usb_insert_transfer(xfer); 2929 mutex_exit(&sc->sc_lock); 2930 if (err) 2931 return err; 2932 2933 /* Pipe isn't running, start first */ 2934 return ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2935 } 2936 2937 Static usbd_status 2938 ohci_device_bulk_start(struct usbd_xfer *xfer) 2939 { 2940 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2941 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2942 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2943 ohci_soft_td_t *last; 2944 ohci_soft_td_t *data, *tail, *tdp; 2945 ohci_soft_ed_t *sed; 2946 int len, isread, endpt; 2947 const bool polling = sc->sc_bus.ub_usepolling; 2948 2949 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2950 2951 if (sc->sc_dying) 2952 return USBD_IOERROR; 2953 2954 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2955 2956 len = xfer->ux_length; 2957 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2958 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2959 sed = opipe->sed; 2960 2961 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 2962 len, isread, xfer->ux_flags); 2963 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 2964 2965 if (!polling) 2966 mutex_enter(&sc->sc_lock); 2967 2968 /* 2969 * Use the pipe "tail" TD as our first and loan our first TD to the 2970 * next transfer 2971 */ 2972 data = opipe->tail.td; 2973 opipe->tail.td = ox->ox_stds[0]; 2974 ox->ox_stds[0] = data; 2975 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 2976 2977 /* point at sentinel */ 2978 tail = opipe->tail.td; 2979 memset(&tail->td, 0, sizeof(tail->td)); 2980 tail->nexttd = NULL; 2981 tail->xfer = NULL; 2982 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 2983 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2984 xfer->ux_hcpriv = data; 2985 2986 DPRINTFN(8, "xfer %#jx data %#jx tail %#jx", (uintptr_t)xfer, 2987 (uintptr_t)ox->ox_stds[0], (uintptr_t)tail, 0); 2988 KASSERT(opipe->tail.td == tail); 2989 2990 /* We want interrupt at the end of the transfer. */ 2991 last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 2992 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 2993 last->td.td_nexttd = HTOO32(tail->physaddr); 2994 last->nexttd = tail; 2995 last->flags |= OHCI_CALL_DONE; 2996 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 2997 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2998 2999 DPRINTFN(4, "ed_flags=0x%08jx td_flags=0x%08jx " 3000 "td_cbp=0x%08jx td_be=0x%08jx", 3001 (int)O32TOH(sed->ed.ed_flags), 3002 (int)O32TOH(data->td.td_flags), 3003 (int)O32TOH(data->td.td_cbp), 3004 (int)O32TOH(data->td.td_be)); 3005 3006 #ifdef OHCI_DEBUG 3007 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3008 if (ohcidebug >= 5) { 3009 ohci_dump_ed(sc, sed); 3010 ohci_dump_tds(sc, data); 3011 } 3012 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3013 #endif 3014 3015 /* Insert ED in schedule */ 3016 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3017 KASSERT(tdp->xfer == xfer); 3018 } 3019 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3020 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3021 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3022 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3023 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3024 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3025 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3026 usbd_xfer_schedule_timeout(xfer); 3027 xfer->ux_status = USBD_IN_PROGRESS; 3028 if (!polling) 3029 mutex_exit(&sc->sc_lock); 3030 3031 return USBD_IN_PROGRESS; 3032 } 3033 3034 Static void 3035 ohci_device_bulk_abort(struct usbd_xfer *xfer) 3036 { 3037 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3038 3039 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3040 3041 KASSERT(mutex_owned(&sc->sc_lock)); 3042 3043 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3044 usbd_xfer_abort(xfer); 3045 } 3046 3047 /* 3048 * Close a device bulk pipe. 3049 */ 3050 Static void 3051 ohci_device_bulk_close(struct usbd_pipe *pipe) 3052 { 3053 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3054 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3055 3056 KASSERT(mutex_owned(&sc->sc_lock)); 3057 3058 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3059 3060 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3061 ohci_close_pipe(pipe, sc->sc_bulk_head); 3062 ohci_free_std_locked(sc, opipe->tail.td); 3063 } 3064 3065 /************************/ 3066 3067 Static int 3068 ohci_device_intr_init(struct usbd_xfer *xfer) 3069 { 3070 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3071 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3072 int len = xfer->ux_bufsize; 3073 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3074 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3075 int err; 3076 3077 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3078 3079 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3080 KASSERT(len != 0); 3081 3082 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 3083 len, isread, xfer->ux_flags); 3084 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 3085 3086 ox->ox_nstd = 0; 3087 3088 err = ohci_alloc_std_chain(sc, xfer, len, isread); 3089 if (err) { 3090 return err; 3091 } 3092 3093 return 0; 3094 } 3095 3096 Static void 3097 ohci_device_intr_fini(struct usbd_xfer *xfer) 3098 { 3099 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3100 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3101 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3102 3103 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3104 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 3105 3106 mutex_enter(&sc->sc_lock); 3107 for (size_t i = 0; i < ox->ox_nstd; i++) { 3108 ohci_soft_td_t *std = ox->ox_stds[i]; 3109 if (std != NULL) 3110 break; 3111 if (std != opipe->tail.td) 3112 ohci_free_std_locked(sc, std); 3113 } 3114 mutex_exit(&sc->sc_lock); 3115 3116 if (ox->ox_nstd) { 3117 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 3118 kmem_free(ox->ox_stds, sz); 3119 } 3120 } 3121 3122 Static usbd_status 3123 ohci_device_intr_transfer(struct usbd_xfer *xfer) 3124 { 3125 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3126 usbd_status err; 3127 3128 /* Insert last in queue. */ 3129 mutex_enter(&sc->sc_lock); 3130 err = usb_insert_transfer(xfer); 3131 mutex_exit(&sc->sc_lock); 3132 if (err) 3133 return err; 3134 3135 /* Pipe isn't running, start first */ 3136 return ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3137 } 3138 3139 Static usbd_status 3140 ohci_device_intr_start(struct usbd_xfer *xfer) 3141 { 3142 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3143 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3144 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3145 ohci_soft_ed_t *sed = opipe->sed; 3146 ohci_soft_td_t *data, *last, *tail; 3147 int len, isread, endpt; 3148 const bool polling = sc->sc_bus.ub_usepolling; 3149 3150 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3151 3152 if (sc->sc_dying) 3153 return USBD_IOERROR; 3154 3155 DPRINTFN(3, "xfer=%#jx len=%jd flags=%jd priv=%#jx", (uintptr_t)xfer, 3156 xfer->ux_length, xfer->ux_flags, (uintptr_t)xfer->ux_priv); 3157 3158 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3159 3160 len = xfer->ux_length; 3161 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3162 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3163 3164 if (!polling) 3165 mutex_enter(&sc->sc_lock); 3166 3167 /* 3168 * Use the pipe "tail" TD as our first and loan our first TD to the 3169 * next transfer. 3170 */ 3171 data = opipe->tail.td; 3172 opipe->tail.td = ox->ox_stds[0]; 3173 ox->ox_stds[0] = data; 3174 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3175 3176 /* point at sentinel */ 3177 tail = opipe->tail.td; 3178 memset(&tail->td, 0, sizeof(tail->td)); 3179 tail->nexttd = NULL; 3180 tail->xfer = NULL; 3181 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3182 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3183 xfer->ux_hcpriv = data; 3184 3185 DPRINTFN(8, "data %#jx tail %#jx", (uintptr_t)ox->ox_stds[0], 3186 (uintptr_t)tail, 0, 0); 3187 KASSERT(opipe->tail.td == tail); 3188 3189 /* We want interrupt at the end of the transfer. */ 3190 last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3191 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3192 3193 last->td.td_nexttd = HTOO32(tail->physaddr); 3194 last->nexttd = tail; 3195 last->flags |= OHCI_CALL_DONE; 3196 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3197 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3198 3199 #ifdef OHCI_DEBUG 3200 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3201 if (ohcidebug >= 5) { 3202 ohci_dump_ed(sc, sed); 3203 ohci_dump_tds(sc, data); 3204 } 3205 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3206 #endif 3207 3208 /* Insert ED in schedule */ 3209 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3210 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3211 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3212 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3213 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3214 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3215 3216 xfer->ux_status = USBD_IN_PROGRESS; 3217 if (!polling) 3218 mutex_exit(&sc->sc_lock); 3219 3220 return USBD_IN_PROGRESS; 3221 } 3222 3223 /* Abort a device interrupt request. */ 3224 Static void 3225 ohci_device_intr_abort(struct usbd_xfer *xfer) 3226 { 3227 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3228 3229 KASSERT(mutex_owned(&sc->sc_lock)); 3230 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3231 3232 usbd_xfer_abort(xfer); 3233 } 3234 3235 /* Close a device interrupt pipe. */ 3236 Static void 3237 ohci_device_intr_close(struct usbd_pipe *pipe) 3238 { 3239 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3240 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3241 int nslots = opipe->intr.nslots; 3242 int pos = opipe->intr.pos; 3243 int j; 3244 ohci_soft_ed_t *p, *sed = opipe->sed; 3245 3246 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3247 3248 KASSERT(mutex_owned(&sc->sc_lock)); 3249 3250 DPRINTFN(1, "pipe=%#jx nslots=%jd pos=%jd", (uintptr_t)pipe, nslots, 3251 pos, 0); 3252 usb_syncmem(&sed->dma, sed->offs, 3253 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3254 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3255 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3256 sizeof(sed->ed.ed_flags), 3257 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3258 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3259 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3260 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3261 3262 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3263 continue; 3264 KASSERT(p); 3265 p->next = sed->next; 3266 p->ed.ed_nexted = sed->ed.ed_nexted; 3267 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3268 sizeof(p->ed.ed_nexted), 3269 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3270 3271 for (j = 0; j < nslots; j++) 3272 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3273 3274 ohci_free_std_locked(sc, opipe->tail.td); 3275 ohci_free_sed_locked(sc, opipe->sed); 3276 } 3277 3278 Static usbd_status 3279 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3280 { 3281 int i, j, best; 3282 u_int npoll, slow, shigh, nslots; 3283 u_int bestbw, bw; 3284 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3285 3286 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3287 3288 DPRINTFN(2, "pipe=%#jx", (uintptr_t)opipe, 0, 0, 0); 3289 if (ival == 0) { 3290 printf("ohci_setintr: 0 interval\n"); 3291 return USBD_INVAL; 3292 } 3293 3294 npoll = OHCI_NO_INTRS; 3295 while (npoll > ival) 3296 npoll /= 2; 3297 DPRINTFN(2, "ival=%jd npoll=%jd", ival, npoll, 0, 0); 3298 3299 /* 3300 * We now know which level in the tree the ED must go into. 3301 * Figure out which slot has most bandwidth left over. 3302 * Slots to examine: 3303 * npoll 3304 * 1 0 3305 * 2 1 2 3306 * 4 3 4 5 6 3307 * 8 7 8 9 10 11 12 13 14 3308 * N (N-1) .. (N-1+N-1) 3309 */ 3310 slow = npoll-1; 3311 shigh = slow + npoll; 3312 nslots = OHCI_NO_INTRS / npoll; 3313 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3314 bw = 0; 3315 for (j = 0; j < nslots; j++) 3316 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3317 if (bw < bestbw) { 3318 best = i; 3319 bestbw = bw; 3320 } 3321 } 3322 DPRINTFN(2, "best=%jd(%jd..%jd) bestbw=%jd", best, slow, shigh, bestbw); 3323 3324 mutex_enter(&sc->sc_lock); 3325 hsed = sc->sc_eds[best]; 3326 sed->next = hsed->next; 3327 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3328 sizeof(hsed->ed.ed_flags), 3329 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3330 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3331 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3332 sizeof(sed->ed.ed_flags), 3333 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3334 hsed->next = sed; 3335 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3336 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3337 sizeof(hsed->ed.ed_flags), 3338 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3339 mutex_exit(&sc->sc_lock); 3340 3341 for (j = 0; j < nslots; j++) 3342 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3343 opipe->intr.nslots = nslots; 3344 opipe->intr.pos = best; 3345 3346 DPRINTFN(5, "returns %#jx", (uintptr_t)opipe, 0, 0, 0); 3347 return USBD_NORMAL_COMPLETION; 3348 } 3349 3350 /***********************/ 3351 3352 Static int 3353 ohci_device_isoc_init(struct usbd_xfer *xfer) 3354 { 3355 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3356 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3357 ohci_soft_itd_t *sitd; 3358 size_t i; 3359 int err; 3360 3361 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3362 3363 DPRINTFN(1, "xfer %#jx len %jd flags %jd", (uintptr_t)xfer, 3364 xfer->ux_length, xfer->ux_flags, 0); 3365 3366 const size_t nfsitd = howmany(xfer->ux_nframes, OHCI_ITD_NOFFSET); 3367 const size_t nbsitd = xfer->ux_bufsize / OHCI_PAGE_SIZE; 3368 const size_t nsitd = MAX(nfsitd, nbsitd) + 1; 3369 3370 ox->ox_sitds = kmem_zalloc(sizeof(ohci_soft_itd_t *) * nsitd, 3371 KM_SLEEP); 3372 ox->ox_nsitd = nsitd; 3373 3374 for (i = 0; i < nsitd; i++) { 3375 /* Allocate next ITD */ 3376 sitd = ohci_alloc_sitd(sc); 3377 if (sitd == NULL) { 3378 err = ENOMEM; 3379 goto fail; 3380 } 3381 ox->ox_sitds[i] = sitd; 3382 sitd->xfer = xfer; 3383 sitd->flags = 0; 3384 } 3385 3386 return 0; 3387 fail: 3388 for (; i > 0;) { 3389 ohci_free_sitd(sc, ox->ox_sitds[--i]); 3390 } 3391 return err; 3392 } 3393 3394 Static void 3395 ohci_device_isoc_fini(struct usbd_xfer *xfer) 3396 { 3397 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3398 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3399 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3400 3401 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3402 3403 mutex_enter(&sc->sc_lock); 3404 for (size_t i = 0; i < ox->ox_nsitd; i++) { 3405 if (ox->ox_sitds[i] != opipe->tail.itd) { 3406 ohci_free_sitd_locked(sc, ox->ox_sitds[i]); 3407 } 3408 } 3409 mutex_exit(&sc->sc_lock); 3410 3411 if (ox->ox_nsitd) { 3412 const size_t sz = sizeof(ohci_soft_itd_t *) * ox->ox_nsitd; 3413 kmem_free(ox->ox_sitds, sz); 3414 } 3415 } 3416 3417 3418 usbd_status 3419 ohci_device_isoc_transfer(struct usbd_xfer *xfer) 3420 { 3421 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3422 usbd_status __diagused err; 3423 3424 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3425 3426 DPRINTFN(5, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3427 3428 /* Put it on our queue, */ 3429 mutex_enter(&sc->sc_lock); 3430 err = usb_insert_transfer(xfer); 3431 mutex_exit(&sc->sc_lock); 3432 3433 KASSERT(err == USBD_NORMAL_COMPLETION); 3434 3435 /* insert into schedule, */ 3436 ohci_device_isoc_enter(xfer); 3437 3438 /* and start if the pipe wasn't running */ 3439 return USBD_IN_PROGRESS; 3440 } 3441 3442 void 3443 ohci_device_isoc_enter(struct usbd_xfer *xfer) 3444 { 3445 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3446 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3447 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3448 ohci_soft_ed_t *sed = opipe->sed; 3449 ohci_soft_itd_t *sitd, *nsitd, *tail; 3450 ohci_physaddr_t buf, offs, noffs, bp0; 3451 int i, ncur, nframes; 3452 3453 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3454 DPRINTFN(5, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3455 3456 mutex_enter(&sc->sc_lock); 3457 3458 if (sc->sc_dying) { 3459 mutex_exit(&sc->sc_lock); 3460 return; 3461 } 3462 3463 struct isoc *isoc = &opipe->isoc; 3464 3465 DPRINTFN(1, "used=%jd next=%jd xfer=%#jx nframes=%jd", 3466 isoc->inuse, isoc->next, (uintptr_t)xfer, xfer->ux_nframes); 3467 3468 int isread = 3469 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 3470 3471 if (xfer->ux_length) 3472 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3473 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3474 3475 if (isoc->next == -1) { 3476 /* Not in use yet, schedule it a few frames ahead. */ 3477 usb_syncmem(&sc->sc_hccadma, 3478 offsetof(struct ohci_hcca, hcca_frame_number), 3479 sizeof(sc->sc_hcca->hcca_frame_number), 3480 BUS_DMASYNC_POSTREAD); 3481 isoc->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3482 DPRINTFN(2,"start next=%jd", isoc->next, 0, 0, 0); 3483 } 3484 3485 sitd = opipe->tail.itd; 3486 opipe->tail.itd = ox->ox_sitds[0]; 3487 ox->ox_sitds[0] = sitd; 3488 3489 buf = DMAADDR(&xfer->ux_dmabuf, 0); 3490 bp0 = OHCI_PAGE(buf); 3491 offs = OHCI_PAGE_OFFSET(buf); 3492 nframes = xfer->ux_nframes; 3493 xfer->ux_hcpriv = sitd; 3494 size_t j = 1; 3495 for (i = ncur = 0; i < nframes; i++, ncur++) { 3496 noffs = offs + xfer->ux_frlengths[i]; 3497 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3498 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3499 3500 /* Allocate next ITD */ 3501 nsitd = ox->ox_sitds[j++]; 3502 KASSERT(nsitd != NULL); 3503 KASSERT(j < ox->ox_nsitd); 3504 3505 /* Fill current ITD */ 3506 sitd->itd.itd_flags = HTOO32( 3507 OHCI_ITD_NOCC | 3508 OHCI_ITD_SET_SF(isoc->next) | 3509 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3510 OHCI_ITD_SET_FC(ncur)); 3511 sitd->itd.itd_bp0 = HTOO32(bp0); 3512 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3513 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3514 sitd->nextitd = nsitd; 3515 sitd->xfer = xfer; 3516 sitd->flags = 0; 3517 #ifdef DIAGNOSTIC 3518 sitd->isdone = false; 3519 #endif 3520 ohci_hash_add_itd(sc, sitd); 3521 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3522 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3523 3524 sitd = nsitd; 3525 isoc->next = isoc->next + ncur; 3526 bp0 = OHCI_PAGE(buf + offs); 3527 ncur = 0; 3528 } 3529 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3530 offs = noffs; 3531 } 3532 KASSERT(j <= ox->ox_nsitd); 3533 3534 /* point at sentinel */ 3535 tail = opipe->tail.itd; 3536 memset(&tail->itd, 0, sizeof(tail->itd)); 3537 tail->nextitd = NULL; 3538 tail->xfer = NULL; 3539 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->itd), 3540 BUS_DMASYNC_PREWRITE); 3541 3542 /* Fixup last used ITD */ 3543 sitd->itd.itd_flags = HTOO32( 3544 OHCI_ITD_NOCC | 3545 OHCI_ITD_SET_SF(isoc->next) | 3546 OHCI_ITD_SET_DI(0) | 3547 OHCI_ITD_SET_FC(ncur)); 3548 sitd->itd.itd_bp0 = HTOO32(bp0); 3549 sitd->itd.itd_nextitd = HTOO32(tail->physaddr); 3550 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3551 sitd->nextitd = tail; 3552 sitd->xfer = xfer; 3553 sitd->flags = OHCI_CALL_DONE; 3554 #ifdef DIAGNOSTIC 3555 sitd->isdone = false; 3556 #endif 3557 ohci_hash_add_itd(sc, sitd); 3558 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3559 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3560 3561 isoc->next = isoc->next + ncur; 3562 isoc->inuse += nframes; 3563 3564 /* XXX pretend we did it all */ 3565 xfer->ux_actlen = offs; 3566 xfer->ux_status = USBD_IN_PROGRESS; 3567 3568 #ifdef OHCI_DEBUG 3569 if (ohcidebug >= 5) { 3570 usb_syncmem(&sc->sc_hccadma, 3571 offsetof(struct ohci_hcca, hcca_frame_number), 3572 sizeof(sc->sc_hcca->hcca_frame_number), 3573 BUS_DMASYNC_POSTREAD); 3574 DPRINTF("frame=%jd", O32TOH(sc->sc_hcca->hcca_frame_number), 3575 0, 0, 0); 3576 ohci_dump_itds(sc, xfer->ux_hcpriv); 3577 ohci_dump_ed(sc, sed); 3578 } 3579 #endif 3580 3581 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3582 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3583 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3584 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3585 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3586 sizeof(sed->ed.ed_flags), 3587 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3588 mutex_exit(&sc->sc_lock); 3589 } 3590 3591 void 3592 ohci_device_isoc_abort(struct usbd_xfer *xfer) 3593 { 3594 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3595 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3596 ohci_soft_ed_t *sed; 3597 ohci_soft_itd_t *sitd; 3598 3599 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3600 DPRINTFN(1, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3601 3602 KASSERT(mutex_owned(&sc->sc_lock)); 3603 3604 /* Transfer is already done. */ 3605 if (xfer->ux_status != USBD_NOT_STARTED && 3606 xfer->ux_status != USBD_IN_PROGRESS) { 3607 printf("ohci_device_isoc_abort: early return\n"); 3608 goto done; 3609 } 3610 3611 /* Give xfer the requested abort code. */ 3612 xfer->ux_status = USBD_CANCELLED; 3613 3614 sed = opipe->sed; 3615 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3616 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3617 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3618 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3619 sizeof(sed->ed.ed_flags), 3620 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3621 3622 sitd = xfer->ux_hcpriv; 3623 KASSERT(sitd); 3624 3625 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3626 3627 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3628 ohci_hash_rem_itd(sc, sitd); 3629 #ifdef DIAGNOSTIC 3630 DPRINTFN(1, "abort sets done sitd=%#jx", (uintptr_t)sitd, 3631 0, 0, 0); 3632 sitd->isdone = true; 3633 #endif 3634 } 3635 3636 /* Run callback. */ 3637 usb_transfer_complete(xfer); 3638 3639 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3640 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3641 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3642 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3643 3644 done: 3645 KASSERT(mutex_owned(&sc->sc_lock)); 3646 } 3647 3648 void 3649 ohci_device_isoc_done(struct usbd_xfer *xfer) 3650 { 3651 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3652 DPRINTFN(1, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3653 3654 int isread = 3655 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 3656 3657 DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 3658 0, 0); 3659 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3660 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3661 } 3662 3663 usbd_status 3664 ohci_setup_isoc(struct usbd_pipe *pipe) 3665 { 3666 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3667 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3668 struct isoc *isoc = &opipe->isoc; 3669 3670 isoc->next = -1; 3671 isoc->inuse = 0; 3672 3673 mutex_enter(&sc->sc_lock); 3674 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3675 mutex_exit(&sc->sc_lock); 3676 3677 return USBD_NORMAL_COMPLETION; 3678 } 3679 3680 void 3681 ohci_device_isoc_close(struct usbd_pipe *pipe) 3682 { 3683 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3684 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3685 3686 KASSERT(mutex_owned(&sc->sc_lock)); 3687 3688 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3689 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3690 ohci_close_pipe(pipe, sc->sc_isoc_head); 3691 #ifdef DIAGNOSTIC 3692 opipe->tail.itd->isdone = true; 3693 #endif 3694 ohci_free_sitd_locked(sc, opipe->tail.itd); 3695 } 3696
Indexes created Tue Sep 23 22:09:46 GMT 2025