ohci.c revision 1.308
1 /* $NetBSD: ohci.c,v 1.308 2020/05/24 07:42:51 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * USB Open Host Controller driver. 38 * 39 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 40 * USB spec: http://www.usb.org/developers/docs/ 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.308 2020/05/24 07:42:51 skrll Exp $"); 45 46 #ifdef _KERNEL_OPT 47 #include "opt_usb.h" 48 #endif 49 50 #include <sys/param.h> 51 52 #include <sys/cpu.h> 53 #include <sys/device.h> 54 #include <sys/kernel.h> 55 #include <sys/kmem.h> 56 #include <sys/proc.h> 57 #include <sys/queue.h> 58 #include <sys/select.h> 59 #include <sys/sysctl.h> 60 #include <sys/systm.h> 61 62 #include <machine/endian.h> 63 64 #include <dev/usb/usb.h> 65 #include <dev/usb/usbdi.h> 66 #include <dev/usb/usbdivar.h> 67 #include <dev/usb/usb_mem.h> 68 #include <dev/usb/usb_quirks.h> 69 70 #include <dev/usb/ohcireg.h> 71 #include <dev/usb/ohcivar.h> 72 #include <dev/usb/usbroothub.h> 73 #include <dev/usb/usbhist.h> 74 75 #ifdef USB_DEBUG 76 #ifndef OHCI_DEBUG 77 #define ohcidebug 0 78 #else 79 static int ohcidebug = 10; 80 81 SYSCTL_SETUP(sysctl_hw_ohci_setup, "sysctl hw.ohci setup") 82 { 83 int err; 84 const struct sysctlnode *rnode; 85 const struct sysctlnode *cnode; 86 87 err = sysctl_createv(clog, 0, NULL, &rnode, 88 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ohci", 89 SYSCTL_DESCR("ohci global controls"), 90 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 91 92 if (err) 93 goto fail; 94 95 /* control debugging printfs */ 96 err = sysctl_createv(clog, 0, &rnode, &cnode, 97 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 98 "debug", SYSCTL_DESCR("Enable debugging output"), 99 NULL, 0, &ohcidebug, sizeof(ohcidebug), CTL_CREATE, CTL_EOL); 100 if (err) 101 goto fail; 102 103 return; 104 fail: 105 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 106 } 107 108 #endif /* OHCI_DEBUG */ 109 #endif /* USB_DEBUG */ 110 111 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ohcidebug,FMT,A,B,C,D) 112 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ohcidebug,N,FMT,A,B,C,D) 113 #define OHCIHIST_FUNC() USBHIST_FUNC() 114 #define OHCIHIST_CALLED(name) USBHIST_CALLED(ohcidebug) 115 116 #if BYTE_ORDER == BIG_ENDIAN 117 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 118 #else 119 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 120 #endif 121 122 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 123 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 124 #define HTOO16(val) O16TOH(val) 125 #define HTOO32(val) O32TOH(val) 126 127 struct ohci_pipe; 128 129 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 130 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 131 132 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 133 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 134 Static void ohci_free_std_locked(ohci_softc_t *, ohci_soft_td_t *); 135 136 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 137 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 138 Static void ohci_free_sitd_locked(ohci_softc_t *, 139 ohci_soft_itd_t *); 140 141 Static int ohci_alloc_std_chain(ohci_softc_t *, struct usbd_xfer *, 142 int, int); 143 Static void ohci_free_stds(ohci_softc_t *, struct ohci_xfer *); 144 145 Static void ohci_reset_std_chain(ohci_softc_t *, struct usbd_xfer *, 146 int, int, ohci_soft_td_t *, ohci_soft_td_t **); 147 148 Static usbd_status ohci_open(struct usbd_pipe *); 149 Static void ohci_poll(struct usbd_bus *); 150 Static void ohci_softintr(void *); 151 Static void ohci_rhsc(ohci_softc_t *, struct usbd_xfer *); 152 Static void ohci_rhsc_softint(void *); 153 154 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 155 ohci_soft_ed_t *); 156 157 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 158 ohci_soft_ed_t *); 159 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 160 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 161 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 162 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 163 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 164 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 165 166 Static usbd_status ohci_setup_isoc(struct usbd_pipe *); 167 Static void ohci_device_isoc_enter(struct usbd_xfer *); 168 169 Static struct usbd_xfer * 170 ohci_allocx(struct usbd_bus *, unsigned int); 171 Static void ohci_freex(struct usbd_bus *, struct usbd_xfer *); 172 Static bool ohci_dying(struct usbd_bus *); 173 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 174 Static int ohci_roothub_ctrl(struct usbd_bus *, 175 usb_device_request_t *, void *, int); 176 177 Static usbd_status ohci_root_intr_transfer(struct usbd_xfer *); 178 Static usbd_status ohci_root_intr_start(struct usbd_xfer *); 179 Static void ohci_root_intr_abort(struct usbd_xfer *); 180 Static void ohci_root_intr_close(struct usbd_pipe *); 181 Static void ohci_root_intr_done(struct usbd_xfer *); 182 183 Static int ohci_device_ctrl_init(struct usbd_xfer *); 184 Static void ohci_device_ctrl_fini(struct usbd_xfer *); 185 Static usbd_status ohci_device_ctrl_transfer(struct usbd_xfer *); 186 Static usbd_status ohci_device_ctrl_start(struct usbd_xfer *); 187 Static void ohci_device_ctrl_abort(struct usbd_xfer *); 188 Static void ohci_device_ctrl_close(struct usbd_pipe *); 189 Static void ohci_device_ctrl_done(struct usbd_xfer *); 190 191 Static int ohci_device_bulk_init(struct usbd_xfer *); 192 Static void ohci_device_bulk_fini(struct usbd_xfer *); 193 Static usbd_status ohci_device_bulk_transfer(struct usbd_xfer *); 194 Static usbd_status ohci_device_bulk_start(struct usbd_xfer *); 195 Static void ohci_device_bulk_abort(struct usbd_xfer *); 196 Static void ohci_device_bulk_close(struct usbd_pipe *); 197 Static void ohci_device_bulk_done(struct usbd_xfer *); 198 199 Static int ohci_device_intr_init(struct usbd_xfer *); 200 Static void ohci_device_intr_fini(struct usbd_xfer *); 201 Static usbd_status ohci_device_intr_transfer(struct usbd_xfer *); 202 Static usbd_status ohci_device_intr_start(struct usbd_xfer *); 203 Static void ohci_device_intr_abort(struct usbd_xfer *); 204 Static void ohci_device_intr_close(struct usbd_pipe *); 205 Static void ohci_device_intr_done(struct usbd_xfer *); 206 207 Static int ohci_device_isoc_init(struct usbd_xfer *); 208 Static void ohci_device_isoc_fini(struct usbd_xfer *); 209 Static usbd_status ohci_device_isoc_transfer(struct usbd_xfer *); 210 Static void ohci_device_isoc_abort(struct usbd_xfer *); 211 Static void ohci_device_isoc_close(struct usbd_pipe *); 212 Static void ohci_device_isoc_done(struct usbd_xfer *); 213 214 Static usbd_status ohci_device_setintr(ohci_softc_t *, 215 struct ohci_pipe *, int); 216 217 Static void ohci_rhsc_enable(void *); 218 219 Static void ohci_close_pipe(struct usbd_pipe *, ohci_soft_ed_t *); 220 Static void ohci_abortx(struct usbd_xfer *); 221 222 Static void ohci_device_clear_toggle(struct usbd_pipe *); 223 Static void ohci_noop(struct usbd_pipe *); 224 225 #ifdef OHCI_DEBUG 226 Static void ohci_dumpregs(ohci_softc_t *); 227 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 228 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 229 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 230 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 231 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 232 #endif 233 234 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 235 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 236 #define OWRITE1(sc, r, x) \ 237 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 238 #define OWRITE2(sc, r, x) \ 239 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 240 #define OWRITE4(sc, r, x) \ 241 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 242 243 static __inline uint32_t 244 OREAD4(ohci_softc_t *sc, bus_size_t r) 245 { 246 247 OBARR(sc); 248 return bus_space_read_4(sc->iot, sc->ioh, r); 249 } 250 251 /* Reverse the bits in a value 0 .. 31 */ 252 Static uint8_t revbits[OHCI_NO_INTRS] = 253 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 254 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 255 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 256 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 257 258 struct ohci_pipe { 259 struct usbd_pipe pipe; 260 ohci_soft_ed_t *sed; 261 union { 262 ohci_soft_td_t *td; 263 ohci_soft_itd_t *itd; 264 } tail; 265 /* Info needed for different pipe kinds. */ 266 union { 267 /* Control pipe */ 268 struct { 269 usb_dma_t reqdma; 270 } ctrl; 271 /* Interrupt pipe */ 272 struct { 273 int nslots; 274 int pos; 275 } intr; 276 /* Isochronous pipe */ 277 struct isoc { 278 int next, inuse; 279 } isoc; 280 }; 281 }; 282 283 Static const struct usbd_bus_methods ohci_bus_methods = { 284 .ubm_open = ohci_open, 285 .ubm_softint = ohci_softintr, 286 .ubm_dopoll = ohci_poll, 287 .ubm_allocx = ohci_allocx, 288 .ubm_freex = ohci_freex, 289 .ubm_abortx = ohci_abortx, 290 .ubm_dying = ohci_dying, 291 .ubm_getlock = ohci_get_lock, 292 .ubm_rhctrl = ohci_roothub_ctrl, 293 }; 294 295 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 296 .upm_transfer = ohci_root_intr_transfer, 297 .upm_start = ohci_root_intr_start, 298 .upm_abort = ohci_root_intr_abort, 299 .upm_close = ohci_root_intr_close, 300 .upm_cleartoggle = ohci_noop, 301 .upm_done = ohci_root_intr_done, 302 }; 303 304 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 305 .upm_init = ohci_device_ctrl_init, 306 .upm_fini = ohci_device_ctrl_fini, 307 .upm_transfer = ohci_device_ctrl_transfer, 308 .upm_start = ohci_device_ctrl_start, 309 .upm_abort = ohci_device_ctrl_abort, 310 .upm_close = ohci_device_ctrl_close, 311 .upm_cleartoggle = ohci_noop, 312 .upm_done = ohci_device_ctrl_done, 313 }; 314 315 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 316 .upm_init = ohci_device_intr_init, 317 .upm_fini = ohci_device_intr_fini, 318 .upm_transfer = ohci_device_intr_transfer, 319 .upm_start = ohci_device_intr_start, 320 .upm_abort = ohci_device_intr_abort, 321 .upm_close = ohci_device_intr_close, 322 .upm_cleartoggle = ohci_device_clear_toggle, 323 .upm_done = ohci_device_intr_done, 324 }; 325 326 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 327 .upm_init = ohci_device_bulk_init, 328 .upm_fini = ohci_device_bulk_fini, 329 .upm_transfer = ohci_device_bulk_transfer, 330 .upm_start = ohci_device_bulk_start, 331 .upm_abort = ohci_device_bulk_abort, 332 .upm_close = ohci_device_bulk_close, 333 .upm_cleartoggle = ohci_device_clear_toggle, 334 .upm_done = ohci_device_bulk_done, 335 }; 336 337 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 338 .upm_init = ohci_device_isoc_init, 339 .upm_fini = ohci_device_isoc_fini, 340 .upm_transfer = ohci_device_isoc_transfer, 341 .upm_abort = ohci_device_isoc_abort, 342 .upm_close = ohci_device_isoc_close, 343 .upm_cleartoggle = ohci_noop, 344 .upm_done = ohci_device_isoc_done, 345 }; 346 347 int 348 ohci_activate(device_t self, enum devact act) 349 { 350 struct ohci_softc *sc = device_private(self); 351 352 switch (act) { 353 case DVACT_DEACTIVATE: 354 sc->sc_dying = 1; 355 return 0; 356 default: 357 return EOPNOTSUPP; 358 } 359 } 360 361 void 362 ohci_childdet(device_t self, device_t child) 363 { 364 struct ohci_softc *sc = device_private(self); 365 366 KASSERT(sc->sc_child == child); 367 sc->sc_child = NULL; 368 } 369 370 int 371 ohci_detach(struct ohci_softc *sc, int flags) 372 { 373 int rv = 0; 374 375 if (sc->sc_child != NULL) 376 rv = config_detach(sc->sc_child, flags); 377 378 if (rv != 0) 379 return rv; 380 381 softint_disestablish(sc->sc_rhsc_si); 382 383 callout_halt(&sc->sc_tmo_rhsc, NULL); 384 callout_destroy(&sc->sc_tmo_rhsc); 385 386 mutex_destroy(&sc->sc_lock); 387 mutex_destroy(&sc->sc_intr_lock); 388 389 if (sc->sc_hcca != NULL) 390 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 391 pool_cache_destroy(sc->sc_xferpool); 392 393 return rv; 394 } 395 396 ohci_soft_ed_t * 397 ohci_alloc_sed(ohci_softc_t *sc) 398 { 399 ohci_soft_ed_t *sed; 400 usbd_status err; 401 int i, offs; 402 usb_dma_t dma; 403 404 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 405 406 mutex_enter(&sc->sc_lock); 407 if (sc->sc_freeeds == NULL) { 408 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 409 mutex_exit(&sc->sc_lock); 410 411 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 412 OHCI_ED_ALIGN, USBMALLOC_COHERENT, &dma); 413 if (err) 414 return NULL; 415 416 mutex_enter(&sc->sc_lock); 417 for (i = 0; i < OHCI_SED_CHUNK; i++) { 418 offs = i * OHCI_SED_SIZE; 419 sed = KERNADDR(&dma, offs); 420 sed->physaddr = DMAADDR(&dma, offs); 421 sed->dma = dma; 422 sed->offs = offs; 423 sed->next = sc->sc_freeeds; 424 sc->sc_freeeds = sed; 425 } 426 } 427 sed = sc->sc_freeeds; 428 sc->sc_freeeds = sed->next; 429 mutex_exit(&sc->sc_lock); 430 431 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 432 sed->next = 0; 433 return sed; 434 } 435 436 static inline void 437 ohci_free_sed_locked(ohci_softc_t *sc, ohci_soft_ed_t *sed) 438 { 439 440 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 441 442 sed->next = sc->sc_freeeds; 443 sc->sc_freeeds = sed; 444 } 445 446 void 447 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 448 { 449 450 mutex_enter(&sc->sc_lock); 451 ohci_free_sed_locked(sc, sed); 452 mutex_exit(&sc->sc_lock); 453 } 454 455 ohci_soft_td_t * 456 ohci_alloc_std(ohci_softc_t *sc) 457 { 458 ohci_soft_td_t *std; 459 usbd_status err; 460 int i, offs; 461 usb_dma_t dma; 462 463 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 464 465 mutex_enter(&sc->sc_lock); 466 if (sc->sc_freetds == NULL) { 467 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 468 mutex_exit(&sc->sc_lock); 469 470 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 471 OHCI_TD_ALIGN, USBMALLOC_COHERENT, &dma); 472 if (err) 473 return NULL; 474 475 mutex_enter(&sc->sc_lock); 476 for (i = 0; i < OHCI_STD_CHUNK; i++) { 477 offs = i * OHCI_STD_SIZE; 478 std = KERNADDR(&dma, offs); 479 std->physaddr = DMAADDR(&dma, offs); 480 std->dma = dma; 481 std->offs = offs; 482 std->nexttd = sc->sc_freetds; 483 sc->sc_freetds = std; 484 } 485 } 486 487 std = sc->sc_freetds; 488 sc->sc_freetds = std->nexttd; 489 mutex_exit(&sc->sc_lock); 490 491 memset(&std->td, 0, sizeof(ohci_td_t)); 492 std->nexttd = NULL; 493 std->xfer = NULL; 494 495 return std; 496 } 497 498 void 499 ohci_free_std_locked(ohci_softc_t *sc, ohci_soft_td_t *std) 500 { 501 502 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 503 504 std->nexttd = sc->sc_freetds; 505 sc->sc_freetds = std; 506 } 507 508 void 509 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 510 { 511 512 mutex_enter(&sc->sc_lock); 513 ohci_free_std_locked(sc, std); 514 mutex_exit(&sc->sc_lock); 515 } 516 517 Static int 518 ohci_alloc_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, int length, int rd) 519 { 520 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 521 uint16_t flags = xfer->ux_flags; 522 523 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 524 525 DPRINTFN(8, "addr=%jd endpt=%jd len=%jd speed=%jd", 526 xfer->ux_pipe->up_dev->ud_addr, 527 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 528 length, xfer->ux_pipe->up_dev->ud_speed); 529 530 ASSERT_SLEEPABLE(); 531 KASSERT(length != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 532 533 size_t nstd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 534 nstd += howmany(length, OHCI_PAGE_SIZE); 535 ox->ox_stds = kmem_zalloc(sizeof(ohci_soft_td_t *) * nstd, 536 KM_SLEEP); 537 ox->ox_nstd = nstd; 538 539 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, nstd, 0, 0); 540 541 for (size_t j = 0; j < ox->ox_nstd;) { 542 ohci_soft_td_t *cur = ohci_alloc_std(sc); 543 if (cur == NULL) 544 goto nomem; 545 546 ox->ox_stds[j++] = cur; 547 cur->xfer = xfer; 548 cur->flags = 0; 549 } 550 551 return 0; 552 553 nomem: 554 ohci_free_stds(sc, ox); 555 kmem_free(ox->ox_stds, sizeof(ohci_soft_td_t *) * nstd); 556 557 return ENOMEM; 558 } 559 560 Static void 561 ohci_free_stds(ohci_softc_t *sc, struct ohci_xfer *ox) 562 { 563 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 564 DPRINTF("ox=%#jx", (uintptr_t)ox, 0, 0, 0); 565 566 mutex_enter(&sc->sc_lock); 567 for (size_t i = 0; i < ox->ox_nstd; i++) { 568 ohci_soft_td_t *std = ox->ox_stds[i]; 569 if (std == NULL) 570 break; 571 ohci_free_std_locked(sc, std); 572 } 573 mutex_exit(&sc->sc_lock); 574 } 575 576 void 577 ohci_reset_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, 578 int alen, int rd, ohci_soft_td_t *sp, ohci_soft_td_t **ep) 579 { 580 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 581 ohci_soft_td_t *next, *cur; 582 int len, curlen; 583 usb_dma_t *dma = &xfer->ux_dmabuf; 584 uint16_t flags = xfer->ux_flags; 585 586 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 587 DPRINTF("start len=%jd", alen, 0, 0, 0); 588 589 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 590 591 DPRINTFN(8, "addr=%jd endpt=%jd len=%jd speed=%jd", 592 xfer->ux_pipe->up_dev->ud_addr, 593 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 594 alen, xfer->ux_pipe->up_dev->ud_speed); 595 596 KASSERT(sp); 597 598 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 599 600 /* 601 * Assign next for the len == 0 case where we don't go through the 602 * main loop. 603 */ 604 len = alen; 605 cur = next = sp; 606 607 usb_syncmem(dma, 0, len, 608 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 609 const uint32_t tdflags = HTOO32( 610 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 611 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 612 613 size_t curoffs = 0; 614 for (size_t j = 1; len != 0;) { 615 if (j == ox->ox_nstd) 616 next = NULL; 617 else 618 next = ox->ox_stds[j++]; 619 KASSERT(next != cur); 620 621 curlen = len; 622 /* 623 * The OHCI hardware can handle at most one page crossing per 624 * TD. That is, 2 * OHCI_PAGE_SIZE as a maximum. Limit the 625 * length in this TD accordingly. 626 */ 627 const ohci_physaddr_t sdataphys = DMAADDR(dma, curoffs); 628 629 int maxlen = (2 * OHCI_PAGE_SIZE) - OHCI_PAGE_OFFSET(sdataphys); 630 if (curlen > maxlen) { 631 curlen = maxlen; 632 633 /* 634 * the length must be a multiple of 635 * the max size 636 */ 637 curlen -= curlen % mps; 638 } 639 640 const int edataoffs = curoffs + curlen - 1; 641 const ohci_physaddr_t edataphys = DMAADDR(dma, edataoffs); 642 643 KASSERT(curlen != 0); 644 DPRINTFN(4, "sdataphys=0x%08jx edataphys=0x%08jx " 645 "len=%jd curlen=%jd", sdataphys, edataphys, len, curlen); 646 647 cur->td.td_flags = tdflags; 648 cur->td.td_cbp = HTOO32(sdataphys); 649 cur->td.td_be = HTOO32(edataphys); 650 cur->td.td_nexttd = (next != NULL) ? HTOO32(next->physaddr) : 0; 651 cur->nexttd = next; 652 cur->len = curlen; 653 cur->flags = OHCI_ADD_LEN; 654 cur->xfer = xfer; 655 ohci_hash_add_td(sc, cur); 656 657 curoffs += curlen; 658 len -= curlen; 659 660 if (len != 0) { 661 KASSERT(next != NULL); 662 DPRINTFN(10, "extend chain", 0, 0, 0, 0); 663 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 664 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 665 666 cur = next; 667 } 668 } 669 cur->td.td_flags |= 670 HTOO32(xfer->ux_flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0); 671 672 if (!rd && 673 (flags & USBD_FORCE_SHORT_XFER) && 674 alen % mps == 0) { 675 /* We're adding a ZLP so sync the previous TD */ 676 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 677 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 678 679 /* Force a 0 length transfer at the end. */ 680 681 KASSERT(next != NULL); 682 cur = next; 683 684 cur->td.td_flags = tdflags; 685 cur->td.td_cbp = 0; /* indicate 0 length packet */ 686 cur->td.td_nexttd = 0; 687 cur->td.td_be = ~0; 688 cur->nexttd = NULL; 689 cur->len = 0; 690 cur->flags = 0; 691 cur->xfer = xfer; 692 ohci_hash_add_td(sc, cur); 693 694 DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0); 695 } 696 697 /* Last TD gets usb_syncmem'ed by caller */ 698 *ep = cur; 699 } 700 701 ohci_soft_itd_t * 702 ohci_alloc_sitd(ohci_softc_t *sc) 703 { 704 ohci_soft_itd_t *sitd; 705 usbd_status err; 706 int i, offs; 707 usb_dma_t dma; 708 709 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 710 711 mutex_enter(&sc->sc_lock); 712 if (sc->sc_freeitds == NULL) { 713 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 714 mutex_exit(&sc->sc_lock); 715 716 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 717 OHCI_ITD_ALIGN, USBMALLOC_COHERENT, &dma); 718 if (err) 719 return NULL; 720 mutex_enter(&sc->sc_lock); 721 for (i = 0; i < OHCI_SITD_CHUNK; i++) { 722 offs = i * OHCI_SITD_SIZE; 723 sitd = KERNADDR(&dma, offs); 724 sitd->physaddr = DMAADDR(&dma, offs); 725 sitd->dma = dma; 726 sitd->offs = offs; 727 sitd->nextitd = sc->sc_freeitds; 728 sc->sc_freeitds = sitd; 729 } 730 } 731 732 sitd = sc->sc_freeitds; 733 sc->sc_freeitds = sitd->nextitd; 734 mutex_exit(&sc->sc_lock); 735 736 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 737 sitd->nextitd = NULL; 738 sitd->xfer = NULL; 739 740 #ifdef DIAGNOSTIC 741 sitd->isdone = true; 742 #endif 743 744 return sitd; 745 } 746 747 Static void 748 ohci_free_sitd_locked(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 749 { 750 751 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 752 DPRINTFN(10, "sitd=%#jx", (uintptr_t)sitd, 0, 0, 0); 753 754 KASSERT(sitd->isdone); 755 #ifdef DIAGNOSTIC 756 /* Warn double free */ 757 sitd->isdone = false; 758 #endif 759 760 sitd->nextitd = sc->sc_freeitds; 761 sc->sc_freeitds = sitd; 762 } 763 764 void 765 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 766 { 767 768 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 769 770 mutex_enter(&sc->sc_lock); 771 ohci_free_sitd_locked(sc, sitd); 772 mutex_exit(&sc->sc_lock); 773 } 774 775 int 776 ohci_init(ohci_softc_t *sc) 777 { 778 ohci_soft_ed_t *sed, *psed; 779 usbd_status err; 780 int i; 781 uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */; 782 783 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 784 785 aprint_normal_dev(sc->sc_dev, ""); 786 787 sc->sc_hcca = NULL; 788 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 789 790 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 791 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 792 793 sc->sc_rhsc_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 794 ohci_rhsc_softint, sc); 795 796 for (i = 0; i < OHCI_HASH_SIZE; i++) 797 LIST_INIT(&sc->sc_hash_tds[i]); 798 for (i = 0; i < OHCI_HASH_SIZE; i++) 799 LIST_INIT(&sc->sc_hash_itds[i]); 800 801 sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0, 802 "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL); 803 804 rev = OREAD4(sc, OHCI_REVISION); 805 aprint_normal("OHCI version %d.%d%s\n", 806 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 807 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 808 809 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 810 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 811 sc->sc_bus.ub_revision = USBREV_UNKNOWN; 812 return -1; 813 } 814 sc->sc_bus.ub_revision = USBREV_1_0; 815 sc->sc_bus.ub_usedma = true; 816 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 817 818 /* XXX determine alignment by R/W */ 819 /* Allocate the HCCA area. */ 820 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 821 OHCI_HCCA_ALIGN, USBMALLOC_COHERENT, &sc->sc_hccadma); 822 if (err) { 823 sc->sc_hcca = NULL; 824 return err; 825 } 826 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 827 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 828 829 sc->sc_eintrs = OHCI_NORMAL_INTRS; 830 831 /* Allocate dummy ED that starts the control list. */ 832 sc->sc_ctrl_head = ohci_alloc_sed(sc); 833 if (sc->sc_ctrl_head == NULL) { 834 err = ENOMEM; 835 goto bad1; 836 } 837 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 838 839 /* Allocate dummy ED that starts the bulk list. */ 840 sc->sc_bulk_head = ohci_alloc_sed(sc); 841 if (sc->sc_bulk_head == NULL) { 842 err = ENOMEM; 843 goto bad2; 844 } 845 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 846 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 847 sizeof(sc->sc_bulk_head->ed), 848 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 849 850 /* Allocate dummy ED that starts the isochronous list. */ 851 sc->sc_isoc_head = ohci_alloc_sed(sc); 852 if (sc->sc_isoc_head == NULL) { 853 err = ENOMEM; 854 goto bad3; 855 } 856 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 857 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 858 sizeof(sc->sc_isoc_head->ed), 859 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 860 861 /* Allocate all the dummy EDs that make up the interrupt tree. */ 862 for (i = 0; i < OHCI_NO_EDS; i++) { 863 sed = ohci_alloc_sed(sc); 864 if (sed == NULL) { 865 while (--i >= 0) 866 ohci_free_sed(sc, sc->sc_eds[i]); 867 err = ENOMEM; 868 goto bad4; 869 } 870 /* All ED fields are set to 0. */ 871 sc->sc_eds[i] = sed; 872 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 873 if (i != 0) 874 psed = sc->sc_eds[(i-1) / 2]; 875 else 876 psed= sc->sc_isoc_head; 877 sed->next = psed; 878 sed->ed.ed_nexted = HTOO32(psed->physaddr); 879 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 880 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 881 } 882 /* 883 * Fill HCCA interrupt table. The bit reversal is to get 884 * the tree set up properly to spread the interrupts. 885 */ 886 for (i = 0; i < OHCI_NO_INTRS; i++) 887 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 888 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 889 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 890 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 891 892 #ifdef OHCI_DEBUG 893 DPRINTFN(15, "--- dump start ---", 0, 0, 0 ,0); 894 if (ohcidebug >= 15) { 895 for (i = 0; i < OHCI_NO_EDS; i++) { 896 DPRINTFN(15, "ed#%jd ", i, 0, 0, 0); 897 ohci_dump_ed(sc, sc->sc_eds[i]); 898 } 899 DPRINTFN(15, "iso", 0, 0, 0 ,0); 900 ohci_dump_ed(sc, sc->sc_isoc_head); 901 } 902 DPRINTFN(15, "--- dump end ---", 0, 0, 0 ,0); 903 #endif 904 905 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 906 ctl = OREAD4(sc, OHCI_CONTROL); 907 rwc = ctl & OHCI_RWC; 908 fm = OREAD4(sc, OHCI_FM_INTERVAL); 909 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 910 /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */ 911 912 /* Determine in what context we are running. */ 913 if (ctl & OHCI_IR) { 914 /* SMM active, request change */ 915 DPRINTF("SMM active, request owner change", 0, 0, 0, 0); 916 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 917 (OHCI_OC | OHCI_MIE)) 918 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 919 s = OREAD4(sc, OHCI_COMMAND_STATUS); 920 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 921 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 922 usb_delay_ms(&sc->sc_bus, 1); 923 ctl = OREAD4(sc, OHCI_CONTROL); 924 } 925 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 926 if ((ctl & OHCI_IR) == 0) { 927 aprint_error_dev(sc->sc_dev, 928 "SMM does not respond, resetting\n"); 929 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 930 goto reset; 931 } 932 #if 0 933 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 934 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 935 /* BIOS started controller. */ 936 DPRINTF("BIOS active", 0, 0, 0, 0); 937 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 938 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 939 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 940 } 941 #endif 942 } else { 943 DPRINTF("cold started", 0 ,0 ,0 ,0); 944 reset: 945 /* Controller was cold started. */ 946 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 947 } 948 949 /* 950 * This reset should not be necessary according to the OHCI spec, but 951 * without it some controllers do not start. 952 */ 953 DPRINTF("sc %#jx: resetting", (uintptr_t)sc, 0, 0, 0); 954 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 955 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 956 957 /* We now own the host controller and the bus has been reset. */ 958 959 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 960 /* Nominal time for a reset is 10 us. */ 961 for (i = 0; i < 10; i++) { 962 delay(10); 963 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 964 if (!hcr) 965 break; 966 } 967 if (hcr) { 968 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 969 err = EIO; 970 goto bad5; 971 } 972 #ifdef OHCI_DEBUG 973 if (ohcidebug >= 15) 974 ohci_dumpregs(sc); 975 #endif 976 977 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 978 979 /* Set up HC registers. */ 980 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 981 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 982 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 983 /* disable all interrupts and then switch on all desired interrupts */ 984 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 985 /* switch on desired functional features */ 986 ctl = OREAD4(sc, OHCI_CONTROL); 987 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 988 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 989 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 990 /* And finally start it! */ 991 OWRITE4(sc, OHCI_CONTROL, ctl); 992 993 /* 994 * The controller is now OPERATIONAL. Set a some final 995 * registers that should be set earlier, but that the 996 * controller ignores when in the SUSPEND state. 997 */ 998 ival = OHCI_GET_IVAL(fm); 999 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 1000 fm |= OHCI_FSMPS(ival) | ival; 1001 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 1002 per = OHCI_PERIODIC(ival); /* 90% periodic */ 1003 OWRITE4(sc, OHCI_PERIODIC_START, per); 1004 1005 if (sc->sc_flags & OHCIF_SUPERIO) { 1006 /* no overcurrent protection */ 1007 desca |= OHCI_NOCP; 1008 /* 1009 * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning 1010 * that 1011 * - ports are always power switched 1012 * - don't wait for powered root hub port 1013 */ 1014 desca &= ~(__SHIFTIN(0xff, OHCI_POTPGT_MASK) | OHCI_NPS); 1015 } 1016 1017 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 1018 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 1019 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 1020 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 1021 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 1022 1023 /* 1024 * The AMD756 requires a delay before re-reading the register, 1025 * otherwise it will occasionally report 0 ports. 1026 */ 1027 sc->sc_noport = 0; 1028 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 1029 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 1030 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 1031 } 1032 1033 #ifdef OHCI_DEBUG 1034 if (ohcidebug >= 5) 1035 ohci_dumpregs(sc); 1036 #endif 1037 1038 /* Set up the bus struct. */ 1039 sc->sc_bus.ub_methods = &ohci_bus_methods; 1040 sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe); 1041 1042 sc->sc_control = sc->sc_intre = 0; 1043 1044 /* Finally, turn on interrupts. */ 1045 DPRINTF("enabling %#jx", sc->sc_eintrs | OHCI_MIE, 0, 0, 0); 1046 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 1047 1048 return 0; 1049 1050 bad5: 1051 for (i = 0; i < OHCI_NO_EDS; i++) 1052 ohci_free_sed(sc, sc->sc_eds[i]); 1053 bad4: 1054 ohci_free_sed(sc, sc->sc_isoc_head); 1055 bad3: 1056 ohci_free_sed(sc, sc->sc_bulk_head); 1057 bad2: 1058 ohci_free_sed(sc, sc->sc_ctrl_head); 1059 bad1: 1060 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 1061 sc->sc_hcca = NULL; 1062 return err; 1063 } 1064 1065 struct usbd_xfer * 1066 ohci_allocx(struct usbd_bus *bus, unsigned int nframes) 1067 { 1068 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1069 struct usbd_xfer *xfer; 1070 1071 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 1072 if (xfer != NULL) { 1073 memset(xfer, 0, sizeof(struct ohci_xfer)); 1074 1075 #ifdef DIAGNOSTIC 1076 xfer->ux_state = XFER_BUSY; 1077 #endif 1078 } 1079 return xfer; 1080 } 1081 1082 void 1083 ohci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1084 { 1085 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1086 1087 KASSERTMSG(xfer->ux_state == XFER_BUSY || 1088 xfer->ux_status == USBD_NOT_STARTED, 1089 "xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state); 1090 #ifdef DIAGNOSTIC 1091 xfer->ux_state = XFER_FREE; 1092 #endif 1093 pool_cache_put(sc->sc_xferpool, xfer); 1094 } 1095 1096 Static bool 1097 ohci_dying(struct usbd_bus *bus) 1098 { 1099 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1100 1101 return sc->sc_dying; 1102 } 1103 1104 Static void 1105 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1106 { 1107 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1108 1109 *lock = &sc->sc_lock; 1110 } 1111 1112 /* 1113 * Shut down the controller when the system is going down. 1114 */ 1115 bool 1116 ohci_shutdown(device_t self, int flags) 1117 { 1118 ohci_softc_t *sc = device_private(self); 1119 1120 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1121 1122 DPRINTF("stopping the HC", 0, 0, 0, 0); 1123 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 1124 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1125 return true; 1126 } 1127 1128 bool 1129 ohci_resume(device_t dv, const pmf_qual_t *qual) 1130 { 1131 ohci_softc_t *sc = device_private(dv); 1132 uint32_t ctl; 1133 1134 mutex_spin_enter(&sc->sc_intr_lock); 1135 sc->sc_bus.ub_usepolling++; 1136 mutex_spin_exit(&sc->sc_intr_lock); 1137 1138 /* Some broken BIOSes do not recover these values */ 1139 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1140 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1141 sc->sc_ctrl_head->physaddr); 1142 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1143 sc->sc_bulk_head->physaddr); 1144 if (sc->sc_intre) 1145 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1146 (OHCI_ALL_INTRS | OHCI_MIE)); 1147 if (sc->sc_control) 1148 ctl = sc->sc_control; 1149 else 1150 ctl = OREAD4(sc, OHCI_CONTROL); 1151 ctl |= OHCI_HCFS_RESUME; 1152 OWRITE4(sc, OHCI_CONTROL, ctl); 1153 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1154 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1155 OWRITE4(sc, OHCI_CONTROL, ctl); 1156 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1157 sc->sc_control = sc->sc_intre = 0; 1158 1159 mutex_spin_enter(&sc->sc_intr_lock); 1160 sc->sc_bus.ub_usepolling--; 1161 mutex_spin_exit(&sc->sc_intr_lock); 1162 1163 return true; 1164 } 1165 1166 bool 1167 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1168 { 1169 ohci_softc_t *sc = device_private(dv); 1170 uint32_t ctl; 1171 1172 mutex_spin_enter(&sc->sc_intr_lock); 1173 sc->sc_bus.ub_usepolling++; 1174 mutex_spin_exit(&sc->sc_intr_lock); 1175 1176 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1177 if (sc->sc_control == 0) { 1178 /* 1179 * Preserve register values, in case that BIOS 1180 * does not recover them. 1181 */ 1182 sc->sc_control = ctl; 1183 sc->sc_intre = OREAD4(sc, 1184 OHCI_INTERRUPT_ENABLE); 1185 } 1186 ctl |= OHCI_HCFS_SUSPEND; 1187 OWRITE4(sc, OHCI_CONTROL, ctl); 1188 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1189 1190 mutex_spin_enter(&sc->sc_intr_lock); 1191 sc->sc_bus.ub_usepolling--; 1192 mutex_spin_exit(&sc->sc_intr_lock); 1193 1194 return true; 1195 } 1196 1197 #ifdef OHCI_DEBUG 1198 void 1199 ohci_dumpregs(ohci_softc_t *sc) 1200 { 1201 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1202 1203 DPRINTF("rev=0x%08jx control=0x%08jx command=0x%08jx", 1204 OREAD4(sc, OHCI_REVISION), 1205 OREAD4(sc, OHCI_CONTROL), 1206 OREAD4(sc, OHCI_COMMAND_STATUS), 0); 1207 DPRINTF(" intrstat=0x%08jx intre=0x%08jx intrd=0x%08jx", 1208 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1209 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1210 OREAD4(sc, OHCI_INTERRUPT_DISABLE), 0); 1211 DPRINTF(" hcca=0x%08jx percur=0x%08jx ctrlhd=0x%08jx", 1212 OREAD4(sc, OHCI_HCCA), 1213 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1214 OREAD4(sc, OHCI_CONTROL_HEAD_ED), 0); 1215 DPRINTF(" ctrlcur=0x%08jx bulkhd=0x%08jx bulkcur=0x%08jx", 1216 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1217 OREAD4(sc, OHCI_BULK_HEAD_ED), 1218 OREAD4(sc, OHCI_BULK_CURRENT_ED) ,0); 1219 DPRINTF(" done=0x%08jx fmival=0x%08jx fmrem=0x%08jx", 1220 OREAD4(sc, OHCI_DONE_HEAD), 1221 OREAD4(sc, OHCI_FM_INTERVAL), 1222 OREAD4(sc, OHCI_FM_REMAINING), 0); 1223 DPRINTF(" fmnum=0x%08jx perst=0x%08jx lsthrs=0x%08jx", 1224 OREAD4(sc, OHCI_FM_NUMBER), 1225 OREAD4(sc, OHCI_PERIODIC_START), 1226 OREAD4(sc, OHCI_LS_THRESHOLD), 0); 1227 DPRINTF(" desca=0x%08jx descb=0x%08jx stat=0x%08jx", 1228 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1229 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1230 OREAD4(sc, OHCI_RH_STATUS), 0); 1231 DPRINTF(" port1=0x%08jx port2=0x%08jx", 1232 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1233 OREAD4(sc, OHCI_RH_PORT_STATUS(2)), 0, 0); 1234 usb_syncmem(&sc->sc_hccadma, 1235 offsetof(struct ohci_hcca, hcca_frame_number), 1236 sizeof(sc->sc_hcca->hcca_frame_number) + 1237 sizeof(sc->sc_hcca->hcca_done_head), 1238 BUS_DMASYNC_POSTREAD); 1239 DPRINTF(" HCCA: frame_number=0x%04jx done_head=0x%08jx", 1240 O32TOH(sc->sc_hcca->hcca_frame_number), 1241 O32TOH(sc->sc_hcca->hcca_done_head), 0, 0); 1242 } 1243 #endif 1244 1245 Static int ohci_intr1(ohci_softc_t *); 1246 1247 int 1248 ohci_intr(void *p) 1249 { 1250 ohci_softc_t *sc = p; 1251 int ret = 0; 1252 1253 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1254 1255 if (sc == NULL) 1256 return 0; 1257 1258 mutex_spin_enter(&sc->sc_intr_lock); 1259 1260 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1261 goto done; 1262 1263 /* If we get an interrupt while polling, then just ignore it. */ 1264 if (sc->sc_bus.ub_usepolling) { 1265 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1266 /* for level triggered intrs, should do something to ack */ 1267 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1268 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1269 1270 goto done; 1271 } 1272 1273 ret = ohci_intr1(sc); 1274 1275 done: 1276 mutex_spin_exit(&sc->sc_intr_lock); 1277 return ret; 1278 } 1279 1280 Static int 1281 ohci_intr1(ohci_softc_t *sc) 1282 { 1283 uint32_t intrs, eintrs; 1284 1285 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1286 1287 /* In case the interrupt occurs before initialization has completed. */ 1288 if (sc == NULL || sc->sc_hcca == NULL) { 1289 #ifdef DIAGNOSTIC 1290 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1291 #endif 1292 return 0; 1293 } 1294 1295 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1296 1297 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1298 if (!intrs) 1299 return 0; 1300 1301 /* Acknowledge */ 1302 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); 1303 eintrs = intrs & sc->sc_eintrs; 1304 DPRINTFN(7, "sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1305 DPRINTFN(7, "intrs=%#jx(%#jx) eintrs=%#jx(%#jx)", 1306 intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), eintrs, 1307 sc->sc_eintrs); 1308 1309 if (!eintrs) { 1310 return 0; 1311 } 1312 1313 if (eintrs & OHCI_SO) { 1314 sc->sc_overrun_cnt++; 1315 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1316 printf("%s: %u scheduling overruns\n", 1317 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1318 sc->sc_overrun_cnt = 0; 1319 } 1320 /* XXX do what */ 1321 eintrs &= ~OHCI_SO; 1322 } 1323 if (eintrs & OHCI_WDH) { 1324 /* 1325 * We block the interrupt below, and reenable it later from 1326 * ohci_softintr(). 1327 */ 1328 usb_schedsoftintr(&sc->sc_bus); 1329 } 1330 if (eintrs & OHCI_RD) { 1331 DPRINTFN(5, "resume detect sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1332 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1333 /* XXX process resume detect */ 1334 } 1335 if (eintrs & OHCI_UE) { 1336 DPRINTFN(5, "unrecoverable error sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1337 printf("%s: unrecoverable error, controller halted\n", 1338 device_xname(sc->sc_dev)); 1339 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1340 /* XXX what else */ 1341 } 1342 if (eintrs & OHCI_RHSC) { 1343 /* 1344 * We block the interrupt below, and reenable it later from 1345 * a timeout. 1346 */ 1347 softint_schedule(sc->sc_rhsc_si); 1348 } 1349 1350 if (eintrs != 0) { 1351 /* Block unprocessed interrupts. */ 1352 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1353 sc->sc_eintrs &= ~eintrs; 1354 DPRINTF("sc %#jx blocking intrs %#jx", (uintptr_t)sc, 1355 eintrs, 0, 0); 1356 } 1357 1358 return 1; 1359 } 1360 1361 void 1362 ohci_rhsc_enable(void *v_sc) 1363 { 1364 ohci_softc_t *sc = v_sc; 1365 1366 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1367 DPRINTF("sc %#jx", (uintptr_t)sc, 0, 0, 0); 1368 mutex_spin_enter(&sc->sc_intr_lock); 1369 sc->sc_eintrs |= OHCI_RHSC; 1370 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1371 mutex_spin_exit(&sc->sc_intr_lock); 1372 } 1373 1374 #ifdef OHCI_DEBUG 1375 const char *ohci_cc_strs[] = { 1376 "NO_ERROR", 1377 "CRC", 1378 "BIT_STUFFING", 1379 "DATA_TOGGLE_MISMATCH", 1380 "STALL", 1381 "DEVICE_NOT_RESPONDING", 1382 "PID_CHECK_FAILURE", 1383 "UNEXPECTED_PID", 1384 "DATA_OVERRUN", 1385 "DATA_UNDERRUN", 1386 "BUFFER_OVERRUN", 1387 "BUFFER_UNDERRUN", 1388 "reserved", 1389 "reserved", 1390 "NOT_ACCESSED", 1391 "NOT_ACCESSED", 1392 }; 1393 #endif 1394 1395 void 1396 ohci_softintr(void *v) 1397 { 1398 struct usbd_bus *bus = v; 1399 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1400 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1401 ohci_soft_td_t *std, *sdone, *stdnext; 1402 struct usbd_xfer *xfer; 1403 struct ohci_pipe *opipe; 1404 int len, cc; 1405 int i, j, actlen, iframes, uedir; 1406 ohci_physaddr_t done; 1407 1408 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1409 1410 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1411 1412 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1413 sizeof(sc->sc_hcca->hcca_done_head), 1414 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1415 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1416 sc->sc_hcca->hcca_done_head = 0; 1417 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1418 sizeof(sc->sc_hcca->hcca_done_head), 1419 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1420 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1421 sc->sc_eintrs |= OHCI_WDH; 1422 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1423 1424 /* Reverse the done list. */ 1425 for (sdone = NULL, sidone = NULL; done != 0; ) { 1426 std = ohci_hash_find_td(sc, done); 1427 if (std != NULL) { 1428 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1429 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1430 std->dnext = sdone; 1431 done = O32TOH(std->td.td_nexttd); 1432 sdone = std; 1433 DPRINTFN(10, "add TD %#jx", (uintptr_t)std, 0, 0, 0); 1434 continue; 1435 } 1436 sitd = ohci_hash_find_itd(sc, done); 1437 if (sitd != NULL) { 1438 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1439 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1440 sitd->dnext = sidone; 1441 done = O32TOH(sitd->itd.itd_nextitd); 1442 sidone = sitd; 1443 DPRINTFN(5, "add ITD %#jx", (uintptr_t)sitd, 0, 0, 0); 1444 continue; 1445 } 1446 DPRINTFN(10, "addr %#jx not found", (uintptr_t)done, 0, 0, 0); 1447 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1448 (u_long)done); 1449 break; 1450 } 1451 1452 DPRINTFN(10, "sdone=%#jx sidone=%#jx", (uintptr_t)sdone, 1453 (uintptr_t)sidone, 0, 0); 1454 DPRINTFN(10, "--- TD dump start ---", 0, 0, 0, 0); 1455 #ifdef OHCI_DEBUG 1456 if (ohcidebug >= 10) { 1457 for (std = sdone; std; std = std->dnext) 1458 ohci_dump_td(sc, std); 1459 } 1460 #endif 1461 DPRINTFN(10, "--- TD dump end ---", 0, 0, 0, 0); 1462 1463 for (std = sdone; std; std = stdnext) { 1464 xfer = std->xfer; 1465 stdnext = std->dnext; 1466 DPRINTFN(10, "std=%#jx xfer=%#jx hcpriv=%#jx", (uintptr_t)std, 1467 (uintptr_t)xfer, (uintptr_t)(xfer ? xfer->ux_hcpriv : 0), 1468 0); 1469 if (xfer == NULL) { 1470 /* 1471 * xfer == NULL: There seems to be no xfer associated 1472 * with this TD. It is tailp that happened to end up on 1473 * the done queue. 1474 * Shouldn't happen, but some chips are broken(?). 1475 */ 1476 continue; 1477 } 1478 1479 /* 1480 * Try to claim this xfer for completion. If it has 1481 * already completed or aborted, drop it on the floor. 1482 */ 1483 if (!usbd_xfer_trycomplete(xfer)) 1484 continue; 1485 1486 len = std->len; 1487 if (std->td.td_cbp != 0) 1488 len -= O32TOH(std->td.td_be) - 1489 O32TOH(std->td.td_cbp) + 1; 1490 DPRINTFN(10, "len=%jd, flags=%#jx", len, std->flags, 0, 0); 1491 if (std->flags & OHCI_ADD_LEN) 1492 xfer->ux_actlen += len; 1493 1494 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1495 if (cc == OHCI_CC_NO_ERROR) { 1496 ohci_hash_rem_td(sc, std); 1497 if (std->flags & OHCI_CALL_DONE) { 1498 xfer->ux_status = USBD_NORMAL_COMPLETION; 1499 usb_transfer_complete(xfer); 1500 } 1501 } else { 1502 /* 1503 * Endpoint is halted. First unlink all the TDs 1504 * belonging to the failed transfer, and then restart 1505 * the endpoint. 1506 */ 1507 ohci_soft_td_t *p, *n; 1508 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1509 1510 DPRINTFN(10, "error cc=%jd", cc, 0, 0, 0); 1511 1512 /* remove xfer's TDs from the hash */ 1513 for (p = std; p->xfer == xfer; p = n) { 1514 n = p->nexttd; 1515 ohci_hash_rem_td(sc, p); 1516 } 1517 1518 ohci_soft_ed_t *sed = opipe->sed; 1519 1520 /* clear halt and TD chain, preserving toggle carry */ 1521 sed->ed.ed_headp = HTOO32(p->physaddr | 1522 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 1523 usb_syncmem(&sed->dma, 1524 sed->offs + offsetof(ohci_ed_t, ed_headp), 1525 sizeof(sed->ed.ed_headp), 1526 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1527 1528 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1529 1530 if (cc == OHCI_CC_DATA_UNDERRUN) 1531 xfer->ux_status = USBD_NORMAL_COMPLETION; 1532 else if (cc == OHCI_CC_STALL) 1533 xfer->ux_status = USBD_STALLED; 1534 else 1535 xfer->ux_status = USBD_IOERROR; 1536 usb_transfer_complete(xfer); 1537 } 1538 } 1539 DPRINTFN(10, "--- ITD dump start ---", 0, 0, 0, 0); 1540 #ifdef OHCI_DEBUG 1541 if (ohcidebug >= 10) { 1542 for (sitd = sidone; sitd; sitd = sitd->dnext) 1543 ohci_dump_itd(sc, sitd); 1544 } 1545 #endif 1546 DPRINTFN(10, "--- ITD dump end ---", 0, 0, 0, 0); 1547 1548 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1549 xfer = sitd->xfer; 1550 sitdnext = sitd->dnext; 1551 DPRINTFN(1, "sitd=%#jx xfer=%#jx hcpriv=%#jx", (uintptr_t)sitd, 1552 (uintptr_t)xfer, (uintptr_t)(xfer ? xfer->ux_hcpriv : 0), 1553 0); 1554 if (xfer == NULL) 1555 continue; 1556 1557 /* 1558 * Try to claim this xfer for completion. If it has 1559 * already completed or aborted, drop it on the floor. 1560 */ 1561 if (!usbd_xfer_trycomplete(xfer)) 1562 continue; 1563 1564 KASSERT(!sitd->isdone); 1565 #ifdef DIAGNOSTIC 1566 sitd->isdone = true; 1567 #endif 1568 if (sitd->flags & OHCI_CALL_DONE) { 1569 ohci_soft_itd_t *next; 1570 1571 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1572 opipe->isoc.inuse -= xfer->ux_nframes; 1573 uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc-> 1574 bEndpointAddress); 1575 xfer->ux_status = USBD_NORMAL_COMPLETION; 1576 actlen = 0; 1577 for (i = 0, sitd = xfer->ux_hcpriv;; 1578 sitd = next) { 1579 next = sitd->nextitd; 1580 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1581 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1582 xfer->ux_status = USBD_IOERROR; 1583 /* For input, update frlengths with actual */ 1584 /* XXX anything necessary for output? */ 1585 if (uedir == UE_DIR_IN && 1586 xfer->ux_status == USBD_NORMAL_COMPLETION) { 1587 iframes = OHCI_ITD_GET_FC(O32TOH( 1588 sitd->itd.itd_flags)); 1589 for (j = 0; j < iframes; i++, j++) { 1590 len = O16TOH(sitd-> 1591 itd.itd_offset[j]); 1592 if ((OHCI_ITD_PSW_GET_CC(len) & 1593 OHCI_CC_NOT_ACCESSED_MASK) 1594 == OHCI_CC_NOT_ACCESSED) 1595 len = 0; 1596 else 1597 len = OHCI_ITD_PSW_LENGTH(len); 1598 xfer->ux_frlengths[i] = len; 1599 actlen += len; 1600 } 1601 } 1602 if (sitd->flags & OHCI_CALL_DONE) 1603 break; 1604 ohci_hash_rem_itd(sc, sitd); 1605 1606 } 1607 ohci_hash_rem_itd(sc, sitd); 1608 if (uedir == UE_DIR_IN && 1609 xfer->ux_status == USBD_NORMAL_COMPLETION) 1610 xfer->ux_actlen = actlen; 1611 xfer->ux_hcpriv = NULL; 1612 1613 usb_transfer_complete(xfer); 1614 } 1615 } 1616 1617 DPRINTFN(10, "done", 0, 0, 0, 0); 1618 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1619 } 1620 1621 void 1622 ohci_device_ctrl_done(struct usbd_xfer *xfer) 1623 { 1624 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1625 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1626 int len = UGETW(xfer->ux_request.wLength); 1627 int isread = (xfer->ux_request.bmRequestType & UT_READ); 1628 1629 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1630 DPRINTFN(10, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 1631 1632 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1633 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 1634 1635 if (len) 1636 usb_syncmem(&xfer->ux_dmabuf, 0, len, 1637 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1638 usb_syncmem(&opipe->ctrl.reqdma, 0, 1639 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1640 } 1641 1642 void 1643 ohci_device_intr_done(struct usbd_xfer *xfer) 1644 { 1645 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1646 int isread = 1647 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1648 1649 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1650 DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, 1651 xfer->ux_actlen, 0, 0); 1652 1653 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1654 1655 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1656 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1657 } 1658 1659 void 1660 ohci_device_bulk_done(struct usbd_xfer *xfer) 1661 { 1662 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1663 1664 int isread = 1665 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1666 1667 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1668 1669 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1670 DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 1671 0, 0); 1672 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1673 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1674 } 1675 1676 Static void 1677 ohci_rhsc_softint(void *arg) 1678 { 1679 ohci_softc_t *sc = arg; 1680 1681 mutex_enter(&sc->sc_lock); 1682 1683 ohci_rhsc(sc, sc->sc_intrxfer); 1684 1685 /* Do not allow RHSC interrupts > 1 per second */ 1686 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1687 1688 mutex_exit(&sc->sc_lock); 1689 } 1690 1691 void 1692 ohci_rhsc(ohci_softc_t *sc, struct usbd_xfer *xfer) 1693 { 1694 u_char *p; 1695 int i, m; 1696 int hstatus __unused; 1697 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1698 1699 KASSERT(mutex_owned(&sc->sc_lock)); 1700 1701 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1702 DPRINTF("sc=%#jx xfer=%#jx hstatus=0x%08jx", (uintptr_t)sc, 1703 (uintptr_t)xfer, hstatus, 0); 1704 1705 if (xfer == NULL) { 1706 /* Just ignore the change. */ 1707 return; 1708 } 1709 KASSERT(xfer == sc->sc_intrxfer); 1710 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 1711 1712 p = xfer->ux_buf; 1713 m = uimin(sc->sc_noport, xfer->ux_length * 8 - 1); 1714 memset(p, 0, xfer->ux_length); 1715 for (i = 1; i <= m; i++) { 1716 /* Pick out CHANGE bits from the status reg. */ 1717 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1718 p[i/8] |= 1 << (i%8); 1719 } 1720 DPRINTF("change=0x%02jx", *p, 0, 0, 0); 1721 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 1722 xfer->ux_actlen = xfer->ux_length; 1723 xfer->ux_status = USBD_NORMAL_COMPLETION; 1724 1725 usb_transfer_complete(xfer); 1726 } 1727 1728 void 1729 ohci_root_intr_done(struct usbd_xfer *xfer) 1730 { 1731 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1732 1733 KASSERT(mutex_owned(&sc->sc_lock)); 1734 1735 /* Claim the xfer so it doesn't get completed again. */ 1736 KASSERT(sc->sc_intrxfer == xfer); 1737 KASSERT(xfer->ux_status != USBD_IN_PROGRESS); 1738 sc->sc_intrxfer = NULL; 1739 } 1740 1741 void 1742 ohci_poll(struct usbd_bus *bus) 1743 { 1744 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1745 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1746 1747 #ifdef OHCI_DEBUG 1748 static int last; 1749 int new; 1750 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1751 if (new != last) { 1752 DPRINTFN(10, "intrs=0x%04jx", new, 0, 0, 0); 1753 last = new; 1754 } 1755 #endif 1756 sc->sc_eintrs |= OHCI_WDH; 1757 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1758 mutex_spin_enter(&sc->sc_intr_lock); 1759 ohci_intr1(sc); 1760 mutex_spin_exit(&sc->sc_intr_lock); 1761 } 1762 } 1763 1764 /* 1765 * Add an ED to the schedule. Called with USB lock held. 1766 */ 1767 Static void 1768 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1769 { 1770 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1771 DPRINTFN(8, "sed=%#jx head=%#jx", (uintptr_t)sed, (uintptr_t)head, 0, 1772 0); 1773 1774 KASSERT(mutex_owned(&sc->sc_lock)); 1775 1776 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1777 sizeof(head->ed.ed_nexted), 1778 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1779 sed->next = head->next; 1780 sed->ed.ed_nexted = head->ed.ed_nexted; 1781 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1782 sizeof(sed->ed.ed_nexted), 1783 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1784 head->next = sed; 1785 head->ed.ed_nexted = HTOO32(sed->physaddr); 1786 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1787 sizeof(head->ed.ed_nexted), 1788 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1789 } 1790 1791 /* 1792 * Remove an ED from the schedule. Called with USB lock held. 1793 */ 1794 Static void 1795 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1796 { 1797 ohci_soft_ed_t *p; 1798 1799 KASSERT(mutex_owned(&sc->sc_lock)); 1800 1801 /* XXX */ 1802 for (p = head; p != NULL && p->next != sed; p = p->next) 1803 ; 1804 KASSERT(p != NULL); 1805 1806 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1807 sizeof(sed->ed.ed_nexted), 1808 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1809 p->next = sed->next; 1810 p->ed.ed_nexted = sed->ed.ed_nexted; 1811 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1812 sizeof(p->ed.ed_nexted), 1813 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1814 } 1815 1816 /* 1817 * When a transfer is completed the TD is added to the done queue by 1818 * the host controller. This queue is the processed by software. 1819 * Unfortunately the queue contains the physical address of the TD 1820 * and we have no simple way to translate this back to a kernel address. 1821 * To make the translation possible (and fast) we use a hash table of 1822 * TDs currently in the schedule. The physical address is used as the 1823 * hash value. 1824 */ 1825 1826 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1827 /* Called with USB lock held. */ 1828 void 1829 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1830 { 1831 int h = HASH(std->physaddr); 1832 1833 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1834 1835 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1836 } 1837 1838 /* Called with USB lock held. */ 1839 void 1840 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1841 { 1842 1843 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1844 1845 LIST_REMOVE(std, hnext); 1846 } 1847 1848 ohci_soft_td_t * 1849 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1850 { 1851 int h = HASH(a); 1852 ohci_soft_td_t *std; 1853 1854 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1855 std != NULL; 1856 std = LIST_NEXT(std, hnext)) 1857 if (std->physaddr == a) 1858 return std; 1859 return NULL; 1860 } 1861 1862 /* Called with USB lock held. */ 1863 void 1864 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1865 { 1866 int h = HASH(sitd->physaddr); 1867 1868 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1869 1870 KASSERT(mutex_owned(&sc->sc_lock)); 1871 1872 DPRINTFN(10, "sitd=%#jx physaddr=0x%08jx", 1873 (uintptr_t)sitd, (u_long)sitd->physaddr, 0, 0); 1874 1875 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1876 } 1877 1878 /* Called with USB lock held. */ 1879 void 1880 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1881 { 1882 1883 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1884 1885 KASSERT(mutex_owned(&sc->sc_lock)); 1886 1887 DPRINTFN(10, "sitd=%#jx physaddr=0x%08jx", (uintptr_t)sitd, 1888 sitd->physaddr, 0, 0); 1889 1890 LIST_REMOVE(sitd, hnext); 1891 } 1892 1893 ohci_soft_itd_t * 1894 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1895 { 1896 int h = HASH(a); 1897 ohci_soft_itd_t *sitd; 1898 1899 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1900 sitd != NULL; 1901 sitd = LIST_NEXT(sitd, hnext)) 1902 if (sitd->physaddr == a) 1903 return sitd; 1904 return NULL; 1905 } 1906 1907 #ifdef OHCI_DEBUG 1908 void 1909 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 1910 { 1911 for (; std; std = std->nexttd) { 1912 ohci_dump_td(sc, std); 1913 KASSERTMSG(std->nexttd == NULL || std != std->nexttd, 1914 "std %p next %p", std, std->nexttd); 1915 } 1916 } 1917 1918 void 1919 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1920 { 1921 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1922 1923 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1924 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1925 1926 uint32_t flags = O32TOH(std->td.td_flags); 1927 DPRINTF("TD(%#jx) at 0x%08jx:", (uintptr_t)std, std->physaddr, 0, 0); 1928 DPRINTF(" round=%jd DP=%jx DI=%jx T=%jx", 1929 !!(flags & OHCI_TD_R), 1930 __SHIFTOUT(flags, OHCI_TD_DP_MASK), 1931 OHCI_TD_GET_DI(flags), 1932 __SHIFTOUT(flags, OHCI_TD_TOGGLE_MASK)); 1933 DPRINTF(" EC=%jd CC=%jd", OHCI_TD_GET_EC(flags), 1934 OHCI_TD_GET_CC(flags), 0, 0); 1935 DPRINTF(" td_cbp=0x%08jx td_nexttd=0x%08jx td_be=0x%08jx", 1936 (u_long)O32TOH(std->td.td_cbp), 1937 (u_long)O32TOH(std->td.td_nexttd), 1938 (u_long)O32TOH(std->td.td_be), 0); 1939 } 1940 1941 void 1942 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1943 { 1944 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1945 1946 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1947 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1948 1949 uint32_t flags = O32TOH(sitd->itd.itd_flags); 1950 DPRINTF("ITD(%#jx) at 0x%08jx", (uintptr_t)sitd, sitd->physaddr, 0, 0); 1951 DPRINTF(" sf=%jd di=%jd fc=%jd cc=%jd", 1952 OHCI_ITD_GET_SF(flags), OHCI_ITD_GET_DI(flags), 1953 OHCI_ITD_GET_FC(flags), OHCI_ITD_GET_CC(flags)); 1954 DPRINTF(" bp0=0x%08jx next=0x%08jx be=0x%08jx", 1955 O32TOH(sitd->itd.itd_bp0), 1956 O32TOH(sitd->itd.itd_nextitd), 1957 O32TOH(sitd->itd.itd_be), 0); 1958 CTASSERT(OHCI_ITD_NOFFSET == 8); 1959 DPRINTF(" offs[0] = 0x%04jx offs[1] = 0x%04jx " 1960 "offs[2] = 0x%04jx offs[3] = 0x%04jx", 1961 O16TOH(sitd->itd.itd_offset[0]), 1962 O16TOH(sitd->itd.itd_offset[1]), 1963 O16TOH(sitd->itd.itd_offset[2]), 1964 O16TOH(sitd->itd.itd_offset[3])); 1965 DPRINTF(" offs[4] = 0x%04jx offs[5] = 0x%04jx " 1966 "offs[6] = 0x%04jx offs[7] = 0x%04jx", 1967 O16TOH(sitd->itd.itd_offset[4]), 1968 O16TOH(sitd->itd.itd_offset[5]), 1969 O16TOH(sitd->itd.itd_offset[6]), 1970 O16TOH(sitd->itd.itd_offset[7])); 1971 } 1972 1973 void 1974 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1975 { 1976 for (; sitd; sitd = sitd->nextitd) 1977 ohci_dump_itd(sc, sitd); 1978 } 1979 1980 void 1981 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 1982 { 1983 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1984 1985 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 1986 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1987 1988 uint32_t flags = O32TOH(sed->ed.ed_flags); 1989 DPRINTF("ED(%#jx) at 0x%08jx:", (uintptr_t)sed, sed->physaddr, 0, 0); 1990 DPRINTF(" addr=%jd endpt=%jd maxp=%jd", 1991 OHCI_ED_GET_FA(flags), 1992 OHCI_ED_GET_EN(flags), 1993 OHCI_ED_GET_MAXP(flags), 1994 0); 1995 DPRINTF(" dir=%jd speed=%jd skip=%jd iso=%jd", 1996 __SHIFTOUT(flags, OHCI_ED_DIR_MASK), 1997 !!(flags & OHCI_ED_SPEED), 1998 !!(flags & OHCI_ED_SKIP), 1999 !!(flags & OHCI_ED_FORMAT_ISO)); 2000 DPRINTF(" tailp=0x%08jx", (u_long)O32TOH(sed->ed.ed_tailp), 2001 0, 0, 0); 2002 DPRINTF(" headp=0x%08jx nexted=0x%08jx halted=%jd carry=%jd", 2003 O32TOH(sed->ed.ed_headp), O32TOH(sed->ed.ed_nexted), 2004 !!(O32TOH(sed->ed.ed_headp) & OHCI_HALTED), 2005 !!(O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 2006 } 2007 #endif 2008 2009 usbd_status 2010 ohci_open(struct usbd_pipe *pipe) 2011 { 2012 struct usbd_device *dev = pipe->up_dev; 2013 struct usbd_bus *bus = dev->ud_bus; 2014 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2015 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 2016 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2017 uint8_t addr = dev->ud_addr; 2018 uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2019 ohci_soft_ed_t *sed; 2020 ohci_soft_td_t *std; 2021 ohci_soft_itd_t *sitd; 2022 ohci_physaddr_t tdphys; 2023 uint32_t fmt; 2024 usbd_status err = USBD_NOMEM; 2025 int ival; 2026 2027 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2028 DPRINTFN(1, "pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, 2029 addr, ed->bEndpointAddress, bus->ub_rhaddr); 2030 2031 if (sc->sc_dying) { 2032 return USBD_IOERROR; 2033 } 2034 2035 std = NULL; 2036 sed = NULL; 2037 2038 if (addr == bus->ub_rhaddr) { 2039 switch (ed->bEndpointAddress) { 2040 case USB_CONTROL_ENDPOINT: 2041 pipe->up_methods = &roothub_ctrl_methods; 2042 break; 2043 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 2044 pipe->up_methods = &ohci_root_intr_methods; 2045 break; 2046 default: 2047 err = USBD_INVAL; 2048 goto bad; 2049 } 2050 } else { 2051 sed = ohci_alloc_sed(sc); 2052 if (sed == NULL) 2053 goto bad; 2054 opipe->sed = sed; 2055 if (xfertype == UE_ISOCHRONOUS) { 2056 sitd = ohci_alloc_sitd(sc); 2057 if (sitd == NULL) 2058 goto bad; 2059 2060 opipe->tail.itd = sitd; 2061 tdphys = sitd->physaddr; 2062 fmt = OHCI_ED_FORMAT_ISO; 2063 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2064 fmt |= OHCI_ED_DIR_IN; 2065 else 2066 fmt |= OHCI_ED_DIR_OUT; 2067 } else { 2068 std = ohci_alloc_std(sc); 2069 if (std == NULL) 2070 goto bad; 2071 2072 opipe->tail.td = std; 2073 tdphys = std->physaddr; 2074 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2075 } 2076 sed->ed.ed_flags = HTOO32( 2077 OHCI_ED_SET_FA(addr) | 2078 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2079 (dev->ud_speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2080 fmt | 2081 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2082 sed->ed.ed_headp = HTOO32(tdphys | 2083 (pipe->up_endpoint->ue_toggle ? OHCI_TOGGLECARRY : 0)); 2084 sed->ed.ed_tailp = HTOO32(tdphys); 2085 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2086 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2087 2088 switch (xfertype) { 2089 case UE_CONTROL: 2090 pipe->up_methods = &ohci_device_ctrl_methods; 2091 err = usb_allocmem(&sc->sc_bus, 2092 sizeof(usb_device_request_t), 0, 2093 USBMALLOC_COHERENT, &opipe->ctrl.reqdma); 2094 if (err) 2095 goto bad; 2096 mutex_enter(&sc->sc_lock); 2097 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2098 mutex_exit(&sc->sc_lock); 2099 break; 2100 case UE_INTERRUPT: 2101 pipe->up_methods = &ohci_device_intr_methods; 2102 ival = pipe->up_interval; 2103 if (ival == USBD_DEFAULT_INTERVAL) 2104 ival = ed->bInterval; 2105 err = ohci_device_setintr(sc, opipe, ival); 2106 if (err) 2107 goto bad; 2108 break; 2109 case UE_ISOCHRONOUS: 2110 pipe->up_serialise = false; 2111 pipe->up_methods = &ohci_device_isoc_methods; 2112 return ohci_setup_isoc(pipe); 2113 case UE_BULK: 2114 pipe->up_methods = &ohci_device_bulk_methods; 2115 mutex_enter(&sc->sc_lock); 2116 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2117 mutex_exit(&sc->sc_lock); 2118 break; 2119 } 2120 } 2121 2122 return USBD_NORMAL_COMPLETION; 2123 2124 bad: 2125 if (std != NULL) { 2126 ohci_free_std(sc, std); 2127 } 2128 if (sed != NULL) 2129 ohci_free_sed(sc, sed); 2130 return err; 2131 2132 } 2133 2134 /* 2135 * Close a reqular pipe. 2136 * Assumes that there are no pending transactions. 2137 */ 2138 void 2139 ohci_close_pipe(struct usbd_pipe *pipe, ohci_soft_ed_t *head) 2140 { 2141 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2142 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2143 ohci_soft_ed_t *sed = opipe->sed; 2144 2145 KASSERT(mutex_owned(&sc->sc_lock)); 2146 2147 #ifdef DIAGNOSTIC 2148 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2149 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2150 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2151 ohci_soft_td_t *std; 2152 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2153 printf("ohci_close_pipe: pipe not empty sed=%p hd=%#x " 2154 "tl=%#x pipe=%p, std=%p\n", sed, 2155 (int)O32TOH(sed->ed.ed_headp), 2156 (int)O32TOH(sed->ed.ed_tailp), 2157 pipe, std); 2158 #ifdef OHCI_DEBUG 2159 usbd_dump_pipe(&opipe->pipe); 2160 ohci_dump_ed(sc, sed); 2161 if (std) 2162 ohci_dump_td(sc, std); 2163 #endif 2164 usb_delay_ms(&sc->sc_bus, 2); 2165 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2166 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2167 printf("ohci_close_pipe: pipe still not empty\n"); 2168 } 2169 #endif 2170 ohci_rem_ed(sc, sed, head); 2171 /* Make sure the host controller is not touching this ED */ 2172 usb_delay_ms(&sc->sc_bus, 1); 2173 pipe->up_endpoint->ue_toggle = 2174 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2175 ohci_free_sed_locked(sc, opipe->sed); 2176 } 2177 2178 /* 2179 * Arrange for the hardware to tells us that it is not still processing 2180 * the TDs by setting the sKip bit and requesting a SOF interrupt 2181 * 2182 * Once we see the SOF interrupt we can check the transfer TDs/iTDs to see if 2183 * they've been processed and either 2184 * a) if they're unused recover them for later use, or 2185 * b) if they've been used allocate new TD/iTDs to replace those 2186 * used. The softint handler will free the old ones. 2187 */ 2188 void 2189 ohci_abortx(struct usbd_xfer *xfer) 2190 { 2191 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2192 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2193 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2194 ohci_soft_ed_t *sed = opipe->sed; 2195 ohci_soft_td_t *p, *n; 2196 ohci_physaddr_t headp; 2197 int hit; 2198 2199 DPRINTF("xfer=%#jx pipe=%#jx sed=%#jx", (uintptr_t)xfer, 2200 (uintptr_t)opipe, (uintptr_t)sed, 0); 2201 2202 KASSERT(mutex_owned(&sc->sc_lock)); 2203 ASSERT_SLEEPABLE(); 2204 2205 KASSERTMSG((xfer->ux_status == USBD_CANCELLED || 2206 xfer->ux_status == USBD_TIMEOUT), 2207 "bad abort status: %d", xfer->ux_status); 2208 2209 /* 2210 * If we're dying, skip the hardware action and just notify the 2211 * software that we're done. 2212 */ 2213 if (sc->sc_dying) { 2214 DPRINTFN(4, "xfer %#jx dying %ju", (uintptr_t)xfer, 2215 xfer->ux_status, 0, 0); 2216 goto dying; 2217 } 2218 2219 /* 2220 * HC Step 1: Unless the endpoint is already halted, we set the endpoint 2221 * descriptor sKip bit and wait for hardware to complete processing. 2222 * 2223 * This includes ensuring that any TDs of the transfer that got onto 2224 * the done list are also removed. We ensure this by waiting for 2225 * both a WDH and SOF interrupt. 2226 */ 2227 DPRINTFN(1, "stop ed=%#jx", (uintptr_t)sed, 0, 0, 0); 2228 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2229 sizeof(sed->ed.ed_flags), 2230 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2231 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2232 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2233 sizeof(sed->ed.ed_flags), 2234 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2235 2236 /* 2237 * HC Step 2: Wait until we know hardware has finished any possible 2238 * use of the xfer. 2239 */ 2240 /* Hardware finishes in 1ms */ 2241 usb_delay_ms_locked(opipe->pipe.up_dev->ud_bus, 20, &sc->sc_lock); 2242 2243 /* 2244 * HC Step 3: Remove any vestiges of the xfer from the hardware. 2245 * The complication here is that the hardware may have executed 2246 * beyond the xfer we're trying to abort. So as we're scanning 2247 * the TDs of this xfer we check if the hardware points to 2248 * any of them. 2249 */ 2250 p = xfer->ux_hcpriv; 2251 KASSERT(p); 2252 2253 #ifdef OHCI_DEBUG 2254 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2255 2256 if (ohcidebug >= 2) { 2257 DPRINTF("sed:", 0, 0, 0, 0); 2258 ohci_dump_ed(sc, sed); 2259 ohci_dump_tds(sc, p); 2260 } 2261 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2262 #endif 2263 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2264 hit = 0; 2265 for (; p->xfer == xfer; p = n) { 2266 hit |= headp == p->physaddr; 2267 n = p->nexttd; 2268 ohci_hash_rem_td(sc, p); 2269 } 2270 /* Zap headp register if hardware pointed inside the xfer. */ 2271 if (hit) { 2272 DPRINTFN(1, "set hd=0x%08jx, tl=0x%08jx", (int)p->physaddr, 2273 (int)O32TOH(sed->ed.ed_tailp), 0, 0); 2274 /* unlink TDs, preserving toggle carry */ 2275 sed->ed.ed_headp = HTOO32(p->physaddr | 2276 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 2277 usb_syncmem(&sed->dma, 2278 sed->offs + offsetof(ohci_ed_t, ed_headp), 2279 sizeof(sed->ed.ed_headp), 2280 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2281 } else { 2282 DPRINTFN(1, "no hit", 0, 0, 0, 0); 2283 } 2284 2285 /* 2286 * HC Step 4: Turn on hardware again. 2287 */ 2288 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2289 sizeof(sed->ed.ed_flags), 2290 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2291 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2292 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2293 sizeof(sed->ed.ed_flags), 2294 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2295 2296 /* 2297 * Final step: Notify completion to waiting xfers. 2298 */ 2299 dying: 2300 usb_transfer_complete(xfer); 2301 DPRINTFN(14, "end", 0, 0, 0, 0); 2302 2303 KASSERT(mutex_owned(&sc->sc_lock)); 2304 } 2305 2306 /* 2307 * Data structures and routines to emulate the root hub. 2308 */ 2309 Static int 2310 ohci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2311 void *buf, int buflen) 2312 { 2313 ohci_softc_t *sc = OHCI_BUS2SC(bus); 2314 usb_port_status_t ps; 2315 uint16_t len, value, index; 2316 int l, totlen = 0; 2317 int port, i; 2318 uint32_t v; 2319 2320 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2321 2322 if (sc->sc_dying) 2323 return -1; 2324 2325 DPRINTFN(4, "type=0x%02jx request=%02jx", req->bmRequestType, 2326 req->bRequest, 0, 0); 2327 2328 len = UGETW(req->wLength); 2329 value = UGETW(req->wValue); 2330 index = UGETW(req->wIndex); 2331 2332 #define C(x,y) ((x) | ((y) << 8)) 2333 switch (C(req->bRequest, req->bmRequestType)) { 2334 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2335 DPRINTFN(8, "wValue=0x%04jx", value, 0, 0, 0); 2336 if (len == 0) 2337 break; 2338 switch (value) { 2339 #define sd ((usb_string_descriptor_t *)buf) 2340 case C(2, UDESC_STRING): 2341 /* Product */ 2342 totlen = usb_makestrdesc(sd, len, "OHCI root hub"); 2343 break; 2344 #undef sd 2345 default: 2346 /* default from usbroothub */ 2347 return buflen; 2348 } 2349 break; 2350 2351 /* Hub requests */ 2352 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2353 break; 2354 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2355 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", 2356 index, value, 0, 0); 2357 if (index < 1 || index > sc->sc_noport) { 2358 return -1; 2359 } 2360 port = OHCI_RH_PORT_STATUS(index); 2361 switch(value) { 2362 case UHF_PORT_ENABLE: 2363 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2364 break; 2365 case UHF_PORT_SUSPEND: 2366 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2367 break; 2368 case UHF_PORT_POWER: 2369 /* Yes, writing to the LOW_SPEED bit clears power. */ 2370 OWRITE4(sc, port, UPS_LOW_SPEED); 2371 break; 2372 case UHF_C_PORT_CONNECTION: 2373 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2374 break; 2375 case UHF_C_PORT_ENABLE: 2376 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2377 break; 2378 case UHF_C_PORT_SUSPEND: 2379 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2380 break; 2381 case UHF_C_PORT_OVER_CURRENT: 2382 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2383 break; 2384 case UHF_C_PORT_RESET: 2385 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2386 break; 2387 default: 2388 return -1; 2389 } 2390 switch(value) { 2391 case UHF_C_PORT_CONNECTION: 2392 case UHF_C_PORT_ENABLE: 2393 case UHF_C_PORT_SUSPEND: 2394 case UHF_C_PORT_OVER_CURRENT: 2395 case UHF_C_PORT_RESET: 2396 /* Enable RHSC interrupt if condition is cleared. */ 2397 if ((OREAD4(sc, port) >> 16) == 0) 2398 ohci_rhsc_enable(sc); 2399 break; 2400 default: 2401 break; 2402 } 2403 break; 2404 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2405 if (len == 0) 2406 break; 2407 if ((value & 0xff) != 0) { 2408 return -1; 2409 } 2410 usb_hub_descriptor_t hubd; 2411 2412 totlen = uimin(buflen, sizeof(hubd)); 2413 memcpy(&hubd, buf, totlen); 2414 2415 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2416 hubd.bNbrPorts = sc->sc_noport; 2417 USETW(hubd.wHubCharacteristics, 2418 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2419 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2420 /* XXX overcurrent */ 2421 ); 2422 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2423 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2424 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2425 hubd.DeviceRemovable[i++] = (uint8_t)v; 2426 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2427 totlen = uimin(totlen, hubd.bDescLength); 2428 memcpy(buf, &hubd, totlen); 2429 break; 2430 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2431 if (len != 4) { 2432 return -1; 2433 } 2434 memset(buf, 0, len); /* ? XXX */ 2435 totlen = len; 2436 break; 2437 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2438 DPRINTFN(8, "get port status i=%jd", index, 0, 0, 0); 2439 if (index < 1 || index > sc->sc_noport) { 2440 return -1; 2441 } 2442 if (len != 4) { 2443 return -1; 2444 } 2445 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2446 DPRINTFN(8, "port status=0x%04jx", v, 0, 0, 0); 2447 USETW(ps.wPortStatus, v); 2448 USETW(ps.wPortChange, v >> 16); 2449 totlen = uimin(len, sizeof(ps)); 2450 memcpy(buf, &ps, totlen); 2451 break; 2452 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2453 return -1; 2454 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2455 break; 2456 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2457 if (index < 1 || index > sc->sc_noport) { 2458 return -1; 2459 } 2460 port = OHCI_RH_PORT_STATUS(index); 2461 switch(value) { 2462 case UHF_PORT_ENABLE: 2463 OWRITE4(sc, port, UPS_PORT_ENABLED); 2464 break; 2465 case UHF_PORT_SUSPEND: 2466 OWRITE4(sc, port, UPS_SUSPEND); 2467 break; 2468 case UHF_PORT_RESET: 2469 DPRINTFN(5, "reset port %jd", index, 0, 0, 0); 2470 OWRITE4(sc, port, UPS_RESET); 2471 for (i = 0; i < 5; i++) { 2472 usb_delay_ms(&sc->sc_bus, 2473 USB_PORT_ROOT_RESET_DELAY); 2474 if (sc->sc_dying) { 2475 return -1; 2476 } 2477 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2478 break; 2479 } 2480 DPRINTFN(8, "port %jd reset, status = 0x%04jx", index, 2481 OREAD4(sc, port), 0, 0); 2482 break; 2483 case UHF_PORT_POWER: 2484 DPRINTFN(2, "set port power %jd", index, 0, 0, 0); 2485 OWRITE4(sc, port, UPS_PORT_POWER); 2486 break; 2487 default: 2488 return -1; 2489 } 2490 break; 2491 default: 2492 /* default from usbroothub */ 2493 return buflen; 2494 } 2495 2496 return totlen; 2497 } 2498 2499 Static usbd_status 2500 ohci_root_intr_transfer(struct usbd_xfer *xfer) 2501 { 2502 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2503 usbd_status err; 2504 2505 /* Insert last in queue. */ 2506 mutex_enter(&sc->sc_lock); 2507 err = usb_insert_transfer(xfer); 2508 mutex_exit(&sc->sc_lock); 2509 if (err) 2510 return err; 2511 2512 /* Pipe isn't running, start first */ 2513 return ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2514 } 2515 2516 Static usbd_status 2517 ohci_root_intr_start(struct usbd_xfer *xfer) 2518 { 2519 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2520 const bool polling = sc->sc_bus.ub_usepolling; 2521 2522 if (sc->sc_dying) 2523 return USBD_IOERROR; 2524 2525 if (!polling) 2526 mutex_enter(&sc->sc_lock); 2527 KASSERT(sc->sc_intrxfer == NULL); 2528 sc->sc_intrxfer = xfer; 2529 xfer->ux_status = USBD_IN_PROGRESS; 2530 if (!polling) 2531 mutex_exit(&sc->sc_lock); 2532 2533 return USBD_IN_PROGRESS; 2534 } 2535 2536 /* Abort a root interrupt request. */ 2537 Static void 2538 ohci_root_intr_abort(struct usbd_xfer *xfer) 2539 { 2540 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2541 2542 KASSERT(mutex_owned(&sc->sc_lock)); 2543 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2544 2545 /* If xfer has already completed, nothing to do here. */ 2546 if (sc->sc_intrxfer == NULL) 2547 return; 2548 2549 /* 2550 * Otherwise, sc->sc_intrxfer had better be this transfer. 2551 * Cancel it. 2552 */ 2553 KASSERT(sc->sc_intrxfer == xfer); 2554 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 2555 xfer->ux_status = USBD_CANCELLED; 2556 usb_transfer_complete(xfer); 2557 } 2558 2559 /* Close the root pipe. */ 2560 Static void 2561 ohci_root_intr_close(struct usbd_pipe *pipe) 2562 { 2563 ohci_softc_t *sc __diagused = OHCI_PIPE2SC(pipe); 2564 2565 KASSERT(mutex_owned(&sc->sc_lock)); 2566 2567 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2568 2569 /* 2570 * Caller must guarantee the xfer has completed first, by 2571 * closing the pipe only after normal completion or an abort. 2572 */ 2573 KASSERT(sc->sc_intrxfer == NULL); 2574 } 2575 2576 /************************/ 2577 2578 int 2579 ohci_device_ctrl_init(struct usbd_xfer *xfer) 2580 { 2581 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2582 usb_device_request_t *req = &xfer->ux_request; 2583 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2584 ohci_soft_td_t *stat, *setup; 2585 int isread = req->bmRequestType & UT_READ; 2586 int len = xfer->ux_bufsize; 2587 int err = ENOMEM; 2588 2589 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2590 2591 setup = ohci_alloc_std(sc); 2592 if (setup == NULL) { 2593 goto bad1; 2594 } 2595 stat = ohci_alloc_std(sc); 2596 if (stat == NULL) { 2597 goto bad2; 2598 } 2599 2600 ox->ox_setup = setup; 2601 ox->ox_stat = stat; 2602 ox->ox_nstd = 0; 2603 2604 /* Set up data transaction */ 2605 if (len != 0) { 2606 err = ohci_alloc_std_chain(sc, xfer, len, isread); 2607 if (err) { 2608 goto bad3; 2609 } 2610 } 2611 return 0; 2612 2613 bad3: 2614 ohci_free_std(sc, stat); 2615 bad2: 2616 ohci_free_std(sc, setup); 2617 bad1: 2618 return err; 2619 } 2620 2621 void 2622 ohci_device_ctrl_fini(struct usbd_xfer *xfer) 2623 { 2624 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2625 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2626 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2627 2628 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2629 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 2630 2631 mutex_enter(&sc->sc_lock); 2632 if (ox->ox_setup != opipe->tail.td) { 2633 ohci_free_std_locked(sc, ox->ox_setup); 2634 } 2635 for (size_t i = 0; i < ox->ox_nstd; i++) { 2636 ohci_soft_td_t *std = ox->ox_stds[i]; 2637 if (std == NULL) 2638 break; 2639 ohci_free_std_locked(sc, std); 2640 } 2641 ohci_free_std_locked(sc, ox->ox_stat); 2642 mutex_exit(&sc->sc_lock); 2643 2644 if (ox->ox_nstd) { 2645 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 2646 kmem_free(ox->ox_stds, sz); 2647 } 2648 } 2649 2650 Static usbd_status 2651 ohci_device_ctrl_transfer(struct usbd_xfer *xfer) 2652 { 2653 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2654 usbd_status err; 2655 2656 /* Insert last in queue. */ 2657 mutex_enter(&sc->sc_lock); 2658 err = usb_insert_transfer(xfer); 2659 mutex_exit(&sc->sc_lock); 2660 if (err) 2661 return err; 2662 2663 /* Pipe isn't running, start first */ 2664 return ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2665 } 2666 2667 Static usbd_status 2668 ohci_device_ctrl_start(struct usbd_xfer *xfer) 2669 { 2670 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2671 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2672 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2673 usb_device_request_t *req = &xfer->ux_request; 2674 struct usbd_device *dev __diagused = opipe->pipe.up_dev; 2675 ohci_soft_td_t *setup, *stat, *next, *tail; 2676 ohci_soft_ed_t *sed; 2677 int isread; 2678 int len; 2679 const bool polling = sc->sc_bus.ub_usepolling; 2680 2681 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2682 2683 if (sc->sc_dying) 2684 return USBD_IOERROR; 2685 2686 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2687 2688 isread = req->bmRequestType & UT_READ; 2689 len = UGETW(req->wLength); 2690 2691 DPRINTF("xfer=%#jx len=%jd, addr=%jd, endpt=%jd", (uintptr_t)xfer, len, 2692 dev->ud_addr, opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress); 2693 DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx", 2694 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2695 UGETW(req->wIndex)); 2696 2697 /* Need to take lock here for pipe->tail.td */ 2698 if (!polling) 2699 mutex_enter(&sc->sc_lock); 2700 2701 /* 2702 * Use the pipe "tail" TD as our first and loan our first TD to the 2703 * next transfer 2704 */ 2705 setup = opipe->tail.td; 2706 opipe->tail.td = ox->ox_setup; 2707 ox->ox_setup = setup; 2708 2709 stat = ox->ox_stat; 2710 2711 /* point at sentinel */ 2712 tail = opipe->tail.td; 2713 sed = opipe->sed; 2714 2715 KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->ud_addr, 2716 "address ED %d pipe %d\n", 2717 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->ud_addr); 2718 KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) == 2719 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 2720 "MPL ED %d pipe %d\n", 2721 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), 2722 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 2723 2724 /* next will point to data if len != 0 */ 2725 next = stat; 2726 2727 /* Set up data transaction */ 2728 if (len != 0) { 2729 ohci_soft_td_t *std; 2730 ohci_soft_td_t *end; 2731 2732 next = ox->ox_stds[0]; 2733 ohci_reset_std_chain(sc, xfer, len, isread, next, &end); 2734 2735 end->td.td_nexttd = HTOO32(stat->physaddr); 2736 end->nexttd = stat; 2737 2738 usb_syncmem(&end->dma, end->offs, sizeof(end->td), 2739 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2740 2741 usb_syncmem(&xfer->ux_dmabuf, 0, len, 2742 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2743 std = ox->ox_stds[0]; 2744 /* Start toggle at 1 and then use the carried toggle. */ 2745 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 2746 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 2747 usb_syncmem(&std->dma, 2748 std->offs + offsetof(ohci_td_t, td_flags), 2749 sizeof(std->td.td_flags), 2750 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2751 } 2752 2753 DPRINTFN(8, "setup %#jx data %#jx stat %#jx tail %#jx", 2754 (uintptr_t)setup, 2755 (uintptr_t)(len != 0 ? ox->ox_stds[0] : NULL), (uintptr_t)stat, 2756 (uintptr_t)tail); 2757 KASSERT(opipe->tail.td == tail); 2758 2759 memcpy(KERNADDR(&opipe->ctrl.reqdma, 0), req, sizeof(*req)); 2760 usb_syncmem(&opipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2761 2762 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 2763 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 2764 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->ctrl.reqdma, 0)); 2765 setup->td.td_nexttd = HTOO32(next->physaddr); 2766 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof(*req) - 1); 2767 setup->nexttd = next; 2768 setup->len = 0; 2769 setup->xfer = xfer; 2770 setup->flags = 0; 2771 ohci_hash_add_td(sc, setup); 2772 2773 xfer->ux_hcpriv = setup; 2774 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2775 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2776 2777 stat->td.td_flags = HTOO32( 2778 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 2779 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 2780 stat->td.td_cbp = 0; 2781 stat->td.td_nexttd = HTOO32(tail->physaddr); 2782 stat->td.td_be = 0; 2783 stat->nexttd = tail; 2784 stat->flags = OHCI_CALL_DONE; 2785 stat->len = 0; 2786 stat->xfer = xfer; 2787 ohci_hash_add_td(sc, stat); 2788 2789 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2790 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2791 2792 memset(&tail->td, 0, sizeof(tail->td)); 2793 tail->nexttd = NULL; 2794 tail->xfer = NULL; 2795 2796 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 2797 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2798 2799 #ifdef OHCI_DEBUG 2800 USBHIST_LOGN(ohcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2801 if (ohcidebug >= 5) { 2802 ohci_dump_ed(sc, sed); 2803 ohci_dump_tds(sc, setup); 2804 } 2805 USBHIST_LOGN(ohcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2806 #endif 2807 2808 /* Insert ED in schedule */ 2809 sed->ed.ed_tailp = HTOO32(tail->physaddr); 2810 usb_syncmem(&sed->dma, 2811 sed->offs + offsetof(ohci_ed_t, ed_tailp), 2812 sizeof(sed->ed.ed_tailp), 2813 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2814 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2815 usbd_xfer_schedule_timeout(xfer); 2816 2817 DPRINTF("done", 0, 0, 0, 0); 2818 2819 xfer->ux_status = USBD_IN_PROGRESS; 2820 if (!polling) 2821 mutex_exit(&sc->sc_lock); 2822 2823 return USBD_IN_PROGRESS; 2824 } 2825 2826 /* Abort a device control request. */ 2827 Static void 2828 ohci_device_ctrl_abort(struct usbd_xfer *xfer) 2829 { 2830 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 2831 2832 KASSERT(mutex_owned(&sc->sc_lock)); 2833 2834 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2835 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 2836 usbd_xfer_abort(xfer); 2837 } 2838 2839 /* Close a device control pipe. */ 2840 Static void 2841 ohci_device_ctrl_close(struct usbd_pipe *pipe) 2842 { 2843 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2844 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2845 2846 KASSERT(mutex_owned(&sc->sc_lock)); 2847 2848 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2849 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 2850 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2851 ohci_free_std_locked(sc, opipe->tail.td); 2852 2853 usb_freemem(&sc->sc_bus, &opipe->ctrl.reqdma); 2854 } 2855 2856 /************************/ 2857 2858 Static void 2859 ohci_device_clear_toggle(struct usbd_pipe *pipe) 2860 { 2861 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2862 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2863 2864 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2865 } 2866 2867 Static void 2868 ohci_noop(struct usbd_pipe *pipe) 2869 { 2870 } 2871 2872 Static int 2873 ohci_device_bulk_init(struct usbd_xfer *xfer) 2874 { 2875 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2876 int len = xfer->ux_bufsize; 2877 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2878 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2879 int err; 2880 2881 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2882 2883 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2884 2885 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 2886 len, isread, xfer->ux_flags); 2887 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 2888 2889 /* Allocate a chain of new TDs (including a new tail). */ 2890 err = ohci_alloc_std_chain(sc, xfer, len, isread); 2891 if (err) 2892 return err; 2893 2894 return 0; 2895 } 2896 2897 Static void 2898 ohci_device_bulk_fini(struct usbd_xfer *xfer) 2899 { 2900 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2901 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2902 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2903 2904 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2905 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 2906 2907 mutex_enter(&sc->sc_lock); 2908 for (size_t i = 0; i < ox->ox_nstd; i++) { 2909 ohci_soft_td_t *std = ox->ox_stds[i]; 2910 if (std == NULL) 2911 break; 2912 if (std != opipe->tail.td) 2913 ohci_free_std_locked(sc, std); 2914 } 2915 mutex_exit(&sc->sc_lock); 2916 2917 if (ox->ox_nstd) { 2918 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 2919 kmem_free(ox->ox_stds, sz); 2920 } 2921 } 2922 2923 Static usbd_status 2924 ohci_device_bulk_transfer(struct usbd_xfer *xfer) 2925 { 2926 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2927 usbd_status err; 2928 2929 /* Insert last in queue. */ 2930 mutex_enter(&sc->sc_lock); 2931 err = usb_insert_transfer(xfer); 2932 mutex_exit(&sc->sc_lock); 2933 if (err) 2934 return err; 2935 2936 /* Pipe isn't running, start first */ 2937 return ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2938 } 2939 2940 Static usbd_status 2941 ohci_device_bulk_start(struct usbd_xfer *xfer) 2942 { 2943 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2944 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2945 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2946 ohci_soft_td_t *last; 2947 ohci_soft_td_t *data, *tail, *tdp; 2948 ohci_soft_ed_t *sed; 2949 int len, isread, endpt; 2950 const bool polling = sc->sc_bus.ub_usepolling; 2951 2952 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2953 2954 if (sc->sc_dying) 2955 return USBD_IOERROR; 2956 2957 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2958 2959 len = xfer->ux_length; 2960 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2961 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2962 sed = opipe->sed; 2963 2964 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 2965 len, isread, xfer->ux_flags); 2966 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 2967 2968 if (!polling) 2969 mutex_enter(&sc->sc_lock); 2970 2971 /* 2972 * Use the pipe "tail" TD as our first and loan our first TD to the 2973 * next transfer 2974 */ 2975 data = opipe->tail.td; 2976 opipe->tail.td = ox->ox_stds[0]; 2977 ox->ox_stds[0] = data; 2978 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 2979 2980 /* point at sentinel */ 2981 tail = opipe->tail.td; 2982 memset(&tail->td, 0, sizeof(tail->td)); 2983 tail->nexttd = NULL; 2984 tail->xfer = NULL; 2985 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 2986 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2987 xfer->ux_hcpriv = data; 2988 2989 DPRINTFN(8, "xfer %#jx data %#jx tail %#jx", (uintptr_t)xfer, 2990 (uintptr_t)ox->ox_stds[0], (uintptr_t)tail, 0); 2991 KASSERT(opipe->tail.td == tail); 2992 2993 /* We want interrupt at the end of the transfer. */ 2994 last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 2995 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 2996 last->td.td_nexttd = HTOO32(tail->physaddr); 2997 last->nexttd = tail; 2998 last->flags |= OHCI_CALL_DONE; 2999 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3000 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3001 3002 DPRINTFN(4, "ed_flags=0x%08jx td_flags=0x%08jx " 3003 "td_cbp=0x%08jx td_be=0x%08jx", 3004 (int)O32TOH(sed->ed.ed_flags), 3005 (int)O32TOH(data->td.td_flags), 3006 (int)O32TOH(data->td.td_cbp), 3007 (int)O32TOH(data->td.td_be)); 3008 3009 #ifdef OHCI_DEBUG 3010 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3011 if (ohcidebug >= 5) { 3012 ohci_dump_ed(sc, sed); 3013 ohci_dump_tds(sc, data); 3014 } 3015 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3016 #endif 3017 3018 /* Insert ED in schedule */ 3019 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3020 KASSERT(tdp->xfer == xfer); 3021 } 3022 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3023 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3024 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3025 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3026 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3027 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3028 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3029 usbd_xfer_schedule_timeout(xfer); 3030 xfer->ux_status = USBD_IN_PROGRESS; 3031 if (!polling) 3032 mutex_exit(&sc->sc_lock); 3033 3034 return USBD_IN_PROGRESS; 3035 } 3036 3037 Static void 3038 ohci_device_bulk_abort(struct usbd_xfer *xfer) 3039 { 3040 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3041 3042 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3043 3044 KASSERT(mutex_owned(&sc->sc_lock)); 3045 3046 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3047 usbd_xfer_abort(xfer); 3048 } 3049 3050 /* 3051 * Close a device bulk pipe. 3052 */ 3053 Static void 3054 ohci_device_bulk_close(struct usbd_pipe *pipe) 3055 { 3056 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3057 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3058 3059 KASSERT(mutex_owned(&sc->sc_lock)); 3060 3061 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3062 3063 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3064 ohci_close_pipe(pipe, sc->sc_bulk_head); 3065 ohci_free_std_locked(sc, opipe->tail.td); 3066 } 3067 3068 /************************/ 3069 3070 Static int 3071 ohci_device_intr_init(struct usbd_xfer *xfer) 3072 { 3073 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3074 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3075 int len = xfer->ux_bufsize; 3076 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3077 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3078 int err; 3079 3080 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3081 3082 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3083 KASSERT(len != 0); 3084 3085 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 3086 len, isread, xfer->ux_flags); 3087 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 3088 3089 ox->ox_nstd = 0; 3090 3091 err = ohci_alloc_std_chain(sc, xfer, len, isread); 3092 if (err) { 3093 return err; 3094 } 3095 3096 return 0; 3097 } 3098 3099 Static void 3100 ohci_device_intr_fini(struct usbd_xfer *xfer) 3101 { 3102 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3103 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3104 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3105 3106 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3107 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 3108 3109 mutex_enter(&sc->sc_lock); 3110 for (size_t i = 0; i < ox->ox_nstd; i++) { 3111 ohci_soft_td_t *std = ox->ox_stds[i]; 3112 if (std != NULL) 3113 break; 3114 if (std != opipe->tail.td) 3115 ohci_free_std_locked(sc, std); 3116 } 3117 mutex_exit(&sc->sc_lock); 3118 3119 if (ox->ox_nstd) { 3120 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 3121 kmem_free(ox->ox_stds, sz); 3122 } 3123 } 3124 3125 Static usbd_status 3126 ohci_device_intr_transfer(struct usbd_xfer *xfer) 3127 { 3128 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3129 usbd_status err; 3130 3131 /* Insert last in queue. */ 3132 mutex_enter(&sc->sc_lock); 3133 err = usb_insert_transfer(xfer); 3134 mutex_exit(&sc->sc_lock); 3135 if (err) 3136 return err; 3137 3138 /* Pipe isn't running, start first */ 3139 return ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3140 } 3141 3142 Static usbd_status 3143 ohci_device_intr_start(struct usbd_xfer *xfer) 3144 { 3145 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3146 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3147 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3148 ohci_soft_ed_t *sed = opipe->sed; 3149 ohci_soft_td_t *data, *last, *tail; 3150 int len, isread, endpt; 3151 const bool polling = sc->sc_bus.ub_usepolling; 3152 3153 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3154 3155 if (sc->sc_dying) 3156 return USBD_IOERROR; 3157 3158 DPRINTFN(3, "xfer=%#jx len=%jd flags=%jd priv=%#jx", (uintptr_t)xfer, 3159 xfer->ux_length, xfer->ux_flags, (uintptr_t)xfer->ux_priv); 3160 3161 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3162 3163 len = xfer->ux_length; 3164 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3165 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3166 3167 if (!polling) 3168 mutex_enter(&sc->sc_lock); 3169 3170 /* 3171 * Use the pipe "tail" TD as our first and loan our first TD to the 3172 * next transfer. 3173 */ 3174 data = opipe->tail.td; 3175 opipe->tail.td = ox->ox_stds[0]; 3176 ox->ox_stds[0] = data; 3177 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3178 3179 /* point at sentinel */ 3180 tail = opipe->tail.td; 3181 memset(&tail->td, 0, sizeof(tail->td)); 3182 tail->nexttd = NULL; 3183 tail->xfer = NULL; 3184 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3185 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3186 xfer->ux_hcpriv = data; 3187 3188 DPRINTFN(8, "data %#jx tail %#jx", (uintptr_t)ox->ox_stds[0], 3189 (uintptr_t)tail, 0, 0); 3190 KASSERT(opipe->tail.td == tail); 3191 3192 /* We want interrupt at the end of the transfer. */ 3193 last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3194 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3195 3196 last->td.td_nexttd = HTOO32(tail->physaddr); 3197 last->nexttd = tail; 3198 last->flags |= OHCI_CALL_DONE; 3199 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3200 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3201 3202 #ifdef OHCI_DEBUG 3203 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3204 if (ohcidebug >= 5) { 3205 ohci_dump_ed(sc, sed); 3206 ohci_dump_tds(sc, data); 3207 } 3208 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3209 #endif 3210 3211 /* Insert ED in schedule */ 3212 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3213 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3214 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3215 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3216 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3217 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3218 3219 xfer->ux_status = USBD_IN_PROGRESS; 3220 if (!polling) 3221 mutex_exit(&sc->sc_lock); 3222 3223 return USBD_IN_PROGRESS; 3224 } 3225 3226 /* Abort a device interrupt request. */ 3227 Static void 3228 ohci_device_intr_abort(struct usbd_xfer *xfer) 3229 { 3230 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3231 3232 KASSERT(mutex_owned(&sc->sc_lock)); 3233 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3234 3235 usbd_xfer_abort(xfer); 3236 } 3237 3238 /* Close a device interrupt pipe. */ 3239 Static void 3240 ohci_device_intr_close(struct usbd_pipe *pipe) 3241 { 3242 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3243 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3244 int nslots = opipe->intr.nslots; 3245 int pos = opipe->intr.pos; 3246 int j; 3247 ohci_soft_ed_t *p, *sed = opipe->sed; 3248 3249 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3250 3251 KASSERT(mutex_owned(&sc->sc_lock)); 3252 3253 DPRINTFN(1, "pipe=%#jx nslots=%jd pos=%jd", (uintptr_t)pipe, nslots, 3254 pos, 0); 3255 usb_syncmem(&sed->dma, sed->offs, 3256 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3257 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3258 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3259 sizeof(sed->ed.ed_flags), 3260 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3261 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3262 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3263 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3264 3265 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3266 continue; 3267 KASSERT(p); 3268 p->next = sed->next; 3269 p->ed.ed_nexted = sed->ed.ed_nexted; 3270 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3271 sizeof(p->ed.ed_nexted), 3272 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3273 3274 for (j = 0; j < nslots; j++) 3275 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3276 3277 ohci_free_std_locked(sc, opipe->tail.td); 3278 ohci_free_sed_locked(sc, opipe->sed); 3279 } 3280 3281 Static usbd_status 3282 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3283 { 3284 int i, j, best; 3285 u_int npoll, slow, shigh, nslots; 3286 u_int bestbw, bw; 3287 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3288 3289 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3290 3291 DPRINTFN(2, "pipe=%#jx", (uintptr_t)opipe, 0, 0, 0); 3292 if (ival == 0) { 3293 printf("ohci_setintr: 0 interval\n"); 3294 return USBD_INVAL; 3295 } 3296 3297 npoll = OHCI_NO_INTRS; 3298 while (npoll > ival) 3299 npoll /= 2; 3300 DPRINTFN(2, "ival=%jd npoll=%jd", ival, npoll, 0, 0); 3301 3302 /* 3303 * We now know which level in the tree the ED must go into. 3304 * Figure out which slot has most bandwidth left over. 3305 * Slots to examine: 3306 * npoll 3307 * 1 0 3308 * 2 1 2 3309 * 4 3 4 5 6 3310 * 8 7 8 9 10 11 12 13 14 3311 * N (N-1) .. (N-1+N-1) 3312 */ 3313 slow = npoll-1; 3314 shigh = slow + npoll; 3315 nslots = OHCI_NO_INTRS / npoll; 3316 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3317 bw = 0; 3318 for (j = 0; j < nslots; j++) 3319 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3320 if (bw < bestbw) { 3321 best = i; 3322 bestbw = bw; 3323 } 3324 } 3325 DPRINTFN(2, "best=%jd(%jd..%jd) bestbw=%jd", best, slow, shigh, bestbw); 3326 3327 mutex_enter(&sc->sc_lock); 3328 hsed = sc->sc_eds[best]; 3329 sed->next = hsed->next; 3330 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3331 sizeof(hsed->ed.ed_flags), 3332 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3333 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3334 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3335 sizeof(sed->ed.ed_flags), 3336 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3337 hsed->next = sed; 3338 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3339 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3340 sizeof(hsed->ed.ed_flags), 3341 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3342 mutex_exit(&sc->sc_lock); 3343 3344 for (j = 0; j < nslots; j++) 3345 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3346 opipe->intr.nslots = nslots; 3347 opipe->intr.pos = best; 3348 3349 DPRINTFN(5, "returns %#jx", (uintptr_t)opipe, 0, 0, 0); 3350 return USBD_NORMAL_COMPLETION; 3351 } 3352 3353 /***********************/ 3354 3355 Static int 3356 ohci_device_isoc_init(struct usbd_xfer *xfer) 3357 { 3358 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3359 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3360 ohci_soft_itd_t *sitd; 3361 size_t i; 3362 int err; 3363 3364 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3365 3366 DPRINTFN(1, "xfer %#jx len %jd flags %jd", (uintptr_t)xfer, 3367 xfer->ux_length, xfer->ux_flags, 0); 3368 3369 const size_t nfsitd = howmany(xfer->ux_nframes, OHCI_ITD_NOFFSET); 3370 const size_t nbsitd = xfer->ux_bufsize / OHCI_PAGE_SIZE; 3371 const size_t nsitd = MAX(nfsitd, nbsitd) + 1; 3372 3373 ox->ox_sitds = kmem_zalloc(sizeof(ohci_soft_itd_t *) * nsitd, 3374 KM_SLEEP); 3375 ox->ox_nsitd = nsitd; 3376 3377 for (i = 0; i < nsitd; i++) { 3378 /* Allocate next ITD */ 3379 sitd = ohci_alloc_sitd(sc); 3380 if (sitd == NULL) { 3381 err = ENOMEM; 3382 goto fail; 3383 } 3384 ox->ox_sitds[i] = sitd; 3385 sitd->xfer = xfer; 3386 sitd->flags = 0; 3387 } 3388 3389 return 0; 3390 fail: 3391 for (; i > 0;) { 3392 ohci_free_sitd(sc, ox->ox_sitds[--i]); 3393 } 3394 return err; 3395 } 3396 3397 Static void 3398 ohci_device_isoc_fini(struct usbd_xfer *xfer) 3399 { 3400 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3401 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3402 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3403 3404 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3405 3406 mutex_enter(&sc->sc_lock); 3407 for (size_t i = 0; i < ox->ox_nsitd; i++) { 3408 if (ox->ox_sitds[i] != opipe->tail.itd) { 3409 ohci_free_sitd_locked(sc, ox->ox_sitds[i]); 3410 } 3411 } 3412 mutex_exit(&sc->sc_lock); 3413 3414 if (ox->ox_nsitd) { 3415 const size_t sz = sizeof(ohci_soft_itd_t *) * ox->ox_nsitd; 3416 kmem_free(ox->ox_sitds, sz); 3417 } 3418 } 3419 3420 3421 usbd_status 3422 ohci_device_isoc_transfer(struct usbd_xfer *xfer) 3423 { 3424 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3425 usbd_status __diagused err; 3426 3427 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3428 3429 DPRINTFN(5, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3430 3431 /* Put it on our queue, */ 3432 mutex_enter(&sc->sc_lock); 3433 err = usb_insert_transfer(xfer); 3434 mutex_exit(&sc->sc_lock); 3435 3436 KASSERT(err == USBD_NORMAL_COMPLETION); 3437 3438 /* insert into schedule, */ 3439 ohci_device_isoc_enter(xfer); 3440 3441 /* and start if the pipe wasn't running */ 3442 return USBD_IN_PROGRESS; 3443 } 3444 3445 void 3446 ohci_device_isoc_enter(struct usbd_xfer *xfer) 3447 { 3448 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3449 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3450 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3451 ohci_soft_ed_t *sed = opipe->sed; 3452 ohci_soft_itd_t *sitd, *nsitd, *tail; 3453 ohci_physaddr_t buf, offs, bp0, bp1; 3454 int i, ncur, nframes; 3455 size_t boff, frlen; 3456 3457 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3458 DPRINTFN(5, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3459 3460 mutex_enter(&sc->sc_lock); 3461 3462 if (sc->sc_dying) { 3463 mutex_exit(&sc->sc_lock); 3464 return; 3465 } 3466 3467 struct isoc *isoc = &opipe->isoc; 3468 3469 DPRINTFN(1, "used=%jd next=%jd xfer=%#jx nframes=%jd", 3470 isoc->inuse, isoc->next, (uintptr_t)xfer, xfer->ux_nframes); 3471 3472 int isread = 3473 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 3474 3475 if (xfer->ux_length) 3476 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3477 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3478 3479 if (isoc->next == -1) { 3480 /* Not in use yet, schedule it a few frames ahead. */ 3481 usb_syncmem(&sc->sc_hccadma, 3482 offsetof(struct ohci_hcca, hcca_frame_number), 3483 sizeof(sc->sc_hcca->hcca_frame_number), 3484 BUS_DMASYNC_POSTREAD); 3485 isoc->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3486 DPRINTFN(2,"start next=%jd", isoc->next, 0, 0, 0); 3487 } 3488 3489 sitd = opipe->tail.itd; 3490 opipe->tail.itd = ox->ox_sitds[0]; 3491 ox->ox_sitds[0] = sitd; 3492 3493 boff = 0; 3494 buf = DMAADDR(&xfer->ux_dmabuf, 0); 3495 bp0 = bp1 = OHCI_PAGE(buf); 3496 offs = OHCI_PAGE_OFFSET(buf); 3497 3498 ohci_physaddr_t end = bp0; /* XXX stupid GCC */ 3499 3500 nframes = xfer->ux_nframes; 3501 xfer->ux_hcpriv = sitd; 3502 size_t j = 1; 3503 for (i = ncur = 0; i < nframes; i++, ncur++) { 3504 frlen = xfer->ux_frlengths[i]; 3505 3506 DPRINTFN(1, "frame=%jd ux_frlengths[%jd]=%jd", i, i, 3507 xfer->ux_frlengths[i], 0); 3508 /* 3509 * XXXNH: The loop assumes this is never true, because 3510 * incrementing 'i' assumes all the ux_frlengths[i] is covered. 3511 */ 3512 if (frlen > 2 * OHCI_PAGE_SIZE - offs) 3513 frlen = 2 * OHCI_PAGE_SIZE - offs; 3514 3515 boff += frlen; 3516 buf = DMAADDR(&xfer->ux_dmabuf, boff); 3517 ohci_physaddr_t noffs = OHCI_PAGE_OFFSET(buf); 3518 3519 ohci_physaddr_t nend = DMAADDR(&xfer->ux_dmabuf, boff - 1); 3520 const ohci_physaddr_t nep = OHCI_PAGE(nend); 3521 3522 /* Note the first page crossing in bp1 */ 3523 if (bp0 == bp1 && bp1 != nep) 3524 bp1 = nep; 3525 3526 DPRINTFN(1, "ncur=%jd bp0=%#jx bp1=%#jx nend=%#jx", 3527 ncur, bp0, bp1, nend); 3528 3529 /* all offsets used or too many page crossings */ 3530 if (ncur == OHCI_ITD_NOFFSET || (bp0 != bp1 && bp1 != nep)) { 3531 /* Allocate next ITD */ 3532 nsitd = ox->ox_sitds[j++]; 3533 KASSERT(nsitd != NULL); 3534 KASSERT(j < ox->ox_nsitd); 3535 3536 /* Fill current ITD */ 3537 sitd->itd.itd_flags = HTOO32( 3538 OHCI_ITD_NOCC | 3539 OHCI_ITD_SET_SF(isoc->next) | 3540 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3541 OHCI_ITD_SET_FC(ncur)); 3542 sitd->itd.itd_bp0 = HTOO32(bp0); 3543 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3544 sitd->itd.itd_be = HTOO32(end); 3545 sitd->nextitd = nsitd; 3546 sitd->xfer = xfer; 3547 sitd->flags = 0; 3548 #ifdef DIAGNOSTIC 3549 sitd->isdone = false; 3550 #endif 3551 ohci_hash_add_itd(sc, sitd); 3552 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3553 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3554 3555 sitd = nsitd; 3556 isoc->next = isoc->next + ncur; 3557 bp0 = bp1 = OHCI_PAGE(buf); 3558 ncur = 0; 3559 } 3560 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3561 end = nend; 3562 offs = noffs; 3563 } 3564 KASSERT(j <= ox->ox_nsitd); 3565 3566 /* point at sentinel */ 3567 tail = opipe->tail.itd; 3568 memset(&tail->itd, 0, sizeof(tail->itd)); 3569 tail->nextitd = NULL; 3570 tail->xfer = NULL; 3571 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->itd), 3572 BUS_DMASYNC_PREWRITE); 3573 3574 /* Fixup last used ITD */ 3575 sitd->itd.itd_flags = HTOO32( 3576 OHCI_ITD_NOCC | 3577 OHCI_ITD_SET_SF(isoc->next) | 3578 OHCI_ITD_SET_DI(0) | 3579 OHCI_ITD_SET_FC(ncur)); 3580 sitd->itd.itd_bp0 = HTOO32(bp0); 3581 sitd->itd.itd_nextitd = HTOO32(tail->physaddr); 3582 sitd->itd.itd_be = HTOO32(end); 3583 sitd->nextitd = tail; 3584 sitd->xfer = xfer; 3585 sitd->flags = OHCI_CALL_DONE; 3586 #ifdef DIAGNOSTIC 3587 sitd->isdone = false; 3588 #endif 3589 ohci_hash_add_itd(sc, sitd); 3590 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3591 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3592 3593 isoc->next = isoc->next + ncur; 3594 isoc->inuse += nframes; 3595 3596 /* XXX pretend we did it all */ 3597 xfer->ux_actlen = offs; 3598 xfer->ux_status = USBD_IN_PROGRESS; 3599 3600 #ifdef OHCI_DEBUG 3601 if (ohcidebug >= 5) { 3602 usb_syncmem(&sc->sc_hccadma, 3603 offsetof(struct ohci_hcca, hcca_frame_number), 3604 sizeof(sc->sc_hcca->hcca_frame_number), 3605 BUS_DMASYNC_POSTREAD); 3606 DPRINTF("frame=%jd", O32TOH(sc->sc_hcca->hcca_frame_number), 3607 0, 0, 0); 3608 ohci_dump_itds(sc, xfer->ux_hcpriv); 3609 ohci_dump_ed(sc, sed); 3610 } 3611 #endif 3612 3613 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3614 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3615 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3616 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3617 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3618 sizeof(sed->ed.ed_flags), 3619 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3620 mutex_exit(&sc->sc_lock); 3621 } 3622 3623 void 3624 ohci_device_isoc_abort(struct usbd_xfer *xfer) 3625 { 3626 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3627 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3628 ohci_soft_ed_t *sed; 3629 ohci_soft_itd_t *sitd; 3630 3631 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3632 DPRINTFN(1, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3633 3634 KASSERT(mutex_owned(&sc->sc_lock)); 3635 3636 /* Transfer is already done. */ 3637 if (xfer->ux_status != USBD_NOT_STARTED && 3638 xfer->ux_status != USBD_IN_PROGRESS) { 3639 printf("ohci_device_isoc_abort: early return\n"); 3640 goto done; 3641 } 3642 3643 /* Give xfer the requested abort code. */ 3644 xfer->ux_status = USBD_CANCELLED; 3645 3646 sed = opipe->sed; 3647 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3648 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3649 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3650 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3651 sizeof(sed->ed.ed_flags), 3652 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3653 3654 sitd = xfer->ux_hcpriv; 3655 KASSERT(sitd); 3656 3657 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3658 3659 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3660 ohci_hash_rem_itd(sc, sitd); 3661 #ifdef DIAGNOSTIC 3662 DPRINTFN(1, "abort sets done sitd=%#jx", (uintptr_t)sitd, 3663 0, 0, 0); 3664 sitd->isdone = true; 3665 #endif 3666 } 3667 3668 /* Run callback. */ 3669 usb_transfer_complete(xfer); 3670 3671 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3672 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3673 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3674 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3675 3676 done: 3677 KASSERT(mutex_owned(&sc->sc_lock)); 3678 } 3679 3680 void 3681 ohci_device_isoc_done(struct usbd_xfer *xfer) 3682 { 3683 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3684 DPRINTFN(1, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3685 3686 int isread = 3687 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 3688 3689 DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 3690 0, 0); 3691 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3692 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3693 } 3694 3695 usbd_status 3696 ohci_setup_isoc(struct usbd_pipe *pipe) 3697 { 3698 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3699 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3700 struct isoc *isoc = &opipe->isoc; 3701 3702 isoc->next = -1; 3703 isoc->inuse = 0; 3704 3705 mutex_enter(&sc->sc_lock); 3706 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3707 mutex_exit(&sc->sc_lock); 3708 3709 return USBD_NORMAL_COMPLETION; 3710 } 3711 3712 void 3713 ohci_device_isoc_close(struct usbd_pipe *pipe) 3714 { 3715 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3716 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3717 3718 KASSERT(mutex_owned(&sc->sc_lock)); 3719 3720 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3721 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3722 ohci_close_pipe(pipe, sc->sc_isoc_head); 3723 #ifdef DIAGNOSTIC 3724 opipe->tail.itd->isdone = true; 3725 #endif 3726 ohci_free_sitd_locked(sc, opipe->tail.itd); 3727 } 3728
Indexes created Wed Sep 24 15:09:51 GMT 2025