ohci.c revision 1.313
1 /* $NetBSD: ohci.c,v 1.313 2020/12/10 20:50:24 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012, 2016, 2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca), 10 * Matthew R. Green (mrg (at) eterna.com.au), and Nick Hudson. 11 * 12 * This code is derived from software contributed to The NetBSD Foundation 13 * by Charles M. Hannum. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * USB Open Host Controller driver. 39 * 40 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 41 * USB spec: http://www.usb.org/developers/docs/ 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.313 2020/12/10 20:50:24 skrll Exp $"); 46 47 #ifdef _KERNEL_OPT 48 #include "opt_usb.h" 49 #endif 50 51 #include <sys/param.h> 52 53 #include <sys/cpu.h> 54 #include <sys/device.h> 55 #include <sys/kernel.h> 56 #include <sys/kmem.h> 57 #include <sys/proc.h> 58 #include <sys/queue.h> 59 #include <sys/select.h> 60 #include <sys/sysctl.h> 61 #include <sys/systm.h> 62 63 #include <machine/endian.h> 64 65 #include <dev/usb/usb.h> 66 #include <dev/usb/usbdi.h> 67 #include <dev/usb/usbdivar.h> 68 #include <dev/usb/usb_mem.h> 69 #include <dev/usb/usb_quirks.h> 70 71 #include <dev/usb/ohcireg.h> 72 #include <dev/usb/ohcivar.h> 73 #include <dev/usb/usbroothub.h> 74 #include <dev/usb/usbhist.h> 75 76 #ifdef USB_DEBUG 77 #ifndef OHCI_DEBUG 78 #define ohcidebug 0 79 #else 80 static int ohcidebug = 10; 81 82 SYSCTL_SETUP(sysctl_hw_ohci_setup, "sysctl hw.ohci setup") 83 { 84 int err; 85 const struct sysctlnode *rnode; 86 const struct sysctlnode *cnode; 87 88 err = sysctl_createv(clog, 0, NULL, &rnode, 89 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ohci", 90 SYSCTL_DESCR("ohci global controls"), 91 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 92 93 if (err) 94 goto fail; 95 96 /* control debugging printfs */ 97 err = sysctl_createv(clog, 0, &rnode, &cnode, 98 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 99 "debug", SYSCTL_DESCR("Enable debugging output"), 100 NULL, 0, &ohcidebug, sizeof(ohcidebug), CTL_CREATE, CTL_EOL); 101 if (err) 102 goto fail; 103 104 return; 105 fail: 106 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 107 } 108 109 #endif /* OHCI_DEBUG */ 110 #endif /* USB_DEBUG */ 111 112 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ohcidebug,FMT,A,B,C,D) 113 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ohcidebug,N,FMT,A,B,C,D) 114 #define OHCIHIST_FUNC() USBHIST_FUNC() 115 #define OHCIHIST_CALLED(name) USBHIST_CALLED(ohcidebug) 116 117 #if BYTE_ORDER == BIG_ENDIAN 118 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 119 #else 120 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 121 #endif 122 123 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 124 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 125 #define HTOO16(val) O16TOH(val) 126 #define HTOO32(val) O32TOH(val) 127 128 struct ohci_pipe; 129 130 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 131 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 132 133 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 134 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 135 Static void ohci_free_std_locked(ohci_softc_t *, ohci_soft_td_t *); 136 137 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 138 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 139 Static void ohci_free_sitd_locked(ohci_softc_t *, 140 ohci_soft_itd_t *); 141 142 Static int ohci_alloc_std_chain(ohci_softc_t *, struct usbd_xfer *, 143 int, int); 144 Static void ohci_free_stds(ohci_softc_t *, struct ohci_xfer *); 145 146 Static void ohci_reset_std_chain(ohci_softc_t *, struct usbd_xfer *, 147 int, int, ohci_soft_td_t *, ohci_soft_td_t **); 148 149 Static usbd_status ohci_open(struct usbd_pipe *); 150 Static void ohci_poll(struct usbd_bus *); 151 Static void ohci_softintr(void *); 152 Static void ohci_rhsc(ohci_softc_t *, struct usbd_xfer *); 153 Static void ohci_rhsc_softint(void *); 154 155 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 156 ohci_soft_ed_t *); 157 158 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 159 ohci_soft_ed_t *); 160 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 161 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 162 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 163 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 164 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 165 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 166 167 Static usbd_status ohci_setup_isoc(struct usbd_pipe *); 168 Static void ohci_device_isoc_enter(struct usbd_xfer *); 169 170 Static struct usbd_xfer * 171 ohci_allocx(struct usbd_bus *, unsigned int); 172 Static void ohci_freex(struct usbd_bus *, struct usbd_xfer *); 173 Static bool ohci_dying(struct usbd_bus *); 174 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 175 Static int ohci_roothub_ctrl(struct usbd_bus *, 176 usb_device_request_t *, void *, int); 177 178 Static usbd_status ohci_root_intr_transfer(struct usbd_xfer *); 179 Static usbd_status ohci_root_intr_start(struct usbd_xfer *); 180 Static void ohci_root_intr_abort(struct usbd_xfer *); 181 Static void ohci_root_intr_close(struct usbd_pipe *); 182 Static void ohci_root_intr_done(struct usbd_xfer *); 183 184 Static int ohci_device_ctrl_init(struct usbd_xfer *); 185 Static void ohci_device_ctrl_fini(struct usbd_xfer *); 186 Static usbd_status ohci_device_ctrl_transfer(struct usbd_xfer *); 187 Static usbd_status ohci_device_ctrl_start(struct usbd_xfer *); 188 Static void ohci_device_ctrl_abort(struct usbd_xfer *); 189 Static void ohci_device_ctrl_close(struct usbd_pipe *); 190 Static void ohci_device_ctrl_done(struct usbd_xfer *); 191 192 Static int ohci_device_bulk_init(struct usbd_xfer *); 193 Static void ohci_device_bulk_fini(struct usbd_xfer *); 194 Static usbd_status ohci_device_bulk_transfer(struct usbd_xfer *); 195 Static usbd_status ohci_device_bulk_start(struct usbd_xfer *); 196 Static void ohci_device_bulk_abort(struct usbd_xfer *); 197 Static void ohci_device_bulk_close(struct usbd_pipe *); 198 Static void ohci_device_bulk_done(struct usbd_xfer *); 199 200 Static int ohci_device_intr_init(struct usbd_xfer *); 201 Static void ohci_device_intr_fini(struct usbd_xfer *); 202 Static usbd_status ohci_device_intr_transfer(struct usbd_xfer *); 203 Static usbd_status ohci_device_intr_start(struct usbd_xfer *); 204 Static void ohci_device_intr_abort(struct usbd_xfer *); 205 Static void ohci_device_intr_close(struct usbd_pipe *); 206 Static void ohci_device_intr_done(struct usbd_xfer *); 207 208 Static int ohci_device_isoc_init(struct usbd_xfer *); 209 Static void ohci_device_isoc_fini(struct usbd_xfer *); 210 Static usbd_status ohci_device_isoc_transfer(struct usbd_xfer *); 211 Static void ohci_device_isoc_abort(struct usbd_xfer *); 212 Static void ohci_device_isoc_close(struct usbd_pipe *); 213 Static void ohci_device_isoc_done(struct usbd_xfer *); 214 215 Static usbd_status ohci_device_setintr(ohci_softc_t *, 216 struct ohci_pipe *, int); 217 218 Static void ohci_rhsc_enable(void *); 219 220 Static void ohci_close_pipe(struct usbd_pipe *, ohci_soft_ed_t *); 221 Static void ohci_abortx(struct usbd_xfer *); 222 223 Static void ohci_device_clear_toggle(struct usbd_pipe *); 224 Static void ohci_noop(struct usbd_pipe *); 225 226 #ifdef OHCI_DEBUG 227 Static void ohci_dumpregs(ohci_softc_t *); 228 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 229 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 230 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 231 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 232 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 233 #endif 234 235 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 236 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 237 #define OWRITE1(sc, r, x) \ 238 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 239 #define OWRITE2(sc, r, x) \ 240 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 241 #define OWRITE4(sc, r, x) \ 242 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 243 244 static __inline uint32_t 245 OREAD4(ohci_softc_t *sc, bus_size_t r) 246 { 247 248 OBARR(sc); 249 return bus_space_read_4(sc->iot, sc->ioh, r); 250 } 251 252 /* Reverse the bits in a value 0 .. 31 */ 253 Static uint8_t revbits[OHCI_NO_INTRS] = 254 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 255 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 256 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 257 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 258 259 struct ohci_pipe { 260 struct usbd_pipe pipe; 261 ohci_soft_ed_t *sed; 262 union { 263 ohci_soft_td_t *td; 264 ohci_soft_itd_t *itd; 265 } tail; 266 /* Info needed for different pipe kinds. */ 267 union { 268 /* Control pipe */ 269 struct { 270 usb_dma_t reqdma; 271 } ctrl; 272 /* Interrupt pipe */ 273 struct { 274 int nslots; 275 int pos; 276 } intr; 277 /* Isochronous pipe */ 278 struct isoc { 279 int next, inuse; 280 } isoc; 281 }; 282 }; 283 284 Static const struct usbd_bus_methods ohci_bus_methods = { 285 .ubm_open = ohci_open, 286 .ubm_softint = ohci_softintr, 287 .ubm_dopoll = ohci_poll, 288 .ubm_allocx = ohci_allocx, 289 .ubm_freex = ohci_freex, 290 .ubm_abortx = ohci_abortx, 291 .ubm_dying = ohci_dying, 292 .ubm_getlock = ohci_get_lock, 293 .ubm_rhctrl = ohci_roothub_ctrl, 294 }; 295 296 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 297 .upm_transfer = ohci_root_intr_transfer, 298 .upm_start = ohci_root_intr_start, 299 .upm_abort = ohci_root_intr_abort, 300 .upm_close = ohci_root_intr_close, 301 .upm_cleartoggle = ohci_noop, 302 .upm_done = ohci_root_intr_done, 303 }; 304 305 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 306 .upm_init = ohci_device_ctrl_init, 307 .upm_fini = ohci_device_ctrl_fini, 308 .upm_transfer = ohci_device_ctrl_transfer, 309 .upm_start = ohci_device_ctrl_start, 310 .upm_abort = ohci_device_ctrl_abort, 311 .upm_close = ohci_device_ctrl_close, 312 .upm_cleartoggle = ohci_noop, 313 .upm_done = ohci_device_ctrl_done, 314 }; 315 316 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 317 .upm_init = ohci_device_intr_init, 318 .upm_fini = ohci_device_intr_fini, 319 .upm_transfer = ohci_device_intr_transfer, 320 .upm_start = ohci_device_intr_start, 321 .upm_abort = ohci_device_intr_abort, 322 .upm_close = ohci_device_intr_close, 323 .upm_cleartoggle = ohci_device_clear_toggle, 324 .upm_done = ohci_device_intr_done, 325 }; 326 327 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 328 .upm_init = ohci_device_bulk_init, 329 .upm_fini = ohci_device_bulk_fini, 330 .upm_transfer = ohci_device_bulk_transfer, 331 .upm_start = ohci_device_bulk_start, 332 .upm_abort = ohci_device_bulk_abort, 333 .upm_close = ohci_device_bulk_close, 334 .upm_cleartoggle = ohci_device_clear_toggle, 335 .upm_done = ohci_device_bulk_done, 336 }; 337 338 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 339 .upm_init = ohci_device_isoc_init, 340 .upm_fini = ohci_device_isoc_fini, 341 .upm_transfer = ohci_device_isoc_transfer, 342 .upm_abort = ohci_device_isoc_abort, 343 .upm_close = ohci_device_isoc_close, 344 .upm_cleartoggle = ohci_noop, 345 .upm_done = ohci_device_isoc_done, 346 }; 347 348 int 349 ohci_activate(device_t self, enum devact act) 350 { 351 struct ohci_softc *sc = device_private(self); 352 353 switch (act) { 354 case DVACT_DEACTIVATE: 355 sc->sc_dying = 1; 356 return 0; 357 default: 358 return EOPNOTSUPP; 359 } 360 } 361 362 void 363 ohci_childdet(device_t self, device_t child) 364 { 365 struct ohci_softc *sc = device_private(self); 366 367 KASSERT(sc->sc_child == child); 368 sc->sc_child = NULL; 369 } 370 371 int 372 ohci_detach(struct ohci_softc *sc, int flags) 373 { 374 int rv = 0; 375 376 if (sc->sc_child != NULL) 377 rv = config_detach(sc->sc_child, flags); 378 379 if (rv != 0) 380 return rv; 381 382 softint_disestablish(sc->sc_rhsc_si); 383 384 callout_halt(&sc->sc_tmo_rhsc, NULL); 385 callout_destroy(&sc->sc_tmo_rhsc); 386 387 mutex_destroy(&sc->sc_lock); 388 mutex_destroy(&sc->sc_intr_lock); 389 390 if (sc->sc_hcca != NULL) 391 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 392 pool_cache_destroy(sc->sc_xferpool); 393 cv_destroy(&sc->sc_abort_cv); 394 395 return rv; 396 } 397 398 ohci_soft_ed_t * 399 ohci_alloc_sed(ohci_softc_t *sc) 400 { 401 ohci_soft_ed_t *sed; 402 usbd_status err; 403 int i, offs; 404 usb_dma_t dma; 405 406 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 407 408 mutex_enter(&sc->sc_lock); 409 if (sc->sc_freeeds == NULL) { 410 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 411 mutex_exit(&sc->sc_lock); 412 413 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 414 OHCI_ED_ALIGN, USBMALLOC_COHERENT, &dma); 415 if (err) 416 return NULL; 417 418 mutex_enter(&sc->sc_lock); 419 for (i = 0; i < OHCI_SED_CHUNK; i++) { 420 offs = i * OHCI_SED_SIZE; 421 sed = KERNADDR(&dma, offs); 422 sed->physaddr = DMAADDR(&dma, offs); 423 sed->dma = dma; 424 sed->offs = offs; 425 sed->next = sc->sc_freeeds; 426 sc->sc_freeeds = sed; 427 } 428 } 429 sed = sc->sc_freeeds; 430 sc->sc_freeeds = sed->next; 431 mutex_exit(&sc->sc_lock); 432 433 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 434 sed->next = 0; 435 return sed; 436 } 437 438 static inline void 439 ohci_free_sed_locked(ohci_softc_t *sc, ohci_soft_ed_t *sed) 440 { 441 442 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 443 444 sed->next = sc->sc_freeeds; 445 sc->sc_freeeds = sed; 446 } 447 448 void 449 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 450 { 451 452 mutex_enter(&sc->sc_lock); 453 ohci_free_sed_locked(sc, sed); 454 mutex_exit(&sc->sc_lock); 455 } 456 457 ohci_soft_td_t * 458 ohci_alloc_std(ohci_softc_t *sc) 459 { 460 ohci_soft_td_t *std; 461 usbd_status err; 462 int i, offs; 463 usb_dma_t dma; 464 465 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 466 467 mutex_enter(&sc->sc_lock); 468 if (sc->sc_freetds == NULL) { 469 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 470 mutex_exit(&sc->sc_lock); 471 472 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 473 OHCI_TD_ALIGN, USBMALLOC_COHERENT, &dma); 474 if (err) 475 return NULL; 476 477 mutex_enter(&sc->sc_lock); 478 for (i = 0; i < OHCI_STD_CHUNK; i++) { 479 offs = i * OHCI_STD_SIZE; 480 std = KERNADDR(&dma, offs); 481 std->physaddr = DMAADDR(&dma, offs); 482 std->dma = dma; 483 std->offs = offs; 484 std->nexttd = sc->sc_freetds; 485 sc->sc_freetds = std; 486 } 487 } 488 489 std = sc->sc_freetds; 490 sc->sc_freetds = std->nexttd; 491 mutex_exit(&sc->sc_lock); 492 493 memset(&std->td, 0, sizeof(ohci_td_t)); 494 std->nexttd = NULL; 495 std->xfer = NULL; 496 std->held = NULL; 497 498 return std; 499 } 500 501 void 502 ohci_free_std_locked(ohci_softc_t *sc, ohci_soft_td_t *std) 503 { 504 505 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 506 507 std->nexttd = sc->sc_freetds; 508 sc->sc_freetds = std; 509 } 510 511 void 512 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 513 { 514 515 mutex_enter(&sc->sc_lock); 516 ohci_free_std_locked(sc, std); 517 mutex_exit(&sc->sc_lock); 518 } 519 520 Static int 521 ohci_alloc_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, int length, int rd) 522 { 523 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 524 uint16_t flags = xfer->ux_flags; 525 526 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 527 528 DPRINTFN(8, "addr=%jd endpt=%jd len=%jd speed=%jd", 529 xfer->ux_pipe->up_dev->ud_addr, 530 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 531 length, xfer->ux_pipe->up_dev->ud_speed); 532 533 ASSERT_SLEEPABLE(); 534 KASSERT(length != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 535 536 size_t nstd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 537 nstd += howmany(length, OHCI_PAGE_SIZE); 538 ox->ox_stds = kmem_zalloc(sizeof(ohci_soft_td_t *) * nstd, 539 KM_SLEEP); 540 ox->ox_nstd = nstd; 541 542 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, nstd, 0, 0); 543 544 for (size_t j = 0; j < ox->ox_nstd; j++) { 545 ohci_soft_td_t *cur = ohci_alloc_std(sc); 546 if (cur == NULL) 547 goto nomem; 548 549 ox->ox_stds[j] = cur; 550 cur->held = &ox->ox_stds[j]; 551 cur->xfer = xfer; 552 cur->flags = 0; 553 DPRINTFN(10, "xfer=%#jx new std=%#jx held at %#jx", (uintptr_t)ox, 554 (uintptr_t)cur, (uintptr_t)cur->held, 0); 555 } 556 557 return 0; 558 559 nomem: 560 ohci_free_stds(sc, ox); 561 kmem_free(ox->ox_stds, sizeof(ohci_soft_td_t *) * nstd); 562 563 return ENOMEM; 564 } 565 566 Static void 567 ohci_free_stds(ohci_softc_t *sc, struct ohci_xfer *ox) 568 { 569 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 570 DPRINTF("ox=%#jx", (uintptr_t)ox, 0, 0, 0); 571 572 mutex_enter(&sc->sc_lock); 573 for (size_t i = 0; i < ox->ox_nstd; i++) { 574 ohci_soft_td_t *std = ox->ox_stds[i]; 575 if (std == NULL) 576 break; 577 ohci_free_std_locked(sc, std); 578 } 579 mutex_exit(&sc->sc_lock); 580 } 581 582 void 583 ohci_reset_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, 584 int alen, int rd, ohci_soft_td_t *sp, ohci_soft_td_t **ep) 585 { 586 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 587 ohci_soft_td_t *next, *cur; 588 int len, curlen; 589 usb_dma_t *dma = &xfer->ux_dmabuf; 590 uint16_t flags = xfer->ux_flags; 591 592 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 593 DPRINTF("start len=%jd", alen, 0, 0, 0); 594 595 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 596 597 DPRINTFN(8, "addr=%jd endpt=%jd len=%jd speed=%jd", 598 xfer->ux_pipe->up_dev->ud_addr, 599 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 600 alen, xfer->ux_pipe->up_dev->ud_speed); 601 602 KASSERT(sp); 603 604 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 605 606 /* 607 * Assign next for the len == 0 case where we don't go through the 608 * main loop. 609 */ 610 len = alen; 611 cur = next = sp; 612 613 usb_syncmem(dma, 0, len, 614 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 615 const uint32_t tdflags = HTOO32( 616 OHCI_TD_SET_DP(rd ? OHCI_TD_DP_IN : OHCI_TD_DP_OUT) | 617 OHCI_TD_SET_CC(OHCI_TD_NOCC) | 618 OHCI_TD_SET_TOGGLE(OHCI_TD_TOGGLE_CARRY) | 619 OHCI_TD_SET_DI(OHCI_TD_NOINTR) 620 ); 621 622 size_t curoffs = 0; 623 for (size_t j = 1; len != 0;) { 624 if (j == ox->ox_nstd) 625 next = NULL; 626 else 627 next = ox->ox_stds[j++]; 628 KASSERT(next != cur); 629 630 curlen = len; 631 /* 632 * The OHCI hardware can handle at most one page crossing per 633 * TD. That is, 2 * OHCI_PAGE_SIZE as a maximum. Limit the 634 * length in this TD accordingly. 635 */ 636 const ohci_physaddr_t sdataphys = DMAADDR(dma, curoffs); 637 638 int maxlen = (2 * OHCI_PAGE_SIZE) - OHCI_PAGE_OFFSET(sdataphys); 639 if (curlen > maxlen) { 640 curlen = maxlen; 641 642 /* 643 * the length must be a multiple of 644 * the max size 645 */ 646 curlen -= curlen % mps; 647 } 648 649 const int edataoffs = curoffs + curlen - 1; 650 const ohci_physaddr_t edataphys = DMAADDR(dma, edataoffs); 651 652 KASSERT(curlen != 0); 653 DPRINTFN(4, "sdataphys=0x%08jx edataphys=0x%08jx " 654 "len=%jd curlen=%jd", sdataphys, edataphys, len, curlen); 655 656 cur->td.td_flags = tdflags; 657 cur->td.td_cbp = HTOO32(sdataphys); 658 cur->td.td_be = HTOO32(edataphys); 659 cur->td.td_nexttd = (next != NULL) ? HTOO32(next->physaddr) : 0; 660 cur->nexttd = next; 661 cur->len = curlen; 662 cur->flags = OHCI_ADD_LEN; 663 cur->xfer = xfer; 664 ohci_hash_add_td(sc, cur); 665 666 curoffs += curlen; 667 len -= curlen; 668 669 if (len != 0) { 670 KASSERT(next != NULL); 671 DPRINTFN(10, "extend chain", 0, 0, 0, 0); 672 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 673 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 674 675 cur = next; 676 } 677 } 678 cur->td.td_flags |= 679 HTOO32(xfer->ux_flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0); 680 681 if (!rd && 682 (flags & USBD_FORCE_SHORT_XFER) && 683 alen % mps == 0) { 684 /* We're adding a ZLP so sync the previous TD */ 685 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 686 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 687 688 /* Force a 0 length transfer at the end. */ 689 690 KASSERT(next != NULL); 691 cur = next; 692 693 cur->td.td_flags = tdflags; 694 cur->td.td_cbp = 0; /* indicate 0 length packet */ 695 cur->td.td_nexttd = 0; 696 cur->td.td_be = ~0; 697 cur->nexttd = NULL; 698 cur->len = 0; 699 cur->flags = 0; 700 cur->xfer = xfer; 701 ohci_hash_add_td(sc, cur); 702 703 DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0); 704 } 705 706 /* Last TD gets usb_syncmem'ed by caller */ 707 *ep = cur; 708 } 709 710 ohci_soft_itd_t * 711 ohci_alloc_sitd(ohci_softc_t *sc) 712 { 713 ohci_soft_itd_t *sitd; 714 usbd_status err; 715 int i, offs; 716 usb_dma_t dma; 717 718 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 719 720 mutex_enter(&sc->sc_lock); 721 if (sc->sc_freeitds == NULL) { 722 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 723 mutex_exit(&sc->sc_lock); 724 725 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 726 OHCI_ITD_ALIGN, USBMALLOC_COHERENT, &dma); 727 if (err) 728 return NULL; 729 mutex_enter(&sc->sc_lock); 730 for (i = 0; i < OHCI_SITD_CHUNK; i++) { 731 offs = i * OHCI_SITD_SIZE; 732 sitd = KERNADDR(&dma, offs); 733 sitd->physaddr = DMAADDR(&dma, offs); 734 sitd->dma = dma; 735 sitd->offs = offs; 736 sitd->nextitd = sc->sc_freeitds; 737 sc->sc_freeitds = sitd; 738 } 739 } 740 741 sitd = sc->sc_freeitds; 742 sc->sc_freeitds = sitd->nextitd; 743 mutex_exit(&sc->sc_lock); 744 745 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 746 sitd->nextitd = NULL; 747 sitd->xfer = NULL; 748 749 #ifdef DIAGNOSTIC 750 sitd->isdone = true; 751 #endif 752 753 return sitd; 754 } 755 756 Static void 757 ohci_free_sitd_locked(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 758 { 759 760 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 761 DPRINTFN(10, "sitd=%#jx", (uintptr_t)sitd, 0, 0, 0); 762 763 KASSERT(sitd->isdone); 764 #ifdef DIAGNOSTIC 765 /* Warn double free */ 766 sitd->isdone = false; 767 #endif 768 769 sitd->nextitd = sc->sc_freeitds; 770 sc->sc_freeitds = sitd; 771 } 772 773 void 774 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 775 { 776 777 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 778 779 mutex_enter(&sc->sc_lock); 780 ohci_free_sitd_locked(sc, sitd); 781 mutex_exit(&sc->sc_lock); 782 } 783 784 int 785 ohci_init(ohci_softc_t *sc) 786 { 787 ohci_soft_ed_t *sed, *psed; 788 usbd_status err; 789 int i; 790 uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */; 791 792 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 793 794 aprint_normal_dev(sc->sc_dev, ""); 795 796 sc->sc_hcca = NULL; 797 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 798 799 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 800 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 801 802 sc->sc_rhsc_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 803 ohci_rhsc_softint, sc); 804 805 for (i = 0; i < OHCI_HASH_SIZE; i++) 806 LIST_INIT(&sc->sc_hash_tds[i]); 807 for (i = 0; i < OHCI_HASH_SIZE; i++) 808 LIST_INIT(&sc->sc_hash_itds[i]); 809 810 TAILQ_INIT(&sc->sc_abortingxfers); 811 cv_init(&sc->sc_abort_cv, "ohciabt"); 812 813 sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0, 814 "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL); 815 816 rev = OREAD4(sc, OHCI_REVISION); 817 aprint_normal("OHCI version %" __PRIuBITS ".%" __PRIuBITS "%s\n", 818 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 819 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 820 821 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 822 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 823 sc->sc_bus.ub_revision = USBREV_UNKNOWN; 824 return -1; 825 } 826 sc->sc_bus.ub_revision = USBREV_1_0; 827 sc->sc_bus.ub_usedma = true; 828 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 829 830 /* XXX determine alignment by R/W */ 831 /* Allocate the HCCA area. */ 832 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 833 OHCI_HCCA_ALIGN, USBMALLOC_COHERENT, &sc->sc_hccadma); 834 if (err) { 835 sc->sc_hcca = NULL; 836 return err; 837 } 838 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 839 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 840 841 sc->sc_eintrs = OHCI_NORMAL_INTRS; 842 843 /* Allocate dummy ED that starts the control list. */ 844 sc->sc_ctrl_head = ohci_alloc_sed(sc); 845 if (sc->sc_ctrl_head == NULL) { 846 err = ENOMEM; 847 goto bad1; 848 } 849 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 850 851 /* Allocate dummy ED that starts the bulk list. */ 852 sc->sc_bulk_head = ohci_alloc_sed(sc); 853 if (sc->sc_bulk_head == NULL) { 854 err = ENOMEM; 855 goto bad2; 856 } 857 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 858 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 859 sizeof(sc->sc_bulk_head->ed), 860 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 861 862 /* Allocate dummy ED that starts the isochronous list. */ 863 sc->sc_isoc_head = ohci_alloc_sed(sc); 864 if (sc->sc_isoc_head == NULL) { 865 err = ENOMEM; 866 goto bad3; 867 } 868 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 869 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 870 sizeof(sc->sc_isoc_head->ed), 871 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 872 873 /* Allocate all the dummy EDs that make up the interrupt tree. */ 874 for (i = 0; i < OHCI_NO_EDS; i++) { 875 sed = ohci_alloc_sed(sc); 876 if (sed == NULL) { 877 while (--i >= 0) 878 ohci_free_sed(sc, sc->sc_eds[i]); 879 err = ENOMEM; 880 goto bad4; 881 } 882 /* All ED fields are set to 0. */ 883 sc->sc_eds[i] = sed; 884 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 885 if (i != 0) 886 psed = sc->sc_eds[(i-1) / 2]; 887 else 888 psed= sc->sc_isoc_head; 889 sed->next = psed; 890 sed->ed.ed_nexted = HTOO32(psed->physaddr); 891 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 892 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 893 } 894 /* 895 * Fill HCCA interrupt table. The bit reversal is to get 896 * the tree set up properly to spread the interrupts. 897 */ 898 for (i = 0; i < OHCI_NO_INTRS; i++) 899 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 900 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 901 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 902 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 903 904 #ifdef OHCI_DEBUG 905 DPRINTFN(15, "--- dump start ---", 0, 0, 0 ,0); 906 if (ohcidebug >= 15) { 907 for (i = 0; i < OHCI_NO_EDS; i++) { 908 DPRINTFN(15, "ed#%jd ", i, 0, 0, 0); 909 ohci_dump_ed(sc, sc->sc_eds[i]); 910 } 911 DPRINTFN(15, "iso", 0, 0, 0 ,0); 912 ohci_dump_ed(sc, sc->sc_isoc_head); 913 } 914 DPRINTFN(15, "--- dump end ---", 0, 0, 0 ,0); 915 #endif 916 917 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 918 ctl = OREAD4(sc, OHCI_CONTROL); 919 rwc = ctl & OHCI_RWC; 920 fm = OREAD4(sc, OHCI_FM_INTERVAL); 921 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 922 /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */ 923 924 /* Determine in what context we are running. */ 925 if (ctl & OHCI_IR) { 926 /* SMM active, request change */ 927 DPRINTF("SMM active, request owner change", 0, 0, 0, 0); 928 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 929 (OHCI_OC | OHCI_MIE)) 930 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 931 s = OREAD4(sc, OHCI_COMMAND_STATUS); 932 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 933 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 934 usb_delay_ms(&sc->sc_bus, 1); 935 ctl = OREAD4(sc, OHCI_CONTROL); 936 } 937 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 938 if ((ctl & OHCI_IR) == 0) { 939 aprint_error_dev(sc->sc_dev, 940 "SMM does not respond, resetting\n"); 941 OWRITE4(sc, OHCI_CONTROL, 942 OHCI_SET_HCFS(OHCI_HCFS_RESET) | rwc); 943 goto reset; 944 } 945 #if 0 946 /* 947 * Don't bother trying to reuse the BIOS init, we'll reset it 948 * anyway. 949 */ 950 } else if (OHCI_GET_HCFS(ctl) != OHCI_HCFS_RESET) { 951 /* BIOS started controller. */ 952 DPRINTF("BIOS active", 0, 0, 0, 0); 953 if (OHCI_GET_HCFS(ctl) != OHCI_HCFS_OPERATIONAL) { 954 OWRITE4(sc, OHCI_CONTROL, 955 OHCI_SET_HCFS(OHCI_HCFS_OPERATIONAL) | rwc); 956 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 957 } 958 #endif 959 } else { 960 DPRINTF("cold started", 0 ,0 ,0 ,0); 961 reset: 962 /* Controller was cold started. */ 963 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 964 } 965 966 /* 967 * This reset should not be necessary according to the OHCI spec, but 968 * without it some controllers do not start. 969 */ 970 DPRINTF("sc %#jx: resetting", (uintptr_t)sc, 0, 0, 0); 971 OWRITE4(sc, OHCI_CONTROL, OHCI_SET_HCFS(OHCI_HCFS_RESET) | rwc); 972 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 973 974 /* We now own the host controller and the bus has been reset. */ 975 976 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 977 /* Nominal time for a reset is 10 us. */ 978 for (i = 0; i < 10; i++) { 979 delay(10); 980 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 981 if (!hcr) 982 break; 983 } 984 if (hcr) { 985 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 986 err = EIO; 987 goto bad5; 988 } 989 #ifdef OHCI_DEBUG 990 if (ohcidebug >= 15) 991 ohci_dumpregs(sc); 992 #endif 993 994 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 995 996 /* Set up HC registers. */ 997 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 998 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 999 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 1000 /* disable all interrupts and then switch on all desired interrupts */ 1001 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 1002 /* switch on desired functional features */ 1003 ctl = OREAD4(sc, OHCI_CONTROL); 1004 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 1005 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 1006 OHCI_CBSR_SET(OHCI_RATIO_1_4) | 1007 OHCI_SET_HCFS(OHCI_HCFS_OPERATIONAL) | rwc; 1008 /* And finally start it! */ 1009 OWRITE4(sc, OHCI_CONTROL, ctl); 1010 1011 /* 1012 * The controller is now OPERATIONAL. Set a some final 1013 * registers that should be set earlier, but that the 1014 * controller ignores when in the SUSPEND state. 1015 */ 1016 ival = OHCI_FM_GET_IVAL(fm); 1017 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FM_FIT) ^ OHCI_FM_FIT; 1018 fm |= OHCI_FSMPS(ival) | ival; 1019 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 1020 per = OHCI_PERIODIC(ival); /* 90% periodic */ 1021 OWRITE4(sc, OHCI_PERIODIC_START, per); 1022 1023 if (sc->sc_flags & OHCIF_SUPERIO) { 1024 /* no overcurrent protection */ 1025 desca |= OHCI_RHD_NOCP; 1026 /* 1027 * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning 1028 * that 1029 * - ports are always power switched 1030 * - don't wait for powered root hub port 1031 */ 1032 desca &= ~(OHCI_RHD_POTPGT_MASK | OHCI_RHD_NPS); 1033 } 1034 1035 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 1036 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_RHD_NOCP); 1037 OWRITE4(sc, OHCI_RH_STATUS, OHCI_RHS_LPSC); /* Enable port power */ 1038 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 1039 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 1040 1041 /* 1042 * The AMD756 requires a delay before re-reading the register, 1043 * otherwise it will occasionally report 0 ports. 1044 */ 1045 sc->sc_noport = 0; 1046 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 1047 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 1048 sc->sc_noport = 1049 OHCI_RHD_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 1050 } 1051 1052 #ifdef OHCI_DEBUG 1053 if (ohcidebug >= 5) 1054 ohci_dumpregs(sc); 1055 #endif 1056 1057 /* Set up the bus struct. */ 1058 sc->sc_bus.ub_methods = &ohci_bus_methods; 1059 sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe); 1060 1061 sc->sc_control = sc->sc_intre = 0; 1062 1063 /* Finally, turn on interrupts. */ 1064 DPRINTF("enabling %#jx", sc->sc_eintrs | OHCI_MIE, 0, 0, 0); 1065 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 1066 1067 return 0; 1068 1069 bad5: 1070 for (i = 0; i < OHCI_NO_EDS; i++) 1071 ohci_free_sed(sc, sc->sc_eds[i]); 1072 bad4: 1073 ohci_free_sed(sc, sc->sc_isoc_head); 1074 bad3: 1075 ohci_free_sed(sc, sc->sc_bulk_head); 1076 bad2: 1077 ohci_free_sed(sc, sc->sc_ctrl_head); 1078 bad1: 1079 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 1080 sc->sc_hcca = NULL; 1081 return err; 1082 } 1083 1084 struct usbd_xfer * 1085 ohci_allocx(struct usbd_bus *bus, unsigned int nframes) 1086 { 1087 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1088 struct usbd_xfer *xfer; 1089 1090 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 1091 if (xfer != NULL) { 1092 memset(xfer, 0, sizeof(struct ohci_xfer)); 1093 1094 #ifdef DIAGNOSTIC 1095 xfer->ux_state = XFER_BUSY; 1096 #endif 1097 } 1098 return xfer; 1099 } 1100 1101 void 1102 ohci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1103 { 1104 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1105 1106 KASSERTMSG(xfer->ux_state == XFER_BUSY || 1107 xfer->ux_status == USBD_NOT_STARTED, 1108 "xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state); 1109 #ifdef DIAGNOSTIC 1110 xfer->ux_state = XFER_FREE; 1111 #endif 1112 pool_cache_put(sc->sc_xferpool, xfer); 1113 } 1114 1115 Static bool 1116 ohci_dying(struct usbd_bus *bus) 1117 { 1118 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1119 1120 return sc->sc_dying; 1121 } 1122 1123 Static void 1124 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1125 { 1126 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1127 1128 *lock = &sc->sc_lock; 1129 } 1130 1131 /* 1132 * Shut down the controller when the system is going down. 1133 */ 1134 bool 1135 ohci_shutdown(device_t self, int flags) 1136 { 1137 ohci_softc_t *sc = device_private(self); 1138 1139 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1140 1141 DPRINTF("stopping the HC", 0, 0, 0, 0); 1142 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 1143 OWRITE4(sc, OHCI_CONTROL, OHCI_SET_HCFS(OHCI_HCFS_RESET)); 1144 return true; 1145 } 1146 1147 bool 1148 ohci_resume(device_t dv, const pmf_qual_t *qual) 1149 { 1150 ohci_softc_t *sc = device_private(dv); 1151 uint32_t ctl; 1152 1153 mutex_spin_enter(&sc->sc_intr_lock); 1154 sc->sc_bus.ub_usepolling++; 1155 mutex_spin_exit(&sc->sc_intr_lock); 1156 1157 /* Some broken BIOSes do not recover these values */ 1158 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1159 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1160 sc->sc_ctrl_head->physaddr); 1161 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1162 sc->sc_bulk_head->physaddr); 1163 if (sc->sc_intre) 1164 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1165 (OHCI_ALL_INTRS | OHCI_MIE)); 1166 if (sc->sc_control) 1167 ctl = sc->sc_control; 1168 else 1169 ctl = OREAD4(sc, OHCI_CONTROL); 1170 ctl |= OHCI_SET_HCFS(OHCI_HCFS_RESUME); 1171 OWRITE4(sc, OHCI_CONTROL, ctl); 1172 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1173 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_SET_HCFS(OHCI_HCFS_OPERATIONAL); 1174 OWRITE4(sc, OHCI_CONTROL, ctl); 1175 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1176 sc->sc_control = sc->sc_intre = 0; 1177 1178 mutex_spin_enter(&sc->sc_intr_lock); 1179 sc->sc_bus.ub_usepolling--; 1180 mutex_spin_exit(&sc->sc_intr_lock); 1181 1182 return true; 1183 } 1184 1185 bool 1186 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1187 { 1188 ohci_softc_t *sc = device_private(dv); 1189 uint32_t ctl; 1190 1191 mutex_spin_enter(&sc->sc_intr_lock); 1192 sc->sc_bus.ub_usepolling++; 1193 mutex_spin_exit(&sc->sc_intr_lock); 1194 1195 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1196 if (sc->sc_control == 0) { 1197 /* 1198 * Preserve register values, in case that BIOS 1199 * does not recover them. 1200 */ 1201 sc->sc_control = ctl; 1202 sc->sc_intre = OREAD4(sc, 1203 OHCI_INTERRUPT_ENABLE); 1204 } 1205 ctl |= OHCI_SET_HCFS(OHCI_HCFS_SUSPEND); 1206 OWRITE4(sc, OHCI_CONTROL, ctl); 1207 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1208 1209 mutex_spin_enter(&sc->sc_intr_lock); 1210 sc->sc_bus.ub_usepolling--; 1211 mutex_spin_exit(&sc->sc_intr_lock); 1212 1213 return true; 1214 } 1215 1216 #ifdef OHCI_DEBUG 1217 void 1218 ohci_dumpregs(ohci_softc_t *sc) 1219 { 1220 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1221 1222 DPRINTF("rev=0x%08jx control=0x%08jx command=0x%08jx", 1223 OREAD4(sc, OHCI_REVISION), 1224 OREAD4(sc, OHCI_CONTROL), 1225 OREAD4(sc, OHCI_COMMAND_STATUS), 0); 1226 DPRINTF(" intrstat=0x%08jx intre=0x%08jx intrd=0x%08jx", 1227 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1228 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1229 OREAD4(sc, OHCI_INTERRUPT_DISABLE), 0); 1230 DPRINTF(" hcca=0x%08jx percur=0x%08jx ctrlhd=0x%08jx", 1231 OREAD4(sc, OHCI_HCCA), 1232 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1233 OREAD4(sc, OHCI_CONTROL_HEAD_ED), 0); 1234 DPRINTF(" ctrlcur=0x%08jx bulkhd=0x%08jx bulkcur=0x%08jx", 1235 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1236 OREAD4(sc, OHCI_BULK_HEAD_ED), 1237 OREAD4(sc, OHCI_BULK_CURRENT_ED) ,0); 1238 DPRINTF(" done=0x%08jx fmival=0x%08jx fmrem=0x%08jx", 1239 OREAD4(sc, OHCI_DONE_HEAD), 1240 OREAD4(sc, OHCI_FM_INTERVAL), 1241 OREAD4(sc, OHCI_FM_REMAINING), 0); 1242 DPRINTF(" fmnum=0x%08jx perst=0x%08jx lsthrs=0x%08jx", 1243 OREAD4(sc, OHCI_FM_NUMBER), 1244 OREAD4(sc, OHCI_PERIODIC_START), 1245 OREAD4(sc, OHCI_LS_THRESHOLD), 0); 1246 DPRINTF(" desca=0x%08jx descb=0x%08jx stat=0x%08jx", 1247 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1248 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1249 OREAD4(sc, OHCI_RH_STATUS), 0); 1250 DPRINTF(" port1=0x%08jx port2=0x%08jx", 1251 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1252 OREAD4(sc, OHCI_RH_PORT_STATUS(2)), 0, 0); 1253 usb_syncmem(&sc->sc_hccadma, 1254 offsetof(struct ohci_hcca, hcca_frame_number), 1255 sizeof(sc->sc_hcca->hcca_frame_number) + 1256 sizeof(sc->sc_hcca->hcca_done_head), 1257 BUS_DMASYNC_POSTREAD); 1258 DPRINTF(" HCCA: frame_number=0x%04jx done_head=0x%08jx", 1259 O32TOH(sc->sc_hcca->hcca_frame_number), 1260 O32TOH(sc->sc_hcca->hcca_done_head), 0, 0); 1261 } 1262 #endif 1263 1264 Static int ohci_intr1(ohci_softc_t *); 1265 1266 int 1267 ohci_intr(void *p) 1268 { 1269 ohci_softc_t *sc = p; 1270 int ret = 0; 1271 1272 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1273 1274 if (sc == NULL) 1275 return 0; 1276 1277 mutex_spin_enter(&sc->sc_intr_lock); 1278 1279 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1280 goto done; 1281 1282 /* If we get an interrupt while polling, then just ignore it. */ 1283 if (sc->sc_bus.ub_usepolling) { 1284 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1285 /* for level triggered intrs, should do something to ack */ 1286 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1287 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1288 1289 goto done; 1290 } 1291 1292 ret = ohci_intr1(sc); 1293 1294 done: 1295 mutex_spin_exit(&sc->sc_intr_lock); 1296 return ret; 1297 } 1298 1299 Static int 1300 ohci_intr1(ohci_softc_t *sc) 1301 { 1302 uint32_t intrs, eintrs; 1303 1304 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1305 1306 /* In case the interrupt occurs before initialization has completed. */ 1307 if (sc == NULL || sc->sc_hcca == NULL) { 1308 #ifdef DIAGNOSTIC 1309 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1310 #endif 1311 return 0; 1312 } 1313 1314 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1315 1316 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1317 if (!intrs) 1318 return 0; 1319 1320 /* Acknowledge */ 1321 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); 1322 eintrs = intrs & sc->sc_eintrs; 1323 DPRINTFN(7, "sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1324 DPRINTFN(7, "intrs=%#jx(%#jx) eintrs=%#jx(%#jx)", 1325 intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), eintrs, 1326 sc->sc_eintrs); 1327 1328 if (!eintrs) { 1329 return 0; 1330 } 1331 1332 if (eintrs & OHCI_SO) { 1333 sc->sc_overrun_cnt++; 1334 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1335 printf("%s: %u scheduling overruns\n", 1336 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1337 sc->sc_overrun_cnt = 0; 1338 } 1339 /* XXX do what */ 1340 eintrs &= ~OHCI_SO; 1341 } 1342 if (eintrs & OHCI_WDH) { 1343 /* 1344 * We block the interrupt below, and reenable it later from 1345 * ohci_softintr(). 1346 */ 1347 usb_schedsoftintr(&sc->sc_bus); 1348 } 1349 if (eintrs & OHCI_SF) { 1350 struct ohci_xfer *ox, *tmp; 1351 TAILQ_FOREACH_SAFE(ox, &sc->sc_abortingxfers, ox_abnext, tmp) { 1352 DPRINTFN(10, "SF %#jx xfer %#jx", (uintptr_t)sc, 1353 (uintptr_t)ox, 0, 0); 1354 ox->ox_abintrs &= ~OHCI_SF; 1355 KASSERT(ox->ox_abintrs == 0); 1356 TAILQ_REMOVE(&sc->sc_abortingxfers, ox, ox_abnext); 1357 } 1358 cv_broadcast(&sc->sc_abort_cv); 1359 1360 KASSERT(TAILQ_EMPTY(&sc->sc_abortingxfers)); 1361 DPRINTFN(10, "end SOF %#jx", (uintptr_t)sc, 0, 0, 0); 1362 /* Don't remove OHIC_SF from eintrs so it is blocked below */ 1363 } 1364 if (eintrs & OHCI_RD) { 1365 DPRINTFN(5, "resume detect sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1366 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1367 /* XXX process resume detect */ 1368 } 1369 if (eintrs & OHCI_UE) { 1370 DPRINTFN(5, "unrecoverable error sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1371 printf("%s: unrecoverable error, controller halted\n", 1372 device_xname(sc->sc_dev)); 1373 OWRITE4(sc, OHCI_CONTROL, OHCI_SET_HCFS(OHCI_HCFS_RESET)); 1374 /* XXX what else */ 1375 } 1376 if (eintrs & OHCI_RHSC) { 1377 /* 1378 * We block the interrupt below, and reenable it later from 1379 * a timeout. 1380 */ 1381 softint_schedule(sc->sc_rhsc_si); 1382 } 1383 1384 if (eintrs != 0) { 1385 /* Block unprocessed interrupts. */ 1386 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1387 sc->sc_eintrs &= ~eintrs; 1388 DPRINTF("sc %#jx blocking intrs %#jx", (uintptr_t)sc, 1389 eintrs, 0, 0); 1390 } 1391 1392 return 1; 1393 } 1394 1395 void 1396 ohci_rhsc_enable(void *v_sc) 1397 { 1398 ohci_softc_t *sc = v_sc; 1399 1400 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1401 DPRINTF("sc %#jx", (uintptr_t)sc, 0, 0, 0); 1402 mutex_spin_enter(&sc->sc_intr_lock); 1403 sc->sc_eintrs |= OHCI_RHSC; 1404 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1405 mutex_spin_exit(&sc->sc_intr_lock); 1406 } 1407 1408 #ifdef OHCI_DEBUG 1409 const char *ohci_cc_strs[] = { 1410 "NO_ERROR", 1411 "CRC", 1412 "BIT_STUFFING", 1413 "DATA_TOGGLE_MISMATCH", 1414 "STALL", 1415 "DEVICE_NOT_RESPONDING", 1416 "PID_CHECK_FAILURE", 1417 "UNEXPECTED_PID", 1418 "DATA_OVERRUN", 1419 "DATA_UNDERRUN", 1420 "BUFFER_OVERRUN", 1421 "BUFFER_UNDERRUN", 1422 "reserved", 1423 "reserved", 1424 "NOT_ACCESSED", 1425 "NOT_ACCESSED", 1426 }; 1427 #endif 1428 1429 void 1430 ohci_softintr(void *v) 1431 { 1432 struct usbd_bus *bus = v; 1433 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1434 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1435 ohci_soft_td_t *std, *sdone, *stdnext; 1436 struct usbd_xfer *xfer; 1437 struct ohci_pipe *opipe; 1438 int len, cc; 1439 int i, j, actlen, iframes, uedir; 1440 ohci_physaddr_t done = 0; 1441 1442 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1443 1444 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1445 1446 /* 1447 * Only read hccadone if WDH is set - we might get here from places 1448 * other than an interrupt 1449 */ 1450 if (!(OREAD4(sc, OHCI_INTERRUPT_STATUS) & OHCI_WDH)) { 1451 DPRINTFN(10, "no WDH %#jx", (uintptr_t)sc, 0, 0, 0); 1452 return; 1453 } 1454 1455 DPRINTFN(10, "WDH %#jx", (uintptr_t)sc, 0, 0, 0); 1456 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1457 sizeof(sc->sc_hcca->hcca_done_head), 1458 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1459 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1460 sc->sc_hcca->hcca_done_head = 0; 1461 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1462 sizeof(sc->sc_hcca->hcca_done_head), 1463 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1464 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1465 sc->sc_eintrs |= OHCI_WDH; 1466 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1467 1468 /* Reverse the done list. */ 1469 for (sdone = NULL, sidone = NULL; done != 0; ) { 1470 std = ohci_hash_find_td(sc, done); 1471 if (std != NULL) { 1472 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1473 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1474 std->dnext = sdone; 1475 done = O32TOH(std->td.td_nexttd); 1476 sdone = std; 1477 DPRINTFN(10, "add TD %#jx", (uintptr_t)std, 0, 0, 0); 1478 continue; 1479 } 1480 sitd = ohci_hash_find_itd(sc, done); 1481 if (sitd != NULL) { 1482 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1483 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1484 sitd->dnext = sidone; 1485 done = O32TOH(sitd->itd.itd_nextitd); 1486 sidone = sitd; 1487 DPRINTFN(5, "add ITD %#jx", (uintptr_t)sitd, 0, 0, 0); 1488 continue; 1489 } 1490 DPRINTFN(10, "addr %#jx not found", (uintptr_t)done, 0, 0, 0); 1491 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1492 (u_long)done); 1493 break; 1494 } 1495 1496 DPRINTFN(10, "sdone=%#jx sidone=%#jx", (uintptr_t)sdone, 1497 (uintptr_t)sidone, 0, 0); 1498 DPRINTFN(10, "--- TD dump start ---", 0, 0, 0, 0); 1499 #ifdef OHCI_DEBUG 1500 if (ohcidebug >= 10) { 1501 for (std = sdone; std; std = std->dnext) 1502 ohci_dump_td(sc, std); 1503 } 1504 #endif 1505 DPRINTFN(10, "--- TD dump end ---", 0, 0, 0, 0); 1506 1507 for (std = sdone; std; std = stdnext) { 1508 stdnext = std->dnext; 1509 if (std->held == NULL) { 1510 DPRINTFN(10, "std=%#jx held is null", (uintptr_t)std, 1511 0, 0, 0); 1512 ohci_hash_rem_td(sc, std); 1513 ohci_free_std_locked(sc, std); 1514 continue; 1515 } 1516 1517 xfer = std->xfer; 1518 DPRINTFN(10, "std=%#jx xfer=%#jx hcpriv=%#jx dnext=%#jx", 1519 (uintptr_t)std, (uintptr_t)xfer, 1520 (uintptr_t)(xfer ? xfer->ux_hcpriv : 0), (uintptr_t)stdnext); 1521 if (xfer == NULL) { 1522 /* 1523 * xfer == NULL: There seems to be no xfer associated 1524 * with this TD. It is tailp that happened to end up on 1525 * the done queue. 1526 * Shouldn't happen, but some chips are broken(?). 1527 */ 1528 continue; 1529 } 1530 /* 1531 * Try to claim this xfer for completion. If it has 1532 * already completed or aborted, drop it on the floor. 1533 */ 1534 if (!usbd_xfer_trycomplete(xfer)) 1535 continue; 1536 1537 len = std->len; 1538 if (std->td.td_cbp != 0) 1539 len -= O32TOH(std->td.td_be) - 1540 O32TOH(std->td.td_cbp) + 1; 1541 DPRINTFN(10, "len=%jd, flags=%#jx", len, std->flags, 0, 0); 1542 if (std->flags & OHCI_ADD_LEN) 1543 xfer->ux_actlen += len; 1544 1545 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1546 if (cc == OHCI_CC_NO_ERROR) { 1547 ohci_hash_rem_td(sc, std); 1548 if (std->flags & OHCI_CALL_DONE) { 1549 xfer->ux_status = USBD_NORMAL_COMPLETION; 1550 usb_transfer_complete(xfer); 1551 } 1552 } else { 1553 /* 1554 * Endpoint is halted. First unlink all the TDs 1555 * belonging to the failed transfer, and then restart 1556 * the endpoint. 1557 */ 1558 ohci_soft_td_t *p, *n; 1559 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1560 1561 DPRINTFN(10, "error cc=%jd", cc, 0, 0, 0); 1562 1563 /* remove xfer's TDs from the hash */ 1564 for (p = std; p->xfer == xfer; p = n) { 1565 n = p->nexttd; 1566 ohci_hash_rem_td(sc, p); 1567 } 1568 1569 ohci_soft_ed_t *sed = opipe->sed; 1570 1571 /* clear halt and TD chain, preserving toggle carry */ 1572 sed->ed.ed_headp = HTOO32(p->physaddr | 1573 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 1574 usb_syncmem(&sed->dma, 1575 sed->offs + offsetof(ohci_ed_t, ed_headp), 1576 sizeof(sed->ed.ed_headp), 1577 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1578 1579 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1580 1581 if (cc == OHCI_CC_DATA_UNDERRUN) 1582 xfer->ux_status = USBD_NORMAL_COMPLETION; 1583 else if (cc == OHCI_CC_STALL) 1584 xfer->ux_status = USBD_STALLED; 1585 else 1586 xfer->ux_status = USBD_IOERROR; 1587 usb_transfer_complete(xfer); 1588 } 1589 } 1590 DPRINTFN(10, "--- ITD dump start ---", 0, 0, 0, 0); 1591 #ifdef OHCI_DEBUG 1592 if (ohcidebug >= 10) { 1593 for (sitd = sidone; sitd; sitd = sitd->dnext) 1594 ohci_dump_itd(sc, sitd); 1595 } 1596 #endif 1597 DPRINTFN(10, "--- ITD dump end ---", 0, 0, 0, 0); 1598 1599 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1600 xfer = sitd->xfer; 1601 sitdnext = sitd->dnext; 1602 DPRINTFN(1, "sitd=%#jx xfer=%#jx hcpriv=%#jx", (uintptr_t)sitd, 1603 (uintptr_t)xfer, (uintptr_t)(xfer ? xfer->ux_hcpriv : 0), 1604 0); 1605 if (xfer == NULL) 1606 continue; 1607 1608 /* 1609 * Try to claim this xfer for completion. If it has 1610 * already completed or aborted, drop it on the floor. 1611 */ 1612 if (!usbd_xfer_trycomplete(xfer)) 1613 continue; 1614 1615 KASSERT(!sitd->isdone); 1616 #ifdef DIAGNOSTIC 1617 sitd->isdone = true; 1618 #endif 1619 if (sitd->flags & OHCI_CALL_DONE) { 1620 ohci_soft_itd_t *next; 1621 1622 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1623 opipe->isoc.inuse -= xfer->ux_nframes; 1624 uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc-> 1625 bEndpointAddress); 1626 xfer->ux_status = USBD_NORMAL_COMPLETION; 1627 actlen = 0; 1628 for (i = 0, sitd = xfer->ux_hcpriv;; 1629 sitd = next) { 1630 next = sitd->nextitd; 1631 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1632 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1633 xfer->ux_status = USBD_IOERROR; 1634 /* For input, update frlengths with actual */ 1635 /* XXX anything necessary for output? */ 1636 if (uedir == UE_DIR_IN && 1637 xfer->ux_status == USBD_NORMAL_COMPLETION) { 1638 iframes = OHCI_ITD_GET_FC(O32TOH( 1639 sitd->itd.itd_flags)); 1640 for (j = 0; j < iframes; i++, j++) { 1641 len = O16TOH(sitd-> 1642 itd.itd_offset[j]); 1643 if ((OHCI_ITD_PSW_GET_CC(len) & 1644 OHCI_CC_NOT_ACCESSED_MASK) 1645 == OHCI_CC_NOT_ACCESSED) 1646 len = 0; 1647 else 1648 len = OHCI_ITD_PSW_SIZE(len); 1649 xfer->ux_frlengths[i] = len; 1650 actlen += len; 1651 } 1652 } 1653 if (sitd->flags & OHCI_CALL_DONE) 1654 break; 1655 ohci_hash_rem_itd(sc, sitd); 1656 1657 } 1658 ohci_hash_rem_itd(sc, sitd); 1659 if (uedir == UE_DIR_IN && 1660 xfer->ux_status == USBD_NORMAL_COMPLETION) 1661 xfer->ux_actlen = actlen; 1662 xfer->ux_hcpriv = NULL; 1663 1664 usb_transfer_complete(xfer); 1665 } 1666 } 1667 1668 DPRINTFN(10, "done", 0, 0, 0, 0); 1669 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1670 } 1671 1672 void 1673 ohci_device_ctrl_done(struct usbd_xfer *xfer) 1674 { 1675 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1676 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1677 int len = UGETW(xfer->ux_request.wLength); 1678 int isread = (xfer->ux_request.bmRequestType & UT_READ); 1679 1680 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1681 DPRINTFN(10, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 1682 1683 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1684 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 1685 1686 if (len) 1687 usb_syncmem(&xfer->ux_dmabuf, 0, len, 1688 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1689 usb_syncmem(&opipe->ctrl.reqdma, 0, 1690 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1691 } 1692 1693 void 1694 ohci_device_intr_done(struct usbd_xfer *xfer) 1695 { 1696 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1697 int isread = 1698 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1699 1700 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1701 DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, 1702 xfer->ux_actlen, 0, 0); 1703 1704 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1705 1706 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1707 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1708 } 1709 1710 void 1711 ohci_device_bulk_done(struct usbd_xfer *xfer) 1712 { 1713 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1714 1715 int isread = 1716 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1717 1718 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1719 1720 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1721 DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 1722 0, 0); 1723 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1724 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1725 } 1726 1727 Static void 1728 ohci_rhsc_softint(void *arg) 1729 { 1730 ohci_softc_t *sc = arg; 1731 1732 mutex_enter(&sc->sc_lock); 1733 1734 ohci_rhsc(sc, sc->sc_intrxfer); 1735 1736 /* Do not allow RHSC interrupts > 1 per second */ 1737 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1738 1739 mutex_exit(&sc->sc_lock); 1740 } 1741 1742 void 1743 ohci_rhsc(ohci_softc_t *sc, struct usbd_xfer *xfer) 1744 { 1745 u_char *p; 1746 int i, m; 1747 int hstatus __unused; 1748 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1749 1750 KASSERT(mutex_owned(&sc->sc_lock)); 1751 1752 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1753 DPRINTF("sc=%#jx xfer=%#jx hstatus=0x%08jx", (uintptr_t)sc, 1754 (uintptr_t)xfer, hstatus, 0); 1755 1756 if (xfer == NULL) { 1757 /* Just ignore the change. */ 1758 return; 1759 } 1760 KASSERT(xfer == sc->sc_intrxfer); 1761 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 1762 1763 p = xfer->ux_buf; 1764 m = uimin(sc->sc_noport, xfer->ux_length * 8 - 1); 1765 memset(p, 0, xfer->ux_length); 1766 for (i = 1; i <= m; i++) { 1767 /* Pick out CHANGE bits from the status reg. */ 1768 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1769 p[i/8] |= 1 << (i%8); 1770 } 1771 DPRINTF("change=0x%02jx", *p, 0, 0, 0); 1772 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 1773 xfer->ux_actlen = xfer->ux_length; 1774 xfer->ux_status = USBD_NORMAL_COMPLETION; 1775 1776 usb_transfer_complete(xfer); 1777 } 1778 1779 void 1780 ohci_root_intr_done(struct usbd_xfer *xfer) 1781 { 1782 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1783 1784 KASSERT(mutex_owned(&sc->sc_lock)); 1785 1786 /* Claim the xfer so it doesn't get completed again. */ 1787 KASSERT(sc->sc_intrxfer == xfer); 1788 KASSERT(xfer->ux_status != USBD_IN_PROGRESS); 1789 sc->sc_intrxfer = NULL; 1790 } 1791 1792 void 1793 ohci_poll(struct usbd_bus *bus) 1794 { 1795 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1796 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1797 1798 #ifdef OHCI_DEBUG 1799 static int last; 1800 int new; 1801 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1802 if (new != last) { 1803 DPRINTFN(10, "intrs=0x%04jx", new, 0, 0, 0); 1804 last = new; 1805 } 1806 #endif 1807 sc->sc_eintrs |= OHCI_WDH; 1808 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1809 mutex_spin_enter(&sc->sc_intr_lock); 1810 ohci_intr1(sc); 1811 mutex_spin_exit(&sc->sc_intr_lock); 1812 } 1813 } 1814 1815 /* 1816 * Add an ED to the schedule. Called with USB lock held. 1817 */ 1818 Static void 1819 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1820 { 1821 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1822 DPRINTFN(8, "sed=%#jx head=%#jx", (uintptr_t)sed, (uintptr_t)head, 0, 1823 0); 1824 1825 KASSERT(mutex_owned(&sc->sc_lock)); 1826 1827 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1828 sizeof(head->ed.ed_nexted), 1829 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1830 sed->next = head->next; 1831 sed->ed.ed_nexted = head->ed.ed_nexted; 1832 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1833 sizeof(sed->ed.ed_nexted), 1834 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1835 head->next = sed; 1836 head->ed.ed_nexted = HTOO32(sed->physaddr); 1837 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1838 sizeof(head->ed.ed_nexted), 1839 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1840 } 1841 1842 /* 1843 * Remove an ED from the schedule. Called with USB lock held. 1844 */ 1845 Static void 1846 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1847 { 1848 ohci_soft_ed_t *p; 1849 1850 KASSERT(mutex_owned(&sc->sc_lock)); 1851 1852 /* XXX */ 1853 for (p = head; p != NULL && p->next != sed; p = p->next) 1854 ; 1855 KASSERT(p != NULL); 1856 1857 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1858 sizeof(sed->ed.ed_nexted), 1859 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1860 p->next = sed->next; 1861 p->ed.ed_nexted = sed->ed.ed_nexted; 1862 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1863 sizeof(p->ed.ed_nexted), 1864 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1865 } 1866 1867 /* 1868 * When a transfer is completed the TD is added to the done queue by 1869 * the host controller. This queue is the processed by software. 1870 * Unfortunately the queue contains the physical address of the TD 1871 * and we have no simple way to translate this back to a kernel address. 1872 * To make the translation possible (and fast) we use a hash table of 1873 * TDs currently in the schedule. The physical address is used as the 1874 * hash value. 1875 */ 1876 1877 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1878 /* Called with USB lock held. */ 1879 void 1880 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1881 { 1882 int h = HASH(std->physaddr); 1883 1884 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1885 1886 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1887 } 1888 1889 /* Called with USB lock held. */ 1890 void 1891 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1892 { 1893 1894 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1895 1896 LIST_REMOVE(std, hnext); 1897 } 1898 1899 ohci_soft_td_t * 1900 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1901 { 1902 int h = HASH(a); 1903 ohci_soft_td_t *std; 1904 1905 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1906 std != NULL; 1907 std = LIST_NEXT(std, hnext)) 1908 if (std->physaddr == a) 1909 return std; 1910 return NULL; 1911 } 1912 1913 /* Called with USB lock held. */ 1914 void 1915 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1916 { 1917 int h = HASH(sitd->physaddr); 1918 1919 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1920 1921 KASSERT(mutex_owned(&sc->sc_lock)); 1922 1923 DPRINTFN(10, "sitd=%#jx physaddr=0x%08jx", 1924 (uintptr_t)sitd, (u_long)sitd->physaddr, 0, 0); 1925 1926 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1927 } 1928 1929 /* Called with USB lock held. */ 1930 void 1931 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1932 { 1933 1934 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1935 1936 KASSERT(mutex_owned(&sc->sc_lock)); 1937 1938 DPRINTFN(10, "sitd=%#jx physaddr=0x%08jx", (uintptr_t)sitd, 1939 sitd->physaddr, 0, 0); 1940 1941 LIST_REMOVE(sitd, hnext); 1942 } 1943 1944 ohci_soft_itd_t * 1945 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1946 { 1947 int h = HASH(a); 1948 ohci_soft_itd_t *sitd; 1949 1950 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1951 sitd != NULL; 1952 sitd = LIST_NEXT(sitd, hnext)) 1953 if (sitd->physaddr == a) 1954 return sitd; 1955 return NULL; 1956 } 1957 1958 #ifdef OHCI_DEBUG 1959 void 1960 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 1961 { 1962 for (; std; std = std->nexttd) { 1963 ohci_dump_td(sc, std); 1964 KASSERTMSG(std->nexttd == NULL || std != std->nexttd, 1965 "std %p next %p", std, std->nexttd); 1966 } 1967 } 1968 1969 void 1970 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1971 { 1972 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1973 1974 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1975 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1976 1977 uint32_t flags = O32TOH(std->td.td_flags); 1978 DPRINTF("TD(%#jx) at 0x%08jx:", (uintptr_t)std, std->physaddr, 0, 0); 1979 DPRINTF(" round=%jd DP=%jx DI=%jx T=%jx", 1980 !!(flags & OHCI_TD_R), 1981 OHCI_TD_GET_DP(flags), 1982 OHCI_TD_GET_DI(flags), 1983 OHCI_TD_GET_TOGGLE(flags)); 1984 DPRINTF(" EC=%jd CC=%jd", OHCI_TD_GET_EC(flags), 1985 OHCI_TD_GET_CC(flags), 0, 0); 1986 DPRINTF(" td_cbp=0x%08jx td_nexttd=0x%08jx td_be=0x%08jx", 1987 (u_long)O32TOH(std->td.td_cbp), 1988 (u_long)O32TOH(std->td.td_nexttd), 1989 (u_long)O32TOH(std->td.td_be), 0); 1990 } 1991 1992 void 1993 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1994 { 1995 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1996 1997 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1998 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1999 2000 uint32_t flags = O32TOH(sitd->itd.itd_flags); 2001 DPRINTF("ITD(%#jx) at 0x%08jx", (uintptr_t)sitd, sitd->physaddr, 0, 0); 2002 DPRINTF(" sf=%jd di=%jd fc=%jd cc=%jd", 2003 OHCI_ITD_GET_SF(flags), OHCI_ITD_GET_DI(flags), 2004 OHCI_ITD_GET_FC(flags), OHCI_ITD_GET_CC(flags)); 2005 DPRINTF(" bp0=0x%08jx next=0x%08jx be=0x%08jx", 2006 O32TOH(sitd->itd.itd_bp0), 2007 O32TOH(sitd->itd.itd_nextitd), 2008 O32TOH(sitd->itd.itd_be), 0); 2009 CTASSERT(OHCI_ITD_NOFFSET == 8); 2010 DPRINTF(" offs[0] = 0x%04jx offs[1] = 0x%04jx " 2011 "offs[2] = 0x%04jx offs[3] = 0x%04jx", 2012 O16TOH(sitd->itd.itd_offset[0]), 2013 O16TOH(sitd->itd.itd_offset[1]), 2014 O16TOH(sitd->itd.itd_offset[2]), 2015 O16TOH(sitd->itd.itd_offset[3])); 2016 DPRINTF(" offs[4] = 0x%04jx offs[5] = 0x%04jx " 2017 "offs[6] = 0x%04jx offs[7] = 0x%04jx", 2018 O16TOH(sitd->itd.itd_offset[4]), 2019 O16TOH(sitd->itd.itd_offset[5]), 2020 O16TOH(sitd->itd.itd_offset[6]), 2021 O16TOH(sitd->itd.itd_offset[7])); 2022 } 2023 2024 void 2025 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2026 { 2027 for (; sitd; sitd = sitd->nextitd) 2028 ohci_dump_itd(sc, sitd); 2029 } 2030 2031 void 2032 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2033 { 2034 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2035 2036 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2037 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2038 2039 uint32_t flags = O32TOH(sed->ed.ed_flags); 2040 DPRINTF("ED(%#jx) at 0x%08jx:", (uintptr_t)sed, sed->physaddr, 0, 0); 2041 DPRINTF(" addr=%jd endpt=%jd maxp=%jd", 2042 OHCI_ED_GET_FA(flags), 2043 OHCI_ED_GET_EN(flags), 2044 OHCI_ED_GET_MAXP(flags), 2045 0); 2046 DPRINTF(" dir=%jd speed=%jd skip=%jd iso=%jd", 2047 OHCI_ED_GET_DIR(flags), 2048 __SHIFTOUT(flags, OHCI_ED_SPEED), 2049 __SHIFTOUT(flags, OHCI_ED_SKIP), 2050 OHCI_ED_GET_FORMAT(flags)); 2051 DPRINTF(" tailp=0x%08jx", (u_long)O32TOH(sed->ed.ed_tailp), 2052 0, 0, 0); 2053 DPRINTF(" headp=0x%08jx nexted=0x%08jx halted=%jd carry=%jd", 2054 O32TOH(sed->ed.ed_headp), O32TOH(sed->ed.ed_nexted), 2055 !!(O32TOH(sed->ed.ed_headp) & OHCI_HALTED), 2056 !!(O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 2057 } 2058 #endif 2059 2060 usbd_status 2061 ohci_open(struct usbd_pipe *pipe) 2062 { 2063 struct usbd_device *dev = pipe->up_dev; 2064 struct usbd_bus *bus = dev->ud_bus; 2065 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2066 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 2067 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2068 uint8_t addr = dev->ud_addr; 2069 uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2070 ohci_soft_ed_t *sed; 2071 ohci_soft_td_t *std; 2072 ohci_soft_itd_t *sitd; 2073 ohci_physaddr_t tdphys; 2074 uint32_t fmt; 2075 usbd_status err = USBD_NOMEM; 2076 int ival; 2077 2078 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2079 DPRINTFN(1, "pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, 2080 addr, ed->bEndpointAddress, bus->ub_rhaddr); 2081 2082 if (sc->sc_dying) { 2083 return USBD_IOERROR; 2084 } 2085 2086 std = NULL; 2087 sed = NULL; 2088 2089 if (addr == bus->ub_rhaddr) { 2090 switch (ed->bEndpointAddress) { 2091 case USB_CONTROL_ENDPOINT: 2092 pipe->up_methods = &roothub_ctrl_methods; 2093 break; 2094 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 2095 pipe->up_methods = &ohci_root_intr_methods; 2096 break; 2097 default: 2098 err = USBD_INVAL; 2099 goto bad; 2100 } 2101 } else { 2102 sed = ohci_alloc_sed(sc); 2103 if (sed == NULL) 2104 goto bad; 2105 opipe->sed = sed; 2106 if (xfertype == UE_ISOCHRONOUS) { 2107 sitd = ohci_alloc_sitd(sc); 2108 if (sitd == NULL) 2109 goto bad; 2110 2111 opipe->tail.itd = sitd; 2112 sitd->held = &opipe->tail.itd; 2113 tdphys = sitd->physaddr; 2114 fmt = OHCI_ED_SET_FORMAT(OHCI_ED_FORMAT_ISO); 2115 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2116 fmt |= OHCI_ED_SET_DIR(OHCI_ED_DIR_IN); 2117 else 2118 fmt |= OHCI_ED_SET_DIR(OHCI_ED_DIR_OUT); 2119 } else { 2120 std = ohci_alloc_std(sc); 2121 if (std == NULL) 2122 goto bad; 2123 2124 opipe->tail.td = std; 2125 std->held = &opipe->tail.td; 2126 tdphys = std->physaddr; 2127 fmt = 2128 OHCI_ED_SET_FORMAT(OHCI_ED_FORMAT_GEN) | 2129 OHCI_ED_SET_DIR(OHCI_ED_DIR_TD); 2130 } 2131 sed->ed.ed_flags = HTOO32( 2132 OHCI_ED_SET_FA(addr) | 2133 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2134 (dev->ud_speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2135 fmt | 2136 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2137 sed->ed.ed_headp = HTOO32(tdphys | 2138 (pipe->up_endpoint->ue_toggle ? OHCI_TOGGLECARRY : 0)); 2139 sed->ed.ed_tailp = HTOO32(tdphys); 2140 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2141 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2142 2143 switch (xfertype) { 2144 case UE_CONTROL: 2145 pipe->up_methods = &ohci_device_ctrl_methods; 2146 err = usb_allocmem(&sc->sc_bus, 2147 sizeof(usb_device_request_t), 0, 2148 USBMALLOC_COHERENT, &opipe->ctrl.reqdma); 2149 if (err) 2150 goto bad; 2151 mutex_enter(&sc->sc_lock); 2152 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2153 mutex_exit(&sc->sc_lock); 2154 break; 2155 case UE_INTERRUPT: 2156 pipe->up_methods = &ohci_device_intr_methods; 2157 ival = pipe->up_interval; 2158 if (ival == USBD_DEFAULT_INTERVAL) 2159 ival = ed->bInterval; 2160 err = ohci_device_setintr(sc, opipe, ival); 2161 if (err) 2162 goto bad; 2163 break; 2164 case UE_ISOCHRONOUS: 2165 pipe->up_serialise = false; 2166 pipe->up_methods = &ohci_device_isoc_methods; 2167 return ohci_setup_isoc(pipe); 2168 case UE_BULK: 2169 pipe->up_methods = &ohci_device_bulk_methods; 2170 mutex_enter(&sc->sc_lock); 2171 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2172 mutex_exit(&sc->sc_lock); 2173 break; 2174 } 2175 } 2176 2177 return USBD_NORMAL_COMPLETION; 2178 2179 bad: 2180 if (std != NULL) { 2181 ohci_free_std(sc, std); 2182 } 2183 if (sed != NULL) 2184 ohci_free_sed(sc, sed); 2185 return err; 2186 2187 } 2188 2189 /* 2190 * Close a reqular pipe. 2191 * Assumes that there are no pending transactions. 2192 */ 2193 void 2194 ohci_close_pipe(struct usbd_pipe *pipe, ohci_soft_ed_t *head) 2195 { 2196 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2197 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2198 ohci_soft_ed_t *sed = opipe->sed; 2199 2200 KASSERT(mutex_owned(&sc->sc_lock)); 2201 2202 #ifdef DIAGNOSTIC 2203 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2204 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2205 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2206 ohci_soft_td_t *std; 2207 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2208 printf("ohci_close_pipe: pipe not empty sed=%p hd=%#x " 2209 "tl=%#x pipe=%p, std=%p\n", sed, 2210 (int)O32TOH(sed->ed.ed_headp), 2211 (int)O32TOH(sed->ed.ed_tailp), 2212 pipe, std); 2213 #ifdef OHCI_DEBUG 2214 usbd_dump_pipe(&opipe->pipe); 2215 ohci_dump_ed(sc, sed); 2216 if (std) 2217 ohci_dump_td(sc, std); 2218 #endif 2219 usb_delay_ms(&sc->sc_bus, 2); 2220 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2221 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2222 printf("ohci_close_pipe: pipe still not empty\n"); 2223 } 2224 #endif 2225 ohci_rem_ed(sc, sed, head); 2226 /* Make sure the host controller is not touching this ED */ 2227 usb_delay_ms(&sc->sc_bus, 1); 2228 pipe->up_endpoint->ue_toggle = 2229 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2230 ohci_free_sed_locked(sc, opipe->sed); 2231 } 2232 2233 /* 2234 * Arrange for the hardware to tells us that it is not still processing 2235 * the TDs by setting the sKip bit and requesting a SOF interrupt 2236 * 2237 * Once we see the SOF interrupt we can check the transfer TDs/iTDs to see if 2238 * they've been processed and either 2239 * a) if they're unused recover them for later use, or 2240 * b) if they've been used allocate new TD/iTDs to replace those 2241 * used. The softint handler will free the old ones. 2242 */ 2243 void 2244 ohci_abortx(struct usbd_xfer *xfer) 2245 { 2246 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2247 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2248 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2249 ohci_soft_ed_t *sed = opipe->sed; 2250 ohci_soft_td_t *p, *n; 2251 ohci_physaddr_t headp; 2252 int hit; 2253 2254 DPRINTF("xfer=%#jx pipe=%#jx sed=%#jx", (uintptr_t)xfer, 2255 (uintptr_t)opipe, (uintptr_t)sed, 0); 2256 2257 KASSERT(mutex_owned(&sc->sc_lock)); 2258 ASSERT_SLEEPABLE(); 2259 2260 KASSERTMSG((xfer->ux_status == USBD_CANCELLED || 2261 xfer->ux_status == USBD_TIMEOUT), 2262 "bad abort status: %d", xfer->ux_status); 2263 2264 /* 2265 * If we're dying, skip the hardware action and just notify the 2266 * software that we're done. 2267 */ 2268 if (sc->sc_dying) { 2269 DPRINTFN(4, "xfer %#jx dying %ju", (uintptr_t)xfer, 2270 xfer->ux_status, 0, 0); 2271 goto dying; 2272 } 2273 2274 /* 2275 * HC Step 1: Unless the endpoint is already halted, we set the 2276 * endpoint descriptor sKip bit and wait for hardware to complete 2277 * processing. We ensure the HC stops processing the endpoint by 2278 * waiting for the next start of frame (OHCI_SF) 2279 */ 2280 DPRINTFN(1, "stop ed=%#jx", (uintptr_t)sed, 0, 0, 0); 2281 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2282 sizeof(sed->ed.ed_flags), 2283 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2284 if (!(sed->ed.ed_flags & OHCI_HALTED)) { 2285 /* force hardware skip */ 2286 DPRINTFN(1, "pausing ed=%#jx", (uintptr_t)sed, 0, 0, 0); 2287 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2288 usb_syncmem(&sed->dma, 2289 sed->offs + offsetof(ohci_ed_t, ed_flags), 2290 sizeof(sed->ed.ed_flags), 2291 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2292 2293 DPRINTFN(10, "SF %#jx xfer %#jx", (uintptr_t)sc, 2294 (uintptr_t)xfer, 0, 0); 2295 2296 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2297 ox->ox_abintrs = OHCI_SF; 2298 2299 mutex_enter(&sc->sc_intr_lock); 2300 TAILQ_INSERT_TAIL(&sc->sc_abortingxfers, ox, ox_abnext); 2301 2302 /* Clear any previous SF interrupt */ 2303 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_SF); 2304 2305 /* Tell interrupt handler and HC SF interrupt is requested */ 2306 sc->sc_eintrs |= OHCI_SF; 2307 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_SF); 2308 /* 2309 * Step 2: Wait until we know hardware has finished any 2310 * processing of the end-point. 2311 */ 2312 while (ox->ox_abintrs != 0) { 2313 DPRINTFN(10, "SF %#jx xfer %#jx intrs %#x", 2314 (uintptr_t)sc, (uintptr_t)xfer, 2315 (uintptr_t)ox->ox_abintrs, 0); 2316 cv_wait(&sc->sc_abort_cv, &sc->sc_intr_lock); 2317 } 2318 mutex_exit(&sc->sc_intr_lock); 2319 } else { 2320 DPRINTFN(1, "halted ed=%#jx", (uintptr_t)sed, 0, 0, 0); 2321 } 2322 2323 /* 2324 * HC Step 3: Remove any vestiges of the xfer from the hardware. 2325 * There are two complications here 2326 * 2327 * 1) the hardware may have executed beyond the xfer we're trying to 2328 * abort. So as we're scanning the TDs of this xfer we check if 2329 * the hardware points to any of them. 2330 * 2331 * 2) the hardware may have only partially excuted the transfer 2332 * which means some TDs will appear on the done list. Wait for 2333 * WDH so we can remove them safely. 2334 */ 2335 p = xfer->ux_hcpriv; 2336 KASSERT(p); 2337 2338 #ifdef OHCI_DEBUG 2339 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2340 2341 if (ohcidebug >= 2) { 2342 DPRINTF("sed:", 0, 0, 0, 0); 2343 ohci_dump_ed(sc, sed); 2344 ohci_dump_tds(sc, p); 2345 } 2346 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2347 #endif 2348 2349 2350 #define OHCI_CC_ACCESSED_P(x) \ 2351 (((x) & OHCI_CC_NOT_ACCESSED_MASK) != OHCI_CC_NOT_ACCESSED) 2352 2353 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2354 hit = 0; 2355 for (; p->xfer == xfer; p = n) { 2356 hit |= headp == p->physaddr; 2357 n = p->nexttd; 2358 2359 int cc = OHCI_TD_GET_CC(O32TOH(p->td.td_flags)); 2360 if (!OHCI_CC_ACCESSED_P(cc)) { 2361 ohci_hash_rem_td(sc, p); 2362 continue; 2363 } 2364 DPRINTFN(10, "xfer=%#jx has been touched by HC", (uintptr_t)p, 2365 0, 0, 0); 2366 2367 mutex_exit(&sc->sc_lock); 2368 ohci_soft_td_t *std; 2369 for (;;) { 2370 std = ohci_alloc_std(sc); 2371 if (std) 2372 break; 2373 kpause("ohciabt2", true, hz, NULL); 2374 } 2375 2376 mutex_enter(&sc->sc_lock); 2377 if (sc->sc_dying) { 2378 DPRINTFN(4, "xfer %#jx dying %ju", (uintptr_t)xfer, 2379 xfer->ux_status, 0, 0); 2380 goto dying; 2381 } 2382 2383 DPRINTFN(10, "new std=%#jx now held at %#jx", (uintptr_t)std, 2384 (uintptr_t)p->held, 0, 0); 2385 *(p->held) = std; 2386 std->held = p->held; 2387 std->xfer = xfer; 2388 p->held = NULL; 2389 } 2390 /* Zap headp register if hardware pointed inside the xfer. */ 2391 if (hit) { 2392 DPRINTFN(1, "set hd=0x%08jx, tl=0x%08jx", (int)p->physaddr, 2393 (int)O32TOH(sed->ed.ed_tailp), 0, 0); 2394 /* unlink TDs, preserving toggle carry */ 2395 sed->ed.ed_headp = HTOO32(p->physaddr | 2396 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 2397 usb_syncmem(&sed->dma, 2398 sed->offs + offsetof(ohci_ed_t, ed_headp), 2399 sizeof(sed->ed.ed_headp), 2400 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2401 } else { 2402 DPRINTFN(1, "no hit", 0, 0, 0, 0); 2403 } 2404 2405 /* 2406 * HC Step 4: Turn on hardware again. 2407 */ 2408 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2409 sizeof(sed->ed.ed_flags), 2410 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2411 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2412 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2413 sizeof(sed->ed.ed_flags), 2414 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2415 2416 /* 2417 * Final step: Notify completion to waiting xfers. 2418 */ 2419 dying: 2420 usb_transfer_complete(xfer); 2421 DPRINTFN(14, "end", 0, 0, 0, 0); 2422 2423 KASSERT(mutex_owned(&sc->sc_lock)); 2424 } 2425 2426 /* 2427 * Data structures and routines to emulate the root hub. 2428 */ 2429 Static int 2430 ohci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2431 void *buf, int buflen) 2432 { 2433 ohci_softc_t *sc = OHCI_BUS2SC(bus); 2434 usb_port_status_t ps; 2435 uint16_t len, value, index; 2436 int l, totlen = 0; 2437 int port, i; 2438 uint32_t v; 2439 2440 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2441 2442 if (sc->sc_dying) 2443 return -1; 2444 2445 DPRINTFN(4, "type=0x%02jx request=%02jx", req->bmRequestType, 2446 req->bRequest, 0, 0); 2447 2448 len = UGETW(req->wLength); 2449 value = UGETW(req->wValue); 2450 index = UGETW(req->wIndex); 2451 2452 #define C(x,y) ((x) | ((y) << 8)) 2453 switch (C(req->bRequest, req->bmRequestType)) { 2454 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2455 DPRINTFN(8, "wValue=0x%04jx", value, 0, 0, 0); 2456 if (len == 0) 2457 break; 2458 switch (value) { 2459 #define sd ((usb_string_descriptor_t *)buf) 2460 case C(2, UDESC_STRING): 2461 /* Product */ 2462 totlen = usb_makestrdesc(sd, len, "OHCI root hub"); 2463 break; 2464 #undef sd 2465 default: 2466 /* default from usbroothub */ 2467 return buflen; 2468 } 2469 break; 2470 2471 /* Hub requests */ 2472 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2473 break; 2474 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2475 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", 2476 index, value, 0, 0); 2477 if (index < 1 || index > sc->sc_noport) { 2478 return -1; 2479 } 2480 port = OHCI_RH_PORT_STATUS(index); 2481 switch(value) { 2482 case UHF_PORT_ENABLE: 2483 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2484 break; 2485 case UHF_PORT_SUSPEND: 2486 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2487 break; 2488 case UHF_PORT_POWER: 2489 /* Yes, writing to the LOW_SPEED bit clears power. */ 2490 OWRITE4(sc, port, UPS_LOW_SPEED); 2491 break; 2492 case UHF_C_PORT_CONNECTION: 2493 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2494 break; 2495 case UHF_C_PORT_ENABLE: 2496 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2497 break; 2498 case UHF_C_PORT_SUSPEND: 2499 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2500 break; 2501 case UHF_C_PORT_OVER_CURRENT: 2502 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2503 break; 2504 case UHF_C_PORT_RESET: 2505 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2506 break; 2507 default: 2508 return -1; 2509 } 2510 switch(value) { 2511 case UHF_C_PORT_CONNECTION: 2512 case UHF_C_PORT_ENABLE: 2513 case UHF_C_PORT_SUSPEND: 2514 case UHF_C_PORT_OVER_CURRENT: 2515 case UHF_C_PORT_RESET: 2516 /* Enable RHSC interrupt if condition is cleared. */ 2517 if ((OREAD4(sc, port) >> 16) == 0) 2518 ohci_rhsc_enable(sc); 2519 break; 2520 default: 2521 break; 2522 } 2523 break; 2524 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2525 if (len == 0) 2526 break; 2527 if ((value & 0xff) != 0) { 2528 return -1; 2529 } 2530 usb_hub_descriptor_t hubd; 2531 2532 totlen = uimin(buflen, sizeof(hubd)); 2533 memcpy(&hubd, buf, totlen); 2534 2535 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2536 hubd.bNbrPorts = sc->sc_noport; 2537 USETW(hubd.wHubCharacteristics, 2538 (v & OHCI_RHD_NPS ? UHD_PWR_NO_SWITCH : 2539 v & OHCI_RHD_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2540 /* XXX overcurrent */ 2541 ); 2542 hubd.bPwrOn2PwrGood = OHCI_RHD_GET_POTPGT(v); 2543 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2544 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2545 hubd.DeviceRemovable[i++] = (uint8_t)v; 2546 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2547 totlen = uimin(totlen, hubd.bDescLength); 2548 memcpy(buf, &hubd, totlen); 2549 break; 2550 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2551 if (len != 4) { 2552 return -1; 2553 } 2554 memset(buf, 0, len); /* ? XXX */ 2555 totlen = len; 2556 break; 2557 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2558 DPRINTFN(8, "get port status i=%jd", index, 0, 0, 0); 2559 if (index < 1 || index > sc->sc_noport) { 2560 return -1; 2561 } 2562 if (len != 4) { 2563 return -1; 2564 } 2565 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2566 DPRINTFN(8, "port status=0x%04jx", v, 0, 0, 0); 2567 USETW(ps.wPortStatus, v); 2568 USETW(ps.wPortChange, v >> 16); 2569 totlen = uimin(len, sizeof(ps)); 2570 memcpy(buf, &ps, totlen); 2571 break; 2572 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2573 return -1; 2574 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2575 break; 2576 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2577 if (index < 1 || index > sc->sc_noport) { 2578 return -1; 2579 } 2580 port = OHCI_RH_PORT_STATUS(index); 2581 switch(value) { 2582 case UHF_PORT_ENABLE: 2583 OWRITE4(sc, port, UPS_PORT_ENABLED); 2584 break; 2585 case UHF_PORT_SUSPEND: 2586 OWRITE4(sc, port, UPS_SUSPEND); 2587 break; 2588 case UHF_PORT_RESET: 2589 DPRINTFN(5, "reset port %jd", index, 0, 0, 0); 2590 OWRITE4(sc, port, UPS_RESET); 2591 for (i = 0; i < 5; i++) { 2592 usb_delay_ms(&sc->sc_bus, 2593 USB_PORT_ROOT_RESET_DELAY); 2594 if (sc->sc_dying) { 2595 return -1; 2596 } 2597 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2598 break; 2599 } 2600 DPRINTFN(8, "port %jd reset, status = 0x%04jx", index, 2601 OREAD4(sc, port), 0, 0); 2602 break; 2603 case UHF_PORT_POWER: 2604 DPRINTFN(2, "set port power %jd", index, 0, 0, 0); 2605 OWRITE4(sc, port, UPS_PORT_POWER); 2606 break; 2607 default: 2608 return -1; 2609 } 2610 break; 2611 default: 2612 /* default from usbroothub */ 2613 return buflen; 2614 } 2615 2616 return totlen; 2617 } 2618 2619 Static usbd_status 2620 ohci_root_intr_transfer(struct usbd_xfer *xfer) 2621 { 2622 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2623 usbd_status err; 2624 2625 /* Insert last in queue. */ 2626 mutex_enter(&sc->sc_lock); 2627 err = usb_insert_transfer(xfer); 2628 mutex_exit(&sc->sc_lock); 2629 if (err) 2630 return err; 2631 2632 /* Pipe isn't running, start first */ 2633 return ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2634 } 2635 2636 Static usbd_status 2637 ohci_root_intr_start(struct usbd_xfer *xfer) 2638 { 2639 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2640 const bool polling = sc->sc_bus.ub_usepolling; 2641 2642 if (sc->sc_dying) 2643 return USBD_IOERROR; 2644 2645 if (!polling) 2646 mutex_enter(&sc->sc_lock); 2647 KASSERT(sc->sc_intrxfer == NULL); 2648 sc->sc_intrxfer = xfer; 2649 xfer->ux_status = USBD_IN_PROGRESS; 2650 if (!polling) 2651 mutex_exit(&sc->sc_lock); 2652 2653 return USBD_IN_PROGRESS; 2654 } 2655 2656 /* Abort a root interrupt request. */ 2657 Static void 2658 ohci_root_intr_abort(struct usbd_xfer *xfer) 2659 { 2660 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2661 2662 KASSERT(mutex_owned(&sc->sc_lock)); 2663 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2664 2665 /* If xfer has already completed, nothing to do here. */ 2666 if (sc->sc_intrxfer == NULL) 2667 return; 2668 2669 /* 2670 * Otherwise, sc->sc_intrxfer had better be this transfer. 2671 * Cancel it. 2672 */ 2673 KASSERT(sc->sc_intrxfer == xfer); 2674 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 2675 xfer->ux_status = USBD_CANCELLED; 2676 usb_transfer_complete(xfer); 2677 } 2678 2679 /* Close the root pipe. */ 2680 Static void 2681 ohci_root_intr_close(struct usbd_pipe *pipe) 2682 { 2683 ohci_softc_t *sc __diagused = OHCI_PIPE2SC(pipe); 2684 2685 KASSERT(mutex_owned(&sc->sc_lock)); 2686 2687 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2688 2689 /* 2690 * Caller must guarantee the xfer has completed first, by 2691 * closing the pipe only after normal completion or an abort. 2692 */ 2693 KASSERT(sc->sc_intrxfer == NULL); 2694 } 2695 2696 /************************/ 2697 2698 int 2699 ohci_device_ctrl_init(struct usbd_xfer *xfer) 2700 { 2701 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2702 usb_device_request_t *req = &xfer->ux_request; 2703 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2704 ohci_soft_td_t *stat, *setup; 2705 int isread = req->bmRequestType & UT_READ; 2706 int len = xfer->ux_bufsize; 2707 int err = ENOMEM; 2708 2709 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2710 2711 setup = ohci_alloc_std(sc); 2712 if (setup == NULL) { 2713 goto bad1; 2714 } 2715 stat = ohci_alloc_std(sc); 2716 if (stat == NULL) { 2717 goto bad2; 2718 } 2719 2720 ox->ox_setup = setup; 2721 ox->ox_stat = stat; 2722 ox->ox_nstd = 0; 2723 setup->held = &ox->ox_setup; 2724 stat->held = &ox->ox_stat; 2725 2726 DPRINTFN(10, "xfer=%#jx setup=%#jx held at %#jx", (uintptr_t)ox, 2727 (uintptr_t)setup, (uintptr_t)setup->held, 0); 2728 DPRINTFN(10, "xfer=%#jx stat= %#jx held at %#jx", (uintptr_t)ox, 2729 (uintptr_t)stat, (uintptr_t)stat->held, 0); 2730 2731 /* Set up data transaction */ 2732 if (len != 0) { 2733 err = ohci_alloc_std_chain(sc, xfer, len, isread); 2734 if (err) { 2735 goto bad3; 2736 } 2737 } 2738 return 0; 2739 2740 bad3: 2741 ohci_free_std(sc, stat); 2742 bad2: 2743 ohci_free_std(sc, setup); 2744 bad1: 2745 return err; 2746 } 2747 2748 void 2749 ohci_device_ctrl_fini(struct usbd_xfer *xfer) 2750 { 2751 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2752 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2753 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2754 2755 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2756 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 2757 2758 mutex_enter(&sc->sc_lock); 2759 if (ox->ox_setup != opipe->tail.td) { 2760 ohci_free_std_locked(sc, ox->ox_setup); 2761 } 2762 for (size_t i = 0; i < ox->ox_nstd; i++) { 2763 ohci_soft_td_t *std = ox->ox_stds[i]; 2764 if (std == NULL) 2765 break; 2766 ohci_free_std_locked(sc, std); 2767 } 2768 ohci_free_std_locked(sc, ox->ox_stat); 2769 mutex_exit(&sc->sc_lock); 2770 2771 if (ox->ox_nstd) { 2772 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 2773 kmem_free(ox->ox_stds, sz); 2774 } 2775 } 2776 2777 Static usbd_status 2778 ohci_device_ctrl_transfer(struct usbd_xfer *xfer) 2779 { 2780 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2781 usbd_status err; 2782 2783 /* Insert last in queue. */ 2784 mutex_enter(&sc->sc_lock); 2785 err = usb_insert_transfer(xfer); 2786 mutex_exit(&sc->sc_lock); 2787 if (err) 2788 return err; 2789 2790 /* Pipe isn't running, start first */ 2791 return ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2792 } 2793 2794 Static usbd_status 2795 ohci_device_ctrl_start(struct usbd_xfer *xfer) 2796 { 2797 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2798 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2799 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2800 usb_device_request_t *req = &xfer->ux_request; 2801 struct usbd_device *dev __diagused = opipe->pipe.up_dev; 2802 ohci_soft_td_t *setup, *stat, *next, *tail; 2803 ohci_soft_ed_t *sed; 2804 int isread; 2805 int len; 2806 const bool polling = sc->sc_bus.ub_usepolling; 2807 2808 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2809 2810 if (sc->sc_dying) 2811 return USBD_IOERROR; 2812 2813 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2814 2815 isread = req->bmRequestType & UT_READ; 2816 len = UGETW(req->wLength); 2817 2818 DPRINTF("xfer=%#jx len=%jd, addr=%jd, endpt=%jd", (uintptr_t)xfer, len, 2819 dev->ud_addr, opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress); 2820 DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx", 2821 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2822 UGETW(req->wIndex)); 2823 2824 /* Need to take lock here for pipe->tail.td */ 2825 if (!polling) 2826 mutex_enter(&sc->sc_lock); 2827 2828 /* 2829 * Use the pipe "tail" TD as our first and loan our first TD to the 2830 * next transfer 2831 */ 2832 setup = opipe->tail.td; 2833 opipe->tail.td = ox->ox_setup; 2834 ox->ox_setup = setup; 2835 setup->held = &ox->ox_setup; 2836 2837 DPRINTFN(10, "xfer=%#jx new setup=%#jx held at %#jx", (uintptr_t)ox, 2838 (uintptr_t)setup, (uintptr_t)setup->held, 0); 2839 2840 stat = ox->ox_stat; 2841 2842 /* point at sentinel */ 2843 tail = opipe->tail.td; 2844 tail->held = &opipe->tail.td; 2845 sed = opipe->sed; 2846 2847 DPRINTFN(10, "xfer=%#jx new tail=%#jx held at %#jx", (uintptr_t)ox, 2848 (uintptr_t)tail, (uintptr_t)tail->held, 0); 2849 2850 KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->ud_addr, 2851 "address ED %" __PRIuBITS " pipe %d\n", 2852 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->ud_addr); 2853 KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) == 2854 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 2855 "MPL ED %" __PRIuBITS " pipe %d\n", 2856 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), 2857 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 2858 2859 /* next will point to data if len != 0 */ 2860 next = stat; 2861 2862 /* Set up data transaction */ 2863 if (len != 0) { 2864 ohci_soft_td_t *std; 2865 ohci_soft_td_t *end; 2866 2867 next = ox->ox_stds[0]; 2868 ohci_reset_std_chain(sc, xfer, len, isread, next, &end); 2869 2870 end->td.td_nexttd = HTOO32(stat->physaddr); 2871 end->nexttd = stat; 2872 2873 usb_syncmem(&end->dma, end->offs, sizeof(end->td), 2874 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2875 2876 usb_syncmem(&xfer->ux_dmabuf, 0, len, 2877 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2878 std = ox->ox_stds[0]; 2879 /* Start toggle at 1 and then use the carried toggle. */ 2880 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 2881 std->td.td_flags |= HTOO32(OHCI_TD_SET_TOGGLE(OHCI_TD_TOGGLE_1)); 2882 usb_syncmem(&std->dma, 2883 std->offs + offsetof(ohci_td_t, td_flags), 2884 sizeof(std->td.td_flags), 2885 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2886 } 2887 2888 DPRINTFN(8, "setup %#jx data %#jx stat %#jx tail %#jx", 2889 (uintptr_t)setup, 2890 (uintptr_t)(len != 0 ? ox->ox_stds[0] : NULL), (uintptr_t)stat, 2891 (uintptr_t)tail); 2892 KASSERT(opipe->tail.td == tail); 2893 2894 memcpy(KERNADDR(&opipe->ctrl.reqdma, 0), req, sizeof(*req)); 2895 usb_syncmem(&opipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2896 2897 setup->td.td_flags = HTOO32( 2898 OHCI_TD_SET_DP(OHCI_TD_DP_SETUP) | 2899 OHCI_TD_SET_CC(OHCI_TD_NOCC) | 2900 OHCI_TD_SET_TOGGLE(OHCI_TD_TOGGLE_0) | 2901 OHCI_TD_SET_DI(OHCI_TD_NOINTR) 2902 ); 2903 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->ctrl.reqdma, 0)); 2904 setup->td.td_nexttd = HTOO32(next->physaddr); 2905 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof(*req) - 1); 2906 setup->nexttd = next; 2907 setup->len = 0; 2908 setup->xfer = xfer; 2909 setup->flags = 0; 2910 ohci_hash_add_td(sc, setup); 2911 2912 xfer->ux_hcpriv = setup; 2913 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2914 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2915 2916 stat->td.td_flags = HTOO32( 2917 OHCI_TD_SET_DP(isread ? OHCI_TD_DP_OUT : OHCI_TD_DP_IN) | 2918 OHCI_TD_SET_CC(OHCI_TD_NOCC) | 2919 OHCI_TD_SET_TOGGLE(OHCI_TD_TOGGLE_1) | 2920 OHCI_TD_SET_DI(1) 2921 ); 2922 stat->td.td_cbp = 0; 2923 stat->td.td_nexttd = HTOO32(tail->physaddr); 2924 stat->td.td_be = 0; 2925 stat->nexttd = tail; 2926 stat->flags = OHCI_CALL_DONE; 2927 stat->len = 0; 2928 stat->xfer = xfer; 2929 ohci_hash_add_td(sc, stat); 2930 2931 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2932 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2933 2934 memset(&tail->td, 0, sizeof(tail->td)); 2935 tail->nexttd = NULL; 2936 tail->xfer = NULL; 2937 2938 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 2939 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2940 2941 #ifdef OHCI_DEBUG 2942 USBHIST_LOGN(ohcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2943 if (ohcidebug >= 5) { 2944 ohci_dump_ed(sc, sed); 2945 ohci_dump_tds(sc, setup); 2946 } 2947 USBHIST_LOGN(ohcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2948 #endif 2949 2950 /* Insert ED in schedule */ 2951 sed->ed.ed_tailp = HTOO32(tail->physaddr); 2952 usb_syncmem(&sed->dma, 2953 sed->offs + offsetof(ohci_ed_t, ed_tailp), 2954 sizeof(sed->ed.ed_tailp), 2955 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2956 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2957 usbd_xfer_schedule_timeout(xfer); 2958 2959 DPRINTF("done", 0, 0, 0, 0); 2960 2961 xfer->ux_status = USBD_IN_PROGRESS; 2962 if (!polling) 2963 mutex_exit(&sc->sc_lock); 2964 2965 return USBD_IN_PROGRESS; 2966 } 2967 2968 /* Abort a device control request. */ 2969 Static void 2970 ohci_device_ctrl_abort(struct usbd_xfer *xfer) 2971 { 2972 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 2973 2974 KASSERT(mutex_owned(&sc->sc_lock)); 2975 2976 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2977 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 2978 usbd_xfer_abort(xfer); 2979 } 2980 2981 /* Close a device control pipe. */ 2982 Static void 2983 ohci_device_ctrl_close(struct usbd_pipe *pipe) 2984 { 2985 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2986 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2987 2988 KASSERT(mutex_owned(&sc->sc_lock)); 2989 2990 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2991 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 2992 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2993 ohci_free_std_locked(sc, opipe->tail.td); 2994 2995 usb_freemem(&sc->sc_bus, &opipe->ctrl.reqdma); 2996 } 2997 2998 /************************/ 2999 3000 Static void 3001 ohci_device_clear_toggle(struct usbd_pipe *pipe) 3002 { 3003 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3004 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3005 3006 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 3007 } 3008 3009 Static void 3010 ohci_noop(struct usbd_pipe *pipe) 3011 { 3012 } 3013 3014 Static int 3015 ohci_device_bulk_init(struct usbd_xfer *xfer) 3016 { 3017 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3018 int len = xfer->ux_bufsize; 3019 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3020 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3021 int err; 3022 3023 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3024 3025 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3026 3027 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 3028 len, isread, xfer->ux_flags); 3029 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 3030 3031 /* Allocate a chain of new TDs (including a new tail). */ 3032 err = ohci_alloc_std_chain(sc, xfer, len, isread); 3033 if (err) 3034 return err; 3035 3036 return 0; 3037 } 3038 3039 Static void 3040 ohci_device_bulk_fini(struct usbd_xfer *xfer) 3041 { 3042 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3043 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3044 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3045 3046 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3047 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 3048 3049 mutex_enter(&sc->sc_lock); 3050 for (size_t i = 0; i < ox->ox_nstd; i++) { 3051 ohci_soft_td_t *std = ox->ox_stds[i]; 3052 if (std == NULL) 3053 break; 3054 if (std != opipe->tail.td) 3055 ohci_free_std_locked(sc, std); 3056 } 3057 mutex_exit(&sc->sc_lock); 3058 3059 if (ox->ox_nstd) { 3060 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 3061 kmem_free(ox->ox_stds, sz); 3062 } 3063 } 3064 3065 Static usbd_status 3066 ohci_device_bulk_transfer(struct usbd_xfer *xfer) 3067 { 3068 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3069 usbd_status err; 3070 3071 /* Insert last in queue. */ 3072 mutex_enter(&sc->sc_lock); 3073 err = usb_insert_transfer(xfer); 3074 mutex_exit(&sc->sc_lock); 3075 if (err) 3076 return err; 3077 3078 /* Pipe isn't running, start first */ 3079 return ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3080 } 3081 3082 Static usbd_status 3083 ohci_device_bulk_start(struct usbd_xfer *xfer) 3084 { 3085 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3086 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3087 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3088 ohci_soft_td_t *last; 3089 ohci_soft_td_t *data, *tail, *tdp; 3090 ohci_soft_ed_t *sed; 3091 int len, isread, endpt; 3092 const bool polling = sc->sc_bus.ub_usepolling; 3093 3094 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3095 3096 if (sc->sc_dying) 3097 return USBD_IOERROR; 3098 3099 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3100 3101 len = xfer->ux_length; 3102 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3103 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3104 sed = opipe->sed; 3105 3106 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 3107 len, isread, xfer->ux_flags); 3108 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 3109 3110 if (!polling) 3111 mutex_enter(&sc->sc_lock); 3112 3113 /* 3114 * Use the pipe "tail" TD as our first and loan our first TD to the 3115 * next transfer 3116 */ 3117 data = opipe->tail.td; 3118 opipe->tail.td = ox->ox_stds[0]; 3119 ox->ox_stds[0] = data; 3120 data->held = &ox->ox_stds[0]; 3121 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3122 DPRINTFN(10, "xfer=%#jx new data=%#jx held at %#jx", 3123 (uintptr_t)ox, (uintptr_t)data, (uintptr_t)data->held, 0); 3124 3125 /* point at sentinel */ 3126 tail = opipe->tail.td; 3127 memset(&tail->td, 0, sizeof(tail->td)); 3128 tail->held = &opipe->tail.td; 3129 tail->nexttd = NULL; 3130 tail->xfer = NULL; 3131 DPRINTFN(10, "xfer=%#jx new tail=%#jx held at %#ux", 3132 (uintptr_t)ox, (uintptr_t)tail, (uintptr_t)tail->held, 0); 3133 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3134 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3135 xfer->ux_hcpriv = data; 3136 3137 DPRINTFN(8, "xfer %#jx data %#jx tail %#jx", (uintptr_t)xfer, 3138 (uintptr_t)ox->ox_stds[0], (uintptr_t)tail, 0); 3139 KASSERT(opipe->tail.td == tail); 3140 3141 /* We want interrupt at the end of the transfer. */ 3142 last->td.td_flags &= HTOO32(~OHCI_TD_DI_MASK); 3143 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3144 last->td.td_nexttd = HTOO32(tail->physaddr); 3145 last->nexttd = tail; 3146 last->flags |= OHCI_CALL_DONE; 3147 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3148 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3149 3150 DPRINTFN(4, "ed_flags=0x%08jx td_flags=0x%08jx " 3151 "td_cbp=0x%08jx td_be=0x%08jx", 3152 (int)O32TOH(sed->ed.ed_flags), 3153 (int)O32TOH(data->td.td_flags), 3154 (int)O32TOH(data->td.td_cbp), 3155 (int)O32TOH(data->td.td_be)); 3156 3157 #ifdef OHCI_DEBUG 3158 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3159 if (ohcidebug >= 5) { 3160 ohci_dump_ed(sc, sed); 3161 ohci_dump_tds(sc, data); 3162 } 3163 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3164 #endif 3165 3166 /* Insert ED in schedule */ 3167 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3168 KASSERT(tdp->xfer == xfer); 3169 } 3170 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3171 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3172 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3173 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3174 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3175 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3176 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3177 usbd_xfer_schedule_timeout(xfer); 3178 xfer->ux_status = USBD_IN_PROGRESS; 3179 if (!polling) 3180 mutex_exit(&sc->sc_lock); 3181 3182 return USBD_IN_PROGRESS; 3183 } 3184 3185 Static void 3186 ohci_device_bulk_abort(struct usbd_xfer *xfer) 3187 { 3188 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3189 3190 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3191 3192 KASSERT(mutex_owned(&sc->sc_lock)); 3193 3194 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3195 usbd_xfer_abort(xfer); 3196 } 3197 3198 /* 3199 * Close a device bulk pipe. 3200 */ 3201 Static void 3202 ohci_device_bulk_close(struct usbd_pipe *pipe) 3203 { 3204 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3205 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3206 3207 KASSERT(mutex_owned(&sc->sc_lock)); 3208 3209 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3210 3211 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3212 ohci_close_pipe(pipe, sc->sc_bulk_head); 3213 ohci_free_std_locked(sc, opipe->tail.td); 3214 } 3215 3216 /************************/ 3217 3218 Static int 3219 ohci_device_intr_init(struct usbd_xfer *xfer) 3220 { 3221 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3222 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3223 int len = xfer->ux_bufsize; 3224 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3225 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3226 int err; 3227 3228 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3229 3230 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3231 KASSERT(len != 0); 3232 3233 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 3234 len, isread, xfer->ux_flags); 3235 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 3236 3237 ox->ox_nstd = 0; 3238 3239 err = ohci_alloc_std_chain(sc, xfer, len, isread); 3240 if (err) { 3241 return err; 3242 } 3243 3244 return 0; 3245 } 3246 3247 Static void 3248 ohci_device_intr_fini(struct usbd_xfer *xfer) 3249 { 3250 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3251 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3252 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3253 3254 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3255 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 3256 3257 mutex_enter(&sc->sc_lock); 3258 for (size_t i = 0; i < ox->ox_nstd; i++) { 3259 ohci_soft_td_t *std = ox->ox_stds[i]; 3260 if (std != NULL) 3261 break; 3262 if (std != opipe->tail.td) 3263 ohci_free_std_locked(sc, std); 3264 } 3265 mutex_exit(&sc->sc_lock); 3266 3267 if (ox->ox_nstd) { 3268 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 3269 kmem_free(ox->ox_stds, sz); 3270 } 3271 } 3272 3273 Static usbd_status 3274 ohci_device_intr_transfer(struct usbd_xfer *xfer) 3275 { 3276 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3277 usbd_status err; 3278 3279 /* Insert last in queue. */ 3280 mutex_enter(&sc->sc_lock); 3281 err = usb_insert_transfer(xfer); 3282 mutex_exit(&sc->sc_lock); 3283 if (err) 3284 return err; 3285 3286 /* Pipe isn't running, start first */ 3287 return ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3288 } 3289 3290 Static usbd_status 3291 ohci_device_intr_start(struct usbd_xfer *xfer) 3292 { 3293 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3294 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3295 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3296 ohci_soft_ed_t *sed = opipe->sed; 3297 ohci_soft_td_t *data, *last, *tail; 3298 int len, isread, endpt; 3299 const bool polling = sc->sc_bus.ub_usepolling; 3300 3301 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3302 3303 if (sc->sc_dying) 3304 return USBD_IOERROR; 3305 3306 DPRINTFN(3, "xfer=%#jx len=%jd flags=%jd priv=%#jx", (uintptr_t)xfer, 3307 xfer->ux_length, xfer->ux_flags, (uintptr_t)xfer->ux_priv); 3308 3309 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3310 3311 len = xfer->ux_length; 3312 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3313 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3314 3315 if (!polling) 3316 mutex_enter(&sc->sc_lock); 3317 3318 /* 3319 * Use the pipe "tail" TD as our first and loan our first TD to the 3320 * next transfer. 3321 */ 3322 data = opipe->tail.td; 3323 opipe->tail.td = ox->ox_stds[0]; 3324 ox->ox_stds[0] = data; 3325 data->held = &ox->ox_stds[0]; 3326 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3327 DPRINTFN(10, "xfer=%#jx new data=%#jx held at %#jx", 3328 (uintptr_t)ox, (uintptr_t)data, (uintptr_t)data->held, 0); 3329 3330 /* point at sentinel */ 3331 tail = opipe->tail.td; 3332 memset(&tail->td, 0, sizeof(tail->td)); 3333 tail->held = &opipe->tail.td; 3334 tail->nexttd = NULL; 3335 tail->xfer = NULL; 3336 DPRINTFN(10, "xfer=%#jx new tail=%#jx held at %#jx", 3337 (uintptr_t)ox, (uintptr_t)tail, (uintptr_t)tail->held, 0); 3338 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3339 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3340 xfer->ux_hcpriv = data; 3341 3342 DPRINTFN(8, "data %#jx tail %#jx", (uintptr_t)ox->ox_stds[0], 3343 (uintptr_t)tail, 0, 0); 3344 KASSERT(opipe->tail.td == tail); 3345 3346 /* We want interrupt at the end of the transfer. */ 3347 last->td.td_flags &= HTOO32(~OHCI_TD_DI_MASK); 3348 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3349 3350 last->td.td_nexttd = HTOO32(tail->physaddr); 3351 last->nexttd = tail; 3352 last->flags |= OHCI_CALL_DONE; 3353 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3354 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3355 3356 #ifdef OHCI_DEBUG 3357 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3358 if (ohcidebug >= 5) { 3359 ohci_dump_ed(sc, sed); 3360 ohci_dump_tds(sc, data); 3361 } 3362 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3363 #endif 3364 3365 /* Insert ED in schedule */ 3366 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3367 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3368 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3369 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3370 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3371 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3372 3373 xfer->ux_status = USBD_IN_PROGRESS; 3374 if (!polling) 3375 mutex_exit(&sc->sc_lock); 3376 3377 return USBD_IN_PROGRESS; 3378 } 3379 3380 /* Abort a device interrupt request. */ 3381 Static void 3382 ohci_device_intr_abort(struct usbd_xfer *xfer) 3383 { 3384 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3385 3386 KASSERT(mutex_owned(&sc->sc_lock)); 3387 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3388 3389 usbd_xfer_abort(xfer); 3390 } 3391 3392 /* Close a device interrupt pipe. */ 3393 Static void 3394 ohci_device_intr_close(struct usbd_pipe *pipe) 3395 { 3396 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3397 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3398 int nslots = opipe->intr.nslots; 3399 int pos = opipe->intr.pos; 3400 int j; 3401 ohci_soft_ed_t *p, *sed = opipe->sed; 3402 3403 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3404 3405 KASSERT(mutex_owned(&sc->sc_lock)); 3406 3407 DPRINTFN(1, "pipe=%#jx nslots=%jd pos=%jd", (uintptr_t)pipe, nslots, 3408 pos, 0); 3409 usb_syncmem(&sed->dma, sed->offs, 3410 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3411 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3412 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3413 sizeof(sed->ed.ed_flags), 3414 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3415 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3416 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3417 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3418 3419 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3420 continue; 3421 KASSERT(p); 3422 p->next = sed->next; 3423 p->ed.ed_nexted = sed->ed.ed_nexted; 3424 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3425 sizeof(p->ed.ed_nexted), 3426 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3427 3428 for (j = 0; j < nslots; j++) 3429 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3430 3431 ohci_free_std_locked(sc, opipe->tail.td); 3432 ohci_free_sed_locked(sc, opipe->sed); 3433 } 3434 3435 Static usbd_status 3436 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3437 { 3438 int i, j, best; 3439 u_int npoll, slow, shigh, nslots; 3440 u_int bestbw, bw; 3441 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3442 3443 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3444 3445 DPRINTFN(2, "pipe=%#jx", (uintptr_t)opipe, 0, 0, 0); 3446 if (ival == 0) { 3447 printf("ohci_setintr: 0 interval\n"); 3448 return USBD_INVAL; 3449 } 3450 3451 npoll = OHCI_NO_INTRS; 3452 while (npoll > ival) 3453 npoll /= 2; 3454 DPRINTFN(2, "ival=%jd npoll=%jd", ival, npoll, 0, 0); 3455 3456 /* 3457 * We now know which level in the tree the ED must go into. 3458 * Figure out which slot has most bandwidth left over. 3459 * Slots to examine: 3460 * npoll 3461 * 1 0 3462 * 2 1 2 3463 * 4 3 4 5 6 3464 * 8 7 8 9 10 11 12 13 14 3465 * N (N-1) .. (N-1+N-1) 3466 */ 3467 slow = npoll-1; 3468 shigh = slow + npoll; 3469 nslots = OHCI_NO_INTRS / npoll; 3470 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3471 bw = 0; 3472 for (j = 0; j < nslots; j++) 3473 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3474 if (bw < bestbw) { 3475 best = i; 3476 bestbw = bw; 3477 } 3478 } 3479 DPRINTFN(2, "best=%jd(%jd..%jd) bestbw=%jd", best, slow, shigh, bestbw); 3480 3481 mutex_enter(&sc->sc_lock); 3482 hsed = sc->sc_eds[best]; 3483 sed->next = hsed->next; 3484 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3485 sizeof(hsed->ed.ed_flags), 3486 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3487 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3488 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3489 sizeof(sed->ed.ed_flags), 3490 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3491 hsed->next = sed; 3492 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3493 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3494 sizeof(hsed->ed.ed_flags), 3495 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3496 mutex_exit(&sc->sc_lock); 3497 3498 for (j = 0; j < nslots; j++) 3499 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3500 opipe->intr.nslots = nslots; 3501 opipe->intr.pos = best; 3502 3503 DPRINTFN(5, "returns %#jx", (uintptr_t)opipe, 0, 0, 0); 3504 return USBD_NORMAL_COMPLETION; 3505 } 3506 3507 /***********************/ 3508 3509 Static int 3510 ohci_device_isoc_init(struct usbd_xfer *xfer) 3511 { 3512 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3513 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3514 ohci_soft_itd_t *sitd; 3515 size_t i; 3516 int err; 3517 3518 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3519 3520 DPRINTFN(1, "xfer %#jx len %jd flags %jd", (uintptr_t)xfer, 3521 xfer->ux_length, xfer->ux_flags, 0); 3522 3523 const size_t nfsitd = howmany(xfer->ux_nframes, OHCI_ITD_NOFFSET); 3524 const size_t nbsitd = xfer->ux_bufsize / OHCI_PAGE_SIZE; 3525 const size_t nsitd = MAX(nfsitd, nbsitd) + 1; 3526 3527 ox->ox_sitds = kmem_zalloc(sizeof(ohci_soft_itd_t *) * nsitd, 3528 KM_SLEEP); 3529 ox->ox_nsitd = nsitd; 3530 3531 for (i = 0; i < nsitd; i++) { 3532 /* Allocate next ITD */ 3533 sitd = ohci_alloc_sitd(sc); 3534 if (sitd == NULL) { 3535 err = ENOMEM; 3536 goto fail; 3537 } 3538 ox->ox_sitds[i] = sitd; 3539 sitd->held = &ox->ox_sitds[i]; 3540 sitd->xfer = xfer; 3541 sitd->flags = 0; 3542 // DPRINTFN(10, "xfer=%#jx new tail=%#jx held at %#jx", 3543 // (uintptr_t)ox, (uintptr_t)tail, (uintptr_t)tail->held, 0); 3544 } 3545 3546 return 0; 3547 fail: 3548 for (; i > 0;) { 3549 ohci_free_sitd(sc, ox->ox_sitds[--i]); 3550 } 3551 return err; 3552 } 3553 3554 Static void 3555 ohci_device_isoc_fini(struct usbd_xfer *xfer) 3556 { 3557 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3558 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3559 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3560 3561 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3562 3563 mutex_enter(&sc->sc_lock); 3564 for (size_t i = 0; i < ox->ox_nsitd; i++) { 3565 if (ox->ox_sitds[i] != opipe->tail.itd) { 3566 ohci_free_sitd_locked(sc, ox->ox_sitds[i]); 3567 } 3568 } 3569 mutex_exit(&sc->sc_lock); 3570 3571 if (ox->ox_nsitd) { 3572 const size_t sz = sizeof(ohci_soft_itd_t *) * ox->ox_nsitd; 3573 kmem_free(ox->ox_sitds, sz); 3574 } 3575 } 3576 3577 3578 usbd_status 3579 ohci_device_isoc_transfer(struct usbd_xfer *xfer) 3580 { 3581 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3582 usbd_status __diagused err; 3583 3584 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3585 3586 DPRINTFN(5, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3587 3588 /* Put it on our queue, */ 3589 mutex_enter(&sc->sc_lock); 3590 err = usb_insert_transfer(xfer); 3591 mutex_exit(&sc->sc_lock); 3592 3593 KASSERT(err == USBD_NORMAL_COMPLETION); 3594 3595 /* insert into schedule, */ 3596 ohci_device_isoc_enter(xfer); 3597 3598 /* and start if the pipe wasn't running */ 3599 return USBD_IN_PROGRESS; 3600 } 3601 3602 void 3603 ohci_device_isoc_enter(struct usbd_xfer *xfer) 3604 { 3605 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3606 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3607 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3608 ohci_soft_ed_t *sed = opipe->sed; 3609 ohci_soft_itd_t *sitd, *nsitd, *tail; 3610 ohci_physaddr_t buf, offs, bp0, bp1; 3611 int i, ncur, nframes; 3612 size_t boff, frlen; 3613 3614 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3615 DPRINTFN(5, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3616 3617 mutex_enter(&sc->sc_lock); 3618 3619 if (sc->sc_dying) { 3620 mutex_exit(&sc->sc_lock); 3621 return; 3622 } 3623 3624 struct isoc *isoc = &opipe->isoc; 3625 3626 DPRINTFN(1, "used=%jd next=%jd xfer=%#jx nframes=%jd", 3627 isoc->inuse, isoc->next, (uintptr_t)xfer, xfer->ux_nframes); 3628 3629 int isread = 3630 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 3631 3632 if (xfer->ux_length) 3633 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3634 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3635 3636 if (isoc->next == -1) { 3637 /* Not in use yet, schedule it a few frames ahead. */ 3638 usb_syncmem(&sc->sc_hccadma, 3639 offsetof(struct ohci_hcca, hcca_frame_number), 3640 sizeof(sc->sc_hcca->hcca_frame_number), 3641 BUS_DMASYNC_POSTREAD); 3642 isoc->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3643 DPRINTFN(2,"start next=%jd", isoc->next, 0, 0, 0); 3644 } 3645 3646 sitd = opipe->tail.itd; 3647 opipe->tail.itd = ox->ox_sitds[0]; 3648 ox->ox_sitds[0] = sitd; 3649 sitd->held = &ox->ox_sitds[0]; 3650 3651 boff = 0; 3652 buf = DMAADDR(&xfer->ux_dmabuf, 0); 3653 bp0 = bp1 = OHCI_PAGE(buf); 3654 offs = OHCI_PAGE_OFFSET(buf); 3655 3656 ohci_physaddr_t end = bp0; /* XXX stupid GCC */ 3657 3658 nframes = xfer->ux_nframes; 3659 xfer->ux_hcpriv = sitd; 3660 size_t j = 1; 3661 for (i = ncur = 0; i < nframes; i++, ncur++) { 3662 frlen = xfer->ux_frlengths[i]; 3663 3664 DPRINTFN(1, "frame=%jd ux_frlengths[%jd]=%jd", i, i, 3665 xfer->ux_frlengths[i], 0); 3666 /* 3667 * XXXNH: The loop assumes this is never true, because 3668 * incrementing 'i' assumes all the ux_frlengths[i] is covered. 3669 */ 3670 if (frlen > 2 * OHCI_PAGE_SIZE - offs) 3671 frlen = 2 * OHCI_PAGE_SIZE - offs; 3672 3673 boff += frlen; 3674 buf = DMAADDR(&xfer->ux_dmabuf, boff); 3675 ohci_physaddr_t noffs = OHCI_PAGE_OFFSET(buf); 3676 3677 ohci_physaddr_t nend = DMAADDR(&xfer->ux_dmabuf, boff - 1); 3678 const ohci_physaddr_t nep = OHCI_PAGE(nend); 3679 3680 /* Note the first page crossing in bp1 */ 3681 if (bp0 == bp1 && bp1 != nep) 3682 bp1 = nep; 3683 3684 DPRINTFN(1, "ncur=%jd bp0=%#jx bp1=%#jx nend=%#jx", 3685 ncur, bp0, bp1, nend); 3686 3687 /* all offsets used or too many page crossings */ 3688 if (ncur == OHCI_ITD_NOFFSET || (bp0 != bp1 && bp1 != nep)) { 3689 /* Allocate next ITD */ 3690 nsitd = ox->ox_sitds[j++]; 3691 KASSERT(nsitd != NULL); 3692 KASSERT(j < ox->ox_nsitd); 3693 3694 /* Fill current ITD */ 3695 sitd->itd.itd_flags = HTOO32( 3696 OHCI_ITD_SET_CC(OHCI_ITD_NOCC) | 3697 OHCI_ITD_SET_SF(isoc->next) | 3698 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3699 OHCI_ITD_SET_FC(ncur) 3700 ); 3701 sitd->itd.itd_bp0 = HTOO32(bp0); 3702 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3703 sitd->itd.itd_be = HTOO32(end); 3704 sitd->nextitd = nsitd; 3705 sitd->xfer = xfer; 3706 sitd->flags = 0; 3707 #ifdef DIAGNOSTIC 3708 sitd->isdone = false; 3709 #endif 3710 ohci_hash_add_itd(sc, sitd); 3711 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3712 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3713 3714 sitd = nsitd; 3715 isoc->next = isoc->next + ncur; 3716 bp0 = bp1 = OHCI_PAGE(buf); 3717 ncur = 0; 3718 } 3719 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3720 end = nend; 3721 offs = noffs; 3722 } 3723 KASSERT(j <= ox->ox_nsitd); 3724 3725 /* point at sentinel */ 3726 tail = opipe->tail.itd; 3727 memset(&tail->itd, 0, sizeof(tail->itd)); 3728 tail->held = &opipe->tail.itd; 3729 tail->nextitd = NULL; 3730 tail->xfer = NULL; 3731 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->itd), 3732 BUS_DMASYNC_PREWRITE); 3733 3734 /* Fixup last used ITD */ 3735 sitd->itd.itd_flags = HTOO32( 3736 OHCI_ITD_SET_CC(OHCI_ITD_NOCC) | 3737 OHCI_ITD_SET_SF(isoc->next) | 3738 OHCI_ITD_SET_DI(0) | 3739 OHCI_ITD_SET_FC(ncur) 3740 ); 3741 sitd->itd.itd_bp0 = HTOO32(bp0); 3742 sitd->itd.itd_nextitd = HTOO32(tail->physaddr); 3743 sitd->itd.itd_be = HTOO32(end); 3744 sitd->nextitd = tail; 3745 sitd->xfer = xfer; 3746 sitd->flags = OHCI_CALL_DONE; 3747 #ifdef DIAGNOSTIC 3748 sitd->isdone = false; 3749 #endif 3750 ohci_hash_add_itd(sc, sitd); 3751 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3752 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3753 3754 isoc->next = isoc->next + ncur; 3755 isoc->inuse += nframes; 3756 3757 /* XXX pretend we did it all */ 3758 xfer->ux_actlen = offs; 3759 xfer->ux_status = USBD_IN_PROGRESS; 3760 3761 #ifdef OHCI_DEBUG 3762 if (ohcidebug >= 5) { 3763 usb_syncmem(&sc->sc_hccadma, 3764 offsetof(struct ohci_hcca, hcca_frame_number), 3765 sizeof(sc->sc_hcca->hcca_frame_number), 3766 BUS_DMASYNC_POSTREAD); 3767 DPRINTF("frame=%jd", O32TOH(sc->sc_hcca->hcca_frame_number), 3768 0, 0, 0); 3769 ohci_dump_itds(sc, xfer->ux_hcpriv); 3770 ohci_dump_ed(sc, sed); 3771 } 3772 #endif 3773 3774 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3775 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3776 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3777 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3778 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3779 sizeof(sed->ed.ed_flags), 3780 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3781 mutex_exit(&sc->sc_lock); 3782 } 3783 3784 void 3785 ohci_device_isoc_abort(struct usbd_xfer *xfer) 3786 { 3787 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3788 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3789 ohci_soft_ed_t *sed; 3790 ohci_soft_itd_t *sitd; 3791 3792 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3793 DPRINTFN(1, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3794 3795 KASSERT(mutex_owned(&sc->sc_lock)); 3796 3797 /* Transfer is already done. */ 3798 if (xfer->ux_status != USBD_NOT_STARTED && 3799 xfer->ux_status != USBD_IN_PROGRESS) { 3800 printf("ohci_device_isoc_abort: early return\n"); 3801 goto done; 3802 } 3803 3804 /* Give xfer the requested abort code. */ 3805 xfer->ux_status = USBD_CANCELLED; 3806 3807 sed = opipe->sed; 3808 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3809 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3810 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3811 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3812 sizeof(sed->ed.ed_flags), 3813 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3814 3815 sitd = xfer->ux_hcpriv; 3816 KASSERT(sitd); 3817 3818 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3819 3820 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3821 ohci_hash_rem_itd(sc, sitd); 3822 #ifdef DIAGNOSTIC 3823 DPRINTFN(1, "abort sets done sitd=%#jx", (uintptr_t)sitd, 3824 0, 0, 0); 3825 sitd->isdone = true; 3826 #endif 3827 } 3828 3829 /* Run callback. */ 3830 usb_transfer_complete(xfer); 3831 3832 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3833 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3834 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3835 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3836 3837 done: 3838 KASSERT(mutex_owned(&sc->sc_lock)); 3839 } 3840 3841 void 3842 ohci_device_isoc_done(struct usbd_xfer *xfer) 3843 { 3844 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3845 DPRINTFN(1, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3846 3847 int isread = 3848 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 3849 3850 DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 3851 0, 0); 3852 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3853 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3854 } 3855 3856 usbd_status 3857 ohci_setup_isoc(struct usbd_pipe *pipe) 3858 { 3859 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3860 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3861 struct isoc *isoc = &opipe->isoc; 3862 3863 isoc->next = -1; 3864 isoc->inuse = 0; 3865 3866 mutex_enter(&sc->sc_lock); 3867 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3868 mutex_exit(&sc->sc_lock); 3869 3870 return USBD_NORMAL_COMPLETION; 3871 } 3872 3873 void 3874 ohci_device_isoc_close(struct usbd_pipe *pipe) 3875 { 3876 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3877 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3878 3879 KASSERT(mutex_owned(&sc->sc_lock)); 3880 3881 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3882 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3883 ohci_close_pipe(pipe, sc->sc_isoc_head); 3884 #ifdef DIAGNOSTIC 3885 opipe->tail.itd->isdone = true; 3886 #endif 3887 ohci_free_sitd_locked(sc, opipe->tail.itd); 3888 } 3889
Indexes created Tue Sep 23 02:09:52 GMT 2025