ohci.c revision 1.316
1 /* $NetBSD: ohci.c,v 1.316 2021/06/15 23:39:43 riastradh Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012, 2016, 2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca), 10 * Matthew R. Green (mrg (at) eterna.com.au), and Nick Hudson. 11 * 12 * This code is derived from software contributed to The NetBSD Foundation 13 * by Charles M. Hannum. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * USB Open Host Controller driver. 39 * 40 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 41 * USB spec: http://www.usb.org/developers/docs/ 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.316 2021/06/15 23:39:43 riastradh Exp $"); 46 47 #ifdef _KERNEL_OPT 48 #include "opt_usb.h" 49 #endif 50 51 #include <sys/param.h> 52 53 #include <sys/cpu.h> 54 #include <sys/device.h> 55 #include <sys/kernel.h> 56 #include <sys/kmem.h> 57 #include <sys/proc.h> 58 #include <sys/queue.h> 59 #include <sys/select.h> 60 #include <sys/sysctl.h> 61 #include <sys/systm.h> 62 63 #include <machine/endian.h> 64 65 #include <dev/usb/usb.h> 66 #include <dev/usb/usbdi.h> 67 #include <dev/usb/usbdivar.h> 68 #include <dev/usb/usb_mem.h> 69 #include <dev/usb/usb_quirks.h> 70 71 #include <dev/usb/ohcireg.h> 72 #include <dev/usb/ohcivar.h> 73 #include <dev/usb/usbroothub.h> 74 #include <dev/usb/usbhist.h> 75 76 #ifdef USB_DEBUG 77 #ifndef OHCI_DEBUG 78 #define ohcidebug 0 79 #else 80 static int ohcidebug = 10; 81 82 SYSCTL_SETUP(sysctl_hw_ohci_setup, "sysctl hw.ohci setup") 83 { 84 int err; 85 const struct sysctlnode *rnode; 86 const struct sysctlnode *cnode; 87 88 err = sysctl_createv(clog, 0, NULL, &rnode, 89 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ohci", 90 SYSCTL_DESCR("ohci global controls"), 91 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 92 93 if (err) 94 goto fail; 95 96 /* control debugging printfs */ 97 err = sysctl_createv(clog, 0, &rnode, &cnode, 98 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 99 "debug", SYSCTL_DESCR("Enable debugging output"), 100 NULL, 0, &ohcidebug, sizeof(ohcidebug), CTL_CREATE, CTL_EOL); 101 if (err) 102 goto fail; 103 104 return; 105 fail: 106 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 107 } 108 109 #endif /* OHCI_DEBUG */ 110 #endif /* USB_DEBUG */ 111 112 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ohcidebug,FMT,A,B,C,D) 113 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ohcidebug,N,FMT,A,B,C,D) 114 #define OHCIHIST_FUNC() USBHIST_FUNC() 115 #define OHCIHIST_CALLED(name) USBHIST_CALLED(ohcidebug) 116 117 #if BYTE_ORDER == BIG_ENDIAN 118 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 119 #else 120 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 121 #endif 122 123 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 124 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 125 #define HTOO16(val) O16TOH(val) 126 #define HTOO32(val) O32TOH(val) 127 128 struct ohci_pipe; 129 130 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 131 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 132 133 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 134 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 135 Static void ohci_free_std_locked(ohci_softc_t *, ohci_soft_td_t *); 136 137 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 138 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 139 Static void ohci_free_sitd_locked(ohci_softc_t *, 140 ohci_soft_itd_t *); 141 142 Static int ohci_alloc_std_chain(ohci_softc_t *, struct usbd_xfer *, 143 int, int); 144 Static void ohci_free_stds(ohci_softc_t *, struct ohci_xfer *); 145 146 Static void ohci_reset_std_chain(ohci_softc_t *, struct usbd_xfer *, 147 int, int, ohci_soft_td_t *, ohci_soft_td_t **); 148 149 Static usbd_status ohci_open(struct usbd_pipe *); 150 Static void ohci_poll(struct usbd_bus *); 151 Static void ohci_softintr(void *); 152 Static void ohci_rhsc(ohci_softc_t *, struct usbd_xfer *); 153 Static void ohci_rhsc_softint(void *); 154 155 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 156 ohci_soft_ed_t *); 157 158 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 159 ohci_soft_ed_t *); 160 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 161 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 162 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 163 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 164 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 165 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 166 167 Static usbd_status ohci_setup_isoc(struct usbd_pipe *); 168 Static void ohci_device_isoc_enter(struct usbd_xfer *); 169 170 Static struct usbd_xfer * 171 ohci_allocx(struct usbd_bus *, unsigned int); 172 Static void ohci_freex(struct usbd_bus *, struct usbd_xfer *); 173 Static bool ohci_dying(struct usbd_bus *); 174 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 175 Static int ohci_roothub_ctrl(struct usbd_bus *, 176 usb_device_request_t *, void *, int); 177 178 Static usbd_status ohci_root_intr_transfer(struct usbd_xfer *); 179 Static usbd_status ohci_root_intr_start(struct usbd_xfer *); 180 Static void ohci_root_intr_abort(struct usbd_xfer *); 181 Static void ohci_root_intr_close(struct usbd_pipe *); 182 Static void ohci_root_intr_done(struct usbd_xfer *); 183 184 Static int ohci_device_ctrl_init(struct usbd_xfer *); 185 Static void ohci_device_ctrl_fini(struct usbd_xfer *); 186 Static usbd_status ohci_device_ctrl_transfer(struct usbd_xfer *); 187 Static usbd_status ohci_device_ctrl_start(struct usbd_xfer *); 188 Static void ohci_device_ctrl_abort(struct usbd_xfer *); 189 Static void ohci_device_ctrl_close(struct usbd_pipe *); 190 Static void ohci_device_ctrl_done(struct usbd_xfer *); 191 192 Static int ohci_device_bulk_init(struct usbd_xfer *); 193 Static void ohci_device_bulk_fini(struct usbd_xfer *); 194 Static usbd_status ohci_device_bulk_transfer(struct usbd_xfer *); 195 Static usbd_status ohci_device_bulk_start(struct usbd_xfer *); 196 Static void ohci_device_bulk_abort(struct usbd_xfer *); 197 Static void ohci_device_bulk_close(struct usbd_pipe *); 198 Static void ohci_device_bulk_done(struct usbd_xfer *); 199 200 Static int ohci_device_intr_init(struct usbd_xfer *); 201 Static void ohci_device_intr_fini(struct usbd_xfer *); 202 Static usbd_status ohci_device_intr_transfer(struct usbd_xfer *); 203 Static usbd_status ohci_device_intr_start(struct usbd_xfer *); 204 Static void ohci_device_intr_abort(struct usbd_xfer *); 205 Static void ohci_device_intr_close(struct usbd_pipe *); 206 Static void ohci_device_intr_done(struct usbd_xfer *); 207 208 Static int ohci_device_isoc_init(struct usbd_xfer *); 209 Static void ohci_device_isoc_fini(struct usbd_xfer *); 210 Static usbd_status ohci_device_isoc_transfer(struct usbd_xfer *); 211 Static void ohci_device_isoc_abort(struct usbd_xfer *); 212 Static void ohci_device_isoc_close(struct usbd_pipe *); 213 Static void ohci_device_isoc_done(struct usbd_xfer *); 214 215 Static usbd_status ohci_device_setintr(ohci_softc_t *, 216 struct ohci_pipe *, int); 217 218 Static void ohci_rhsc_enable(void *); 219 220 Static void ohci_close_pipe(struct usbd_pipe *, ohci_soft_ed_t *); 221 Static void ohci_abortx(struct usbd_xfer *); 222 223 Static void ohci_device_clear_toggle(struct usbd_pipe *); 224 Static void ohci_noop(struct usbd_pipe *); 225 226 #ifdef OHCI_DEBUG 227 Static void ohci_dumpregs(ohci_softc_t *); 228 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 229 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 230 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 231 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 232 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 233 #endif 234 235 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 236 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 237 #define OWRITE1(sc, r, x) \ 238 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 239 #define OWRITE2(sc, r, x) \ 240 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 241 #define OWRITE4(sc, r, x) \ 242 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 243 244 static __inline uint32_t 245 OREAD4(ohci_softc_t *sc, bus_size_t r) 246 { 247 248 OBARR(sc); 249 return bus_space_read_4(sc->iot, sc->ioh, r); 250 } 251 252 /* Reverse the bits in a value 0 .. 31 */ 253 Static uint8_t revbits[OHCI_NO_INTRS] = 254 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 255 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 256 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 257 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 258 259 struct ohci_pipe { 260 struct usbd_pipe pipe; 261 ohci_soft_ed_t *sed; 262 union { 263 ohci_soft_td_t *td; 264 ohci_soft_itd_t *itd; 265 } tail; 266 /* Info needed for different pipe kinds. */ 267 union { 268 /* Control pipe */ 269 struct { 270 usb_dma_t reqdma; 271 } ctrl; 272 /* Interrupt pipe */ 273 struct { 274 int nslots; 275 int pos; 276 } intr; 277 /* Isochronous pipe */ 278 struct isoc { 279 int next, inuse; 280 } isoc; 281 }; 282 }; 283 284 Static const struct usbd_bus_methods ohci_bus_methods = { 285 .ubm_open = ohci_open, 286 .ubm_softint = ohci_softintr, 287 .ubm_dopoll = ohci_poll, 288 .ubm_allocx = ohci_allocx, 289 .ubm_freex = ohci_freex, 290 .ubm_abortx = ohci_abortx, 291 .ubm_dying = ohci_dying, 292 .ubm_getlock = ohci_get_lock, 293 .ubm_rhctrl = ohci_roothub_ctrl, 294 }; 295 296 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 297 .upm_transfer = ohci_root_intr_transfer, 298 .upm_start = ohci_root_intr_start, 299 .upm_abort = ohci_root_intr_abort, 300 .upm_close = ohci_root_intr_close, 301 .upm_cleartoggle = ohci_noop, 302 .upm_done = ohci_root_intr_done, 303 }; 304 305 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 306 .upm_init = ohci_device_ctrl_init, 307 .upm_fini = ohci_device_ctrl_fini, 308 .upm_transfer = ohci_device_ctrl_transfer, 309 .upm_start = ohci_device_ctrl_start, 310 .upm_abort = ohci_device_ctrl_abort, 311 .upm_close = ohci_device_ctrl_close, 312 .upm_cleartoggle = ohci_noop, 313 .upm_done = ohci_device_ctrl_done, 314 }; 315 316 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 317 .upm_init = ohci_device_intr_init, 318 .upm_fini = ohci_device_intr_fini, 319 .upm_transfer = ohci_device_intr_transfer, 320 .upm_start = ohci_device_intr_start, 321 .upm_abort = ohci_device_intr_abort, 322 .upm_close = ohci_device_intr_close, 323 .upm_cleartoggle = ohci_device_clear_toggle, 324 .upm_done = ohci_device_intr_done, 325 }; 326 327 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 328 .upm_init = ohci_device_bulk_init, 329 .upm_fini = ohci_device_bulk_fini, 330 .upm_transfer = ohci_device_bulk_transfer, 331 .upm_start = ohci_device_bulk_start, 332 .upm_abort = ohci_device_bulk_abort, 333 .upm_close = ohci_device_bulk_close, 334 .upm_cleartoggle = ohci_device_clear_toggle, 335 .upm_done = ohci_device_bulk_done, 336 }; 337 338 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 339 .upm_init = ohci_device_isoc_init, 340 .upm_fini = ohci_device_isoc_fini, 341 .upm_transfer = ohci_device_isoc_transfer, 342 .upm_abort = ohci_device_isoc_abort, 343 .upm_close = ohci_device_isoc_close, 344 .upm_cleartoggle = ohci_noop, 345 .upm_done = ohci_device_isoc_done, 346 }; 347 348 int 349 ohci_activate(device_t self, enum devact act) 350 { 351 struct ohci_softc *sc = device_private(self); 352 353 switch (act) { 354 case DVACT_DEACTIVATE: 355 sc->sc_dying = 1; 356 return 0; 357 default: 358 return EOPNOTSUPP; 359 } 360 } 361 362 void 363 ohci_childdet(device_t self, device_t child) 364 { 365 struct ohci_softc *sc = device_private(self); 366 367 KASSERT(sc->sc_child == child); 368 sc->sc_child = NULL; 369 } 370 371 int 372 ohci_detach(struct ohci_softc *sc, int flags) 373 { 374 int rv = 0; 375 376 if (sc->sc_child != NULL) 377 rv = config_detach(sc->sc_child, flags); 378 379 if (rv != 0) 380 return rv; 381 382 softint_disestablish(sc->sc_rhsc_si); 383 384 callout_halt(&sc->sc_tmo_rhsc, NULL); 385 callout_destroy(&sc->sc_tmo_rhsc); 386 387 mutex_destroy(&sc->sc_lock); 388 mutex_destroy(&sc->sc_intr_lock); 389 390 if (sc->sc_hcca != NULL) 391 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 392 pool_cache_destroy(sc->sc_xferpool); 393 cv_destroy(&sc->sc_abort_cv); 394 395 return rv; 396 } 397 398 ohci_soft_ed_t * 399 ohci_alloc_sed(ohci_softc_t *sc) 400 { 401 ohci_soft_ed_t *sed; 402 int i, offs; 403 usb_dma_t dma; 404 405 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 406 407 mutex_enter(&sc->sc_lock); 408 if (sc->sc_freeeds == NULL) { 409 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 410 mutex_exit(&sc->sc_lock); 411 412 int err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 413 OHCI_ED_ALIGN, 0 /*!USBMALLOC_COHERENT*/, &dma); 414 if (err) 415 return NULL; 416 417 mutex_enter(&sc->sc_lock); 418 for (i = 0; i < OHCI_SED_CHUNK; i++) { 419 offs = i * OHCI_SED_SIZE; 420 sed = KERNADDR(&dma, offs); 421 sed->physaddr = DMAADDR(&dma, offs); 422 sed->dma = dma; 423 sed->offs = offs; 424 sed->next = sc->sc_freeeds; 425 sc->sc_freeeds = sed; 426 } 427 } 428 sed = sc->sc_freeeds; 429 sc->sc_freeeds = sed->next; 430 mutex_exit(&sc->sc_lock); 431 432 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 433 sed->next = 0; 434 return sed; 435 } 436 437 static inline void 438 ohci_free_sed_locked(ohci_softc_t *sc, ohci_soft_ed_t *sed) 439 { 440 441 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 442 443 sed->next = sc->sc_freeeds; 444 sc->sc_freeeds = sed; 445 } 446 447 void 448 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 449 { 450 451 mutex_enter(&sc->sc_lock); 452 ohci_free_sed_locked(sc, sed); 453 mutex_exit(&sc->sc_lock); 454 } 455 456 ohci_soft_td_t * 457 ohci_alloc_std(ohci_softc_t *sc) 458 { 459 ohci_soft_td_t *std; 460 int i, offs; 461 usb_dma_t dma; 462 463 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 464 465 mutex_enter(&sc->sc_lock); 466 if (sc->sc_freetds == NULL) { 467 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 468 mutex_exit(&sc->sc_lock); 469 470 int err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 471 OHCI_TD_ALIGN, USBMALLOC_COHERENT, &dma); 472 if (err) 473 return NULL; 474 475 mutex_enter(&sc->sc_lock); 476 for (i = 0; i < OHCI_STD_CHUNK; i++) { 477 offs = i * OHCI_STD_SIZE; 478 std = KERNADDR(&dma, offs); 479 std->physaddr = DMAADDR(&dma, offs); 480 std->dma = dma; 481 std->offs = offs; 482 std->nexttd = sc->sc_freetds; 483 sc->sc_freetds = std; 484 } 485 } 486 487 std = sc->sc_freetds; 488 sc->sc_freetds = std->nexttd; 489 mutex_exit(&sc->sc_lock); 490 491 memset(&std->td, 0, sizeof(ohci_td_t)); 492 std->nexttd = NULL; 493 std->xfer = NULL; 494 std->held = NULL; 495 496 return std; 497 } 498 499 void 500 ohci_free_std_locked(ohci_softc_t *sc, ohci_soft_td_t *std) 501 { 502 503 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 504 505 std->nexttd = sc->sc_freetds; 506 sc->sc_freetds = std; 507 } 508 509 void 510 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 511 { 512 513 mutex_enter(&sc->sc_lock); 514 ohci_free_std_locked(sc, std); 515 mutex_exit(&sc->sc_lock); 516 } 517 518 Static int 519 ohci_alloc_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, int length, int rd) 520 { 521 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 522 uint16_t flags = xfer->ux_flags; 523 524 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 525 526 DPRINTFN(8, "addr=%jd endpt=%jd len=%jd speed=%jd", 527 xfer->ux_pipe->up_dev->ud_addr, 528 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 529 length, xfer->ux_pipe->up_dev->ud_speed); 530 531 ASSERT_SLEEPABLE(); 532 KASSERT(length != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 533 534 size_t nstd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 535 nstd += howmany(length, OHCI_PAGE_SIZE); 536 ox->ox_stds = kmem_zalloc(sizeof(ohci_soft_td_t *) * nstd, 537 KM_SLEEP); 538 ox->ox_nstd = nstd; 539 540 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, nstd, 0, 0); 541 542 for (size_t j = 0; j < ox->ox_nstd; j++) { 543 ohci_soft_td_t *cur = ohci_alloc_std(sc); 544 if (cur == NULL) 545 goto nomem; 546 547 ox->ox_stds[j] = cur; 548 cur->held = &ox->ox_stds[j]; 549 cur->xfer = xfer; 550 cur->flags = 0; 551 DPRINTFN(10, "xfer=%#jx new std=%#jx held at %#jx", (uintptr_t)ox, 552 (uintptr_t)cur, (uintptr_t)cur->held, 0); 553 } 554 555 return 0; 556 557 nomem: 558 ohci_free_stds(sc, ox); 559 kmem_free(ox->ox_stds, sizeof(ohci_soft_td_t *) * nstd); 560 561 return ENOMEM; 562 } 563 564 Static void 565 ohci_free_stds(ohci_softc_t *sc, struct ohci_xfer *ox) 566 { 567 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 568 DPRINTF("ox=%#jx", (uintptr_t)ox, 0, 0, 0); 569 570 mutex_enter(&sc->sc_lock); 571 for (size_t i = 0; i < ox->ox_nstd; i++) { 572 ohci_soft_td_t *std = ox->ox_stds[i]; 573 if (std == NULL) 574 break; 575 ohci_free_std_locked(sc, std); 576 } 577 mutex_exit(&sc->sc_lock); 578 } 579 580 void 581 ohci_reset_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, 582 int alen, int rd, ohci_soft_td_t *sp, ohci_soft_td_t **ep) 583 { 584 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 585 ohci_soft_td_t *next, *cur; 586 int len, curlen; 587 usb_dma_t *dma = &xfer->ux_dmabuf; 588 uint16_t flags = xfer->ux_flags; 589 590 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 591 DPRINTF("start len=%jd", alen, 0, 0, 0); 592 593 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 594 595 DPRINTFN(8, "addr=%jd endpt=%jd len=%jd speed=%jd", 596 xfer->ux_pipe->up_dev->ud_addr, 597 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 598 alen, xfer->ux_pipe->up_dev->ud_speed); 599 600 KASSERT(sp); 601 602 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 603 604 /* 605 * Assign next for the len == 0 case where we don't go through the 606 * main loop. 607 */ 608 len = alen; 609 cur = next = sp; 610 611 usb_syncmem(dma, 0, len, 612 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 613 const uint32_t tdflags = HTOO32( 614 OHCI_TD_SET_DP(rd ? OHCI_TD_DP_IN : OHCI_TD_DP_OUT) | 615 OHCI_TD_SET_CC(OHCI_TD_NOCC) | 616 OHCI_TD_SET_TOGGLE(OHCI_TD_TOGGLE_CARRY) | 617 OHCI_TD_SET_DI(OHCI_TD_NOINTR) 618 ); 619 620 size_t curoffs = 0; 621 for (size_t j = 1; len != 0;) { 622 if (j == ox->ox_nstd) 623 next = NULL; 624 else 625 next = ox->ox_stds[j++]; 626 KASSERT(next != cur); 627 628 curlen = len; 629 /* 630 * The OHCI hardware can handle at most one page crossing per 631 * TD. That is, 2 * OHCI_PAGE_SIZE as a maximum. Limit the 632 * length in this TD accordingly. 633 */ 634 const ohci_physaddr_t sdataphys = DMAADDR(dma, curoffs); 635 636 int maxlen = (2 * OHCI_PAGE_SIZE) - OHCI_PAGE_OFFSET(sdataphys); 637 if (curlen > maxlen) { 638 curlen = maxlen; 639 640 /* 641 * the length must be a multiple of 642 * the max size 643 */ 644 curlen -= curlen % mps; 645 } 646 647 const int edataoffs = curoffs + curlen - 1; 648 const ohci_physaddr_t edataphys = DMAADDR(dma, edataoffs); 649 650 KASSERT(curlen != 0); 651 DPRINTFN(4, "sdataphys=0x%08jx edataphys=0x%08jx " 652 "len=%jd curlen=%jd", sdataphys, edataphys, len, curlen); 653 654 cur->td.td_flags = tdflags; 655 cur->td.td_cbp = HTOO32(sdataphys); 656 cur->td.td_be = HTOO32(edataphys); 657 cur->td.td_nexttd = (next != NULL) ? HTOO32(next->physaddr) : 0; 658 cur->nexttd = next; 659 cur->len = curlen; 660 cur->flags = OHCI_ADD_LEN; 661 cur->xfer = xfer; 662 ohci_hash_add_td(sc, cur); 663 664 curoffs += curlen; 665 len -= curlen; 666 667 if (len != 0) { 668 KASSERT(next != NULL); 669 DPRINTFN(10, "extend chain", 0, 0, 0, 0); 670 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 671 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 672 673 cur = next; 674 } 675 } 676 cur->td.td_flags |= 677 HTOO32(xfer->ux_flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0); 678 679 if (!rd && 680 (flags & USBD_FORCE_SHORT_XFER) && 681 alen % mps == 0) { 682 /* We're adding a ZLP so sync the previous TD */ 683 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 684 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 685 686 /* Force a 0 length transfer at the end. */ 687 688 KASSERT(next != NULL); 689 cur = next; 690 691 cur->td.td_flags = tdflags; 692 cur->td.td_cbp = 0; /* indicate 0 length packet */ 693 cur->td.td_nexttd = 0; 694 cur->td.td_be = ~0; 695 cur->nexttd = NULL; 696 cur->len = 0; 697 cur->flags = 0; 698 cur->xfer = xfer; 699 ohci_hash_add_td(sc, cur); 700 701 DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0); 702 } 703 704 /* Last TD gets usb_syncmem'ed by caller */ 705 *ep = cur; 706 } 707 708 ohci_soft_itd_t * 709 ohci_alloc_sitd(ohci_softc_t *sc) 710 { 711 ohci_soft_itd_t *sitd; 712 int i, offs; 713 usb_dma_t dma; 714 715 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 716 717 mutex_enter(&sc->sc_lock); 718 if (sc->sc_freeitds == NULL) { 719 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 720 mutex_exit(&sc->sc_lock); 721 722 int err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 723 OHCI_ITD_ALIGN, USBMALLOC_COHERENT, &dma); 724 if (err) 725 return NULL; 726 mutex_enter(&sc->sc_lock); 727 for (i = 0; i < OHCI_SITD_CHUNK; i++) { 728 offs = i * OHCI_SITD_SIZE; 729 sitd = KERNADDR(&dma, offs); 730 sitd->physaddr = DMAADDR(&dma, offs); 731 sitd->dma = dma; 732 sitd->offs = offs; 733 sitd->nextitd = sc->sc_freeitds; 734 sc->sc_freeitds = sitd; 735 } 736 } 737 738 sitd = sc->sc_freeitds; 739 sc->sc_freeitds = sitd->nextitd; 740 mutex_exit(&sc->sc_lock); 741 742 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 743 sitd->nextitd = NULL; 744 sitd->xfer = NULL; 745 746 #ifdef DIAGNOSTIC 747 sitd->isdone = true; 748 #endif 749 750 return sitd; 751 } 752 753 Static void 754 ohci_free_sitd_locked(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 755 { 756 757 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 758 DPRINTFN(10, "sitd=%#jx", (uintptr_t)sitd, 0, 0, 0); 759 760 KASSERT(sitd->isdone); 761 #ifdef DIAGNOSTIC 762 /* Warn double free */ 763 sitd->isdone = false; 764 #endif 765 766 sitd->nextitd = sc->sc_freeitds; 767 sc->sc_freeitds = sitd; 768 } 769 770 void 771 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 772 { 773 774 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 775 776 mutex_enter(&sc->sc_lock); 777 ohci_free_sitd_locked(sc, sitd); 778 mutex_exit(&sc->sc_lock); 779 } 780 781 int 782 ohci_init(ohci_softc_t *sc) 783 { 784 ohci_soft_ed_t *sed, *psed; 785 usbd_status err; 786 int i; 787 uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */; 788 789 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 790 791 aprint_normal_dev(sc->sc_dev, ""); 792 793 sc->sc_hcca = NULL; 794 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 795 796 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 797 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 798 799 sc->sc_rhsc_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 800 ohci_rhsc_softint, sc); 801 802 for (i = 0; i < OHCI_HASH_SIZE; i++) 803 LIST_INIT(&sc->sc_hash_tds[i]); 804 for (i = 0; i < OHCI_HASH_SIZE; i++) 805 LIST_INIT(&sc->sc_hash_itds[i]); 806 807 TAILQ_INIT(&sc->sc_abortingxfers); 808 cv_init(&sc->sc_abort_cv, "ohciabt"); 809 810 sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0, 811 "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL); 812 813 rev = OREAD4(sc, OHCI_REVISION); 814 aprint_normal("OHCI version %" __PRIuBITS ".%" __PRIuBITS "%s\n", 815 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 816 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 817 818 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 819 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 820 sc->sc_bus.ub_revision = USBREV_UNKNOWN; 821 return -1; 822 } 823 sc->sc_bus.ub_revision = USBREV_1_0; 824 sc->sc_bus.ub_usedma = true; 825 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 826 827 /* XXX determine alignment by R/W */ 828 /* Allocate the HCCA area. */ 829 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, OHCI_HCCA_ALIGN, 830 USBMALLOC_COHERENT, &sc->sc_hccadma); 831 if (err) { 832 sc->sc_hcca = NULL; 833 return err; 834 } 835 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 836 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 837 838 sc->sc_eintrs = OHCI_NORMAL_INTRS; 839 840 /* Allocate dummy ED that starts the control list. */ 841 sc->sc_ctrl_head = ohci_alloc_sed(sc); 842 if (sc->sc_ctrl_head == NULL) { 843 err = ENOMEM; 844 goto bad1; 845 } 846 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 847 848 /* Allocate dummy ED that starts the bulk list. */ 849 sc->sc_bulk_head = ohci_alloc_sed(sc); 850 if (sc->sc_bulk_head == NULL) { 851 err = ENOMEM; 852 goto bad2; 853 } 854 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 855 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 856 sizeof(sc->sc_bulk_head->ed), 857 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 858 859 /* Allocate dummy ED that starts the isochronous list. */ 860 sc->sc_isoc_head = ohci_alloc_sed(sc); 861 if (sc->sc_isoc_head == NULL) { 862 err = ENOMEM; 863 goto bad3; 864 } 865 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 866 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 867 sizeof(sc->sc_isoc_head->ed), 868 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 869 870 /* Allocate all the dummy EDs that make up the interrupt tree. */ 871 for (i = 0; i < OHCI_NO_EDS; i++) { 872 sed = ohci_alloc_sed(sc); 873 if (sed == NULL) { 874 while (--i >= 0) 875 ohci_free_sed(sc, sc->sc_eds[i]); 876 err = ENOMEM; 877 goto bad4; 878 } 879 /* All ED fields are set to 0. */ 880 sc->sc_eds[i] = sed; 881 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 882 if (i != 0) 883 psed = sc->sc_eds[(i-1) / 2]; 884 else 885 psed= sc->sc_isoc_head; 886 sed->next = psed; 887 sed->ed.ed_nexted = HTOO32(psed->physaddr); 888 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 889 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 890 } 891 /* 892 * Fill HCCA interrupt table. The bit reversal is to get 893 * the tree set up properly to spread the interrupts. 894 */ 895 for (i = 0; i < OHCI_NO_INTRS; i++) 896 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 897 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 898 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 899 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 900 901 #ifdef OHCI_DEBUG 902 DPRINTFN(15, "--- dump start ---", 0, 0, 0 ,0); 903 if (ohcidebug >= 15) { 904 for (i = 0; i < OHCI_NO_EDS; i++) { 905 DPRINTFN(15, "ed#%jd ", i, 0, 0, 0); 906 ohci_dump_ed(sc, sc->sc_eds[i]); 907 } 908 DPRINTFN(15, "iso", 0, 0, 0 ,0); 909 ohci_dump_ed(sc, sc->sc_isoc_head); 910 } 911 DPRINTFN(15, "--- dump end ---", 0, 0, 0 ,0); 912 #endif 913 914 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 915 ctl = OREAD4(sc, OHCI_CONTROL); 916 rwc = ctl & OHCI_RWC; 917 fm = OREAD4(sc, OHCI_FM_INTERVAL); 918 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 919 /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */ 920 921 /* Determine in what context we are running. */ 922 if (ctl & OHCI_IR) { 923 /* SMM active, request change */ 924 DPRINTF("SMM active, request owner change", 0, 0, 0, 0); 925 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 926 (OHCI_OC | OHCI_MIE)) 927 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 928 s = OREAD4(sc, OHCI_COMMAND_STATUS); 929 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 930 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 931 usb_delay_ms(&sc->sc_bus, 1); 932 ctl = OREAD4(sc, OHCI_CONTROL); 933 } 934 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 935 if ((ctl & OHCI_IR) == 0) { 936 aprint_error_dev(sc->sc_dev, 937 "SMM does not respond, resetting\n"); 938 OWRITE4(sc, OHCI_CONTROL, 939 OHCI_SET_HCFS(OHCI_HCFS_RESET) | rwc); 940 goto reset; 941 } 942 #if 0 943 /* 944 * Don't bother trying to reuse the BIOS init, we'll reset it 945 * anyway. 946 */ 947 } else if (OHCI_GET_HCFS(ctl) != OHCI_HCFS_RESET) { 948 /* BIOS started controller. */ 949 DPRINTF("BIOS active", 0, 0, 0, 0); 950 if (OHCI_GET_HCFS(ctl) != OHCI_HCFS_OPERATIONAL) { 951 OWRITE4(sc, OHCI_CONTROL, 952 OHCI_SET_HCFS(OHCI_HCFS_OPERATIONAL) | rwc); 953 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 954 } 955 #endif 956 } else { 957 DPRINTF("cold started", 0 ,0 ,0 ,0); 958 reset: 959 /* Controller was cold started. */ 960 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 961 } 962 963 /* 964 * This reset should not be necessary according to the OHCI spec, but 965 * without it some controllers do not start. 966 */ 967 DPRINTF("sc %#jx: resetting", (uintptr_t)sc, 0, 0, 0); 968 OWRITE4(sc, OHCI_CONTROL, OHCI_SET_HCFS(OHCI_HCFS_RESET) | rwc); 969 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 970 971 /* We now own the host controller and the bus has been reset. */ 972 973 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 974 /* Nominal time for a reset is 10 us. */ 975 for (i = 0; i < 10; i++) { 976 delay(10); 977 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 978 if (!hcr) 979 break; 980 } 981 if (hcr) { 982 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 983 err = EIO; 984 goto bad5; 985 } 986 #ifdef OHCI_DEBUG 987 if (ohcidebug >= 15) 988 ohci_dumpregs(sc); 989 #endif 990 991 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 992 993 /* Set up HC registers. */ 994 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 995 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 996 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 997 /* disable all interrupts and then switch on all desired interrupts */ 998 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 999 /* switch on desired functional features */ 1000 ctl = OREAD4(sc, OHCI_CONTROL); 1001 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 1002 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 1003 OHCI_CBSR_SET(OHCI_RATIO_1_4) | 1004 OHCI_SET_HCFS(OHCI_HCFS_OPERATIONAL) | rwc; 1005 /* And finally start it! */ 1006 OWRITE4(sc, OHCI_CONTROL, ctl); 1007 1008 /* 1009 * The controller is now OPERATIONAL. Set a some final 1010 * registers that should be set earlier, but that the 1011 * controller ignores when in the SUSPEND state. 1012 */ 1013 ival = OHCI_FM_GET_IVAL(fm); 1014 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FM_FIT) ^ OHCI_FM_FIT; 1015 fm |= OHCI_FSMPS(ival) | ival; 1016 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 1017 per = OHCI_PERIODIC(ival); /* 90% periodic */ 1018 OWRITE4(sc, OHCI_PERIODIC_START, per); 1019 1020 if (sc->sc_flags & OHCIF_SUPERIO) { 1021 /* no overcurrent protection */ 1022 desca |= OHCI_RHD_NOCP; 1023 /* 1024 * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning 1025 * that 1026 * - ports are always power switched 1027 * - don't wait for powered root hub port 1028 */ 1029 desca &= ~(OHCI_RHD_POTPGT_MASK | OHCI_RHD_NPS); 1030 } 1031 1032 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 1033 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_RHD_NOCP); 1034 OWRITE4(sc, OHCI_RH_STATUS, OHCI_RHS_LPSC); /* Enable port power */ 1035 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 1036 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 1037 1038 /* 1039 * The AMD756 requires a delay before re-reading the register, 1040 * otherwise it will occasionally report 0 ports. 1041 */ 1042 sc->sc_noport = 0; 1043 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 1044 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 1045 sc->sc_noport = 1046 OHCI_RHD_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 1047 } 1048 1049 #ifdef OHCI_DEBUG 1050 if (ohcidebug >= 5) 1051 ohci_dumpregs(sc); 1052 #endif 1053 1054 /* Set up the bus struct. */ 1055 sc->sc_bus.ub_methods = &ohci_bus_methods; 1056 sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe); 1057 1058 sc->sc_control = sc->sc_intre = 0; 1059 1060 /* Finally, turn on interrupts. */ 1061 DPRINTF("enabling %#jx", sc->sc_eintrs | OHCI_MIE, 0, 0, 0); 1062 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 1063 1064 return 0; 1065 1066 bad5: 1067 for (i = 0; i < OHCI_NO_EDS; i++) 1068 ohci_free_sed(sc, sc->sc_eds[i]); 1069 bad4: 1070 ohci_free_sed(sc, sc->sc_isoc_head); 1071 bad3: 1072 ohci_free_sed(sc, sc->sc_bulk_head); 1073 bad2: 1074 ohci_free_sed(sc, sc->sc_ctrl_head); 1075 bad1: 1076 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 1077 sc->sc_hcca = NULL; 1078 return err; 1079 } 1080 1081 struct usbd_xfer * 1082 ohci_allocx(struct usbd_bus *bus, unsigned int nframes) 1083 { 1084 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1085 struct usbd_xfer *xfer; 1086 1087 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 1088 if (xfer != NULL) { 1089 memset(xfer, 0, sizeof(struct ohci_xfer)); 1090 1091 #ifdef DIAGNOSTIC 1092 xfer->ux_state = XFER_BUSY; 1093 #endif 1094 } 1095 return xfer; 1096 } 1097 1098 void 1099 ohci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1100 { 1101 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1102 1103 KASSERTMSG(xfer->ux_state == XFER_BUSY || 1104 xfer->ux_status == USBD_NOT_STARTED, 1105 "xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state); 1106 #ifdef DIAGNOSTIC 1107 xfer->ux_state = XFER_FREE; 1108 #endif 1109 pool_cache_put(sc->sc_xferpool, xfer); 1110 } 1111 1112 Static bool 1113 ohci_dying(struct usbd_bus *bus) 1114 { 1115 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1116 1117 return sc->sc_dying; 1118 } 1119 1120 Static void 1121 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1122 { 1123 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1124 1125 *lock = &sc->sc_lock; 1126 } 1127 1128 /* 1129 * Shut down the controller when the system is going down. 1130 */ 1131 bool 1132 ohci_shutdown(device_t self, int flags) 1133 { 1134 ohci_softc_t *sc = device_private(self); 1135 1136 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1137 1138 DPRINTF("stopping the HC", 0, 0, 0, 0); 1139 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 1140 OWRITE4(sc, OHCI_CONTROL, OHCI_SET_HCFS(OHCI_HCFS_RESET)); 1141 return true; 1142 } 1143 1144 bool 1145 ohci_resume(device_t dv, const pmf_qual_t *qual) 1146 { 1147 ohci_softc_t *sc = device_private(dv); 1148 uint32_t ctl; 1149 1150 mutex_spin_enter(&sc->sc_intr_lock); 1151 sc->sc_bus.ub_usepolling++; 1152 mutex_spin_exit(&sc->sc_intr_lock); 1153 1154 /* Some broken BIOSes do not recover these values */ 1155 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1156 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1157 sc->sc_ctrl_head->physaddr); 1158 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1159 sc->sc_bulk_head->physaddr); 1160 if (sc->sc_intre) 1161 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1162 (OHCI_ALL_INTRS | OHCI_MIE)); 1163 if (sc->sc_control) 1164 ctl = sc->sc_control; 1165 else 1166 ctl = OREAD4(sc, OHCI_CONTROL); 1167 ctl |= OHCI_SET_HCFS(OHCI_HCFS_RESUME); 1168 OWRITE4(sc, OHCI_CONTROL, ctl); 1169 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1170 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_SET_HCFS(OHCI_HCFS_OPERATIONAL); 1171 OWRITE4(sc, OHCI_CONTROL, ctl); 1172 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1173 sc->sc_control = sc->sc_intre = 0; 1174 1175 mutex_spin_enter(&sc->sc_intr_lock); 1176 sc->sc_bus.ub_usepolling--; 1177 mutex_spin_exit(&sc->sc_intr_lock); 1178 1179 return true; 1180 } 1181 1182 bool 1183 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1184 { 1185 ohci_softc_t *sc = device_private(dv); 1186 uint32_t ctl; 1187 1188 mutex_spin_enter(&sc->sc_intr_lock); 1189 sc->sc_bus.ub_usepolling++; 1190 mutex_spin_exit(&sc->sc_intr_lock); 1191 1192 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1193 if (sc->sc_control == 0) { 1194 /* 1195 * Preserve register values, in case that BIOS 1196 * does not recover them. 1197 */ 1198 sc->sc_control = ctl; 1199 sc->sc_intre = OREAD4(sc, 1200 OHCI_INTERRUPT_ENABLE); 1201 } 1202 ctl |= OHCI_SET_HCFS(OHCI_HCFS_SUSPEND); 1203 OWRITE4(sc, OHCI_CONTROL, ctl); 1204 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1205 1206 mutex_spin_enter(&sc->sc_intr_lock); 1207 sc->sc_bus.ub_usepolling--; 1208 mutex_spin_exit(&sc->sc_intr_lock); 1209 1210 return true; 1211 } 1212 1213 #ifdef OHCI_DEBUG 1214 void 1215 ohci_dumpregs(ohci_softc_t *sc) 1216 { 1217 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1218 1219 DPRINTF("rev=0x%08jx control=0x%08jx command=0x%08jx", 1220 OREAD4(sc, OHCI_REVISION), 1221 OREAD4(sc, OHCI_CONTROL), 1222 OREAD4(sc, OHCI_COMMAND_STATUS), 0); 1223 DPRINTF(" intrstat=0x%08jx intre=0x%08jx intrd=0x%08jx", 1224 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1225 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1226 OREAD4(sc, OHCI_INTERRUPT_DISABLE), 0); 1227 DPRINTF(" hcca=0x%08jx percur=0x%08jx ctrlhd=0x%08jx", 1228 OREAD4(sc, OHCI_HCCA), 1229 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1230 OREAD4(sc, OHCI_CONTROL_HEAD_ED), 0); 1231 DPRINTF(" ctrlcur=0x%08jx bulkhd=0x%08jx bulkcur=0x%08jx", 1232 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1233 OREAD4(sc, OHCI_BULK_HEAD_ED), 1234 OREAD4(sc, OHCI_BULK_CURRENT_ED) ,0); 1235 DPRINTF(" done=0x%08jx fmival=0x%08jx fmrem=0x%08jx", 1236 OREAD4(sc, OHCI_DONE_HEAD), 1237 OREAD4(sc, OHCI_FM_INTERVAL), 1238 OREAD4(sc, OHCI_FM_REMAINING), 0); 1239 DPRINTF(" fmnum=0x%08jx perst=0x%08jx lsthrs=0x%08jx", 1240 OREAD4(sc, OHCI_FM_NUMBER), 1241 OREAD4(sc, OHCI_PERIODIC_START), 1242 OREAD4(sc, OHCI_LS_THRESHOLD), 0); 1243 DPRINTF(" desca=0x%08jx descb=0x%08jx stat=0x%08jx", 1244 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1245 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1246 OREAD4(sc, OHCI_RH_STATUS), 0); 1247 DPRINTF(" port1=0x%08jx port2=0x%08jx", 1248 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1249 OREAD4(sc, OHCI_RH_PORT_STATUS(2)), 0, 0); 1250 usb_syncmem(&sc->sc_hccadma, 1251 offsetof(struct ohci_hcca, hcca_frame_number), 1252 sizeof(sc->sc_hcca->hcca_frame_number) + 1253 sizeof(sc->sc_hcca->hcca_done_head), 1254 BUS_DMASYNC_POSTREAD); 1255 DPRINTF(" HCCA: frame_number=0x%04jx done_head=0x%08jx", 1256 O32TOH(sc->sc_hcca->hcca_frame_number), 1257 O32TOH(sc->sc_hcca->hcca_done_head), 0, 0); 1258 } 1259 #endif 1260 1261 Static int ohci_intr1(ohci_softc_t *); 1262 1263 int 1264 ohci_intr(void *p) 1265 { 1266 ohci_softc_t *sc = p; 1267 int ret = 0; 1268 1269 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1270 1271 if (sc == NULL) 1272 return 0; 1273 1274 mutex_spin_enter(&sc->sc_intr_lock); 1275 1276 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1277 goto done; 1278 1279 /* If we get an interrupt while polling, then just ignore it. */ 1280 if (sc->sc_bus.ub_usepolling) { 1281 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1282 /* for level triggered intrs, should do something to ack */ 1283 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1284 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1285 1286 goto done; 1287 } 1288 1289 ret = ohci_intr1(sc); 1290 1291 done: 1292 mutex_spin_exit(&sc->sc_intr_lock); 1293 return ret; 1294 } 1295 1296 Static int 1297 ohci_intr1(ohci_softc_t *sc) 1298 { 1299 uint32_t intrs, eintrs; 1300 1301 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1302 1303 /* In case the interrupt occurs before initialization has completed. */ 1304 if (sc == NULL || sc->sc_hcca == NULL) { 1305 #ifdef DIAGNOSTIC 1306 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1307 #endif 1308 return 0; 1309 } 1310 1311 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1312 1313 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1314 if (!intrs) 1315 return 0; 1316 1317 /* Acknowledge */ 1318 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); 1319 eintrs = intrs & sc->sc_eintrs; 1320 DPRINTFN(7, "sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1321 DPRINTFN(7, "intrs=%#jx(%#jx) eintrs=%#jx(%#jx)", 1322 intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), eintrs, 1323 sc->sc_eintrs); 1324 1325 if (!eintrs) { 1326 return 0; 1327 } 1328 1329 if (eintrs & OHCI_SO) { 1330 sc->sc_overrun_cnt++; 1331 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1332 printf("%s: %u scheduling overruns\n", 1333 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1334 sc->sc_overrun_cnt = 0; 1335 } 1336 /* XXX do what */ 1337 eintrs &= ~OHCI_SO; 1338 } 1339 if (eintrs & OHCI_WDH) { 1340 /* 1341 * We block the interrupt below, and reenable it later from 1342 * ohci_softintr(). 1343 */ 1344 usb_schedsoftintr(&sc->sc_bus); 1345 } 1346 if (eintrs & OHCI_SF) { 1347 struct ohci_xfer *ox, *tmp; 1348 TAILQ_FOREACH_SAFE(ox, &sc->sc_abortingxfers, ox_abnext, tmp) { 1349 DPRINTFN(10, "SF %#jx xfer %#jx", (uintptr_t)sc, 1350 (uintptr_t)ox, 0, 0); 1351 ox->ox_abintrs &= ~OHCI_SF; 1352 KASSERT(ox->ox_abintrs == 0); 1353 TAILQ_REMOVE(&sc->sc_abortingxfers, ox, ox_abnext); 1354 } 1355 cv_broadcast(&sc->sc_abort_cv); 1356 1357 KASSERT(TAILQ_EMPTY(&sc->sc_abortingxfers)); 1358 DPRINTFN(10, "end SOF %#jx", (uintptr_t)sc, 0, 0, 0); 1359 /* Don't remove OHIC_SF from eintrs so it is blocked below */ 1360 } 1361 if (eintrs & OHCI_RD) { 1362 DPRINTFN(5, "resume detect sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1363 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1364 /* XXX process resume detect */ 1365 } 1366 if (eintrs & OHCI_UE) { 1367 DPRINTFN(5, "unrecoverable error sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1368 printf("%s: unrecoverable error, controller halted\n", 1369 device_xname(sc->sc_dev)); 1370 OWRITE4(sc, OHCI_CONTROL, OHCI_SET_HCFS(OHCI_HCFS_RESET)); 1371 /* XXX what else */ 1372 } 1373 if (eintrs & OHCI_RHSC) { 1374 /* 1375 * We block the interrupt below, and reenable it later from 1376 * a timeout. 1377 */ 1378 softint_schedule(sc->sc_rhsc_si); 1379 } 1380 1381 if (eintrs != 0) { 1382 /* Block unprocessed interrupts. */ 1383 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1384 sc->sc_eintrs &= ~eintrs; 1385 DPRINTF("sc %#jx blocking intrs %#jx", (uintptr_t)sc, 1386 eintrs, 0, 0); 1387 } 1388 1389 return 1; 1390 } 1391 1392 void 1393 ohci_rhsc_enable(void *v_sc) 1394 { 1395 ohci_softc_t *sc = v_sc; 1396 1397 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1398 DPRINTF("sc %#jx", (uintptr_t)sc, 0, 0, 0); 1399 mutex_spin_enter(&sc->sc_intr_lock); 1400 sc->sc_eintrs |= OHCI_RHSC; 1401 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1402 mutex_spin_exit(&sc->sc_intr_lock); 1403 } 1404 1405 #ifdef OHCI_DEBUG 1406 const char *const ohci_cc_strs[] = { 1407 "NO_ERROR", 1408 "CRC", 1409 "BIT_STUFFING", 1410 "DATA_TOGGLE_MISMATCH", 1411 "STALL", 1412 "DEVICE_NOT_RESPONDING", 1413 "PID_CHECK_FAILURE", 1414 "UNEXPECTED_PID", 1415 "DATA_OVERRUN", 1416 "DATA_UNDERRUN", 1417 "BUFFER_OVERRUN", 1418 "BUFFER_UNDERRUN", 1419 "reserved", 1420 "reserved", 1421 "NOT_ACCESSED", 1422 "NOT_ACCESSED", 1423 }; 1424 #endif 1425 1426 void 1427 ohci_softintr(void *v) 1428 { 1429 struct usbd_bus *bus = v; 1430 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1431 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1432 ohci_soft_td_t *std, *sdone, *stdnext; 1433 struct usbd_xfer *xfer; 1434 struct ohci_pipe *opipe; 1435 int len, cc; 1436 int i, j, actlen, iframes, uedir; 1437 ohci_physaddr_t done = 0; 1438 1439 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1440 1441 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1442 1443 /* 1444 * Only read hccadone if WDH is set - we might get here from places 1445 * other than an interrupt 1446 */ 1447 if (!(OREAD4(sc, OHCI_INTERRUPT_STATUS) & OHCI_WDH)) { 1448 DPRINTFN(10, "no WDH %#jx", (uintptr_t)sc, 0, 0, 0); 1449 return; 1450 } 1451 1452 DPRINTFN(10, "WDH %#jx", (uintptr_t)sc, 0, 0, 0); 1453 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1454 sizeof(sc->sc_hcca->hcca_done_head), 1455 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1456 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1457 sc->sc_hcca->hcca_done_head = 0; 1458 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1459 sizeof(sc->sc_hcca->hcca_done_head), 1460 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1461 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1462 sc->sc_eintrs |= OHCI_WDH; 1463 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1464 1465 /* Reverse the done list. */ 1466 for (sdone = NULL, sidone = NULL; done != 0; ) { 1467 std = ohci_hash_find_td(sc, done); 1468 if (std != NULL) { 1469 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1470 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1471 std->dnext = sdone; 1472 done = O32TOH(std->td.td_nexttd); 1473 sdone = std; 1474 DPRINTFN(10, "add TD %#jx", (uintptr_t)std, 0, 0, 0); 1475 continue; 1476 } 1477 sitd = ohci_hash_find_itd(sc, done); 1478 if (sitd != NULL) { 1479 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1480 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1481 sitd->dnext = sidone; 1482 done = O32TOH(sitd->itd.itd_nextitd); 1483 sidone = sitd; 1484 DPRINTFN(5, "add ITD %#jx", (uintptr_t)sitd, 0, 0, 0); 1485 continue; 1486 } 1487 DPRINTFN(10, "addr %#jx not found", (uintptr_t)done, 0, 0, 0); 1488 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1489 (u_long)done); 1490 break; 1491 } 1492 1493 DPRINTFN(10, "sdone=%#jx sidone=%#jx", (uintptr_t)sdone, 1494 (uintptr_t)sidone, 0, 0); 1495 DPRINTFN(10, "--- TD dump start ---", 0, 0, 0, 0); 1496 #ifdef OHCI_DEBUG 1497 if (ohcidebug >= 10) { 1498 for (std = sdone; std; std = std->dnext) 1499 ohci_dump_td(sc, std); 1500 } 1501 #endif 1502 DPRINTFN(10, "--- TD dump end ---", 0, 0, 0, 0); 1503 1504 for (std = sdone; std; std = stdnext) { 1505 stdnext = std->dnext; 1506 if (std->held == NULL) { 1507 DPRINTFN(10, "std=%#jx held is null", (uintptr_t)std, 1508 0, 0, 0); 1509 ohci_hash_rem_td(sc, std); 1510 ohci_free_std_locked(sc, std); 1511 continue; 1512 } 1513 1514 xfer = std->xfer; 1515 DPRINTFN(10, "std=%#jx xfer=%#jx hcpriv=%#jx dnext=%#jx", 1516 (uintptr_t)std, (uintptr_t)xfer, 1517 (uintptr_t)(xfer ? xfer->ux_hcpriv : 0), (uintptr_t)stdnext); 1518 if (xfer == NULL) { 1519 /* 1520 * xfer == NULL: There seems to be no xfer associated 1521 * with this TD. It is tailp that happened to end up on 1522 * the done queue. 1523 * Shouldn't happen, but some chips are broken(?). 1524 */ 1525 continue; 1526 } 1527 /* 1528 * Try to claim this xfer for completion. If it has 1529 * already completed or aborted, drop it on the floor. 1530 */ 1531 if (!usbd_xfer_trycomplete(xfer)) 1532 continue; 1533 1534 len = std->len; 1535 if (std->td.td_cbp != 0) 1536 len -= O32TOH(std->td.td_be) - 1537 O32TOH(std->td.td_cbp) + 1; 1538 DPRINTFN(10, "len=%jd, flags=%#jx", len, std->flags, 0, 0); 1539 if (std->flags & OHCI_ADD_LEN) 1540 xfer->ux_actlen += len; 1541 1542 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1543 if (cc == OHCI_CC_NO_ERROR) { 1544 ohci_hash_rem_td(sc, std); 1545 if (std->flags & OHCI_CALL_DONE) { 1546 xfer->ux_status = USBD_NORMAL_COMPLETION; 1547 usb_transfer_complete(xfer); 1548 } 1549 } else { 1550 /* 1551 * Endpoint is halted. First unlink all the TDs 1552 * belonging to the failed transfer, and then restart 1553 * the endpoint. 1554 */ 1555 ohci_soft_td_t *p, *n; 1556 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1557 1558 DPRINTFN(10, "error cc=%jd", cc, 0, 0, 0); 1559 1560 /* remove xfer's TDs from the hash */ 1561 for (p = std; p->xfer == xfer; p = n) { 1562 n = p->nexttd; 1563 ohci_hash_rem_td(sc, p); 1564 } 1565 1566 ohci_soft_ed_t *sed = opipe->sed; 1567 1568 /* clear halt and TD chain, preserving toggle carry */ 1569 sed->ed.ed_headp = HTOO32(p->physaddr | 1570 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 1571 usb_syncmem(&sed->dma, 1572 sed->offs + offsetof(ohci_ed_t, ed_headp), 1573 sizeof(sed->ed.ed_headp), 1574 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1575 1576 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1577 1578 if (cc == OHCI_CC_DATA_UNDERRUN) 1579 xfer->ux_status = USBD_NORMAL_COMPLETION; 1580 else if (cc == OHCI_CC_STALL) 1581 xfer->ux_status = USBD_STALLED; 1582 else 1583 xfer->ux_status = USBD_IOERROR; 1584 usb_transfer_complete(xfer); 1585 } 1586 } 1587 DPRINTFN(10, "--- ITD dump start ---", 0, 0, 0, 0); 1588 #ifdef OHCI_DEBUG 1589 if (ohcidebug >= 10) { 1590 for (sitd = sidone; sitd; sitd = sitd->dnext) 1591 ohci_dump_itd(sc, sitd); 1592 } 1593 #endif 1594 DPRINTFN(10, "--- ITD dump end ---", 0, 0, 0, 0); 1595 1596 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1597 xfer = sitd->xfer; 1598 sitdnext = sitd->dnext; 1599 DPRINTFN(1, "sitd=%#jx xfer=%#jx hcpriv=%#jx", (uintptr_t)sitd, 1600 (uintptr_t)xfer, (uintptr_t)(xfer ? xfer->ux_hcpriv : 0), 1601 0); 1602 if (xfer == NULL) 1603 continue; 1604 1605 /* 1606 * Try to claim this xfer for completion. If it has 1607 * already completed or aborted, drop it on the floor. 1608 */ 1609 if (!usbd_xfer_trycomplete(xfer)) 1610 continue; 1611 1612 KASSERT(!sitd->isdone); 1613 #ifdef DIAGNOSTIC 1614 sitd->isdone = true; 1615 #endif 1616 if (sitd->flags & OHCI_CALL_DONE) { 1617 ohci_soft_itd_t *next; 1618 1619 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1620 opipe->isoc.inuse -= xfer->ux_nframes; 1621 uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc-> 1622 bEndpointAddress); 1623 xfer->ux_status = USBD_NORMAL_COMPLETION; 1624 actlen = 0; 1625 for (i = 0, sitd = xfer->ux_hcpriv;; 1626 sitd = next) { 1627 next = sitd->nextitd; 1628 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1629 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1630 xfer->ux_status = USBD_IOERROR; 1631 /* For input, update frlengths with actual */ 1632 /* XXX anything necessary for output? */ 1633 if (uedir == UE_DIR_IN && 1634 xfer->ux_status == USBD_NORMAL_COMPLETION) { 1635 iframes = OHCI_ITD_GET_FC(O32TOH( 1636 sitd->itd.itd_flags)); 1637 for (j = 0; j < iframes; i++, j++) { 1638 len = O16TOH(sitd-> 1639 itd.itd_offset[j]); 1640 if ((OHCI_ITD_PSW_GET_CC(len) & 1641 OHCI_CC_NOT_ACCESSED_MASK) 1642 == OHCI_CC_NOT_ACCESSED) 1643 len = 0; 1644 else 1645 len = OHCI_ITD_PSW_SIZE(len); 1646 xfer->ux_frlengths[i] = len; 1647 actlen += len; 1648 } 1649 } 1650 if (sitd->flags & OHCI_CALL_DONE) 1651 break; 1652 ohci_hash_rem_itd(sc, sitd); 1653 1654 } 1655 ohci_hash_rem_itd(sc, sitd); 1656 if (uedir == UE_DIR_IN && 1657 xfer->ux_status == USBD_NORMAL_COMPLETION) 1658 xfer->ux_actlen = actlen; 1659 xfer->ux_hcpriv = NULL; 1660 1661 usb_transfer_complete(xfer); 1662 } 1663 } 1664 1665 DPRINTFN(10, "done", 0, 0, 0, 0); 1666 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1667 } 1668 1669 void 1670 ohci_device_ctrl_done(struct usbd_xfer *xfer) 1671 { 1672 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1673 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1674 int len = UGETW(xfer->ux_request.wLength); 1675 int isread = (xfer->ux_request.bmRequestType & UT_READ); 1676 1677 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1678 DPRINTFN(10, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 1679 1680 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1681 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 1682 1683 if (len) 1684 usb_syncmem(&xfer->ux_dmabuf, 0, len, 1685 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1686 usb_syncmem(&opipe->ctrl.reqdma, 0, 1687 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1688 } 1689 1690 void 1691 ohci_device_intr_done(struct usbd_xfer *xfer) 1692 { 1693 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1694 int isread = 1695 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1696 1697 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1698 DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, 1699 xfer->ux_actlen, 0, 0); 1700 1701 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1702 1703 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1704 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1705 } 1706 1707 void 1708 ohci_device_bulk_done(struct usbd_xfer *xfer) 1709 { 1710 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1711 1712 int isread = 1713 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1714 1715 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1716 1717 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1718 DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 1719 0, 0); 1720 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1721 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1722 } 1723 1724 Static void 1725 ohci_rhsc_softint(void *arg) 1726 { 1727 ohci_softc_t *sc = arg; 1728 1729 mutex_enter(&sc->sc_lock); 1730 1731 ohci_rhsc(sc, sc->sc_intrxfer); 1732 1733 /* Do not allow RHSC interrupts > 1 per second */ 1734 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1735 1736 mutex_exit(&sc->sc_lock); 1737 } 1738 1739 void 1740 ohci_rhsc(ohci_softc_t *sc, struct usbd_xfer *xfer) 1741 { 1742 u_char *p; 1743 int i, m; 1744 int hstatus __unused; 1745 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1746 1747 KASSERT(mutex_owned(&sc->sc_lock)); 1748 1749 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1750 DPRINTF("sc=%#jx xfer=%#jx hstatus=0x%08jx", (uintptr_t)sc, 1751 (uintptr_t)xfer, hstatus, 0); 1752 1753 if (xfer == NULL) { 1754 /* Just ignore the change. */ 1755 return; 1756 } 1757 KASSERT(xfer == sc->sc_intrxfer); 1758 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 1759 1760 p = xfer->ux_buf; 1761 m = uimin(sc->sc_noport, xfer->ux_length * 8 - 1); 1762 memset(p, 0, xfer->ux_length); 1763 for (i = 1; i <= m; i++) { 1764 /* Pick out CHANGE bits from the status reg. */ 1765 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1766 p[i/8] |= 1 << (i%8); 1767 } 1768 DPRINTF("change=0x%02jx", *p, 0, 0, 0); 1769 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 1770 xfer->ux_actlen = xfer->ux_length; 1771 xfer->ux_status = USBD_NORMAL_COMPLETION; 1772 1773 usb_transfer_complete(xfer); 1774 } 1775 1776 void 1777 ohci_root_intr_done(struct usbd_xfer *xfer) 1778 { 1779 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1780 1781 KASSERT(mutex_owned(&sc->sc_lock)); 1782 1783 /* Claim the xfer so it doesn't get completed again. */ 1784 KASSERT(sc->sc_intrxfer == xfer); 1785 KASSERT(xfer->ux_status != USBD_IN_PROGRESS); 1786 sc->sc_intrxfer = NULL; 1787 } 1788 1789 void 1790 ohci_poll(struct usbd_bus *bus) 1791 { 1792 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1793 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1794 1795 #ifdef OHCI_DEBUG 1796 static int last; 1797 int new; 1798 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1799 if (new != last) { 1800 DPRINTFN(10, "intrs=0x%04jx", new, 0, 0, 0); 1801 last = new; 1802 } 1803 #endif 1804 sc->sc_eintrs |= OHCI_WDH; 1805 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1806 mutex_spin_enter(&sc->sc_intr_lock); 1807 ohci_intr1(sc); 1808 mutex_spin_exit(&sc->sc_intr_lock); 1809 } 1810 } 1811 1812 /* 1813 * Add an ED to the schedule. Called with USB lock held. 1814 */ 1815 Static void 1816 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1817 { 1818 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1819 DPRINTFN(8, "sed=%#jx head=%#jx", (uintptr_t)sed, (uintptr_t)head, 0, 1820 0); 1821 1822 KASSERT(mutex_owned(&sc->sc_lock)); 1823 1824 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1825 sizeof(head->ed.ed_nexted), 1826 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1827 sed->next = head->next; 1828 sed->ed.ed_nexted = head->ed.ed_nexted; 1829 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1830 sizeof(sed->ed.ed_nexted), 1831 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1832 head->next = sed; 1833 head->ed.ed_nexted = HTOO32(sed->physaddr); 1834 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1835 sizeof(head->ed.ed_nexted), 1836 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1837 } 1838 1839 /* 1840 * Remove an ED from the schedule. Called with USB lock held. 1841 */ 1842 Static void 1843 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1844 { 1845 ohci_soft_ed_t *p; 1846 1847 KASSERT(mutex_owned(&sc->sc_lock)); 1848 1849 /* XXX */ 1850 for (p = head; p != NULL && p->next != sed; p = p->next) 1851 ; 1852 KASSERT(p != NULL); 1853 1854 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1855 sizeof(sed->ed.ed_nexted), 1856 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1857 p->next = sed->next; 1858 p->ed.ed_nexted = sed->ed.ed_nexted; 1859 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1860 sizeof(p->ed.ed_nexted), 1861 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1862 } 1863 1864 /* 1865 * When a transfer is completed the TD is added to the done queue by 1866 * the host controller. This queue is the processed by software. 1867 * Unfortunately the queue contains the physical address of the TD 1868 * and we have no simple way to translate this back to a kernel address. 1869 * To make the translation possible (and fast) we use a hash table of 1870 * TDs currently in the schedule. The physical address is used as the 1871 * hash value. 1872 */ 1873 1874 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1875 /* Called with USB lock held. */ 1876 void 1877 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1878 { 1879 int h = HASH(std->physaddr); 1880 1881 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1882 1883 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1884 } 1885 1886 /* Called with USB lock held. */ 1887 void 1888 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1889 { 1890 1891 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1892 1893 LIST_REMOVE(std, hnext); 1894 } 1895 1896 ohci_soft_td_t * 1897 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1898 { 1899 int h = HASH(a); 1900 ohci_soft_td_t *std; 1901 1902 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1903 std != NULL; 1904 std = LIST_NEXT(std, hnext)) 1905 if (std->physaddr == a) 1906 return std; 1907 return NULL; 1908 } 1909 1910 /* Called with USB lock held. */ 1911 void 1912 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1913 { 1914 int h = HASH(sitd->physaddr); 1915 1916 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1917 1918 KASSERT(mutex_owned(&sc->sc_lock)); 1919 1920 DPRINTFN(10, "sitd=%#jx physaddr=0x%08jx", 1921 (uintptr_t)sitd, (u_long)sitd->physaddr, 0, 0); 1922 1923 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1924 } 1925 1926 /* Called with USB lock held. */ 1927 void 1928 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1929 { 1930 1931 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1932 1933 KASSERT(mutex_owned(&sc->sc_lock)); 1934 1935 DPRINTFN(10, "sitd=%#jx physaddr=0x%08jx", (uintptr_t)sitd, 1936 sitd->physaddr, 0, 0); 1937 1938 LIST_REMOVE(sitd, hnext); 1939 } 1940 1941 ohci_soft_itd_t * 1942 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1943 { 1944 int h = HASH(a); 1945 ohci_soft_itd_t *sitd; 1946 1947 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1948 sitd != NULL; 1949 sitd = LIST_NEXT(sitd, hnext)) 1950 if (sitd->physaddr == a) 1951 return sitd; 1952 return NULL; 1953 } 1954 1955 #ifdef OHCI_DEBUG 1956 void 1957 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 1958 { 1959 for (; std; std = std->nexttd) { 1960 ohci_dump_td(sc, std); 1961 KASSERTMSG(std->nexttd == NULL || std != std->nexttd, 1962 "std %p next %p", std, std->nexttd); 1963 } 1964 } 1965 1966 void 1967 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1968 { 1969 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1970 1971 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1972 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1973 1974 uint32_t flags = O32TOH(std->td.td_flags); 1975 DPRINTF("TD(%#jx) at 0x%08jx:", (uintptr_t)std, std->physaddr, 0, 0); 1976 DPRINTF(" round=%jd DP=%jx DI=%jx T=%jx", 1977 !!(flags & OHCI_TD_R), 1978 OHCI_TD_GET_DP(flags), 1979 OHCI_TD_GET_DI(flags), 1980 OHCI_TD_GET_TOGGLE(flags)); 1981 DPRINTF(" EC=%jd CC=%jd", OHCI_TD_GET_EC(flags), 1982 OHCI_TD_GET_CC(flags), 0, 0); 1983 DPRINTF(" td_cbp=0x%08jx td_nexttd=0x%08jx td_be=0x%08jx", 1984 (u_long)O32TOH(std->td.td_cbp), 1985 (u_long)O32TOH(std->td.td_nexttd), 1986 (u_long)O32TOH(std->td.td_be), 0); 1987 } 1988 1989 void 1990 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1991 { 1992 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1993 1994 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1995 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1996 1997 uint32_t flags = O32TOH(sitd->itd.itd_flags); 1998 DPRINTF("ITD(%#jx) at 0x%08jx", (uintptr_t)sitd, sitd->physaddr, 0, 0); 1999 DPRINTF(" sf=%jd di=%jd fc=%jd cc=%jd", 2000 OHCI_ITD_GET_SF(flags), OHCI_ITD_GET_DI(flags), 2001 OHCI_ITD_GET_FC(flags), OHCI_ITD_GET_CC(flags)); 2002 DPRINTF(" bp0=0x%08jx next=0x%08jx be=0x%08jx", 2003 O32TOH(sitd->itd.itd_bp0), 2004 O32TOH(sitd->itd.itd_nextitd), 2005 O32TOH(sitd->itd.itd_be), 0); 2006 CTASSERT(OHCI_ITD_NOFFSET == 8); 2007 DPRINTF(" offs[0] = 0x%04jx offs[1] = 0x%04jx " 2008 "offs[2] = 0x%04jx offs[3] = 0x%04jx", 2009 O16TOH(sitd->itd.itd_offset[0]), 2010 O16TOH(sitd->itd.itd_offset[1]), 2011 O16TOH(sitd->itd.itd_offset[2]), 2012 O16TOH(sitd->itd.itd_offset[3])); 2013 DPRINTF(" offs[4] = 0x%04jx offs[5] = 0x%04jx " 2014 "offs[6] = 0x%04jx offs[7] = 0x%04jx", 2015 O16TOH(sitd->itd.itd_offset[4]), 2016 O16TOH(sitd->itd.itd_offset[5]), 2017 O16TOH(sitd->itd.itd_offset[6]), 2018 O16TOH(sitd->itd.itd_offset[7])); 2019 } 2020 2021 void 2022 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2023 { 2024 for (; sitd; sitd = sitd->nextitd) 2025 ohci_dump_itd(sc, sitd); 2026 } 2027 2028 void 2029 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2030 { 2031 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2032 2033 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2034 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2035 2036 uint32_t flags = O32TOH(sed->ed.ed_flags); 2037 DPRINTF("ED(%#jx) at 0x%08jx:", (uintptr_t)sed, sed->physaddr, 0, 0); 2038 DPRINTF(" addr=%jd endpt=%jd maxp=%jd", 2039 OHCI_ED_GET_FA(flags), 2040 OHCI_ED_GET_EN(flags), 2041 OHCI_ED_GET_MAXP(flags), 2042 0); 2043 DPRINTF(" dir=%jd speed=%jd skip=%jd iso=%jd", 2044 OHCI_ED_GET_DIR(flags), 2045 __SHIFTOUT(flags, OHCI_ED_SPEED), 2046 __SHIFTOUT(flags, OHCI_ED_SKIP), 2047 OHCI_ED_GET_FORMAT(flags)); 2048 DPRINTF(" tailp=0x%08jx", (u_long)O32TOH(sed->ed.ed_tailp), 2049 0, 0, 0); 2050 DPRINTF(" headp=0x%08jx nexted=0x%08jx halted=%jd carry=%jd", 2051 O32TOH(sed->ed.ed_headp), O32TOH(sed->ed.ed_nexted), 2052 !!(O32TOH(sed->ed.ed_headp) & OHCI_HALTED), 2053 !!(O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 2054 } 2055 #endif 2056 2057 usbd_status 2058 ohci_open(struct usbd_pipe *pipe) 2059 { 2060 struct usbd_device *dev = pipe->up_dev; 2061 struct usbd_bus *bus = dev->ud_bus; 2062 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2063 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 2064 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2065 uint8_t addr = dev->ud_addr; 2066 uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2067 ohci_soft_ed_t *sed; 2068 ohci_soft_td_t *std; 2069 ohci_soft_itd_t *sitd; 2070 ohci_physaddr_t tdphys; 2071 uint32_t fmt; 2072 usbd_status err = USBD_NOMEM; 2073 int ival; 2074 2075 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2076 DPRINTFN(1, "pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, 2077 addr, ed->bEndpointAddress, bus->ub_rhaddr); 2078 2079 if (sc->sc_dying) { 2080 return USBD_IOERROR; 2081 } 2082 2083 std = NULL; 2084 sed = NULL; 2085 2086 if (addr == bus->ub_rhaddr) { 2087 switch (ed->bEndpointAddress) { 2088 case USB_CONTROL_ENDPOINT: 2089 pipe->up_methods = &roothub_ctrl_methods; 2090 break; 2091 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 2092 pipe->up_methods = &ohci_root_intr_methods; 2093 break; 2094 default: 2095 err = USBD_INVAL; 2096 goto bad; 2097 } 2098 } else { 2099 sed = ohci_alloc_sed(sc); 2100 if (sed == NULL) 2101 goto bad; 2102 opipe->sed = sed; 2103 if (xfertype == UE_ISOCHRONOUS) { 2104 sitd = ohci_alloc_sitd(sc); 2105 if (sitd == NULL) 2106 goto bad; 2107 2108 opipe->tail.itd = sitd; 2109 sitd->held = &opipe->tail.itd; 2110 tdphys = sitd->physaddr; 2111 fmt = OHCI_ED_SET_FORMAT(OHCI_ED_FORMAT_ISO); 2112 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2113 fmt |= OHCI_ED_SET_DIR(OHCI_ED_DIR_IN); 2114 else 2115 fmt |= OHCI_ED_SET_DIR(OHCI_ED_DIR_OUT); 2116 } else { 2117 std = ohci_alloc_std(sc); 2118 if (std == NULL) 2119 goto bad; 2120 2121 opipe->tail.td = std; 2122 std->held = &opipe->tail.td; 2123 tdphys = std->physaddr; 2124 fmt = 2125 OHCI_ED_SET_FORMAT(OHCI_ED_FORMAT_GEN) | 2126 OHCI_ED_SET_DIR(OHCI_ED_DIR_TD); 2127 } 2128 sed->ed.ed_flags = HTOO32( 2129 OHCI_ED_SET_FA(addr) | 2130 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2131 (dev->ud_speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2132 fmt | 2133 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2134 sed->ed.ed_headp = HTOO32(tdphys | 2135 (pipe->up_endpoint->ue_toggle ? OHCI_TOGGLECARRY : 0)); 2136 sed->ed.ed_tailp = HTOO32(tdphys); 2137 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2138 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2139 2140 switch (xfertype) { 2141 case UE_CONTROL: 2142 pipe->up_methods = &ohci_device_ctrl_methods; 2143 int error = usb_allocmem(&sc->sc_bus, 2144 sizeof(usb_device_request_t), 0, 2145 USBMALLOC_COHERENT, &opipe->ctrl.reqdma); 2146 if (error) 2147 goto bad; 2148 mutex_enter(&sc->sc_lock); 2149 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2150 mutex_exit(&sc->sc_lock); 2151 break; 2152 case UE_INTERRUPT: 2153 pipe->up_methods = &ohci_device_intr_methods; 2154 ival = pipe->up_interval; 2155 if (ival == USBD_DEFAULT_INTERVAL) 2156 ival = ed->bInterval; 2157 err = ohci_device_setintr(sc, opipe, ival); 2158 if (err) 2159 goto bad; 2160 break; 2161 case UE_ISOCHRONOUS: 2162 pipe->up_serialise = false; 2163 pipe->up_methods = &ohci_device_isoc_methods; 2164 return ohci_setup_isoc(pipe); 2165 case UE_BULK: 2166 pipe->up_methods = &ohci_device_bulk_methods; 2167 mutex_enter(&sc->sc_lock); 2168 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2169 mutex_exit(&sc->sc_lock); 2170 break; 2171 } 2172 } 2173 2174 return USBD_NORMAL_COMPLETION; 2175 2176 bad: 2177 if (std != NULL) { 2178 ohci_free_std(sc, std); 2179 } 2180 if (sed != NULL) 2181 ohci_free_sed(sc, sed); 2182 return err; 2183 2184 } 2185 2186 /* 2187 * Close a reqular pipe. 2188 * Assumes that there are no pending transactions. 2189 */ 2190 void 2191 ohci_close_pipe(struct usbd_pipe *pipe, ohci_soft_ed_t *head) 2192 { 2193 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2194 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2195 ohci_soft_ed_t *sed = opipe->sed; 2196 2197 KASSERT(mutex_owned(&sc->sc_lock)); 2198 2199 #ifdef DIAGNOSTIC 2200 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2201 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2202 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2203 ohci_soft_td_t *std; 2204 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2205 printf("ohci_close_pipe: pipe not empty sed=%p hd=%#x " 2206 "tl=%#x pipe=%p, std=%p\n", sed, 2207 (int)O32TOH(sed->ed.ed_headp), 2208 (int)O32TOH(sed->ed.ed_tailp), 2209 pipe, std); 2210 #ifdef OHCI_DEBUG 2211 usbd_dump_pipe(&opipe->pipe); 2212 ohci_dump_ed(sc, sed); 2213 if (std) 2214 ohci_dump_td(sc, std); 2215 #endif 2216 usb_delay_ms(&sc->sc_bus, 2); 2217 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2218 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2219 printf("ohci_close_pipe: pipe still not empty\n"); 2220 } 2221 #endif 2222 ohci_rem_ed(sc, sed, head); 2223 /* Make sure the host controller is not touching this ED */ 2224 usb_delay_ms(&sc->sc_bus, 1); 2225 pipe->up_endpoint->ue_toggle = 2226 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2227 ohci_free_sed_locked(sc, opipe->sed); 2228 } 2229 2230 /* 2231 * Arrange for the hardware to tells us that it is not still processing 2232 * the TDs by setting the sKip bit and requesting a SOF interrupt 2233 * 2234 * Once we see the SOF interrupt we can check the transfer TDs/iTDs to see if 2235 * they've been processed and either 2236 * a) if they're unused recover them for later use, or 2237 * b) if they've been used allocate new TD/iTDs to replace those 2238 * used. The softint handler will free the old ones. 2239 */ 2240 void 2241 ohci_abortx(struct usbd_xfer *xfer) 2242 { 2243 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2244 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2245 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2246 ohci_soft_ed_t *sed = opipe->sed; 2247 ohci_soft_td_t *p, *n; 2248 ohci_physaddr_t headp; 2249 int hit; 2250 2251 DPRINTF("xfer=%#jx pipe=%#jx sed=%#jx", (uintptr_t)xfer, 2252 (uintptr_t)opipe, (uintptr_t)sed, 0); 2253 2254 KASSERT(mutex_owned(&sc->sc_lock)); 2255 ASSERT_SLEEPABLE(); 2256 2257 KASSERTMSG((xfer->ux_status == USBD_CANCELLED || 2258 xfer->ux_status == USBD_TIMEOUT), 2259 "bad abort status: %d", xfer->ux_status); 2260 2261 /* 2262 * If we're dying, skip the hardware action and just notify the 2263 * software that we're done. 2264 */ 2265 if (sc->sc_dying) { 2266 DPRINTFN(4, "xfer %#jx dying %ju", (uintptr_t)xfer, 2267 xfer->ux_status, 0, 0); 2268 goto dying; 2269 } 2270 2271 /* 2272 * HC Step 1: Unless the endpoint is already halted, we set the 2273 * endpoint descriptor sKip bit and wait for hardware to complete 2274 * processing. We ensure the HC stops processing the endpoint by 2275 * waiting for the next start of frame (OHCI_SF) 2276 */ 2277 DPRINTFN(1, "stop ed=%#jx", (uintptr_t)sed, 0, 0, 0); 2278 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2279 sizeof(sed->ed.ed_flags), 2280 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2281 if (!(sed->ed.ed_flags & OHCI_HALTED)) { 2282 /* force hardware skip */ 2283 DPRINTFN(1, "pausing ed=%#jx", (uintptr_t)sed, 0, 0, 0); 2284 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2285 usb_syncmem(&sed->dma, 2286 sed->offs + offsetof(ohci_ed_t, ed_flags), 2287 sizeof(sed->ed.ed_flags), 2288 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2289 2290 DPRINTFN(10, "SF %#jx xfer %#jx", (uintptr_t)sc, 2291 (uintptr_t)xfer, 0, 0); 2292 2293 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2294 ox->ox_abintrs = OHCI_SF; 2295 2296 mutex_enter(&sc->sc_intr_lock); 2297 TAILQ_INSERT_TAIL(&sc->sc_abortingxfers, ox, ox_abnext); 2298 2299 /* Clear any previous SF interrupt */ 2300 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_SF); 2301 2302 /* Tell interrupt handler and HC SF interrupt is requested */ 2303 sc->sc_eintrs |= OHCI_SF; 2304 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_SF); 2305 /* 2306 * Step 2: Wait until we know hardware has finished any 2307 * processing of the end-point. 2308 */ 2309 while (ox->ox_abintrs != 0) { 2310 DPRINTFN(10, "SF %#jx xfer %#jx intrs %#x", 2311 (uintptr_t)sc, (uintptr_t)xfer, 2312 (uintptr_t)ox->ox_abintrs, 0); 2313 cv_wait(&sc->sc_abort_cv, &sc->sc_intr_lock); 2314 } 2315 mutex_exit(&sc->sc_intr_lock); 2316 } else { 2317 DPRINTFN(1, "halted ed=%#jx", (uintptr_t)sed, 0, 0, 0); 2318 } 2319 2320 /* 2321 * HC Step 3: Remove any vestiges of the xfer from the hardware. 2322 * There are two complications here 2323 * 2324 * 1) the hardware may have executed beyond the xfer we're trying to 2325 * abort. So as we're scanning the TDs of this xfer we check if 2326 * the hardware points to any of them. 2327 * 2328 * 2) the hardware may have only partially excuted the transfer 2329 * which means some TDs will appear on the done list. Wait for 2330 * WDH so we can remove them safely. 2331 */ 2332 p = xfer->ux_hcpriv; 2333 KASSERT(p); 2334 2335 #ifdef OHCI_DEBUG 2336 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2337 2338 if (ohcidebug >= 2) { 2339 DPRINTF("sed:", 0, 0, 0, 0); 2340 ohci_dump_ed(sc, sed); 2341 ohci_dump_tds(sc, p); 2342 } 2343 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2344 #endif 2345 2346 2347 #define OHCI_CC_ACCESSED_P(x) \ 2348 (((x) & OHCI_CC_NOT_ACCESSED_MASK) != OHCI_CC_NOT_ACCESSED) 2349 2350 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2351 hit = 0; 2352 for (; p->xfer == xfer; p = n) { 2353 hit |= headp == p->physaddr; 2354 n = p->nexttd; 2355 2356 int cc = OHCI_TD_GET_CC(O32TOH(p->td.td_flags)); 2357 if (!OHCI_CC_ACCESSED_P(cc)) { 2358 ohci_hash_rem_td(sc, p); 2359 continue; 2360 } 2361 DPRINTFN(10, "xfer=%#jx has been touched by HC", (uintptr_t)p, 2362 0, 0, 0); 2363 2364 mutex_exit(&sc->sc_lock); 2365 ohci_soft_td_t *std; 2366 for (;;) { 2367 std = ohci_alloc_std(sc); 2368 if (std) 2369 break; 2370 kpause("ohciabt2", true, hz, NULL); 2371 } 2372 2373 mutex_enter(&sc->sc_lock); 2374 if (sc->sc_dying) { 2375 DPRINTFN(4, "xfer %#jx dying %ju", (uintptr_t)xfer, 2376 xfer->ux_status, 0, 0); 2377 goto dying; 2378 } 2379 2380 DPRINTFN(10, "new std=%#jx now held at %#jx", (uintptr_t)std, 2381 (uintptr_t)p->held, 0, 0); 2382 *(p->held) = std; 2383 std->held = p->held; 2384 std->xfer = xfer; 2385 p->held = NULL; 2386 } 2387 /* Zap headp register if hardware pointed inside the xfer. */ 2388 if (hit) { 2389 DPRINTFN(1, "set hd=0x%08jx, tl=0x%08jx", (int)p->physaddr, 2390 (int)O32TOH(sed->ed.ed_tailp), 0, 0); 2391 /* unlink TDs, preserving toggle carry */ 2392 sed->ed.ed_headp = HTOO32(p->physaddr | 2393 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 2394 usb_syncmem(&sed->dma, 2395 sed->offs + offsetof(ohci_ed_t, ed_headp), 2396 sizeof(sed->ed.ed_headp), 2397 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2398 } else { 2399 DPRINTFN(1, "no hit", 0, 0, 0, 0); 2400 } 2401 2402 /* 2403 * HC Step 4: Turn on hardware again. 2404 */ 2405 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2406 sizeof(sed->ed.ed_flags), 2407 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2408 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2409 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2410 sizeof(sed->ed.ed_flags), 2411 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2412 2413 /* 2414 * Final step: Notify completion to waiting xfers. 2415 */ 2416 dying: 2417 usb_transfer_complete(xfer); 2418 DPRINTFN(14, "end", 0, 0, 0, 0); 2419 2420 KASSERT(mutex_owned(&sc->sc_lock)); 2421 } 2422 2423 /* 2424 * Data structures and routines to emulate the root hub. 2425 */ 2426 Static int 2427 ohci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2428 void *buf, int buflen) 2429 { 2430 ohci_softc_t *sc = OHCI_BUS2SC(bus); 2431 usb_port_status_t ps; 2432 uint16_t len, value, index; 2433 int l, totlen = 0; 2434 int port, i; 2435 uint32_t v; 2436 2437 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2438 2439 if (sc->sc_dying) 2440 return -1; 2441 2442 DPRINTFN(4, "type=0x%02jx request=%02jx", req->bmRequestType, 2443 req->bRequest, 0, 0); 2444 2445 len = UGETW(req->wLength); 2446 value = UGETW(req->wValue); 2447 index = UGETW(req->wIndex); 2448 2449 #define C(x,y) ((x) | ((y) << 8)) 2450 switch (C(req->bRequest, req->bmRequestType)) { 2451 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2452 DPRINTFN(8, "wValue=0x%04jx", value, 0, 0, 0); 2453 if (len == 0) 2454 break; 2455 switch (value) { 2456 #define sd ((usb_string_descriptor_t *)buf) 2457 case C(2, UDESC_STRING): 2458 /* Product */ 2459 totlen = usb_makestrdesc(sd, len, "OHCI root hub"); 2460 break; 2461 #undef sd 2462 default: 2463 /* default from usbroothub */ 2464 return buflen; 2465 } 2466 break; 2467 2468 /* Hub requests */ 2469 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2470 break; 2471 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2472 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", 2473 index, value, 0, 0); 2474 if (index < 1 || index > sc->sc_noport) { 2475 return -1; 2476 } 2477 port = OHCI_RH_PORT_STATUS(index); 2478 switch(value) { 2479 case UHF_PORT_ENABLE: 2480 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2481 break; 2482 case UHF_PORT_SUSPEND: 2483 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2484 break; 2485 case UHF_PORT_POWER: 2486 /* Yes, writing to the LOW_SPEED bit clears power. */ 2487 OWRITE4(sc, port, UPS_LOW_SPEED); 2488 break; 2489 case UHF_C_PORT_CONNECTION: 2490 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2491 break; 2492 case UHF_C_PORT_ENABLE: 2493 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2494 break; 2495 case UHF_C_PORT_SUSPEND: 2496 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2497 break; 2498 case UHF_C_PORT_OVER_CURRENT: 2499 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2500 break; 2501 case UHF_C_PORT_RESET: 2502 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2503 break; 2504 default: 2505 return -1; 2506 } 2507 switch(value) { 2508 case UHF_C_PORT_CONNECTION: 2509 case UHF_C_PORT_ENABLE: 2510 case UHF_C_PORT_SUSPEND: 2511 case UHF_C_PORT_OVER_CURRENT: 2512 case UHF_C_PORT_RESET: 2513 /* Enable RHSC interrupt if condition is cleared. */ 2514 if ((OREAD4(sc, port) >> 16) == 0) 2515 ohci_rhsc_enable(sc); 2516 break; 2517 default: 2518 break; 2519 } 2520 break; 2521 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2522 if (len == 0) 2523 break; 2524 if ((value & 0xff) != 0) { 2525 return -1; 2526 } 2527 usb_hub_descriptor_t hubd; 2528 2529 totlen = uimin(buflen, sizeof(hubd)); 2530 memcpy(&hubd, buf, totlen); 2531 2532 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2533 hubd.bNbrPorts = sc->sc_noport; 2534 USETW(hubd.wHubCharacteristics, 2535 (v & OHCI_RHD_NPS ? UHD_PWR_NO_SWITCH : 2536 v & OHCI_RHD_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2537 /* XXX overcurrent */ 2538 ); 2539 hubd.bPwrOn2PwrGood = OHCI_RHD_GET_POTPGT(v); 2540 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2541 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2542 hubd.DeviceRemovable[i++] = (uint8_t)v; 2543 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2544 totlen = uimin(totlen, hubd.bDescLength); 2545 memcpy(buf, &hubd, totlen); 2546 break; 2547 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2548 if (len != 4) { 2549 return -1; 2550 } 2551 memset(buf, 0, len); /* ? XXX */ 2552 totlen = len; 2553 break; 2554 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2555 DPRINTFN(8, "get port status i=%jd", index, 0, 0, 0); 2556 if (index < 1 || index > sc->sc_noport) { 2557 return -1; 2558 } 2559 if (len != 4) { 2560 return -1; 2561 } 2562 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2563 DPRINTFN(8, "port status=0x%04jx", v, 0, 0, 0); 2564 USETW(ps.wPortStatus, v); 2565 USETW(ps.wPortChange, v >> 16); 2566 totlen = uimin(len, sizeof(ps)); 2567 memcpy(buf, &ps, totlen); 2568 break; 2569 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2570 return -1; 2571 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2572 break; 2573 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2574 if (index < 1 || index > sc->sc_noport) { 2575 return -1; 2576 } 2577 port = OHCI_RH_PORT_STATUS(index); 2578 switch(value) { 2579 case UHF_PORT_ENABLE: 2580 OWRITE4(sc, port, UPS_PORT_ENABLED); 2581 break; 2582 case UHF_PORT_SUSPEND: 2583 OWRITE4(sc, port, UPS_SUSPEND); 2584 break; 2585 case UHF_PORT_RESET: 2586 DPRINTFN(5, "reset port %jd", index, 0, 0, 0); 2587 OWRITE4(sc, port, UPS_RESET); 2588 for (i = 0; i < 5; i++) { 2589 usb_delay_ms(&sc->sc_bus, 2590 USB_PORT_ROOT_RESET_DELAY); 2591 if (sc->sc_dying) { 2592 return -1; 2593 } 2594 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2595 break; 2596 } 2597 DPRINTFN(8, "port %jd reset, status = 0x%04jx", index, 2598 OREAD4(sc, port), 0, 0); 2599 break; 2600 case UHF_PORT_POWER: 2601 DPRINTFN(2, "set port power %jd", index, 0, 0, 0); 2602 OWRITE4(sc, port, UPS_PORT_POWER); 2603 break; 2604 default: 2605 return -1; 2606 } 2607 break; 2608 default: 2609 /* default from usbroothub */ 2610 return buflen; 2611 } 2612 2613 return totlen; 2614 } 2615 2616 Static usbd_status 2617 ohci_root_intr_transfer(struct usbd_xfer *xfer) 2618 { 2619 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2620 usbd_status err; 2621 2622 /* Insert last in queue. */ 2623 mutex_enter(&sc->sc_lock); 2624 err = usb_insert_transfer(xfer); 2625 mutex_exit(&sc->sc_lock); 2626 if (err) 2627 return err; 2628 2629 /* Pipe isn't running, start first */ 2630 return ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2631 } 2632 2633 Static usbd_status 2634 ohci_root_intr_start(struct usbd_xfer *xfer) 2635 { 2636 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2637 const bool polling = sc->sc_bus.ub_usepolling; 2638 2639 if (sc->sc_dying) 2640 return USBD_IOERROR; 2641 2642 if (!polling) 2643 mutex_enter(&sc->sc_lock); 2644 KASSERT(sc->sc_intrxfer == NULL); 2645 sc->sc_intrxfer = xfer; 2646 xfer->ux_status = USBD_IN_PROGRESS; 2647 if (!polling) 2648 mutex_exit(&sc->sc_lock); 2649 2650 return USBD_IN_PROGRESS; 2651 } 2652 2653 /* Abort a root interrupt request. */ 2654 Static void 2655 ohci_root_intr_abort(struct usbd_xfer *xfer) 2656 { 2657 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2658 2659 KASSERT(mutex_owned(&sc->sc_lock)); 2660 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2661 2662 /* If xfer has already completed, nothing to do here. */ 2663 if (sc->sc_intrxfer == NULL) 2664 return; 2665 2666 /* 2667 * Otherwise, sc->sc_intrxfer had better be this transfer. 2668 * Cancel it. 2669 */ 2670 KASSERT(sc->sc_intrxfer == xfer); 2671 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 2672 xfer->ux_status = USBD_CANCELLED; 2673 usb_transfer_complete(xfer); 2674 } 2675 2676 /* Close the root pipe. */ 2677 Static void 2678 ohci_root_intr_close(struct usbd_pipe *pipe) 2679 { 2680 ohci_softc_t *sc __diagused = OHCI_PIPE2SC(pipe); 2681 2682 KASSERT(mutex_owned(&sc->sc_lock)); 2683 2684 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2685 2686 /* 2687 * Caller must guarantee the xfer has completed first, by 2688 * closing the pipe only after normal completion or an abort. 2689 */ 2690 KASSERT(sc->sc_intrxfer == NULL); 2691 } 2692 2693 /************************/ 2694 2695 int 2696 ohci_device_ctrl_init(struct usbd_xfer *xfer) 2697 { 2698 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2699 usb_device_request_t *req = &xfer->ux_request; 2700 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2701 ohci_soft_td_t *stat, *setup; 2702 int isread = req->bmRequestType & UT_READ; 2703 int len = xfer->ux_bufsize; 2704 int err = ENOMEM; 2705 2706 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2707 2708 setup = ohci_alloc_std(sc); 2709 if (setup == NULL) { 2710 goto bad1; 2711 } 2712 stat = ohci_alloc_std(sc); 2713 if (stat == NULL) { 2714 goto bad2; 2715 } 2716 2717 ox->ox_setup = setup; 2718 ox->ox_stat = stat; 2719 ox->ox_nstd = 0; 2720 setup->held = &ox->ox_setup; 2721 stat->held = &ox->ox_stat; 2722 2723 DPRINTFN(10, "xfer=%#jx setup=%#jx held at %#jx", (uintptr_t)ox, 2724 (uintptr_t)setup, (uintptr_t)setup->held, 0); 2725 DPRINTFN(10, "xfer=%#jx stat= %#jx held at %#jx", (uintptr_t)ox, 2726 (uintptr_t)stat, (uintptr_t)stat->held, 0); 2727 2728 /* Set up data transaction */ 2729 if (len != 0) { 2730 err = ohci_alloc_std_chain(sc, xfer, len, isread); 2731 if (err) { 2732 goto bad3; 2733 } 2734 } 2735 return 0; 2736 2737 bad3: 2738 ohci_free_std(sc, stat); 2739 bad2: 2740 ohci_free_std(sc, setup); 2741 bad1: 2742 return err; 2743 } 2744 2745 void 2746 ohci_device_ctrl_fini(struct usbd_xfer *xfer) 2747 { 2748 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2749 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2750 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2751 2752 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2753 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 2754 2755 mutex_enter(&sc->sc_lock); 2756 if (ox->ox_setup != opipe->tail.td) { 2757 ohci_free_std_locked(sc, ox->ox_setup); 2758 } 2759 for (size_t i = 0; i < ox->ox_nstd; i++) { 2760 ohci_soft_td_t *std = ox->ox_stds[i]; 2761 if (std == NULL) 2762 break; 2763 ohci_free_std_locked(sc, std); 2764 } 2765 ohci_free_std_locked(sc, ox->ox_stat); 2766 mutex_exit(&sc->sc_lock); 2767 2768 if (ox->ox_nstd) { 2769 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 2770 kmem_free(ox->ox_stds, sz); 2771 } 2772 } 2773 2774 Static usbd_status 2775 ohci_device_ctrl_transfer(struct usbd_xfer *xfer) 2776 { 2777 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2778 usbd_status err; 2779 2780 /* Insert last in queue. */ 2781 mutex_enter(&sc->sc_lock); 2782 err = usb_insert_transfer(xfer); 2783 mutex_exit(&sc->sc_lock); 2784 if (err) 2785 return err; 2786 2787 /* Pipe isn't running, start first */ 2788 return ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2789 } 2790 2791 Static usbd_status 2792 ohci_device_ctrl_start(struct usbd_xfer *xfer) 2793 { 2794 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2795 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2796 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2797 usb_device_request_t *req = &xfer->ux_request; 2798 struct usbd_device *dev __diagused = opipe->pipe.up_dev; 2799 ohci_soft_td_t *setup, *stat, *next, *tail; 2800 ohci_soft_ed_t *sed; 2801 int isread; 2802 int len; 2803 const bool polling = sc->sc_bus.ub_usepolling; 2804 2805 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2806 2807 if (sc->sc_dying) 2808 return USBD_IOERROR; 2809 2810 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2811 2812 isread = req->bmRequestType & UT_READ; 2813 len = UGETW(req->wLength); 2814 2815 DPRINTF("xfer=%#jx len=%jd, addr=%jd, endpt=%jd", (uintptr_t)xfer, len, 2816 dev->ud_addr, opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress); 2817 DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx", 2818 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2819 UGETW(req->wIndex)); 2820 2821 /* Need to take lock here for pipe->tail.td */ 2822 if (!polling) 2823 mutex_enter(&sc->sc_lock); 2824 2825 /* 2826 * Use the pipe "tail" TD as our first and loan our first TD to the 2827 * next transfer 2828 */ 2829 setup = opipe->tail.td; 2830 opipe->tail.td = ox->ox_setup; 2831 ox->ox_setup = setup; 2832 setup->held = &ox->ox_setup; 2833 2834 DPRINTFN(10, "xfer=%#jx new setup=%#jx held at %#jx", (uintptr_t)ox, 2835 (uintptr_t)setup, (uintptr_t)setup->held, 0); 2836 2837 stat = ox->ox_stat; 2838 2839 /* point at sentinel */ 2840 tail = opipe->tail.td; 2841 tail->held = &opipe->tail.td; 2842 sed = opipe->sed; 2843 2844 DPRINTFN(10, "xfer=%#jx new tail=%#jx held at %#jx", (uintptr_t)ox, 2845 (uintptr_t)tail, (uintptr_t)tail->held, 0); 2846 2847 KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->ud_addr, 2848 "address ED %" __PRIuBITS " pipe %d\n", 2849 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->ud_addr); 2850 KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) == 2851 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 2852 "MPL ED %" __PRIuBITS " pipe %d\n", 2853 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), 2854 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 2855 2856 /* next will point to data if len != 0 */ 2857 next = stat; 2858 2859 /* Set up data transaction */ 2860 if (len != 0) { 2861 ohci_soft_td_t *std; 2862 ohci_soft_td_t *end; 2863 2864 next = ox->ox_stds[0]; 2865 ohci_reset_std_chain(sc, xfer, len, isread, next, &end); 2866 2867 end->td.td_nexttd = HTOO32(stat->physaddr); 2868 end->nexttd = stat; 2869 2870 usb_syncmem(&end->dma, end->offs, sizeof(end->td), 2871 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2872 2873 usb_syncmem(&xfer->ux_dmabuf, 0, len, 2874 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2875 std = ox->ox_stds[0]; 2876 /* Start toggle at 1 and then use the carried toggle. */ 2877 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 2878 std->td.td_flags |= HTOO32(OHCI_TD_SET_TOGGLE(OHCI_TD_TOGGLE_1)); 2879 usb_syncmem(&std->dma, 2880 std->offs + offsetof(ohci_td_t, td_flags), 2881 sizeof(std->td.td_flags), 2882 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2883 } 2884 2885 DPRINTFN(8, "setup %#jx data %#jx stat %#jx tail %#jx", 2886 (uintptr_t)setup, 2887 (uintptr_t)(len != 0 ? ox->ox_stds[0] : NULL), (uintptr_t)stat, 2888 (uintptr_t)tail); 2889 KASSERT(opipe->tail.td == tail); 2890 2891 memcpy(KERNADDR(&opipe->ctrl.reqdma, 0), req, sizeof(*req)); 2892 usb_syncmem(&opipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2893 2894 setup->td.td_flags = HTOO32( 2895 OHCI_TD_SET_DP(OHCI_TD_DP_SETUP) | 2896 OHCI_TD_SET_CC(OHCI_TD_NOCC) | 2897 OHCI_TD_SET_TOGGLE(OHCI_TD_TOGGLE_0) | 2898 OHCI_TD_SET_DI(OHCI_TD_NOINTR) 2899 ); 2900 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->ctrl.reqdma, 0)); 2901 setup->td.td_nexttd = HTOO32(next->physaddr); 2902 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof(*req) - 1); 2903 setup->nexttd = next; 2904 setup->len = 0; 2905 setup->xfer = xfer; 2906 setup->flags = 0; 2907 ohci_hash_add_td(sc, setup); 2908 2909 xfer->ux_hcpriv = setup; 2910 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2911 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2912 2913 stat->td.td_flags = HTOO32( 2914 OHCI_TD_SET_DP(isread ? OHCI_TD_DP_OUT : OHCI_TD_DP_IN) | 2915 OHCI_TD_SET_CC(OHCI_TD_NOCC) | 2916 OHCI_TD_SET_TOGGLE(OHCI_TD_TOGGLE_1) | 2917 OHCI_TD_SET_DI(1) 2918 ); 2919 stat->td.td_cbp = 0; 2920 stat->td.td_nexttd = HTOO32(tail->physaddr); 2921 stat->td.td_be = 0; 2922 stat->nexttd = tail; 2923 stat->flags = OHCI_CALL_DONE; 2924 stat->len = 0; 2925 stat->xfer = xfer; 2926 ohci_hash_add_td(sc, stat); 2927 2928 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2929 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2930 2931 memset(&tail->td, 0, sizeof(tail->td)); 2932 tail->nexttd = NULL; 2933 tail->xfer = NULL; 2934 2935 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 2936 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2937 2938 #ifdef OHCI_DEBUG 2939 USBHIST_LOGN(ohcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2940 if (ohcidebug >= 5) { 2941 ohci_dump_ed(sc, sed); 2942 ohci_dump_tds(sc, setup); 2943 } 2944 USBHIST_LOGN(ohcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2945 #endif 2946 2947 /* Insert ED in schedule */ 2948 sed->ed.ed_tailp = HTOO32(tail->physaddr); 2949 usb_syncmem(&sed->dma, 2950 sed->offs + offsetof(ohci_ed_t, ed_tailp), 2951 sizeof(sed->ed.ed_tailp), 2952 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2953 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2954 usbd_xfer_schedule_timeout(xfer); 2955 2956 DPRINTF("done", 0, 0, 0, 0); 2957 2958 xfer->ux_status = USBD_IN_PROGRESS; 2959 if (!polling) 2960 mutex_exit(&sc->sc_lock); 2961 2962 return USBD_IN_PROGRESS; 2963 } 2964 2965 /* Abort a device control request. */ 2966 Static void 2967 ohci_device_ctrl_abort(struct usbd_xfer *xfer) 2968 { 2969 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 2970 2971 KASSERT(mutex_owned(&sc->sc_lock)); 2972 2973 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2974 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 2975 usbd_xfer_abort(xfer); 2976 } 2977 2978 /* Close a device control pipe. */ 2979 Static void 2980 ohci_device_ctrl_close(struct usbd_pipe *pipe) 2981 { 2982 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2983 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2984 2985 KASSERT(mutex_owned(&sc->sc_lock)); 2986 2987 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2988 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 2989 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2990 ohci_free_std_locked(sc, opipe->tail.td); 2991 2992 usb_freemem(&sc->sc_bus, &opipe->ctrl.reqdma); 2993 } 2994 2995 /************************/ 2996 2997 Static void 2998 ohci_device_clear_toggle(struct usbd_pipe *pipe) 2999 { 3000 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3001 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3002 3003 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 3004 } 3005 3006 Static void 3007 ohci_noop(struct usbd_pipe *pipe) 3008 { 3009 } 3010 3011 Static int 3012 ohci_device_bulk_init(struct usbd_xfer *xfer) 3013 { 3014 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3015 int len = xfer->ux_bufsize; 3016 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3017 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3018 int err; 3019 3020 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3021 3022 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3023 3024 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 3025 len, isread, xfer->ux_flags); 3026 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 3027 3028 /* Allocate a chain of new TDs (including a new tail). */ 3029 err = ohci_alloc_std_chain(sc, xfer, len, isread); 3030 if (err) 3031 return err; 3032 3033 return 0; 3034 } 3035 3036 Static void 3037 ohci_device_bulk_fini(struct usbd_xfer *xfer) 3038 { 3039 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3040 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3041 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3042 3043 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3044 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 3045 3046 mutex_enter(&sc->sc_lock); 3047 for (size_t i = 0; i < ox->ox_nstd; i++) { 3048 ohci_soft_td_t *std = ox->ox_stds[i]; 3049 if (std == NULL) 3050 break; 3051 if (std != opipe->tail.td) 3052 ohci_free_std_locked(sc, std); 3053 } 3054 mutex_exit(&sc->sc_lock); 3055 3056 if (ox->ox_nstd) { 3057 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 3058 kmem_free(ox->ox_stds, sz); 3059 } 3060 } 3061 3062 Static usbd_status 3063 ohci_device_bulk_transfer(struct usbd_xfer *xfer) 3064 { 3065 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3066 usbd_status err; 3067 3068 /* Insert last in queue. */ 3069 mutex_enter(&sc->sc_lock); 3070 err = usb_insert_transfer(xfer); 3071 mutex_exit(&sc->sc_lock); 3072 if (err) 3073 return err; 3074 3075 /* Pipe isn't running, start first */ 3076 return ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3077 } 3078 3079 Static usbd_status 3080 ohci_device_bulk_start(struct usbd_xfer *xfer) 3081 { 3082 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3083 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3084 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3085 ohci_soft_td_t *last; 3086 ohci_soft_td_t *data, *tail, *tdp; 3087 ohci_soft_ed_t *sed; 3088 int len, isread, endpt; 3089 const bool polling = sc->sc_bus.ub_usepolling; 3090 3091 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3092 3093 if (sc->sc_dying) 3094 return USBD_IOERROR; 3095 3096 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3097 3098 len = xfer->ux_length; 3099 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3100 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3101 sed = opipe->sed; 3102 3103 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 3104 len, isread, xfer->ux_flags); 3105 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 3106 3107 if (!polling) 3108 mutex_enter(&sc->sc_lock); 3109 3110 /* 3111 * Use the pipe "tail" TD as our first and loan our first TD to the 3112 * next transfer 3113 */ 3114 data = opipe->tail.td; 3115 opipe->tail.td = ox->ox_stds[0]; 3116 ox->ox_stds[0] = data; 3117 data->held = &ox->ox_stds[0]; 3118 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3119 DPRINTFN(10, "xfer=%#jx new data=%#jx held at %#jx", 3120 (uintptr_t)ox, (uintptr_t)data, (uintptr_t)data->held, 0); 3121 3122 /* point at sentinel */ 3123 tail = opipe->tail.td; 3124 memset(&tail->td, 0, sizeof(tail->td)); 3125 tail->held = &opipe->tail.td; 3126 tail->nexttd = NULL; 3127 tail->xfer = NULL; 3128 DPRINTFN(10, "xfer=%#jx new tail=%#jx held at %#ux", 3129 (uintptr_t)ox, (uintptr_t)tail, (uintptr_t)tail->held, 0); 3130 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3131 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3132 xfer->ux_hcpriv = data; 3133 3134 DPRINTFN(8, "xfer %#jx data %#jx tail %#jx", (uintptr_t)xfer, 3135 (uintptr_t)ox->ox_stds[0], (uintptr_t)tail, 0); 3136 KASSERT(opipe->tail.td == tail); 3137 3138 /* We want interrupt at the end of the transfer. */ 3139 last->td.td_flags &= HTOO32(~OHCI_TD_DI_MASK); 3140 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3141 last->td.td_nexttd = HTOO32(tail->physaddr); 3142 last->nexttd = tail; 3143 last->flags |= OHCI_CALL_DONE; 3144 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3145 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3146 3147 DPRINTFN(4, "ed_flags=0x%08jx td_flags=0x%08jx " 3148 "td_cbp=0x%08jx td_be=0x%08jx", 3149 (int)O32TOH(sed->ed.ed_flags), 3150 (int)O32TOH(data->td.td_flags), 3151 (int)O32TOH(data->td.td_cbp), 3152 (int)O32TOH(data->td.td_be)); 3153 3154 #ifdef OHCI_DEBUG 3155 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3156 if (ohcidebug >= 5) { 3157 ohci_dump_ed(sc, sed); 3158 ohci_dump_tds(sc, data); 3159 } 3160 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3161 #endif 3162 3163 /* Insert ED in schedule */ 3164 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3165 KASSERT(tdp->xfer == xfer); 3166 } 3167 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3168 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3169 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3170 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3171 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3172 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3173 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3174 usbd_xfer_schedule_timeout(xfer); 3175 xfer->ux_status = USBD_IN_PROGRESS; 3176 if (!polling) 3177 mutex_exit(&sc->sc_lock); 3178 3179 return USBD_IN_PROGRESS; 3180 } 3181 3182 Static void 3183 ohci_device_bulk_abort(struct usbd_xfer *xfer) 3184 { 3185 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3186 3187 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3188 3189 KASSERT(mutex_owned(&sc->sc_lock)); 3190 3191 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3192 usbd_xfer_abort(xfer); 3193 } 3194 3195 /* 3196 * Close a device bulk pipe. 3197 */ 3198 Static void 3199 ohci_device_bulk_close(struct usbd_pipe *pipe) 3200 { 3201 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3202 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3203 3204 KASSERT(mutex_owned(&sc->sc_lock)); 3205 3206 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3207 3208 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3209 ohci_close_pipe(pipe, sc->sc_bulk_head); 3210 ohci_free_std_locked(sc, opipe->tail.td); 3211 } 3212 3213 /************************/ 3214 3215 Static int 3216 ohci_device_intr_init(struct usbd_xfer *xfer) 3217 { 3218 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3219 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3220 int len = xfer->ux_bufsize; 3221 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3222 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3223 int err; 3224 3225 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3226 3227 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3228 KASSERT(len != 0); 3229 3230 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 3231 len, isread, xfer->ux_flags); 3232 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 3233 3234 ox->ox_nstd = 0; 3235 3236 err = ohci_alloc_std_chain(sc, xfer, len, isread); 3237 if (err) { 3238 return err; 3239 } 3240 3241 return 0; 3242 } 3243 3244 Static void 3245 ohci_device_intr_fini(struct usbd_xfer *xfer) 3246 { 3247 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3248 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3249 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3250 3251 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3252 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 3253 3254 mutex_enter(&sc->sc_lock); 3255 for (size_t i = 0; i < ox->ox_nstd; i++) { 3256 ohci_soft_td_t *std = ox->ox_stds[i]; 3257 if (std != NULL) 3258 break; 3259 if (std != opipe->tail.td) 3260 ohci_free_std_locked(sc, std); 3261 } 3262 mutex_exit(&sc->sc_lock); 3263 3264 if (ox->ox_nstd) { 3265 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 3266 kmem_free(ox->ox_stds, sz); 3267 } 3268 } 3269 3270 Static usbd_status 3271 ohci_device_intr_transfer(struct usbd_xfer *xfer) 3272 { 3273 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3274 usbd_status err; 3275 3276 /* Insert last in queue. */ 3277 mutex_enter(&sc->sc_lock); 3278 err = usb_insert_transfer(xfer); 3279 mutex_exit(&sc->sc_lock); 3280 if (err) 3281 return err; 3282 3283 /* Pipe isn't running, start first */ 3284 return ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3285 } 3286 3287 Static usbd_status 3288 ohci_device_intr_start(struct usbd_xfer *xfer) 3289 { 3290 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3291 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3292 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3293 ohci_soft_ed_t *sed = opipe->sed; 3294 ohci_soft_td_t *data, *last, *tail; 3295 int len, isread, endpt; 3296 const bool polling = sc->sc_bus.ub_usepolling; 3297 3298 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3299 3300 if (sc->sc_dying) 3301 return USBD_IOERROR; 3302 3303 DPRINTFN(3, "xfer=%#jx len=%jd flags=%jd priv=%#jx", (uintptr_t)xfer, 3304 xfer->ux_length, xfer->ux_flags, (uintptr_t)xfer->ux_priv); 3305 3306 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3307 3308 len = xfer->ux_length; 3309 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3310 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3311 3312 if (!polling) 3313 mutex_enter(&sc->sc_lock); 3314 3315 /* 3316 * Use the pipe "tail" TD as our first and loan our first TD to the 3317 * next transfer. 3318 */ 3319 data = opipe->tail.td; 3320 opipe->tail.td = ox->ox_stds[0]; 3321 ox->ox_stds[0] = data; 3322 data->held = &ox->ox_stds[0]; 3323 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3324 DPRINTFN(10, "xfer=%#jx new data=%#jx held at %#jx", 3325 (uintptr_t)ox, (uintptr_t)data, (uintptr_t)data->held, 0); 3326 3327 /* point at sentinel */ 3328 tail = opipe->tail.td; 3329 memset(&tail->td, 0, sizeof(tail->td)); 3330 tail->held = &opipe->tail.td; 3331 tail->nexttd = NULL; 3332 tail->xfer = NULL; 3333 DPRINTFN(10, "xfer=%#jx new tail=%#jx held at %#jx", 3334 (uintptr_t)ox, (uintptr_t)tail, (uintptr_t)tail->held, 0); 3335 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3336 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3337 xfer->ux_hcpriv = data; 3338 3339 DPRINTFN(8, "data %#jx tail %#jx", (uintptr_t)ox->ox_stds[0], 3340 (uintptr_t)tail, 0, 0); 3341 KASSERT(opipe->tail.td == tail); 3342 3343 /* We want interrupt at the end of the transfer. */ 3344 last->td.td_flags &= HTOO32(~OHCI_TD_DI_MASK); 3345 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3346 3347 last->td.td_nexttd = HTOO32(tail->physaddr); 3348 last->nexttd = tail; 3349 last->flags |= OHCI_CALL_DONE; 3350 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3351 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3352 3353 #ifdef OHCI_DEBUG 3354 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3355 if (ohcidebug >= 5) { 3356 ohci_dump_ed(sc, sed); 3357 ohci_dump_tds(sc, data); 3358 } 3359 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3360 #endif 3361 3362 /* Insert ED in schedule */ 3363 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3364 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3365 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3366 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3367 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3368 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3369 3370 xfer->ux_status = USBD_IN_PROGRESS; 3371 if (!polling) 3372 mutex_exit(&sc->sc_lock); 3373 3374 return USBD_IN_PROGRESS; 3375 } 3376 3377 /* Abort a device interrupt request. */ 3378 Static void 3379 ohci_device_intr_abort(struct usbd_xfer *xfer) 3380 { 3381 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3382 3383 KASSERT(mutex_owned(&sc->sc_lock)); 3384 3385 usbd_xfer_abort(xfer); 3386 } 3387 3388 /* Close a device interrupt pipe. */ 3389 Static void 3390 ohci_device_intr_close(struct usbd_pipe *pipe) 3391 { 3392 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3393 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3394 int nslots = opipe->intr.nslots; 3395 int pos = opipe->intr.pos; 3396 int j; 3397 ohci_soft_ed_t *p, *sed = opipe->sed; 3398 3399 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3400 3401 KASSERT(mutex_owned(&sc->sc_lock)); 3402 3403 DPRINTFN(1, "pipe=%#jx nslots=%jd pos=%jd", (uintptr_t)pipe, nslots, 3404 pos, 0); 3405 usb_syncmem(&sed->dma, sed->offs, 3406 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3407 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3408 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3409 sizeof(sed->ed.ed_flags), 3410 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3411 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3412 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3413 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3414 3415 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3416 continue; 3417 KASSERT(p); 3418 p->next = sed->next; 3419 p->ed.ed_nexted = sed->ed.ed_nexted; 3420 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3421 sizeof(p->ed.ed_nexted), 3422 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3423 3424 for (j = 0; j < nslots; j++) 3425 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3426 3427 ohci_free_std_locked(sc, opipe->tail.td); 3428 ohci_free_sed_locked(sc, opipe->sed); 3429 } 3430 3431 Static usbd_status 3432 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3433 { 3434 int i, j, best; 3435 u_int npoll, slow, shigh, nslots; 3436 u_int bestbw, bw; 3437 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3438 3439 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3440 3441 DPRINTFN(2, "pipe=%#jx", (uintptr_t)opipe, 0, 0, 0); 3442 if (ival == 0) { 3443 printf("ohci_setintr: 0 interval\n"); 3444 return USBD_INVAL; 3445 } 3446 3447 npoll = OHCI_NO_INTRS; 3448 while (npoll > ival) 3449 npoll /= 2; 3450 DPRINTFN(2, "ival=%jd npoll=%jd", ival, npoll, 0, 0); 3451 3452 /* 3453 * We now know which level in the tree the ED must go into. 3454 * Figure out which slot has most bandwidth left over. 3455 * Slots to examine: 3456 * npoll 3457 * 1 0 3458 * 2 1 2 3459 * 4 3 4 5 6 3460 * 8 7 8 9 10 11 12 13 14 3461 * N (N-1) .. (N-1+N-1) 3462 */ 3463 slow = npoll-1; 3464 shigh = slow + npoll; 3465 nslots = OHCI_NO_INTRS / npoll; 3466 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3467 bw = 0; 3468 for (j = 0; j < nslots; j++) 3469 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3470 if (bw < bestbw) { 3471 best = i; 3472 bestbw = bw; 3473 } 3474 } 3475 DPRINTFN(2, "best=%jd(%jd..%jd) bestbw=%jd", best, slow, shigh, bestbw); 3476 3477 mutex_enter(&sc->sc_lock); 3478 hsed = sc->sc_eds[best]; 3479 sed->next = hsed->next; 3480 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3481 sizeof(hsed->ed.ed_flags), 3482 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3483 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3484 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3485 sizeof(sed->ed.ed_flags), 3486 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3487 hsed->next = sed; 3488 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3489 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3490 sizeof(hsed->ed.ed_flags), 3491 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3492 mutex_exit(&sc->sc_lock); 3493 3494 for (j = 0; j < nslots; j++) 3495 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3496 opipe->intr.nslots = nslots; 3497 opipe->intr.pos = best; 3498 3499 DPRINTFN(5, "returns %#jx", (uintptr_t)opipe, 0, 0, 0); 3500 return USBD_NORMAL_COMPLETION; 3501 } 3502 3503 /***********************/ 3504 3505 Static int 3506 ohci_device_isoc_init(struct usbd_xfer *xfer) 3507 { 3508 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3509 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3510 ohci_soft_itd_t *sitd; 3511 size_t i; 3512 int err; 3513 3514 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3515 3516 DPRINTFN(1, "xfer %#jx len %jd flags %jd", (uintptr_t)xfer, 3517 xfer->ux_length, xfer->ux_flags, 0); 3518 3519 const size_t nfsitd = howmany(xfer->ux_nframes, OHCI_ITD_NOFFSET); 3520 const size_t nbsitd = xfer->ux_bufsize / OHCI_PAGE_SIZE; 3521 const size_t nsitd = MAX(nfsitd, nbsitd) + 1; 3522 3523 ox->ox_sitds = kmem_zalloc(sizeof(ohci_soft_itd_t *) * nsitd, 3524 KM_SLEEP); 3525 ox->ox_nsitd = nsitd; 3526 3527 for (i = 0; i < nsitd; i++) { 3528 /* Allocate next ITD */ 3529 sitd = ohci_alloc_sitd(sc); 3530 if (sitd == NULL) { 3531 err = ENOMEM; 3532 goto fail; 3533 } 3534 ox->ox_sitds[i] = sitd; 3535 sitd->held = &ox->ox_sitds[i]; 3536 sitd->xfer = xfer; 3537 sitd->flags = 0; 3538 // DPRINTFN(10, "xfer=%#jx new tail=%#jx held at %#jx", 3539 // (uintptr_t)ox, (uintptr_t)tail, (uintptr_t)tail->held, 0); 3540 } 3541 3542 return 0; 3543 fail: 3544 for (; i > 0;) { 3545 ohci_free_sitd(sc, ox->ox_sitds[--i]); 3546 } 3547 return err; 3548 } 3549 3550 Static void 3551 ohci_device_isoc_fini(struct usbd_xfer *xfer) 3552 { 3553 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3554 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3555 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3556 3557 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3558 3559 mutex_enter(&sc->sc_lock); 3560 for (size_t i = 0; i < ox->ox_nsitd; i++) { 3561 if (ox->ox_sitds[i] != opipe->tail.itd) { 3562 ohci_free_sitd_locked(sc, ox->ox_sitds[i]); 3563 } 3564 } 3565 mutex_exit(&sc->sc_lock); 3566 3567 if (ox->ox_nsitd) { 3568 const size_t sz = sizeof(ohci_soft_itd_t *) * ox->ox_nsitd; 3569 kmem_free(ox->ox_sitds, sz); 3570 } 3571 } 3572 3573 3574 usbd_status 3575 ohci_device_isoc_transfer(struct usbd_xfer *xfer) 3576 { 3577 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3578 usbd_status __diagused err; 3579 3580 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3581 3582 DPRINTFN(5, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3583 3584 /* Put it on our queue, */ 3585 mutex_enter(&sc->sc_lock); 3586 err = usb_insert_transfer(xfer); 3587 mutex_exit(&sc->sc_lock); 3588 3589 KASSERT(err == USBD_NORMAL_COMPLETION); 3590 3591 /* insert into schedule, */ 3592 ohci_device_isoc_enter(xfer); 3593 3594 /* and start if the pipe wasn't running */ 3595 return USBD_IN_PROGRESS; 3596 } 3597 3598 void 3599 ohci_device_isoc_enter(struct usbd_xfer *xfer) 3600 { 3601 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3602 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3603 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3604 ohci_soft_ed_t *sed = opipe->sed; 3605 ohci_soft_itd_t *sitd, *nsitd, *tail; 3606 ohci_physaddr_t buf, offs, bp0, bp1; 3607 int i, ncur, nframes; 3608 size_t boff, frlen; 3609 3610 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3611 DPRINTFN(5, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3612 3613 mutex_enter(&sc->sc_lock); 3614 3615 if (sc->sc_dying) { 3616 mutex_exit(&sc->sc_lock); 3617 return; 3618 } 3619 3620 struct isoc *isoc = &opipe->isoc; 3621 3622 DPRINTFN(1, "used=%jd next=%jd xfer=%#jx nframes=%jd", 3623 isoc->inuse, isoc->next, (uintptr_t)xfer, xfer->ux_nframes); 3624 3625 int isread = 3626 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 3627 3628 if (xfer->ux_length) 3629 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3630 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3631 3632 if (isoc->next == -1) { 3633 /* Not in use yet, schedule it a few frames ahead. */ 3634 usb_syncmem(&sc->sc_hccadma, 3635 offsetof(struct ohci_hcca, hcca_frame_number), 3636 sizeof(sc->sc_hcca->hcca_frame_number), 3637 BUS_DMASYNC_POSTREAD); 3638 isoc->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3639 DPRINTFN(2,"start next=%jd", isoc->next, 0, 0, 0); 3640 } 3641 3642 sitd = opipe->tail.itd; 3643 opipe->tail.itd = ox->ox_sitds[0]; 3644 ox->ox_sitds[0] = sitd; 3645 sitd->held = &ox->ox_sitds[0]; 3646 3647 boff = 0; 3648 buf = DMAADDR(&xfer->ux_dmabuf, 0); 3649 bp0 = bp1 = OHCI_PAGE(buf); 3650 offs = OHCI_PAGE_OFFSET(buf); 3651 3652 ohci_physaddr_t end = bp0; /* XXX stupid GCC */ 3653 3654 nframes = xfer->ux_nframes; 3655 xfer->ux_hcpriv = sitd; 3656 size_t j = 1; 3657 for (i = ncur = 0; i < nframes; i++, ncur++) { 3658 frlen = xfer->ux_frlengths[i]; 3659 3660 DPRINTFN(1, "frame=%jd ux_frlengths[%jd]=%jd", i, i, 3661 xfer->ux_frlengths[i], 0); 3662 /* 3663 * XXXNH: The loop assumes this is never true, because 3664 * incrementing 'i' assumes all the ux_frlengths[i] is covered. 3665 */ 3666 if (frlen > 2 * OHCI_PAGE_SIZE - offs) 3667 frlen = 2 * OHCI_PAGE_SIZE - offs; 3668 3669 boff += frlen; 3670 buf = DMAADDR(&xfer->ux_dmabuf, boff); 3671 ohci_physaddr_t noffs = OHCI_PAGE_OFFSET(buf); 3672 3673 ohci_physaddr_t nend = DMAADDR(&xfer->ux_dmabuf, boff - 1); 3674 const ohci_physaddr_t nep = OHCI_PAGE(nend); 3675 3676 /* Note the first page crossing in bp1 */ 3677 if (bp0 == bp1 && bp1 != nep) 3678 bp1 = nep; 3679 3680 DPRINTFN(1, "ncur=%jd bp0=%#jx bp1=%#jx nend=%#jx", 3681 ncur, bp0, bp1, nend); 3682 3683 /* all offsets used or too many page crossings */ 3684 if (ncur == OHCI_ITD_NOFFSET || (bp0 != bp1 && bp1 != nep)) { 3685 /* Allocate next ITD */ 3686 nsitd = ox->ox_sitds[j++]; 3687 KASSERT(nsitd != NULL); 3688 KASSERT(j < ox->ox_nsitd); 3689 3690 /* Fill current ITD */ 3691 sitd->itd.itd_flags = HTOO32( 3692 OHCI_ITD_SET_CC(OHCI_ITD_NOCC) | 3693 OHCI_ITD_SET_SF(isoc->next) | 3694 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3695 OHCI_ITD_SET_FC(ncur) 3696 ); 3697 sitd->itd.itd_bp0 = HTOO32(bp0); 3698 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3699 sitd->itd.itd_be = HTOO32(end); 3700 sitd->nextitd = nsitd; 3701 sitd->xfer = xfer; 3702 sitd->flags = 0; 3703 #ifdef DIAGNOSTIC 3704 sitd->isdone = false; 3705 #endif 3706 ohci_hash_add_itd(sc, sitd); 3707 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3708 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3709 3710 sitd = nsitd; 3711 isoc->next = isoc->next + ncur; 3712 bp0 = bp1 = OHCI_PAGE(buf); 3713 ncur = 0; 3714 } 3715 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3716 end = nend; 3717 offs = noffs; 3718 } 3719 KASSERT(j <= ox->ox_nsitd); 3720 3721 /* point at sentinel */ 3722 tail = opipe->tail.itd; 3723 memset(&tail->itd, 0, sizeof(tail->itd)); 3724 tail->held = &opipe->tail.itd; 3725 tail->nextitd = NULL; 3726 tail->xfer = NULL; 3727 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->itd), 3728 BUS_DMASYNC_PREWRITE); 3729 3730 /* Fixup last used ITD */ 3731 sitd->itd.itd_flags = HTOO32( 3732 OHCI_ITD_SET_CC(OHCI_ITD_NOCC) | 3733 OHCI_ITD_SET_SF(isoc->next) | 3734 OHCI_ITD_SET_DI(0) | 3735 OHCI_ITD_SET_FC(ncur) 3736 ); 3737 sitd->itd.itd_bp0 = HTOO32(bp0); 3738 sitd->itd.itd_nextitd = HTOO32(tail->physaddr); 3739 sitd->itd.itd_be = HTOO32(end); 3740 sitd->nextitd = tail; 3741 sitd->xfer = xfer; 3742 sitd->flags = OHCI_CALL_DONE; 3743 #ifdef DIAGNOSTIC 3744 sitd->isdone = false; 3745 #endif 3746 ohci_hash_add_itd(sc, sitd); 3747 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3748 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3749 3750 isoc->next = isoc->next + ncur; 3751 isoc->inuse += nframes; 3752 3753 /* XXX pretend we did it all */ 3754 xfer->ux_actlen = offs; 3755 xfer->ux_status = USBD_IN_PROGRESS; 3756 3757 #ifdef OHCI_DEBUG 3758 if (ohcidebug >= 5) { 3759 usb_syncmem(&sc->sc_hccadma, 3760 offsetof(struct ohci_hcca, hcca_frame_number), 3761 sizeof(sc->sc_hcca->hcca_frame_number), 3762 BUS_DMASYNC_POSTREAD); 3763 DPRINTF("frame=%jd", O32TOH(sc->sc_hcca->hcca_frame_number), 3764 0, 0, 0); 3765 ohci_dump_itds(sc, xfer->ux_hcpriv); 3766 ohci_dump_ed(sc, sed); 3767 } 3768 #endif 3769 3770 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3771 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3772 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3773 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3774 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3775 sizeof(sed->ed.ed_flags), 3776 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3777 mutex_exit(&sc->sc_lock); 3778 } 3779 3780 void 3781 ohci_device_isoc_abort(struct usbd_xfer *xfer) 3782 { 3783 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3784 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3785 ohci_soft_ed_t *sed; 3786 ohci_soft_itd_t *sitd; 3787 3788 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3789 DPRINTFN(1, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3790 3791 KASSERT(mutex_owned(&sc->sc_lock)); 3792 3793 /* Transfer is already done. */ 3794 if (xfer->ux_status != USBD_NOT_STARTED && 3795 xfer->ux_status != USBD_IN_PROGRESS) { 3796 printf("ohci_device_isoc_abort: early return\n"); 3797 goto done; 3798 } 3799 3800 /* Give xfer the requested abort code. */ 3801 xfer->ux_status = USBD_CANCELLED; 3802 3803 sed = opipe->sed; 3804 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3805 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3806 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3807 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3808 sizeof(sed->ed.ed_flags), 3809 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3810 3811 sitd = xfer->ux_hcpriv; 3812 KASSERT(sitd); 3813 3814 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3815 3816 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3817 ohci_hash_rem_itd(sc, sitd); 3818 #ifdef DIAGNOSTIC 3819 DPRINTFN(1, "abort sets done sitd=%#jx", (uintptr_t)sitd, 3820 0, 0, 0); 3821 sitd->isdone = true; 3822 #endif 3823 } 3824 3825 /* Run callback. */ 3826 usb_transfer_complete(xfer); 3827 3828 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3829 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3830 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3831 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3832 3833 done: 3834 KASSERT(mutex_owned(&sc->sc_lock)); 3835 } 3836 3837 void 3838 ohci_device_isoc_done(struct usbd_xfer *xfer) 3839 { 3840 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3841 DPRINTFN(1, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3842 3843 int isread = 3844 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 3845 3846 DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 3847 0, 0); 3848 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3849 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3850 } 3851 3852 usbd_status 3853 ohci_setup_isoc(struct usbd_pipe *pipe) 3854 { 3855 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3856 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3857 struct isoc *isoc = &opipe->isoc; 3858 3859 isoc->next = -1; 3860 isoc->inuse = 0; 3861 3862 mutex_enter(&sc->sc_lock); 3863 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3864 mutex_exit(&sc->sc_lock); 3865 3866 return USBD_NORMAL_COMPLETION; 3867 } 3868 3869 void 3870 ohci_device_isoc_close(struct usbd_pipe *pipe) 3871 { 3872 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3873 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3874 3875 KASSERT(mutex_owned(&sc->sc_lock)); 3876 3877 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3878 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3879 ohci_close_pipe(pipe, sc->sc_isoc_head); 3880 #ifdef DIAGNOSTIC 3881 opipe->tail.itd->isdone = true; 3882 #endif 3883 ohci_free_sitd_locked(sc, opipe->tail.itd); 3884 } 3885
Indexes created Fri Sep 26 20:09:58 GMT 2025