ohci.c revision 1.32
1 /* $NetBSD: ohci.c,v 1.32 1999/06/09 22:57:16 augustss Exp $ */ 2 3 /* 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (augustss (at) carlstedt.se) at 9 * Carlstedt Research & Technology. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * USB Open Host Controller driver. 42 * 43 * OHCI spec: ftp://ftp.compaq.com/pub/supportinformation/papers/hcir1_0a.exe 44 * USB spec: http://www.usb.org/developers/data/usb11.pdf 45 */ 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/malloc.h> 51 #if defined(__NetBSD__) 52 #include <sys/device.h> 53 #elif defined(__FreeBSD__) 54 #include <sys/module.h> 55 #include <sys/bus.h> 56 #endif 57 #include <sys/proc.h> 58 #include <sys/queue.h> 59 #include <sys/select.h> 60 61 #include <machine/bus.h> 62 #include <machine/endian.h> 63 64 #include <dev/usb/usb.h> 65 #include <dev/usb/usbdi.h> 66 #include <dev/usb/usbdivar.h> 67 #include <dev/usb/usb_quirks.h> 68 #include <dev/usb/usb_mem.h> 69 70 #include <dev/usb/ohcireg.h> 71 #include <dev/usb/ohcivar.h> 72 73 #if defined(__FreeBSD__) 74 #include <machine/clock.h> 75 76 #define delay(d) DELAY(d) 77 78 #endif 79 80 /* 81 * The OHCI controller is little endian, so on big endian machines 82 * the data strored in memory needs to be swapped. 83 */ 84 #if BYTE_ORDER == BIG_ENDIAN 85 #define LE(x) (bswap32(x)) 86 #else 87 #define LE(x) (x) 88 #endif 89 90 struct ohci_pipe; 91 92 ohci_soft_ed_t *ohci_alloc_sed __P((ohci_softc_t *)); 93 void ohci_free_sed __P((ohci_softc_t *, ohci_soft_ed_t *)); 94 95 ohci_soft_td_t *ohci_alloc_std __P((ohci_softc_t *)); 96 void ohci_free_std __P((ohci_softc_t *, ohci_soft_td_t *)); 97 98 usbd_status ohci_open __P((usbd_pipe_handle)); 99 void ohci_poll __P((struct usbd_bus *)); 100 void ohci_waitintr __P((ohci_softc_t *, usbd_request_handle)); 101 void ohci_rhsc __P((ohci_softc_t *, usbd_request_handle)); 102 void ohci_process_done __P((ohci_softc_t *, ohci_physaddr_t)); 103 void ohci_ii_done __P((ohci_softc_t *, usbd_request_handle)); 104 void ohci_ctrl_done __P((ohci_softc_t *, usbd_request_handle)); 105 void ohci_intr_done __P((ohci_softc_t *, usbd_request_handle)); 106 void ohci_bulk_done __P((ohci_softc_t *, usbd_request_handle)); 107 108 usbd_status ohci_device_request __P((usbd_request_handle reqh)); 109 void ohci_add_ed __P((ohci_soft_ed_t *, ohci_soft_ed_t *)); 110 void ohci_rem_ed __P((ohci_soft_ed_t *, ohci_soft_ed_t *)); 111 void ohci_hash_add_td __P((ohci_softc_t *, ohci_soft_td_t *)); 112 void ohci_hash_rem_td __P((ohci_softc_t *, ohci_soft_td_t *)); 113 ohci_soft_td_t *ohci_hash_find_td __P((ohci_softc_t *, ohci_physaddr_t)); 114 115 usbd_status ohci_root_ctrl_transfer __P((usbd_request_handle)); 116 usbd_status ohci_root_ctrl_start __P((usbd_request_handle)); 117 void ohci_root_ctrl_abort __P((usbd_request_handle)); 118 void ohci_root_ctrl_close __P((usbd_pipe_handle)); 119 120 usbd_status ohci_root_intr_transfer __P((usbd_request_handle)); 121 usbd_status ohci_root_intr_start __P((usbd_request_handle)); 122 void ohci_root_intr_abort __P((usbd_request_handle)); 123 void ohci_root_intr_close __P((usbd_pipe_handle)); 124 125 usbd_status ohci_device_ctrl_transfer __P((usbd_request_handle)); 126 usbd_status ohci_device_ctrl_start __P((usbd_request_handle)); 127 void ohci_device_ctrl_abort __P((usbd_request_handle)); 128 void ohci_device_ctrl_close __P((usbd_pipe_handle)); 129 130 usbd_status ohci_device_bulk_transfer __P((usbd_request_handle)); 131 usbd_status ohci_device_bulk_start __P((usbd_request_handle)); 132 void ohci_device_bulk_abort __P((usbd_request_handle)); 133 void ohci_device_bulk_close __P((usbd_pipe_handle)); 134 135 usbd_status ohci_device_intr_transfer __P((usbd_request_handle)); 136 usbd_status ohci_device_intr_start __P((usbd_request_handle)); 137 void ohci_device_intr_abort __P((usbd_request_handle)); 138 void ohci_device_intr_close __P((usbd_pipe_handle)); 139 usbd_status ohci_device_setintr __P((ohci_softc_t *sc, 140 struct ohci_pipe *pipe, int ival)); 141 142 int ohci_str __P((usb_string_descriptor_t *, int, char *)); 143 144 void ohci_timeout __P((void *)); 145 void ohci_rhsc_able __P((ohci_softc_t *, int)); 146 147 #ifdef USB_DEBUG 148 ohci_softc_t *thesc; 149 void ohci_dumpregs __P((ohci_softc_t *)); 150 void ohci_dump_tds __P((ohci_soft_td_t *)); 151 void ohci_dump_td __P((ohci_soft_td_t *)); 152 void ohci_dump_ed __P((ohci_soft_ed_t *)); 153 #endif 154 155 #if defined(__NetBSD__) 156 #define OWRITE4(sc, r, x) bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)) 157 #define OREAD4(sc, r) bus_space_read_4((sc)->iot, (sc)->ioh, (r)) 158 #define OREAD2(sc, r) bus_space_read_2((sc)->iot, (sc)->ioh, (r)) 159 #elif defined(__FreeBSD__) 160 #define OWRITE4(sc, r, x) *(u_int32_t *) ((sc)->sc_iobase + (r)) = x 161 #define OREAD4(sc, r) (*(u_int32_t *) ((sc)->sc_iobase + (r))) 162 #define OREAD2(sc, r) (*(u_int16_t *) ((sc)->sc_iobase + (r))) 163 #endif 164 165 /* Reverse the bits in a value 0 .. 31 */ 166 static u_int8_t revbits[OHCI_NO_INTRS] = 167 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 168 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 169 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 170 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 171 172 struct ohci_pipe { 173 struct usbd_pipe pipe; 174 ohci_soft_ed_t *sed; 175 ohci_soft_td_t *tail; 176 /* Info needed for different pipe kinds. */ 177 union { 178 /* Control pipe */ 179 struct { 180 usb_dma_t datadma; 181 usb_dma_t reqdma; 182 u_int length; 183 ohci_soft_td_t *setup, *xfer, *stat; 184 } ctl; 185 /* Interrupt pipe */ 186 struct { 187 usb_dma_t datadma; 188 int nslots; 189 int pos; 190 } intr; 191 /* Bulk pipe */ 192 struct { 193 usb_dma_t datadma; 194 u_int length; 195 int isread; 196 } bulk; 197 } u; 198 }; 199 200 #define OHCI_INTR_ENDPT 1 201 202 struct usbd_methods ohci_root_ctrl_methods = { 203 ohci_root_ctrl_transfer, 204 ohci_root_ctrl_start, 205 ohci_root_ctrl_abort, 206 ohci_root_ctrl_close, 207 0, 208 }; 209 210 struct usbd_methods ohci_root_intr_methods = { 211 ohci_root_intr_transfer, 212 ohci_root_intr_start, 213 ohci_root_intr_abort, 214 ohci_root_intr_close, 215 0, 216 }; 217 218 struct usbd_methods ohci_device_ctrl_methods = { 219 ohci_device_ctrl_transfer, 220 ohci_device_ctrl_start, 221 ohci_device_ctrl_abort, 222 ohci_device_ctrl_close, 223 0, 224 }; 225 226 struct usbd_methods ohci_device_intr_methods = { 227 ohci_device_intr_transfer, 228 ohci_device_intr_start, 229 ohci_device_intr_abort, 230 ohci_device_intr_close, 231 }; 232 233 struct usbd_methods ohci_device_bulk_methods = { 234 ohci_device_bulk_transfer, 235 ohci_device_bulk_start, 236 ohci_device_bulk_abort, 237 ohci_device_bulk_close, 238 0, 239 }; 240 241 ohci_soft_ed_t * 242 ohci_alloc_sed(sc) 243 ohci_softc_t *sc; 244 { 245 ohci_soft_ed_t *sed; 246 usbd_status r; 247 int i, offs; 248 usb_dma_t dma; 249 250 if (!sc->sc_freeeds) { 251 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n")); 252 sed = malloc(sizeof(ohci_soft_ed_t) * OHCI_ED_CHUNK, 253 M_USBDEV, M_NOWAIT); 254 if (!sed) 255 return 0; 256 r = usb_allocmem(sc->sc_dmatag, OHCI_ED_SIZE * OHCI_ED_CHUNK, 257 OHCI_ED_ALIGN, &dma); 258 if (r != USBD_NORMAL_COMPLETION) { 259 free(sed, M_USBDEV); 260 return 0; 261 } 262 for(i = 0; i < OHCI_ED_CHUNK; i++, sed++) { 263 offs = i * OHCI_ED_SIZE; 264 sed->physaddr = DMAADDR(&dma) + offs; 265 sed->ed = (ohci_ed_t *) 266 ((char *)KERNADDR(&dma) + offs); 267 sed->next = sc->sc_freeeds; 268 sc->sc_freeeds = sed; 269 } 270 } 271 sed = sc->sc_freeeds; 272 sc->sc_freeeds = sed->next; 273 memset(sed->ed, 0, OHCI_ED_SIZE); 274 sed->next = 0; 275 return sed; 276 } 277 278 void 279 ohci_free_sed(sc, sed) 280 ohci_softc_t *sc; 281 ohci_soft_ed_t *sed; 282 { 283 sed->next = sc->sc_freeeds; 284 sc->sc_freeeds = sed; 285 } 286 287 ohci_soft_td_t * 288 ohci_alloc_std(sc) 289 ohci_softc_t *sc; 290 { 291 ohci_soft_td_t *std; 292 usbd_status r; 293 int i, offs; 294 usb_dma_t dma; 295 296 if (!sc->sc_freetds) { 297 DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n")); 298 std = malloc(sizeof(ohci_soft_td_t) * OHCI_TD_CHUNK, 299 M_USBDEV, M_NOWAIT); 300 if (!std) 301 return 0; 302 r = usb_allocmem(sc->sc_dmatag, OHCI_TD_SIZE * OHCI_TD_CHUNK, 303 OHCI_TD_ALIGN, &dma); 304 if (r != USBD_NORMAL_COMPLETION) { 305 free(std, M_USBDEV); 306 return 0; 307 } 308 for(i = 0; i < OHCI_TD_CHUNK; i++, std++) { 309 offs = i * OHCI_TD_SIZE; 310 std->physaddr = DMAADDR(&dma) + offs; 311 std->td = (ohci_td_t *) 312 ((char *)KERNADDR(&dma) + offs); 313 std->nexttd = sc->sc_freetds; 314 sc->sc_freetds = std; 315 } 316 } 317 std = sc->sc_freetds; 318 sc->sc_freetds = std->nexttd; 319 memset(std->td, 0, OHCI_TD_SIZE); 320 std->nexttd = 0; 321 return (std); 322 } 323 324 void 325 ohci_free_std(sc, std) 326 ohci_softc_t *sc; 327 ohci_soft_td_t *std; 328 { 329 std->nexttd = sc->sc_freetds; 330 sc->sc_freetds = std; 331 } 332 333 usbd_status 334 ohci_init(sc) 335 ohci_softc_t *sc; 336 { 337 ohci_soft_ed_t *sed, *psed; 338 usbd_status r; 339 int rev; 340 int i; 341 u_int32_t s, ctl, ival, hcr, fm, per; 342 343 DPRINTF(("ohci_init: start\n")); 344 rev = OREAD4(sc, OHCI_REVISION); 345 printf("%s: OHCI version %d.%d%s\n", USBDEVNAME(sc->sc_bus.bdev), 346 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 347 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 348 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 349 printf("%s: unsupported OHCI revision\n", 350 USBDEVNAME(sc->sc_bus.bdev)); 351 return (USBD_INVAL); 352 } 353 354 for (i = 0; i < OHCI_HASH_SIZE; i++) 355 LIST_INIT(&sc->sc_hash_tds[i]); 356 357 /* Allocate the HCCA area. */ 358 r = usb_allocmem(sc->sc_dmatag, OHCI_HCCA_SIZE, 359 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 360 if (r != USBD_NORMAL_COMPLETION) 361 return (r); 362 sc->sc_hcca = (struct ohci_hcca *)KERNADDR(&sc->sc_hccadma); 363 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 364 365 sc->sc_eintrs = OHCI_NORMAL_INTRS; 366 367 sc->sc_ctrl_head = ohci_alloc_sed(sc); 368 if (!sc->sc_ctrl_head) { 369 r = USBD_NOMEM; 370 goto bad1; 371 } 372 sc->sc_ctrl_head->ed->ed_flags |= LE(OHCI_ED_SKIP); 373 sc->sc_bulk_head = ohci_alloc_sed(sc); 374 if (!sc->sc_bulk_head) { 375 r = USBD_NOMEM; 376 goto bad2; 377 } 378 sc->sc_bulk_head->ed->ed_flags |= LE(OHCI_ED_SKIP); 379 380 /* Allocate all the dummy EDs that make up the interrupt tree. */ 381 for (i = 0; i < OHCI_NO_EDS; i++) { 382 sed = ohci_alloc_sed(sc); 383 if (!sed) { 384 while (--i >= 0) 385 ohci_free_sed(sc, sc->sc_eds[i]); 386 r = USBD_NOMEM; 387 goto bad3; 388 } 389 /* All ED fields are set to 0. */ 390 sc->sc_eds[i] = sed; 391 sed->ed->ed_flags |= LE(OHCI_ED_SKIP); 392 if (i != 0) { 393 psed = sc->sc_eds[(i-1) / 2]; 394 sed->next = psed; 395 sed->ed->ed_nexted = LE(psed->physaddr); 396 } 397 } 398 /* 399 * Fill HCCA interrupt table. The bit reversal is to get 400 * the tree set up properly to spread the interrupts. 401 */ 402 for (i = 0; i < OHCI_NO_INTRS; i++) 403 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 404 LE(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 405 406 /* Determine in what context we are running. */ 407 ctl = OREAD4(sc, OHCI_CONTROL); 408 if (ctl & OHCI_IR) { 409 /* SMM active, request change */ 410 DPRINTF(("ohci_init: SMM active, request owner change\n")); 411 s = OREAD4(sc, OHCI_COMMAND_STATUS); 412 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 413 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 414 delay(1000); 415 ctl = OREAD4(sc, OHCI_CONTROL); 416 } 417 if ((ctl & OHCI_IR) == 0) { 418 printf("%s: SMM does not respond, resetting\n", 419 USBDEVNAME(sc->sc_bus.bdev)); 420 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 421 goto reset; 422 } 423 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 424 /* BIOS started controller. */ 425 DPRINTF(("ohci_init: BIOS active\n")); 426 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 427 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL); 428 delay(USB_RESUME_DELAY * 1000); 429 } 430 } else { 431 DPRINTF(("ohci_init: cold started\n")); 432 reset: 433 /* Controller was cold started. */ 434 delay(USB_BUS_RESET_DELAY * 1000); 435 } 436 437 /* 438 * This reset should not be necessary according to the OHCI spec, but 439 * without it some controllers do not start. 440 */ 441 DPRINTF(("%s: resetting\n", USBDEVNAME(sc->sc_bus.bdev))); 442 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 443 delay(USB_BUS_RESET_DELAY * 1000); 444 445 /* We now own the host controller and the bus has been reset. */ 446 ival = OHCI_GET_IVAL(OREAD4(sc, OHCI_FM_INTERVAL)); 447 448 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 449 /* Nominal time for a reset is 10 us. */ 450 for (i = 0; i < 10; i++) { 451 delay(10); 452 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 453 if (!hcr) 454 break; 455 } 456 if (hcr) { 457 printf("%s: reset timeout\n", USBDEVNAME(sc->sc_bus.bdev)); 458 r = USBD_IOERROR; 459 goto bad3; 460 } 461 #ifdef USB_DEBUG 462 thesc = sc; 463 if (ohcidebug > 15) 464 ohci_dumpregs(sc); 465 #endif 466 467 /* The controller is now in suspend state, we have 2ms to finish. */ 468 469 /* Set up HC registers. */ 470 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma)); 471 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 472 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 473 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 474 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 475 ctl = OREAD4(sc, OHCI_CONTROL); 476 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 477 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 478 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL; 479 /* And finally start it! */ 480 OWRITE4(sc, OHCI_CONTROL, ctl); 481 482 /* 483 * The controller is now OPERATIONAL. Set a some final 484 * registers that should be set earlier, but that the 485 * controller ignores when in the SUSPEND state. 486 */ 487 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 488 fm |= OHCI_FSMPS(ival) | ival; 489 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 490 per = OHCI_PERIODIC(ival); /* 90% periodic */ 491 OWRITE4(sc, OHCI_PERIODIC_START, per); 492 493 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 494 495 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 496 497 #ifdef USB_DEBUG 498 if (ohcidebug > 5) 499 ohci_dumpregs(sc); 500 #endif 501 502 /* Set up the bus struct. */ 503 sc->sc_bus.open_pipe = ohci_open; 504 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe); 505 sc->sc_bus.do_poll = ohci_poll; 506 507 return (USBD_NORMAL_COMPLETION); 508 509 bad3: 510 ohci_free_sed(sc, sc->sc_ctrl_head); 511 bad2: 512 ohci_free_sed(sc, sc->sc_bulk_head); 513 bad1: 514 usb_freemem(sc->sc_dmatag, &sc->sc_hccadma); 515 return (r); 516 } 517 518 #ifdef USB_DEBUG 519 void ohcidump(void); 520 void ohcidump(void) { ohci_dumpregs(thesc); } 521 522 void 523 ohci_dumpregs(sc) 524 ohci_softc_t *sc; 525 { 526 printf("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 527 OREAD4(sc, OHCI_REVISION), 528 OREAD4(sc, OHCI_CONTROL), 529 OREAD4(sc, OHCI_COMMAND_STATUS)); 530 printf(" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 531 OREAD4(sc, OHCI_INTERRUPT_STATUS), 532 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 533 OREAD4(sc, OHCI_INTERRUPT_DISABLE)); 534 printf(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 535 OREAD4(sc, OHCI_HCCA), 536 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 537 OREAD4(sc, OHCI_CONTROL_HEAD_ED)); 538 printf(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 539 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 540 OREAD4(sc, OHCI_BULK_HEAD_ED), 541 OREAD4(sc, OHCI_BULK_CURRENT_ED)); 542 printf(" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 543 OREAD4(sc, OHCI_DONE_HEAD), 544 OREAD4(sc, OHCI_FM_INTERVAL), 545 OREAD4(sc, OHCI_FM_REMAINING)); 546 printf(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 547 OREAD4(sc, OHCI_FM_NUMBER), 548 OREAD4(sc, OHCI_PERIODIC_START), 549 OREAD4(sc, OHCI_LS_THRESHOLD)); 550 printf(" desca=0x%08x descb=0x%08x stat=0x%08x\n", 551 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 552 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 553 OREAD4(sc, OHCI_RH_STATUS)); 554 printf(" port1=0x%08x port2=0x%08x\n", 555 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 556 OREAD4(sc, OHCI_RH_PORT_STATUS(2))); 557 printf(" HCCA: frame_number=0x%04x done_head=0x%08x\n", 558 LE(sc->sc_hcca->hcca_frame_number), 559 LE(sc->sc_hcca->hcca_done_head)); 560 } 561 #endif 562 563 int 564 ohci_intr(p) 565 void *p; 566 { 567 ohci_softc_t *sc = p; 568 u_int32_t intrs, eintrs; 569 ohci_physaddr_t done; 570 571 /* In case the interrupt occurs before initialization has completed. */ 572 if (sc == NULL || sc->sc_hcca == NULL) { /* NWH added sc==0 */ 573 #ifdef DIAGNOSTIC 574 printf("ohci_intr: sc->sc_hcca == NULL\n"); 575 #endif 576 return (0); 577 } 578 579 intrs = 0; 580 done = LE(sc->sc_hcca->hcca_done_head); 581 if (done != 0) { 582 sc->sc_hcca->hcca_done_head = 0; 583 if (done & ~OHCI_DONE_INTRS) 584 intrs = OHCI_WDH; 585 if (done & OHCI_DONE_INTRS) 586 intrs |= OREAD4(sc, OHCI_INTERRUPT_STATUS); 587 } else 588 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 589 if (!intrs) 590 return (0); 591 intrs &= ~OHCI_MIE; 592 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs); /* Acknowledge */ 593 eintrs = intrs & sc->sc_eintrs; 594 if (!eintrs) 595 return (0); 596 597 sc->sc_intrs++; 598 DPRINTFN(7, ("ohci_intr: sc=%p intrs=%x(%x) eintr=%x\n", 599 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), 600 (u_int)eintrs)); 601 602 if (eintrs & OHCI_SO) { 603 printf("%s: scheduling overrun\n",USBDEVNAME(sc->sc_bus.bdev)); 604 /* XXX do what */ 605 intrs &= ~OHCI_SO; 606 } 607 if (eintrs & OHCI_WDH) { 608 ohci_process_done(sc, done &~ OHCI_DONE_INTRS); 609 intrs &= ~OHCI_WDH; 610 } 611 if (eintrs & OHCI_RD) { 612 /* XXX process resume detect */ 613 } 614 if (eintrs & OHCI_UE) { 615 printf("%s: unrecoverable error, controller halted\n", 616 USBDEVNAME(sc->sc_bus.bdev)); 617 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 618 /* XXX what else */ 619 } 620 if (eintrs & OHCI_RHSC) { 621 ohci_rhsc(sc, sc->sc_intrreqh); 622 intrs &= ~OHCI_RHSC; 623 624 /* 625 * Disable RHSC interrupt for now, because it will be 626 * on until the port has been reset. 627 */ 628 ohci_rhsc_able(sc, 0); 629 } 630 631 /* Block unprocessed interrupts. XXX */ 632 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, intrs); 633 sc->sc_eintrs &= ~intrs; 634 635 return (1); 636 } 637 638 void 639 ohci_rhsc_able(sc, on) 640 ohci_softc_t *sc; 641 int on; 642 { 643 DPRINTFN(4, ("ohci_rhsc_able: on=%d\n", on)); 644 if (on) { 645 sc->sc_eintrs |= OHCI_RHSC; 646 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 647 } else { 648 sc->sc_eintrs &= ~OHCI_RHSC; 649 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_RHSC); 650 } 651 } 652 653 #ifdef USB_DEBUG 654 char *ohci_cc_strs[] = { 655 "NO_ERROR", 656 "CRC", 657 "BIT_STUFFING", 658 "DATA_TOGGLE_MISMATCH", 659 "STALL", 660 "DEVICE_NOT_RESPONDING", 661 "PID_CHECK_FAILURE", 662 "UNEXPECTED_PID", 663 "DATA_OVERRUN", 664 "DATA_UNDERRUN", 665 "BUFFER_OVERRUN", 666 "BUFFER_UNDERRUN", 667 "NOT_ACCESSED", 668 }; 669 #endif 670 671 void 672 ohci_process_done(sc, done) 673 ohci_softc_t *sc; 674 ohci_physaddr_t done; 675 { 676 ohci_soft_td_t *std, *sdone; 677 usbd_request_handle reqh; 678 int len, cc; 679 680 DPRINTFN(10,("ohci_process_done: done=0x%08lx\n", (u_long)done)); 681 682 /* Reverse the done list. */ 683 for (sdone = 0; done; done = LE(std->td->td_nexttd)) { 684 std = ohci_hash_find_td(sc, done); 685 std->dnext = sdone; 686 sdone = std; 687 } 688 689 #ifdef USB_DEBUG 690 if (ohcidebug > 10) { 691 printf("ohci_process_done: TD done:\n"); 692 ohci_dump_tds(sdone); 693 } 694 #endif 695 696 for (std = sdone; std; std = std->dnext) { 697 reqh = std->reqh; 698 DPRINTFN(10, ("ohci_process_done: std=%p reqh=%p hcpriv=%p\n", 699 std, reqh, reqh->hcpriv)); 700 cc = OHCI_TD_GET_CC(LE(std->td->td_flags)); 701 if (cc == OHCI_CC_NO_ERROR) { 702 if (std->td->td_cbp == 0) 703 len = std->len; 704 else 705 len = LE(std->td->td_be) - 706 LE(std->td->td_cbp) + 1; 707 /* 708 * Only do a callback on the last stage of a transfer. 709 * Others have hcpriv = 0. 710 */ 711 if ((reqh->pipe->endpoint->edesc->bmAttributes & 712 UE_XFERTYPE) == UE_CONTROL) { 713 /* For a control transfer the length is in 714 * the xfer stage */ 715 if (reqh->hcpriv == std) { 716 reqh->status = USBD_NORMAL_COMPLETION; 717 ohci_ii_done(sc, reqh); 718 } else 719 reqh->actlen = len; 720 } else { 721 if (reqh->hcpriv == std) { 722 reqh->actlen = len; 723 reqh->status = USBD_NORMAL_COMPLETION; 724 ohci_ii_done(sc, reqh); 725 } 726 } 727 } else { 728 ohci_soft_td_t *p, *n; 729 struct ohci_pipe *opipe = 730 (struct ohci_pipe *)reqh->pipe; 731 DPRINTFN(-1,("ohci_process_done: error cc=%d (%s)\n", 732 OHCI_TD_GET_CC(LE(std->td->td_flags)), 733 ohci_cc_strs[OHCI_TD_GET_CC(LE(std->td->td_flags))])); 734 /* 735 * Endpoint is halted. First unlink all the TDs 736 * belonging to the failed transfer, and then restart 737 * the endpoint. 738 */ 739 for (p = std->nexttd; p->reqh == reqh; p = n) { 740 n = p->nexttd; 741 ohci_hash_rem_td(sc, p); 742 ohci_free_std(sc, p); 743 } 744 /* clear halt */ 745 opipe->sed->ed->ed_headp = LE(p->physaddr); 746 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 747 748 if (cc == OHCI_CC_STALL) 749 reqh->status = USBD_STALLED; 750 else 751 reqh->status = USBD_IOERROR; 752 ohci_ii_done(sc, reqh); 753 } 754 ohci_hash_rem_td(sc, std); 755 ohci_free_std(sc, std); 756 } 757 } 758 759 void 760 ohci_ii_done(sc, reqh) 761 ohci_softc_t *sc; 762 usbd_request_handle reqh; 763 { 764 switch (reqh->pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 765 case UE_CONTROL: 766 ohci_ctrl_done(sc, reqh); 767 usb_start_next(reqh->pipe); 768 break; 769 case UE_INTERRUPT: 770 ohci_intr_done(sc, reqh); 771 break; 772 case UE_BULK: 773 ohci_bulk_done(sc, reqh); 774 usb_start_next(reqh->pipe); 775 break; 776 case UE_ISOCHRONOUS: 777 printf("ohci_process_done: ISO done?\n"); 778 usb_start_next(reqh->pipe); 779 break; 780 } 781 782 /* And finally execute callback. */ 783 reqh->xfercb(reqh); 784 } 785 786 void 787 ohci_ctrl_done(sc, reqh) 788 ohci_softc_t *sc; 789 usbd_request_handle reqh; 790 { 791 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 792 u_int len = opipe->u.ctl.length; 793 usb_dma_t *dma; 794 795 DPRINTFN(10,("ohci_ctrl_done: reqh=%p\n", reqh)); 796 797 if (!reqh->isreq) { 798 panic("ohci_ctrl_done: not a request\n"); 799 return; 800 } 801 802 if (len != 0) { 803 dma = &opipe->u.ctl.datadma; 804 if (reqh->request.bmRequestType & UT_READ) 805 memcpy(reqh->buffer, KERNADDR(dma), len); 806 usb_freemem(sc->sc_dmatag, dma); 807 } 808 usb_untimeout(ohci_timeout, reqh, reqh->timo_handle); 809 } 810 811 void 812 ohci_intr_done(sc, reqh) 813 ohci_softc_t *sc; 814 usbd_request_handle reqh; 815 { 816 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 817 usb_dma_t *dma; 818 ohci_soft_ed_t *sed = opipe->sed; 819 ohci_soft_td_t *xfer, *tail; 820 821 822 DPRINTFN(10,("ohci_intr_done: reqh=%p, actlen=%d\n", 823 reqh, reqh->actlen)); 824 825 dma = &opipe->u.intr.datadma; 826 memcpy(reqh->buffer, KERNADDR(dma), reqh->actlen); 827 828 if (reqh->pipe->intrreqh == reqh) { 829 xfer = opipe->tail; 830 tail = ohci_alloc_std(sc); /* XXX should reuse TD */ 831 if (!tail) { 832 reqh->status = USBD_NOMEM; 833 return; 834 } 835 tail->reqh = 0; 836 837 xfer->td->td_flags = LE( 838 OHCI_TD_IN | OHCI_TD_NOCC | 839 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 840 if (reqh->flags & USBD_SHORT_XFER_OK) 841 xfer->td->td_flags |= LE(OHCI_TD_R); 842 xfer->td->td_cbp = LE(DMAADDR(dma)); 843 xfer->nexttd = tail; 844 xfer->td->td_nexttd = LE(tail->physaddr); 845 xfer->td->td_be = LE(LE(xfer->td->td_cbp) + reqh->length - 1); 846 xfer->len = reqh->length; 847 xfer->reqh = reqh; 848 849 reqh->hcpriv = xfer; 850 851 ohci_hash_add_td(sc, xfer); 852 sed->ed->ed_tailp = LE(tail->physaddr); 853 opipe->tail = tail; 854 } else { 855 usb_freemem(sc->sc_dmatag, dma); 856 usb_start_next(reqh->pipe); 857 } 858 } 859 860 void 861 ohci_bulk_done(sc, reqh) 862 ohci_softc_t *sc; 863 usbd_request_handle reqh; 864 { 865 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 866 u_int len = opipe->u.bulk.length; 867 usb_dma_t *dma; 868 869 870 DPRINTFN(10,("ohci_bulk_done: reqh=%p, actlen=%d\n", 871 reqh, reqh->actlen)); 872 873 if (len != 0) { 874 dma = &opipe->u.bulk.datadma; 875 if (opipe->u.bulk.isread) 876 memcpy(reqh->buffer, KERNADDR(dma), len); 877 usb_freemem(sc->sc_dmatag, dma); 878 } 879 usb_untimeout(ohci_timeout, reqh, reqh->timo_handle); 880 } 881 882 void 883 ohci_rhsc(sc, reqh) 884 ohci_softc_t *sc; 885 usbd_request_handle reqh; 886 { 887 usbd_pipe_handle pipe; 888 struct ohci_pipe *opipe; 889 u_char *p; 890 int i, m; 891 int hstatus; 892 893 hstatus = OREAD4(sc, OHCI_RH_STATUS); 894 DPRINTF(("ohci_rhsc: sc=%p reqh=%p hstatus=0x%08x\n", 895 sc, reqh, hstatus)); 896 897 if (reqh == 0) { 898 /* Just ignore the change. */ 899 return; 900 } 901 902 pipe = reqh->pipe; 903 opipe = (struct ohci_pipe *)pipe; 904 905 p = KERNADDR(&opipe->u.intr.datadma); 906 m = min(sc->sc_noport, reqh->length * 8 - 1); 907 memset(p, 0, reqh->length); 908 for (i = 1; i <= m; i++) { 909 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 910 p[i/8] |= 1 << (i%8); 911 } 912 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p)); 913 reqh->actlen = reqh->length; 914 reqh->status = USBD_NORMAL_COMPLETION; 915 reqh->xfercb(reqh); 916 917 if (reqh->pipe->intrreqh != reqh) { 918 sc->sc_intrreqh = 0; 919 usb_freemem(sc->sc_dmatag, &opipe->u.intr.datadma); 920 usb_start_next(reqh->pipe); 921 } 922 } 923 924 /* 925 * Wait here until controller claims to have an interrupt. 926 * Then call ohci_intr and return. Use timeout to avoid waiting 927 * too long. 928 */ 929 void 930 ohci_waitintr(sc, reqh) 931 ohci_softc_t *sc; 932 usbd_request_handle reqh; 933 { 934 int timo = reqh->timeout; 935 int usecs; 936 u_int32_t intrs; 937 938 reqh->status = USBD_IN_PROGRESS; 939 for (usecs = timo * 1000000 / hz; usecs > 0; usecs -= 1000) { 940 usb_delay_ms(&sc->sc_bus, 1); 941 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 942 DPRINTFN(15,("ohci_waitintr: 0x%04x\n", intrs)); 943 #ifdef USB_DEBUG 944 if (ohcidebug > 15) 945 ohci_dumpregs(sc); 946 #endif 947 if (intrs) { 948 ohci_intr(sc); 949 if (reqh->status != USBD_IN_PROGRESS) 950 return; 951 } 952 } 953 954 /* Timeout */ 955 DPRINTF(("ohci_waitintr: timeout\n")); 956 reqh->status = USBD_TIMEOUT; 957 ohci_ii_done(sc, reqh); 958 /* XXX should free TD */ 959 } 960 961 void 962 ohci_poll(bus) 963 struct usbd_bus *bus; 964 { 965 ohci_softc_t *sc = (ohci_softc_t *)bus; 966 967 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) 968 ohci_intr(sc); 969 } 970 971 usbd_status 972 ohci_device_request(reqh) 973 usbd_request_handle reqh; 974 { 975 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 976 usb_device_request_t *req = &reqh->request; 977 usbd_device_handle dev = opipe->pipe.device; 978 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 979 int addr = dev->address; 980 ohci_soft_td_t *setup, *xfer = 0, *stat, *next, *tail; 981 ohci_soft_ed_t *sed; 982 usb_dma_t *dmap; 983 int isread; 984 int len; 985 usbd_status r; 986 int s; 987 988 isread = req->bmRequestType & UT_READ; 989 len = UGETW(req->wLength); 990 991 DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, " 992 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 993 req->bmRequestType, req->bRequest, UGETW(req->wValue), 994 UGETW(req->wIndex), len, addr, 995 opipe->pipe.endpoint->edesc->bEndpointAddress)); 996 997 setup = opipe->tail; 998 stat = ohci_alloc_std(sc); 999 if (!stat) { 1000 r = USBD_NOMEM; 1001 goto bad1; 1002 } 1003 tail = ohci_alloc_std(sc); 1004 if (!tail) { 1005 r = USBD_NOMEM; 1006 goto bad2; 1007 } 1008 tail->reqh = 0; 1009 1010 sed = opipe->sed; 1011 dmap = &opipe->u.ctl.datadma; 1012 opipe->u.ctl.length = len; 1013 1014 /* Update device address and length since they may have changed. */ 1015 /* XXX This only needs to be done once, but it's too early in open. */ 1016 sed->ed->ed_flags = LE( 1017 (LE(sed->ed->ed_flags) & ~(OHCI_ED_ADDRMASK | OHCI_ED_MAXPMASK)) | 1018 OHCI_ED_SET_FA(addr) | 1019 OHCI_ED_SET_MAXP(UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize))); 1020 1021 /* Set up data transaction */ 1022 if (len != 0) { 1023 xfer = ohci_alloc_std(sc); 1024 if (!xfer) { 1025 r = USBD_NOMEM; 1026 goto bad3; 1027 } 1028 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap); 1029 if (r != USBD_NORMAL_COMPLETION) 1030 goto bad4; 1031 xfer->td->td_flags = LE( 1032 (isread ? OHCI_TD_IN : OHCI_TD_OUT) | OHCI_TD_NOCC | 1033 OHCI_TD_TOGGLE_1 | OHCI_TD_NOINTR | 1034 (reqh->flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0)); 1035 xfer->td->td_cbp = LE(DMAADDR(dmap)); 1036 xfer->nexttd = stat; 1037 xfer->td->td_nexttd = LE(stat->physaddr); 1038 xfer->td->td_be = LE(LE(xfer->td->td_cbp) + len - 1); 1039 xfer->len = len; 1040 xfer->reqh = reqh; 1041 1042 next = xfer; 1043 } else 1044 next = stat; 1045 1046 memcpy(KERNADDR(&opipe->u.ctl.reqdma), req, sizeof *req); 1047 if (!isread && len != 0) 1048 memcpy(KERNADDR(dmap), reqh->buffer, len); 1049 1050 setup->td->td_flags = LE(OHCI_TD_SETUP | OHCI_TD_NOCC | 1051 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1052 setup->td->td_cbp = LE(DMAADDR(&opipe->u.ctl.reqdma)); 1053 setup->nexttd = next; 1054 setup->td->td_nexttd = LE(next->physaddr); 1055 setup->td->td_be = LE(LE(setup->td->td_cbp) + sizeof *req - 1); 1056 setup->len = 0; /* XXX The number of byte we count */ 1057 setup->reqh = reqh; 1058 1059 stat->td->td_flags = LE( 1060 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | OHCI_TD_NOCC | 1061 OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1062 stat->td->td_cbp = 0; 1063 stat->nexttd = tail; 1064 stat->td->td_nexttd = LE(tail->physaddr); 1065 stat->td->td_be = 0; 1066 stat->len = 0; 1067 stat->reqh = reqh; 1068 1069 reqh->hcpriv = stat; 1070 1071 #if USB_DEBUG 1072 if (ohcidebug > 5) { 1073 printf("ohci_device_request:\n"); 1074 ohci_dump_ed(sed); 1075 ohci_dump_tds(setup); 1076 } 1077 #endif 1078 1079 /* Insert ED in schedule */ 1080 s = splusb(); 1081 ohci_hash_add_td(sc, setup); 1082 if (len != 0) 1083 ohci_hash_add_td(sc, xfer); 1084 ohci_hash_add_td(sc, stat); 1085 sed->ed->ed_tailp = LE(tail->physaddr); 1086 opipe->tail = tail; 1087 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1088 if (reqh->timeout && !sc->sc_bus.use_polling) { 1089 usb_timeout(ohci_timeout, reqh, 1090 MS_TO_TICKS(reqh->timeout), reqh->timo_handle); 1091 } 1092 splx(s); 1093 1094 #if USB_DEBUG 1095 if (ohcidebug > 5) { 1096 delay(5000); 1097 printf("ohci_device_request: status=%x\n", 1098 OREAD4(sc, OHCI_COMMAND_STATUS)); 1099 ohci_dump_ed(sed); 1100 ohci_dump_tds(setup); 1101 } 1102 #endif 1103 1104 return (USBD_NORMAL_COMPLETION); 1105 1106 bad4: 1107 ohci_free_std(sc, xfer); 1108 bad3: 1109 ohci_free_std(sc, tail); 1110 bad2: 1111 ohci_free_std(sc, stat); 1112 bad1: 1113 return (r); 1114 } 1115 1116 /* 1117 * Add an ED to the schedule. Called at splusb(). 1118 */ 1119 void 1120 ohci_add_ed(sed, head) 1121 ohci_soft_ed_t *sed; 1122 ohci_soft_ed_t *head; 1123 { 1124 sed->next = head->next; 1125 sed->ed->ed_nexted = head->ed->ed_nexted; 1126 head->next = sed; 1127 head->ed->ed_nexted = LE(sed->physaddr); 1128 } 1129 1130 /* 1131 * Remove an ED from the schedule. Called at splusb(). 1132 */ 1133 void 1134 ohci_rem_ed(sed, head) 1135 ohci_soft_ed_t *sed; 1136 ohci_soft_ed_t *head; 1137 { 1138 ohci_soft_ed_t *p; 1139 1140 /* XXX */ 1141 for (p = head; p && p->next != sed; p = p->next) 1142 ; 1143 if (!p) 1144 panic("ohci_rem_ed: ED not found\n"); 1145 p->next = sed->next; 1146 p->ed->ed_nexted = sed->ed->ed_nexted; 1147 } 1148 1149 /* 1150 * When a transfer is completed the TD is added to the done queue by 1151 * the host controller. This queue is the processed by software. 1152 * Unfortunately the queue contains the physical address of the TD 1153 * and we have no simple way to translate this back to a kernel address. 1154 * To make the translation possible (and fast) we use a hash table of 1155 * TDs currently in the schedule. The physical address is used as the 1156 * hash value. 1157 */ 1158 1159 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1160 /* Called at splusb() */ 1161 void 1162 ohci_hash_add_td(sc, std) 1163 ohci_softc_t *sc; 1164 ohci_soft_td_t *std; 1165 { 1166 int h = HASH(std->physaddr); 1167 1168 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1169 } 1170 1171 /* Called at splusb() */ 1172 void 1173 ohci_hash_rem_td(sc, std) 1174 ohci_softc_t *sc; 1175 ohci_soft_td_t *std; 1176 { 1177 LIST_REMOVE(std, hnext); 1178 } 1179 1180 ohci_soft_td_t * 1181 ohci_hash_find_td(sc, a) 1182 ohci_softc_t *sc; 1183 ohci_physaddr_t a; 1184 { 1185 int h = HASH(a); 1186 ohci_soft_td_t *std; 1187 1188 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1189 std != 0; 1190 std = LIST_NEXT(std, hnext)) 1191 if (std->physaddr == a) 1192 return (std); 1193 panic("ohci_hash_find_td: addr 0x%08lx not found\n", (u_long)a); 1194 } 1195 1196 void 1197 ohci_timeout(addr) 1198 void *addr; 1199 { 1200 #if 0 1201 usbd_request_handle *reqh = addr; 1202 int s; 1203 1204 DPRINTF(("ohci_timeout: reqh=%p\n", reqh)); 1205 s = splusb(); 1206 /* XXX need to inactivate TD before calling interrupt routine */ 1207 ohci_XXX_done(reqh); 1208 splx(s); 1209 #endif 1210 } 1211 1212 #ifdef USB_DEBUG 1213 void 1214 ohci_dump_tds(std) 1215 ohci_soft_td_t *std; 1216 { 1217 for (; std; std = std->nexttd) 1218 ohci_dump_td(std); 1219 } 1220 1221 void 1222 ohci_dump_td(std) 1223 ohci_soft_td_t *std; 1224 { 1225 printf("TD(%p) at %08lx: %b delay=%d ec=%d cc=%d\ncbp=0x%08lx " 1226 "nexttd=0x%08lx be=0x%08lx\n", 1227 std, (u_long)std->physaddr, 1228 (u_long)LE(std->td->td_flags), 1229 "\20\23R\24OUT\25IN\31TOG1\32SETTOGGLE", 1230 OHCI_TD_GET_DI(LE(std->td->td_flags)), 1231 OHCI_TD_GET_EC(LE(std->td->td_flags)), 1232 OHCI_TD_GET_CC(LE(std->td->td_flags)), 1233 (u_long)LE(std->td->td_cbp), 1234 (u_long)LE(std->td->td_nexttd), (u_long)LE(std->td->td_be)); 1235 } 1236 1237 void 1238 ohci_dump_ed(sed) 1239 ohci_soft_ed_t *sed; 1240 { 1241 printf("ED(%p) at %08lx: addr=%d endpt=%d maxp=%d %b\ntailp=0x%08lx " 1242 "headp=%b nexted=0x%08lx\n", 1243 sed, (u_long)sed->physaddr, 1244 OHCI_ED_GET_FA(LE(sed->ed->ed_flags)), 1245 OHCI_ED_GET_EN(LE(sed->ed->ed_flags)), 1246 OHCI_ED_GET_MAXP(LE(sed->ed->ed_flags)), 1247 (u_long)LE(sed->ed->ed_flags), 1248 "\20\14OUT\15IN\16LOWSPEED\17SKIP\20ISO", 1249 (u_long)LE(sed->ed->ed_tailp), 1250 (u_long)LE(sed->ed->ed_headp), "\20\1HALT\2CARRY", 1251 (u_long)LE(sed->ed->ed_nexted)); 1252 } 1253 #endif 1254 1255 usbd_status 1256 ohci_open(pipe) 1257 usbd_pipe_handle pipe; 1258 { 1259 usbd_device_handle dev = pipe->device; 1260 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 1261 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1262 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 1263 u_int8_t addr = dev->address; 1264 ohci_soft_ed_t *sed; 1265 ohci_soft_td_t *std; 1266 usbd_status r; 1267 int s; 1268 1269 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1270 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1271 if (addr == sc->sc_addr) { 1272 switch (ed->bEndpointAddress) { 1273 case USB_CONTROL_ENDPOINT: 1274 pipe->methods = &ohci_root_ctrl_methods; 1275 break; 1276 case UE_IN | OHCI_INTR_ENDPT: 1277 pipe->methods = &ohci_root_intr_methods; 1278 break; 1279 default: 1280 return (USBD_INVAL); 1281 } 1282 } else { 1283 sed = ohci_alloc_sed(sc); 1284 if (sed == 0) 1285 goto bad0; 1286 std = ohci_alloc_std(sc); 1287 if (std == 0) 1288 goto bad1; 1289 opipe->sed = sed; 1290 opipe->tail = std; 1291 sed->ed->ed_flags = LE( 1292 OHCI_ED_SET_FA(addr) | 1293 OHCI_ED_SET_EN(ed->bEndpointAddress) | 1294 OHCI_ED_DIR_TD | 1295 (dev->lowspeed ? OHCI_ED_SPEED : 0) | 1296 ((ed->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS ? 1297 OHCI_ED_FORMAT_ISO : OHCI_ED_FORMAT_GEN) | 1298 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 1299 sed->ed->ed_headp = sed->ed->ed_tailp = LE(std->physaddr); 1300 1301 switch (ed->bmAttributes & UE_XFERTYPE) { 1302 case UE_CONTROL: 1303 pipe->methods = &ohci_device_ctrl_methods; 1304 r = usb_allocmem(sc->sc_dmatag, 1305 sizeof(usb_device_request_t), 1306 0, &opipe->u.ctl.reqdma); 1307 if (r != USBD_NORMAL_COMPLETION) 1308 goto bad; 1309 s = splusb(); 1310 ohci_add_ed(sed, sc->sc_ctrl_head); 1311 splx(s); 1312 break; 1313 case UE_INTERRUPT: 1314 pipe->methods = &ohci_device_intr_methods; 1315 return (ohci_device_setintr(sc, opipe, ed->bInterval)); 1316 case UE_ISOCHRONOUS: 1317 printf("ohci_open: open iso unimplemented\n"); 1318 return (USBD_XXX); 1319 case UE_BULK: 1320 pipe->methods = &ohci_device_bulk_methods; 1321 s = splusb(); 1322 ohci_add_ed(sed, sc->sc_bulk_head); 1323 splx(s); 1324 break; 1325 } 1326 } 1327 return (USBD_NORMAL_COMPLETION); 1328 1329 bad: 1330 ohci_free_std(sc, std); 1331 bad1: 1332 ohci_free_sed(sc, sed); 1333 bad0: 1334 return (USBD_NOMEM); 1335 1336 } 1337 1338 /* 1339 * Data structures and routines to emulate the root hub. 1340 */ 1341 usb_device_descriptor_t ohci_devd = { 1342 USB_DEVICE_DESCRIPTOR_SIZE, 1343 UDESC_DEVICE, /* type */ 1344 {0x00, 0x01}, /* USB version */ 1345 UCLASS_HUB, /* class */ 1346 USUBCLASS_HUB, /* subclass */ 1347 0, /* protocol */ 1348 64, /* max packet */ 1349 {0},{0},{0x00,0x01}, /* device id */ 1350 1,2,0, /* string indicies */ 1351 1 /* # of configurations */ 1352 }; 1353 1354 usb_config_descriptor_t ohci_confd = { 1355 USB_CONFIG_DESCRIPTOR_SIZE, 1356 UDESC_CONFIG, 1357 {USB_CONFIG_DESCRIPTOR_SIZE + 1358 USB_INTERFACE_DESCRIPTOR_SIZE + 1359 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1360 1, 1361 1, 1362 0, 1363 UC_SELF_POWERED, 1364 0 /* max power */ 1365 }; 1366 1367 usb_interface_descriptor_t ohci_ifcd = { 1368 USB_INTERFACE_DESCRIPTOR_SIZE, 1369 UDESC_INTERFACE, 1370 0, 1371 0, 1372 1, 1373 UCLASS_HUB, 1374 USUBCLASS_HUB, 1375 0, 1376 0 1377 }; 1378 1379 usb_endpoint_descriptor_t ohci_endpd = { 1380 USB_ENDPOINT_DESCRIPTOR_SIZE, 1381 UDESC_ENDPOINT, 1382 UE_IN | OHCI_INTR_ENDPT, 1383 UE_INTERRUPT, 1384 {8, 0}, /* max packet */ 1385 255 1386 }; 1387 1388 usb_hub_descriptor_t ohci_hubd = { 1389 USB_HUB_DESCRIPTOR_SIZE, 1390 UDESC_HUB, 1391 0, 1392 {0,0}, 1393 0, 1394 0, 1395 {0}, 1396 }; 1397 1398 int 1399 ohci_str(p, l, s) 1400 usb_string_descriptor_t *p; 1401 int l; 1402 char *s; 1403 { 1404 int i; 1405 1406 if (l == 0) 1407 return (0); 1408 p->bLength = 2 * strlen(s) + 2; 1409 if (l == 1) 1410 return (1); 1411 p->bDescriptorType = UDESC_STRING; 1412 l -= 2; 1413 for (i = 0; s[i] && l > 1; i++, l -= 2) 1414 USETW2(p->bString[i], 0, s[i]); 1415 return (2*i+2); 1416 } 1417 1418 /* 1419 * Simulate a hardware hub by handling all the necessary requests. 1420 */ 1421 usbd_status 1422 ohci_root_ctrl_transfer(reqh) 1423 usbd_request_handle reqh; 1424 { 1425 int s; 1426 usbd_status r; 1427 1428 s = splusb(); 1429 r = usb_insert_transfer(reqh); 1430 splx(s); 1431 if (r != USBD_NORMAL_COMPLETION) 1432 return (r); 1433 else 1434 return (ohci_root_ctrl_start(reqh)); 1435 } 1436 1437 usbd_status 1438 ohci_root_ctrl_start(reqh) 1439 usbd_request_handle reqh; 1440 { 1441 ohci_softc_t *sc = (ohci_softc_t *)reqh->pipe->device->bus; 1442 usb_device_request_t *req; 1443 void *buf; 1444 int port, i; 1445 int len, value, index, l, totlen = 0; 1446 usb_port_status_t ps; 1447 usb_hub_descriptor_t hubd; 1448 usbd_status r; 1449 u_int32_t v; 1450 1451 if (!reqh->isreq) 1452 /* XXX panic */ 1453 return (USBD_INVAL); 1454 req = &reqh->request; 1455 buf = reqh->buffer; 1456 1457 DPRINTFN(4,("ohci_root_ctrl_control type=0x%02x request=%02x\n", 1458 req->bmRequestType, req->bRequest)); 1459 1460 len = UGETW(req->wLength); 1461 value = UGETW(req->wValue); 1462 index = UGETW(req->wIndex); 1463 #define C(x,y) ((x) | ((y) << 8)) 1464 switch(C(req->bRequest, req->bmRequestType)) { 1465 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 1466 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 1467 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 1468 /* 1469 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 1470 * for the integrated root hub. 1471 */ 1472 break; 1473 case C(UR_GET_CONFIG, UT_READ_DEVICE): 1474 if (len > 0) { 1475 *(u_int8_t *)buf = sc->sc_conf; 1476 totlen = 1; 1477 } 1478 break; 1479 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 1480 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value)); 1481 switch(value >> 8) { 1482 case UDESC_DEVICE: 1483 if ((value & 0xff) != 0) { 1484 r = USBD_IOERROR; 1485 goto ret; 1486 } 1487 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1488 USETW(ohci_devd.idVendor, sc->sc_id_vendor); 1489 memcpy(buf, &ohci_devd, l); 1490 break; 1491 case UDESC_CONFIG: 1492 if ((value & 0xff) != 0) { 1493 r = USBD_IOERROR; 1494 goto ret; 1495 } 1496 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 1497 memcpy(buf, &ohci_confd, l); 1498 buf = (char *)buf + l; 1499 len -= l; 1500 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 1501 totlen += l; 1502 memcpy(buf, &ohci_ifcd, l); 1503 buf = (char *)buf + l; 1504 len -= l; 1505 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 1506 totlen += l; 1507 memcpy(buf, &ohci_endpd, l); 1508 break; 1509 case UDESC_STRING: 1510 if (len == 0) 1511 break; 1512 *(u_int8_t *)buf = 0; 1513 totlen = 1; 1514 switch (value & 0xff) { 1515 case 1: /* Vendor */ 1516 totlen = ohci_str(buf, len, sc->sc_vendor); 1517 break; 1518 case 2: /* Product */ 1519 totlen = ohci_str(buf, len, "OHCI root hub"); 1520 break; 1521 } 1522 break; 1523 default: 1524 r = USBD_IOERROR; 1525 goto ret; 1526 } 1527 break; 1528 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 1529 if (len > 0) { 1530 *(u_int8_t *)buf = 0; 1531 totlen = 1; 1532 } 1533 break; 1534 case C(UR_GET_STATUS, UT_READ_DEVICE): 1535 if (len > 1) { 1536 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 1537 totlen = 2; 1538 } 1539 break; 1540 case C(UR_GET_STATUS, UT_READ_INTERFACE): 1541 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 1542 if (len > 1) { 1543 USETW(((usb_status_t *)buf)->wStatus, 0); 1544 totlen = 2; 1545 } 1546 break; 1547 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 1548 if (value >= USB_MAX_DEVICES) { 1549 r = USBD_IOERROR; 1550 goto ret; 1551 } 1552 sc->sc_addr = value; 1553 break; 1554 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 1555 if (value != 0 && value != 1) { 1556 r = USBD_IOERROR; 1557 goto ret; 1558 } 1559 sc->sc_conf = value; 1560 break; 1561 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 1562 break; 1563 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 1564 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 1565 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 1566 r = USBD_IOERROR; 1567 goto ret; 1568 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 1569 break; 1570 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 1571 break; 1572 /* Hub requests */ 1573 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 1574 break; 1575 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 1576 DPRINTFN(8, ("ohci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 1577 "port=%d feature=%d\n", 1578 index, value)); 1579 if (index < 1 || index > sc->sc_noport) { 1580 r = USBD_IOERROR; 1581 goto ret; 1582 } 1583 port = OHCI_RH_PORT_STATUS(index); 1584 switch(value) { 1585 case UHF_PORT_ENABLE: 1586 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 1587 break; 1588 case UHF_PORT_SUSPEND: 1589 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 1590 break; 1591 case UHF_PORT_POWER: 1592 OWRITE4(sc, port, UPS_LOW_SPEED); 1593 break; 1594 case UHF_C_PORT_CONNECTION: 1595 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 1596 break; 1597 case UHF_C_PORT_ENABLE: 1598 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 1599 break; 1600 case UHF_C_PORT_SUSPEND: 1601 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 1602 break; 1603 case UHF_C_PORT_OVER_CURRENT: 1604 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 1605 break; 1606 case UHF_C_PORT_RESET: 1607 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 1608 break; 1609 default: 1610 r = USBD_IOERROR; 1611 goto ret; 1612 } 1613 switch(value) { 1614 case UHF_C_PORT_CONNECTION: 1615 case UHF_C_PORT_ENABLE: 1616 case UHF_C_PORT_SUSPEND: 1617 case UHF_C_PORT_OVER_CURRENT: 1618 case UHF_C_PORT_RESET: 1619 /* Enable RHSC interrupt if condition is cleared. */ 1620 if ((OREAD4(sc, port) >> 16) == 0) 1621 ohci_rhsc_able(sc, 1); 1622 break; 1623 default: 1624 break; 1625 } 1626 break; 1627 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 1628 if (value != 0) { 1629 r = USBD_IOERROR; 1630 goto ret; 1631 } 1632 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 1633 hubd = ohci_hubd; 1634 hubd.bNbrPorts = sc->sc_noport; 1635 USETW(hubd.wHubCharacteristics, 1636 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 1637 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 1638 /* XXX overcurrent */ 1639 ); 1640 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 1641 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 1642 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 1643 hubd.DeviceRemovable[i++] = (u_int8_t)v; 1644 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 1645 l = min(len, hubd.bDescLength); 1646 totlen = l; 1647 memcpy(buf, &hubd, l); 1648 break; 1649 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 1650 if (len != 4) { 1651 r = USBD_IOERROR; 1652 goto ret; 1653 } 1654 memset(buf, 0, len); /* ? XXX */ 1655 totlen = len; 1656 break; 1657 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 1658 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n", 1659 index)); 1660 if (index < 1 || index > sc->sc_noport) { 1661 r = USBD_IOERROR; 1662 goto ret; 1663 } 1664 if (len != 4) { 1665 r = USBD_IOERROR; 1666 goto ret; 1667 } 1668 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 1669 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n", 1670 v)); 1671 USETW(ps.wPortStatus, v); 1672 USETW(ps.wPortChange, v >> 16); 1673 l = min(len, sizeof ps); 1674 memcpy(buf, &ps, l); 1675 totlen = l; 1676 break; 1677 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 1678 r = USBD_IOERROR; 1679 goto ret; 1680 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 1681 break; 1682 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 1683 if (index < 1 || index > sc->sc_noport) { 1684 r = USBD_IOERROR; 1685 goto ret; 1686 } 1687 port = OHCI_RH_PORT_STATUS(index); 1688 switch(value) { 1689 case UHF_PORT_ENABLE: 1690 OWRITE4(sc, port, UPS_PORT_ENABLED); 1691 break; 1692 case UHF_PORT_SUSPEND: 1693 OWRITE4(sc, port, UPS_SUSPEND); 1694 break; 1695 case UHF_PORT_RESET: 1696 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n", 1697 index)); 1698 OWRITE4(sc, port, UPS_RESET); 1699 for (i = 0; i < 10; i++) { 1700 usb_delay_ms(&sc->sc_bus, 10); 1701 if ((OREAD4(sc, port) & UPS_RESET) == 0) 1702 break; 1703 } 1704 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n", 1705 index, OREAD4(sc, port))); 1706 break; 1707 case UHF_PORT_POWER: 1708 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power " 1709 "%d\n", index)); 1710 OWRITE4(sc, port, UPS_PORT_POWER); 1711 break; 1712 default: 1713 r = USBD_IOERROR; 1714 goto ret; 1715 } 1716 break; 1717 default: 1718 r = USBD_IOERROR; 1719 goto ret; 1720 } 1721 reqh->actlen = totlen; 1722 r = USBD_NORMAL_COMPLETION; 1723 ret: 1724 reqh->status = r; 1725 reqh->xfercb(reqh); 1726 usb_start_next(reqh->pipe); 1727 return (USBD_IN_PROGRESS); 1728 } 1729 1730 /* Abort a root control request. */ 1731 void 1732 ohci_root_ctrl_abort(reqh) 1733 usbd_request_handle reqh; 1734 { 1735 /* Nothing to do, all transfers are synchronous. */ 1736 } 1737 1738 /* Close the root pipe. */ 1739 void 1740 ohci_root_ctrl_close(pipe) 1741 usbd_pipe_handle pipe; 1742 { 1743 DPRINTF(("ohci_root_ctrl_close\n")); 1744 } 1745 1746 usbd_status 1747 ohci_root_intr_transfer(reqh) 1748 usbd_request_handle reqh; 1749 { 1750 int s; 1751 usbd_status r; 1752 1753 s = splusb(); 1754 r = usb_insert_transfer(reqh); 1755 splx(s); 1756 if (r != USBD_NORMAL_COMPLETION) 1757 return (r); 1758 else 1759 return (ohci_root_intr_start(reqh)); 1760 } 1761 1762 usbd_status 1763 ohci_root_intr_start(reqh) 1764 usbd_request_handle reqh; 1765 { 1766 usbd_pipe_handle pipe = reqh->pipe; 1767 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 1768 struct ohci_pipe *upipe = (struct ohci_pipe *)pipe; 1769 usb_dma_t *dmap; 1770 usbd_status r; 1771 int len; 1772 1773 len = reqh->length; 1774 dmap = &upipe->u.intr.datadma; 1775 if (len == 0) 1776 return (USBD_INVAL); /* XXX should it be? */ 1777 1778 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap); 1779 if (r != USBD_NORMAL_COMPLETION) 1780 return (r); 1781 sc->sc_intrreqh = reqh; 1782 1783 return (USBD_IN_PROGRESS); 1784 } 1785 1786 /* Abort a root interrupt request. */ 1787 void 1788 ohci_root_intr_abort(reqh) 1789 usbd_request_handle reqh; 1790 { 1791 /* No need to abort. */ 1792 } 1793 1794 /* Close the root pipe. */ 1795 void 1796 ohci_root_intr_close(pipe) 1797 usbd_pipe_handle pipe; 1798 { 1799 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 1800 sc->sc_intrreqh = 0; 1801 1802 DPRINTF(("ohci_root_intr_close\n")); 1803 } 1804 1805 /************************/ 1806 1807 usbd_status 1808 ohci_device_ctrl_transfer(reqh) 1809 usbd_request_handle reqh; 1810 { 1811 int s; 1812 usbd_status r; 1813 1814 s = splusb(); 1815 r = usb_insert_transfer(reqh); 1816 splx(s); 1817 if (r != USBD_NORMAL_COMPLETION) 1818 return (r); 1819 else 1820 return (ohci_device_ctrl_start(reqh)); 1821 } 1822 1823 usbd_status 1824 ohci_device_ctrl_start(reqh) 1825 usbd_request_handle reqh; 1826 { 1827 ohci_softc_t *sc = (ohci_softc_t *)reqh->pipe->device->bus; 1828 usbd_status r; 1829 1830 if (!reqh->isreq) { 1831 /* XXX panic */ 1832 printf("ohci_device_ctrl_transfer: not a request\n"); 1833 return (USBD_INVAL); 1834 } 1835 1836 r = ohci_device_request(reqh); 1837 if (r != USBD_NORMAL_COMPLETION) 1838 return (r); 1839 1840 if (sc->sc_bus.use_polling) 1841 ohci_waitintr(sc, reqh); 1842 return (USBD_IN_PROGRESS); 1843 } 1844 1845 /* Abort a device control request. */ 1846 void 1847 ohci_device_ctrl_abort(reqh) 1848 usbd_request_handle reqh; 1849 { 1850 /* XXX inactivate */ 1851 usb_delay_ms(reqh->pipe->device->bus, 1); /* make sure it is donw */ 1852 /* XXX call done */ 1853 } 1854 1855 /* Close a device control pipe. */ 1856 void 1857 ohci_device_ctrl_close(pipe) 1858 usbd_pipe_handle pipe; 1859 { 1860 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 1861 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 1862 ohci_soft_ed_t *sed = opipe->sed; 1863 int s; 1864 1865 s = splusb(); 1866 sed->ed->ed_flags |= LE(OHCI_ED_SKIP); 1867 if ((LE(sed->ed->ed_tailp) & OHCI_TAILMASK) != LE(sed->ed->ed_headp)) 1868 usb_delay_ms(&sc->sc_bus, 2); 1869 ohci_rem_ed(sed, sc->sc_ctrl_head); 1870 splx(s); 1871 ohci_free_std(sc, opipe->tail); 1872 ohci_free_sed(sc, opipe->sed); 1873 /* XXX free other resources */ 1874 } 1875 1876 /************************/ 1877 1878 usbd_status 1879 ohci_device_bulk_transfer(reqh) 1880 usbd_request_handle reqh; 1881 { 1882 int s; 1883 usbd_status r; 1884 1885 s = splusb(); 1886 r = usb_insert_transfer(reqh); 1887 splx(s); 1888 if (r != USBD_NORMAL_COMPLETION) 1889 return (r); 1890 else 1891 return (ohci_device_bulk_start(reqh)); 1892 } 1893 1894 usbd_status 1895 ohci_device_bulk_start(reqh) 1896 usbd_request_handle reqh; 1897 { 1898 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 1899 usbd_device_handle dev = opipe->pipe.device; 1900 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 1901 int addr = dev->address; 1902 ohci_soft_td_t *xfer, *tail; 1903 ohci_soft_ed_t *sed; 1904 usb_dma_t *dmap; 1905 usbd_status r; 1906 int s, len, isread; 1907 1908 if (reqh->isreq) { 1909 /* XXX panic */ 1910 printf("ohci_device_bulk_transfer: a request\n"); 1911 return (USBD_INVAL); 1912 } 1913 1914 len = reqh->length; 1915 dmap = &opipe->u.bulk.datadma; 1916 isread = reqh->pipe->endpoint->edesc->bEndpointAddress & UE_IN; 1917 sed = opipe->sed; 1918 1919 opipe->u.bulk.isread = isread; 1920 opipe->u.bulk.length = len; 1921 1922 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap); 1923 if (r != USBD_NORMAL_COMPLETION) 1924 goto ret1; 1925 1926 tail = ohci_alloc_std(sc); 1927 if (!tail) { 1928 r = USBD_NOMEM; 1929 goto ret2; 1930 } 1931 tail->reqh = 0; 1932 1933 /* Update device address */ 1934 sed->ed->ed_flags = LE( 1935 (LE(sed->ed->ed_flags) & ~OHCI_ED_ADDRMASK) | 1936 OHCI_ED_SET_FA(addr)); 1937 1938 /* Set up data transaction */ 1939 xfer = opipe->tail; 1940 xfer->td->td_flags = LE( 1941 (isread ? OHCI_TD_IN : OHCI_TD_OUT) | OHCI_TD_NOCC | 1942 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY | 1943 (reqh->flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0)); 1944 xfer->td->td_cbp = LE(DMAADDR(dmap)); 1945 xfer->nexttd = tail; 1946 xfer->td->td_nexttd = LE(tail->physaddr); 1947 xfer->td->td_be = LE(LE(xfer->td->td_cbp) + len - 1); 1948 xfer->len = len; 1949 xfer->reqh = reqh; 1950 1951 reqh->hcpriv = xfer; 1952 1953 if (!isread) 1954 memcpy(KERNADDR(dmap), reqh->buffer, len); 1955 1956 /* Insert ED in schedule */ 1957 s = splusb(); 1958 ohci_hash_add_td(sc, xfer); 1959 sed->ed->ed_tailp = LE(tail->physaddr); 1960 opipe->tail = tail; 1961 sed->ed->ed_flags &= LE(~OHCI_ED_SKIP); /* XXX why */ 1962 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 1963 if (reqh->timeout && !sc->sc_bus.use_polling) { 1964 usb_timeout(ohci_timeout, reqh, 1965 MS_TO_TICKS(reqh->timeout), reqh->timo_handle); 1966 } 1967 splx(s); 1968 1969 return (USBD_IN_PROGRESS); 1970 1971 ret2: 1972 usb_freemem(sc->sc_dmatag, dmap); 1973 ret1: 1974 return (r); 1975 } 1976 1977 /* Abort a device bulk request. */ 1978 void 1979 ohci_device_bulk_abort(reqh) 1980 usbd_request_handle reqh; 1981 { 1982 #if 0 1983 sed->ed->ed_flags |= LE(OHCI_ED_SKIP); 1984 if ((LE(sed->ed->ed_tailp) & OHCI_TAILMASK) != LE(sed->ed->ed_headp)) 1985 usb_delay_ms(reqh->pipe->device->bus, 2); 1986 #endif 1987 /* XXX inactivate */ 1988 usb_delay_ms(reqh->pipe->device->bus, 1); /* make sure it is done */ 1989 /* XXX call done */ 1990 } 1991 1992 /* Close a device bulk pipe. */ 1993 void 1994 ohci_device_bulk_close(pipe) 1995 usbd_pipe_handle pipe; 1996 { 1997 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 1998 usbd_device_handle dev = opipe->pipe.device; 1999 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 2000 int s; 2001 2002 s = splusb(); 2003 ohci_rem_ed(opipe->sed, sc->sc_bulk_head); 2004 splx(s); 2005 ohci_free_std(sc, opipe->tail); 2006 ohci_free_sed(sc, opipe->sed); 2007 /* XXX free other resources */ 2008 } 2009 2010 /************************/ 2011 2012 usbd_status 2013 ohci_device_intr_transfer(reqh) 2014 usbd_request_handle reqh; 2015 { 2016 int s; 2017 usbd_status r; 2018 2019 s = splusb(); 2020 r = usb_insert_transfer(reqh); 2021 splx(s); 2022 if (r != USBD_NORMAL_COMPLETION) 2023 return (r); 2024 else 2025 return (ohci_device_intr_start(reqh)); 2026 } 2027 2028 usbd_status 2029 ohci_device_intr_start(reqh) 2030 usbd_request_handle reqh; 2031 { 2032 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 2033 usbd_device_handle dev = opipe->pipe.device; 2034 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 2035 ohci_soft_ed_t *sed = opipe->sed; 2036 ohci_soft_td_t *xfer, *tail; 2037 usb_dma_t *dmap; 2038 usbd_status r; 2039 int len; 2040 int s; 2041 2042 DPRINTFN(3, ("ohci_device_intr_transfer: reqh=%p buf=%p len=%d " 2043 "flags=%d priv=%p\n", 2044 reqh, reqh->buffer, reqh->length, reqh->flags, reqh->priv)); 2045 2046 if (reqh->isreq) 2047 panic("ohci_device_intr_transfer: a request\n"); 2048 2049 len = reqh->length; 2050 dmap = &opipe->u.intr.datadma; 2051 if (len == 0) 2052 return (USBD_INVAL); /* XXX should it be? */ 2053 2054 xfer = opipe->tail; 2055 tail = ohci_alloc_std(sc); 2056 if (!tail) { 2057 r = USBD_NOMEM; 2058 goto ret1; 2059 } 2060 tail->reqh = 0; 2061 2062 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap); 2063 if (r != USBD_NORMAL_COMPLETION) 2064 goto ret2; 2065 2066 xfer->td->td_flags = LE( 2067 OHCI_TD_IN | OHCI_TD_NOCC | 2068 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 2069 if (reqh->flags & USBD_SHORT_XFER_OK) 2070 xfer->td->td_flags |= LE(OHCI_TD_R); 2071 xfer->td->td_cbp = LE(DMAADDR(dmap)); 2072 xfer->nexttd = tail; 2073 xfer->td->td_nexttd = LE(tail->physaddr); 2074 xfer->td->td_be = LE(LE(xfer->td->td_cbp) + len - 1); 2075 xfer->len = len; 2076 xfer->reqh = reqh; 2077 2078 reqh->hcpriv = xfer; 2079 2080 #if USB_DEBUG 2081 if (ohcidebug > 5) { 2082 printf("ohci_device_intr_transfer:\n"); 2083 ohci_dump_ed(sed); 2084 ohci_dump_tds(xfer); 2085 } 2086 #endif 2087 2088 /* Insert ED in schedule */ 2089 s = splusb(); 2090 ohci_hash_add_td(sc, xfer); 2091 sed->ed->ed_tailp = LE(tail->physaddr); 2092 opipe->tail = tail; 2093 #if 0 2094 if (reqh->timeout && !sc->sc_bus.use_polling) { 2095 usb_timeout(ohci_timeout, reqh, 2096 MS_TO_TICKS(reqh->timeout), reqh->timo_handle); 2097 } 2098 #endif 2099 sed->ed->ed_flags &= LE(~OHCI_ED_SKIP); 2100 2101 #ifdef USB_DEBUG 2102 if (ohcidebug > 5) { 2103 delay(5000); 2104 printf("ohci_device_intr_transfer: status=%x\n", 2105 OREAD4(sc, OHCI_COMMAND_STATUS)); 2106 ohci_dump_ed(sed); 2107 ohci_dump_tds(xfer); 2108 } 2109 #endif 2110 splx(s); 2111 2112 return (USBD_IN_PROGRESS); 2113 2114 ret2: 2115 ohci_free_std(sc, xfer); 2116 ret1: 2117 return (r); 2118 } 2119 2120 /* Abort a device control request. */ 2121 void 2122 ohci_device_intr_abort(reqh) 2123 usbd_request_handle reqh; 2124 { 2125 /* XXX inactivate */ 2126 usb_delay_ms(reqh->pipe->device->bus, 1); /* make sure it is done */ 2127 if (reqh->pipe->intrreqh == reqh) { 2128 DPRINTF(("ohci_device_intr_abort: remove\n")); 2129 reqh->pipe->intrreqh = 0; 2130 ohci_intr_done((ohci_softc_t *)reqh->pipe->device->bus, reqh); 2131 } 2132 } 2133 2134 /* Close a device interrupt pipe. */ 2135 void 2136 ohci_device_intr_close(pipe) 2137 usbd_pipe_handle pipe; 2138 { 2139 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2140 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 2141 int nslots = opipe->u.intr.nslots; 2142 int pos = opipe->u.intr.pos; 2143 int j; 2144 ohci_soft_ed_t *p, *sed = opipe->sed; 2145 int s; 2146 2147 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n", 2148 pipe, nslots, pos)); 2149 s = splusb(); 2150 sed->ed->ed_flags |= LE(OHCI_ED_SKIP); 2151 if ((sed->ed->ed_tailp & LE(OHCI_TAILMASK)) != sed->ed->ed_headp) 2152 usb_delay_ms(&sc->sc_bus, 2); 2153 2154 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 2155 ; 2156 if (!p) 2157 panic("ohci_device_intr_close: ED not found\n"); 2158 p->next = sed->next; 2159 p->ed->ed_nexted = sed->ed->ed_nexted; 2160 splx(s); 2161 2162 for (j = 0; j < nslots; j++) 2163 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 2164 2165 ohci_free_std(sc, opipe->tail); 2166 ohci_free_sed(sc, opipe->sed); 2167 /* XXX free other resources */ 2168 } 2169 2170 usbd_status 2171 ohci_device_setintr(sc, opipe, ival) 2172 ohci_softc_t *sc; 2173 struct ohci_pipe *opipe; 2174 int ival; 2175 { 2176 int i, j, s, best; 2177 u_int npoll, slow, shigh, nslots; 2178 u_int bestbw, bw; 2179 ohci_soft_ed_t *hsed, *sed = opipe->sed; 2180 2181 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe)); 2182 if (ival == 0) { 2183 printf("ohci_setintr: 0 interval\n"); 2184 return (USBD_INVAL); 2185 } 2186 2187 npoll = OHCI_NO_INTRS; 2188 while (npoll > ival) 2189 npoll /= 2; 2190 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll)); 2191 2192 /* 2193 * We now know which level in the tree the ED must go into. 2194 * Figure out which slot has most bandwidth left over. 2195 * Slots to examine: 2196 * npoll 2197 * 1 0 2198 * 2 1 2 2199 * 4 3 4 5 6 2200 * 8 7 8 9 10 11 12 13 14 2201 * N (N-1) .. (N-1+N-1) 2202 */ 2203 slow = npoll-1; 2204 shigh = slow + npoll; 2205 nslots = OHCI_NO_INTRS / npoll; 2206 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 2207 bw = 0; 2208 for (j = 0; j < nslots; j++) 2209 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 2210 if (bw < bestbw) { 2211 best = i; 2212 bestbw = bw; 2213 } 2214 } 2215 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n", 2216 best, slow, shigh, bestbw)); 2217 2218 s = splusb(); 2219 hsed = sc->sc_eds[best]; 2220 sed->next = hsed->next; 2221 sed->ed->ed_nexted = hsed->ed->ed_nexted; 2222 hsed->next = sed; 2223 hsed->ed->ed_nexted = LE(sed->physaddr); 2224 splx(s); 2225 2226 for (j = 0; j < nslots; j++) 2227 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 2228 opipe->u.intr.nslots = nslots; 2229 opipe->u.intr.pos = best; 2230 2231 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe)); 2232 return (USBD_NORMAL_COMPLETION); 2233 } 2234 2235
Indexes created Thu Sep 25 08:09:54 GMT 2025