ohci.c revision 1.323.4.2
1 /* $NetBSD: ohci.c,v 1.323.4.2 2024/10/02 12:19:37 martin Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012, 2016, 2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca), 10 * Matthew R. Green (mrg (at) eterna.com.au), and Nick Hudson. 11 * 12 * This code is derived from software contributed to The NetBSD Foundation 13 * by Charles M. Hannum. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * USB Open Host Controller driver. 39 * 40 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 41 * USB spec: http://www.usb.org/developers/docs/ 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.323.4.2 2024/10/02 12:19:37 martin Exp $"); 46 47 #ifdef _KERNEL_OPT 48 #include "opt_usb.h" 49 #endif 50 51 #include <sys/param.h> 52 53 #include <sys/cpu.h> 54 #include <sys/device.h> 55 #include <sys/kernel.h> 56 #include <sys/kmem.h> 57 #include <sys/proc.h> 58 #include <sys/queue.h> 59 #include <sys/select.h> 60 #include <sys/sysctl.h> 61 #include <sys/systm.h> 62 63 #include <machine/endian.h> 64 65 #include <dev/usb/usb.h> 66 #include <dev/usb/usbdi.h> 67 #include <dev/usb/usbdivar.h> 68 #include <dev/usb/usb_mem.h> 69 #include <dev/usb/usb_quirks.h> 70 71 #include <dev/usb/ohcireg.h> 72 #include <dev/usb/ohcivar.h> 73 #include <dev/usb/usbroothub.h> 74 #include <dev/usb/usbhist.h> 75 76 #ifdef USB_DEBUG 77 #ifndef OHCI_DEBUG 78 #define ohcidebug 0 79 #else 80 static int ohcidebug = 0; 81 82 SYSCTL_SETUP(sysctl_hw_ohci_setup, "sysctl hw.ohci setup") 83 { 84 int err; 85 const struct sysctlnode *rnode; 86 const struct sysctlnode *cnode; 87 88 err = sysctl_createv(clog, 0, NULL, &rnode, 89 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ohci", 90 SYSCTL_DESCR("ohci global controls"), 91 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 92 93 if (err) 94 goto fail; 95 96 /* control debugging printfs */ 97 err = sysctl_createv(clog, 0, &rnode, &cnode, 98 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 99 "debug", SYSCTL_DESCR("Enable debugging output"), 100 NULL, 0, &ohcidebug, sizeof(ohcidebug), CTL_CREATE, CTL_EOL); 101 if (err) 102 goto fail; 103 104 return; 105 fail: 106 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 107 } 108 109 #endif /* OHCI_DEBUG */ 110 #endif /* USB_DEBUG */ 111 112 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ohcidebug,FMT,A,B,C,D) 113 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ohcidebug,N,FMT,A,B,C,D) 114 #define OHCIHIST_FUNC() USBHIST_FUNC() 115 #define OHCIHIST_CALLED(name) USBHIST_CALLED(ohcidebug) 116 117 #if BYTE_ORDER == BIG_ENDIAN 118 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 119 #else 120 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 121 #endif 122 123 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 124 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 125 #define HTOO16(val) O16TOH(val) 126 #define HTOO32(val) O32TOH(val) 127 128 struct ohci_pipe; 129 130 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 131 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 132 133 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 134 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 135 Static void ohci_free_std_locked(ohci_softc_t *, ohci_soft_td_t *); 136 137 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 138 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 139 Static void ohci_free_sitd_locked(ohci_softc_t *, 140 ohci_soft_itd_t *); 141 142 Static int ohci_alloc_std_chain(ohci_softc_t *, struct usbd_xfer *, 143 int, int); 144 Static void ohci_free_stds(ohci_softc_t *, struct ohci_xfer *); 145 146 Static void ohci_reset_std_chain(ohci_softc_t *, struct usbd_xfer *, 147 int, int, ohci_soft_td_t *, ohci_soft_td_t **); 148 149 Static usbd_status ohci_open(struct usbd_pipe *); 150 Static void ohci_poll(struct usbd_bus *); 151 Static void ohci_softintr(void *); 152 Static void ohci_rhsc(ohci_softc_t *, struct usbd_xfer *); 153 Static void ohci_rhsc_softint(void *); 154 155 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 156 ohci_soft_ed_t *); 157 158 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 159 ohci_soft_ed_t *); 160 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 161 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 162 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 163 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 164 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 165 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 166 167 Static usbd_status ohci_setup_isoc(struct usbd_pipe *); 168 Static void ohci_device_isoc_enter(struct usbd_xfer *); 169 170 Static struct usbd_xfer * 171 ohci_allocx(struct usbd_bus *, unsigned int); 172 Static void ohci_freex(struct usbd_bus *, struct usbd_xfer *); 173 Static bool ohci_dying(struct usbd_bus *); 174 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 175 Static int ohci_roothub_ctrl(struct usbd_bus *, 176 usb_device_request_t *, void *, int); 177 178 Static usbd_status ohci_root_intr_transfer(struct usbd_xfer *); 179 Static usbd_status ohci_root_intr_start(struct usbd_xfer *); 180 Static void ohci_root_intr_abort(struct usbd_xfer *); 181 Static void ohci_root_intr_close(struct usbd_pipe *); 182 Static void ohci_root_intr_done(struct usbd_xfer *); 183 184 Static int ohci_device_ctrl_init(struct usbd_xfer *); 185 Static void ohci_device_ctrl_fini(struct usbd_xfer *); 186 Static usbd_status ohci_device_ctrl_transfer(struct usbd_xfer *); 187 Static usbd_status ohci_device_ctrl_start(struct usbd_xfer *); 188 Static void ohci_device_ctrl_abort(struct usbd_xfer *); 189 Static void ohci_device_ctrl_close(struct usbd_pipe *); 190 Static void ohci_device_ctrl_done(struct usbd_xfer *); 191 192 Static int ohci_device_bulk_init(struct usbd_xfer *); 193 Static void ohci_device_bulk_fini(struct usbd_xfer *); 194 Static usbd_status ohci_device_bulk_transfer(struct usbd_xfer *); 195 Static usbd_status ohci_device_bulk_start(struct usbd_xfer *); 196 Static void ohci_device_bulk_abort(struct usbd_xfer *); 197 Static void ohci_device_bulk_close(struct usbd_pipe *); 198 Static void ohci_device_bulk_done(struct usbd_xfer *); 199 200 Static int ohci_device_intr_init(struct usbd_xfer *); 201 Static void ohci_device_intr_fini(struct usbd_xfer *); 202 Static usbd_status ohci_device_intr_transfer(struct usbd_xfer *); 203 Static usbd_status ohci_device_intr_start(struct usbd_xfer *); 204 Static void ohci_device_intr_abort(struct usbd_xfer *); 205 Static void ohci_device_intr_close(struct usbd_pipe *); 206 Static void ohci_device_intr_done(struct usbd_xfer *); 207 208 Static int ohci_device_isoc_init(struct usbd_xfer *); 209 Static void ohci_device_isoc_fini(struct usbd_xfer *); 210 Static usbd_status ohci_device_isoc_transfer(struct usbd_xfer *); 211 Static void ohci_device_isoc_abort(struct usbd_xfer *); 212 Static void ohci_device_isoc_close(struct usbd_pipe *); 213 Static void ohci_device_isoc_done(struct usbd_xfer *); 214 215 Static usbd_status ohci_device_setintr(ohci_softc_t *, 216 struct ohci_pipe *, int); 217 218 Static void ohci_rhsc_enable(void *); 219 220 Static void ohci_close_pipe(struct usbd_pipe *, ohci_soft_ed_t *); 221 Static void ohci_abortx(struct usbd_xfer *); 222 223 Static void ohci_device_clear_toggle(struct usbd_pipe *); 224 Static void ohci_noop(struct usbd_pipe *); 225 226 #ifdef OHCI_DEBUG 227 Static void ohci_dumpregs(ohci_softc_t *); 228 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 229 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 230 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 231 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 232 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 233 #endif 234 235 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 236 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 237 #define OWRITE1(sc, r, x) \ 238 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 239 #define OWRITE2(sc, r, x) \ 240 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 241 #define OWRITE4(sc, r, x) \ 242 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 243 244 static __inline uint32_t 245 OREAD4(ohci_softc_t *sc, bus_size_t r) 246 { 247 248 OBARR(sc); 249 return bus_space_read_4(sc->iot, sc->ioh, r); 250 } 251 252 /* Reverse the bits in a value 0 .. 31 */ 253 Static uint8_t revbits[OHCI_NO_INTRS] = 254 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 255 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 256 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 257 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 258 259 struct ohci_pipe { 260 struct usbd_pipe pipe; 261 ohci_soft_ed_t *sed; 262 union { 263 ohci_soft_td_t *td; 264 ohci_soft_itd_t *itd; 265 } tail; 266 /* Info needed for different pipe kinds. */ 267 union { 268 /* Control pipe */ 269 struct { 270 usb_dma_t reqdma; 271 } ctrl; 272 /* Interrupt pipe */ 273 struct { 274 int nslots; 275 int pos; 276 } intr; 277 /* Isochronous pipe */ 278 struct isoc { 279 int next, inuse; 280 } isoc; 281 }; 282 }; 283 284 Static const struct usbd_bus_methods ohci_bus_methods = { 285 .ubm_open = ohci_open, 286 .ubm_softint = ohci_softintr, 287 .ubm_dopoll = ohci_poll, 288 .ubm_allocx = ohci_allocx, 289 .ubm_freex = ohci_freex, 290 .ubm_abortx = ohci_abortx, 291 .ubm_dying = ohci_dying, 292 .ubm_getlock = ohci_get_lock, 293 .ubm_rhctrl = ohci_roothub_ctrl, 294 }; 295 296 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 297 .upm_transfer = ohci_root_intr_transfer, 298 .upm_start = ohci_root_intr_start, 299 .upm_abort = ohci_root_intr_abort, 300 .upm_close = ohci_root_intr_close, 301 .upm_cleartoggle = ohci_noop, 302 .upm_done = ohci_root_intr_done, 303 }; 304 305 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 306 .upm_init = ohci_device_ctrl_init, 307 .upm_fini = ohci_device_ctrl_fini, 308 .upm_transfer = ohci_device_ctrl_transfer, 309 .upm_start = ohci_device_ctrl_start, 310 .upm_abort = ohci_device_ctrl_abort, 311 .upm_close = ohci_device_ctrl_close, 312 .upm_cleartoggle = ohci_noop, 313 .upm_done = ohci_device_ctrl_done, 314 }; 315 316 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 317 .upm_init = ohci_device_intr_init, 318 .upm_fini = ohci_device_intr_fini, 319 .upm_transfer = ohci_device_intr_transfer, 320 .upm_start = ohci_device_intr_start, 321 .upm_abort = ohci_device_intr_abort, 322 .upm_close = ohci_device_intr_close, 323 .upm_cleartoggle = ohci_device_clear_toggle, 324 .upm_done = ohci_device_intr_done, 325 }; 326 327 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 328 .upm_init = ohci_device_bulk_init, 329 .upm_fini = ohci_device_bulk_fini, 330 .upm_transfer = ohci_device_bulk_transfer, 331 .upm_start = ohci_device_bulk_start, 332 .upm_abort = ohci_device_bulk_abort, 333 .upm_close = ohci_device_bulk_close, 334 .upm_cleartoggle = ohci_device_clear_toggle, 335 .upm_done = ohci_device_bulk_done, 336 }; 337 338 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 339 .upm_init = ohci_device_isoc_init, 340 .upm_fini = ohci_device_isoc_fini, 341 .upm_transfer = ohci_device_isoc_transfer, 342 .upm_abort = ohci_device_isoc_abort, 343 .upm_close = ohci_device_isoc_close, 344 .upm_cleartoggle = ohci_noop, 345 .upm_done = ohci_device_isoc_done, 346 }; 347 348 int 349 ohci_activate(device_t self, enum devact act) 350 { 351 struct ohci_softc *sc = device_private(self); 352 353 switch (act) { 354 case DVACT_DEACTIVATE: 355 sc->sc_dying = 1; 356 return 0; 357 default: 358 return EOPNOTSUPP; 359 } 360 } 361 362 void 363 ohci_childdet(device_t self, device_t child) 364 { 365 struct ohci_softc *sc = device_private(self); 366 367 KASSERT(sc->sc_child == child); 368 sc->sc_child = NULL; 369 } 370 371 int 372 ohci_detach(struct ohci_softc *sc, int flags) 373 { 374 int rv = 0; 375 376 if (sc->sc_child != NULL) 377 rv = config_detach(sc->sc_child, flags); 378 379 if (rv != 0) 380 return rv; 381 382 softint_disestablish(sc->sc_rhsc_si); 383 384 callout_halt(&sc->sc_tmo_rhsc, NULL); 385 callout_destroy(&sc->sc_tmo_rhsc); 386 387 mutex_destroy(&sc->sc_lock); 388 mutex_destroy(&sc->sc_intr_lock); 389 390 if (sc->sc_hcca != NULL) 391 usb_freemem(&sc->sc_hccadma); 392 pool_cache_destroy(sc->sc_xferpool); 393 cv_destroy(&sc->sc_abort_cv); 394 395 return rv; 396 } 397 398 ohci_soft_ed_t * 399 ohci_alloc_sed(ohci_softc_t *sc) 400 { 401 ohci_soft_ed_t *sed; 402 int i, offs; 403 usb_dma_t dma; 404 405 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 406 407 mutex_enter(&sc->sc_lock); 408 if (sc->sc_freeeds == NULL) { 409 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 410 mutex_exit(&sc->sc_lock); 411 412 int err = usb_allocmem(sc->sc_bus.ub_dmatag, OHCI_SED_SIZE * OHCI_SED_CHUNK, 413 OHCI_ED_ALIGN, 0 /*!USBMALLOC_COHERENT*/, &dma); 414 if (err) 415 return NULL; 416 417 mutex_enter(&sc->sc_lock); 418 for (i = 0; i < OHCI_SED_CHUNK; i++) { 419 offs = i * OHCI_SED_SIZE; 420 sed = KERNADDR(&dma, offs); 421 sed->physaddr = DMAADDR(&dma, offs); 422 sed->dma = dma; 423 sed->offs = offs; 424 sed->next = sc->sc_freeeds; 425 sc->sc_freeeds = sed; 426 } 427 } 428 sed = sc->sc_freeeds; 429 sc->sc_freeeds = sed->next; 430 mutex_exit(&sc->sc_lock); 431 432 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 433 sed->next = 0; 434 return sed; 435 } 436 437 static inline void 438 ohci_free_sed_locked(ohci_softc_t *sc, ohci_soft_ed_t *sed) 439 { 440 441 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 442 443 sed->next = sc->sc_freeeds; 444 sc->sc_freeeds = sed; 445 } 446 447 void 448 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 449 { 450 451 mutex_enter(&sc->sc_lock); 452 ohci_free_sed_locked(sc, sed); 453 mutex_exit(&sc->sc_lock); 454 } 455 456 ohci_soft_td_t * 457 ohci_alloc_std(ohci_softc_t *sc) 458 { 459 ohci_soft_td_t *std; 460 int i, offs; 461 usb_dma_t dma; 462 463 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 464 465 mutex_enter(&sc->sc_lock); 466 if (sc->sc_freetds == NULL) { 467 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 468 mutex_exit(&sc->sc_lock); 469 470 int err = usb_allocmem(sc->sc_bus.ub_dmatag, OHCI_STD_SIZE * OHCI_STD_CHUNK, 471 OHCI_TD_ALIGN, USBMALLOC_COHERENT, &dma); 472 if (err) 473 return NULL; 474 475 mutex_enter(&sc->sc_lock); 476 for (i = 0; i < OHCI_STD_CHUNK; i++) { 477 offs = i * OHCI_STD_SIZE; 478 std = KERNADDR(&dma, offs); 479 std->physaddr = DMAADDR(&dma, offs); 480 std->dma = dma; 481 std->offs = offs; 482 std->nexttd = sc->sc_freetds; 483 sc->sc_freetds = std; 484 } 485 } 486 487 std = sc->sc_freetds; 488 sc->sc_freetds = std->nexttd; 489 mutex_exit(&sc->sc_lock); 490 491 memset(&std->td, 0, sizeof(ohci_td_t)); 492 std->nexttd = NULL; 493 std->xfer = NULL; 494 std->held = NULL; 495 496 return std; 497 } 498 499 void 500 ohci_free_std_locked(ohci_softc_t *sc, ohci_soft_td_t *std) 501 { 502 503 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 504 505 std->nexttd = sc->sc_freetds; 506 sc->sc_freetds = std; 507 } 508 509 void 510 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 511 { 512 513 mutex_enter(&sc->sc_lock); 514 ohci_free_std_locked(sc, std); 515 mutex_exit(&sc->sc_lock); 516 } 517 518 Static int 519 ohci_alloc_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, int length, int rd) 520 { 521 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 522 uint16_t flags = xfer->ux_flags; 523 524 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 525 526 DPRINTFN(8, "addr=%jd endpt=%jd len=%jd speed=%jd", 527 xfer->ux_pipe->up_dev->ud_addr, 528 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 529 length, xfer->ux_pipe->up_dev->ud_speed); 530 531 ASSERT_SLEEPABLE(); 532 KASSERT(length != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 533 534 size_t nstd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 535 nstd += howmany(length, OHCI_PAGE_SIZE); 536 ox->ox_stds = kmem_zalloc(sizeof(ohci_soft_td_t *) * nstd, 537 KM_SLEEP); 538 ox->ox_nstd = nstd; 539 540 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, nstd, 0, 0); 541 542 for (size_t j = 0; j < ox->ox_nstd; j++) { 543 ohci_soft_td_t *cur = ohci_alloc_std(sc); 544 if (cur == NULL) 545 goto nomem; 546 547 ox->ox_stds[j] = cur; 548 cur->held = &ox->ox_stds[j]; 549 cur->xfer = xfer; 550 cur->flags = 0; 551 DPRINTFN(10, "xfer=%#jx new std=%#jx held at %#jx", (uintptr_t)ox, 552 (uintptr_t)cur, (uintptr_t)cur->held, 0); 553 } 554 555 return 0; 556 557 nomem: 558 ohci_free_stds(sc, ox); 559 kmem_free(ox->ox_stds, sizeof(ohci_soft_td_t *) * nstd); 560 561 return ENOMEM; 562 } 563 564 Static void 565 ohci_free_stds(ohci_softc_t *sc, struct ohci_xfer *ox) 566 { 567 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 568 DPRINTF("ox=%#jx", (uintptr_t)ox, 0, 0, 0); 569 570 mutex_enter(&sc->sc_lock); 571 for (size_t i = 0; i < ox->ox_nstd; i++) { 572 ohci_soft_td_t *std = ox->ox_stds[i]; 573 if (std == NULL) 574 break; 575 ohci_free_std_locked(sc, std); 576 } 577 mutex_exit(&sc->sc_lock); 578 } 579 580 void 581 ohci_reset_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, 582 int alen, int rd, ohci_soft_td_t *sp, ohci_soft_td_t **ep) 583 { 584 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 585 ohci_soft_td_t *next, *cur; 586 int len, curlen; 587 usb_dma_t *dma = &xfer->ux_dmabuf; 588 uint16_t flags = xfer->ux_flags; 589 590 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 591 DPRINTF("start len=%jd", alen, 0, 0, 0); 592 593 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 594 595 DPRINTFN(8, "addr=%jd endpt=%jd len=%jd speed=%jd", 596 xfer->ux_pipe->up_dev->ud_addr, 597 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 598 alen, xfer->ux_pipe->up_dev->ud_speed); 599 600 KASSERT(sp); 601 602 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 603 604 /* 605 * Assign next for the len == 0 case where we don't go through the 606 * main loop. 607 */ 608 len = alen; 609 cur = next = sp; 610 611 usb_syncmem(dma, 0, len, 612 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 613 const uint32_t tdflags = HTOO32( 614 OHCI_TD_SET_DP(rd ? OHCI_TD_DP_IN : OHCI_TD_DP_OUT) | 615 OHCI_TD_SET_CC(OHCI_TD_NOCC) | 616 OHCI_TD_SET_TOGGLE(OHCI_TD_TOGGLE_CARRY) | 617 OHCI_TD_SET_DI(OHCI_TD_NOINTR) 618 ); 619 620 size_t curoffs = 0; 621 for (size_t j = 1; len != 0;) { 622 if (j == ox->ox_nstd) 623 next = NULL; 624 else 625 next = ox->ox_stds[j++]; 626 KASSERT(next != cur); 627 628 curlen = len; 629 /* 630 * The OHCI hardware can handle at most one page crossing per 631 * TD. That is, 2 * OHCI_PAGE_SIZE as a maximum. Limit the 632 * length in this TD accordingly. 633 */ 634 const ohci_physaddr_t sdataphys = DMAADDR(dma, curoffs); 635 636 int maxlen = (2 * OHCI_PAGE_SIZE) - OHCI_PAGE_OFFSET(sdataphys); 637 if (curlen > maxlen) { 638 curlen = maxlen; 639 640 /* 641 * the length must be a multiple of 642 * the max size 643 */ 644 curlen -= curlen % mps; 645 } 646 647 const int edataoffs = curoffs + curlen - 1; 648 const ohci_physaddr_t edataphys = DMAADDR(dma, edataoffs); 649 650 KASSERT(curlen != 0); 651 DPRINTFN(4, "sdataphys=0x%08jx edataphys=0x%08jx " 652 "len=%jd curlen=%jd", sdataphys, edataphys, len, curlen); 653 654 cur->td.td_flags = tdflags; 655 cur->td.td_cbp = HTOO32(sdataphys); 656 cur->td.td_be = HTOO32(edataphys); 657 cur->td.td_nexttd = (next != NULL) ? HTOO32(next->physaddr) : 0; 658 cur->nexttd = next; 659 cur->len = curlen; 660 cur->flags = OHCI_ADD_LEN; 661 cur->xfer = xfer; 662 ohci_hash_add_td(sc, cur); 663 664 curoffs += curlen; 665 len -= curlen; 666 667 if (len != 0) { 668 KASSERT(next != NULL); 669 DPRINTFN(10, "extend chain", 0, 0, 0, 0); 670 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 671 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 672 673 cur = next; 674 } 675 } 676 cur->td.td_flags |= 677 HTOO32(xfer->ux_flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0); 678 679 if (!rd && 680 (flags & USBD_FORCE_SHORT_XFER) && 681 alen % mps == 0) { 682 /* We're adding a ZLP so sync the previous TD */ 683 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 684 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 685 686 /* Force a 0 length transfer at the end. */ 687 688 KASSERT(next != NULL); 689 cur = next; 690 691 cur->td.td_flags = tdflags; 692 cur->td.td_cbp = 0; /* indicate 0 length packet */ 693 cur->td.td_nexttd = 0; 694 cur->td.td_be = ~0; 695 cur->nexttd = NULL; 696 cur->len = 0; 697 cur->flags = 0; 698 cur->xfer = xfer; 699 ohci_hash_add_td(sc, cur); 700 701 DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0); 702 } 703 704 /* Last TD gets usb_syncmem'ed by caller */ 705 *ep = cur; 706 } 707 708 ohci_soft_itd_t * 709 ohci_alloc_sitd(ohci_softc_t *sc) 710 { 711 ohci_soft_itd_t *sitd; 712 int i, offs; 713 usb_dma_t dma; 714 715 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 716 717 mutex_enter(&sc->sc_lock); 718 if (sc->sc_freeitds == NULL) { 719 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 720 mutex_exit(&sc->sc_lock); 721 722 int err = usb_allocmem(sc->sc_bus.ub_dmatag, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 723 OHCI_ITD_ALIGN, USBMALLOC_COHERENT, &dma); 724 if (err) 725 return NULL; 726 mutex_enter(&sc->sc_lock); 727 for (i = 0; i < OHCI_SITD_CHUNK; i++) { 728 offs = i * OHCI_SITD_SIZE; 729 sitd = KERNADDR(&dma, offs); 730 sitd->physaddr = DMAADDR(&dma, offs); 731 sitd->dma = dma; 732 sitd->offs = offs; 733 sitd->nextitd = sc->sc_freeitds; 734 sc->sc_freeitds = sitd; 735 } 736 } 737 738 sitd = sc->sc_freeitds; 739 sc->sc_freeitds = sitd->nextitd; 740 mutex_exit(&sc->sc_lock); 741 742 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 743 sitd->nextitd = NULL; 744 sitd->xfer = NULL; 745 746 #ifdef DIAGNOSTIC 747 sitd->isdone = true; 748 #endif 749 750 return sitd; 751 } 752 753 Static void 754 ohci_free_sitd_locked(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 755 { 756 757 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 758 DPRINTFN(10, "sitd=%#jx", (uintptr_t)sitd, 0, 0, 0); 759 760 KASSERT(sitd->isdone); 761 #ifdef DIAGNOSTIC 762 /* Warn double free */ 763 sitd->isdone = false; 764 #endif 765 766 sitd->nextitd = sc->sc_freeitds; 767 sc->sc_freeitds = sitd; 768 } 769 770 void 771 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 772 { 773 774 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 775 776 mutex_enter(&sc->sc_lock); 777 ohci_free_sitd_locked(sc, sitd); 778 mutex_exit(&sc->sc_lock); 779 } 780 781 int 782 ohci_init(ohci_softc_t *sc) 783 { 784 ohci_soft_ed_t *sed, *psed; 785 usbd_status err; 786 int i; 787 uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */; 788 789 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 790 791 aprint_normal_dev(sc->sc_dev, ""); 792 793 sc->sc_hcca = NULL; 794 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 795 796 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 797 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 798 799 sc->sc_rhsc_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 800 ohci_rhsc_softint, sc); 801 802 for (i = 0; i < OHCI_HASH_SIZE; i++) 803 LIST_INIT(&sc->sc_hash_tds[i]); 804 for (i = 0; i < OHCI_HASH_SIZE; i++) 805 LIST_INIT(&sc->sc_hash_itds[i]); 806 807 TAILQ_INIT(&sc->sc_abortingxfers); 808 cv_init(&sc->sc_abort_cv, "ohciabt"); 809 810 sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0, 811 "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL); 812 813 rev = OREAD4(sc, OHCI_REVISION); 814 aprint_normal("OHCI version %" __PRIuBITS ".%" __PRIuBITS "%s\n", 815 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 816 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 817 818 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 819 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 820 sc->sc_bus.ub_revision = USBREV_UNKNOWN; 821 return -1; 822 } 823 sc->sc_bus.ub_revision = USBREV_1_0; 824 sc->sc_bus.ub_usedma = true; 825 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 826 827 /* XXX determine alignment by R/W */ 828 /* Allocate the HCCA area. */ 829 err = usb_allocmem(sc->sc_bus.ub_dmatag, OHCI_HCCA_SIZE, OHCI_HCCA_ALIGN, 830 USBMALLOC_COHERENT, &sc->sc_hccadma); 831 if (err) { 832 sc->sc_hcca = NULL; 833 return err; 834 } 835 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 836 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 837 838 sc->sc_eintrs = OHCI_NORMAL_INTRS; 839 840 /* Allocate dummy ED that starts the control list. */ 841 sc->sc_ctrl_head = ohci_alloc_sed(sc); 842 if (sc->sc_ctrl_head == NULL) { 843 err = ENOMEM; 844 goto bad1; 845 } 846 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 847 usb_syncmem(&sc->sc_ctrl_head->dma, sc->sc_ctrl_head->offs, 848 sizeof(sc->sc_ctrl_head->ed), 849 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 850 851 /* Allocate dummy ED that starts the bulk list. */ 852 sc->sc_bulk_head = ohci_alloc_sed(sc); 853 if (sc->sc_bulk_head == NULL) { 854 err = ENOMEM; 855 goto bad2; 856 } 857 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 858 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 859 sizeof(sc->sc_bulk_head->ed), 860 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 861 862 /* Allocate dummy ED that starts the isochronous list. */ 863 sc->sc_isoc_head = ohci_alloc_sed(sc); 864 if (sc->sc_isoc_head == NULL) { 865 err = ENOMEM; 866 goto bad3; 867 } 868 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 869 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 870 sizeof(sc->sc_isoc_head->ed), 871 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 872 873 /* Allocate all the dummy EDs that make up the interrupt tree. */ 874 for (i = 0; i < OHCI_NO_EDS; i++) { 875 sed = ohci_alloc_sed(sc); 876 if (sed == NULL) { 877 while (--i >= 0) 878 ohci_free_sed(sc, sc->sc_eds[i]); 879 err = ENOMEM; 880 goto bad4; 881 } 882 /* All ED fields are set to 0. */ 883 sc->sc_eds[i] = sed; 884 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 885 if (i != 0) 886 psed = sc->sc_eds[(i-1) / 2]; 887 else 888 psed= sc->sc_isoc_head; 889 sed->next = psed; 890 sed->ed.ed_nexted = HTOO32(psed->physaddr); 891 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 892 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 893 } 894 /* 895 * Fill HCCA interrupt table. The bit reversal is to get 896 * the tree set up properly to spread the interrupts. 897 */ 898 for (i = 0; i < OHCI_NO_INTRS; i++) 899 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 900 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 901 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 902 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 903 904 #ifdef OHCI_DEBUG 905 DPRINTFN(15, "--- dump start ---", 0, 0, 0 ,0); 906 if (ohcidebug >= 15) { 907 for (i = 0; i < OHCI_NO_EDS; i++) { 908 DPRINTFN(15, "ed#%jd ", i, 0, 0, 0); 909 ohci_dump_ed(sc, sc->sc_eds[i]); 910 } 911 DPRINTFN(15, "iso", 0, 0, 0 ,0); 912 ohci_dump_ed(sc, sc->sc_isoc_head); 913 } 914 DPRINTFN(15, "--- dump end ---", 0, 0, 0 ,0); 915 #endif 916 917 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 918 ctl = OREAD4(sc, OHCI_CONTROL); 919 rwc = ctl & OHCI_RWC; 920 fm = OREAD4(sc, OHCI_FM_INTERVAL); 921 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 922 /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */ 923 924 /* Determine in what context we are running. */ 925 if (ctl & OHCI_IR) { 926 /* SMM active, request change */ 927 DPRINTF("SMM active, request owner change", 0, 0, 0, 0); 928 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 929 (OHCI_OC | OHCI_MIE)) 930 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 931 s = OREAD4(sc, OHCI_COMMAND_STATUS); 932 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 933 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 934 usb_delay_ms(&sc->sc_bus, 1); 935 ctl = OREAD4(sc, OHCI_CONTROL); 936 } 937 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 938 if ((ctl & OHCI_IR) == 0) { 939 aprint_error_dev(sc->sc_dev, 940 "SMM does not respond, resetting\n"); 941 OWRITE4(sc, OHCI_CONTROL, 942 OHCI_SET_HCFS(OHCI_HCFS_RESET) | rwc); 943 goto reset; 944 } 945 #if 0 946 /* 947 * Don't bother trying to reuse the BIOS init, we'll reset it 948 * anyway. 949 */ 950 } else if (OHCI_GET_HCFS(ctl) != OHCI_HCFS_RESET) { 951 /* BIOS started controller. */ 952 DPRINTF("BIOS active", 0, 0, 0, 0); 953 if (OHCI_GET_HCFS(ctl) != OHCI_HCFS_OPERATIONAL) { 954 OWRITE4(sc, OHCI_CONTROL, 955 OHCI_SET_HCFS(OHCI_HCFS_OPERATIONAL) | rwc); 956 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 957 } 958 #endif 959 } else { 960 DPRINTF("cold started", 0 ,0 ,0 ,0); 961 reset: 962 /* Controller was cold started. */ 963 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 964 } 965 966 /* 967 * This reset should not be necessary according to the OHCI spec, but 968 * without it some controllers do not start. 969 */ 970 DPRINTF("sc %#jx: resetting", (uintptr_t)sc, 0, 0, 0); 971 OWRITE4(sc, OHCI_CONTROL, OHCI_SET_HCFS(OHCI_HCFS_RESET) | rwc); 972 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 973 974 /* We now own the host controller and the bus has been reset. */ 975 976 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 977 /* Nominal time for a reset is 10 us. */ 978 for (i = 0; i < 10; i++) { 979 delay(10); 980 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 981 if (!hcr) 982 break; 983 } 984 if (hcr) { 985 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 986 err = EIO; 987 goto bad5; 988 } 989 #ifdef OHCI_DEBUG 990 if (ohcidebug >= 15) 991 ohci_dumpregs(sc); 992 #endif 993 994 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 995 996 /* Set up HC registers. */ 997 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 998 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 999 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 1000 /* disable all interrupts and then switch on all desired interrupts */ 1001 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 1002 /* switch on desired functional features */ 1003 ctl = OREAD4(sc, OHCI_CONTROL); 1004 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 1005 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 1006 OHCI_CBSR_SET(OHCI_RATIO_1_4) | 1007 OHCI_SET_HCFS(OHCI_HCFS_OPERATIONAL) | rwc; 1008 /* And finally start it! */ 1009 OWRITE4(sc, OHCI_CONTROL, ctl); 1010 1011 /* 1012 * The controller is now OPERATIONAL. Set a some final 1013 * registers that should be set earlier, but that the 1014 * controller ignores when in the SUSPEND state. 1015 */ 1016 ival = OHCI_FM_GET_IVAL(fm); 1017 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FM_FIT) ^ OHCI_FM_FIT; 1018 fm |= OHCI_FSMPS(ival) | ival; 1019 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 1020 per = OHCI_PERIODIC(ival); /* 90% periodic */ 1021 OWRITE4(sc, OHCI_PERIODIC_START, per); 1022 1023 if (sc->sc_flags & OHCIF_SUPERIO) { 1024 /* no overcurrent protection */ 1025 desca |= OHCI_RHD_NOCP; 1026 /* 1027 * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning 1028 * that 1029 * - ports are always power switched 1030 * - don't wait for powered root hub port 1031 */ 1032 desca &= ~(OHCI_RHD_POTPGT_MASK | OHCI_RHD_NPS); 1033 } 1034 1035 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 1036 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_RHD_NOCP); 1037 OWRITE4(sc, OHCI_RH_STATUS, OHCI_RHS_LPSC); /* Enable port power */ 1038 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 1039 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 1040 1041 /* 1042 * The AMD756 requires a delay before re-reading the register, 1043 * otherwise it will occasionally report 0 ports. 1044 */ 1045 sc->sc_noport = 0; 1046 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 1047 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 1048 sc->sc_noport = 1049 OHCI_RHD_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 1050 } 1051 1052 #ifdef OHCI_DEBUG 1053 if (ohcidebug >= 5) 1054 ohci_dumpregs(sc); 1055 #endif 1056 1057 /* Set up the bus struct. */ 1058 sc->sc_bus.ub_methods = &ohci_bus_methods; 1059 sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe); 1060 1061 sc->sc_control = sc->sc_intre = 0; 1062 1063 /* Finally, turn on interrupts. */ 1064 DPRINTF("enabling %#jx", sc->sc_eintrs | OHCI_MIE, 0, 0, 0); 1065 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 1066 1067 return 0; 1068 1069 bad5: 1070 for (i = 0; i < OHCI_NO_EDS; i++) 1071 ohci_free_sed(sc, sc->sc_eds[i]); 1072 bad4: 1073 ohci_free_sed(sc, sc->sc_isoc_head); 1074 bad3: 1075 ohci_free_sed(sc, sc->sc_bulk_head); 1076 bad2: 1077 ohci_free_sed(sc, sc->sc_ctrl_head); 1078 bad1: 1079 usb_freemem(&sc->sc_hccadma); 1080 sc->sc_hcca = NULL; 1081 return err; 1082 } 1083 1084 struct usbd_xfer * 1085 ohci_allocx(struct usbd_bus *bus, unsigned int nframes) 1086 { 1087 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1088 struct usbd_xfer *xfer; 1089 1090 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 1091 if (xfer != NULL) { 1092 memset(xfer, 0, sizeof(struct ohci_xfer)); 1093 1094 #ifdef DIAGNOSTIC 1095 xfer->ux_state = XFER_BUSY; 1096 #endif 1097 } 1098 return xfer; 1099 } 1100 1101 void 1102 ohci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1103 { 1104 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1105 1106 KASSERTMSG(xfer->ux_state == XFER_BUSY || 1107 xfer->ux_status == USBD_NOT_STARTED, 1108 "xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state); 1109 #ifdef DIAGNOSTIC 1110 xfer->ux_state = XFER_FREE; 1111 #endif 1112 pool_cache_put(sc->sc_xferpool, xfer); 1113 } 1114 1115 Static bool 1116 ohci_dying(struct usbd_bus *bus) 1117 { 1118 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1119 1120 return sc->sc_dying; 1121 } 1122 1123 Static void 1124 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1125 { 1126 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1127 1128 *lock = &sc->sc_lock; 1129 } 1130 1131 /* 1132 * Shut down the controller when the system is going down. 1133 */ 1134 bool 1135 ohci_shutdown(device_t self, int flags) 1136 { 1137 ohci_softc_t *sc = device_private(self); 1138 1139 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1140 1141 DPRINTF("stopping the HC", 0, 0, 0, 0); 1142 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 1143 OWRITE4(sc, OHCI_CONTROL, OHCI_SET_HCFS(OHCI_HCFS_RESET)); 1144 return true; 1145 } 1146 1147 bool 1148 ohci_resume(device_t dv, const pmf_qual_t *qual) 1149 { 1150 ohci_softc_t *sc = device_private(dv); 1151 uint32_t ctl; 1152 1153 /* Some broken BIOSes do not recover these values */ 1154 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1155 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1156 sc->sc_ctrl_head->physaddr); 1157 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1158 sc->sc_bulk_head->physaddr); 1159 if (sc->sc_intre) 1160 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1161 (OHCI_ALL_INTRS | OHCI_MIE)); 1162 if (sc->sc_control) 1163 ctl = sc->sc_control; 1164 else 1165 ctl = OREAD4(sc, OHCI_CONTROL); 1166 ctl |= OHCI_SET_HCFS(OHCI_HCFS_RESUME); 1167 OWRITE4(sc, OHCI_CONTROL, ctl); 1168 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1169 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_SET_HCFS(OHCI_HCFS_OPERATIONAL); 1170 OWRITE4(sc, OHCI_CONTROL, ctl); 1171 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1172 sc->sc_control = sc->sc_intre = 0; 1173 1174 return true; 1175 } 1176 1177 bool 1178 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1179 { 1180 ohci_softc_t *sc = device_private(dv); 1181 uint32_t ctl; 1182 1183 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1184 if (sc->sc_control == 0) { 1185 /* 1186 * Preserve register values, in case that BIOS 1187 * does not recover them. 1188 */ 1189 sc->sc_control = ctl; 1190 sc->sc_intre = OREAD4(sc, 1191 OHCI_INTERRUPT_ENABLE); 1192 } 1193 ctl |= OHCI_SET_HCFS(OHCI_HCFS_SUSPEND); 1194 OWRITE4(sc, OHCI_CONTROL, ctl); 1195 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1196 1197 return true; 1198 } 1199 1200 #ifdef OHCI_DEBUG 1201 void 1202 ohci_dumpregs(ohci_softc_t *sc) 1203 { 1204 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1205 1206 DPRINTF("rev=0x%08jx control=0x%08jx command=0x%08jx", 1207 OREAD4(sc, OHCI_REVISION), 1208 OREAD4(sc, OHCI_CONTROL), 1209 OREAD4(sc, OHCI_COMMAND_STATUS), 0); 1210 DPRINTF(" intrstat=0x%08jx intre=0x%08jx intrd=0x%08jx", 1211 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1212 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1213 OREAD4(sc, OHCI_INTERRUPT_DISABLE), 0); 1214 DPRINTF(" hcca=0x%08jx percur=0x%08jx ctrlhd=0x%08jx", 1215 OREAD4(sc, OHCI_HCCA), 1216 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1217 OREAD4(sc, OHCI_CONTROL_HEAD_ED), 0); 1218 DPRINTF(" ctrlcur=0x%08jx bulkhd=0x%08jx bulkcur=0x%08jx", 1219 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1220 OREAD4(sc, OHCI_BULK_HEAD_ED), 1221 OREAD4(sc, OHCI_BULK_CURRENT_ED) ,0); 1222 DPRINTF(" done=0x%08jx fmival=0x%08jx fmrem=0x%08jx", 1223 OREAD4(sc, OHCI_DONE_HEAD), 1224 OREAD4(sc, OHCI_FM_INTERVAL), 1225 OREAD4(sc, OHCI_FM_REMAINING), 0); 1226 DPRINTF(" fmnum=0x%08jx perst=0x%08jx lsthrs=0x%08jx", 1227 OREAD4(sc, OHCI_FM_NUMBER), 1228 OREAD4(sc, OHCI_PERIODIC_START), 1229 OREAD4(sc, OHCI_LS_THRESHOLD), 0); 1230 DPRINTF(" desca=0x%08jx descb=0x%08jx stat=0x%08jx", 1231 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1232 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1233 OREAD4(sc, OHCI_RH_STATUS), 0); 1234 DPRINTF(" port1=0x%08jx port2=0x%08jx", 1235 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1236 OREAD4(sc, OHCI_RH_PORT_STATUS(2)), 0, 0); 1237 usb_syncmem(&sc->sc_hccadma, 1238 offsetof(struct ohci_hcca, hcca_frame_number), 1239 sizeof(sc->sc_hcca->hcca_frame_number) + 1240 sizeof(sc->sc_hcca->hcca_done_head), 1241 BUS_DMASYNC_POSTREAD); 1242 DPRINTF(" HCCA: frame_number=0x%04jx done_head=0x%08jx", 1243 O32TOH(sc->sc_hcca->hcca_frame_number), 1244 O32TOH(sc->sc_hcca->hcca_done_head), 0, 0); 1245 } 1246 #endif 1247 1248 Static int ohci_intr1(ohci_softc_t *); 1249 1250 int 1251 ohci_intr(void *p) 1252 { 1253 ohci_softc_t *sc = p; 1254 int ret = 0; 1255 1256 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1257 1258 if (sc == NULL) 1259 return 0; 1260 1261 mutex_spin_enter(&sc->sc_intr_lock); 1262 1263 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1264 goto done; 1265 1266 /* If we get an interrupt while polling, then just ignore it. */ 1267 if (sc->sc_bus.ub_usepolling) { 1268 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1269 /* for level triggered intrs, should do something to ack */ 1270 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1271 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1272 1273 goto done; 1274 } 1275 1276 ret = ohci_intr1(sc); 1277 1278 done: 1279 mutex_spin_exit(&sc->sc_intr_lock); 1280 return ret; 1281 } 1282 1283 Static int 1284 ohci_intr1(ohci_softc_t *sc) 1285 { 1286 uint32_t intrs, eintrs; 1287 1288 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1289 1290 /* In case the interrupt occurs before initialization has completed. */ 1291 if (sc == NULL || sc->sc_hcca == NULL) { 1292 #ifdef DIAGNOSTIC 1293 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1294 #endif 1295 return 0; 1296 } 1297 1298 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1299 1300 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1301 if (!intrs) 1302 return 0; 1303 1304 /* Acknowledge */ 1305 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); 1306 eintrs = intrs & sc->sc_eintrs; 1307 DPRINTFN(7, "sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1308 DPRINTFN(7, "intrs=%#jx(%#jx) eintrs=%#jx(%#jx)", 1309 intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), eintrs, 1310 sc->sc_eintrs); 1311 1312 if (!eintrs) { 1313 return 0; 1314 } 1315 1316 if (eintrs & OHCI_SO) { 1317 sc->sc_overrun_cnt++; 1318 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1319 printf("%s: %u scheduling overruns\n", 1320 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1321 sc->sc_overrun_cnt = 0; 1322 } 1323 /* XXX do what */ 1324 eintrs &= ~OHCI_SO; 1325 } 1326 if (eintrs & OHCI_WDH) { 1327 /* 1328 * We block the interrupt below, and reenable it later from 1329 * ohci_softintr(). 1330 */ 1331 usb_schedsoftintr(&sc->sc_bus); 1332 } 1333 if (eintrs & OHCI_SF) { 1334 struct ohci_xfer *ox, *tmp; 1335 TAILQ_FOREACH_SAFE(ox, &sc->sc_abortingxfers, ox_abnext, tmp) { 1336 DPRINTFN(10, "SF %#jx xfer %#jx", (uintptr_t)sc, 1337 (uintptr_t)ox, 0, 0); 1338 ox->ox_abintrs &= ~OHCI_SF; 1339 KASSERT(ox->ox_abintrs == 0); 1340 TAILQ_REMOVE(&sc->sc_abortingxfers, ox, ox_abnext); 1341 } 1342 cv_broadcast(&sc->sc_abort_cv); 1343 1344 KASSERT(TAILQ_EMPTY(&sc->sc_abortingxfers)); 1345 DPRINTFN(10, "end SOF %#jx", (uintptr_t)sc, 0, 0, 0); 1346 /* Don't remove OHIC_SF from eintrs so it is blocked below */ 1347 } 1348 if (eintrs & OHCI_RD) { 1349 DPRINTFN(5, "resume detect sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1350 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1351 /* XXX process resume detect */ 1352 } 1353 if (eintrs & OHCI_UE) { 1354 DPRINTFN(5, "unrecoverable error sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1355 printf("%s: unrecoverable error, controller halted\n", 1356 device_xname(sc->sc_dev)); 1357 OWRITE4(sc, OHCI_CONTROL, OHCI_SET_HCFS(OHCI_HCFS_RESET)); 1358 /* XXX what else */ 1359 } 1360 if (eintrs & OHCI_RHSC) { 1361 /* 1362 * We block the interrupt below, and reenable it later from 1363 * a timeout. 1364 */ 1365 softint_schedule(sc->sc_rhsc_si); 1366 } 1367 1368 if (eintrs != 0) { 1369 /* Block unprocessed interrupts. */ 1370 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1371 sc->sc_eintrs &= ~eintrs; 1372 DPRINTF("sc %#jx blocking intrs %#jx", (uintptr_t)sc, 1373 eintrs, 0, 0); 1374 } 1375 1376 return 1; 1377 } 1378 1379 void 1380 ohci_rhsc_enable(void *v_sc) 1381 { 1382 ohci_softc_t *sc = v_sc; 1383 1384 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1385 DPRINTF("sc %#jx", (uintptr_t)sc, 0, 0, 0); 1386 mutex_spin_enter(&sc->sc_intr_lock); 1387 sc->sc_eintrs |= OHCI_RHSC; 1388 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1389 mutex_spin_exit(&sc->sc_intr_lock); 1390 } 1391 1392 #ifdef OHCI_DEBUG 1393 const char *const ohci_cc_strs[] = { 1394 "NO_ERROR", 1395 "CRC", 1396 "BIT_STUFFING", 1397 "DATA_TOGGLE_MISMATCH", 1398 "STALL", 1399 "DEVICE_NOT_RESPONDING", 1400 "PID_CHECK_FAILURE", 1401 "UNEXPECTED_PID", 1402 "DATA_OVERRUN", 1403 "DATA_UNDERRUN", 1404 "BUFFER_OVERRUN", 1405 "BUFFER_UNDERRUN", 1406 "reserved", 1407 "reserved", 1408 "NOT_ACCESSED", 1409 "NOT_ACCESSED", 1410 }; 1411 #endif 1412 1413 void 1414 ohci_softintr(void *v) 1415 { 1416 struct usbd_bus *bus = v; 1417 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1418 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1419 ohci_soft_td_t *std, *sdone, *stdnext; 1420 struct usbd_xfer *xfer; 1421 struct ohci_pipe *opipe; 1422 int len, cc; 1423 int i, j, actlen, iframes, uedir; 1424 ohci_physaddr_t done = 0; 1425 1426 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1427 1428 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1429 1430 /* 1431 * Only read hccadone if WDH is set - we might get here from places 1432 * other than an interrupt 1433 */ 1434 if (!(OREAD4(sc, OHCI_INTERRUPT_STATUS) & OHCI_WDH)) { 1435 DPRINTFN(10, "no WDH %#jx", (uintptr_t)sc, 0, 0, 0); 1436 return; 1437 } 1438 1439 DPRINTFN(10, "WDH %#jx", (uintptr_t)sc, 0, 0, 0); 1440 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1441 sizeof(sc->sc_hcca->hcca_done_head), 1442 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1443 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1444 sc->sc_hcca->hcca_done_head = 0; 1445 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1446 sizeof(sc->sc_hcca->hcca_done_head), 1447 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1448 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1449 sc->sc_eintrs |= OHCI_WDH; 1450 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1451 1452 /* Reverse the done list. */ 1453 for (sdone = NULL, sidone = NULL; done != 0; ) { 1454 std = ohci_hash_find_td(sc, done); 1455 if (std != NULL) { 1456 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1457 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1458 std->dnext = sdone; 1459 done = O32TOH(std->td.td_nexttd); 1460 sdone = std; 1461 DPRINTFN(10, "add TD %#jx", (uintptr_t)std, 0, 0, 0); 1462 continue; 1463 } 1464 sitd = ohci_hash_find_itd(sc, done); 1465 if (sitd != NULL) { 1466 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1467 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1468 sitd->dnext = sidone; 1469 done = O32TOH(sitd->itd.itd_nextitd); 1470 sidone = sitd; 1471 DPRINTFN(5, "add ITD %#jx", (uintptr_t)sitd, 0, 0, 0); 1472 continue; 1473 } 1474 DPRINTFN(10, "addr %#jx not found", (uintptr_t)done, 0, 0, 0); 1475 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1476 (u_long)done); 1477 break; 1478 } 1479 1480 DPRINTFN(10, "sdone=%#jx sidone=%#jx", (uintptr_t)sdone, 1481 (uintptr_t)sidone, 0, 0); 1482 DPRINTFN(10, "--- TD dump start ---", 0, 0, 0, 0); 1483 #ifdef OHCI_DEBUG 1484 if (ohcidebug >= 10) { 1485 for (std = sdone; std; std = std->dnext) 1486 ohci_dump_td(sc, std); 1487 } 1488 #endif 1489 DPRINTFN(10, "--- TD dump end ---", 0, 0, 0, 0); 1490 1491 for (std = sdone; std; std = stdnext) { 1492 stdnext = std->dnext; 1493 if (std->held == NULL) { 1494 DPRINTFN(10, "std=%#jx held is null", (uintptr_t)std, 1495 0, 0, 0); 1496 ohci_hash_rem_td(sc, std); 1497 ohci_free_std_locked(sc, std); 1498 continue; 1499 } 1500 1501 xfer = std->xfer; 1502 DPRINTFN(10, "std=%#jx xfer=%#jx hcpriv=%#jx dnext=%#jx", 1503 (uintptr_t)std, (uintptr_t)xfer, 1504 (uintptr_t)(xfer ? xfer->ux_hcpriv : 0), (uintptr_t)stdnext); 1505 if (xfer == NULL) { 1506 /* 1507 * xfer == NULL: There seems to be no xfer associated 1508 * with this TD. It is tailp that happened to end up on 1509 * the done queue. 1510 * Shouldn't happen, but some chips are broken(?). 1511 */ 1512 continue; 1513 } 1514 /* 1515 * Try to claim this xfer for completion. If it has 1516 * already completed or aborted, drop it on the floor. 1517 */ 1518 if (!usbd_xfer_trycomplete(xfer)) 1519 continue; 1520 1521 len = std->len; 1522 if (std->td.td_cbp != 0) 1523 len -= O32TOH(std->td.td_be) - 1524 O32TOH(std->td.td_cbp) + 1; 1525 DPRINTFN(10, "len=%jd, flags=%#jx", len, std->flags, 0, 0); 1526 if (std->flags & OHCI_ADD_LEN) 1527 xfer->ux_actlen += len; 1528 1529 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1530 if (cc == OHCI_CC_NO_ERROR) { 1531 ohci_hash_rem_td(sc, std); 1532 if (std->flags & OHCI_CALL_DONE) { 1533 xfer->ux_status = USBD_NORMAL_COMPLETION; 1534 usb_transfer_complete(xfer); 1535 } 1536 } else { 1537 /* 1538 * Endpoint is halted. First unlink all the TDs 1539 * belonging to the failed transfer, and then restart 1540 * the endpoint. 1541 */ 1542 ohci_soft_td_t *p, *n; 1543 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1544 1545 DPRINTFN(10, "error cc=%jd", cc, 0, 0, 0); 1546 1547 /* remove xfer's TDs from the hash */ 1548 for (p = std; p->xfer == xfer; p = n) { 1549 n = p->nexttd; 1550 ohci_hash_rem_td(sc, p); 1551 } 1552 1553 ohci_soft_ed_t *sed = opipe->sed; 1554 1555 /* clear halt and TD chain, preserving toggle carry */ 1556 sed->ed.ed_headp = HTOO32(p->physaddr | 1557 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 1558 usb_syncmem(&sed->dma, 1559 sed->offs + offsetof(ohci_ed_t, ed_headp), 1560 sizeof(sed->ed.ed_headp), 1561 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1562 1563 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1564 1565 if (cc == OHCI_CC_DATA_UNDERRUN) 1566 xfer->ux_status = USBD_NORMAL_COMPLETION; 1567 else if (cc == OHCI_CC_STALL) 1568 xfer->ux_status = USBD_STALLED; 1569 else 1570 xfer->ux_status = USBD_IOERROR; 1571 usb_transfer_complete(xfer); 1572 } 1573 } 1574 DPRINTFN(10, "--- ITD dump start ---", 0, 0, 0, 0); 1575 #ifdef OHCI_DEBUG 1576 if (ohcidebug >= 10) { 1577 for (sitd = sidone; sitd; sitd = sitd->dnext) 1578 ohci_dump_itd(sc, sitd); 1579 } 1580 #endif 1581 DPRINTFN(10, "--- ITD dump end ---", 0, 0, 0, 0); 1582 1583 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1584 xfer = sitd->xfer; 1585 sitdnext = sitd->dnext; 1586 DPRINTFN(1, "sitd=%#jx xfer=%#jx hcpriv=%#jx", (uintptr_t)sitd, 1587 (uintptr_t)xfer, (uintptr_t)(xfer ? xfer->ux_hcpriv : 0), 1588 0); 1589 if (xfer == NULL) 1590 continue; 1591 1592 /* 1593 * Try to claim this xfer for completion. If it has 1594 * already completed or aborted, drop it on the floor. 1595 */ 1596 if (!usbd_xfer_trycomplete(xfer)) 1597 continue; 1598 1599 KASSERT(!sitd->isdone); 1600 #ifdef DIAGNOSTIC 1601 sitd->isdone = true; 1602 #endif 1603 if (sitd->flags & OHCI_CALL_DONE) { 1604 ohci_soft_itd_t *next; 1605 1606 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1607 opipe->isoc.inuse -= xfer->ux_nframes; 1608 uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc-> 1609 bEndpointAddress); 1610 xfer->ux_status = USBD_NORMAL_COMPLETION; 1611 actlen = 0; 1612 for (i = 0, sitd = xfer->ux_hcpriv;; 1613 sitd = next) { 1614 next = sitd->nextitd; 1615 1616 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1617 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1618 1619 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1620 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1621 xfer->ux_status = USBD_IOERROR; 1622 /* For input, update frlengths with actual */ 1623 /* XXX anything necessary for output? */ 1624 if (uedir == UE_DIR_IN && 1625 xfer->ux_status == USBD_NORMAL_COMPLETION) { 1626 iframes = OHCI_ITD_GET_FC(O32TOH( 1627 sitd->itd.itd_flags)); 1628 for (j = 0; j < iframes; i++, j++) { 1629 len = O16TOH(sitd-> 1630 itd.itd_offset[j]); 1631 if ((OHCI_ITD_PSW_GET_CC(len) & 1632 OHCI_CC_NOT_ACCESSED_MASK) 1633 == OHCI_CC_NOT_ACCESSED) 1634 len = 0; 1635 else 1636 len = OHCI_ITD_PSW_SIZE(len); 1637 xfer->ux_frlengths[i] = len; 1638 actlen += len; 1639 } 1640 } 1641 if (sitd->flags & OHCI_CALL_DONE) 1642 break; 1643 ohci_hash_rem_itd(sc, sitd); 1644 1645 } 1646 ohci_hash_rem_itd(sc, sitd); 1647 if (uedir == UE_DIR_IN && 1648 xfer->ux_status == USBD_NORMAL_COMPLETION) 1649 xfer->ux_actlen = actlen; 1650 xfer->ux_hcpriv = NULL; 1651 1652 usb_transfer_complete(xfer); 1653 } 1654 } 1655 1656 DPRINTFN(10, "done", 0, 0, 0, 0); 1657 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1658 } 1659 1660 void 1661 ohci_device_ctrl_done(struct usbd_xfer *xfer) 1662 { 1663 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1664 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1665 int len = UGETW(xfer->ux_request.wLength); 1666 int isread = (xfer->ux_request.bmRequestType & UT_READ); 1667 1668 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1669 DPRINTFN(10, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 1670 1671 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1672 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 1673 1674 if (len) 1675 usb_syncmem(&xfer->ux_dmabuf, 0, len, 1676 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1677 usb_syncmem(&opipe->ctrl.reqdma, 0, 1678 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1679 } 1680 1681 void 1682 ohci_device_intr_done(struct usbd_xfer *xfer) 1683 { 1684 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1685 int isread = 1686 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1687 1688 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1689 DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, 1690 xfer->ux_actlen, 0, 0); 1691 1692 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1693 1694 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1695 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1696 } 1697 1698 void 1699 ohci_device_bulk_done(struct usbd_xfer *xfer) 1700 { 1701 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1702 1703 int isread = 1704 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1705 1706 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1707 1708 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1709 DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 1710 0, 0); 1711 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1712 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1713 } 1714 1715 Static void 1716 ohci_rhsc_softint(void *arg) 1717 { 1718 ohci_softc_t *sc = arg; 1719 1720 mutex_enter(&sc->sc_lock); 1721 1722 ohci_rhsc(sc, sc->sc_intrxfer); 1723 1724 /* Do not allow RHSC interrupts > 1 per second */ 1725 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1726 1727 mutex_exit(&sc->sc_lock); 1728 } 1729 1730 void 1731 ohci_rhsc(ohci_softc_t *sc, struct usbd_xfer *xfer) 1732 { 1733 u_char *p; 1734 int i, m; 1735 int hstatus __unused; 1736 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1737 1738 KASSERT(mutex_owned(&sc->sc_lock)); 1739 1740 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1741 DPRINTF("sc=%#jx xfer=%#jx hstatus=0x%08jx", (uintptr_t)sc, 1742 (uintptr_t)xfer, hstatus, 0); 1743 1744 if (xfer == NULL) { 1745 /* Just ignore the change. */ 1746 return; 1747 } 1748 KASSERT(xfer == sc->sc_intrxfer); 1749 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 1750 1751 p = xfer->ux_buf; 1752 m = uimin(sc->sc_noport, xfer->ux_length * 8 - 1); 1753 memset(p, 0, xfer->ux_length); 1754 for (i = 1; i <= m; i++) { 1755 /* Pick out CHANGE bits from the status reg. */ 1756 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1757 p[i/8] |= 1 << (i%8); 1758 } 1759 DPRINTF("change=0x%02jx", *p, 0, 0, 0); 1760 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 1761 xfer->ux_actlen = xfer->ux_length; 1762 xfer->ux_status = USBD_NORMAL_COMPLETION; 1763 1764 usb_transfer_complete(xfer); 1765 } 1766 1767 void 1768 ohci_root_intr_done(struct usbd_xfer *xfer) 1769 { 1770 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1771 1772 KASSERT(mutex_owned(&sc->sc_lock)); 1773 1774 /* Claim the xfer so it doesn't get completed again. */ 1775 KASSERT(sc->sc_intrxfer == xfer); 1776 KASSERT(xfer->ux_status != USBD_IN_PROGRESS); 1777 sc->sc_intrxfer = NULL; 1778 } 1779 1780 void 1781 ohci_poll(struct usbd_bus *bus) 1782 { 1783 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1784 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1785 1786 #ifdef OHCI_DEBUG 1787 static int last; 1788 int new; 1789 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1790 if (new != last) { 1791 DPRINTFN(10, "intrs=0x%04jx", new, 0, 0, 0); 1792 last = new; 1793 } 1794 #endif 1795 sc->sc_eintrs |= OHCI_WDH; 1796 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1797 mutex_spin_enter(&sc->sc_intr_lock); 1798 ohci_intr1(sc); 1799 mutex_spin_exit(&sc->sc_intr_lock); 1800 } 1801 } 1802 1803 /* 1804 * Add an ED to the schedule. Called with USB lock held. 1805 */ 1806 Static void 1807 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1808 { 1809 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1810 DPRINTFN(8, "sed=%#jx head=%#jx", (uintptr_t)sed, (uintptr_t)head, 0, 1811 0); 1812 1813 KASSERT(mutex_owned(&sc->sc_lock)); 1814 1815 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1816 sizeof(head->ed.ed_nexted), 1817 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1818 sed->next = head->next; 1819 sed->ed.ed_nexted = head->ed.ed_nexted; 1820 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1821 sizeof(sed->ed.ed_nexted), 1822 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1823 head->next = sed; 1824 head->ed.ed_nexted = HTOO32(sed->physaddr); 1825 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1826 sizeof(head->ed.ed_nexted), 1827 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1828 } 1829 1830 /* 1831 * Remove an ED from the schedule. Called with USB lock held. 1832 */ 1833 Static void 1834 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1835 { 1836 ohci_soft_ed_t *p; 1837 1838 KASSERT(mutex_owned(&sc->sc_lock)); 1839 1840 /* XXX */ 1841 for (p = head; p != NULL && p->next != sed; p = p->next) 1842 ; 1843 KASSERT(p != NULL); 1844 1845 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1846 sizeof(sed->ed.ed_nexted), 1847 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1848 p->next = sed->next; 1849 p->ed.ed_nexted = sed->ed.ed_nexted; 1850 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1851 sizeof(p->ed.ed_nexted), 1852 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1853 } 1854 1855 /* 1856 * When a transfer is completed the TD is added to the done queue by 1857 * the host controller. This queue is the processed by software. 1858 * Unfortunately the queue contains the physical address of the TD 1859 * and we have no simple way to translate this back to a kernel address. 1860 * To make the translation possible (and fast) we use a hash table of 1861 * TDs currently in the schedule. The physical address is used as the 1862 * hash value. 1863 */ 1864 1865 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1866 /* Called with USB lock held. */ 1867 void 1868 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1869 { 1870 int h = HASH(std->physaddr); 1871 1872 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1873 1874 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1875 } 1876 1877 /* Called with USB lock held. */ 1878 void 1879 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1880 { 1881 1882 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1883 1884 LIST_REMOVE(std, hnext); 1885 } 1886 1887 ohci_soft_td_t * 1888 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1889 { 1890 int h = HASH(a); 1891 ohci_soft_td_t *std; 1892 1893 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1894 std != NULL; 1895 std = LIST_NEXT(std, hnext)) 1896 if (std->physaddr == a) 1897 return std; 1898 return NULL; 1899 } 1900 1901 /* Called with USB lock held. */ 1902 void 1903 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1904 { 1905 int h = HASH(sitd->physaddr); 1906 1907 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1908 1909 KASSERT(mutex_owned(&sc->sc_lock)); 1910 1911 DPRINTFN(10, "sitd=%#jx physaddr=0x%08jx", 1912 (uintptr_t)sitd, (u_long)sitd->physaddr, 0, 0); 1913 1914 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1915 } 1916 1917 /* Called with USB lock held. */ 1918 void 1919 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1920 { 1921 1922 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1923 1924 KASSERT(mutex_owned(&sc->sc_lock)); 1925 1926 DPRINTFN(10, "sitd=%#jx physaddr=0x%08jx", (uintptr_t)sitd, 1927 sitd->physaddr, 0, 0); 1928 1929 LIST_REMOVE(sitd, hnext); 1930 } 1931 1932 ohci_soft_itd_t * 1933 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1934 { 1935 int h = HASH(a); 1936 ohci_soft_itd_t *sitd; 1937 1938 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1939 sitd != NULL; 1940 sitd = LIST_NEXT(sitd, hnext)) 1941 if (sitd->physaddr == a) 1942 return sitd; 1943 return NULL; 1944 } 1945 1946 #ifdef OHCI_DEBUG 1947 void 1948 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 1949 { 1950 for (; std; std = std->nexttd) { 1951 ohci_dump_td(sc, std); 1952 KASSERTMSG(std->nexttd == NULL || std != std->nexttd, 1953 "std %p next %p", std, std->nexttd); 1954 } 1955 } 1956 1957 void 1958 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1959 { 1960 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1961 1962 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1963 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1964 1965 uint32_t flags = O32TOH(std->td.td_flags); 1966 DPRINTF("TD(%#jx) at 0x%08jx:", (uintptr_t)std, std->physaddr, 0, 0); 1967 DPRINTF(" round=%jd DP=%jx DI=%jx T=%jx", 1968 !!(flags & OHCI_TD_R), 1969 OHCI_TD_GET_DP(flags), 1970 OHCI_TD_GET_DI(flags), 1971 OHCI_TD_GET_TOGGLE(flags)); 1972 DPRINTF(" EC=%jd CC=%jd", OHCI_TD_GET_EC(flags), 1973 OHCI_TD_GET_CC(flags), 0, 0); 1974 DPRINTF(" td_cbp=0x%08jx td_nexttd=0x%08jx td_be=0x%08jx", 1975 (u_long)O32TOH(std->td.td_cbp), 1976 (u_long)O32TOH(std->td.td_nexttd), 1977 (u_long)O32TOH(std->td.td_be), 0); 1978 } 1979 1980 void 1981 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1982 { 1983 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1984 1985 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1986 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1987 1988 uint32_t flags = O32TOH(sitd->itd.itd_flags); 1989 DPRINTF("ITD(%#jx) at 0x%08jx", (uintptr_t)sitd, sitd->physaddr, 0, 0); 1990 DPRINTF(" sf=%jd di=%jd fc=%jd cc=%jd", 1991 OHCI_ITD_GET_SF(flags), OHCI_ITD_GET_DI(flags), 1992 OHCI_ITD_GET_FC(flags), OHCI_ITD_GET_CC(flags)); 1993 DPRINTF(" bp0=0x%08jx next=0x%08jx be=0x%08jx", 1994 O32TOH(sitd->itd.itd_bp0), 1995 O32TOH(sitd->itd.itd_nextitd), 1996 O32TOH(sitd->itd.itd_be), 0); 1997 CTASSERT(OHCI_ITD_NOFFSET == 8); 1998 DPRINTF(" offs[0] = 0x%04jx offs[1] = 0x%04jx " 1999 "offs[2] = 0x%04jx offs[3] = 0x%04jx", 2000 O16TOH(sitd->itd.itd_offset[0]), 2001 O16TOH(sitd->itd.itd_offset[1]), 2002 O16TOH(sitd->itd.itd_offset[2]), 2003 O16TOH(sitd->itd.itd_offset[3])); 2004 DPRINTF(" offs[4] = 0x%04jx offs[5] = 0x%04jx " 2005 "offs[6] = 0x%04jx offs[7] = 0x%04jx", 2006 O16TOH(sitd->itd.itd_offset[4]), 2007 O16TOH(sitd->itd.itd_offset[5]), 2008 O16TOH(sitd->itd.itd_offset[6]), 2009 O16TOH(sitd->itd.itd_offset[7])); 2010 } 2011 2012 void 2013 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2014 { 2015 for (; sitd; sitd = sitd->nextitd) 2016 ohci_dump_itd(sc, sitd); 2017 } 2018 2019 void 2020 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2021 { 2022 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2023 2024 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2025 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2026 2027 uint32_t flags = O32TOH(sed->ed.ed_flags); 2028 DPRINTF("ED(%#jx) at 0x%08jx:", (uintptr_t)sed, sed->physaddr, 0, 0); 2029 DPRINTF(" addr=%jd endpt=%jd maxp=%jd", 2030 OHCI_ED_GET_FA(flags), 2031 OHCI_ED_GET_EN(flags), 2032 OHCI_ED_GET_MAXP(flags), 2033 0); 2034 DPRINTF(" dir=%jd speed=%jd skip=%jd iso=%jd", 2035 OHCI_ED_GET_DIR(flags), 2036 __SHIFTOUT(flags, OHCI_ED_SPEED), 2037 __SHIFTOUT(flags, OHCI_ED_SKIP), 2038 OHCI_ED_GET_FORMAT(flags)); 2039 DPRINTF(" tailp=0x%08jx", (u_long)O32TOH(sed->ed.ed_tailp), 2040 0, 0, 0); 2041 DPRINTF(" headp=0x%08jx nexted=0x%08jx halted=%jd carry=%jd", 2042 O32TOH(sed->ed.ed_headp), O32TOH(sed->ed.ed_nexted), 2043 !!(O32TOH(sed->ed.ed_headp) & OHCI_HALTED), 2044 !!(O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 2045 } 2046 #endif 2047 2048 usbd_status 2049 ohci_open(struct usbd_pipe *pipe) 2050 { 2051 struct usbd_device *dev = pipe->up_dev; 2052 struct usbd_bus *bus = dev->ud_bus; 2053 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2054 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 2055 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2056 uint8_t addr = dev->ud_addr; 2057 uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2058 ohci_soft_ed_t *sed; 2059 ohci_soft_td_t *std; 2060 ohci_soft_itd_t *sitd; 2061 ohci_physaddr_t tdphys; 2062 uint32_t fmt; 2063 usbd_status err = USBD_NOMEM; 2064 int ival; 2065 2066 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2067 DPRINTFN(1, "pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, 2068 addr, ed->bEndpointAddress, bus->ub_rhaddr); 2069 2070 if (sc->sc_dying) { 2071 return USBD_IOERROR; 2072 } 2073 2074 std = NULL; 2075 sed = NULL; 2076 2077 if (addr == bus->ub_rhaddr) { 2078 switch (ed->bEndpointAddress) { 2079 case USB_CONTROL_ENDPOINT: 2080 pipe->up_methods = &roothub_ctrl_methods; 2081 break; 2082 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 2083 pipe->up_methods = &ohci_root_intr_methods; 2084 break; 2085 default: 2086 err = USBD_INVAL; 2087 goto bad; 2088 } 2089 } else { 2090 sed = ohci_alloc_sed(sc); 2091 if (sed == NULL) 2092 goto bad; 2093 opipe->sed = sed; 2094 if (xfertype == UE_ISOCHRONOUS) { 2095 sitd = ohci_alloc_sitd(sc); 2096 if (sitd == NULL) 2097 goto bad; 2098 2099 opipe->tail.itd = sitd; 2100 sitd->held = &opipe->tail.itd; 2101 tdphys = sitd->physaddr; 2102 fmt = OHCI_ED_SET_FORMAT(OHCI_ED_FORMAT_ISO); 2103 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2104 fmt |= OHCI_ED_SET_DIR(OHCI_ED_DIR_IN); 2105 else 2106 fmt |= OHCI_ED_SET_DIR(OHCI_ED_DIR_OUT); 2107 } else { 2108 std = ohci_alloc_std(sc); 2109 if (std == NULL) 2110 goto bad; 2111 2112 opipe->tail.td = std; 2113 std->held = &opipe->tail.td; 2114 tdphys = std->physaddr; 2115 fmt = 2116 OHCI_ED_SET_FORMAT(OHCI_ED_FORMAT_GEN) | 2117 OHCI_ED_SET_DIR(OHCI_ED_DIR_TD); 2118 } 2119 sed->ed.ed_flags = HTOO32( 2120 OHCI_ED_SET_FA(addr) | 2121 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2122 (dev->ud_speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2123 fmt | 2124 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2125 sed->ed.ed_headp = HTOO32(tdphys | 2126 (pipe->up_endpoint->ue_toggle ? OHCI_TOGGLECARRY : 0)); 2127 sed->ed.ed_tailp = HTOO32(tdphys); 2128 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2129 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2130 2131 switch (xfertype) { 2132 case UE_CONTROL: 2133 pipe->up_methods = &ohci_device_ctrl_methods; 2134 int error = usb_allocmem(sc->sc_bus.ub_dmatag, 2135 sizeof(usb_device_request_t), 0, 2136 USBMALLOC_COHERENT, &opipe->ctrl.reqdma); 2137 if (error) 2138 goto bad; 2139 mutex_enter(&sc->sc_lock); 2140 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2141 mutex_exit(&sc->sc_lock); 2142 break; 2143 case UE_INTERRUPT: 2144 pipe->up_methods = &ohci_device_intr_methods; 2145 ival = pipe->up_interval; 2146 if (ival == USBD_DEFAULT_INTERVAL) 2147 ival = ed->bInterval; 2148 err = ohci_device_setintr(sc, opipe, ival); 2149 if (err) 2150 goto bad; 2151 break; 2152 case UE_ISOCHRONOUS: 2153 pipe->up_serialise = false; 2154 pipe->up_methods = &ohci_device_isoc_methods; 2155 return ohci_setup_isoc(pipe); 2156 case UE_BULK: 2157 pipe->up_methods = &ohci_device_bulk_methods; 2158 mutex_enter(&sc->sc_lock); 2159 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2160 mutex_exit(&sc->sc_lock); 2161 break; 2162 } 2163 } 2164 2165 return USBD_NORMAL_COMPLETION; 2166 2167 bad: 2168 if (std != NULL) { 2169 ohci_free_std(sc, std); 2170 } 2171 if (sed != NULL) 2172 ohci_free_sed(sc, sed); 2173 return err; 2174 2175 } 2176 2177 /* 2178 * Close a reqular pipe. 2179 * Assumes that there are no pending transactions. 2180 */ 2181 void 2182 ohci_close_pipe(struct usbd_pipe *pipe, ohci_soft_ed_t *head) 2183 { 2184 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2185 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2186 ohci_soft_ed_t *sed = opipe->sed; 2187 2188 KASSERT(mutex_owned(&sc->sc_lock)); 2189 2190 #ifdef DIAGNOSTIC 2191 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2192 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2193 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2194 ohci_soft_td_t *std; 2195 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2196 printf("ohci_close_pipe: pipe not empty sed=%p hd=%#x " 2197 "tl=%#x pipe=%p, std=%p\n", sed, 2198 (int)O32TOH(sed->ed.ed_headp), 2199 (int)O32TOH(sed->ed.ed_tailp), 2200 pipe, std); 2201 #ifdef OHCI_DEBUG 2202 usbd_dump_pipe(&opipe->pipe); 2203 ohci_dump_ed(sc, sed); 2204 if (std) 2205 ohci_dump_td(sc, std); 2206 #endif 2207 usb_delay_ms(&sc->sc_bus, 2); 2208 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2209 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2210 printf("ohci_close_pipe: pipe still not empty\n"); 2211 } 2212 #endif 2213 ohci_rem_ed(sc, sed, head); 2214 /* Make sure the host controller is not touching this ED */ 2215 usb_delay_ms(&sc->sc_bus, 1); 2216 pipe->up_endpoint->ue_toggle = 2217 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2218 ohci_free_sed_locked(sc, opipe->sed); 2219 } 2220 2221 /* 2222 * Arrange for the hardware to tells us that it is not still processing 2223 * the TDs by setting the sKip bit and requesting a SOF interrupt 2224 * 2225 * Once we see the SOF interrupt we can check the transfer TDs/iTDs to see if 2226 * they've been processed and either 2227 * a) if they're unused recover them for later use, or 2228 * b) if they've been used allocate new TD/iTDs to replace those 2229 * used. The softint handler will free the old ones. 2230 */ 2231 void 2232 ohci_abortx(struct usbd_xfer *xfer) 2233 { 2234 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2235 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2236 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2237 ohci_soft_ed_t *sed = opipe->sed; 2238 ohci_soft_td_t *p, *n; 2239 ohci_physaddr_t headp; 2240 int hit; 2241 2242 DPRINTF("xfer=%#jx pipe=%#jx sed=%#jx", (uintptr_t)xfer, 2243 (uintptr_t)opipe, (uintptr_t)sed, 0); 2244 2245 KASSERT(mutex_owned(&sc->sc_lock)); 2246 ASSERT_SLEEPABLE(); 2247 2248 KASSERTMSG((xfer->ux_status == USBD_CANCELLED || 2249 xfer->ux_status == USBD_TIMEOUT), 2250 "bad abort status: %d", xfer->ux_status); 2251 2252 /* 2253 * If we're dying, skip the hardware action and just notify the 2254 * software that we're done. 2255 */ 2256 if (sc->sc_dying) { 2257 DPRINTFN(4, "xfer %#jx dying %ju", (uintptr_t)xfer, 2258 xfer->ux_status, 0, 0); 2259 goto dying; 2260 } 2261 2262 /* 2263 * HC Step 1: Unless the endpoint is already halted, we set the 2264 * endpoint descriptor sKip bit and wait for hardware to complete 2265 * processing. We ensure the HC stops processing the endpoint by 2266 * waiting for the next start of frame (OHCI_SF) 2267 */ 2268 DPRINTFN(1, "stop ed=%#jx", (uintptr_t)sed, 0, 0, 0); 2269 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2270 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2271 if (!(sed->ed.ed_flags & OHCI_HALTED)) { 2272 /* force hardware skip */ 2273 DPRINTFN(1, "pausing ed=%#jx", (uintptr_t)sed, 0, 0, 0); 2274 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2275 usb_syncmem(&sed->dma, 2276 sed->offs + offsetof(ohci_ed_t, ed_flags), 2277 sizeof(sed->ed.ed_flags), 2278 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2279 2280 DPRINTFN(10, "SF %#jx xfer %#jx", (uintptr_t)sc, 2281 (uintptr_t)xfer, 0, 0); 2282 2283 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2284 ox->ox_abintrs = OHCI_SF; 2285 2286 mutex_enter(&sc->sc_intr_lock); 2287 TAILQ_INSERT_TAIL(&sc->sc_abortingxfers, ox, ox_abnext); 2288 2289 /* Clear any previous SF interrupt */ 2290 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_SF); 2291 2292 /* Tell interrupt handler and HC SF interrupt is requested */ 2293 sc->sc_eintrs |= OHCI_SF; 2294 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_SF); 2295 /* 2296 * Step 2: Wait until we know hardware has finished any 2297 * processing of the end-point. 2298 */ 2299 while (ox->ox_abintrs != 0) { 2300 DPRINTFN(10, "SF %#jx xfer %#jx intrs %#x", 2301 (uintptr_t)sc, (uintptr_t)xfer, 2302 (uintptr_t)ox->ox_abintrs, 0); 2303 cv_wait(&sc->sc_abort_cv, &sc->sc_intr_lock); 2304 } 2305 mutex_exit(&sc->sc_intr_lock); 2306 } else { 2307 DPRINTFN(1, "halted ed=%#jx", (uintptr_t)sed, 0, 0, 0); 2308 } 2309 2310 /* 2311 * HC Step 3: Remove any vestiges of the xfer from the hardware. 2312 * There are two complications here 2313 * 2314 * 1) the hardware may have executed beyond the xfer we're trying to 2315 * abort. So as we're scanning the TDs of this xfer we check if 2316 * the hardware points to any of them. 2317 * 2318 * 2) the hardware may have only partially excuted the transfer 2319 * which means some TDs will appear on the done list. Wait for 2320 * WDH so we can remove them safely. 2321 */ 2322 p = xfer->ux_hcpriv; 2323 KASSERT(p); 2324 2325 #ifdef OHCI_DEBUG 2326 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2327 2328 if (ohcidebug >= 2) { 2329 DPRINTF("sed:", 0, 0, 0, 0); 2330 ohci_dump_ed(sc, sed); 2331 ohci_dump_tds(sc, p); 2332 } 2333 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2334 #endif 2335 2336 2337 #define OHCI_CC_ACCESSED_P(x) \ 2338 (((x) & OHCI_CC_NOT_ACCESSED_MASK) != OHCI_CC_NOT_ACCESSED) 2339 2340 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2341 hit = 0; 2342 for (; p->xfer == xfer; p = n) { 2343 hit |= headp == p->physaddr; 2344 n = p->nexttd; 2345 2346 usb_syncmem(&p->dma, p->offs + offsetof(ohci_td_t, td_flags), 2347 sizeof(p->td.td_flags), 2348 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2349 int cc = OHCI_TD_GET_CC(O32TOH(p->td.td_flags)); 2350 if (!OHCI_CC_ACCESSED_P(cc)) { 2351 ohci_hash_rem_td(sc, p); 2352 continue; 2353 } 2354 DPRINTFN(10, "xfer=%#jx has been touched by HC", (uintptr_t)p, 2355 0, 0, 0); 2356 2357 mutex_exit(&sc->sc_lock); 2358 ohci_soft_td_t *std; 2359 for (;;) { 2360 std = ohci_alloc_std(sc); 2361 if (std) 2362 break; 2363 kpause("ohciabt2", true, hz, NULL); 2364 } 2365 2366 mutex_enter(&sc->sc_lock); 2367 if (sc->sc_dying) { 2368 DPRINTFN(4, "xfer %#jx dying %ju", (uintptr_t)xfer, 2369 xfer->ux_status, 0, 0); 2370 goto dying; 2371 } 2372 2373 DPRINTFN(10, "new std=%#jx now held at %#jx", (uintptr_t)std, 2374 (uintptr_t)p->held, 0, 0); 2375 *(p->held) = std; 2376 std->held = p->held; 2377 std->xfer = xfer; 2378 p->held = NULL; 2379 } 2380 /* Zap headp register if hardware pointed inside the xfer. */ 2381 if (hit) { 2382 DPRINTFN(1, "set hd=0x%08jx, tl=0x%08jx", (int)p->physaddr, 2383 (int)O32TOH(sed->ed.ed_tailp), 0, 0); 2384 /* unlink TDs, preserving toggle carry */ 2385 sed->ed.ed_headp = HTOO32(p->physaddr | 2386 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 2387 usb_syncmem(&sed->dma, 2388 sed->offs + offsetof(ohci_ed_t, ed_headp), 2389 sizeof(sed->ed.ed_headp), 2390 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2391 } else { 2392 DPRINTFN(1, "no hit", 0, 0, 0, 0); 2393 } 2394 2395 /* 2396 * HC Step 4: Turn on hardware again. 2397 */ 2398 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2399 sizeof(sed->ed.ed_flags), 2400 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2401 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2402 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2403 sizeof(sed->ed.ed_flags), 2404 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2405 dying: 2406 DPRINTFN(14, "end", 0, 0, 0, 0); 2407 2408 KASSERT(mutex_owned(&sc->sc_lock)); 2409 } 2410 2411 /* 2412 * Data structures and routines to emulate the root hub. 2413 */ 2414 Static int 2415 ohci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2416 void *buf, int buflen) 2417 { 2418 ohci_softc_t *sc = OHCI_BUS2SC(bus); 2419 usb_port_status_t ps; 2420 uint16_t len, value, index; 2421 int l, totlen = 0; 2422 int port, i; 2423 uint32_t v; 2424 2425 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2426 2427 if (sc->sc_dying) 2428 return -1; 2429 2430 DPRINTFN(4, "type=0x%02jx request=%02jx", req->bmRequestType, 2431 req->bRequest, 0, 0); 2432 2433 len = UGETW(req->wLength); 2434 value = UGETW(req->wValue); 2435 index = UGETW(req->wIndex); 2436 2437 #define C(x,y) ((x) | ((y) << 8)) 2438 switch (C(req->bRequest, req->bmRequestType)) { 2439 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2440 DPRINTFN(8, "wValue=0x%04jx", value, 0, 0, 0); 2441 if (len == 0) 2442 break; 2443 switch (value) { 2444 #define sd ((usb_string_descriptor_t *)buf) 2445 case C(2, UDESC_STRING): 2446 /* Product */ 2447 totlen = usb_makestrdesc(sd, len, "OHCI root hub"); 2448 break; 2449 #undef sd 2450 default: 2451 /* default from usbroothub */ 2452 return buflen; 2453 } 2454 break; 2455 2456 /* Hub requests */ 2457 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2458 break; 2459 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2460 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", 2461 index, value, 0, 0); 2462 if (index < 1 || index > sc->sc_noport) { 2463 return -1; 2464 } 2465 port = OHCI_RH_PORT_STATUS(index); 2466 switch(value) { 2467 case UHF_PORT_ENABLE: 2468 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2469 break; 2470 case UHF_PORT_SUSPEND: 2471 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2472 break; 2473 case UHF_PORT_POWER: 2474 /* Yes, writing to the LOW_SPEED bit clears power. */ 2475 OWRITE4(sc, port, UPS_LOW_SPEED); 2476 break; 2477 case UHF_C_PORT_CONNECTION: 2478 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2479 break; 2480 case UHF_C_PORT_ENABLE: 2481 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2482 break; 2483 case UHF_C_PORT_SUSPEND: 2484 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2485 break; 2486 case UHF_C_PORT_OVER_CURRENT: 2487 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2488 break; 2489 case UHF_C_PORT_RESET: 2490 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2491 break; 2492 default: 2493 return -1; 2494 } 2495 switch(value) { 2496 case UHF_C_PORT_CONNECTION: 2497 case UHF_C_PORT_ENABLE: 2498 case UHF_C_PORT_SUSPEND: 2499 case UHF_C_PORT_OVER_CURRENT: 2500 case UHF_C_PORT_RESET: 2501 /* Enable RHSC interrupt if condition is cleared. */ 2502 if ((OREAD4(sc, port) >> 16) == 0) 2503 ohci_rhsc_enable(sc); 2504 break; 2505 default: 2506 break; 2507 } 2508 break; 2509 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2510 if (len == 0) 2511 break; 2512 if ((value & 0xff) != 0) { 2513 return -1; 2514 } 2515 usb_hub_descriptor_t hubd; 2516 2517 totlen = uimin(buflen, sizeof(hubd)); 2518 memcpy(&hubd, buf, totlen); 2519 2520 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2521 hubd.bNbrPorts = sc->sc_noport; 2522 USETW(hubd.wHubCharacteristics, 2523 (v & OHCI_RHD_NPS ? UHD_PWR_NO_SWITCH : 2524 v & OHCI_RHD_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2525 /* XXX overcurrent */ 2526 ); 2527 hubd.bPwrOn2PwrGood = OHCI_RHD_GET_POTPGT(v); 2528 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2529 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2530 hubd.DeviceRemovable[i++] = (uint8_t)v; 2531 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2532 totlen = uimin(totlen, hubd.bDescLength); 2533 memcpy(buf, &hubd, totlen); 2534 break; 2535 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2536 if (len != 4) { 2537 return -1; 2538 } 2539 memset(buf, 0, len); /* ? XXX */ 2540 totlen = len; 2541 break; 2542 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2543 DPRINTFN(8, "get port status i=%jd", index, 0, 0, 0); 2544 if (index < 1 || index > sc->sc_noport) { 2545 return -1; 2546 } 2547 if (len != 4) { 2548 return -1; 2549 } 2550 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2551 DPRINTFN(8, "port status=0x%04jx", v, 0, 0, 0); 2552 USETW(ps.wPortStatus, v); 2553 USETW(ps.wPortChange, v >> 16); 2554 totlen = uimin(len, sizeof(ps)); 2555 memcpy(buf, &ps, totlen); 2556 break; 2557 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2558 return -1; 2559 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2560 break; 2561 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2562 if (index < 1 || index > sc->sc_noport) { 2563 return -1; 2564 } 2565 port = OHCI_RH_PORT_STATUS(index); 2566 switch(value) { 2567 case UHF_PORT_ENABLE: 2568 OWRITE4(sc, port, UPS_PORT_ENABLED); 2569 break; 2570 case UHF_PORT_SUSPEND: 2571 OWRITE4(sc, port, UPS_SUSPEND); 2572 break; 2573 case UHF_PORT_RESET: 2574 DPRINTFN(5, "reset port %jd", index, 0, 0, 0); 2575 OWRITE4(sc, port, UPS_RESET); 2576 for (i = 0; i < 5; i++) { 2577 usb_delay_ms(&sc->sc_bus, 2578 USB_PORT_ROOT_RESET_DELAY); 2579 if (sc->sc_dying) { 2580 return -1; 2581 } 2582 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2583 break; 2584 } 2585 DPRINTFN(8, "port %jd reset, status = 0x%04jx", index, 2586 OREAD4(sc, port), 0, 0); 2587 break; 2588 case UHF_PORT_POWER: 2589 DPRINTFN(2, "set port power %jd", index, 0, 0, 0); 2590 OWRITE4(sc, port, UPS_PORT_POWER); 2591 break; 2592 default: 2593 return -1; 2594 } 2595 break; 2596 default: 2597 /* default from usbroothub */ 2598 return buflen; 2599 } 2600 2601 return totlen; 2602 } 2603 2604 Static usbd_status 2605 ohci_root_intr_transfer(struct usbd_xfer *xfer) 2606 { 2607 2608 /* Pipe isn't running, start first */ 2609 return ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2610 } 2611 2612 Static usbd_status 2613 ohci_root_intr_start(struct usbd_xfer *xfer) 2614 { 2615 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2616 2617 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2618 2619 if (sc->sc_dying) 2620 return USBD_IOERROR; 2621 2622 KASSERT(sc->sc_intrxfer == NULL); 2623 sc->sc_intrxfer = xfer; 2624 xfer->ux_status = USBD_IN_PROGRESS; 2625 2626 return USBD_IN_PROGRESS; 2627 } 2628 2629 /* Abort a root interrupt request. */ 2630 Static void 2631 ohci_root_intr_abort(struct usbd_xfer *xfer) 2632 { 2633 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2634 2635 KASSERT(mutex_owned(&sc->sc_lock)); 2636 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2637 2638 /* If xfer has already completed, nothing to do here. */ 2639 if (sc->sc_intrxfer == NULL) 2640 return; 2641 2642 /* 2643 * Otherwise, sc->sc_intrxfer had better be this transfer. 2644 * Cancel it. 2645 */ 2646 KASSERT(sc->sc_intrxfer == xfer); 2647 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 2648 xfer->ux_status = USBD_CANCELLED; 2649 usb_transfer_complete(xfer); 2650 } 2651 2652 /* Close the root pipe. */ 2653 Static void 2654 ohci_root_intr_close(struct usbd_pipe *pipe) 2655 { 2656 ohci_softc_t *sc __diagused = OHCI_PIPE2SC(pipe); 2657 2658 KASSERT(mutex_owned(&sc->sc_lock)); 2659 2660 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2661 2662 /* 2663 * Caller must guarantee the xfer has completed first, by 2664 * closing the pipe only after normal completion or an abort. 2665 */ 2666 KASSERT(sc->sc_intrxfer == NULL); 2667 } 2668 2669 /************************/ 2670 2671 int 2672 ohci_device_ctrl_init(struct usbd_xfer *xfer) 2673 { 2674 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2675 usb_device_request_t *req = &xfer->ux_request; 2676 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2677 ohci_soft_td_t *stat, *setup; 2678 int isread = req->bmRequestType & UT_READ; 2679 int len = xfer->ux_bufsize; 2680 int err = ENOMEM; 2681 2682 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2683 2684 setup = ohci_alloc_std(sc); 2685 if (setup == NULL) { 2686 goto bad1; 2687 } 2688 stat = ohci_alloc_std(sc); 2689 if (stat == NULL) { 2690 goto bad2; 2691 } 2692 2693 ox->ox_setup = setup; 2694 ox->ox_stat = stat; 2695 ox->ox_nstd = 0; 2696 setup->held = &ox->ox_setup; 2697 stat->held = &ox->ox_stat; 2698 2699 DPRINTFN(10, "xfer=%#jx setup=%#jx held at %#jx", (uintptr_t)ox, 2700 (uintptr_t)setup, (uintptr_t)setup->held, 0); 2701 DPRINTFN(10, "xfer=%#jx stat= %#jx held at %#jx", (uintptr_t)ox, 2702 (uintptr_t)stat, (uintptr_t)stat->held, 0); 2703 2704 /* Set up data transaction */ 2705 if (len != 0) { 2706 err = ohci_alloc_std_chain(sc, xfer, len, isread); 2707 if (err) { 2708 goto bad3; 2709 } 2710 } 2711 return 0; 2712 2713 bad3: 2714 ohci_free_std(sc, stat); 2715 bad2: 2716 ohci_free_std(sc, setup); 2717 bad1: 2718 return err; 2719 } 2720 2721 void 2722 ohci_device_ctrl_fini(struct usbd_xfer *xfer) 2723 { 2724 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2725 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2726 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2727 2728 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2729 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 2730 2731 mutex_enter(&sc->sc_lock); 2732 if (ox->ox_setup != opipe->tail.td) { 2733 ohci_free_std_locked(sc, ox->ox_setup); 2734 } 2735 for (size_t i = 0; i < ox->ox_nstd; i++) { 2736 ohci_soft_td_t *std = ox->ox_stds[i]; 2737 if (std == NULL) 2738 break; 2739 ohci_free_std_locked(sc, std); 2740 } 2741 ohci_free_std_locked(sc, ox->ox_stat); 2742 mutex_exit(&sc->sc_lock); 2743 2744 if (ox->ox_nstd) { 2745 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 2746 kmem_free(ox->ox_stds, sz); 2747 } 2748 } 2749 2750 Static usbd_status 2751 ohci_device_ctrl_transfer(struct usbd_xfer *xfer) 2752 { 2753 2754 /* Pipe isn't running, start first */ 2755 return ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2756 } 2757 2758 Static usbd_status 2759 ohci_device_ctrl_start(struct usbd_xfer *xfer) 2760 { 2761 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2762 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2763 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2764 usb_device_request_t *req = &xfer->ux_request; 2765 struct usbd_device *dev __diagused = opipe->pipe.up_dev; 2766 ohci_soft_td_t *setup, *stat, *next, *tail; 2767 ohci_soft_ed_t *sed; 2768 int isread; 2769 int len; 2770 2771 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2772 2773 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2774 2775 if (sc->sc_dying) 2776 return USBD_IOERROR; 2777 2778 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2779 2780 isread = req->bmRequestType & UT_READ; 2781 len = UGETW(req->wLength); 2782 2783 DPRINTF("xfer=%#jx len=%jd, addr=%jd, endpt=%jd", (uintptr_t)xfer, len, 2784 dev->ud_addr, opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress); 2785 DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx", 2786 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2787 UGETW(req->wIndex)); 2788 2789 /* 2790 * Use the pipe "tail" TD as our first and loan our first TD to the 2791 * next transfer 2792 */ 2793 setup = opipe->tail.td; 2794 opipe->tail.td = ox->ox_setup; 2795 ox->ox_setup = setup; 2796 setup->held = &ox->ox_setup; 2797 2798 DPRINTFN(10, "xfer=%#jx new setup=%#jx held at %#jx", (uintptr_t)ox, 2799 (uintptr_t)setup, (uintptr_t)setup->held, 0); 2800 2801 stat = ox->ox_stat; 2802 2803 /* point at sentinel */ 2804 tail = opipe->tail.td; 2805 tail->held = &opipe->tail.td; 2806 sed = opipe->sed; 2807 2808 DPRINTFN(10, "xfer=%#jx new tail=%#jx held at %#jx", (uintptr_t)ox, 2809 (uintptr_t)tail, (uintptr_t)tail->held, 0); 2810 2811 KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->ud_addr, 2812 "address ED %" __PRIuBITS " pipe %d\n", 2813 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->ud_addr); 2814 KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) == 2815 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 2816 "MPL ED %" __PRIuBITS " pipe %d\n", 2817 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), 2818 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 2819 2820 /* next will point to data if len != 0 */ 2821 next = stat; 2822 2823 /* Set up data transaction */ 2824 if (len != 0) { 2825 ohci_soft_td_t *std; 2826 ohci_soft_td_t *end; 2827 2828 next = ox->ox_stds[0]; 2829 ohci_reset_std_chain(sc, xfer, len, isread, next, &end); 2830 2831 end->td.td_nexttd = HTOO32(stat->physaddr); 2832 end->nexttd = stat; 2833 2834 usb_syncmem(&end->dma, end->offs, sizeof(end->td), 2835 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2836 2837 usb_syncmem(&xfer->ux_dmabuf, 0, len, 2838 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2839 std = ox->ox_stds[0]; 2840 /* Start toggle at 1 and then use the carried toggle. */ 2841 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 2842 std->td.td_flags |= HTOO32(OHCI_TD_SET_TOGGLE(OHCI_TD_TOGGLE_1)); 2843 usb_syncmem(&std->dma, 2844 std->offs + offsetof(ohci_td_t, td_flags), 2845 sizeof(std->td.td_flags), 2846 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2847 } 2848 2849 DPRINTFN(8, "setup %#jx data %#jx stat %#jx tail %#jx", 2850 (uintptr_t)setup, 2851 (uintptr_t)(len != 0 ? ox->ox_stds[0] : NULL), (uintptr_t)stat, 2852 (uintptr_t)tail); 2853 KASSERT(opipe->tail.td == tail); 2854 2855 memcpy(KERNADDR(&opipe->ctrl.reqdma, 0), req, sizeof(*req)); 2856 usb_syncmem(&opipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2857 2858 setup->td.td_flags = HTOO32( 2859 OHCI_TD_SET_DP(OHCI_TD_DP_SETUP) | 2860 OHCI_TD_SET_CC(OHCI_TD_NOCC) | 2861 OHCI_TD_SET_TOGGLE(OHCI_TD_TOGGLE_0) | 2862 OHCI_TD_SET_DI(OHCI_TD_NOINTR) 2863 ); 2864 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->ctrl.reqdma, 0)); 2865 setup->td.td_nexttd = HTOO32(next->physaddr); 2866 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof(*req) - 1); 2867 setup->nexttd = next; 2868 setup->len = 0; 2869 setup->xfer = xfer; 2870 setup->flags = 0; 2871 ohci_hash_add_td(sc, setup); 2872 2873 xfer->ux_hcpriv = setup; 2874 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2875 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2876 2877 stat->td.td_flags = HTOO32( 2878 OHCI_TD_SET_DP(isread ? OHCI_TD_DP_OUT : OHCI_TD_DP_IN) | 2879 OHCI_TD_SET_CC(OHCI_TD_NOCC) | 2880 OHCI_TD_SET_TOGGLE(OHCI_TD_TOGGLE_1) | 2881 OHCI_TD_SET_DI(1) 2882 ); 2883 stat->td.td_cbp = 0; 2884 stat->td.td_nexttd = HTOO32(tail->physaddr); 2885 stat->td.td_be = 0; 2886 stat->nexttd = tail; 2887 stat->flags = OHCI_CALL_DONE; 2888 stat->len = 0; 2889 stat->xfer = xfer; 2890 ohci_hash_add_td(sc, stat); 2891 2892 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2893 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2894 2895 memset(&tail->td, 0, sizeof(tail->td)); 2896 tail->nexttd = NULL; 2897 tail->xfer = NULL; 2898 2899 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 2900 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2901 2902 #ifdef OHCI_DEBUG 2903 USBHIST_LOGN(ohcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2904 if (ohcidebug >= 5) { 2905 ohci_dump_ed(sc, sed); 2906 ohci_dump_tds(sc, setup); 2907 } 2908 USBHIST_LOGN(ohcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2909 #endif 2910 2911 /* Insert ED in schedule */ 2912 sed->ed.ed_tailp = HTOO32(tail->physaddr); 2913 usb_syncmem(&sed->dma, 2914 sed->offs + offsetof(ohci_ed_t, ed_tailp), 2915 sizeof(sed->ed.ed_tailp), 2916 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2917 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2918 usbd_xfer_schedule_timeout(xfer); 2919 2920 DPRINTF("done", 0, 0, 0, 0); 2921 2922 xfer->ux_status = USBD_IN_PROGRESS; 2923 2924 return USBD_IN_PROGRESS; 2925 } 2926 2927 /* Abort a device control request. */ 2928 Static void 2929 ohci_device_ctrl_abort(struct usbd_xfer *xfer) 2930 { 2931 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 2932 2933 KASSERT(mutex_owned(&sc->sc_lock)); 2934 2935 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2936 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 2937 usbd_xfer_abort(xfer); 2938 } 2939 2940 /* Close a device control pipe. */ 2941 Static void 2942 ohci_device_ctrl_close(struct usbd_pipe *pipe) 2943 { 2944 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2945 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2946 2947 KASSERT(mutex_owned(&sc->sc_lock)); 2948 2949 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2950 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 2951 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2952 ohci_free_std_locked(sc, opipe->tail.td); 2953 2954 usb_freemem(&opipe->ctrl.reqdma); 2955 } 2956 2957 /************************/ 2958 2959 Static void 2960 ohci_device_clear_toggle(struct usbd_pipe *pipe) 2961 { 2962 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2963 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2964 ohci_soft_ed_t *sed = opipe->sed; 2965 2966 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_headp), 2967 sizeof(sed->ed.ed_headp), 2968 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2969 2970 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2971 2972 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_headp), 2973 sizeof(sed->ed.ed_headp), 2974 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2975 } 2976 2977 Static void 2978 ohci_noop(struct usbd_pipe *pipe) 2979 { 2980 } 2981 2982 Static int 2983 ohci_device_bulk_init(struct usbd_xfer *xfer) 2984 { 2985 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2986 int len = xfer->ux_bufsize; 2987 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2988 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2989 int err; 2990 2991 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2992 2993 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2994 2995 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 2996 len, isread, xfer->ux_flags); 2997 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 2998 2999 /* Allocate a chain of new TDs (including a new tail). */ 3000 err = ohci_alloc_std_chain(sc, xfer, len, isread); 3001 if (err) 3002 return err; 3003 3004 return 0; 3005 } 3006 3007 Static void 3008 ohci_device_bulk_fini(struct usbd_xfer *xfer) 3009 { 3010 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3011 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3012 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3013 3014 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3015 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 3016 3017 mutex_enter(&sc->sc_lock); 3018 for (size_t i = 0; i < ox->ox_nstd; i++) { 3019 ohci_soft_td_t *std = ox->ox_stds[i]; 3020 if (std == NULL) 3021 break; 3022 if (std != opipe->tail.td) 3023 ohci_free_std_locked(sc, std); 3024 } 3025 mutex_exit(&sc->sc_lock); 3026 3027 if (ox->ox_nstd) { 3028 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 3029 kmem_free(ox->ox_stds, sz); 3030 } 3031 } 3032 3033 Static usbd_status 3034 ohci_device_bulk_transfer(struct usbd_xfer *xfer) 3035 { 3036 3037 /* Pipe isn't running, start first */ 3038 return ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3039 } 3040 3041 Static usbd_status 3042 ohci_device_bulk_start(struct usbd_xfer *xfer) 3043 { 3044 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3045 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3046 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3047 ohci_soft_td_t *last; 3048 ohci_soft_td_t *data, *tail, *tdp; 3049 ohci_soft_ed_t *sed; 3050 int len, isread, endpt; 3051 3052 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3053 3054 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3055 3056 if (sc->sc_dying) 3057 return USBD_IOERROR; 3058 3059 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3060 3061 len = xfer->ux_length; 3062 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3063 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3064 sed = opipe->sed; 3065 3066 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 3067 len, isread, xfer->ux_flags); 3068 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 3069 3070 /* 3071 * Use the pipe "tail" TD as our first and loan our first TD to the 3072 * next transfer 3073 */ 3074 data = opipe->tail.td; 3075 opipe->tail.td = ox->ox_stds[0]; 3076 ox->ox_stds[0] = data; 3077 data->held = &ox->ox_stds[0]; 3078 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3079 DPRINTFN(10, "xfer=%#jx new data=%#jx held at %#jx", 3080 (uintptr_t)ox, (uintptr_t)data, (uintptr_t)data->held, 0); 3081 3082 /* point at sentinel */ 3083 tail = opipe->tail.td; 3084 memset(&tail->td, 0, sizeof(tail->td)); 3085 tail->held = &opipe->tail.td; 3086 tail->nexttd = NULL; 3087 tail->xfer = NULL; 3088 DPRINTFN(10, "xfer=%#jx new tail=%#jx held at %#ux", 3089 (uintptr_t)ox, (uintptr_t)tail, (uintptr_t)tail->held, 0); 3090 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3091 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3092 xfer->ux_hcpriv = data; 3093 3094 DPRINTFN(8, "xfer %#jx data %#jx tail %#jx", (uintptr_t)xfer, 3095 (uintptr_t)ox->ox_stds[0], (uintptr_t)tail, 0); 3096 KASSERT(opipe->tail.td == tail); 3097 3098 /* We want interrupt at the end of the transfer. */ 3099 last->td.td_flags &= HTOO32(~OHCI_TD_DI_MASK); 3100 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3101 last->td.td_nexttd = HTOO32(tail->physaddr); 3102 last->nexttd = tail; 3103 last->flags |= OHCI_CALL_DONE; 3104 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3105 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3106 3107 DPRINTFN(4, "ed_flags=0x%08jx td_flags=0x%08jx " 3108 "td_cbp=0x%08jx td_be=0x%08jx", 3109 (int)O32TOH(sed->ed.ed_flags), 3110 (int)O32TOH(data->td.td_flags), 3111 (int)O32TOH(data->td.td_cbp), 3112 (int)O32TOH(data->td.td_be)); 3113 3114 #ifdef OHCI_DEBUG 3115 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3116 if (ohcidebug >= 5) { 3117 ohci_dump_ed(sc, sed); 3118 ohci_dump_tds(sc, data); 3119 } 3120 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3121 #endif 3122 3123 /* Insert ED in schedule */ 3124 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3125 KASSERT(tdp->xfer == xfer); 3126 } 3127 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3128 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3129 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3130 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3131 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3132 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3133 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3134 usbd_xfer_schedule_timeout(xfer); 3135 xfer->ux_status = USBD_IN_PROGRESS; 3136 3137 return USBD_IN_PROGRESS; 3138 } 3139 3140 Static void 3141 ohci_device_bulk_abort(struct usbd_xfer *xfer) 3142 { 3143 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3144 3145 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3146 3147 KASSERT(mutex_owned(&sc->sc_lock)); 3148 3149 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3150 usbd_xfer_abort(xfer); 3151 } 3152 3153 /* 3154 * Close a device bulk pipe. 3155 */ 3156 Static void 3157 ohci_device_bulk_close(struct usbd_pipe *pipe) 3158 { 3159 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3160 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3161 3162 KASSERT(mutex_owned(&sc->sc_lock)); 3163 3164 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3165 3166 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3167 ohci_close_pipe(pipe, sc->sc_bulk_head); 3168 ohci_free_std_locked(sc, opipe->tail.td); 3169 } 3170 3171 /************************/ 3172 3173 Static int 3174 ohci_device_intr_init(struct usbd_xfer *xfer) 3175 { 3176 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3177 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3178 int len = xfer->ux_bufsize; 3179 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3180 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3181 int err; 3182 3183 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3184 3185 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3186 KASSERT(len != 0); 3187 3188 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 3189 len, isread, xfer->ux_flags); 3190 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 3191 3192 ox->ox_nstd = 0; 3193 3194 err = ohci_alloc_std_chain(sc, xfer, len, isread); 3195 if (err) { 3196 return err; 3197 } 3198 3199 return 0; 3200 } 3201 3202 Static void 3203 ohci_device_intr_fini(struct usbd_xfer *xfer) 3204 { 3205 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3206 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3207 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3208 3209 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3210 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 3211 3212 mutex_enter(&sc->sc_lock); 3213 for (size_t i = 0; i < ox->ox_nstd; i++) { 3214 ohci_soft_td_t *std = ox->ox_stds[i]; 3215 if (std != NULL) 3216 break; 3217 if (std != opipe->tail.td) 3218 ohci_free_std_locked(sc, std); 3219 } 3220 mutex_exit(&sc->sc_lock); 3221 3222 if (ox->ox_nstd) { 3223 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 3224 kmem_free(ox->ox_stds, sz); 3225 } 3226 } 3227 3228 Static usbd_status 3229 ohci_device_intr_transfer(struct usbd_xfer *xfer) 3230 { 3231 3232 /* Pipe isn't running, start first */ 3233 return ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3234 } 3235 3236 Static usbd_status 3237 ohci_device_intr_start(struct usbd_xfer *xfer) 3238 { 3239 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3240 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3241 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3242 ohci_soft_ed_t *sed = opipe->sed; 3243 ohci_soft_td_t *data, *last, *tail; 3244 int len, isread, endpt; 3245 3246 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3247 3248 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3249 3250 if (sc->sc_dying) 3251 return USBD_IOERROR; 3252 3253 DPRINTFN(3, "xfer=%#jx len=%jd flags=%jd priv=%#jx", (uintptr_t)xfer, 3254 xfer->ux_length, xfer->ux_flags, (uintptr_t)xfer->ux_priv); 3255 3256 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3257 3258 len = xfer->ux_length; 3259 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3260 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3261 3262 /* 3263 * Use the pipe "tail" TD as our first and loan our first TD to the 3264 * next transfer. 3265 */ 3266 data = opipe->tail.td; 3267 opipe->tail.td = ox->ox_stds[0]; 3268 ox->ox_stds[0] = data; 3269 data->held = &ox->ox_stds[0]; 3270 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3271 DPRINTFN(10, "xfer=%#jx new data=%#jx held at %#jx", 3272 (uintptr_t)ox, (uintptr_t)data, (uintptr_t)data->held, 0); 3273 3274 /* point at sentinel */ 3275 tail = opipe->tail.td; 3276 memset(&tail->td, 0, sizeof(tail->td)); 3277 tail->held = &opipe->tail.td; 3278 tail->nexttd = NULL; 3279 tail->xfer = NULL; 3280 DPRINTFN(10, "xfer=%#jx new tail=%#jx held at %#jx", 3281 (uintptr_t)ox, (uintptr_t)tail, (uintptr_t)tail->held, 0); 3282 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3283 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3284 xfer->ux_hcpriv = data; 3285 3286 DPRINTFN(8, "data %#jx tail %#jx", (uintptr_t)ox->ox_stds[0], 3287 (uintptr_t)tail, 0, 0); 3288 KASSERT(opipe->tail.td == tail); 3289 3290 /* We want interrupt at the end of the transfer. */ 3291 last->td.td_flags &= HTOO32(~OHCI_TD_DI_MASK); 3292 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3293 3294 last->td.td_nexttd = HTOO32(tail->physaddr); 3295 last->nexttd = tail; 3296 last->flags |= OHCI_CALL_DONE; 3297 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3298 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3299 3300 #ifdef OHCI_DEBUG 3301 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3302 if (ohcidebug >= 5) { 3303 ohci_dump_ed(sc, sed); 3304 ohci_dump_tds(sc, data); 3305 } 3306 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3307 #endif 3308 3309 /* Insert ED in schedule */ 3310 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3311 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3312 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3313 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3314 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3315 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3316 3317 xfer->ux_status = USBD_IN_PROGRESS; 3318 3319 return USBD_IN_PROGRESS; 3320 } 3321 3322 /* Abort a device interrupt request. */ 3323 Static void 3324 ohci_device_intr_abort(struct usbd_xfer *xfer) 3325 { 3326 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3327 3328 KASSERT(mutex_owned(&sc->sc_lock)); 3329 3330 usbd_xfer_abort(xfer); 3331 } 3332 3333 /* Close a device interrupt pipe. */ 3334 Static void 3335 ohci_device_intr_close(struct usbd_pipe *pipe) 3336 { 3337 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3338 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3339 int nslots = opipe->intr.nslots; 3340 int pos = opipe->intr.pos; 3341 int j; 3342 ohci_soft_ed_t *p, *sed = opipe->sed; 3343 3344 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3345 3346 KASSERT(mutex_owned(&sc->sc_lock)); 3347 3348 DPRINTFN(1, "pipe=%#jx nslots=%jd pos=%jd", (uintptr_t)pipe, nslots, 3349 pos, 0); 3350 usb_syncmem(&sed->dma, sed->offs, 3351 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3352 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3353 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3354 sizeof(sed->ed.ed_flags), 3355 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3356 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3357 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3358 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3359 3360 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3361 continue; 3362 KASSERT(p); 3363 p->next = sed->next; 3364 p->ed.ed_nexted = sed->ed.ed_nexted; 3365 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3366 sizeof(p->ed.ed_nexted), 3367 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3368 3369 for (j = 0; j < nslots; j++) 3370 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3371 3372 ohci_free_std_locked(sc, opipe->tail.td); 3373 ohci_free_sed_locked(sc, opipe->sed); 3374 } 3375 3376 Static usbd_status 3377 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3378 { 3379 int i, j, best; 3380 u_int npoll, slow, shigh, nslots; 3381 u_int bestbw, bw; 3382 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3383 3384 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3385 3386 DPRINTFN(2, "pipe=%#jx", (uintptr_t)opipe, 0, 0, 0); 3387 if (ival == 0) { 3388 printf("ohci_setintr: 0 interval\n"); 3389 return USBD_INVAL; 3390 } 3391 3392 npoll = OHCI_NO_INTRS; 3393 while (npoll > ival) 3394 npoll /= 2; 3395 DPRINTFN(2, "ival=%jd npoll=%jd", ival, npoll, 0, 0); 3396 3397 /* 3398 * We now know which level in the tree the ED must go into. 3399 * Figure out which slot has most bandwidth left over. 3400 * Slots to examine: 3401 * npoll 3402 * 1 0 3403 * 2 1 2 3404 * 4 3 4 5 6 3405 * 8 7 8 9 10 11 12 13 14 3406 * N (N-1) .. (N-1+N-1) 3407 */ 3408 slow = npoll-1; 3409 shigh = slow + npoll; 3410 nslots = OHCI_NO_INTRS / npoll; 3411 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3412 bw = 0; 3413 for (j = 0; j < nslots; j++) 3414 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3415 if (bw < bestbw) { 3416 best = i; 3417 bestbw = bw; 3418 } 3419 } 3420 DPRINTFN(2, "best=%jd(%jd..%jd) bestbw=%jd", best, slow, shigh, bestbw); 3421 3422 mutex_enter(&sc->sc_lock); 3423 hsed = sc->sc_eds[best]; 3424 sed->next = hsed->next; 3425 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 3426 sizeof(sed->ed.ed_nexted), 3427 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3428 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3429 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 3430 sizeof(sed->ed.ed_nexted), 3431 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3432 3433 hsed->next = sed; 3434 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_nexted), 3435 sizeof(hsed->ed.ed_nexted), 3436 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3437 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3438 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_nexted), 3439 sizeof(hsed->ed.ed_nexted), 3440 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3441 mutex_exit(&sc->sc_lock); 3442 3443 for (j = 0; j < nslots; j++) 3444 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3445 opipe->intr.nslots = nslots; 3446 opipe->intr.pos = best; 3447 3448 DPRINTFN(5, "returns %#jx", (uintptr_t)opipe, 0, 0, 0); 3449 return USBD_NORMAL_COMPLETION; 3450 } 3451 3452 /***********************/ 3453 3454 Static int 3455 ohci_device_isoc_init(struct usbd_xfer *xfer) 3456 { 3457 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3458 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3459 ohci_soft_itd_t *sitd; 3460 size_t i; 3461 int err; 3462 3463 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3464 3465 DPRINTFN(1, "xfer %#jx len %jd flags %jd", (uintptr_t)xfer, 3466 xfer->ux_length, xfer->ux_flags, 0); 3467 3468 const size_t nfsitd = howmany(xfer->ux_nframes, OHCI_ITD_NOFFSET); 3469 const size_t nbsitd = xfer->ux_bufsize / OHCI_PAGE_SIZE; 3470 const size_t nsitd = MAX(nfsitd, nbsitd) + 1; 3471 3472 ox->ox_sitds = kmem_zalloc(sizeof(ohci_soft_itd_t *) * nsitd, 3473 KM_SLEEP); 3474 ox->ox_nsitd = nsitd; 3475 3476 for (i = 0; i < nsitd; i++) { 3477 /* Allocate next ITD */ 3478 sitd = ohci_alloc_sitd(sc); 3479 if (sitd == NULL) { 3480 err = ENOMEM; 3481 goto fail; 3482 } 3483 ox->ox_sitds[i] = sitd; 3484 sitd->held = &ox->ox_sitds[i]; 3485 sitd->xfer = xfer; 3486 sitd->flags = 0; 3487 // DPRINTFN(10, "xfer=%#jx new tail=%#jx held at %#jx", 3488 // (uintptr_t)ox, (uintptr_t)tail, (uintptr_t)tail->held, 0); 3489 } 3490 3491 return 0; 3492 fail: 3493 for (; i > 0;) { 3494 ohci_free_sitd(sc, ox->ox_sitds[--i]); 3495 } 3496 return err; 3497 } 3498 3499 Static void 3500 ohci_device_isoc_fini(struct usbd_xfer *xfer) 3501 { 3502 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3503 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3504 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3505 3506 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3507 3508 mutex_enter(&sc->sc_lock); 3509 for (size_t i = 0; i < ox->ox_nsitd; i++) { 3510 if (ox->ox_sitds[i] != opipe->tail.itd) { 3511 ohci_free_sitd_locked(sc, ox->ox_sitds[i]); 3512 } 3513 } 3514 mutex_exit(&sc->sc_lock); 3515 3516 if (ox->ox_nsitd) { 3517 const size_t sz = sizeof(ohci_soft_itd_t *) * ox->ox_nsitd; 3518 kmem_free(ox->ox_sitds, sz); 3519 } 3520 } 3521 3522 3523 usbd_status 3524 ohci_device_isoc_transfer(struct usbd_xfer *xfer) 3525 { 3526 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3527 3528 DPRINTFN(5, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3529 3530 /* insert into schedule, */ 3531 ohci_device_isoc_enter(xfer); 3532 3533 /* and start if the pipe wasn't running */ 3534 return USBD_IN_PROGRESS; 3535 } 3536 3537 void 3538 ohci_device_isoc_enter(struct usbd_xfer *xfer) 3539 { 3540 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3541 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3542 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3543 ohci_soft_ed_t *sed = opipe->sed; 3544 ohci_soft_itd_t *sitd, *nsitd, *tail; 3545 ohci_physaddr_t buf, offs, bp0, bp1; 3546 int i, ncur, nframes; 3547 size_t boff, frlen; 3548 3549 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3550 DPRINTFN(5, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3551 3552 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3553 3554 if (sc->sc_dying) 3555 return; 3556 3557 struct isoc *isoc = &opipe->isoc; 3558 3559 DPRINTFN(1, "used=%jd next=%jd xfer=%#jx nframes=%jd", 3560 isoc->inuse, isoc->next, (uintptr_t)xfer, xfer->ux_nframes); 3561 3562 int isread = 3563 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 3564 3565 if (xfer->ux_length) 3566 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3567 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3568 3569 if (isoc->next == -1) { 3570 /* Not in use yet, schedule it a few frames ahead. */ 3571 usb_syncmem(&sc->sc_hccadma, 3572 offsetof(struct ohci_hcca, hcca_frame_number), 3573 sizeof(sc->sc_hcca->hcca_frame_number), 3574 BUS_DMASYNC_POSTREAD); 3575 isoc->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3576 DPRINTFN(2,"start next=%jd", isoc->next, 0, 0, 0); 3577 } 3578 3579 sitd = opipe->tail.itd; 3580 opipe->tail.itd = ox->ox_sitds[0]; 3581 ox->ox_sitds[0] = sitd; 3582 sitd->held = &ox->ox_sitds[0]; 3583 3584 boff = 0; 3585 buf = DMAADDR(&xfer->ux_dmabuf, 0); 3586 bp0 = bp1 = OHCI_PAGE(buf); 3587 offs = OHCI_PAGE_OFFSET(buf); 3588 3589 ohci_physaddr_t end = bp0; /* XXX stupid GCC */ 3590 3591 nframes = xfer->ux_nframes; 3592 xfer->ux_hcpriv = sitd; 3593 size_t j = 1; 3594 for (i = ncur = 0; i < nframes; i++, ncur++) { 3595 frlen = xfer->ux_frlengths[i]; 3596 3597 DPRINTFN(1, "frame=%jd ux_frlengths[%jd]=%jd", i, i, 3598 xfer->ux_frlengths[i], 0); 3599 /* 3600 * XXXNH: The loop assumes this is never true, because 3601 * incrementing 'i' assumes all the ux_frlengths[i] is covered. 3602 */ 3603 if (frlen > 2 * OHCI_PAGE_SIZE - offs) 3604 frlen = 2 * OHCI_PAGE_SIZE - offs; 3605 3606 boff += frlen; 3607 buf = DMAADDR(&xfer->ux_dmabuf, boff); 3608 ohci_physaddr_t noffs = OHCI_PAGE_OFFSET(buf); 3609 3610 ohci_physaddr_t nend = DMAADDR(&xfer->ux_dmabuf, boff - 1); 3611 const ohci_physaddr_t nep = OHCI_PAGE(nend); 3612 3613 /* Note the first page crossing in bp1 */ 3614 if (bp0 == bp1 && bp1 != nep) 3615 bp1 = nep; 3616 3617 DPRINTFN(1, "ncur=%jd bp0=%#jx bp1=%#jx nend=%#jx", 3618 ncur, bp0, bp1, nend); 3619 3620 /* all offsets used or too many page crossings */ 3621 if (ncur == OHCI_ITD_NOFFSET || (bp0 != bp1 && bp1 != nep)) { 3622 /* Allocate next ITD */ 3623 nsitd = ox->ox_sitds[j++]; 3624 KASSERT(nsitd != NULL); 3625 KASSERT(j < ox->ox_nsitd); 3626 3627 /* Fill current ITD */ 3628 sitd->itd.itd_flags = HTOO32( 3629 OHCI_ITD_SET_CC(OHCI_ITD_NOCC) | 3630 OHCI_ITD_SET_SF(isoc->next) | 3631 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3632 OHCI_ITD_SET_FC(ncur) 3633 ); 3634 sitd->itd.itd_bp0 = HTOO32(bp0); 3635 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3636 sitd->itd.itd_be = HTOO32(end); 3637 sitd->nextitd = nsitd; 3638 sitd->xfer = xfer; 3639 sitd->flags = 0; 3640 #ifdef DIAGNOSTIC 3641 sitd->isdone = false; 3642 #endif 3643 ohci_hash_add_itd(sc, sitd); 3644 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3645 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3646 3647 sitd = nsitd; 3648 isoc->next = isoc->next + ncur; 3649 bp0 = bp1 = OHCI_PAGE(buf); 3650 ncur = 0; 3651 } 3652 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3653 end = nend; 3654 offs = noffs; 3655 } 3656 KASSERT(j <= ox->ox_nsitd); 3657 3658 /* point at sentinel */ 3659 tail = opipe->tail.itd; 3660 memset(&tail->itd, 0, sizeof(tail->itd)); 3661 tail->held = &opipe->tail.itd; 3662 tail->nextitd = NULL; 3663 tail->xfer = NULL; 3664 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->itd), 3665 BUS_DMASYNC_PREWRITE); 3666 3667 /* Fixup last used ITD */ 3668 sitd->itd.itd_flags = HTOO32( 3669 OHCI_ITD_SET_CC(OHCI_ITD_NOCC) | 3670 OHCI_ITD_SET_SF(isoc->next) | 3671 OHCI_ITD_SET_DI(0) | 3672 OHCI_ITD_SET_FC(ncur) 3673 ); 3674 sitd->itd.itd_bp0 = HTOO32(bp0); 3675 sitd->itd.itd_nextitd = HTOO32(tail->physaddr); 3676 sitd->itd.itd_be = HTOO32(end); 3677 sitd->nextitd = tail; 3678 sitd->xfer = xfer; 3679 sitd->flags = OHCI_CALL_DONE; 3680 #ifdef DIAGNOSTIC 3681 sitd->isdone = false; 3682 #endif 3683 ohci_hash_add_itd(sc, sitd); 3684 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3685 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3686 3687 isoc->next = isoc->next + ncur; 3688 isoc->inuse += nframes; 3689 3690 /* XXX pretend we did it all */ 3691 xfer->ux_actlen = offs; 3692 xfer->ux_status = USBD_IN_PROGRESS; 3693 3694 #ifdef OHCI_DEBUG 3695 if (ohcidebug >= 5) { 3696 usb_syncmem(&sc->sc_hccadma, 3697 offsetof(struct ohci_hcca, hcca_frame_number), 3698 sizeof(sc->sc_hcca->hcca_frame_number), 3699 BUS_DMASYNC_POSTREAD); 3700 DPRINTF("frame=%jd", O32TOH(sc->sc_hcca->hcca_frame_number), 3701 0, 0, 0); 3702 ohci_dump_itds(sc, xfer->ux_hcpriv); 3703 ohci_dump_ed(sc, sed); 3704 } 3705 #endif 3706 3707 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3708 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3709 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3710 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3711 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3712 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3713 } 3714 3715 void 3716 ohci_device_isoc_abort(struct usbd_xfer *xfer) 3717 { 3718 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3719 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3720 ohci_soft_ed_t *sed; 3721 ohci_soft_itd_t *sitd; 3722 3723 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3724 DPRINTFN(1, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3725 3726 KASSERT(mutex_owned(&sc->sc_lock)); 3727 3728 /* Transfer is already done. */ 3729 if (xfer->ux_status != USBD_NOT_STARTED && 3730 xfer->ux_status != USBD_IN_PROGRESS) { 3731 printf("ohci_device_isoc_abort: early return\n"); 3732 goto done; 3733 } 3734 3735 /* Give xfer the requested abort code. */ 3736 xfer->ux_status = USBD_CANCELLED; 3737 3738 sed = opipe->sed; 3739 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3740 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3741 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3742 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3743 sizeof(sed->ed.ed_flags), 3744 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3745 3746 sitd = xfer->ux_hcpriv; 3747 KASSERT(sitd); 3748 3749 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3750 3751 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3752 ohci_hash_rem_itd(sc, sitd); 3753 #ifdef DIAGNOSTIC 3754 DPRINTFN(1, "abort sets done sitd=%#jx", (uintptr_t)sitd, 3755 0, 0, 0); 3756 sitd->isdone = true; 3757 #endif 3758 } 3759 3760 /* Run callback. */ 3761 usb_transfer_complete(xfer); 3762 3763 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3764 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3765 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3766 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3767 3768 done: 3769 KASSERT(mutex_owned(&sc->sc_lock)); 3770 } 3771 3772 void 3773 ohci_device_isoc_done(struct usbd_xfer *xfer) 3774 { 3775 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3776 DPRINTFN(1, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3777 3778 int isread = 3779 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 3780 3781 DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 3782 0, 0); 3783 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3784 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3785 } 3786 3787 usbd_status 3788 ohci_setup_isoc(struct usbd_pipe *pipe) 3789 { 3790 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3791 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3792 struct isoc *isoc = &opipe->isoc; 3793 3794 isoc->next = -1; 3795 isoc->inuse = 0; 3796 3797 mutex_enter(&sc->sc_lock); 3798 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3799 mutex_exit(&sc->sc_lock); 3800 3801 return USBD_NORMAL_COMPLETION; 3802 } 3803 3804 void 3805 ohci_device_isoc_close(struct usbd_pipe *pipe) 3806 { 3807 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3808 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3809 3810 KASSERT(mutex_owned(&sc->sc_lock)); 3811 3812 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3813 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3814 ohci_close_pipe(pipe, sc->sc_isoc_head); 3815 #ifdef DIAGNOSTIC 3816 opipe->tail.itd->isdone = true; 3817 #endif 3818 ohci_free_sitd_locked(sc, opipe->tail.itd); 3819 } 3820
Indexes created Fri Oct 03 02:09:57 GMT 2025