ohci.c revision 1.325
1 /* $NetBSD: ohci.c,v 1.325 2024/02/09 22:08:37 andvar Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012, 2016, 2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca), 10 * Matthew R. Green (mrg (at) eterna23.net), and Nick Hudson. 11 * 12 * This code is derived from software contributed to The NetBSD Foundation 13 * by Charles M. Hannum. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * USB Open Host Controller driver. 39 * 40 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 41 * USB spec: http://www.usb.org/developers/docs/ 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.325 2024/02/09 22:08:37 andvar Exp $"); 46 47 #ifdef _KERNEL_OPT 48 #include "opt_usb.h" 49 #endif 50 51 #include <sys/param.h> 52 53 #include <sys/cpu.h> 54 #include <sys/device.h> 55 #include <sys/kernel.h> 56 #include <sys/kmem.h> 57 #include <sys/proc.h> 58 #include <sys/queue.h> 59 #include <sys/select.h> 60 #include <sys/sysctl.h> 61 #include <sys/systm.h> 62 63 #include <machine/endian.h> 64 65 #include <dev/usb/usb.h> 66 #include <dev/usb/usbdi.h> 67 #include <dev/usb/usbdivar.h> 68 #include <dev/usb/usb_mem.h> 69 #include <dev/usb/usb_quirks.h> 70 71 #include <dev/usb/ohcireg.h> 72 #include <dev/usb/ohcivar.h> 73 #include <dev/usb/usbroothub.h> 74 #include <dev/usb/usbhist.h> 75 76 #ifdef USB_DEBUG 77 #ifndef OHCI_DEBUG 78 #define ohcidebug 0 79 #else 80 static int ohcidebug = 0; 81 82 SYSCTL_SETUP(sysctl_hw_ohci_setup, "sysctl hw.ohci setup") 83 { 84 int err; 85 const struct sysctlnode *rnode; 86 const struct sysctlnode *cnode; 87 88 err = sysctl_createv(clog, 0, NULL, &rnode, 89 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ohci", 90 SYSCTL_DESCR("ohci global controls"), 91 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 92 93 if (err) 94 goto fail; 95 96 /* control debugging printfs */ 97 err = sysctl_createv(clog, 0, &rnode, &cnode, 98 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 99 "debug", SYSCTL_DESCR("Enable debugging output"), 100 NULL, 0, &ohcidebug, sizeof(ohcidebug), CTL_CREATE, CTL_EOL); 101 if (err) 102 goto fail; 103 104 return; 105 fail: 106 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 107 } 108 109 #endif /* OHCI_DEBUG */ 110 #endif /* USB_DEBUG */ 111 112 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ohcidebug,FMT,A,B,C,D) 113 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ohcidebug,N,FMT,A,B,C,D) 114 #define OHCIHIST_FUNC() USBHIST_FUNC() 115 #define OHCIHIST_CALLED(name) USBHIST_CALLED(ohcidebug) 116 117 #if BYTE_ORDER == BIG_ENDIAN 118 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 119 #else 120 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 121 #endif 122 123 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 124 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 125 #define HTOO16(val) O16TOH(val) 126 #define HTOO32(val) O32TOH(val) 127 128 struct ohci_pipe; 129 130 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 131 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 132 133 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 134 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 135 Static void ohci_free_std_locked(ohci_softc_t *, ohci_soft_td_t *); 136 137 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 138 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 139 Static void ohci_free_sitd_locked(ohci_softc_t *, 140 ohci_soft_itd_t *); 141 142 Static int ohci_alloc_std_chain(ohci_softc_t *, struct usbd_xfer *, 143 int, int); 144 Static void ohci_free_stds(ohci_softc_t *, struct ohci_xfer *); 145 146 Static void ohci_reset_std_chain(ohci_softc_t *, struct usbd_xfer *, 147 int, int, ohci_soft_td_t *, ohci_soft_td_t **); 148 149 Static usbd_status ohci_open(struct usbd_pipe *); 150 Static void ohci_poll(struct usbd_bus *); 151 Static void ohci_softintr(void *); 152 Static void ohci_rhsc(ohci_softc_t *, struct usbd_xfer *); 153 Static void ohci_rhsc_softint(void *); 154 155 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 156 ohci_soft_ed_t *); 157 158 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 159 ohci_soft_ed_t *); 160 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 161 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 162 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 163 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 164 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 165 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 166 167 Static usbd_status ohci_setup_isoc(struct usbd_pipe *); 168 Static void ohci_device_isoc_enter(struct usbd_xfer *); 169 170 Static struct usbd_xfer * 171 ohci_allocx(struct usbd_bus *, unsigned int); 172 Static void ohci_freex(struct usbd_bus *, struct usbd_xfer *); 173 Static bool ohci_dying(struct usbd_bus *); 174 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 175 Static int ohci_roothub_ctrl(struct usbd_bus *, 176 usb_device_request_t *, void *, int); 177 178 Static usbd_status ohci_root_intr_transfer(struct usbd_xfer *); 179 Static usbd_status ohci_root_intr_start(struct usbd_xfer *); 180 Static void ohci_root_intr_abort(struct usbd_xfer *); 181 Static void ohci_root_intr_close(struct usbd_pipe *); 182 Static void ohci_root_intr_done(struct usbd_xfer *); 183 184 Static int ohci_device_ctrl_init(struct usbd_xfer *); 185 Static void ohci_device_ctrl_fini(struct usbd_xfer *); 186 Static usbd_status ohci_device_ctrl_transfer(struct usbd_xfer *); 187 Static usbd_status ohci_device_ctrl_start(struct usbd_xfer *); 188 Static void ohci_device_ctrl_abort(struct usbd_xfer *); 189 Static void ohci_device_ctrl_close(struct usbd_pipe *); 190 Static void ohci_device_ctrl_done(struct usbd_xfer *); 191 192 Static int ohci_device_bulk_init(struct usbd_xfer *); 193 Static void ohci_device_bulk_fini(struct usbd_xfer *); 194 Static usbd_status ohci_device_bulk_transfer(struct usbd_xfer *); 195 Static usbd_status ohci_device_bulk_start(struct usbd_xfer *); 196 Static void ohci_device_bulk_abort(struct usbd_xfer *); 197 Static void ohci_device_bulk_close(struct usbd_pipe *); 198 Static void ohci_device_bulk_done(struct usbd_xfer *); 199 200 Static int ohci_device_intr_init(struct usbd_xfer *); 201 Static void ohci_device_intr_fini(struct usbd_xfer *); 202 Static usbd_status ohci_device_intr_transfer(struct usbd_xfer *); 203 Static usbd_status ohci_device_intr_start(struct usbd_xfer *); 204 Static void ohci_device_intr_abort(struct usbd_xfer *); 205 Static void ohci_device_intr_close(struct usbd_pipe *); 206 Static void ohci_device_intr_done(struct usbd_xfer *); 207 208 Static int ohci_device_isoc_init(struct usbd_xfer *); 209 Static void ohci_device_isoc_fini(struct usbd_xfer *); 210 Static usbd_status ohci_device_isoc_transfer(struct usbd_xfer *); 211 Static void ohci_device_isoc_abort(struct usbd_xfer *); 212 Static void ohci_device_isoc_close(struct usbd_pipe *); 213 Static void ohci_device_isoc_done(struct usbd_xfer *); 214 215 Static usbd_status ohci_device_setintr(ohci_softc_t *, 216 struct ohci_pipe *, int); 217 218 Static void ohci_rhsc_enable(void *); 219 220 Static void ohci_close_pipe(struct usbd_pipe *, ohci_soft_ed_t *); 221 Static void ohci_abortx(struct usbd_xfer *); 222 223 Static void ohci_device_clear_toggle(struct usbd_pipe *); 224 Static void ohci_noop(struct usbd_pipe *); 225 226 #ifdef OHCI_DEBUG 227 Static void ohci_dumpregs(ohci_softc_t *); 228 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 229 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 230 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 231 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 232 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 233 #endif 234 235 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 236 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 237 #define OWRITE1(sc, r, x) \ 238 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 239 #define OWRITE2(sc, r, x) \ 240 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 241 #define OWRITE4(sc, r, x) \ 242 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 243 244 static __inline uint32_t 245 OREAD4(ohci_softc_t *sc, bus_size_t r) 246 { 247 248 OBARR(sc); 249 return bus_space_read_4(sc->iot, sc->ioh, r); 250 } 251 252 /* Reverse the bits in a value 0 .. 31 */ 253 Static uint8_t revbits[OHCI_NO_INTRS] = 254 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 255 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 256 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 257 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 258 259 struct ohci_pipe { 260 struct usbd_pipe pipe; 261 ohci_soft_ed_t *sed; 262 union { 263 ohci_soft_td_t *td; 264 ohci_soft_itd_t *itd; 265 } tail; 266 /* Info needed for different pipe kinds. */ 267 union { 268 /* Control pipe */ 269 struct { 270 usb_dma_t reqdma; 271 } ctrl; 272 /* Interrupt pipe */ 273 struct { 274 int nslots; 275 int pos; 276 } intr; 277 /* Isochronous pipe */ 278 struct isoc { 279 int next, inuse; 280 } isoc; 281 }; 282 }; 283 284 Static const struct usbd_bus_methods ohci_bus_methods = { 285 .ubm_open = ohci_open, 286 .ubm_softint = ohci_softintr, 287 .ubm_dopoll = ohci_poll, 288 .ubm_allocx = ohci_allocx, 289 .ubm_freex = ohci_freex, 290 .ubm_abortx = ohci_abortx, 291 .ubm_dying = ohci_dying, 292 .ubm_getlock = ohci_get_lock, 293 .ubm_rhctrl = ohci_roothub_ctrl, 294 }; 295 296 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 297 .upm_transfer = ohci_root_intr_transfer, 298 .upm_start = ohci_root_intr_start, 299 .upm_abort = ohci_root_intr_abort, 300 .upm_close = ohci_root_intr_close, 301 .upm_cleartoggle = ohci_noop, 302 .upm_done = ohci_root_intr_done, 303 }; 304 305 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 306 .upm_init = ohci_device_ctrl_init, 307 .upm_fini = ohci_device_ctrl_fini, 308 .upm_transfer = ohci_device_ctrl_transfer, 309 .upm_start = ohci_device_ctrl_start, 310 .upm_abort = ohci_device_ctrl_abort, 311 .upm_close = ohci_device_ctrl_close, 312 .upm_cleartoggle = ohci_noop, 313 .upm_done = ohci_device_ctrl_done, 314 }; 315 316 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 317 .upm_init = ohci_device_intr_init, 318 .upm_fini = ohci_device_intr_fini, 319 .upm_transfer = ohci_device_intr_transfer, 320 .upm_start = ohci_device_intr_start, 321 .upm_abort = ohci_device_intr_abort, 322 .upm_close = ohci_device_intr_close, 323 .upm_cleartoggle = ohci_device_clear_toggle, 324 .upm_done = ohci_device_intr_done, 325 }; 326 327 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 328 .upm_init = ohci_device_bulk_init, 329 .upm_fini = ohci_device_bulk_fini, 330 .upm_transfer = ohci_device_bulk_transfer, 331 .upm_start = ohci_device_bulk_start, 332 .upm_abort = ohci_device_bulk_abort, 333 .upm_close = ohci_device_bulk_close, 334 .upm_cleartoggle = ohci_device_clear_toggle, 335 .upm_done = ohci_device_bulk_done, 336 }; 337 338 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 339 .upm_init = ohci_device_isoc_init, 340 .upm_fini = ohci_device_isoc_fini, 341 .upm_transfer = ohci_device_isoc_transfer, 342 .upm_abort = ohci_device_isoc_abort, 343 .upm_close = ohci_device_isoc_close, 344 .upm_cleartoggle = ohci_noop, 345 .upm_done = ohci_device_isoc_done, 346 }; 347 348 int 349 ohci_activate(device_t self, enum devact act) 350 { 351 struct ohci_softc *sc = device_private(self); 352 353 switch (act) { 354 case DVACT_DEACTIVATE: 355 sc->sc_dying = 1; 356 return 0; 357 default: 358 return EOPNOTSUPP; 359 } 360 } 361 362 void 363 ohci_childdet(device_t self, device_t child) 364 { 365 struct ohci_softc *sc = device_private(self); 366 367 KASSERT(sc->sc_child == child); 368 sc->sc_child = NULL; 369 } 370 371 int 372 ohci_detach(struct ohci_softc *sc, int flags) 373 { 374 int rv = 0; 375 376 if (sc->sc_child != NULL) 377 rv = config_detach(sc->sc_child, flags); 378 379 if (rv != 0) 380 return rv; 381 382 softint_disestablish(sc->sc_rhsc_si); 383 384 callout_halt(&sc->sc_tmo_rhsc, NULL); 385 callout_destroy(&sc->sc_tmo_rhsc); 386 387 mutex_destroy(&sc->sc_lock); 388 mutex_destroy(&sc->sc_intr_lock); 389 390 if (sc->sc_hcca != NULL) 391 usb_freemem(&sc->sc_hccadma); 392 pool_cache_destroy(sc->sc_xferpool); 393 cv_destroy(&sc->sc_abort_cv); 394 395 return rv; 396 } 397 398 ohci_soft_ed_t * 399 ohci_alloc_sed(ohci_softc_t *sc) 400 { 401 ohci_soft_ed_t *sed; 402 int i, offs; 403 usb_dma_t dma; 404 405 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 406 407 mutex_enter(&sc->sc_lock); 408 if (sc->sc_freeeds == NULL) { 409 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 410 mutex_exit(&sc->sc_lock); 411 412 int err = usb_allocmem(sc->sc_bus.ub_dmatag, OHCI_SED_SIZE * OHCI_SED_CHUNK, 413 OHCI_ED_ALIGN, 0 /*!USBMALLOC_COHERENT*/, &dma); 414 if (err) 415 return NULL; 416 417 mutex_enter(&sc->sc_lock); 418 for (i = 0; i < OHCI_SED_CHUNK; i++) { 419 offs = i * OHCI_SED_SIZE; 420 sed = KERNADDR(&dma, offs); 421 sed->physaddr = DMAADDR(&dma, offs); 422 sed->dma = dma; 423 sed->offs = offs; 424 sed->next = sc->sc_freeeds; 425 sc->sc_freeeds = sed; 426 } 427 } 428 sed = sc->sc_freeeds; 429 sc->sc_freeeds = sed->next; 430 mutex_exit(&sc->sc_lock); 431 432 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 433 sed->next = 0; 434 return sed; 435 } 436 437 static inline void 438 ohci_free_sed_locked(ohci_softc_t *sc, ohci_soft_ed_t *sed) 439 { 440 441 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 442 443 sed->next = sc->sc_freeeds; 444 sc->sc_freeeds = sed; 445 } 446 447 void 448 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 449 { 450 451 mutex_enter(&sc->sc_lock); 452 ohci_free_sed_locked(sc, sed); 453 mutex_exit(&sc->sc_lock); 454 } 455 456 ohci_soft_td_t * 457 ohci_alloc_std(ohci_softc_t *sc) 458 { 459 ohci_soft_td_t *std; 460 int i, offs; 461 usb_dma_t dma; 462 463 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 464 465 mutex_enter(&sc->sc_lock); 466 if (sc->sc_freetds == NULL) { 467 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 468 mutex_exit(&sc->sc_lock); 469 470 int err = usb_allocmem(sc->sc_bus.ub_dmatag, OHCI_STD_SIZE * OHCI_STD_CHUNK, 471 OHCI_TD_ALIGN, USBMALLOC_COHERENT, &dma); 472 if (err) 473 return NULL; 474 475 mutex_enter(&sc->sc_lock); 476 for (i = 0; i < OHCI_STD_CHUNK; i++) { 477 offs = i * OHCI_STD_SIZE; 478 std = KERNADDR(&dma, offs); 479 std->physaddr = DMAADDR(&dma, offs); 480 std->dma = dma; 481 std->offs = offs; 482 std->nexttd = sc->sc_freetds; 483 sc->sc_freetds = std; 484 } 485 } 486 487 std = sc->sc_freetds; 488 sc->sc_freetds = std->nexttd; 489 mutex_exit(&sc->sc_lock); 490 491 memset(&std->td, 0, sizeof(ohci_td_t)); 492 std->nexttd = NULL; 493 std->xfer = NULL; 494 std->held = NULL; 495 496 return std; 497 } 498 499 void 500 ohci_free_std_locked(ohci_softc_t *sc, ohci_soft_td_t *std) 501 { 502 503 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 504 505 std->nexttd = sc->sc_freetds; 506 sc->sc_freetds = std; 507 } 508 509 void 510 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 511 { 512 513 mutex_enter(&sc->sc_lock); 514 ohci_free_std_locked(sc, std); 515 mutex_exit(&sc->sc_lock); 516 } 517 518 Static int 519 ohci_alloc_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, int length, int rd) 520 { 521 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 522 uint16_t flags = xfer->ux_flags; 523 524 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 525 526 DPRINTFN(8, "addr=%jd endpt=%jd len=%jd speed=%jd", 527 xfer->ux_pipe->up_dev->ud_addr, 528 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 529 length, xfer->ux_pipe->up_dev->ud_speed); 530 531 ASSERT_SLEEPABLE(); 532 KASSERT(length != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 533 534 size_t nstd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 535 nstd += howmany(length, OHCI_PAGE_SIZE); 536 ox->ox_stds = kmem_zalloc(sizeof(ohci_soft_td_t *) * nstd, 537 KM_SLEEP); 538 ox->ox_nstd = nstd; 539 540 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, nstd, 0, 0); 541 542 for (size_t j = 0; j < ox->ox_nstd; j++) { 543 ohci_soft_td_t *cur = ohci_alloc_std(sc); 544 if (cur == NULL) 545 goto nomem; 546 547 ox->ox_stds[j] = cur; 548 cur->held = &ox->ox_stds[j]; 549 cur->xfer = xfer; 550 cur->flags = 0; 551 DPRINTFN(10, "xfer=%#jx new std=%#jx held at %#jx", (uintptr_t)ox, 552 (uintptr_t)cur, (uintptr_t)cur->held, 0); 553 } 554 555 return 0; 556 557 nomem: 558 ohci_free_stds(sc, ox); 559 kmem_free(ox->ox_stds, sizeof(ohci_soft_td_t *) * nstd); 560 561 return ENOMEM; 562 } 563 564 Static void 565 ohci_free_stds(ohci_softc_t *sc, struct ohci_xfer *ox) 566 { 567 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 568 DPRINTF("ox=%#jx", (uintptr_t)ox, 0, 0, 0); 569 570 mutex_enter(&sc->sc_lock); 571 for (size_t i = 0; i < ox->ox_nstd; i++) { 572 ohci_soft_td_t *std = ox->ox_stds[i]; 573 if (std == NULL) 574 break; 575 ohci_free_std_locked(sc, std); 576 } 577 mutex_exit(&sc->sc_lock); 578 } 579 580 void 581 ohci_reset_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, 582 int alen, int rd, ohci_soft_td_t *sp, ohci_soft_td_t **ep) 583 { 584 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 585 ohci_soft_td_t *next, *cur; 586 int len, curlen; 587 usb_dma_t *dma = &xfer->ux_dmabuf; 588 uint16_t flags = xfer->ux_flags; 589 590 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 591 DPRINTF("start len=%jd", alen, 0, 0, 0); 592 593 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 594 595 DPRINTFN(8, "addr=%jd endpt=%jd len=%jd speed=%jd", 596 xfer->ux_pipe->up_dev->ud_addr, 597 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 598 alen, xfer->ux_pipe->up_dev->ud_speed); 599 600 KASSERT(sp); 601 602 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 603 604 /* 605 * Assign next for the len == 0 case where we don't go through the 606 * main loop. 607 */ 608 len = alen; 609 cur = next = sp; 610 611 usb_syncmem(dma, 0, len, 612 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 613 const uint32_t tdflags = HTOO32( 614 OHCI_TD_SET_DP(rd ? OHCI_TD_DP_IN : OHCI_TD_DP_OUT) | 615 OHCI_TD_SET_CC(OHCI_TD_NOCC) | 616 OHCI_TD_SET_TOGGLE(OHCI_TD_TOGGLE_CARRY) | 617 OHCI_TD_SET_DI(OHCI_TD_NOINTR) 618 ); 619 620 size_t curoffs = 0; 621 for (size_t j = 1; len != 0;) { 622 if (j == ox->ox_nstd) 623 next = NULL; 624 else 625 next = ox->ox_stds[j++]; 626 KASSERT(next != cur); 627 628 curlen = len; 629 /* 630 * The OHCI hardware can handle at most one page crossing per 631 * TD. That is, 2 * OHCI_PAGE_SIZE as a maximum. Limit the 632 * length in this TD accordingly. 633 */ 634 const ohci_physaddr_t sdataphys = DMAADDR(dma, curoffs); 635 636 int maxlen = (2 * OHCI_PAGE_SIZE) - OHCI_PAGE_OFFSET(sdataphys); 637 if (curlen > maxlen) { 638 curlen = maxlen; 639 640 /* 641 * the length must be a multiple of 642 * the max size 643 */ 644 curlen -= curlen % mps; 645 } 646 647 const int edataoffs = curoffs + curlen - 1; 648 const ohci_physaddr_t edataphys = DMAADDR(dma, edataoffs); 649 650 KASSERT(curlen != 0); 651 DPRINTFN(4, "sdataphys=0x%08jx edataphys=0x%08jx " 652 "len=%jd curlen=%jd", sdataphys, edataphys, len, curlen); 653 654 cur->td.td_flags = tdflags; 655 cur->td.td_cbp = HTOO32(sdataphys); 656 cur->td.td_be = HTOO32(edataphys); 657 cur->td.td_nexttd = (next != NULL) ? HTOO32(next->physaddr) : 0; 658 cur->nexttd = next; 659 cur->len = curlen; 660 cur->flags = OHCI_ADD_LEN; 661 cur->xfer = xfer; 662 ohci_hash_add_td(sc, cur); 663 664 curoffs += curlen; 665 len -= curlen; 666 667 if (len != 0) { 668 KASSERT(next != NULL); 669 DPRINTFN(10, "extend chain", 0, 0, 0, 0); 670 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 671 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 672 673 cur = next; 674 } 675 } 676 cur->td.td_flags |= 677 HTOO32(xfer->ux_flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0); 678 679 if (!rd && 680 (flags & USBD_FORCE_SHORT_XFER) && 681 alen % mps == 0) { 682 /* We're adding a ZLP so sync the previous TD */ 683 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 684 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 685 686 /* Force a 0 length transfer at the end. */ 687 688 KASSERT(next != NULL); 689 cur = next; 690 691 cur->td.td_flags = tdflags; 692 cur->td.td_cbp = 0; /* indicate 0 length packet */ 693 cur->td.td_nexttd = 0; 694 cur->td.td_be = ~0; 695 cur->nexttd = NULL; 696 cur->len = 0; 697 cur->flags = 0; 698 cur->xfer = xfer; 699 ohci_hash_add_td(sc, cur); 700 701 DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0); 702 } 703 704 /* Last TD gets usb_syncmem'ed by caller */ 705 *ep = cur; 706 } 707 708 ohci_soft_itd_t * 709 ohci_alloc_sitd(ohci_softc_t *sc) 710 { 711 ohci_soft_itd_t *sitd; 712 int i, offs; 713 usb_dma_t dma; 714 715 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 716 717 mutex_enter(&sc->sc_lock); 718 if (sc->sc_freeitds == NULL) { 719 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 720 mutex_exit(&sc->sc_lock); 721 722 int err = usb_allocmem(sc->sc_bus.ub_dmatag, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 723 OHCI_ITD_ALIGN, USBMALLOC_COHERENT, &dma); 724 if (err) 725 return NULL; 726 mutex_enter(&sc->sc_lock); 727 for (i = 0; i < OHCI_SITD_CHUNK; i++) { 728 offs = i * OHCI_SITD_SIZE; 729 sitd = KERNADDR(&dma, offs); 730 sitd->physaddr = DMAADDR(&dma, offs); 731 sitd->dma = dma; 732 sitd->offs = offs; 733 sitd->nextitd = sc->sc_freeitds; 734 sc->sc_freeitds = sitd; 735 } 736 } 737 738 sitd = sc->sc_freeitds; 739 sc->sc_freeitds = sitd->nextitd; 740 mutex_exit(&sc->sc_lock); 741 742 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 743 sitd->nextitd = NULL; 744 sitd->xfer = NULL; 745 746 #ifdef DIAGNOSTIC 747 sitd->isdone = true; 748 #endif 749 750 return sitd; 751 } 752 753 Static void 754 ohci_free_sitd_locked(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 755 { 756 757 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 758 DPRINTFN(10, "sitd=%#jx", (uintptr_t)sitd, 0, 0, 0); 759 760 KASSERT(sitd->isdone); 761 #ifdef DIAGNOSTIC 762 /* Warn double free */ 763 sitd->isdone = false; 764 #endif 765 766 sitd->nextitd = sc->sc_freeitds; 767 sc->sc_freeitds = sitd; 768 } 769 770 void 771 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 772 { 773 774 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 775 776 mutex_enter(&sc->sc_lock); 777 ohci_free_sitd_locked(sc, sitd); 778 mutex_exit(&sc->sc_lock); 779 } 780 781 int 782 ohci_init(ohci_softc_t *sc) 783 { 784 ohci_soft_ed_t *sed, *psed; 785 usbd_status err; 786 int i; 787 uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */; 788 789 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 790 791 aprint_normal_dev(sc->sc_dev, ""); 792 793 sc->sc_hcca = NULL; 794 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 795 796 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 797 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 798 799 sc->sc_rhsc_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 800 ohci_rhsc_softint, sc); 801 802 for (i = 0; i < OHCI_HASH_SIZE; i++) 803 LIST_INIT(&sc->sc_hash_tds[i]); 804 for (i = 0; i < OHCI_HASH_SIZE; i++) 805 LIST_INIT(&sc->sc_hash_itds[i]); 806 807 TAILQ_INIT(&sc->sc_abortingxfers); 808 cv_init(&sc->sc_abort_cv, "ohciabt"); 809 810 sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0, 811 "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL); 812 813 rev = OREAD4(sc, OHCI_REVISION); 814 aprint_normal("OHCI version %" __PRIuBITS ".%" __PRIuBITS "%s\n", 815 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 816 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 817 818 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 819 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 820 sc->sc_bus.ub_revision = USBREV_UNKNOWN; 821 return -1; 822 } 823 sc->sc_bus.ub_revision = USBREV_1_0; 824 sc->sc_bus.ub_usedma = true; 825 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 826 827 /* XXX determine alignment by R/W */ 828 /* Allocate the HCCA area. */ 829 err = usb_allocmem(sc->sc_bus.ub_dmatag, OHCI_HCCA_SIZE, OHCI_HCCA_ALIGN, 830 USBMALLOC_COHERENT, &sc->sc_hccadma); 831 if (err) { 832 sc->sc_hcca = NULL; 833 return err; 834 } 835 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 836 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 837 838 sc->sc_eintrs = OHCI_NORMAL_INTRS; 839 840 /* Allocate dummy ED that starts the control list. */ 841 sc->sc_ctrl_head = ohci_alloc_sed(sc); 842 if (sc->sc_ctrl_head == NULL) { 843 err = ENOMEM; 844 goto bad1; 845 } 846 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 847 848 /* Allocate dummy ED that starts the bulk list. */ 849 sc->sc_bulk_head = ohci_alloc_sed(sc); 850 if (sc->sc_bulk_head == NULL) { 851 err = ENOMEM; 852 goto bad2; 853 } 854 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 855 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 856 sizeof(sc->sc_bulk_head->ed), 857 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 858 859 /* Allocate dummy ED that starts the isochronous list. */ 860 sc->sc_isoc_head = ohci_alloc_sed(sc); 861 if (sc->sc_isoc_head == NULL) { 862 err = ENOMEM; 863 goto bad3; 864 } 865 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 866 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 867 sizeof(sc->sc_isoc_head->ed), 868 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 869 870 /* Allocate all the dummy EDs that make up the interrupt tree. */ 871 for (i = 0; i < OHCI_NO_EDS; i++) { 872 sed = ohci_alloc_sed(sc); 873 if (sed == NULL) { 874 while (--i >= 0) 875 ohci_free_sed(sc, sc->sc_eds[i]); 876 err = ENOMEM; 877 goto bad4; 878 } 879 /* All ED fields are set to 0. */ 880 sc->sc_eds[i] = sed; 881 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 882 if (i != 0) 883 psed = sc->sc_eds[(i-1) / 2]; 884 else 885 psed= sc->sc_isoc_head; 886 sed->next = psed; 887 sed->ed.ed_nexted = HTOO32(psed->physaddr); 888 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 889 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 890 } 891 /* 892 * Fill HCCA interrupt table. The bit reversal is to get 893 * the tree set up properly to spread the interrupts. 894 */ 895 for (i = 0; i < OHCI_NO_INTRS; i++) 896 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 897 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 898 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 899 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 900 901 #ifdef OHCI_DEBUG 902 DPRINTFN(15, "--- dump start ---", 0, 0, 0 ,0); 903 if (ohcidebug >= 15) { 904 for (i = 0; i < OHCI_NO_EDS; i++) { 905 DPRINTFN(15, "ed#%jd ", i, 0, 0, 0); 906 ohci_dump_ed(sc, sc->sc_eds[i]); 907 } 908 DPRINTFN(15, "iso", 0, 0, 0 ,0); 909 ohci_dump_ed(sc, sc->sc_isoc_head); 910 } 911 DPRINTFN(15, "--- dump end ---", 0, 0, 0 ,0); 912 #endif 913 914 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 915 ctl = OREAD4(sc, OHCI_CONTROL); 916 rwc = ctl & OHCI_RWC; 917 fm = OREAD4(sc, OHCI_FM_INTERVAL); 918 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 919 /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */ 920 921 /* Determine in what context we are running. */ 922 if (ctl & OHCI_IR) { 923 /* SMM active, request change */ 924 DPRINTF("SMM active, request owner change", 0, 0, 0, 0); 925 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 926 (OHCI_OC | OHCI_MIE)) 927 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 928 s = OREAD4(sc, OHCI_COMMAND_STATUS); 929 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 930 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 931 usb_delay_ms(&sc->sc_bus, 1); 932 ctl = OREAD4(sc, OHCI_CONTROL); 933 } 934 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 935 if ((ctl & OHCI_IR) == 0) { 936 aprint_error_dev(sc->sc_dev, 937 "SMM does not respond, resetting\n"); 938 OWRITE4(sc, OHCI_CONTROL, 939 OHCI_SET_HCFS(OHCI_HCFS_RESET) | rwc); 940 goto reset; 941 } 942 #if 0 943 /* 944 * Don't bother trying to reuse the BIOS init, we'll reset it 945 * anyway. 946 */ 947 } else if (OHCI_GET_HCFS(ctl) != OHCI_HCFS_RESET) { 948 /* BIOS started controller. */ 949 DPRINTF("BIOS active", 0, 0, 0, 0); 950 if (OHCI_GET_HCFS(ctl) != OHCI_HCFS_OPERATIONAL) { 951 OWRITE4(sc, OHCI_CONTROL, 952 OHCI_SET_HCFS(OHCI_HCFS_OPERATIONAL) | rwc); 953 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 954 } 955 #endif 956 } else { 957 DPRINTF("cold started", 0 ,0 ,0 ,0); 958 reset: 959 /* Controller was cold started. */ 960 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 961 } 962 963 /* 964 * This reset should not be necessary according to the OHCI spec, but 965 * without it some controllers do not start. 966 */ 967 DPRINTF("sc %#jx: resetting", (uintptr_t)sc, 0, 0, 0); 968 OWRITE4(sc, OHCI_CONTROL, OHCI_SET_HCFS(OHCI_HCFS_RESET) | rwc); 969 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 970 971 /* We now own the host controller and the bus has been reset. */ 972 973 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 974 /* Nominal time for a reset is 10 us. */ 975 for (i = 0; i < 10; i++) { 976 delay(10); 977 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 978 if (!hcr) 979 break; 980 } 981 if (hcr) { 982 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 983 err = EIO; 984 goto bad5; 985 } 986 #ifdef OHCI_DEBUG 987 if (ohcidebug >= 15) 988 ohci_dumpregs(sc); 989 #endif 990 991 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 992 993 /* Set up HC registers. */ 994 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 995 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 996 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 997 /* disable all interrupts and then switch on all desired interrupts */ 998 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 999 /* switch on desired functional features */ 1000 ctl = OREAD4(sc, OHCI_CONTROL); 1001 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 1002 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 1003 OHCI_CBSR_SET(OHCI_RATIO_1_4) | 1004 OHCI_SET_HCFS(OHCI_HCFS_OPERATIONAL) | rwc; 1005 /* And finally start it! */ 1006 OWRITE4(sc, OHCI_CONTROL, ctl); 1007 1008 /* 1009 * The controller is now OPERATIONAL. Set a some final 1010 * registers that should be set earlier, but that the 1011 * controller ignores when in the SUSPEND state. 1012 */ 1013 ival = OHCI_FM_GET_IVAL(fm); 1014 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FM_FIT) ^ OHCI_FM_FIT; 1015 fm |= OHCI_FSMPS(ival) | ival; 1016 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 1017 per = OHCI_PERIODIC(ival); /* 90% periodic */ 1018 OWRITE4(sc, OHCI_PERIODIC_START, per); 1019 1020 if (sc->sc_flags & OHCIF_SUPERIO) { 1021 /* no overcurrent protection */ 1022 desca |= OHCI_RHD_NOCP; 1023 /* 1024 * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning 1025 * that 1026 * - ports are always power switched 1027 * - don't wait for powered root hub port 1028 */ 1029 desca &= ~(OHCI_RHD_POTPGT_MASK | OHCI_RHD_NPS); 1030 } 1031 1032 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 1033 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_RHD_NOCP); 1034 OWRITE4(sc, OHCI_RH_STATUS, OHCI_RHS_LPSC); /* Enable port power */ 1035 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 1036 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 1037 1038 /* 1039 * The AMD756 requires a delay before re-reading the register, 1040 * otherwise it will occasionally report 0 ports. 1041 */ 1042 sc->sc_noport = 0; 1043 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 1044 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 1045 sc->sc_noport = 1046 OHCI_RHD_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 1047 } 1048 1049 #ifdef OHCI_DEBUG 1050 if (ohcidebug >= 5) 1051 ohci_dumpregs(sc); 1052 #endif 1053 1054 /* Set up the bus struct. */ 1055 sc->sc_bus.ub_methods = &ohci_bus_methods; 1056 sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe); 1057 1058 sc->sc_control = sc->sc_intre = 0; 1059 1060 /* Finally, turn on interrupts. */ 1061 DPRINTF("enabling %#jx", sc->sc_eintrs | OHCI_MIE, 0, 0, 0); 1062 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 1063 1064 return 0; 1065 1066 bad5: 1067 for (i = 0; i < OHCI_NO_EDS; i++) 1068 ohci_free_sed(sc, sc->sc_eds[i]); 1069 bad4: 1070 ohci_free_sed(sc, sc->sc_isoc_head); 1071 bad3: 1072 ohci_free_sed(sc, sc->sc_bulk_head); 1073 bad2: 1074 ohci_free_sed(sc, sc->sc_ctrl_head); 1075 bad1: 1076 usb_freemem(&sc->sc_hccadma); 1077 sc->sc_hcca = NULL; 1078 return err; 1079 } 1080 1081 struct usbd_xfer * 1082 ohci_allocx(struct usbd_bus *bus, unsigned int nframes) 1083 { 1084 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1085 struct usbd_xfer *xfer; 1086 1087 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 1088 if (xfer != NULL) { 1089 memset(xfer, 0, sizeof(struct ohci_xfer)); 1090 1091 #ifdef DIAGNOSTIC 1092 xfer->ux_state = XFER_BUSY; 1093 #endif 1094 } 1095 return xfer; 1096 } 1097 1098 void 1099 ohci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1100 { 1101 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1102 1103 KASSERTMSG(xfer->ux_state == XFER_BUSY || 1104 xfer->ux_status == USBD_NOT_STARTED, 1105 "xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state); 1106 #ifdef DIAGNOSTIC 1107 xfer->ux_state = XFER_FREE; 1108 #endif 1109 pool_cache_put(sc->sc_xferpool, xfer); 1110 } 1111 1112 Static bool 1113 ohci_dying(struct usbd_bus *bus) 1114 { 1115 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1116 1117 return sc->sc_dying; 1118 } 1119 1120 Static void 1121 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1122 { 1123 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1124 1125 *lock = &sc->sc_lock; 1126 } 1127 1128 /* 1129 * Shut down the controller when the system is going down. 1130 */ 1131 bool 1132 ohci_shutdown(device_t self, int flags) 1133 { 1134 ohci_softc_t *sc = device_private(self); 1135 1136 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1137 1138 DPRINTF("stopping the HC", 0, 0, 0, 0); 1139 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 1140 OWRITE4(sc, OHCI_CONTROL, OHCI_SET_HCFS(OHCI_HCFS_RESET)); 1141 return true; 1142 } 1143 1144 bool 1145 ohci_resume(device_t dv, const pmf_qual_t *qual) 1146 { 1147 ohci_softc_t *sc = device_private(dv); 1148 uint32_t ctl; 1149 1150 /* Some broken BIOSes do not recover these values */ 1151 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1152 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1153 sc->sc_ctrl_head->physaddr); 1154 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1155 sc->sc_bulk_head->physaddr); 1156 if (sc->sc_intre) 1157 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1158 (OHCI_ALL_INTRS | OHCI_MIE)); 1159 if (sc->sc_control) 1160 ctl = sc->sc_control; 1161 else 1162 ctl = OREAD4(sc, OHCI_CONTROL); 1163 ctl |= OHCI_SET_HCFS(OHCI_HCFS_RESUME); 1164 OWRITE4(sc, OHCI_CONTROL, ctl); 1165 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1166 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_SET_HCFS(OHCI_HCFS_OPERATIONAL); 1167 OWRITE4(sc, OHCI_CONTROL, ctl); 1168 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1169 sc->sc_control = sc->sc_intre = 0; 1170 1171 return true; 1172 } 1173 1174 bool 1175 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1176 { 1177 ohci_softc_t *sc = device_private(dv); 1178 uint32_t ctl; 1179 1180 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1181 if (sc->sc_control == 0) { 1182 /* 1183 * Preserve register values, in case that BIOS 1184 * does not recover them. 1185 */ 1186 sc->sc_control = ctl; 1187 sc->sc_intre = OREAD4(sc, 1188 OHCI_INTERRUPT_ENABLE); 1189 } 1190 ctl |= OHCI_SET_HCFS(OHCI_HCFS_SUSPEND); 1191 OWRITE4(sc, OHCI_CONTROL, ctl); 1192 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1193 1194 return true; 1195 } 1196 1197 #ifdef OHCI_DEBUG 1198 void 1199 ohci_dumpregs(ohci_softc_t *sc) 1200 { 1201 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1202 1203 DPRINTF("rev=0x%08jx control=0x%08jx command=0x%08jx", 1204 OREAD4(sc, OHCI_REVISION), 1205 OREAD4(sc, OHCI_CONTROL), 1206 OREAD4(sc, OHCI_COMMAND_STATUS), 0); 1207 DPRINTF(" intrstat=0x%08jx intre=0x%08jx intrd=0x%08jx", 1208 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1209 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1210 OREAD4(sc, OHCI_INTERRUPT_DISABLE), 0); 1211 DPRINTF(" hcca=0x%08jx percur=0x%08jx ctrlhd=0x%08jx", 1212 OREAD4(sc, OHCI_HCCA), 1213 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1214 OREAD4(sc, OHCI_CONTROL_HEAD_ED), 0); 1215 DPRINTF(" ctrlcur=0x%08jx bulkhd=0x%08jx bulkcur=0x%08jx", 1216 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1217 OREAD4(sc, OHCI_BULK_HEAD_ED), 1218 OREAD4(sc, OHCI_BULK_CURRENT_ED) ,0); 1219 DPRINTF(" done=0x%08jx fmival=0x%08jx fmrem=0x%08jx", 1220 OREAD4(sc, OHCI_DONE_HEAD), 1221 OREAD4(sc, OHCI_FM_INTERVAL), 1222 OREAD4(sc, OHCI_FM_REMAINING), 0); 1223 DPRINTF(" fmnum=0x%08jx perst=0x%08jx lsthrs=0x%08jx", 1224 OREAD4(sc, OHCI_FM_NUMBER), 1225 OREAD4(sc, OHCI_PERIODIC_START), 1226 OREAD4(sc, OHCI_LS_THRESHOLD), 0); 1227 DPRINTF(" desca=0x%08jx descb=0x%08jx stat=0x%08jx", 1228 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1229 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1230 OREAD4(sc, OHCI_RH_STATUS), 0); 1231 DPRINTF(" port1=0x%08jx port2=0x%08jx", 1232 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1233 OREAD4(sc, OHCI_RH_PORT_STATUS(2)), 0, 0); 1234 usb_syncmem(&sc->sc_hccadma, 1235 offsetof(struct ohci_hcca, hcca_frame_number), 1236 sizeof(sc->sc_hcca->hcca_frame_number) + 1237 sizeof(sc->sc_hcca->hcca_done_head), 1238 BUS_DMASYNC_POSTREAD); 1239 DPRINTF(" HCCA: frame_number=0x%04jx done_head=0x%08jx", 1240 O32TOH(sc->sc_hcca->hcca_frame_number), 1241 O32TOH(sc->sc_hcca->hcca_done_head), 0, 0); 1242 } 1243 #endif 1244 1245 Static int ohci_intr1(ohci_softc_t *); 1246 1247 int 1248 ohci_intr(void *p) 1249 { 1250 ohci_softc_t *sc = p; 1251 int ret = 0; 1252 1253 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1254 1255 if (sc == NULL) 1256 return 0; 1257 1258 mutex_spin_enter(&sc->sc_intr_lock); 1259 1260 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1261 goto done; 1262 1263 /* If we get an interrupt while polling, then just ignore it. */ 1264 if (sc->sc_bus.ub_usepolling) { 1265 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1266 /* for level triggered intrs, should do something to ack */ 1267 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1268 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1269 1270 goto done; 1271 } 1272 1273 ret = ohci_intr1(sc); 1274 1275 done: 1276 mutex_spin_exit(&sc->sc_intr_lock); 1277 return ret; 1278 } 1279 1280 Static int 1281 ohci_intr1(ohci_softc_t *sc) 1282 { 1283 uint32_t intrs, eintrs; 1284 1285 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1286 1287 /* In case the interrupt occurs before initialization has completed. */ 1288 if (sc == NULL || sc->sc_hcca == NULL) { 1289 #ifdef DIAGNOSTIC 1290 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1291 #endif 1292 return 0; 1293 } 1294 1295 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1296 1297 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1298 if (!intrs) 1299 return 0; 1300 1301 /* Acknowledge */ 1302 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); 1303 eintrs = intrs & sc->sc_eintrs; 1304 DPRINTFN(7, "sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1305 DPRINTFN(7, "intrs=%#jx(%#jx) eintrs=%#jx(%#jx)", 1306 intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), eintrs, 1307 sc->sc_eintrs); 1308 1309 if (!eintrs) { 1310 return 0; 1311 } 1312 1313 if (eintrs & OHCI_SO) { 1314 sc->sc_overrun_cnt++; 1315 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1316 printf("%s: %u scheduling overruns\n", 1317 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1318 sc->sc_overrun_cnt = 0; 1319 } 1320 /* XXX do what */ 1321 eintrs &= ~OHCI_SO; 1322 } 1323 if (eintrs & OHCI_WDH) { 1324 /* 1325 * We block the interrupt below, and reenable it later from 1326 * ohci_softintr(). 1327 */ 1328 usb_schedsoftintr(&sc->sc_bus); 1329 } 1330 if (eintrs & OHCI_SF) { 1331 struct ohci_xfer *ox, *tmp; 1332 TAILQ_FOREACH_SAFE(ox, &sc->sc_abortingxfers, ox_abnext, tmp) { 1333 DPRINTFN(10, "SF %#jx xfer %#jx", (uintptr_t)sc, 1334 (uintptr_t)ox, 0, 0); 1335 ox->ox_abintrs &= ~OHCI_SF; 1336 KASSERT(ox->ox_abintrs == 0); 1337 TAILQ_REMOVE(&sc->sc_abortingxfers, ox, ox_abnext); 1338 } 1339 cv_broadcast(&sc->sc_abort_cv); 1340 1341 KASSERT(TAILQ_EMPTY(&sc->sc_abortingxfers)); 1342 DPRINTFN(10, "end SOF %#jx", (uintptr_t)sc, 0, 0, 0); 1343 /* Don't remove OHIC_SF from eintrs so it is blocked below */ 1344 } 1345 if (eintrs & OHCI_RD) { 1346 DPRINTFN(5, "resume detect sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1347 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1348 /* XXX process resume detect */ 1349 } 1350 if (eintrs & OHCI_UE) { 1351 DPRINTFN(5, "unrecoverable error sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1352 printf("%s: unrecoverable error, controller halted\n", 1353 device_xname(sc->sc_dev)); 1354 OWRITE4(sc, OHCI_CONTROL, OHCI_SET_HCFS(OHCI_HCFS_RESET)); 1355 /* XXX what else */ 1356 } 1357 if (eintrs & OHCI_RHSC) { 1358 /* 1359 * We block the interrupt below, and reenable it later from 1360 * a timeout. 1361 */ 1362 softint_schedule(sc->sc_rhsc_si); 1363 } 1364 1365 if (eintrs != 0) { 1366 /* Block unprocessed interrupts. */ 1367 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1368 sc->sc_eintrs &= ~eintrs; 1369 DPRINTF("sc %#jx blocking intrs %#jx", (uintptr_t)sc, 1370 eintrs, 0, 0); 1371 } 1372 1373 return 1; 1374 } 1375 1376 void 1377 ohci_rhsc_enable(void *v_sc) 1378 { 1379 ohci_softc_t *sc = v_sc; 1380 1381 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1382 DPRINTF("sc %#jx", (uintptr_t)sc, 0, 0, 0); 1383 mutex_spin_enter(&sc->sc_intr_lock); 1384 sc->sc_eintrs |= OHCI_RHSC; 1385 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1386 mutex_spin_exit(&sc->sc_intr_lock); 1387 } 1388 1389 #ifdef OHCI_DEBUG 1390 const char *const ohci_cc_strs[] = { 1391 "NO_ERROR", 1392 "CRC", 1393 "BIT_STUFFING", 1394 "DATA_TOGGLE_MISMATCH", 1395 "STALL", 1396 "DEVICE_NOT_RESPONDING", 1397 "PID_CHECK_FAILURE", 1398 "UNEXPECTED_PID", 1399 "DATA_OVERRUN", 1400 "DATA_UNDERRUN", 1401 "BUFFER_OVERRUN", 1402 "BUFFER_UNDERRUN", 1403 "reserved", 1404 "reserved", 1405 "NOT_ACCESSED", 1406 "NOT_ACCESSED", 1407 }; 1408 #endif 1409 1410 void 1411 ohci_softintr(void *v) 1412 { 1413 struct usbd_bus *bus = v; 1414 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1415 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1416 ohci_soft_td_t *std, *sdone, *stdnext; 1417 struct usbd_xfer *xfer; 1418 struct ohci_pipe *opipe; 1419 int len, cc; 1420 int i, j, actlen, iframes, uedir; 1421 ohci_physaddr_t done = 0; 1422 1423 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1424 1425 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1426 1427 /* 1428 * Only read hccadone if WDH is set - we might get here from places 1429 * other than an interrupt 1430 */ 1431 if (!(OREAD4(sc, OHCI_INTERRUPT_STATUS) & OHCI_WDH)) { 1432 DPRINTFN(10, "no WDH %#jx", (uintptr_t)sc, 0, 0, 0); 1433 return; 1434 } 1435 1436 DPRINTFN(10, "WDH %#jx", (uintptr_t)sc, 0, 0, 0); 1437 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1438 sizeof(sc->sc_hcca->hcca_done_head), 1439 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1440 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1441 sc->sc_hcca->hcca_done_head = 0; 1442 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1443 sizeof(sc->sc_hcca->hcca_done_head), 1444 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1445 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1446 sc->sc_eintrs |= OHCI_WDH; 1447 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1448 1449 /* Reverse the done list. */ 1450 for (sdone = NULL, sidone = NULL; done != 0; ) { 1451 std = ohci_hash_find_td(sc, done); 1452 if (std != NULL) { 1453 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1454 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1455 std->dnext = sdone; 1456 done = O32TOH(std->td.td_nexttd); 1457 sdone = std; 1458 DPRINTFN(10, "add TD %#jx", (uintptr_t)std, 0, 0, 0); 1459 continue; 1460 } 1461 sitd = ohci_hash_find_itd(sc, done); 1462 if (sitd != NULL) { 1463 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1464 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1465 sitd->dnext = sidone; 1466 done = O32TOH(sitd->itd.itd_nextitd); 1467 sidone = sitd; 1468 DPRINTFN(5, "add ITD %#jx", (uintptr_t)sitd, 0, 0, 0); 1469 continue; 1470 } 1471 DPRINTFN(10, "addr %#jx not found", (uintptr_t)done, 0, 0, 0); 1472 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1473 (u_long)done); 1474 break; 1475 } 1476 1477 DPRINTFN(10, "sdone=%#jx sidone=%#jx", (uintptr_t)sdone, 1478 (uintptr_t)sidone, 0, 0); 1479 DPRINTFN(10, "--- TD dump start ---", 0, 0, 0, 0); 1480 #ifdef OHCI_DEBUG 1481 if (ohcidebug >= 10) { 1482 for (std = sdone; std; std = std->dnext) 1483 ohci_dump_td(sc, std); 1484 } 1485 #endif 1486 DPRINTFN(10, "--- TD dump end ---", 0, 0, 0, 0); 1487 1488 for (std = sdone; std; std = stdnext) { 1489 stdnext = std->dnext; 1490 if (std->held == NULL) { 1491 DPRINTFN(10, "std=%#jx held is null", (uintptr_t)std, 1492 0, 0, 0); 1493 ohci_hash_rem_td(sc, std); 1494 ohci_free_std_locked(sc, std); 1495 continue; 1496 } 1497 1498 xfer = std->xfer; 1499 DPRINTFN(10, "std=%#jx xfer=%#jx hcpriv=%#jx dnext=%#jx", 1500 (uintptr_t)std, (uintptr_t)xfer, 1501 (uintptr_t)(xfer ? xfer->ux_hcpriv : 0), (uintptr_t)stdnext); 1502 if (xfer == NULL) { 1503 /* 1504 * xfer == NULL: There seems to be no xfer associated 1505 * with this TD. It is tailp that happened to end up on 1506 * the done queue. 1507 * Shouldn't happen, but some chips are broken(?). 1508 */ 1509 continue; 1510 } 1511 /* 1512 * Try to claim this xfer for completion. If it has 1513 * already completed or aborted, drop it on the floor. 1514 */ 1515 if (!usbd_xfer_trycomplete(xfer)) 1516 continue; 1517 1518 len = std->len; 1519 if (std->td.td_cbp != 0) 1520 len -= O32TOH(std->td.td_be) - 1521 O32TOH(std->td.td_cbp) + 1; 1522 DPRINTFN(10, "len=%jd, flags=%#jx", len, std->flags, 0, 0); 1523 if (std->flags & OHCI_ADD_LEN) 1524 xfer->ux_actlen += len; 1525 1526 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1527 if (cc == OHCI_CC_NO_ERROR) { 1528 ohci_hash_rem_td(sc, std); 1529 if (std->flags & OHCI_CALL_DONE) { 1530 xfer->ux_status = USBD_NORMAL_COMPLETION; 1531 usb_transfer_complete(xfer); 1532 } 1533 } else { 1534 /* 1535 * Endpoint is halted. First unlink all the TDs 1536 * belonging to the failed transfer, and then restart 1537 * the endpoint. 1538 */ 1539 ohci_soft_td_t *p, *n; 1540 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1541 1542 DPRINTFN(10, "error cc=%jd", cc, 0, 0, 0); 1543 1544 /* remove xfer's TDs from the hash */ 1545 for (p = std; p->xfer == xfer; p = n) { 1546 n = p->nexttd; 1547 ohci_hash_rem_td(sc, p); 1548 } 1549 1550 ohci_soft_ed_t *sed = opipe->sed; 1551 1552 /* clear halt and TD chain, preserving toggle carry */ 1553 sed->ed.ed_headp = HTOO32(p->physaddr | 1554 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 1555 usb_syncmem(&sed->dma, 1556 sed->offs + offsetof(ohci_ed_t, ed_headp), 1557 sizeof(sed->ed.ed_headp), 1558 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1559 1560 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1561 1562 if (cc == OHCI_CC_DATA_UNDERRUN) 1563 xfer->ux_status = USBD_NORMAL_COMPLETION; 1564 else if (cc == OHCI_CC_STALL) 1565 xfer->ux_status = USBD_STALLED; 1566 else 1567 xfer->ux_status = USBD_IOERROR; 1568 usb_transfer_complete(xfer); 1569 } 1570 } 1571 DPRINTFN(10, "--- ITD dump start ---", 0, 0, 0, 0); 1572 #ifdef OHCI_DEBUG 1573 if (ohcidebug >= 10) { 1574 for (sitd = sidone; sitd; sitd = sitd->dnext) 1575 ohci_dump_itd(sc, sitd); 1576 } 1577 #endif 1578 DPRINTFN(10, "--- ITD dump end ---", 0, 0, 0, 0); 1579 1580 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1581 xfer = sitd->xfer; 1582 sitdnext = sitd->dnext; 1583 DPRINTFN(1, "sitd=%#jx xfer=%#jx hcpriv=%#jx", (uintptr_t)sitd, 1584 (uintptr_t)xfer, (uintptr_t)(xfer ? xfer->ux_hcpriv : 0), 1585 0); 1586 if (xfer == NULL) 1587 continue; 1588 1589 /* 1590 * Try to claim this xfer for completion. If it has 1591 * already completed or aborted, drop it on the floor. 1592 */ 1593 if (!usbd_xfer_trycomplete(xfer)) 1594 continue; 1595 1596 KASSERT(!sitd->isdone); 1597 #ifdef DIAGNOSTIC 1598 sitd->isdone = true; 1599 #endif 1600 if (sitd->flags & OHCI_CALL_DONE) { 1601 ohci_soft_itd_t *next; 1602 1603 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1604 opipe->isoc.inuse -= xfer->ux_nframes; 1605 uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc-> 1606 bEndpointAddress); 1607 xfer->ux_status = USBD_NORMAL_COMPLETION; 1608 actlen = 0; 1609 for (i = 0, sitd = xfer->ux_hcpriv;; 1610 sitd = next) { 1611 next = sitd->nextitd; 1612 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1613 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1614 xfer->ux_status = USBD_IOERROR; 1615 /* For input, update frlengths with actual */ 1616 /* XXX anything necessary for output? */ 1617 if (uedir == UE_DIR_IN && 1618 xfer->ux_status == USBD_NORMAL_COMPLETION) { 1619 iframes = OHCI_ITD_GET_FC(O32TOH( 1620 sitd->itd.itd_flags)); 1621 for (j = 0; j < iframes; i++, j++) { 1622 len = O16TOH(sitd-> 1623 itd.itd_offset[j]); 1624 if ((OHCI_ITD_PSW_GET_CC(len) & 1625 OHCI_CC_NOT_ACCESSED_MASK) 1626 == OHCI_CC_NOT_ACCESSED) 1627 len = 0; 1628 else 1629 len = OHCI_ITD_PSW_SIZE(len); 1630 xfer->ux_frlengths[i] = len; 1631 actlen += len; 1632 } 1633 } 1634 if (sitd->flags & OHCI_CALL_DONE) 1635 break; 1636 ohci_hash_rem_itd(sc, sitd); 1637 1638 } 1639 ohci_hash_rem_itd(sc, sitd); 1640 if (uedir == UE_DIR_IN && 1641 xfer->ux_status == USBD_NORMAL_COMPLETION) 1642 xfer->ux_actlen = actlen; 1643 xfer->ux_hcpriv = NULL; 1644 1645 usb_transfer_complete(xfer); 1646 } 1647 } 1648 1649 DPRINTFN(10, "done", 0, 0, 0, 0); 1650 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1651 } 1652 1653 void 1654 ohci_device_ctrl_done(struct usbd_xfer *xfer) 1655 { 1656 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1657 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1658 int len = UGETW(xfer->ux_request.wLength); 1659 int isread = (xfer->ux_request.bmRequestType & UT_READ); 1660 1661 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1662 DPRINTFN(10, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 1663 1664 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1665 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 1666 1667 if (len) 1668 usb_syncmem(&xfer->ux_dmabuf, 0, len, 1669 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1670 usb_syncmem(&opipe->ctrl.reqdma, 0, 1671 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1672 } 1673 1674 void 1675 ohci_device_intr_done(struct usbd_xfer *xfer) 1676 { 1677 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1678 int isread = 1679 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1680 1681 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1682 DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, 1683 xfer->ux_actlen, 0, 0); 1684 1685 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1686 1687 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1688 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1689 } 1690 1691 void 1692 ohci_device_bulk_done(struct usbd_xfer *xfer) 1693 { 1694 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1695 1696 int isread = 1697 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1698 1699 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1700 1701 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1702 DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 1703 0, 0); 1704 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1705 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1706 } 1707 1708 Static void 1709 ohci_rhsc_softint(void *arg) 1710 { 1711 ohci_softc_t *sc = arg; 1712 1713 mutex_enter(&sc->sc_lock); 1714 1715 ohci_rhsc(sc, sc->sc_intrxfer); 1716 1717 /* Do not allow RHSC interrupts > 1 per second */ 1718 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1719 1720 mutex_exit(&sc->sc_lock); 1721 } 1722 1723 void 1724 ohci_rhsc(ohci_softc_t *sc, struct usbd_xfer *xfer) 1725 { 1726 u_char *p; 1727 int i, m; 1728 int hstatus __unused; 1729 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1730 1731 KASSERT(mutex_owned(&sc->sc_lock)); 1732 1733 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1734 DPRINTF("sc=%#jx xfer=%#jx hstatus=0x%08jx", (uintptr_t)sc, 1735 (uintptr_t)xfer, hstatus, 0); 1736 1737 if (xfer == NULL) { 1738 /* Just ignore the change. */ 1739 return; 1740 } 1741 KASSERT(xfer == sc->sc_intrxfer); 1742 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 1743 1744 p = xfer->ux_buf; 1745 m = uimin(sc->sc_noport, xfer->ux_length * 8 - 1); 1746 memset(p, 0, xfer->ux_length); 1747 for (i = 1; i <= m; i++) { 1748 /* Pick out CHANGE bits from the status reg. */ 1749 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1750 p[i/8] |= 1 << (i%8); 1751 } 1752 DPRINTF("change=0x%02jx", *p, 0, 0, 0); 1753 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 1754 xfer->ux_actlen = xfer->ux_length; 1755 xfer->ux_status = USBD_NORMAL_COMPLETION; 1756 1757 usb_transfer_complete(xfer); 1758 } 1759 1760 void 1761 ohci_root_intr_done(struct usbd_xfer *xfer) 1762 { 1763 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1764 1765 KASSERT(mutex_owned(&sc->sc_lock)); 1766 1767 /* Claim the xfer so it doesn't get completed again. */ 1768 KASSERT(sc->sc_intrxfer == xfer); 1769 KASSERT(xfer->ux_status != USBD_IN_PROGRESS); 1770 sc->sc_intrxfer = NULL; 1771 } 1772 1773 void 1774 ohci_poll(struct usbd_bus *bus) 1775 { 1776 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1777 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1778 1779 #ifdef OHCI_DEBUG 1780 static int last; 1781 int new; 1782 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1783 if (new != last) { 1784 DPRINTFN(10, "intrs=0x%04jx", new, 0, 0, 0); 1785 last = new; 1786 } 1787 #endif 1788 sc->sc_eintrs |= OHCI_WDH; 1789 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1790 mutex_spin_enter(&sc->sc_intr_lock); 1791 ohci_intr1(sc); 1792 mutex_spin_exit(&sc->sc_intr_lock); 1793 } 1794 } 1795 1796 /* 1797 * Add an ED to the schedule. Called with USB lock held. 1798 */ 1799 Static void 1800 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1801 { 1802 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1803 DPRINTFN(8, "sed=%#jx head=%#jx", (uintptr_t)sed, (uintptr_t)head, 0, 1804 0); 1805 1806 KASSERT(mutex_owned(&sc->sc_lock)); 1807 1808 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1809 sizeof(head->ed.ed_nexted), 1810 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1811 sed->next = head->next; 1812 sed->ed.ed_nexted = head->ed.ed_nexted; 1813 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1814 sizeof(sed->ed.ed_nexted), 1815 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1816 head->next = sed; 1817 head->ed.ed_nexted = HTOO32(sed->physaddr); 1818 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1819 sizeof(head->ed.ed_nexted), 1820 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1821 } 1822 1823 /* 1824 * Remove an ED from the schedule. Called with USB lock held. 1825 */ 1826 Static void 1827 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1828 { 1829 ohci_soft_ed_t *p; 1830 1831 KASSERT(mutex_owned(&sc->sc_lock)); 1832 1833 /* XXX */ 1834 for (p = head; p != NULL && p->next != sed; p = p->next) 1835 ; 1836 KASSERT(p != NULL); 1837 1838 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1839 sizeof(sed->ed.ed_nexted), 1840 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1841 p->next = sed->next; 1842 p->ed.ed_nexted = sed->ed.ed_nexted; 1843 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1844 sizeof(p->ed.ed_nexted), 1845 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1846 } 1847 1848 /* 1849 * When a transfer is completed the TD is added to the done queue by 1850 * the host controller. This queue is the processed by software. 1851 * Unfortunately the queue contains the physical address of the TD 1852 * and we have no simple way to translate this back to a kernel address. 1853 * To make the translation possible (and fast) we use a hash table of 1854 * TDs currently in the schedule. The physical address is used as the 1855 * hash value. 1856 */ 1857 1858 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1859 /* Called with USB lock held. */ 1860 void 1861 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1862 { 1863 int h = HASH(std->physaddr); 1864 1865 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1866 1867 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1868 } 1869 1870 /* Called with USB lock held. */ 1871 void 1872 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1873 { 1874 1875 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1876 1877 LIST_REMOVE(std, hnext); 1878 } 1879 1880 ohci_soft_td_t * 1881 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1882 { 1883 int h = HASH(a); 1884 ohci_soft_td_t *std; 1885 1886 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1887 std != NULL; 1888 std = LIST_NEXT(std, hnext)) 1889 if (std->physaddr == a) 1890 return std; 1891 return NULL; 1892 } 1893 1894 /* Called with USB lock held. */ 1895 void 1896 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1897 { 1898 int h = HASH(sitd->physaddr); 1899 1900 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1901 1902 KASSERT(mutex_owned(&sc->sc_lock)); 1903 1904 DPRINTFN(10, "sitd=%#jx physaddr=0x%08jx", 1905 (uintptr_t)sitd, (u_long)sitd->physaddr, 0, 0); 1906 1907 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1908 } 1909 1910 /* Called with USB lock held. */ 1911 void 1912 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1913 { 1914 1915 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1916 1917 KASSERT(mutex_owned(&sc->sc_lock)); 1918 1919 DPRINTFN(10, "sitd=%#jx physaddr=0x%08jx", (uintptr_t)sitd, 1920 sitd->physaddr, 0, 0); 1921 1922 LIST_REMOVE(sitd, hnext); 1923 } 1924 1925 ohci_soft_itd_t * 1926 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1927 { 1928 int h = HASH(a); 1929 ohci_soft_itd_t *sitd; 1930 1931 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1932 sitd != NULL; 1933 sitd = LIST_NEXT(sitd, hnext)) 1934 if (sitd->physaddr == a) 1935 return sitd; 1936 return NULL; 1937 } 1938 1939 #ifdef OHCI_DEBUG 1940 void 1941 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 1942 { 1943 for (; std; std = std->nexttd) { 1944 ohci_dump_td(sc, std); 1945 KASSERTMSG(std->nexttd == NULL || std != std->nexttd, 1946 "std %p next %p", std, std->nexttd); 1947 } 1948 } 1949 1950 void 1951 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1952 { 1953 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1954 1955 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1956 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1957 1958 uint32_t flags = O32TOH(std->td.td_flags); 1959 DPRINTF("TD(%#jx) at 0x%08jx:", (uintptr_t)std, std->physaddr, 0, 0); 1960 DPRINTF(" round=%jd DP=%jx DI=%jx T=%jx", 1961 !!(flags & OHCI_TD_R), 1962 OHCI_TD_GET_DP(flags), 1963 OHCI_TD_GET_DI(flags), 1964 OHCI_TD_GET_TOGGLE(flags)); 1965 DPRINTF(" EC=%jd CC=%jd", OHCI_TD_GET_EC(flags), 1966 OHCI_TD_GET_CC(flags), 0, 0); 1967 DPRINTF(" td_cbp=0x%08jx td_nexttd=0x%08jx td_be=0x%08jx", 1968 (u_long)O32TOH(std->td.td_cbp), 1969 (u_long)O32TOH(std->td.td_nexttd), 1970 (u_long)O32TOH(std->td.td_be), 0); 1971 } 1972 1973 void 1974 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1975 { 1976 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1977 1978 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1979 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1980 1981 uint32_t flags = O32TOH(sitd->itd.itd_flags); 1982 DPRINTF("ITD(%#jx) at 0x%08jx", (uintptr_t)sitd, sitd->physaddr, 0, 0); 1983 DPRINTF(" sf=%jd di=%jd fc=%jd cc=%jd", 1984 OHCI_ITD_GET_SF(flags), OHCI_ITD_GET_DI(flags), 1985 OHCI_ITD_GET_FC(flags), OHCI_ITD_GET_CC(flags)); 1986 DPRINTF(" bp0=0x%08jx next=0x%08jx be=0x%08jx", 1987 O32TOH(sitd->itd.itd_bp0), 1988 O32TOH(sitd->itd.itd_nextitd), 1989 O32TOH(sitd->itd.itd_be), 0); 1990 CTASSERT(OHCI_ITD_NOFFSET == 8); 1991 DPRINTF(" offs[0] = 0x%04jx offs[1] = 0x%04jx " 1992 "offs[2] = 0x%04jx offs[3] = 0x%04jx", 1993 O16TOH(sitd->itd.itd_offset[0]), 1994 O16TOH(sitd->itd.itd_offset[1]), 1995 O16TOH(sitd->itd.itd_offset[2]), 1996 O16TOH(sitd->itd.itd_offset[3])); 1997 DPRINTF(" offs[4] = 0x%04jx offs[5] = 0x%04jx " 1998 "offs[6] = 0x%04jx offs[7] = 0x%04jx", 1999 O16TOH(sitd->itd.itd_offset[4]), 2000 O16TOH(sitd->itd.itd_offset[5]), 2001 O16TOH(sitd->itd.itd_offset[6]), 2002 O16TOH(sitd->itd.itd_offset[7])); 2003 } 2004 2005 void 2006 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2007 { 2008 for (; sitd; sitd = sitd->nextitd) 2009 ohci_dump_itd(sc, sitd); 2010 } 2011 2012 void 2013 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2014 { 2015 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2016 2017 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2018 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2019 2020 uint32_t flags = O32TOH(sed->ed.ed_flags); 2021 DPRINTF("ED(%#jx) at 0x%08jx:", (uintptr_t)sed, sed->physaddr, 0, 0); 2022 DPRINTF(" addr=%jd endpt=%jd maxp=%jd", 2023 OHCI_ED_GET_FA(flags), 2024 OHCI_ED_GET_EN(flags), 2025 OHCI_ED_GET_MAXP(flags), 2026 0); 2027 DPRINTF(" dir=%jd speed=%jd skip=%jd iso=%jd", 2028 OHCI_ED_GET_DIR(flags), 2029 __SHIFTOUT(flags, OHCI_ED_SPEED), 2030 __SHIFTOUT(flags, OHCI_ED_SKIP), 2031 OHCI_ED_GET_FORMAT(flags)); 2032 DPRINTF(" tailp=0x%08jx", (u_long)O32TOH(sed->ed.ed_tailp), 2033 0, 0, 0); 2034 DPRINTF(" headp=0x%08jx nexted=0x%08jx halted=%jd carry=%jd", 2035 O32TOH(sed->ed.ed_headp), O32TOH(sed->ed.ed_nexted), 2036 !!(O32TOH(sed->ed.ed_headp) & OHCI_HALTED), 2037 !!(O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 2038 } 2039 #endif 2040 2041 usbd_status 2042 ohci_open(struct usbd_pipe *pipe) 2043 { 2044 struct usbd_device *dev = pipe->up_dev; 2045 struct usbd_bus *bus = dev->ud_bus; 2046 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2047 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 2048 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2049 uint8_t addr = dev->ud_addr; 2050 uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2051 ohci_soft_ed_t *sed; 2052 ohci_soft_td_t *std; 2053 ohci_soft_itd_t *sitd; 2054 ohci_physaddr_t tdphys; 2055 uint32_t fmt; 2056 usbd_status err = USBD_NOMEM; 2057 int ival; 2058 2059 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2060 DPRINTFN(1, "pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, 2061 addr, ed->bEndpointAddress, bus->ub_rhaddr); 2062 2063 if (sc->sc_dying) { 2064 return USBD_IOERROR; 2065 } 2066 2067 std = NULL; 2068 sed = NULL; 2069 2070 if (addr == bus->ub_rhaddr) { 2071 switch (ed->bEndpointAddress) { 2072 case USB_CONTROL_ENDPOINT: 2073 pipe->up_methods = &roothub_ctrl_methods; 2074 break; 2075 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 2076 pipe->up_methods = &ohci_root_intr_methods; 2077 break; 2078 default: 2079 err = USBD_INVAL; 2080 goto bad; 2081 } 2082 } else { 2083 sed = ohci_alloc_sed(sc); 2084 if (sed == NULL) 2085 goto bad; 2086 opipe->sed = sed; 2087 if (xfertype == UE_ISOCHRONOUS) { 2088 sitd = ohci_alloc_sitd(sc); 2089 if (sitd == NULL) 2090 goto bad; 2091 2092 opipe->tail.itd = sitd; 2093 sitd->held = &opipe->tail.itd; 2094 tdphys = sitd->physaddr; 2095 fmt = OHCI_ED_SET_FORMAT(OHCI_ED_FORMAT_ISO); 2096 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2097 fmt |= OHCI_ED_SET_DIR(OHCI_ED_DIR_IN); 2098 else 2099 fmt |= OHCI_ED_SET_DIR(OHCI_ED_DIR_OUT); 2100 } else { 2101 std = ohci_alloc_std(sc); 2102 if (std == NULL) 2103 goto bad; 2104 2105 opipe->tail.td = std; 2106 std->held = &opipe->tail.td; 2107 tdphys = std->physaddr; 2108 fmt = 2109 OHCI_ED_SET_FORMAT(OHCI_ED_FORMAT_GEN) | 2110 OHCI_ED_SET_DIR(OHCI_ED_DIR_TD); 2111 } 2112 sed->ed.ed_flags = HTOO32( 2113 OHCI_ED_SET_FA(addr) | 2114 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2115 (dev->ud_speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2116 fmt | 2117 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2118 sed->ed.ed_headp = HTOO32(tdphys | 2119 (pipe->up_endpoint->ue_toggle ? OHCI_TOGGLECARRY : 0)); 2120 sed->ed.ed_tailp = HTOO32(tdphys); 2121 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2122 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2123 2124 switch (xfertype) { 2125 case UE_CONTROL: 2126 pipe->up_methods = &ohci_device_ctrl_methods; 2127 int error = usb_allocmem(sc->sc_bus.ub_dmatag, 2128 sizeof(usb_device_request_t), 0, 2129 USBMALLOC_COHERENT, &opipe->ctrl.reqdma); 2130 if (error) 2131 goto bad; 2132 mutex_enter(&sc->sc_lock); 2133 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2134 mutex_exit(&sc->sc_lock); 2135 break; 2136 case UE_INTERRUPT: 2137 pipe->up_methods = &ohci_device_intr_methods; 2138 ival = pipe->up_interval; 2139 if (ival == USBD_DEFAULT_INTERVAL) 2140 ival = ed->bInterval; 2141 err = ohci_device_setintr(sc, opipe, ival); 2142 if (err) 2143 goto bad; 2144 break; 2145 case UE_ISOCHRONOUS: 2146 pipe->up_serialise = false; 2147 pipe->up_methods = &ohci_device_isoc_methods; 2148 return ohci_setup_isoc(pipe); 2149 case UE_BULK: 2150 pipe->up_methods = &ohci_device_bulk_methods; 2151 mutex_enter(&sc->sc_lock); 2152 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2153 mutex_exit(&sc->sc_lock); 2154 break; 2155 } 2156 } 2157 2158 return USBD_NORMAL_COMPLETION; 2159 2160 bad: 2161 if (std != NULL) { 2162 ohci_free_std(sc, std); 2163 } 2164 if (sed != NULL) 2165 ohci_free_sed(sc, sed); 2166 return err; 2167 2168 } 2169 2170 /* 2171 * Close a regular pipe. 2172 * Assumes that there are no pending transactions. 2173 */ 2174 void 2175 ohci_close_pipe(struct usbd_pipe *pipe, ohci_soft_ed_t *head) 2176 { 2177 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2178 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2179 ohci_soft_ed_t *sed = opipe->sed; 2180 2181 KASSERT(mutex_owned(&sc->sc_lock)); 2182 2183 #ifdef DIAGNOSTIC 2184 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2185 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2186 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2187 ohci_soft_td_t *std; 2188 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2189 printf("ohci_close_pipe: pipe not empty sed=%p hd=%#x " 2190 "tl=%#x pipe=%p, std=%p\n", sed, 2191 (int)O32TOH(sed->ed.ed_headp), 2192 (int)O32TOH(sed->ed.ed_tailp), 2193 pipe, std); 2194 #ifdef OHCI_DEBUG 2195 usbd_dump_pipe(&opipe->pipe); 2196 ohci_dump_ed(sc, sed); 2197 if (std) 2198 ohci_dump_td(sc, std); 2199 #endif 2200 usb_delay_ms(&sc->sc_bus, 2); 2201 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2202 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2203 printf("ohci_close_pipe: pipe still not empty\n"); 2204 } 2205 #endif 2206 ohci_rem_ed(sc, sed, head); 2207 /* Make sure the host controller is not touching this ED */ 2208 usb_delay_ms(&sc->sc_bus, 1); 2209 pipe->up_endpoint->ue_toggle = 2210 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2211 ohci_free_sed_locked(sc, opipe->sed); 2212 } 2213 2214 /* 2215 * Arrange for the hardware to tells us that it is not still processing 2216 * the TDs by setting the sKip bit and requesting a SOF interrupt 2217 * 2218 * Once we see the SOF interrupt we can check the transfer TDs/iTDs to see if 2219 * they've been processed and either 2220 * a) if they're unused recover them for later use, or 2221 * b) if they've been used allocate new TD/iTDs to replace those 2222 * used. The softint handler will free the old ones. 2223 */ 2224 void 2225 ohci_abortx(struct usbd_xfer *xfer) 2226 { 2227 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2228 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2229 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2230 ohci_soft_ed_t *sed = opipe->sed; 2231 ohci_soft_td_t *p, *n; 2232 ohci_physaddr_t headp; 2233 int hit; 2234 2235 DPRINTF("xfer=%#jx pipe=%#jx sed=%#jx", (uintptr_t)xfer, 2236 (uintptr_t)opipe, (uintptr_t)sed, 0); 2237 2238 KASSERT(mutex_owned(&sc->sc_lock)); 2239 ASSERT_SLEEPABLE(); 2240 2241 KASSERTMSG((xfer->ux_status == USBD_CANCELLED || 2242 xfer->ux_status == USBD_TIMEOUT), 2243 "bad abort status: %d", xfer->ux_status); 2244 2245 /* 2246 * If we're dying, skip the hardware action and just notify the 2247 * software that we're done. 2248 */ 2249 if (sc->sc_dying) { 2250 DPRINTFN(4, "xfer %#jx dying %ju", (uintptr_t)xfer, 2251 xfer->ux_status, 0, 0); 2252 goto dying; 2253 } 2254 2255 /* 2256 * HC Step 1: Unless the endpoint is already halted, we set the 2257 * endpoint descriptor sKip bit and wait for hardware to complete 2258 * processing. We ensure the HC stops processing the endpoint by 2259 * waiting for the next start of frame (OHCI_SF) 2260 */ 2261 DPRINTFN(1, "stop ed=%#jx", (uintptr_t)sed, 0, 0, 0); 2262 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2263 sizeof(sed->ed.ed_flags), 2264 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2265 if (!(sed->ed.ed_flags & OHCI_HALTED)) { 2266 /* force hardware skip */ 2267 DPRINTFN(1, "pausing ed=%#jx", (uintptr_t)sed, 0, 0, 0); 2268 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2269 usb_syncmem(&sed->dma, 2270 sed->offs + offsetof(ohci_ed_t, ed_flags), 2271 sizeof(sed->ed.ed_flags), 2272 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2273 2274 DPRINTFN(10, "SF %#jx xfer %#jx", (uintptr_t)sc, 2275 (uintptr_t)xfer, 0, 0); 2276 2277 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2278 ox->ox_abintrs = OHCI_SF; 2279 2280 mutex_enter(&sc->sc_intr_lock); 2281 TAILQ_INSERT_TAIL(&sc->sc_abortingxfers, ox, ox_abnext); 2282 2283 /* Clear any previous SF interrupt */ 2284 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_SF); 2285 2286 /* Tell interrupt handler and HC SF interrupt is requested */ 2287 sc->sc_eintrs |= OHCI_SF; 2288 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_SF); 2289 /* 2290 * Step 2: Wait until we know hardware has finished any 2291 * processing of the end-point. 2292 */ 2293 while (ox->ox_abintrs != 0) { 2294 DPRINTFN(10, "SF %#jx xfer %#jx intrs %#x", 2295 (uintptr_t)sc, (uintptr_t)xfer, 2296 (uintptr_t)ox->ox_abintrs, 0); 2297 cv_wait(&sc->sc_abort_cv, &sc->sc_intr_lock); 2298 } 2299 mutex_exit(&sc->sc_intr_lock); 2300 } else { 2301 DPRINTFN(1, "halted ed=%#jx", (uintptr_t)sed, 0, 0, 0); 2302 } 2303 2304 /* 2305 * HC Step 3: Remove any vestiges of the xfer from the hardware. 2306 * There are two complications here 2307 * 2308 * 1) the hardware may have executed beyond the xfer we're trying to 2309 * abort. So as we're scanning the TDs of this xfer we check if 2310 * the hardware points to any of them. 2311 * 2312 * 2) the hardware may have only partially excuted the transfer 2313 * which means some TDs will appear on the done list. Wait for 2314 * WDH so we can remove them safely. 2315 */ 2316 p = xfer->ux_hcpriv; 2317 KASSERT(p); 2318 2319 #ifdef OHCI_DEBUG 2320 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2321 2322 if (ohcidebug >= 2) { 2323 DPRINTF("sed:", 0, 0, 0, 0); 2324 ohci_dump_ed(sc, sed); 2325 ohci_dump_tds(sc, p); 2326 } 2327 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2328 #endif 2329 2330 2331 #define OHCI_CC_ACCESSED_P(x) \ 2332 (((x) & OHCI_CC_NOT_ACCESSED_MASK) != OHCI_CC_NOT_ACCESSED) 2333 2334 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2335 hit = 0; 2336 for (; p->xfer == xfer; p = n) { 2337 hit |= headp == p->physaddr; 2338 n = p->nexttd; 2339 2340 int cc = OHCI_TD_GET_CC(O32TOH(p->td.td_flags)); 2341 if (!OHCI_CC_ACCESSED_P(cc)) { 2342 ohci_hash_rem_td(sc, p); 2343 continue; 2344 } 2345 DPRINTFN(10, "xfer=%#jx has been touched by HC", (uintptr_t)p, 2346 0, 0, 0); 2347 2348 mutex_exit(&sc->sc_lock); 2349 ohci_soft_td_t *std; 2350 for (;;) { 2351 std = ohci_alloc_std(sc); 2352 if (std) 2353 break; 2354 kpause("ohciabt2", true, hz, NULL); 2355 } 2356 2357 mutex_enter(&sc->sc_lock); 2358 if (sc->sc_dying) { 2359 DPRINTFN(4, "xfer %#jx dying %ju", (uintptr_t)xfer, 2360 xfer->ux_status, 0, 0); 2361 goto dying; 2362 } 2363 2364 DPRINTFN(10, "new std=%#jx now held at %#jx", (uintptr_t)std, 2365 (uintptr_t)p->held, 0, 0); 2366 *(p->held) = std; 2367 std->held = p->held; 2368 std->xfer = xfer; 2369 p->held = NULL; 2370 } 2371 /* Zap headp register if hardware pointed inside the xfer. */ 2372 if (hit) { 2373 DPRINTFN(1, "set hd=0x%08jx, tl=0x%08jx", (int)p->physaddr, 2374 (int)O32TOH(sed->ed.ed_tailp), 0, 0); 2375 /* unlink TDs, preserving toggle carry */ 2376 sed->ed.ed_headp = HTOO32(p->physaddr | 2377 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 2378 usb_syncmem(&sed->dma, 2379 sed->offs + offsetof(ohci_ed_t, ed_headp), 2380 sizeof(sed->ed.ed_headp), 2381 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2382 } else { 2383 DPRINTFN(1, "no hit", 0, 0, 0, 0); 2384 } 2385 2386 /* 2387 * HC Step 4: Turn on hardware again. 2388 */ 2389 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2390 sizeof(sed->ed.ed_flags), 2391 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2392 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2393 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2394 sizeof(sed->ed.ed_flags), 2395 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2396 dying: 2397 DPRINTFN(14, "end", 0, 0, 0, 0); 2398 2399 KASSERT(mutex_owned(&sc->sc_lock)); 2400 } 2401 2402 /* 2403 * Data structures and routines to emulate the root hub. 2404 */ 2405 Static int 2406 ohci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2407 void *buf, int buflen) 2408 { 2409 ohci_softc_t *sc = OHCI_BUS2SC(bus); 2410 usb_port_status_t ps; 2411 uint16_t len, value, index; 2412 int l, totlen = 0; 2413 int port, i; 2414 uint32_t v; 2415 2416 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2417 2418 if (sc->sc_dying) 2419 return -1; 2420 2421 DPRINTFN(4, "type=0x%02jx request=%02jx", req->bmRequestType, 2422 req->bRequest, 0, 0); 2423 2424 len = UGETW(req->wLength); 2425 value = UGETW(req->wValue); 2426 index = UGETW(req->wIndex); 2427 2428 #define C(x,y) ((x) | ((y) << 8)) 2429 switch (C(req->bRequest, req->bmRequestType)) { 2430 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2431 DPRINTFN(8, "wValue=0x%04jx", value, 0, 0, 0); 2432 if (len == 0) 2433 break; 2434 switch (value) { 2435 #define sd ((usb_string_descriptor_t *)buf) 2436 case C(2, UDESC_STRING): 2437 /* Product */ 2438 totlen = usb_makestrdesc(sd, len, "OHCI root hub"); 2439 break; 2440 #undef sd 2441 default: 2442 /* default from usbroothub */ 2443 return buflen; 2444 } 2445 break; 2446 2447 /* Hub requests */ 2448 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2449 break; 2450 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2451 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", 2452 index, value, 0, 0); 2453 if (index < 1 || index > sc->sc_noport) { 2454 return -1; 2455 } 2456 port = OHCI_RH_PORT_STATUS(index); 2457 switch(value) { 2458 case UHF_PORT_ENABLE: 2459 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2460 break; 2461 case UHF_PORT_SUSPEND: 2462 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2463 break; 2464 case UHF_PORT_POWER: 2465 /* Yes, writing to the LOW_SPEED bit clears power. */ 2466 OWRITE4(sc, port, UPS_LOW_SPEED); 2467 break; 2468 case UHF_C_PORT_CONNECTION: 2469 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2470 break; 2471 case UHF_C_PORT_ENABLE: 2472 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2473 break; 2474 case UHF_C_PORT_SUSPEND: 2475 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2476 break; 2477 case UHF_C_PORT_OVER_CURRENT: 2478 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2479 break; 2480 case UHF_C_PORT_RESET: 2481 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2482 break; 2483 default: 2484 return -1; 2485 } 2486 switch(value) { 2487 case UHF_C_PORT_CONNECTION: 2488 case UHF_C_PORT_ENABLE: 2489 case UHF_C_PORT_SUSPEND: 2490 case UHF_C_PORT_OVER_CURRENT: 2491 case UHF_C_PORT_RESET: 2492 /* Enable RHSC interrupt if condition is cleared. */ 2493 if ((OREAD4(sc, port) >> 16) == 0) 2494 ohci_rhsc_enable(sc); 2495 break; 2496 default: 2497 break; 2498 } 2499 break; 2500 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2501 if (len == 0) 2502 break; 2503 if ((value & 0xff) != 0) { 2504 return -1; 2505 } 2506 usb_hub_descriptor_t hubd; 2507 2508 totlen = uimin(buflen, sizeof(hubd)); 2509 memcpy(&hubd, buf, totlen); 2510 2511 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2512 hubd.bNbrPorts = sc->sc_noport; 2513 USETW(hubd.wHubCharacteristics, 2514 (v & OHCI_RHD_NPS ? UHD_PWR_NO_SWITCH : 2515 v & OHCI_RHD_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2516 /* XXX overcurrent */ 2517 ); 2518 hubd.bPwrOn2PwrGood = OHCI_RHD_GET_POTPGT(v); 2519 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2520 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2521 hubd.DeviceRemovable[i++] = (uint8_t)v; 2522 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2523 totlen = uimin(totlen, hubd.bDescLength); 2524 memcpy(buf, &hubd, totlen); 2525 break; 2526 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2527 if (len != 4) { 2528 return -1; 2529 } 2530 memset(buf, 0, len); /* ? XXX */ 2531 totlen = len; 2532 break; 2533 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2534 DPRINTFN(8, "get port status i=%jd", index, 0, 0, 0); 2535 if (index < 1 || index > sc->sc_noport) { 2536 return -1; 2537 } 2538 if (len != 4) { 2539 return -1; 2540 } 2541 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2542 DPRINTFN(8, "port status=0x%04jx", v, 0, 0, 0); 2543 USETW(ps.wPortStatus, v); 2544 USETW(ps.wPortChange, v >> 16); 2545 totlen = uimin(len, sizeof(ps)); 2546 memcpy(buf, &ps, totlen); 2547 break; 2548 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2549 return -1; 2550 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2551 break; 2552 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2553 if (index < 1 || index > sc->sc_noport) { 2554 return -1; 2555 } 2556 port = OHCI_RH_PORT_STATUS(index); 2557 switch(value) { 2558 case UHF_PORT_ENABLE: 2559 OWRITE4(sc, port, UPS_PORT_ENABLED); 2560 break; 2561 case UHF_PORT_SUSPEND: 2562 OWRITE4(sc, port, UPS_SUSPEND); 2563 break; 2564 case UHF_PORT_RESET: 2565 DPRINTFN(5, "reset port %jd", index, 0, 0, 0); 2566 OWRITE4(sc, port, UPS_RESET); 2567 for (i = 0; i < 5; i++) { 2568 usb_delay_ms(&sc->sc_bus, 2569 USB_PORT_ROOT_RESET_DELAY); 2570 if (sc->sc_dying) { 2571 return -1; 2572 } 2573 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2574 break; 2575 } 2576 DPRINTFN(8, "port %jd reset, status = 0x%04jx", index, 2577 OREAD4(sc, port), 0, 0); 2578 break; 2579 case UHF_PORT_POWER: 2580 DPRINTFN(2, "set port power %jd", index, 0, 0, 0); 2581 OWRITE4(sc, port, UPS_PORT_POWER); 2582 break; 2583 default: 2584 return -1; 2585 } 2586 break; 2587 default: 2588 /* default from usbroothub */ 2589 return buflen; 2590 } 2591 2592 return totlen; 2593 } 2594 2595 Static usbd_status 2596 ohci_root_intr_transfer(struct usbd_xfer *xfer) 2597 { 2598 2599 /* Pipe isn't running, start first */ 2600 return ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2601 } 2602 2603 Static usbd_status 2604 ohci_root_intr_start(struct usbd_xfer *xfer) 2605 { 2606 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2607 2608 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2609 2610 if (sc->sc_dying) 2611 return USBD_IOERROR; 2612 2613 KASSERT(sc->sc_intrxfer == NULL); 2614 sc->sc_intrxfer = xfer; 2615 xfer->ux_status = USBD_IN_PROGRESS; 2616 2617 return USBD_IN_PROGRESS; 2618 } 2619 2620 /* Abort a root interrupt request. */ 2621 Static void 2622 ohci_root_intr_abort(struct usbd_xfer *xfer) 2623 { 2624 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2625 2626 KASSERT(mutex_owned(&sc->sc_lock)); 2627 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2628 2629 /* If xfer has already completed, nothing to do here. */ 2630 if (sc->sc_intrxfer == NULL) 2631 return; 2632 2633 /* 2634 * Otherwise, sc->sc_intrxfer had better be this transfer. 2635 * Cancel it. 2636 */ 2637 KASSERT(sc->sc_intrxfer == xfer); 2638 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 2639 xfer->ux_status = USBD_CANCELLED; 2640 usb_transfer_complete(xfer); 2641 } 2642 2643 /* Close the root pipe. */ 2644 Static void 2645 ohci_root_intr_close(struct usbd_pipe *pipe) 2646 { 2647 ohci_softc_t *sc __diagused = OHCI_PIPE2SC(pipe); 2648 2649 KASSERT(mutex_owned(&sc->sc_lock)); 2650 2651 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2652 2653 /* 2654 * Caller must guarantee the xfer has completed first, by 2655 * closing the pipe only after normal completion or an abort. 2656 */ 2657 KASSERT(sc->sc_intrxfer == NULL); 2658 } 2659 2660 /************************/ 2661 2662 int 2663 ohci_device_ctrl_init(struct usbd_xfer *xfer) 2664 { 2665 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2666 usb_device_request_t *req = &xfer->ux_request; 2667 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2668 ohci_soft_td_t *stat, *setup; 2669 int isread = req->bmRequestType & UT_READ; 2670 int len = xfer->ux_bufsize; 2671 int err = ENOMEM; 2672 2673 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2674 2675 setup = ohci_alloc_std(sc); 2676 if (setup == NULL) { 2677 goto bad1; 2678 } 2679 stat = ohci_alloc_std(sc); 2680 if (stat == NULL) { 2681 goto bad2; 2682 } 2683 2684 ox->ox_setup = setup; 2685 ox->ox_stat = stat; 2686 ox->ox_nstd = 0; 2687 setup->held = &ox->ox_setup; 2688 stat->held = &ox->ox_stat; 2689 2690 DPRINTFN(10, "xfer=%#jx setup=%#jx held at %#jx", (uintptr_t)ox, 2691 (uintptr_t)setup, (uintptr_t)setup->held, 0); 2692 DPRINTFN(10, "xfer=%#jx stat= %#jx held at %#jx", (uintptr_t)ox, 2693 (uintptr_t)stat, (uintptr_t)stat->held, 0); 2694 2695 /* Set up data transaction */ 2696 if (len != 0) { 2697 err = ohci_alloc_std_chain(sc, xfer, len, isread); 2698 if (err) { 2699 goto bad3; 2700 } 2701 } 2702 return 0; 2703 2704 bad3: 2705 ohci_free_std(sc, stat); 2706 bad2: 2707 ohci_free_std(sc, setup); 2708 bad1: 2709 return err; 2710 } 2711 2712 void 2713 ohci_device_ctrl_fini(struct usbd_xfer *xfer) 2714 { 2715 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2716 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2717 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2718 2719 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2720 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 2721 2722 mutex_enter(&sc->sc_lock); 2723 if (ox->ox_setup != opipe->tail.td) { 2724 ohci_free_std_locked(sc, ox->ox_setup); 2725 } 2726 for (size_t i = 0; i < ox->ox_nstd; i++) { 2727 ohci_soft_td_t *std = ox->ox_stds[i]; 2728 if (std == NULL) 2729 break; 2730 ohci_free_std_locked(sc, std); 2731 } 2732 ohci_free_std_locked(sc, ox->ox_stat); 2733 mutex_exit(&sc->sc_lock); 2734 2735 if (ox->ox_nstd) { 2736 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 2737 kmem_free(ox->ox_stds, sz); 2738 } 2739 } 2740 2741 Static usbd_status 2742 ohci_device_ctrl_transfer(struct usbd_xfer *xfer) 2743 { 2744 2745 /* Pipe isn't running, start first */ 2746 return ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2747 } 2748 2749 Static usbd_status 2750 ohci_device_ctrl_start(struct usbd_xfer *xfer) 2751 { 2752 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2753 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2754 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2755 usb_device_request_t *req = &xfer->ux_request; 2756 struct usbd_device *dev __diagused = opipe->pipe.up_dev; 2757 ohci_soft_td_t *setup, *stat, *next, *tail; 2758 ohci_soft_ed_t *sed; 2759 int isread; 2760 int len; 2761 2762 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2763 2764 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2765 2766 if (sc->sc_dying) 2767 return USBD_IOERROR; 2768 2769 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2770 2771 isread = req->bmRequestType & UT_READ; 2772 len = UGETW(req->wLength); 2773 2774 DPRINTF("xfer=%#jx len=%jd, addr=%jd, endpt=%jd", (uintptr_t)xfer, len, 2775 dev->ud_addr, opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress); 2776 DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx", 2777 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2778 UGETW(req->wIndex)); 2779 2780 /* 2781 * Use the pipe "tail" TD as our first and loan our first TD to the 2782 * next transfer 2783 */ 2784 setup = opipe->tail.td; 2785 opipe->tail.td = ox->ox_setup; 2786 ox->ox_setup = setup; 2787 setup->held = &ox->ox_setup; 2788 2789 DPRINTFN(10, "xfer=%#jx new setup=%#jx held at %#jx", (uintptr_t)ox, 2790 (uintptr_t)setup, (uintptr_t)setup->held, 0); 2791 2792 stat = ox->ox_stat; 2793 2794 /* point at sentinel */ 2795 tail = opipe->tail.td; 2796 tail->held = &opipe->tail.td; 2797 sed = opipe->sed; 2798 2799 DPRINTFN(10, "xfer=%#jx new tail=%#jx held at %#jx", (uintptr_t)ox, 2800 (uintptr_t)tail, (uintptr_t)tail->held, 0); 2801 2802 KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->ud_addr, 2803 "address ED %" __PRIuBITS " pipe %d\n", 2804 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->ud_addr); 2805 KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) == 2806 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 2807 "MPL ED %" __PRIuBITS " pipe %d\n", 2808 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), 2809 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 2810 2811 /* next will point to data if len != 0 */ 2812 next = stat; 2813 2814 /* Set up data transaction */ 2815 if (len != 0) { 2816 ohci_soft_td_t *std; 2817 ohci_soft_td_t *end; 2818 2819 next = ox->ox_stds[0]; 2820 ohci_reset_std_chain(sc, xfer, len, isread, next, &end); 2821 2822 end->td.td_nexttd = HTOO32(stat->physaddr); 2823 end->nexttd = stat; 2824 2825 usb_syncmem(&end->dma, end->offs, sizeof(end->td), 2826 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2827 2828 usb_syncmem(&xfer->ux_dmabuf, 0, len, 2829 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2830 std = ox->ox_stds[0]; 2831 /* Start toggle at 1 and then use the carried toggle. */ 2832 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 2833 std->td.td_flags |= HTOO32(OHCI_TD_SET_TOGGLE(OHCI_TD_TOGGLE_1)); 2834 usb_syncmem(&std->dma, 2835 std->offs + offsetof(ohci_td_t, td_flags), 2836 sizeof(std->td.td_flags), 2837 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2838 } 2839 2840 DPRINTFN(8, "setup %#jx data %#jx stat %#jx tail %#jx", 2841 (uintptr_t)setup, 2842 (uintptr_t)(len != 0 ? ox->ox_stds[0] : NULL), (uintptr_t)stat, 2843 (uintptr_t)tail); 2844 KASSERT(opipe->tail.td == tail); 2845 2846 memcpy(KERNADDR(&opipe->ctrl.reqdma, 0), req, sizeof(*req)); 2847 usb_syncmem(&opipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2848 2849 setup->td.td_flags = HTOO32( 2850 OHCI_TD_SET_DP(OHCI_TD_DP_SETUP) | 2851 OHCI_TD_SET_CC(OHCI_TD_NOCC) | 2852 OHCI_TD_SET_TOGGLE(OHCI_TD_TOGGLE_0) | 2853 OHCI_TD_SET_DI(OHCI_TD_NOINTR) 2854 ); 2855 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->ctrl.reqdma, 0)); 2856 setup->td.td_nexttd = HTOO32(next->physaddr); 2857 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof(*req) - 1); 2858 setup->nexttd = next; 2859 setup->len = 0; 2860 setup->xfer = xfer; 2861 setup->flags = 0; 2862 ohci_hash_add_td(sc, setup); 2863 2864 xfer->ux_hcpriv = setup; 2865 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2866 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2867 2868 stat->td.td_flags = HTOO32( 2869 OHCI_TD_SET_DP(isread ? OHCI_TD_DP_OUT : OHCI_TD_DP_IN) | 2870 OHCI_TD_SET_CC(OHCI_TD_NOCC) | 2871 OHCI_TD_SET_TOGGLE(OHCI_TD_TOGGLE_1) | 2872 OHCI_TD_SET_DI(1) 2873 ); 2874 stat->td.td_cbp = 0; 2875 stat->td.td_nexttd = HTOO32(tail->physaddr); 2876 stat->td.td_be = 0; 2877 stat->nexttd = tail; 2878 stat->flags = OHCI_CALL_DONE; 2879 stat->len = 0; 2880 stat->xfer = xfer; 2881 ohci_hash_add_td(sc, stat); 2882 2883 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2884 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2885 2886 memset(&tail->td, 0, sizeof(tail->td)); 2887 tail->nexttd = NULL; 2888 tail->xfer = NULL; 2889 2890 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 2891 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2892 2893 #ifdef OHCI_DEBUG 2894 USBHIST_LOGN(ohcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2895 if (ohcidebug >= 5) { 2896 ohci_dump_ed(sc, sed); 2897 ohci_dump_tds(sc, setup); 2898 } 2899 USBHIST_LOGN(ohcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2900 #endif 2901 2902 /* Insert ED in schedule */ 2903 sed->ed.ed_tailp = HTOO32(tail->physaddr); 2904 usb_syncmem(&sed->dma, 2905 sed->offs + offsetof(ohci_ed_t, ed_tailp), 2906 sizeof(sed->ed.ed_tailp), 2907 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2908 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2909 usbd_xfer_schedule_timeout(xfer); 2910 2911 DPRINTF("done", 0, 0, 0, 0); 2912 2913 xfer->ux_status = USBD_IN_PROGRESS; 2914 2915 return USBD_IN_PROGRESS; 2916 } 2917 2918 /* Abort a device control request. */ 2919 Static void 2920 ohci_device_ctrl_abort(struct usbd_xfer *xfer) 2921 { 2922 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 2923 2924 KASSERT(mutex_owned(&sc->sc_lock)); 2925 2926 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2927 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 2928 usbd_xfer_abort(xfer); 2929 } 2930 2931 /* Close a device control pipe. */ 2932 Static void 2933 ohci_device_ctrl_close(struct usbd_pipe *pipe) 2934 { 2935 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2936 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2937 2938 KASSERT(mutex_owned(&sc->sc_lock)); 2939 2940 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2941 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 2942 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2943 ohci_free_std_locked(sc, opipe->tail.td); 2944 2945 usb_freemem(&opipe->ctrl.reqdma); 2946 } 2947 2948 /************************/ 2949 2950 Static void 2951 ohci_device_clear_toggle(struct usbd_pipe *pipe) 2952 { 2953 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2954 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2955 2956 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2957 } 2958 2959 Static void 2960 ohci_noop(struct usbd_pipe *pipe) 2961 { 2962 } 2963 2964 Static int 2965 ohci_device_bulk_init(struct usbd_xfer *xfer) 2966 { 2967 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2968 int len = xfer->ux_bufsize; 2969 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2970 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2971 int err; 2972 2973 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2974 2975 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2976 2977 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 2978 len, isread, xfer->ux_flags); 2979 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 2980 2981 /* Allocate a chain of new TDs (including a new tail). */ 2982 err = ohci_alloc_std_chain(sc, xfer, len, isread); 2983 if (err) 2984 return err; 2985 2986 return 0; 2987 } 2988 2989 Static void 2990 ohci_device_bulk_fini(struct usbd_xfer *xfer) 2991 { 2992 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2993 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2994 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2995 2996 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2997 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 2998 2999 mutex_enter(&sc->sc_lock); 3000 for (size_t i = 0; i < ox->ox_nstd; i++) { 3001 ohci_soft_td_t *std = ox->ox_stds[i]; 3002 if (std == NULL) 3003 break; 3004 if (std != opipe->tail.td) 3005 ohci_free_std_locked(sc, std); 3006 } 3007 mutex_exit(&sc->sc_lock); 3008 3009 if (ox->ox_nstd) { 3010 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 3011 kmem_free(ox->ox_stds, sz); 3012 } 3013 } 3014 3015 Static usbd_status 3016 ohci_device_bulk_transfer(struct usbd_xfer *xfer) 3017 { 3018 3019 /* Pipe isn't running, start first */ 3020 return ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3021 } 3022 3023 Static usbd_status 3024 ohci_device_bulk_start(struct usbd_xfer *xfer) 3025 { 3026 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3027 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3028 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3029 ohci_soft_td_t *last; 3030 ohci_soft_td_t *data, *tail, *tdp; 3031 ohci_soft_ed_t *sed; 3032 int len, isread, endpt; 3033 3034 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3035 3036 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3037 3038 if (sc->sc_dying) 3039 return USBD_IOERROR; 3040 3041 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3042 3043 len = xfer->ux_length; 3044 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3045 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3046 sed = opipe->sed; 3047 3048 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 3049 len, isread, xfer->ux_flags); 3050 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 3051 3052 /* 3053 * Use the pipe "tail" TD as our first and loan our first TD to the 3054 * next transfer 3055 */ 3056 data = opipe->tail.td; 3057 opipe->tail.td = ox->ox_stds[0]; 3058 ox->ox_stds[0] = data; 3059 data->held = &ox->ox_stds[0]; 3060 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3061 DPRINTFN(10, "xfer=%#jx new data=%#jx held at %#jx", 3062 (uintptr_t)ox, (uintptr_t)data, (uintptr_t)data->held, 0); 3063 3064 /* point at sentinel */ 3065 tail = opipe->tail.td; 3066 memset(&tail->td, 0, sizeof(tail->td)); 3067 tail->held = &opipe->tail.td; 3068 tail->nexttd = NULL; 3069 tail->xfer = NULL; 3070 DPRINTFN(10, "xfer=%#jx new tail=%#jx held at %#ux", 3071 (uintptr_t)ox, (uintptr_t)tail, (uintptr_t)tail->held, 0); 3072 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3073 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3074 xfer->ux_hcpriv = data; 3075 3076 DPRINTFN(8, "xfer %#jx data %#jx tail %#jx", (uintptr_t)xfer, 3077 (uintptr_t)ox->ox_stds[0], (uintptr_t)tail, 0); 3078 KASSERT(opipe->tail.td == tail); 3079 3080 /* We want interrupt at the end of the transfer. */ 3081 last->td.td_flags &= HTOO32(~OHCI_TD_DI_MASK); 3082 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3083 last->td.td_nexttd = HTOO32(tail->physaddr); 3084 last->nexttd = tail; 3085 last->flags |= OHCI_CALL_DONE; 3086 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3087 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3088 3089 DPRINTFN(4, "ed_flags=0x%08jx td_flags=0x%08jx " 3090 "td_cbp=0x%08jx td_be=0x%08jx", 3091 (int)O32TOH(sed->ed.ed_flags), 3092 (int)O32TOH(data->td.td_flags), 3093 (int)O32TOH(data->td.td_cbp), 3094 (int)O32TOH(data->td.td_be)); 3095 3096 #ifdef OHCI_DEBUG 3097 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3098 if (ohcidebug >= 5) { 3099 ohci_dump_ed(sc, sed); 3100 ohci_dump_tds(sc, data); 3101 } 3102 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3103 #endif 3104 3105 /* Insert ED in schedule */ 3106 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3107 KASSERT(tdp->xfer == xfer); 3108 } 3109 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3110 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3111 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3112 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3113 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3114 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3115 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3116 usbd_xfer_schedule_timeout(xfer); 3117 xfer->ux_status = USBD_IN_PROGRESS; 3118 3119 return USBD_IN_PROGRESS; 3120 } 3121 3122 Static void 3123 ohci_device_bulk_abort(struct usbd_xfer *xfer) 3124 { 3125 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3126 3127 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3128 3129 KASSERT(mutex_owned(&sc->sc_lock)); 3130 3131 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3132 usbd_xfer_abort(xfer); 3133 } 3134 3135 /* 3136 * Close a device bulk pipe. 3137 */ 3138 Static void 3139 ohci_device_bulk_close(struct usbd_pipe *pipe) 3140 { 3141 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3142 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3143 3144 KASSERT(mutex_owned(&sc->sc_lock)); 3145 3146 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3147 3148 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3149 ohci_close_pipe(pipe, sc->sc_bulk_head); 3150 ohci_free_std_locked(sc, opipe->tail.td); 3151 } 3152 3153 /************************/ 3154 3155 Static int 3156 ohci_device_intr_init(struct usbd_xfer *xfer) 3157 { 3158 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3159 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3160 int len = xfer->ux_bufsize; 3161 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3162 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3163 int err; 3164 3165 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3166 3167 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3168 KASSERT(len != 0); 3169 3170 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 3171 len, isread, xfer->ux_flags); 3172 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 3173 3174 ox->ox_nstd = 0; 3175 3176 err = ohci_alloc_std_chain(sc, xfer, len, isread); 3177 if (err) { 3178 return err; 3179 } 3180 3181 return 0; 3182 } 3183 3184 Static void 3185 ohci_device_intr_fini(struct usbd_xfer *xfer) 3186 { 3187 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3188 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3189 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3190 3191 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3192 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 3193 3194 mutex_enter(&sc->sc_lock); 3195 for (size_t i = 0; i < ox->ox_nstd; i++) { 3196 ohci_soft_td_t *std = ox->ox_stds[i]; 3197 if (std != NULL) 3198 break; 3199 if (std != opipe->tail.td) 3200 ohci_free_std_locked(sc, std); 3201 } 3202 mutex_exit(&sc->sc_lock); 3203 3204 if (ox->ox_nstd) { 3205 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 3206 kmem_free(ox->ox_stds, sz); 3207 } 3208 } 3209 3210 Static usbd_status 3211 ohci_device_intr_transfer(struct usbd_xfer *xfer) 3212 { 3213 3214 /* Pipe isn't running, start first */ 3215 return ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3216 } 3217 3218 Static usbd_status 3219 ohci_device_intr_start(struct usbd_xfer *xfer) 3220 { 3221 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3222 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3223 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3224 ohci_soft_ed_t *sed = opipe->sed; 3225 ohci_soft_td_t *data, *last, *tail; 3226 int len, isread, endpt; 3227 3228 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3229 3230 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3231 3232 if (sc->sc_dying) 3233 return USBD_IOERROR; 3234 3235 DPRINTFN(3, "xfer=%#jx len=%jd flags=%jd priv=%#jx", (uintptr_t)xfer, 3236 xfer->ux_length, xfer->ux_flags, (uintptr_t)xfer->ux_priv); 3237 3238 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3239 3240 len = xfer->ux_length; 3241 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3242 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3243 3244 /* 3245 * Use the pipe "tail" TD as our first and loan our first TD to the 3246 * next transfer. 3247 */ 3248 data = opipe->tail.td; 3249 opipe->tail.td = ox->ox_stds[0]; 3250 ox->ox_stds[0] = data; 3251 data->held = &ox->ox_stds[0]; 3252 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3253 DPRINTFN(10, "xfer=%#jx new data=%#jx held at %#jx", 3254 (uintptr_t)ox, (uintptr_t)data, (uintptr_t)data->held, 0); 3255 3256 /* point at sentinel */ 3257 tail = opipe->tail.td; 3258 memset(&tail->td, 0, sizeof(tail->td)); 3259 tail->held = &opipe->tail.td; 3260 tail->nexttd = NULL; 3261 tail->xfer = NULL; 3262 DPRINTFN(10, "xfer=%#jx new tail=%#jx held at %#jx", 3263 (uintptr_t)ox, (uintptr_t)tail, (uintptr_t)tail->held, 0); 3264 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3265 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3266 xfer->ux_hcpriv = data; 3267 3268 DPRINTFN(8, "data %#jx tail %#jx", (uintptr_t)ox->ox_stds[0], 3269 (uintptr_t)tail, 0, 0); 3270 KASSERT(opipe->tail.td == tail); 3271 3272 /* We want interrupt at the end of the transfer. */ 3273 last->td.td_flags &= HTOO32(~OHCI_TD_DI_MASK); 3274 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3275 3276 last->td.td_nexttd = HTOO32(tail->physaddr); 3277 last->nexttd = tail; 3278 last->flags |= OHCI_CALL_DONE; 3279 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3280 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3281 3282 #ifdef OHCI_DEBUG 3283 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3284 if (ohcidebug >= 5) { 3285 ohci_dump_ed(sc, sed); 3286 ohci_dump_tds(sc, data); 3287 } 3288 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3289 #endif 3290 3291 /* Insert ED in schedule */ 3292 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3293 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3294 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3295 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3296 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3297 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3298 3299 xfer->ux_status = USBD_IN_PROGRESS; 3300 3301 return USBD_IN_PROGRESS; 3302 } 3303 3304 /* Abort a device interrupt request. */ 3305 Static void 3306 ohci_device_intr_abort(struct usbd_xfer *xfer) 3307 { 3308 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3309 3310 KASSERT(mutex_owned(&sc->sc_lock)); 3311 3312 usbd_xfer_abort(xfer); 3313 } 3314 3315 /* Close a device interrupt pipe. */ 3316 Static void 3317 ohci_device_intr_close(struct usbd_pipe *pipe) 3318 { 3319 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3320 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3321 int nslots = opipe->intr.nslots; 3322 int pos = opipe->intr.pos; 3323 int j; 3324 ohci_soft_ed_t *p, *sed = opipe->sed; 3325 3326 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3327 3328 KASSERT(mutex_owned(&sc->sc_lock)); 3329 3330 DPRINTFN(1, "pipe=%#jx nslots=%jd pos=%jd", (uintptr_t)pipe, nslots, 3331 pos, 0); 3332 usb_syncmem(&sed->dma, sed->offs, 3333 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3334 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3335 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3336 sizeof(sed->ed.ed_flags), 3337 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3338 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3339 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3340 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3341 3342 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3343 continue; 3344 KASSERT(p); 3345 p->next = sed->next; 3346 p->ed.ed_nexted = sed->ed.ed_nexted; 3347 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3348 sizeof(p->ed.ed_nexted), 3349 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3350 3351 for (j = 0; j < nslots; j++) 3352 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3353 3354 ohci_free_std_locked(sc, opipe->tail.td); 3355 ohci_free_sed_locked(sc, opipe->sed); 3356 } 3357 3358 Static usbd_status 3359 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3360 { 3361 int i, j, best; 3362 u_int npoll, slow, shigh, nslots; 3363 u_int bestbw, bw; 3364 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3365 3366 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3367 3368 DPRINTFN(2, "pipe=%#jx", (uintptr_t)opipe, 0, 0, 0); 3369 if (ival == 0) { 3370 printf("ohci_setintr: 0 interval\n"); 3371 return USBD_INVAL; 3372 } 3373 3374 npoll = OHCI_NO_INTRS; 3375 while (npoll > ival) 3376 npoll /= 2; 3377 DPRINTFN(2, "ival=%jd npoll=%jd", ival, npoll, 0, 0); 3378 3379 /* 3380 * We now know which level in the tree the ED must go into. 3381 * Figure out which slot has most bandwidth left over. 3382 * Slots to examine: 3383 * npoll 3384 * 1 0 3385 * 2 1 2 3386 * 4 3 4 5 6 3387 * 8 7 8 9 10 11 12 13 14 3388 * N (N-1) .. (N-1+N-1) 3389 */ 3390 slow = npoll-1; 3391 shigh = slow + npoll; 3392 nslots = OHCI_NO_INTRS / npoll; 3393 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3394 bw = 0; 3395 for (j = 0; j < nslots; j++) 3396 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3397 if (bw < bestbw) { 3398 best = i; 3399 bestbw = bw; 3400 } 3401 } 3402 DPRINTFN(2, "best=%jd(%jd..%jd) bestbw=%jd", best, slow, shigh, bestbw); 3403 3404 mutex_enter(&sc->sc_lock); 3405 hsed = sc->sc_eds[best]; 3406 sed->next = hsed->next; 3407 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3408 sizeof(hsed->ed.ed_flags), 3409 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3410 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3411 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3412 sizeof(sed->ed.ed_flags), 3413 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3414 hsed->next = sed; 3415 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3416 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3417 sizeof(hsed->ed.ed_flags), 3418 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3419 mutex_exit(&sc->sc_lock); 3420 3421 for (j = 0; j < nslots; j++) 3422 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3423 opipe->intr.nslots = nslots; 3424 opipe->intr.pos = best; 3425 3426 DPRINTFN(5, "returns %#jx", (uintptr_t)opipe, 0, 0, 0); 3427 return USBD_NORMAL_COMPLETION; 3428 } 3429 3430 /***********************/ 3431 3432 Static int 3433 ohci_device_isoc_init(struct usbd_xfer *xfer) 3434 { 3435 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3436 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3437 ohci_soft_itd_t *sitd; 3438 size_t i; 3439 int err; 3440 3441 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3442 3443 DPRINTFN(1, "xfer %#jx len %jd flags %jd", (uintptr_t)xfer, 3444 xfer->ux_length, xfer->ux_flags, 0); 3445 3446 const size_t nfsitd = howmany(xfer->ux_nframes, OHCI_ITD_NOFFSET); 3447 const size_t nbsitd = xfer->ux_bufsize / OHCI_PAGE_SIZE; 3448 const size_t nsitd = MAX(nfsitd, nbsitd) + 1; 3449 3450 ox->ox_sitds = kmem_zalloc(sizeof(ohci_soft_itd_t *) * nsitd, 3451 KM_SLEEP); 3452 ox->ox_nsitd = nsitd; 3453 3454 for (i = 0; i < nsitd; i++) { 3455 /* Allocate next ITD */ 3456 sitd = ohci_alloc_sitd(sc); 3457 if (sitd == NULL) { 3458 err = ENOMEM; 3459 goto fail; 3460 } 3461 ox->ox_sitds[i] = sitd; 3462 sitd->held = &ox->ox_sitds[i]; 3463 sitd->xfer = xfer; 3464 sitd->flags = 0; 3465 // DPRINTFN(10, "xfer=%#jx new tail=%#jx held at %#jx", 3466 // (uintptr_t)ox, (uintptr_t)tail, (uintptr_t)tail->held, 0); 3467 } 3468 3469 return 0; 3470 fail: 3471 for (; i > 0;) { 3472 ohci_free_sitd(sc, ox->ox_sitds[--i]); 3473 } 3474 return err; 3475 } 3476 3477 Static void 3478 ohci_device_isoc_fini(struct usbd_xfer *xfer) 3479 { 3480 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3481 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3482 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3483 3484 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3485 3486 mutex_enter(&sc->sc_lock); 3487 for (size_t i = 0; i < ox->ox_nsitd; i++) { 3488 if (ox->ox_sitds[i] != opipe->tail.itd) { 3489 ohci_free_sitd_locked(sc, ox->ox_sitds[i]); 3490 } 3491 } 3492 mutex_exit(&sc->sc_lock); 3493 3494 if (ox->ox_nsitd) { 3495 const size_t sz = sizeof(ohci_soft_itd_t *) * ox->ox_nsitd; 3496 kmem_free(ox->ox_sitds, sz); 3497 } 3498 } 3499 3500 3501 usbd_status 3502 ohci_device_isoc_transfer(struct usbd_xfer *xfer) 3503 { 3504 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3505 3506 DPRINTFN(5, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3507 3508 /* insert into schedule, */ 3509 ohci_device_isoc_enter(xfer); 3510 3511 /* and start if the pipe wasn't running */ 3512 return USBD_IN_PROGRESS; 3513 } 3514 3515 void 3516 ohci_device_isoc_enter(struct usbd_xfer *xfer) 3517 { 3518 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3519 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3520 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3521 ohci_soft_ed_t *sed = opipe->sed; 3522 ohci_soft_itd_t *sitd, *nsitd, *tail; 3523 ohci_physaddr_t buf, offs, bp0, bp1; 3524 int i, ncur, nframes; 3525 size_t boff, frlen; 3526 3527 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3528 DPRINTFN(5, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3529 3530 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3531 3532 if (sc->sc_dying) 3533 return; 3534 3535 struct isoc *isoc = &opipe->isoc; 3536 3537 DPRINTFN(1, "used=%jd next=%jd xfer=%#jx nframes=%jd", 3538 isoc->inuse, isoc->next, (uintptr_t)xfer, xfer->ux_nframes); 3539 3540 int isread = 3541 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 3542 3543 if (xfer->ux_length) 3544 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3545 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3546 3547 if (isoc->next == -1) { 3548 /* Not in use yet, schedule it a few frames ahead. */ 3549 usb_syncmem(&sc->sc_hccadma, 3550 offsetof(struct ohci_hcca, hcca_frame_number), 3551 sizeof(sc->sc_hcca->hcca_frame_number), 3552 BUS_DMASYNC_POSTREAD); 3553 isoc->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3554 DPRINTFN(2,"start next=%jd", isoc->next, 0, 0, 0); 3555 } 3556 3557 sitd = opipe->tail.itd; 3558 opipe->tail.itd = ox->ox_sitds[0]; 3559 ox->ox_sitds[0] = sitd; 3560 sitd->held = &ox->ox_sitds[0]; 3561 3562 boff = 0; 3563 buf = DMAADDR(&xfer->ux_dmabuf, 0); 3564 bp0 = bp1 = OHCI_PAGE(buf); 3565 offs = OHCI_PAGE_OFFSET(buf); 3566 3567 ohci_physaddr_t end = bp0; /* XXX stupid GCC */ 3568 3569 nframes = xfer->ux_nframes; 3570 xfer->ux_hcpriv = sitd; 3571 size_t j = 1; 3572 for (i = ncur = 0; i < nframes; i++, ncur++) { 3573 frlen = xfer->ux_frlengths[i]; 3574 3575 DPRINTFN(1, "frame=%jd ux_frlengths[%jd]=%jd", i, i, 3576 xfer->ux_frlengths[i], 0); 3577 /* 3578 * XXXNH: The loop assumes this is never true, because 3579 * incrementing 'i' assumes all the ux_frlengths[i] is covered. 3580 */ 3581 if (frlen > 2 * OHCI_PAGE_SIZE - offs) 3582 frlen = 2 * OHCI_PAGE_SIZE - offs; 3583 3584 boff += frlen; 3585 buf = DMAADDR(&xfer->ux_dmabuf, boff); 3586 ohci_physaddr_t noffs = OHCI_PAGE_OFFSET(buf); 3587 3588 ohci_physaddr_t nend = DMAADDR(&xfer->ux_dmabuf, boff - 1); 3589 const ohci_physaddr_t nep = OHCI_PAGE(nend); 3590 3591 /* Note the first page crossing in bp1 */ 3592 if (bp0 == bp1 && bp1 != nep) 3593 bp1 = nep; 3594 3595 DPRINTFN(1, "ncur=%jd bp0=%#jx bp1=%#jx nend=%#jx", 3596 ncur, bp0, bp1, nend); 3597 3598 /* all offsets used or too many page crossings */ 3599 if (ncur == OHCI_ITD_NOFFSET || (bp0 != bp1 && bp1 != nep)) { 3600 /* Allocate next ITD */ 3601 nsitd = ox->ox_sitds[j++]; 3602 KASSERT(nsitd != NULL); 3603 KASSERT(j < ox->ox_nsitd); 3604 3605 /* Fill current ITD */ 3606 sitd->itd.itd_flags = HTOO32( 3607 OHCI_ITD_SET_CC(OHCI_ITD_NOCC) | 3608 OHCI_ITD_SET_SF(isoc->next) | 3609 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3610 OHCI_ITD_SET_FC(ncur) 3611 ); 3612 sitd->itd.itd_bp0 = HTOO32(bp0); 3613 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3614 sitd->itd.itd_be = HTOO32(end); 3615 sitd->nextitd = nsitd; 3616 sitd->xfer = xfer; 3617 sitd->flags = 0; 3618 #ifdef DIAGNOSTIC 3619 sitd->isdone = false; 3620 #endif 3621 ohci_hash_add_itd(sc, sitd); 3622 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3623 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3624 3625 sitd = nsitd; 3626 isoc->next = isoc->next + ncur; 3627 bp0 = bp1 = OHCI_PAGE(buf); 3628 ncur = 0; 3629 } 3630 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3631 end = nend; 3632 offs = noffs; 3633 } 3634 KASSERT(j <= ox->ox_nsitd); 3635 3636 /* point at sentinel */ 3637 tail = opipe->tail.itd; 3638 memset(&tail->itd, 0, sizeof(tail->itd)); 3639 tail->held = &opipe->tail.itd; 3640 tail->nextitd = NULL; 3641 tail->xfer = NULL; 3642 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->itd), 3643 BUS_DMASYNC_PREWRITE); 3644 3645 /* Fixup last used ITD */ 3646 sitd->itd.itd_flags = HTOO32( 3647 OHCI_ITD_SET_CC(OHCI_ITD_NOCC) | 3648 OHCI_ITD_SET_SF(isoc->next) | 3649 OHCI_ITD_SET_DI(0) | 3650 OHCI_ITD_SET_FC(ncur) 3651 ); 3652 sitd->itd.itd_bp0 = HTOO32(bp0); 3653 sitd->itd.itd_nextitd = HTOO32(tail->physaddr); 3654 sitd->itd.itd_be = HTOO32(end); 3655 sitd->nextitd = tail; 3656 sitd->xfer = xfer; 3657 sitd->flags = OHCI_CALL_DONE; 3658 #ifdef DIAGNOSTIC 3659 sitd->isdone = false; 3660 #endif 3661 ohci_hash_add_itd(sc, sitd); 3662 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3663 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3664 3665 isoc->next = isoc->next + ncur; 3666 isoc->inuse += nframes; 3667 3668 /* XXX pretend we did it all */ 3669 xfer->ux_actlen = offs; 3670 xfer->ux_status = USBD_IN_PROGRESS; 3671 3672 #ifdef OHCI_DEBUG 3673 if (ohcidebug >= 5) { 3674 usb_syncmem(&sc->sc_hccadma, 3675 offsetof(struct ohci_hcca, hcca_frame_number), 3676 sizeof(sc->sc_hcca->hcca_frame_number), 3677 BUS_DMASYNC_POSTREAD); 3678 DPRINTF("frame=%jd", O32TOH(sc->sc_hcca->hcca_frame_number), 3679 0, 0, 0); 3680 ohci_dump_itds(sc, xfer->ux_hcpriv); 3681 ohci_dump_ed(sc, sed); 3682 } 3683 #endif 3684 3685 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3686 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3687 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3688 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3689 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3690 sizeof(sed->ed.ed_flags), 3691 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3692 } 3693 3694 void 3695 ohci_device_isoc_abort(struct usbd_xfer *xfer) 3696 { 3697 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3698 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3699 ohci_soft_ed_t *sed; 3700 ohci_soft_itd_t *sitd; 3701 3702 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3703 DPRINTFN(1, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3704 3705 KASSERT(mutex_owned(&sc->sc_lock)); 3706 3707 /* Transfer is already done. */ 3708 if (xfer->ux_status != USBD_NOT_STARTED && 3709 xfer->ux_status != USBD_IN_PROGRESS) { 3710 printf("ohci_device_isoc_abort: early return\n"); 3711 goto done; 3712 } 3713 3714 /* Give xfer the requested abort code. */ 3715 xfer->ux_status = USBD_CANCELLED; 3716 3717 sed = opipe->sed; 3718 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3719 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3720 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3721 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3722 sizeof(sed->ed.ed_flags), 3723 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3724 3725 sitd = xfer->ux_hcpriv; 3726 KASSERT(sitd); 3727 3728 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3729 3730 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3731 ohci_hash_rem_itd(sc, sitd); 3732 #ifdef DIAGNOSTIC 3733 DPRINTFN(1, "abort sets done sitd=%#jx", (uintptr_t)sitd, 3734 0, 0, 0); 3735 sitd->isdone = true; 3736 #endif 3737 } 3738 3739 /* Run callback. */ 3740 usb_transfer_complete(xfer); 3741 3742 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3743 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3744 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3745 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3746 3747 done: 3748 KASSERT(mutex_owned(&sc->sc_lock)); 3749 } 3750 3751 void 3752 ohci_device_isoc_done(struct usbd_xfer *xfer) 3753 { 3754 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3755 DPRINTFN(1, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3756 3757 int isread = 3758 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 3759 3760 DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 3761 0, 0); 3762 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3763 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3764 } 3765 3766 usbd_status 3767 ohci_setup_isoc(struct usbd_pipe *pipe) 3768 { 3769 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3770 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3771 struct isoc *isoc = &opipe->isoc; 3772 3773 isoc->next = -1; 3774 isoc->inuse = 0; 3775 3776 mutex_enter(&sc->sc_lock); 3777 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3778 mutex_exit(&sc->sc_lock); 3779 3780 return USBD_NORMAL_COMPLETION; 3781 } 3782 3783 void 3784 ohci_device_isoc_close(struct usbd_pipe *pipe) 3785 { 3786 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3787 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3788 3789 KASSERT(mutex_owned(&sc->sc_lock)); 3790 3791 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3792 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3793 ohci_close_pipe(pipe, sc->sc_isoc_head); 3794 #ifdef DIAGNOSTIC 3795 opipe->tail.itd->isdone = true; 3796 #endif 3797 ohci_free_sitd_locked(sc, opipe->tail.itd); 3798 } 3799
Indexes created Tue Sep 23 07:09:52 GMT 2025