ohci.c revision 1.35 1 /* $NetBSD: ohci.c,v 1.35 1999/08/16 20:24:33 augustss Exp $ */
2
3 /*
4 * Copyright (c) 1998 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Lennart Augustsson (augustss (at) carlstedt.se) at
9 * Carlstedt Research & Technology.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the NetBSD
22 * Foundation, Inc. and its contributors.
23 * 4. Neither the name of The NetBSD Foundation nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39
40 /*
41 * USB Open Host Controller driver.
42 *
43 * OHCI spec: ftp://ftp.compaq.com/pub/supportinformation/papers/hcir1_0a.exe
44 * USB spec: http://www.usb.org/developers/data/usb11.pdf
45 */
46
47 #include <sys/param.h>
48 #include <sys/systm.h>
49 #include <sys/kernel.h>
50 #include <sys/malloc.h>
51 #if defined(__NetBSD__)
52 #include <sys/device.h>
53 #elif defined(__FreeBSD__)
54 #include <sys/module.h>
55 #include <sys/bus.h>
56 #endif
57 #include <sys/proc.h>
58 #include <sys/queue.h>
59 #include <sys/select.h>
60
61 #include <machine/bus.h>
62 #include <machine/endian.h>
63
64 #include <dev/usb/usb.h>
65 #include <dev/usb/usbdi.h>
66 #include <dev/usb/usbdivar.h>
67 #include <dev/usb/usb_quirks.h>
68 #include <dev/usb/usb_mem.h>
69
70 #include <dev/usb/ohcireg.h>
71 #include <dev/usb/ohcivar.h>
72
73 #if defined(__FreeBSD__)
74 #include <machine/clock.h>
75
76 #define delay(d) DELAY(d)
77
78 #endif
79
80 /*
81 * The OHCI controller is little endian, so on big endian machines
82 * the data strored in memory needs to be swapped.
83 */
84 #if BYTE_ORDER == BIG_ENDIAN
85 #define LE(x) (bswap32(x))
86 #else
87 #define LE(x) (x)
88 #endif
89
90 struct ohci_pipe;
91
92 ohci_soft_ed_t *ohci_alloc_sed __P((ohci_softc_t *));
93 void ohci_free_sed __P((ohci_softc_t *, ohci_soft_ed_t *));
94
95 ohci_soft_td_t *ohci_alloc_std __P((ohci_softc_t *));
96 void ohci_free_std __P((ohci_softc_t *, ohci_soft_td_t *));
97
98 void ohci_power __P((int, void *));
99 usbd_status ohci_open __P((usbd_pipe_handle));
100 void ohci_poll __P((struct usbd_bus *));
101 void ohci_waitintr __P((ohci_softc_t *, usbd_request_handle));
102 void ohci_rhsc __P((ohci_softc_t *, usbd_request_handle));
103 void ohci_process_done __P((ohci_softc_t *, ohci_physaddr_t));
104 void ohci_idone __P((ohci_softc_t *, usbd_request_handle));
105 void ohci_done __P((ohci_softc_t *, usbd_request_handle));
106 void ohci_ctrl_done __P((ohci_softc_t *, usbd_request_handle));
107 void ohci_intr_done __P((ohci_softc_t *, usbd_request_handle));
108 void ohci_bulk_done __P((ohci_softc_t *, usbd_request_handle));
109
110 usbd_status ohci_device_request __P((usbd_request_handle reqh));
111 void ohci_add_ed __P((ohci_soft_ed_t *, ohci_soft_ed_t *));
112 void ohci_rem_ed __P((ohci_soft_ed_t *, ohci_soft_ed_t *));
113 void ohci_hash_add_td __P((ohci_softc_t *, ohci_soft_td_t *));
114 void ohci_hash_rem_td __P((ohci_softc_t *, ohci_soft_td_t *));
115 ohci_soft_td_t *ohci_hash_find_td __P((ohci_softc_t *, ohci_physaddr_t));
116
117 usbd_status ohci_root_ctrl_transfer __P((usbd_request_handle));
118 usbd_status ohci_root_ctrl_start __P((usbd_request_handle));
119 void ohci_root_ctrl_abort __P((usbd_request_handle));
120 void ohci_root_ctrl_close __P((usbd_pipe_handle));
121
122 usbd_status ohci_root_intr_transfer __P((usbd_request_handle));
123 usbd_status ohci_root_intr_start __P((usbd_request_handle));
124 void ohci_root_intr_abort __P((usbd_request_handle));
125 void ohci_root_intr_close __P((usbd_pipe_handle));
126
127 usbd_status ohci_device_ctrl_transfer __P((usbd_request_handle));
128 usbd_status ohci_device_ctrl_start __P((usbd_request_handle));
129 void ohci_device_ctrl_abort __P((usbd_request_handle));
130 void ohci_device_ctrl_close __P((usbd_pipe_handle));
131
132 usbd_status ohci_device_bulk_transfer __P((usbd_request_handle));
133 usbd_status ohci_device_bulk_start __P((usbd_request_handle));
134 void ohci_device_bulk_abort __P((usbd_request_handle));
135 void ohci_device_bulk_close __P((usbd_pipe_handle));
136
137 usbd_status ohci_device_intr_transfer __P((usbd_request_handle));
138 usbd_status ohci_device_intr_start __P((usbd_request_handle));
139 void ohci_device_intr_abort __P((usbd_request_handle));
140 void ohci_device_intr_close __P((usbd_pipe_handle));
141 usbd_status ohci_device_setintr __P((ohci_softc_t *sc,
142 struct ohci_pipe *pipe, int ival));
143
144 int ohci_str __P((usb_string_descriptor_t *, int, char *));
145
146 void ohci_timeout __P((void *));
147 void ohci_rhsc_able __P((ohci_softc_t *, int));
148
149 void ohci_close_pipe __P((usbd_pipe_handle pipe,
150 ohci_soft_ed_t *head));
151 void ohci_abort_request __P((usbd_request_handle reqh));
152
153 #ifdef USB_DEBUG
154 ohci_softc_t *thesc;
155 void ohci_dumpregs __P((ohci_softc_t *));
156 void ohci_dump_tds __P((ohci_soft_td_t *));
157 void ohci_dump_td __P((ohci_soft_td_t *));
158 void ohci_dump_ed __P((ohci_soft_ed_t *));
159 #endif
160
161 #if defined(__NetBSD__)
162 #define OWRITE4(sc, r, x) bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x))
163 #define OREAD4(sc, r) bus_space_read_4((sc)->iot, (sc)->ioh, (r))
164 #define OREAD2(sc, r) bus_space_read_2((sc)->iot, (sc)->ioh, (r))
165 #elif defined(__FreeBSD__)
166 #define OWRITE4(sc, r, x) (*(u_int32_t *) ((sc)->sc_iobase + (r)) = (x))
167 #define OREAD4(sc, r) (*(u_int32_t *) ((sc)->sc_iobase + (r)))
168 #define OREAD2(sc, r) (*(u_int16_t *) ((sc)->sc_iobase + (r)))
169 #endif
170
171 /* Reverse the bits in a value 0 .. 31 */
172 static u_int8_t revbits[OHCI_NO_INTRS] =
173 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c,
174 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e,
175 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d,
176 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f };
177
178 struct ohci_pipe {
179 struct usbd_pipe pipe;
180 ohci_soft_ed_t *sed;
181 ohci_soft_td_t *tail;
182 /* Info needed for different pipe kinds. */
183 union {
184 /* Control pipe */
185 struct {
186 usb_dma_t datadma;
187 usb_dma_t reqdma;
188 u_int length;
189 ohci_soft_td_t *setup, *xfer, *stat;
190 } ctl;
191 /* Interrupt pipe */
192 struct {
193 usb_dma_t datadma;
194 int nslots;
195 int pos;
196 } intr;
197 /* Bulk pipe */
198 struct {
199 usb_dma_t datadma;
200 u_int length;
201 int isread;
202 } bulk;
203 } u;
204 };
205
206 #define OHCI_INTR_ENDPT 1
207
208 struct usbd_methods ohci_root_ctrl_methods = {
209 ohci_root_ctrl_transfer,
210 ohci_root_ctrl_start,
211 ohci_root_ctrl_abort,
212 ohci_root_ctrl_close,
213 0,
214 };
215
216 struct usbd_methods ohci_root_intr_methods = {
217 ohci_root_intr_transfer,
218 ohci_root_intr_start,
219 ohci_root_intr_abort,
220 ohci_root_intr_close,
221 0,
222 };
223
224 struct usbd_methods ohci_device_ctrl_methods = {
225 ohci_device_ctrl_transfer,
226 ohci_device_ctrl_start,
227 ohci_device_ctrl_abort,
228 ohci_device_ctrl_close,
229 0,
230 };
231
232 struct usbd_methods ohci_device_intr_methods = {
233 ohci_device_intr_transfer,
234 ohci_device_intr_start,
235 ohci_device_intr_abort,
236 ohci_device_intr_close,
237 };
238
239 struct usbd_methods ohci_device_bulk_methods = {
240 ohci_device_bulk_transfer,
241 ohci_device_bulk_start,
242 ohci_device_bulk_abort,
243 ohci_device_bulk_close,
244 0,
245 };
246
247 ohci_soft_ed_t *
248 ohci_alloc_sed(sc)
249 ohci_softc_t *sc;
250 {
251 ohci_soft_ed_t *sed;
252 usbd_status r;
253 int i, offs;
254 usb_dma_t dma;
255
256 if (!sc->sc_freeeds) {
257 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n"));
258 sed = malloc(sizeof(ohci_soft_ed_t) * OHCI_ED_CHUNK,
259 M_USBHC, M_NOWAIT);
260 if (!sed)
261 return 0;
262 r = usb_allocmem(sc->sc_dmatag, OHCI_ED_SIZE * OHCI_ED_CHUNK,
263 OHCI_ED_ALIGN, &dma);
264 if (r != USBD_NORMAL_COMPLETION) {
265 free(sed, M_USBHC);
266 return 0;
267 }
268 for(i = 0; i < OHCI_ED_CHUNK; i++, sed++) {
269 offs = i * OHCI_ED_SIZE;
270 sed->physaddr = DMAADDR(&dma) + offs;
271 sed->ed = (ohci_ed_t *)
272 ((char *)KERNADDR(&dma) + offs);
273 sed->next = sc->sc_freeeds;
274 sc->sc_freeeds = sed;
275 }
276 }
277 sed = sc->sc_freeeds;
278 sc->sc_freeeds = sed->next;
279 memset(sed->ed, 0, OHCI_ED_SIZE);
280 sed->next = 0;
281 return sed;
282 }
283
284 void
285 ohci_free_sed(sc, sed)
286 ohci_softc_t *sc;
287 ohci_soft_ed_t *sed;
288 {
289 sed->next = sc->sc_freeeds;
290 sc->sc_freeeds = sed;
291 }
292
293 ohci_soft_td_t *
294 ohci_alloc_std(sc)
295 ohci_softc_t *sc;
296 {
297 ohci_soft_td_t *std;
298 usbd_status r;
299 int i, offs;
300 usb_dma_t dma;
301
302 if (!sc->sc_freetds) {
303 DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n"));
304 std = malloc(sizeof(ohci_soft_td_t) * OHCI_TD_CHUNK,
305 M_USBHC, M_NOWAIT);
306 if (!std)
307 return 0;
308 r = usb_allocmem(sc->sc_dmatag, OHCI_TD_SIZE * OHCI_TD_CHUNK,
309 OHCI_TD_ALIGN, &dma);
310 if (r != USBD_NORMAL_COMPLETION) {
311 free(std, M_USBHC);
312 return 0;
313 }
314 for(i = 0; i < OHCI_TD_CHUNK; i++, std++) {
315 offs = i * OHCI_TD_SIZE;
316 std->physaddr = DMAADDR(&dma) + offs;
317 std->td = (ohci_td_t *)
318 ((char *)KERNADDR(&dma) + offs);
319 std->nexttd = sc->sc_freetds;
320 sc->sc_freetds = std;
321 }
322 }
323 std = sc->sc_freetds;
324 sc->sc_freetds = std->nexttd;
325 memset(std->td, 0, OHCI_TD_SIZE);
326 std->nexttd = 0;
327 return (std);
328 }
329
330 void
331 ohci_free_std(sc, std)
332 ohci_softc_t *sc;
333 ohci_soft_td_t *std;
334 {
335 std->nexttd = sc->sc_freetds;
336 sc->sc_freetds = std;
337 }
338
339 usbd_status
340 ohci_init(sc)
341 ohci_softc_t *sc;
342 {
343 ohci_soft_ed_t *sed, *psed;
344 usbd_status r;
345 int rev;
346 int i;
347 u_int32_t s, ctl, ival, hcr, fm, per;
348
349 DPRINTF(("ohci_init: start\n"));
350 rev = OREAD4(sc, OHCI_REVISION);
351 printf("%s: OHCI version %d.%d%s\n", USBDEVNAME(sc->sc_bus.bdev),
352 OHCI_REV_HI(rev), OHCI_REV_LO(rev),
353 OHCI_REV_LEGACY(rev) ? ", legacy support" : "");
354 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) {
355 printf("%s: unsupported OHCI revision\n",
356 USBDEVNAME(sc->sc_bus.bdev));
357 return (USBD_INVAL);
358 }
359
360 for (i = 0; i < OHCI_HASH_SIZE; i++)
361 LIST_INIT(&sc->sc_hash_tds[i]);
362
363 /* Allocate the HCCA area. */
364 r = usb_allocmem(sc->sc_dmatag, OHCI_HCCA_SIZE,
365 OHCI_HCCA_ALIGN, &sc->sc_hccadma);
366 if (r != USBD_NORMAL_COMPLETION)
367 return (r);
368 sc->sc_hcca = (struct ohci_hcca *)KERNADDR(&sc->sc_hccadma);
369 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE);
370
371 sc->sc_eintrs = OHCI_NORMAL_INTRS;
372
373 sc->sc_ctrl_head = ohci_alloc_sed(sc);
374 if (!sc->sc_ctrl_head) {
375 r = USBD_NOMEM;
376 goto bad1;
377 }
378 sc->sc_ctrl_head->ed->ed_flags |= LE(OHCI_ED_SKIP);
379
380 sc->sc_bulk_head = ohci_alloc_sed(sc);
381 if (!sc->sc_bulk_head) {
382 r = USBD_NOMEM;
383 goto bad2;
384 }
385 sc->sc_bulk_head->ed->ed_flags |= LE(OHCI_ED_SKIP);
386
387 /* Allocate all the dummy EDs that make up the interrupt tree. */
388 for (i = 0; i < OHCI_NO_EDS; i++) {
389 sed = ohci_alloc_sed(sc);
390 if (!sed) {
391 while (--i >= 0)
392 ohci_free_sed(sc, sc->sc_eds[i]);
393 r = USBD_NOMEM;
394 goto bad3;
395 }
396 /* All ED fields are set to 0. */
397 sc->sc_eds[i] = sed;
398 sed->ed->ed_flags |= LE(OHCI_ED_SKIP);
399 if (i != 0) {
400 psed = sc->sc_eds[(i-1) / 2];
401 sed->next = psed;
402 sed->ed->ed_nexted = LE(psed->physaddr);
403 }
404 }
405 /*
406 * Fill HCCA interrupt table. The bit reversal is to get
407 * the tree set up properly to spread the interrupts.
408 */
409 for (i = 0; i < OHCI_NO_INTRS; i++)
410 sc->sc_hcca->hcca_interrupt_table[revbits[i]] =
411 LE(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr);
412
413 /* Determine in what context we are running. */
414 ctl = OREAD4(sc, OHCI_CONTROL);
415 if (ctl & OHCI_IR) {
416 /* SMM active, request change */
417 DPRINTF(("ohci_init: SMM active, request owner change\n"));
418 s = OREAD4(sc, OHCI_COMMAND_STATUS);
419 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR);
420 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) {
421 delay(1000);
422 ctl = OREAD4(sc, OHCI_CONTROL);
423 }
424 if ((ctl & OHCI_IR) == 0) {
425 printf("%s: SMM does not respond, resetting\n",
426 USBDEVNAME(sc->sc_bus.bdev));
427 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
428 goto reset;
429 }
430 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) {
431 /* BIOS started controller. */
432 DPRINTF(("ohci_init: BIOS active\n"));
433 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) {
434 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL);
435 delay(USB_RESUME_DELAY * 1000);
436 }
437 } else {
438 DPRINTF(("ohci_init: cold started\n"));
439 reset:
440 /* Controller was cold started. */
441 delay(USB_BUS_RESET_DELAY * 1000);
442 }
443
444 /*
445 * This reset should not be necessary according to the OHCI spec, but
446 * without it some controllers do not start.
447 */
448 DPRINTF(("%s: resetting\n", USBDEVNAME(sc->sc_bus.bdev)));
449 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
450 delay(USB_BUS_RESET_DELAY * 1000);
451
452 /* We now own the host controller and the bus has been reset. */
453 ival = OHCI_GET_IVAL(OREAD4(sc, OHCI_FM_INTERVAL));
454
455 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */
456 /* Nominal time for a reset is 10 us. */
457 for (i = 0; i < 10; i++) {
458 delay(10);
459 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR;
460 if (!hcr)
461 break;
462 }
463 if (hcr) {
464 printf("%s: reset timeout\n", USBDEVNAME(sc->sc_bus.bdev));
465 r = USBD_IOERROR;
466 goto bad3;
467 }
468 #ifdef USB_DEBUG
469 thesc = sc;
470 if (ohcidebug > 15)
471 ohci_dumpregs(sc);
472 #endif
473
474 /* The controller is now in suspend state, we have 2ms to finish. */
475
476 /* Set up HC registers. */
477 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma));
478 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr);
479 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr);
480 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
481 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE);
482 ctl = OREAD4(sc, OHCI_CONTROL);
483 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR);
484 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE |
485 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL;
486 /* And finally start it! */
487 OWRITE4(sc, OHCI_CONTROL, ctl);
488
489 /*
490 * The controller is now OPERATIONAL. Set a some final
491 * registers that should be set earlier, but that the
492 * controller ignores when in the SUSPEND state.
493 */
494 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT;
495 fm |= OHCI_FSMPS(ival) | ival;
496 OWRITE4(sc, OHCI_FM_INTERVAL, fm);
497 per = OHCI_PERIODIC(ival); /* 90% periodic */
498 OWRITE4(sc, OHCI_PERIODIC_START, per);
499
500 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */
501
502 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A));
503
504 #ifdef USB_DEBUG
505 if (ohcidebug > 5)
506 ohci_dumpregs(sc);
507 #endif
508
509 /* Set up the bus struct. */
510 sc->sc_bus.open_pipe = ohci_open;
511 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe);
512 sc->sc_bus.do_poll = ohci_poll;
513
514 (void)powerhook_establish(ohci_power, sc);
515
516 return (USBD_NORMAL_COMPLETION);
517
518 bad3:
519 ohci_free_sed(sc, sc->sc_ctrl_head);
520 bad2:
521 ohci_free_sed(sc, sc->sc_bulk_head);
522 bad1:
523 usb_freemem(sc->sc_dmatag, &sc->sc_hccadma);
524 return (r);
525 }
526
527 void
528 ohci_power(why, v)
529 int why;
530 void *v;
531 {
532 #ifdef USB_DEBUG
533 ohci_softc_t *sc = v;
534
535 printf("ohci_power: sc=%p, why=%d\n", sc, why);
536 /* XXX should suspend/resume */
537 ohci_dumpregs(sc);
538 #endif
539 }
540
541 #ifdef USB_DEBUG
542 void ohcidump(void);
543 void ohcidump(void) { ohci_dumpregs(thesc); }
544
545 void
546 ohci_dumpregs(sc)
547 ohci_softc_t *sc;
548 {
549 printf("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n",
550 OREAD4(sc, OHCI_REVISION),
551 OREAD4(sc, OHCI_CONTROL),
552 OREAD4(sc, OHCI_COMMAND_STATUS));
553 printf(" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n",
554 OREAD4(sc, OHCI_INTERRUPT_STATUS),
555 OREAD4(sc, OHCI_INTERRUPT_ENABLE),
556 OREAD4(sc, OHCI_INTERRUPT_DISABLE));
557 printf(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n",
558 OREAD4(sc, OHCI_HCCA),
559 OREAD4(sc, OHCI_PERIOD_CURRENT_ED),
560 OREAD4(sc, OHCI_CONTROL_HEAD_ED));
561 printf(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n",
562 OREAD4(sc, OHCI_CONTROL_CURRENT_ED),
563 OREAD4(sc, OHCI_BULK_HEAD_ED),
564 OREAD4(sc, OHCI_BULK_CURRENT_ED));
565 printf(" done=0x%08x fmival=0x%08x fmrem=0x%08x\n",
566 OREAD4(sc, OHCI_DONE_HEAD),
567 OREAD4(sc, OHCI_FM_INTERVAL),
568 OREAD4(sc, OHCI_FM_REMAINING));
569 printf(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n",
570 OREAD4(sc, OHCI_FM_NUMBER),
571 OREAD4(sc, OHCI_PERIODIC_START),
572 OREAD4(sc, OHCI_LS_THRESHOLD));
573 printf(" desca=0x%08x descb=0x%08x stat=0x%08x\n",
574 OREAD4(sc, OHCI_RH_DESCRIPTOR_A),
575 OREAD4(sc, OHCI_RH_DESCRIPTOR_B),
576 OREAD4(sc, OHCI_RH_STATUS));
577 printf(" port1=0x%08x port2=0x%08x\n",
578 OREAD4(sc, OHCI_RH_PORT_STATUS(1)),
579 OREAD4(sc, OHCI_RH_PORT_STATUS(2)));
580 printf(" HCCA: frame_number=0x%04x done_head=0x%08x\n",
581 LE(sc->sc_hcca->hcca_frame_number),
582 LE(sc->sc_hcca->hcca_done_head));
583 }
584 #endif
585
586 int
587 ohci_intr(p)
588 void *p;
589 {
590 ohci_softc_t *sc = p;
591 u_int32_t intrs, eintrs;
592 ohci_physaddr_t done;
593
594 /* In case the interrupt occurs before initialization has completed. */
595 if (sc == NULL || sc->sc_hcca == NULL) {
596 #ifdef DIAGNOSTIC
597 printf("ohci_intr: sc->sc_hcca == NULL\n");
598 #endif
599 return (0);
600 }
601
602 intrs = 0;
603 done = LE(sc->sc_hcca->hcca_done_head);
604 if (done != 0) {
605 sc->sc_hcca->hcca_done_head = 0;
606 if (done & ~OHCI_DONE_INTRS)
607 intrs = OHCI_WDH;
608 if (done & OHCI_DONE_INTRS)
609 intrs |= OREAD4(sc, OHCI_INTERRUPT_STATUS);
610 } else
611 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS);
612 if (!intrs)
613 return (0);
614 intrs &= ~OHCI_MIE;
615 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs); /* Acknowledge */
616 eintrs = intrs & sc->sc_eintrs;
617 if (!eintrs)
618 return (0);
619
620 sc->sc_intrs++;
621 DPRINTFN(7, ("ohci_intr: sc=%p intrs=%x(%x) eintr=%x\n",
622 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS),
623 (u_int)eintrs));
624
625 if (eintrs & OHCI_SO) {
626 printf("%s: scheduling overrun\n",USBDEVNAME(sc->sc_bus.bdev));
627 /* XXX do what */
628 intrs &= ~OHCI_SO;
629 }
630 if (eintrs & OHCI_WDH) {
631 ohci_process_done(sc, done &~ OHCI_DONE_INTRS);
632 intrs &= ~OHCI_WDH;
633 }
634 if (eintrs & OHCI_RD) {
635 printf("%s: resume detect\n", USBDEVNAME(sc->sc_bus.bdev));
636 /* XXX process resume detect */
637 }
638 if (eintrs & OHCI_UE) {
639 printf("%s: unrecoverable error, controller halted\n",
640 USBDEVNAME(sc->sc_bus.bdev));
641 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
642 /* XXX what else */
643 }
644 if (eintrs & OHCI_RHSC) {
645 ohci_rhsc(sc, sc->sc_intrreqh);
646 intrs &= ~OHCI_RHSC;
647
648 /*
649 * Disable RHSC interrupt for now, because it will be
650 * on until the port has been reset.
651 */
652 ohci_rhsc_able(sc, 0);
653 }
654
655 /* Block unprocessed interrupts. XXX */
656 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, intrs);
657 sc->sc_eintrs &= ~intrs;
658
659 return (1);
660 }
661
662 void
663 ohci_rhsc_able(sc, on)
664 ohci_softc_t *sc;
665 int on;
666 {
667 DPRINTFN(4, ("ohci_rhsc_able: on=%d\n", on));
668 if (on) {
669 sc->sc_eintrs |= OHCI_RHSC;
670 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC);
671 } else {
672 sc->sc_eintrs &= ~OHCI_RHSC;
673 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_RHSC);
674 }
675 }
676
677 #ifdef USB_DEBUG
678 char *ohci_cc_strs[] = {
679 "NO_ERROR",
680 "CRC",
681 "BIT_STUFFING",
682 "DATA_TOGGLE_MISMATCH",
683 "STALL",
684 "DEVICE_NOT_RESPONDING",
685 "PID_CHECK_FAILURE",
686 "UNEXPECTED_PID",
687 "DATA_OVERRUN",
688 "DATA_UNDERRUN",
689 "BUFFER_OVERRUN",
690 "BUFFER_UNDERRUN",
691 "NOT_ACCESSED",
692 };
693 #endif
694
695 void
696 ohci_process_done(sc, done)
697 ohci_softc_t *sc;
698 ohci_physaddr_t done;
699 {
700 ohci_soft_td_t *std, *sdone;
701 usbd_request_handle reqh;
702 int len, cc;
703
704 DPRINTFN(10,("ohci_process_done: done=0x%08lx\n", (u_long)done));
705
706 /* Reverse the done list. */
707 for (sdone = 0; done; done = LE(std->td->td_nexttd)) {
708 std = ohci_hash_find_td(sc, done);
709 std->dnext = sdone;
710 sdone = std;
711 }
712
713 #ifdef USB_DEBUG
714 if (ohcidebug > 10) {
715 printf("ohci_process_done: TD done:\n");
716 ohci_dump_tds(sdone);
717 }
718 #endif
719
720 for (std = sdone; std; std = std->dnext) {
721 reqh = std->reqh;
722 DPRINTFN(10, ("ohci_process_done: std=%p reqh=%p hcpriv=%p\n",
723 std, reqh, reqh->hcpriv));
724 cc = OHCI_TD_GET_CC(LE(std->td->td_flags));
725 if (reqh->status == USBD_CANCELLED ||
726 reqh->status == USBD_TIMEOUT) {
727 DPRINTF(("ohci_process_done: cancel/timeout %p\n",
728 reqh));
729 ohci_idone(sc, reqh);
730 } else if (cc == OHCI_CC_NO_ERROR) {
731 len = std->len;
732 if (std->td->td_cbp != 0)
733 len -= LE(std->td->td_be) -
734 LE(std->td->td_cbp) + 1;
735 if (std->flags & OHCI_SET_LEN)
736 reqh->actlen = len;
737 if (std->flags & OHCI_CALL_DONE) {
738 reqh->status = USBD_NORMAL_COMPLETION;
739 ohci_idone(sc, reqh);
740 }
741 } else {
742 ohci_soft_td_t *p, *n;
743 struct ohci_pipe *opipe =
744 (struct ohci_pipe *)reqh->pipe;
745 DPRINTFN(-1,("ohci_process_done: error cc=%d (%s)\n",
746 OHCI_TD_GET_CC(LE(std->td->td_flags)),
747 ohci_cc_strs[OHCI_TD_GET_CC(LE(std->td->td_flags))]));
748 /*
749 * Endpoint is halted. First unlink all the TDs
750 * belonging to the failed transfer, and then restart
751 * the endpoint.
752 */
753 for (p = std->nexttd; p->reqh == reqh; p = n) {
754 n = p->nexttd;
755 ohci_hash_rem_td(sc, p);
756 ohci_free_std(sc, p);
757 }
758 /* clear halt */
759 opipe->sed->ed->ed_headp = LE(p->physaddr);
760 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF);
761
762 if (cc == OHCI_CC_STALL)
763 reqh->status = USBD_STALLED;
764 else
765 reqh->status = USBD_IOERROR;
766 ohci_idone(sc, reqh);
767 }
768 ohci_hash_rem_td(sc, std);
769 ohci_free_std(sc, std);
770 }
771 }
772
773 void
774 ohci_idone(sc, reqh)
775 ohci_softc_t *sc;
776 usbd_request_handle reqh;
777 {
778 ohci_done(sc, reqh);
779 if (reqh->pipe->intrreqh != reqh)
780 usb_start_next(reqh->pipe);
781 }
782
783 void
784 ohci_done(sc, reqh)
785 ohci_softc_t *sc;
786 usbd_request_handle reqh;
787 {
788 usbd_pipe_handle pipe = reqh->pipe;
789
790 #ifdef DIAGNOSTIC
791 if (!reqh->hcpriv)
792 printf("ohci_done: reqh=%p, no hcpriv\n", reqh);
793 #endif
794 reqh->hcpriv = 0;
795
796 switch (pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
797 case UE_CONTROL:
798 ohci_ctrl_done(sc, reqh);
799 break;
800 case UE_INTERRUPT:
801 ohci_intr_done(sc, reqh);
802 break;
803 case UE_BULK:
804 ohci_bulk_done(sc, reqh);
805 break;
806 case UE_ISOCHRONOUS:
807 printf("ohci_process_done: ISO done?\n");
808 break;
809 }
810
811 /* Remove request from queue. */
812 SIMPLEQ_REMOVE_HEAD(&pipe->queue, reqh, next);
813
814 /* And finally execute callback. */
815 reqh->xfercb(reqh);
816 }
817
818 void
819 ohci_ctrl_done(sc, reqh)
820 ohci_softc_t *sc;
821 usbd_request_handle reqh;
822 {
823 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe;
824 u_int len = opipe->u.ctl.length;
825 usb_dma_t *dma;
826
827 DPRINTFN(10,("ohci_ctrl_done: reqh=%p\n", reqh));
828
829 if (!reqh->isreq) {
830 panic("ohci_ctrl_done: not a request\n");
831 return;
832 }
833
834 if (len != 0) {
835 dma = &opipe->u.ctl.datadma;
836 if (reqh->request.bmRequestType & UT_READ)
837 memcpy(reqh->buffer, KERNADDR(dma), len);
838 usb_freemem(sc->sc_dmatag, dma);
839 }
840 usb_untimeout(ohci_timeout, reqh, reqh->timo_handle);
841 }
842
843 void
844 ohci_intr_done(sc, reqh)
845 ohci_softc_t *sc;
846 usbd_request_handle reqh;
847 {
848 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe;
849 usb_dma_t *dma;
850 ohci_soft_ed_t *sed = opipe->sed;
851 ohci_soft_td_t *xfer, *tail;
852
853
854 DPRINTFN(10,("ohci_intr_done: reqh=%p, actlen=%d\n",
855 reqh, reqh->actlen));
856
857 dma = &opipe->u.intr.datadma;
858 memcpy(reqh->buffer, KERNADDR(dma), reqh->actlen);
859
860 if (reqh->pipe->intrreqh == reqh) {
861 xfer = opipe->tail;
862 tail = ohci_alloc_std(sc); /* XXX should reuse TD */
863 if (!tail) {
864 reqh->status = USBD_NOMEM;
865 return;
866 }
867 tail->reqh = 0;
868
869 xfer->td->td_flags = LE(
870 OHCI_TD_IN | OHCI_TD_NOCC |
871 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY);
872 if (reqh->flags & USBD_SHORT_XFER_OK)
873 xfer->td->td_flags |= LE(OHCI_TD_R);
874 xfer->td->td_cbp = LE(DMAADDR(dma));
875 xfer->nexttd = tail;
876 xfer->td->td_nexttd = LE(tail->physaddr);
877 xfer->td->td_be = LE(LE(xfer->td->td_cbp) + reqh->length - 1);
878 xfer->len = reqh->length;
879 xfer->reqh = reqh;
880 xfer->flags = OHCI_CALL_DONE | OHCI_SET_LEN;
881 reqh->hcpriv = xfer;
882
883 ohci_hash_add_td(sc, xfer);
884 sed->ed->ed_tailp = LE(tail->physaddr);
885 opipe->tail = tail;
886 } else {
887 usb_freemem(sc->sc_dmatag, dma);
888 }
889 }
890
891 void
892 ohci_bulk_done(sc, reqh)
893 ohci_softc_t *sc;
894 usbd_request_handle reqh;
895 {
896 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe;
897 u_int len = opipe->u.bulk.length;
898 usb_dma_t *dma;
899
900
901 DPRINTFN(10,("ohci_bulk_done: reqh=%p, actlen=%d\n",
902 reqh, reqh->actlen));
903
904 dma = &opipe->u.bulk.datadma;
905 if (opipe->u.bulk.isread)
906 memcpy(reqh->buffer, KERNADDR(dma), len);
907 usb_freemem(sc->sc_dmatag, dma);
908 usb_untimeout(ohci_timeout, reqh, reqh->timo_handle);
909 }
910
911 void
912 ohci_rhsc(sc, reqh)
913 ohci_softc_t *sc;
914 usbd_request_handle reqh;
915 {
916 usbd_pipe_handle pipe;
917 struct ohci_pipe *opipe;
918 u_char *p;
919 int i, m;
920 int hstatus;
921
922 hstatus = OREAD4(sc, OHCI_RH_STATUS);
923 DPRINTF(("ohci_rhsc: sc=%p reqh=%p hstatus=0x%08x\n",
924 sc, reqh, hstatus));
925
926 if (reqh == 0) {
927 /* Just ignore the change. */
928 return;
929 }
930
931 pipe = reqh->pipe;
932 opipe = (struct ohci_pipe *)pipe;
933
934 p = KERNADDR(&opipe->u.intr.datadma);
935 m = min(sc->sc_noport, reqh->length * 8 - 1);
936 memset(p, 0, reqh->length);
937 for (i = 1; i <= m; i++) {
938 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16)
939 p[i/8] |= 1 << (i%8);
940 }
941 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p));
942 reqh->actlen = reqh->length;
943 reqh->status = USBD_NORMAL_COMPLETION;
944 reqh->xfercb(reqh);
945
946 if (reqh->pipe->intrreqh != reqh) {
947 sc->sc_intrreqh = 0;
948 usb_freemem(sc->sc_dmatag, &opipe->u.intr.datadma);
949 usb_start_next(reqh->pipe);
950 }
951 }
952
953 /*
954 * Wait here until controller claims to have an interrupt.
955 * Then call ohci_intr and return. Use timeout to avoid waiting
956 * too long.
957 */
958 void
959 ohci_waitintr(sc, reqh)
960 ohci_softc_t *sc;
961 usbd_request_handle reqh;
962 {
963 int timo = reqh->timeout;
964 int usecs;
965 u_int32_t intrs;
966
967 reqh->status = USBD_IN_PROGRESS;
968 for (usecs = timo * 1000000 / hz; usecs > 0; usecs -= 1000) {
969 usb_delay_ms(&sc->sc_bus, 1);
970 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs;
971 DPRINTFN(15,("ohci_waitintr: 0x%04x\n", intrs));
972 #ifdef USB_DEBUG
973 if (ohcidebug > 15)
974 ohci_dumpregs(sc);
975 #endif
976 if (intrs) {
977 ohci_intr(sc);
978 if (reqh->status != USBD_IN_PROGRESS)
979 return;
980 }
981 }
982
983 /* Timeout */
984 DPRINTF(("ohci_waitintr: timeout\n"));
985 reqh->status = USBD_TIMEOUT;
986 ohci_idone(sc, reqh);
987 /* XXX should free TD */
988 }
989
990 void
991 ohci_poll(bus)
992 struct usbd_bus *bus;
993 {
994 ohci_softc_t *sc = (ohci_softc_t *)bus;
995
996 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs)
997 ohci_intr(sc);
998 }
999
1000 usbd_status
1001 ohci_device_request(reqh)
1002 usbd_request_handle reqh;
1003 {
1004 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe;
1005 usb_device_request_t *req = &reqh->request;
1006 usbd_device_handle dev = opipe->pipe.device;
1007 ohci_softc_t *sc = (ohci_softc_t *)dev->bus;
1008 int addr = dev->address;
1009 ohci_soft_td_t *setup, *xfer = 0, *stat, *next, *tail;
1010 ohci_soft_ed_t *sed;
1011 usb_dma_t *dmap;
1012 int isread;
1013 int len;
1014 usbd_status r;
1015 int s;
1016
1017 isread = req->bmRequestType & UT_READ;
1018 len = UGETW(req->wLength);
1019
1020 DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, "
1021 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n",
1022 req->bmRequestType, req->bRequest, UGETW(req->wValue),
1023 UGETW(req->wIndex), len, addr,
1024 opipe->pipe.endpoint->edesc->bEndpointAddress));
1025
1026 setup = opipe->tail;
1027 stat = ohci_alloc_std(sc);
1028 if (!stat) {
1029 r = USBD_NOMEM;
1030 goto bad1;
1031 }
1032 tail = ohci_alloc_std(sc);
1033 if (!tail) {
1034 r = USBD_NOMEM;
1035 goto bad2;
1036 }
1037 tail->reqh = 0;
1038
1039 sed = opipe->sed;
1040 dmap = &opipe->u.ctl.datadma;
1041 opipe->u.ctl.length = len;
1042
1043 /* Update device address and length since they may have changed. */
1044 /* XXX This only needs to be done once, but it's too early in open. */
1045 sed->ed->ed_flags = LE(
1046 (LE(sed->ed->ed_flags) & ~(OHCI_ED_ADDRMASK | OHCI_ED_MAXPMASK)) |
1047 OHCI_ED_SET_FA(addr) |
1048 OHCI_ED_SET_MAXP(UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize)));
1049
1050 /* Set up data transaction */
1051 if (len != 0) {
1052 xfer = ohci_alloc_std(sc);
1053 if (!xfer) {
1054 r = USBD_NOMEM;
1055 goto bad3;
1056 }
1057 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap);
1058 if (r != USBD_NORMAL_COMPLETION)
1059 goto bad4;
1060 xfer->td->td_flags = LE(
1061 (isread ? OHCI_TD_IN : OHCI_TD_OUT) | OHCI_TD_NOCC |
1062 OHCI_TD_TOGGLE_1 | OHCI_TD_NOINTR |
1063 (reqh->flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0));
1064 xfer->td->td_cbp = LE(DMAADDR(dmap));
1065 xfer->nexttd = stat;
1066 xfer->td->td_nexttd = LE(stat->physaddr);
1067 xfer->td->td_be = LE(LE(xfer->td->td_cbp) + len - 1);
1068 xfer->len = len;
1069 xfer->reqh = reqh;
1070 xfer->flags = OHCI_SET_LEN;
1071
1072 next = xfer;
1073 stat->flags = OHCI_CALL_DONE;
1074 } else {
1075 next = stat;
1076 stat->flags = OHCI_CALL_DONE | OHCI_SET_LEN;
1077 }
1078
1079 memcpy(KERNADDR(&opipe->u.ctl.reqdma), req, sizeof *req);
1080 if (!isread && len != 0)
1081 memcpy(KERNADDR(dmap), reqh->buffer, len);
1082
1083 setup->td->td_flags = LE(OHCI_TD_SETUP | OHCI_TD_NOCC |
1084 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR);
1085 setup->td->td_cbp = LE(DMAADDR(&opipe->u.ctl.reqdma));
1086 setup->nexttd = next;
1087 setup->td->td_nexttd = LE(next->physaddr);
1088 setup->td->td_be = LE(LE(setup->td->td_cbp) + sizeof *req - 1);
1089 setup->len = 0; /* XXX The number of byte we count */
1090 setup->reqh = reqh;
1091 setup->flags = 0;
1092 reqh->hcpriv = setup;
1093
1094 stat->td->td_flags = LE(
1095 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | OHCI_TD_NOCC |
1096 OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1));
1097 stat->td->td_cbp = 0;
1098 stat->nexttd = tail;
1099 stat->td->td_nexttd = LE(tail->physaddr);
1100 stat->td->td_be = 0;
1101 stat->len = 0;
1102 stat->reqh = reqh;
1103
1104 #if USB_DEBUG
1105 if (ohcidebug > 5) {
1106 printf("ohci_device_request:\n");
1107 ohci_dump_ed(sed);
1108 ohci_dump_tds(setup);
1109 }
1110 #endif
1111
1112 /* Insert ED in schedule */
1113 s = splusb();
1114 ohci_hash_add_td(sc, setup);
1115 if (len != 0)
1116 ohci_hash_add_td(sc, xfer);
1117 ohci_hash_add_td(sc, stat);
1118 sed->ed->ed_tailp = LE(tail->physaddr);
1119 opipe->tail = tail;
1120 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF);
1121 if (reqh->timeout && !sc->sc_bus.use_polling) {
1122 usb_timeout(ohci_timeout, reqh,
1123 MS_TO_TICKS(reqh->timeout), reqh->timo_handle);
1124 }
1125 splx(s);
1126
1127 #if USB_DEBUG
1128 if (ohcidebug > 5) {
1129 delay(5000);
1130 printf("ohci_device_request: status=%x\n",
1131 OREAD4(sc, OHCI_COMMAND_STATUS));
1132 ohci_dump_ed(sed);
1133 ohci_dump_tds(setup);
1134 }
1135 #endif
1136
1137 return (USBD_NORMAL_COMPLETION);
1138
1139 bad4:
1140 ohci_free_std(sc, xfer);
1141 bad3:
1142 ohci_free_std(sc, tail);
1143 bad2:
1144 ohci_free_std(sc, stat);
1145 bad1:
1146 return (r);
1147 }
1148
1149 /*
1150 * Add an ED to the schedule. Called at splusb().
1151 */
1152 void
1153 ohci_add_ed(sed, head)
1154 ohci_soft_ed_t *sed;
1155 ohci_soft_ed_t *head;
1156 {
1157 sed->next = head->next;
1158 sed->ed->ed_nexted = head->ed->ed_nexted;
1159 head->next = sed;
1160 head->ed->ed_nexted = LE(sed->physaddr);
1161 }
1162
1163 /*
1164 * Remove an ED from the schedule. Called at splusb().
1165 */
1166 void
1167 ohci_rem_ed(sed, head)
1168 ohci_soft_ed_t *sed;
1169 ohci_soft_ed_t *head;
1170 {
1171 ohci_soft_ed_t *p;
1172
1173 /* XXX */
1174 for (p = head; p && p->next != sed; p = p->next)
1175 ;
1176 if (!p)
1177 panic("ohci_rem_ed: ED not found\n");
1178 p->next = sed->next;
1179 p->ed->ed_nexted = sed->ed->ed_nexted;
1180 }
1181
1182 /*
1183 * When a transfer is completed the TD is added to the done queue by
1184 * the host controller. This queue is the processed by software.
1185 * Unfortunately the queue contains the physical address of the TD
1186 * and we have no simple way to translate this back to a kernel address.
1187 * To make the translation possible (and fast) we use a hash table of
1188 * TDs currently in the schedule. The physical address is used as the
1189 * hash value.
1190 */
1191
1192 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE)
1193 /* Called at splusb() */
1194 void
1195 ohci_hash_add_td(sc, std)
1196 ohci_softc_t *sc;
1197 ohci_soft_td_t *std;
1198 {
1199 int h = HASH(std->physaddr);
1200
1201 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext);
1202 }
1203
1204 /* Called at splusb() */
1205 void
1206 ohci_hash_rem_td(sc, std)
1207 ohci_softc_t *sc;
1208 ohci_soft_td_t *std;
1209 {
1210 LIST_REMOVE(std, hnext);
1211 }
1212
1213 ohci_soft_td_t *
1214 ohci_hash_find_td(sc, a)
1215 ohci_softc_t *sc;
1216 ohci_physaddr_t a;
1217 {
1218 int h = HASH(a);
1219 ohci_soft_td_t *std;
1220
1221 for (std = LIST_FIRST(&sc->sc_hash_tds[h]);
1222 std != 0;
1223 std = LIST_NEXT(std, hnext))
1224 if (std->physaddr == a)
1225 return (std);
1226 panic("ohci_hash_find_td: addr 0x%08lx not found\n", (u_long)a);
1227 }
1228
1229 void
1230 ohci_timeout(addr)
1231 void *addr;
1232 {
1233 #if 0
1234 usbd_request_handle *reqh = addr;
1235 int s;
1236
1237 DPRINTF(("ohci_timeout: reqh=%p\n", reqh));
1238 s = splusb();
1239 /* XXX need to inactivate TD before calling interrupt routine */
1240 ohci_XXX_done(reqh);
1241 splx(s);
1242 #endif
1243 }
1244
1245 #ifdef USB_DEBUG
1246 void
1247 ohci_dump_tds(std)
1248 ohci_soft_td_t *std;
1249 {
1250 for (; std; std = std->nexttd)
1251 ohci_dump_td(std);
1252 }
1253
1254 void
1255 ohci_dump_td(std)
1256 ohci_soft_td_t *std;
1257 {
1258 printf("TD(%p) at %08lx: %b delay=%d ec=%d cc=%d\ncbp=0x%08lx "
1259 "nexttd=0x%08lx be=0x%08lx\n",
1260 std, (u_long)std->physaddr,
1261 (int)LE(std->td->td_flags),
1262 "\20\23R\24OUT\25IN\31TOG1\32SETTOGGLE",
1263 OHCI_TD_GET_DI(LE(std->td->td_flags)),
1264 OHCI_TD_GET_EC(LE(std->td->td_flags)),
1265 OHCI_TD_GET_CC(LE(std->td->td_flags)),
1266 (u_long)LE(std->td->td_cbp),
1267 (u_long)LE(std->td->td_nexttd), (u_long)LE(std->td->td_be));
1268 }
1269
1270 void
1271 ohci_dump_ed(sed)
1272 ohci_soft_ed_t *sed;
1273 {
1274 printf("ED(%p) at %08lx: addr=%d endpt=%d maxp=%d %b\ntailp=0x%08lx "
1275 "headp=%b nexted=0x%08lx\n",
1276 sed, (u_long)sed->physaddr,
1277 OHCI_ED_GET_FA(LE(sed->ed->ed_flags)),
1278 OHCI_ED_GET_EN(LE(sed->ed->ed_flags)),
1279 OHCI_ED_GET_MAXP(LE(sed->ed->ed_flags)),
1280 (int)LE(sed->ed->ed_flags),
1281 "\20\14OUT\15IN\16LOWSPEED\17SKIP\20ISO",
1282 (u_long)LE(sed->ed->ed_tailp),
1283 (u_long)LE(sed->ed->ed_headp), "\20\1HALT\2CARRY",
1284 (u_long)LE(sed->ed->ed_nexted));
1285 }
1286 #endif
1287
1288 usbd_status
1289 ohci_open(pipe)
1290 usbd_pipe_handle pipe;
1291 {
1292 usbd_device_handle dev = pipe->device;
1293 ohci_softc_t *sc = (ohci_softc_t *)dev->bus;
1294 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc;
1295 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;
1296 u_int8_t addr = dev->address;
1297 ohci_soft_ed_t *sed;
1298 ohci_soft_td_t *std;
1299 usbd_status r;
1300 int s;
1301
1302 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n",
1303 pipe, addr, ed->bEndpointAddress, sc->sc_addr));
1304 if (addr == sc->sc_addr) {
1305 switch (ed->bEndpointAddress) {
1306 case USB_CONTROL_ENDPOINT:
1307 pipe->methods = &ohci_root_ctrl_methods;
1308 break;
1309 case UE_IN | OHCI_INTR_ENDPT:
1310 pipe->methods = &ohci_root_intr_methods;
1311 break;
1312 default:
1313 return (USBD_INVAL);
1314 }
1315 } else {
1316 sed = ohci_alloc_sed(sc);
1317 if (sed == 0)
1318 goto bad0;
1319 std = ohci_alloc_std(sc);
1320 if (std == 0)
1321 goto bad1;
1322 opipe->sed = sed;
1323 opipe->tail = std;
1324 sed->ed->ed_flags = LE(
1325 OHCI_ED_SET_FA(addr) |
1326 OHCI_ED_SET_EN(ed->bEndpointAddress) |
1327 OHCI_ED_DIR_TD |
1328 (dev->lowspeed ? OHCI_ED_SPEED : 0) |
1329 ((ed->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS ?
1330 OHCI_ED_FORMAT_ISO : OHCI_ED_FORMAT_GEN) |
1331 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize)));
1332 sed->ed->ed_headp = sed->ed->ed_tailp = LE(std->physaddr);
1333
1334 switch (ed->bmAttributes & UE_XFERTYPE) {
1335 case UE_CONTROL:
1336 pipe->methods = &ohci_device_ctrl_methods;
1337 r = usb_allocmem(sc->sc_dmatag,
1338 sizeof(usb_device_request_t),
1339 0, &opipe->u.ctl.reqdma);
1340 if (r != USBD_NORMAL_COMPLETION)
1341 goto bad;
1342 s = splusb();
1343 ohci_add_ed(sed, sc->sc_ctrl_head);
1344 splx(s);
1345 break;
1346 case UE_INTERRUPT:
1347 pipe->methods = &ohci_device_intr_methods;
1348 return (ohci_device_setintr(sc, opipe, ed->bInterval));
1349 case UE_ISOCHRONOUS:
1350 printf("ohci_open: open iso unimplemented\n");
1351 return (USBD_XXX);
1352 case UE_BULK:
1353 pipe->methods = &ohci_device_bulk_methods;
1354 s = splusb();
1355 ohci_add_ed(sed, sc->sc_bulk_head);
1356 splx(s);
1357 /* XXX is the right place and/or time */
1358 /* Make sure DATA0 toggle will be used next. */
1359 usbd_clear_endpoint_stall(pipe);
1360 break;
1361 }
1362 }
1363 return (USBD_NORMAL_COMPLETION);
1364
1365 bad:
1366 ohci_free_std(sc, std);
1367 bad1:
1368 ohci_free_sed(sc, sed);
1369 bad0:
1370 return (USBD_NOMEM);
1371
1372 }
1373
1374 /*
1375 * Close a reqular pipe.
1376 * Assumes that there are no pending transactions.
1377 */
1378 void
1379 ohci_close_pipe(pipe, head)
1380 usbd_pipe_handle pipe;
1381 ohci_soft_ed_t *head;
1382 {
1383 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;
1384 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus;
1385 ohci_soft_ed_t *sed = opipe->sed;
1386 int s;
1387
1388 s = splusb();
1389 #ifdef DIAGNOSTIC
1390 sed->ed->ed_flags |= LE(OHCI_ED_SKIP);
1391 if ((sed->ed->ed_tailp & LE(OHCI_TAILMASK)) !=
1392 (sed->ed->ed_headp & LE(OHCI_TAILMASK))) {
1393 ohci_physaddr_t td = sed->ed->ed_headp;
1394 ohci_soft_td_t *std;
1395 for (std = LIST_FIRST(&sc->sc_hash_tds[HASH(td)]);
1396 std != 0;
1397 std = LIST_NEXT(std, hnext))
1398 if (std->physaddr == td)
1399 break;
1400 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x "
1401 "tl=0x%x pipe=%p, std=%p\n", sed,
1402 (int)LE(sed->ed->ed_headp), (int)LE(sed->ed->ed_tailp),
1403 pipe, std);
1404 usb_delay_ms(&sc->sc_bus, 2);
1405 if ((sed->ed->ed_tailp & LE(OHCI_TAILMASK)) !=
1406 (sed->ed->ed_headp & LE(OHCI_TAILMASK)))
1407 printf("ohci_close_pipe: pipe still not empty\n");
1408 }
1409 #endif
1410 ohci_rem_ed(sed, head);
1411 splx(s);
1412 ohci_free_std(sc, opipe->tail);
1413 ohci_free_sed(sc, opipe->sed);
1414 }
1415
1416 /*
1417 * Abort a device request.
1418 * If this routine is called at splusb() it guarantees that the request
1419 * will be removed from the hardware scheduling and that the callback
1420 * for it will be called with USBD_CANCELLED status.
1421 * It's impossible to guarantee that the requested transfer will not
1422 * have happened since the hardware runs concurrently.
1423 * If the transaction has already happened we rely on the ordinary
1424 * interrupt processing to process it.
1425 */
1426 void
1427 ohci_abort_request(reqh)
1428 usbd_request_handle reqh;
1429 {
1430 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe;
1431 usbd_device_handle dev = opipe->pipe.device;
1432 ohci_softc_t *sc = (ohci_softc_t *)dev->bus;
1433 ohci_soft_ed_t *sed;
1434 ohci_soft_td_t *p, *n;
1435 int s;
1436
1437 DPRINTF(("ohci_abort_request: reqh=%p pipe=%p\n", reqh, opipe));
1438 s = splusb();
1439
1440 reqh->status = USBD_CANCELLED; /* mark as cancelled */
1441
1442 if (!reqh->hcpriv) {
1443 /* Not scheduled */
1444 reqh->xfercb(reqh);
1445 return;
1446 }
1447
1448 sed = opipe->sed;
1449 DPRINTFN(1,("ohci_abort_request: stop ed=%p\n", sed));
1450 sed->ed->ed_flags |= LE(OHCI_ED_SKIP); /* force hardware skip */
1451 delay(10); /* give HC hardware a little time */
1452
1453 /* if already processed by hardware let interrupt routine handle it */
1454 if ((sed->ed->ed_tailp & LE(OHCI_TAILMASK)) ==
1455 (sed->ed->ed_headp & LE(OHCI_TAILMASK))) {
1456 DPRINTF(("ohci_abort_request: request processed\n"));
1457 usb_delay_ms(dev->bus, 2);
1458 } else {
1459 p = reqh->hcpriv;
1460 #ifdef DIAGNOSTIC
1461 if (!p) {
1462 printf("ohci_abort_request: hcpriv==0\n");
1463 return;
1464 }
1465 #endif
1466 ohci_done(sc, reqh);
1467 for (; p->reqh == reqh; p = n) {
1468 n = p->nexttd;
1469 ohci_hash_rem_td(sc, p);
1470 ohci_free_std(sc, p);
1471 }
1472 DPRINTFN(2,("ohci_abort_request: set hd=%x, tl=%x\n",
1473 (int)LE(p->physaddr), (int)LE(sed->ed->ed_tailp)));
1474 sed->ed->ed_headp = p->physaddr; /* unlink TDs */
1475 }
1476
1477 sed->ed->ed_flags &= LE(~OHCI_ED_SKIP); /* remove hardware skip */
1478 splx(s);
1479 }
1480
1481 /*
1482 * Data structures and routines to emulate the root hub.
1483 */
1484 usb_device_descriptor_t ohci_devd = {
1485 USB_DEVICE_DESCRIPTOR_SIZE,
1486 UDESC_DEVICE, /* type */
1487 {0x00, 0x01}, /* USB version */
1488 UCLASS_HUB, /* class */
1489 USUBCLASS_HUB, /* subclass */
1490 0, /* protocol */
1491 64, /* max packet */
1492 {0},{0},{0x00,0x01}, /* device id */
1493 1,2,0, /* string indicies */
1494 1 /* # of configurations */
1495 };
1496
1497 usb_config_descriptor_t ohci_confd = {
1498 USB_CONFIG_DESCRIPTOR_SIZE,
1499 UDESC_CONFIG,
1500 {USB_CONFIG_DESCRIPTOR_SIZE +
1501 USB_INTERFACE_DESCRIPTOR_SIZE +
1502 USB_ENDPOINT_DESCRIPTOR_SIZE},
1503 1,
1504 1,
1505 0,
1506 UC_SELF_POWERED,
1507 0 /* max power */
1508 };
1509
1510 usb_interface_descriptor_t ohci_ifcd = {
1511 USB_INTERFACE_DESCRIPTOR_SIZE,
1512 UDESC_INTERFACE,
1513 0,
1514 0,
1515 1,
1516 UCLASS_HUB,
1517 USUBCLASS_HUB,
1518 0,
1519 0
1520 };
1521
1522 usb_endpoint_descriptor_t ohci_endpd = {
1523 USB_ENDPOINT_DESCRIPTOR_SIZE,
1524 UDESC_ENDPOINT,
1525 UE_IN | OHCI_INTR_ENDPT,
1526 UE_INTERRUPT,
1527 {8, 0}, /* max packet */
1528 255
1529 };
1530
1531 usb_hub_descriptor_t ohci_hubd = {
1532 USB_HUB_DESCRIPTOR_SIZE,
1533 UDESC_HUB,
1534 0,
1535 {0,0},
1536 0,
1537 0,
1538 {0},
1539 };
1540
1541 int
1542 ohci_str(p, l, s)
1543 usb_string_descriptor_t *p;
1544 int l;
1545 char *s;
1546 {
1547 int i;
1548
1549 if (l == 0)
1550 return (0);
1551 p->bLength = 2 * strlen(s) + 2;
1552 if (l == 1)
1553 return (1);
1554 p->bDescriptorType = UDESC_STRING;
1555 l -= 2;
1556 for (i = 0; s[i] && l > 1; i++, l -= 2)
1557 USETW2(p->bString[i], 0, s[i]);
1558 return (2*i+2);
1559 }
1560
1561 /*
1562 * Simulate a hardware hub by handling all the necessary requests.
1563 */
1564 usbd_status
1565 ohci_root_ctrl_transfer(reqh)
1566 usbd_request_handle reqh;
1567 {
1568 int s;
1569 usbd_status r;
1570
1571 s = splusb();
1572 r = usb_insert_transfer(reqh);
1573 splx(s);
1574 if (r != USBD_NORMAL_COMPLETION)
1575 return (r);
1576 else
1577 return (ohci_root_ctrl_start(reqh));
1578 }
1579
1580 usbd_status
1581 ohci_root_ctrl_start(reqh)
1582 usbd_request_handle reqh;
1583 {
1584 ohci_softc_t *sc = (ohci_softc_t *)reqh->pipe->device->bus;
1585 usb_device_request_t *req;
1586 void *buf;
1587 int port, i;
1588 int len, value, index, l, totlen = 0;
1589 usb_port_status_t ps;
1590 usb_hub_descriptor_t hubd;
1591 usbd_status r;
1592 u_int32_t v;
1593
1594 if (!reqh->isreq)
1595 /* XXX panic */
1596 return (USBD_INVAL);
1597 req = &reqh->request;
1598 buf = reqh->buffer;
1599
1600 DPRINTFN(4,("ohci_root_ctrl_control type=0x%02x request=%02x\n",
1601 req->bmRequestType, req->bRequest));
1602
1603 len = UGETW(req->wLength);
1604 value = UGETW(req->wValue);
1605 index = UGETW(req->wIndex);
1606 #define C(x,y) ((x) | ((y) << 8))
1607 switch(C(req->bRequest, req->bmRequestType)) {
1608 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
1609 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
1610 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
1611 /*
1612 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
1613 * for the integrated root hub.
1614 */
1615 break;
1616 case C(UR_GET_CONFIG, UT_READ_DEVICE):
1617 if (len > 0) {
1618 *(u_int8_t *)buf = sc->sc_conf;
1619 totlen = 1;
1620 }
1621 break;
1622 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
1623 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value));
1624 switch(value >> 8) {
1625 case UDESC_DEVICE:
1626 if ((value & 0xff) != 0) {
1627 r = USBD_IOERROR;
1628 goto ret;
1629 }
1630 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE);
1631 USETW(ohci_devd.idVendor, sc->sc_id_vendor);
1632 memcpy(buf, &ohci_devd, l);
1633 break;
1634 case UDESC_CONFIG:
1635 if ((value & 0xff) != 0) {
1636 r = USBD_IOERROR;
1637 goto ret;
1638 }
1639 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE);
1640 memcpy(buf, &ohci_confd, l);
1641 buf = (char *)buf + l;
1642 len -= l;
1643 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE);
1644 totlen += l;
1645 memcpy(buf, &ohci_ifcd, l);
1646 buf = (char *)buf + l;
1647 len -= l;
1648 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE);
1649 totlen += l;
1650 memcpy(buf, &ohci_endpd, l);
1651 break;
1652 case UDESC_STRING:
1653 if (len == 0)
1654 break;
1655 *(u_int8_t *)buf = 0;
1656 totlen = 1;
1657 switch (value & 0xff) {
1658 case 1: /* Vendor */
1659 totlen = ohci_str(buf, len, sc->sc_vendor);
1660 break;
1661 case 2: /* Product */
1662 totlen = ohci_str(buf, len, "OHCI root hub");
1663 break;
1664 }
1665 break;
1666 default:
1667 r = USBD_IOERROR;
1668 goto ret;
1669 }
1670 break;
1671 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
1672 if (len > 0) {
1673 *(u_int8_t *)buf = 0;
1674 totlen = 1;
1675 }
1676 break;
1677 case C(UR_GET_STATUS, UT_READ_DEVICE):
1678 if (len > 1) {
1679 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED);
1680 totlen = 2;
1681 }
1682 break;
1683 case C(UR_GET_STATUS, UT_READ_INTERFACE):
1684 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
1685 if (len > 1) {
1686 USETW(((usb_status_t *)buf)->wStatus, 0);
1687 totlen = 2;
1688 }
1689 break;
1690 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
1691 if (value >= USB_MAX_DEVICES) {
1692 r = USBD_IOERROR;
1693 goto ret;
1694 }
1695 sc->sc_addr = value;
1696 break;
1697 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
1698 if (value != 0 && value != 1) {
1699 r = USBD_IOERROR;
1700 goto ret;
1701 }
1702 sc->sc_conf = value;
1703 break;
1704 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
1705 break;
1706 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
1707 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
1708 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
1709 r = USBD_IOERROR;
1710 goto ret;
1711 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
1712 break;
1713 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
1714 break;
1715 /* Hub requests */
1716 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
1717 break;
1718 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
1719 DPRINTFN(8, ("ohci_root_ctrl_control: UR_CLEAR_PORT_FEATURE "
1720 "port=%d feature=%d\n",
1721 index, value));
1722 if (index < 1 || index > sc->sc_noport) {
1723 r = USBD_IOERROR;
1724 goto ret;
1725 }
1726 port = OHCI_RH_PORT_STATUS(index);
1727 switch(value) {
1728 case UHF_PORT_ENABLE:
1729 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS);
1730 break;
1731 case UHF_PORT_SUSPEND:
1732 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR);
1733 break;
1734 case UHF_PORT_POWER:
1735 OWRITE4(sc, port, UPS_LOW_SPEED);
1736 break;
1737 case UHF_C_PORT_CONNECTION:
1738 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16);
1739 break;
1740 case UHF_C_PORT_ENABLE:
1741 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16);
1742 break;
1743 case UHF_C_PORT_SUSPEND:
1744 OWRITE4(sc, port, UPS_C_SUSPEND << 16);
1745 break;
1746 case UHF_C_PORT_OVER_CURRENT:
1747 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16);
1748 break;
1749 case UHF_C_PORT_RESET:
1750 OWRITE4(sc, port, UPS_C_PORT_RESET << 16);
1751 break;
1752 default:
1753 r = USBD_IOERROR;
1754 goto ret;
1755 }
1756 switch(value) {
1757 case UHF_C_PORT_CONNECTION:
1758 case UHF_C_PORT_ENABLE:
1759 case UHF_C_PORT_SUSPEND:
1760 case UHF_C_PORT_OVER_CURRENT:
1761 case UHF_C_PORT_RESET:
1762 /* Enable RHSC interrupt if condition is cleared. */
1763 if ((OREAD4(sc, port) >> 16) == 0)
1764 ohci_rhsc_able(sc, 1);
1765 break;
1766 default:
1767 break;
1768 }
1769 break;
1770 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
1771 if (value != 0) {
1772 r = USBD_IOERROR;
1773 goto ret;
1774 }
1775 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A);
1776 hubd = ohci_hubd;
1777 hubd.bNbrPorts = sc->sc_noport;
1778 USETW(hubd.wHubCharacteristics,
1779 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH :
1780 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL)
1781 /* XXX overcurrent */
1782 );
1783 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v);
1784 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B);
1785 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8)
1786 hubd.DeviceRemovable[i++] = (u_int8_t)v;
1787 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i;
1788 l = min(len, hubd.bDescLength);
1789 totlen = l;
1790 memcpy(buf, &hubd, l);
1791 break;
1792 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
1793 if (len != 4) {
1794 r = USBD_IOERROR;
1795 goto ret;
1796 }
1797 memset(buf, 0, len); /* ? XXX */
1798 totlen = len;
1799 break;
1800 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
1801 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n",
1802 index));
1803 if (index < 1 || index > sc->sc_noport) {
1804 r = USBD_IOERROR;
1805 goto ret;
1806 }
1807 if (len != 4) {
1808 r = USBD_IOERROR;
1809 goto ret;
1810 }
1811 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index));
1812 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n",
1813 v));
1814 USETW(ps.wPortStatus, v);
1815 USETW(ps.wPortChange, v >> 16);
1816 l = min(len, sizeof ps);
1817 memcpy(buf, &ps, l);
1818 totlen = l;
1819 break;
1820 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
1821 r = USBD_IOERROR;
1822 goto ret;
1823 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
1824 break;
1825 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
1826 if (index < 1 || index > sc->sc_noport) {
1827 r = USBD_IOERROR;
1828 goto ret;
1829 }
1830 port = OHCI_RH_PORT_STATUS(index);
1831 switch(value) {
1832 case UHF_PORT_ENABLE:
1833 OWRITE4(sc, port, UPS_PORT_ENABLED);
1834 break;
1835 case UHF_PORT_SUSPEND:
1836 OWRITE4(sc, port, UPS_SUSPEND);
1837 break;
1838 case UHF_PORT_RESET:
1839 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n",
1840 index));
1841 OWRITE4(sc, port, UPS_RESET);
1842 for (i = 0; i < 10; i++) {
1843 usb_delay_ms(&sc->sc_bus, 10);
1844 if ((OREAD4(sc, port) & UPS_RESET) == 0)
1845 break;
1846 }
1847 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n",
1848 index, OREAD4(sc, port)));
1849 break;
1850 case UHF_PORT_POWER:
1851 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power "
1852 "%d\n", index));
1853 OWRITE4(sc, port, UPS_PORT_POWER);
1854 break;
1855 default:
1856 r = USBD_IOERROR;
1857 goto ret;
1858 }
1859 break;
1860 default:
1861 r = USBD_IOERROR;
1862 goto ret;
1863 }
1864 reqh->actlen = totlen;
1865 r = USBD_NORMAL_COMPLETION;
1866 ret:
1867 SIMPLEQ_REMOVE_HEAD(&reqh->pipe->queue, reqh, next);
1868 reqh->status = r;
1869 reqh->xfercb(reqh);
1870 usb_start_next(reqh->pipe);
1871 return (USBD_IN_PROGRESS);
1872 }
1873
1874 /* Abort a root control request. */
1875 void
1876 ohci_root_ctrl_abort(reqh)
1877 usbd_request_handle reqh;
1878 {
1879 /* Nothing to do, all transfers are synchronous. */
1880 }
1881
1882 /* Close the root pipe. */
1883 void
1884 ohci_root_ctrl_close(pipe)
1885 usbd_pipe_handle pipe;
1886 {
1887 DPRINTF(("ohci_root_ctrl_close\n"));
1888 /* Nothing to do. */
1889 }
1890
1891 usbd_status
1892 ohci_root_intr_transfer(reqh)
1893 usbd_request_handle reqh;
1894 {
1895 int s;
1896 usbd_status r;
1897
1898 s = splusb();
1899 r = usb_insert_transfer(reqh);
1900 splx(s);
1901 if (r != USBD_NORMAL_COMPLETION)
1902 return (r);
1903 else
1904 return (ohci_root_intr_start(reqh));
1905 }
1906
1907 usbd_status
1908 ohci_root_intr_start(reqh)
1909 usbd_request_handle reqh;
1910 {
1911 usbd_pipe_handle pipe = reqh->pipe;
1912 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus;
1913 struct ohci_pipe *upipe = (struct ohci_pipe *)pipe;
1914 usb_dma_t *dmap;
1915 usbd_status r;
1916 int len;
1917
1918 len = reqh->length;
1919 dmap = &upipe->u.intr.datadma;
1920 if (len == 0)
1921 return (USBD_INVAL); /* XXX should it be? */
1922
1923 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap);
1924 if (r != USBD_NORMAL_COMPLETION)
1925 return (r);
1926 sc->sc_intrreqh = reqh;
1927
1928 return (USBD_IN_PROGRESS);
1929 }
1930
1931 /* Abort a root interrupt request. */
1932 void
1933 ohci_root_intr_abort(reqh)
1934 usbd_request_handle reqh;
1935 {
1936 /* No need to abort. */
1937 }
1938
1939 /* Close the root pipe. */
1940 void
1941 ohci_root_intr_close(pipe)
1942 usbd_pipe_handle pipe;
1943 {
1944 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus;
1945
1946 DPRINTF(("ohci_root_intr_close\n"));
1947
1948 sc->sc_intrreqh = 0;
1949 }
1950
1951 /************************/
1952
1953 usbd_status
1954 ohci_device_ctrl_transfer(reqh)
1955 usbd_request_handle reqh;
1956 {
1957 int s;
1958 usbd_status r;
1959
1960 s = splusb();
1961 r = usb_insert_transfer(reqh);
1962 splx(s);
1963 if (r != USBD_NORMAL_COMPLETION)
1964 return (r);
1965 else
1966 return (ohci_device_ctrl_start(reqh));
1967 }
1968
1969 usbd_status
1970 ohci_device_ctrl_start(reqh)
1971 usbd_request_handle reqh;
1972 {
1973 ohci_softc_t *sc = (ohci_softc_t *)reqh->pipe->device->bus;
1974 usbd_status r;
1975
1976 if (!reqh->isreq) {
1977 /* XXX panic */
1978 printf("ohci_device_ctrl_transfer: not a request\n");
1979 return (USBD_INVAL);
1980 }
1981
1982 r = ohci_device_request(reqh);
1983 if (r != USBD_NORMAL_COMPLETION)
1984 return (r);
1985
1986 if (sc->sc_bus.use_polling)
1987 ohci_waitintr(sc, reqh);
1988 return (USBD_IN_PROGRESS);
1989 }
1990
1991 /* Abort a device control request. */
1992 void
1993 ohci_device_ctrl_abort(reqh)
1994 usbd_request_handle reqh;
1995 {
1996 DPRINTF(("ohci_device_ctrl_abort: reqh=%p\n", reqh));
1997 ohci_abort_request(reqh);
1998 }
1999
2000 /* Close a device control pipe. */
2001 void
2002 ohci_device_ctrl_close(pipe)
2003 usbd_pipe_handle pipe;
2004 {
2005 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus;
2006
2007 DPRINTF(("ohci_device_ctrl_close: pipe=%p\n", pipe));
2008 ohci_close_pipe(pipe, sc->sc_ctrl_head);
2009 }
2010
2011 /************************/
2012
2013 usbd_status
2014 ohci_device_bulk_transfer(reqh)
2015 usbd_request_handle reqh;
2016 {
2017 int s;
2018 usbd_status r;
2019
2020 s = splusb();
2021 r = usb_insert_transfer(reqh);
2022 splx(s);
2023 if (r != USBD_NORMAL_COMPLETION)
2024 return (r);
2025 else
2026 return (ohci_device_bulk_start(reqh));
2027 }
2028
2029 usbd_status
2030 ohci_device_bulk_start(reqh)
2031 usbd_request_handle reqh;
2032 {
2033 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe;
2034 usbd_device_handle dev = opipe->pipe.device;
2035 ohci_softc_t *sc = (ohci_softc_t *)dev->bus;
2036 int addr = dev->address;
2037 ohci_soft_td_t *xfer, *tail;
2038 ohci_soft_ed_t *sed;
2039 usb_dma_t *dmap;
2040 usbd_status r;
2041 int s, len, isread;
2042
2043 #ifdef DIAGNOSTIC
2044 if (reqh->isreq) {
2045 /* XXX panic */
2046 printf("ohci_device_bulk_start: a request\n");
2047 return (USBD_INVAL);
2048 }
2049 #endif
2050
2051 len = reqh->length;
2052 dmap = &opipe->u.bulk.datadma;
2053 isread = reqh->pipe->endpoint->edesc->bEndpointAddress & UE_IN;
2054 sed = opipe->sed;
2055
2056 DPRINTFN(4,("ohci_device_bulk_start: reqh=%p len=%d isread=%d "
2057 "flags=%d endpt=%d\n", reqh, len, isread, reqh->flags,
2058 reqh->pipe->endpoint->edesc->bEndpointAddress));
2059
2060 opipe->u.bulk.isread = isread;
2061 opipe->u.bulk.length = len;
2062
2063 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap);
2064 if (r != USBD_NORMAL_COMPLETION)
2065 goto ret1;
2066
2067 tail = ohci_alloc_std(sc);
2068 if (!tail) {
2069 r = USBD_NOMEM;
2070 goto ret2;
2071 }
2072 tail->reqh = 0;
2073
2074 /* Update device address */
2075 sed->ed->ed_flags = LE(
2076 (LE(sed->ed->ed_flags) & ~OHCI_ED_ADDRMASK) |
2077 OHCI_ED_SET_FA(addr));
2078
2079 /* Set up data transaction */
2080 xfer = opipe->tail;
2081 xfer->td->td_flags = LE(
2082 (isread ? OHCI_TD_IN : OHCI_TD_OUT) | OHCI_TD_NOCC |
2083 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY |
2084 (reqh->flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0));
2085 xfer->td->td_cbp = LE(DMAADDR(dmap));
2086 xfer->nexttd = tail;
2087 xfer->td->td_nexttd = LE(tail->physaddr);
2088 xfer->td->td_be = LE(LE(xfer->td->td_cbp) + len - 1);
2089 xfer->len = len;
2090 xfer->reqh = reqh;
2091 xfer->flags = OHCI_CALL_DONE | OHCI_SET_LEN;
2092 reqh->hcpriv = xfer;
2093
2094 if (!isread)
2095 memcpy(KERNADDR(dmap), reqh->buffer, len);
2096
2097 DPRINTFN(4,("ohci_device_bulk_start: ed_flags=0x%08x td_flags=0x%08x "
2098 "td_cbp=0x%08x td_be=0x%08x\n",
2099 (int)LE(sed->ed->ed_flags), (int)LE(xfer->td->td_flags),
2100 (int)LE(xfer->td->td_cbp), (int)LE(xfer->td->td_be)));
2101
2102 #ifdef USB_DEBUG
2103 if (ohcidebug > 4) {
2104 ohci_dump_ed(sed);
2105 ohci_dump_tds(xfer);
2106 }
2107 #endif
2108
2109 /* Insert ED in schedule */
2110 s = splusb();
2111 ohci_hash_add_td(sc, xfer);
2112 sed->ed->ed_tailp = LE(tail->physaddr);
2113 opipe->tail = tail;
2114 sed->ed->ed_flags &= LE(~OHCI_ED_SKIP);
2115 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF);
2116 if (reqh->timeout && !sc->sc_bus.use_polling) {
2117 usb_timeout(ohci_timeout, reqh,
2118 MS_TO_TICKS(reqh->timeout), reqh->timo_handle);
2119 }
2120
2121 #ifdef USB_DEBUG
2122 if (ohcidebug > 5) {
2123 delay(5000);
2124 printf("ohci_device_intr_transfer: status=%x\n",
2125 OREAD4(sc, OHCI_COMMAND_STATUS));
2126 ohci_dump_ed(sed);
2127 ohci_dump_tds(xfer);
2128 }
2129 #endif
2130
2131 splx(s);
2132
2133 return (USBD_IN_PROGRESS);
2134
2135 ret2:
2136 usb_freemem(sc->sc_dmatag, dmap);
2137 ret1:
2138 return (r);
2139 }
2140
2141 void
2142 ohci_device_bulk_abort(reqh)
2143 usbd_request_handle reqh;
2144 {
2145 DPRINTF(("ohci_device_bulk_abort: reqh=%p\n", reqh));
2146 ohci_abort_request(reqh);
2147 }
2148
2149 /*
2150 * Close a device bulk pipe.
2151 */
2152 void
2153 ohci_device_bulk_close(pipe)
2154 usbd_pipe_handle pipe;
2155 {
2156 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus;
2157
2158 DPRINTF(("ohci_device_bulk_close: pipe=%p\n", pipe));
2159 ohci_close_pipe(pipe, sc->sc_bulk_head);
2160 }
2161
2162 /************************/
2163
2164 usbd_status
2165 ohci_device_intr_transfer(reqh)
2166 usbd_request_handle reqh;
2167 {
2168 int s;
2169 usbd_status r;
2170
2171 s = splusb();
2172 r = usb_insert_transfer(reqh);
2173 splx(s);
2174 if (r != USBD_NORMAL_COMPLETION)
2175 return (r);
2176 else
2177 return (ohci_device_intr_start(reqh));
2178 }
2179
2180 usbd_status
2181 ohci_device_intr_start(reqh)
2182 usbd_request_handle reqh;
2183 {
2184 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe;
2185 usbd_device_handle dev = opipe->pipe.device;
2186 ohci_softc_t *sc = (ohci_softc_t *)dev->bus;
2187 ohci_soft_ed_t *sed = opipe->sed;
2188 ohci_soft_td_t *xfer, *tail;
2189 usb_dma_t *dmap;
2190 usbd_status r;
2191 int len;
2192 int s;
2193
2194 DPRINTFN(3, ("ohci_device_intr_transfer: reqh=%p buf=%p len=%d "
2195 "flags=%d priv=%p\n",
2196 reqh, reqh->buffer, reqh->length, reqh->flags, reqh->priv));
2197
2198 if (reqh->isreq)
2199 panic("ohci_device_intr_transfer: a request\n");
2200
2201 len = reqh->length;
2202 dmap = &opipe->u.intr.datadma;
2203 if (len == 0)
2204 return (USBD_INVAL); /* XXX should it be? */
2205
2206 xfer = opipe->tail;
2207 tail = ohci_alloc_std(sc);
2208 if (!tail) {
2209 r = USBD_NOMEM;
2210 goto ret1;
2211 }
2212 tail->reqh = 0;
2213
2214 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap);
2215 if (r != USBD_NORMAL_COMPLETION)
2216 goto ret2;
2217
2218 xfer->td->td_flags = LE(
2219 OHCI_TD_IN | OHCI_TD_NOCC |
2220 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY);
2221 if (reqh->flags & USBD_SHORT_XFER_OK)
2222 xfer->td->td_flags |= LE(OHCI_TD_R);
2223 xfer->td->td_cbp = LE(DMAADDR(dmap));
2224 xfer->nexttd = tail;
2225 xfer->td->td_nexttd = LE(tail->physaddr);
2226 xfer->td->td_be = LE(LE(xfer->td->td_cbp) + len - 1);
2227 xfer->len = len;
2228 xfer->reqh = reqh;
2229 xfer->flags = OHCI_CALL_DONE | OHCI_SET_LEN;
2230 reqh->hcpriv = xfer;
2231
2232 #if USB_DEBUG
2233 if (ohcidebug > 5) {
2234 printf("ohci_device_intr_transfer:\n");
2235 ohci_dump_ed(sed);
2236 ohci_dump_tds(xfer);
2237 }
2238 #endif
2239
2240 /* Insert ED in schedule */
2241 s = splusb();
2242 ohci_hash_add_td(sc, xfer);
2243 sed->ed->ed_tailp = LE(tail->physaddr);
2244 opipe->tail = tail;
2245 #if 0
2246 if (reqh->timeout && !sc->sc_bus.use_polling) {
2247 usb_timeout(ohci_timeout, reqh,
2248 MS_TO_TICKS(reqh->timeout), reqh->timo_handle);
2249 }
2250 #endif
2251 sed->ed->ed_flags &= LE(~OHCI_ED_SKIP);
2252
2253 #ifdef USB_DEBUG
2254 if (ohcidebug > 5) {
2255 delay(5000);
2256 printf("ohci_device_intr_transfer: status=%x\n",
2257 OREAD4(sc, OHCI_COMMAND_STATUS));
2258 ohci_dump_ed(sed);
2259 ohci_dump_tds(xfer);
2260 }
2261 #endif
2262 splx(s);
2263
2264 return (USBD_IN_PROGRESS);
2265
2266 ret2:
2267 ohci_free_std(sc, xfer);
2268 ret1:
2269 return (r);
2270 }
2271
2272 /* Abort a device control request. */
2273 void
2274 ohci_device_intr_abort(reqh)
2275 usbd_request_handle reqh;
2276 {
2277 if (reqh->pipe->intrreqh == reqh) {
2278 DPRINTF(("ohci_device_intr_abort: remove\n"));
2279 reqh->pipe->intrreqh = 0;
2280 }
2281 ohci_abort_request(reqh);
2282 }
2283
2284 /* Close a device interrupt pipe. */
2285 void
2286 ohci_device_intr_close(pipe)
2287 usbd_pipe_handle pipe;
2288 {
2289 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;
2290 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus;
2291 int nslots = opipe->u.intr.nslots;
2292 int pos = opipe->u.intr.pos;
2293 int j;
2294 ohci_soft_ed_t *p, *sed = opipe->sed;
2295 int s;
2296
2297 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n",
2298 pipe, nslots, pos));
2299 s = splusb();
2300 sed->ed->ed_flags |= LE(OHCI_ED_SKIP);
2301 if ((sed->ed->ed_tailp & LE(OHCI_TAILMASK)) !=
2302 (sed->ed->ed_headp & LE(OHCI_TAILMASK)))
2303 usb_delay_ms(&sc->sc_bus, 2);
2304
2305 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next)
2306 ;
2307 if (!p)
2308 panic("ohci_device_intr_close: ED not found\n");
2309 p->next = sed->next;
2310 p->ed->ed_nexted = sed->ed->ed_nexted;
2311 splx(s);
2312
2313 for (j = 0; j < nslots; j++)
2314 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS];
2315
2316 ohci_free_std(sc, opipe->tail);
2317 ohci_free_sed(sc, opipe->sed);
2318 }
2319
2320 usbd_status
2321 ohci_device_setintr(sc, opipe, ival)
2322 ohci_softc_t *sc;
2323 struct ohci_pipe *opipe;
2324 int ival;
2325 {
2326 int i, j, s, best;
2327 u_int npoll, slow, shigh, nslots;
2328 u_int bestbw, bw;
2329 ohci_soft_ed_t *hsed, *sed = opipe->sed;
2330
2331 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe));
2332 if (ival == 0) {
2333 printf("ohci_setintr: 0 interval\n");
2334 return (USBD_INVAL);
2335 }
2336
2337 npoll = OHCI_NO_INTRS;
2338 while (npoll > ival)
2339 npoll /= 2;
2340 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll));
2341
2342 /*
2343 * We now know which level in the tree the ED must go into.
2344 * Figure out which slot has most bandwidth left over.
2345 * Slots to examine:
2346 * npoll
2347 * 1 0
2348 * 2 1 2
2349 * 4 3 4 5 6
2350 * 8 7 8 9 10 11 12 13 14
2351 * N (N-1) .. (N-1+N-1)
2352 */
2353 slow = npoll-1;
2354 shigh = slow + npoll;
2355 nslots = OHCI_NO_INTRS / npoll;
2356 for (best = i = slow, bestbw = ~0; i < shigh; i++) {
2357 bw = 0;
2358 for (j = 0; j < nslots; j++)
2359 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS];
2360 if (bw < bestbw) {
2361 best = i;
2362 bestbw = bw;
2363 }
2364 }
2365 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n",
2366 best, slow, shigh, bestbw));
2367
2368 s = splusb();
2369 hsed = sc->sc_eds[best];
2370 sed->next = hsed->next;
2371 sed->ed->ed_nexted = hsed->ed->ed_nexted;
2372 hsed->next = sed;
2373 hsed->ed->ed_nexted = LE(sed->physaddr);
2374 splx(s);
2375
2376 for (j = 0; j < nslots; j++)
2377 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS];
2378 opipe->u.intr.nslots = nslots;
2379 opipe->u.intr.pos = best;
2380
2381 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe));
2382 return (USBD_NORMAL_COMPLETION);
2383 }
2384
2385