ohci.c revision 1.36 1 /* $NetBSD: ohci.c,v 1.36 1999/08/17 16:06:21 augustss Exp $ */
2
3 /*
4 * Copyright (c) 1998 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Lennart Augustsson (augustss (at) carlstedt.se) at
9 * Carlstedt Research & Technology.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the NetBSD
22 * Foundation, Inc. and its contributors.
23 * 4. Neither the name of The NetBSD Foundation nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39
40 /*
41 * USB Open Host Controller driver.
42 *
43 * OHCI spec: ftp://ftp.compaq.com/pub/supportinformation/papers/hcir1_0a.exe
44 * USB spec: http://www.usb.org/developers/data/usb11.pdf
45 */
46
47 #include <sys/param.h>
48 #include <sys/systm.h>
49 #include <sys/kernel.h>
50 #include <sys/malloc.h>
51 #if defined(__NetBSD__) || defined(__OpenBSD__)
52 #include <sys/device.h>
53 #elif defined(__FreeBSD__)
54 #include <sys/module.h>
55 #include <sys/bus.h>
56 #endif
57 #include <sys/proc.h>
58 #include <sys/queue.h>
59 #include <sys/select.h>
60
61 #include <machine/bus.h>
62 #include <machine/endian.h>
63
64 #include <dev/usb/usb.h>
65 #include <dev/usb/usbdi.h>
66 #include <dev/usb/usbdivar.h>
67 #include <dev/usb/usb_quirks.h>
68 #include <dev/usb/usb_mem.h>
69
70 #include <dev/usb/ohcireg.h>
71 #include <dev/usb/ohcivar.h>
72
73 #if defined(__FreeBSD__)
74 #include <machine/clock.h>
75
76 #define delay(d) DELAY(d)
77
78 #endif
79
80 #if defined(__OpenBSD__)
81 struct cfdriver ohci_cd = {
82 NULL, "ohci", DV_DULL
83 };
84 #endif
85
86 /*
87 * The OHCI controller is little endian, so on big endian machines
88 * the data strored in memory needs to be swapped.
89 */
90 #if BYTE_ORDER == BIG_ENDIAN
91 #define LE(x) (bswap32(x))
92 #else
93 #define LE(x) (x)
94 #endif
95
96 struct ohci_pipe;
97
98 ohci_soft_ed_t *ohci_alloc_sed __P((ohci_softc_t *));
99 void ohci_free_sed __P((ohci_softc_t *, ohci_soft_ed_t *));
100
101 ohci_soft_td_t *ohci_alloc_std __P((ohci_softc_t *));
102 void ohci_free_std __P((ohci_softc_t *, ohci_soft_td_t *));
103
104 void ohci_power __P((int, void *));
105 usbd_status ohci_open __P((usbd_pipe_handle));
106 void ohci_poll __P((struct usbd_bus *));
107 void ohci_waitintr __P((ohci_softc_t *, usbd_request_handle));
108 void ohci_rhsc __P((ohci_softc_t *, usbd_request_handle));
109 void ohci_process_done __P((ohci_softc_t *, ohci_physaddr_t));
110 void ohci_idone __P((ohci_softc_t *, usbd_request_handle));
111 void ohci_done __P((ohci_softc_t *, usbd_request_handle));
112 void ohci_ctrl_done __P((ohci_softc_t *, usbd_request_handle));
113 void ohci_intr_done __P((ohci_softc_t *, usbd_request_handle));
114 void ohci_bulk_done __P((ohci_softc_t *, usbd_request_handle));
115
116 usbd_status ohci_device_request __P((usbd_request_handle reqh));
117 void ohci_add_ed __P((ohci_soft_ed_t *, ohci_soft_ed_t *));
118 void ohci_rem_ed __P((ohci_soft_ed_t *, ohci_soft_ed_t *));
119 void ohci_hash_add_td __P((ohci_softc_t *, ohci_soft_td_t *));
120 void ohci_hash_rem_td __P((ohci_softc_t *, ohci_soft_td_t *));
121 ohci_soft_td_t *ohci_hash_find_td __P((ohci_softc_t *, ohci_physaddr_t));
122
123 usbd_status ohci_root_ctrl_transfer __P((usbd_request_handle));
124 usbd_status ohci_root_ctrl_start __P((usbd_request_handle));
125 void ohci_root_ctrl_abort __P((usbd_request_handle));
126 void ohci_root_ctrl_close __P((usbd_pipe_handle));
127
128 usbd_status ohci_root_intr_transfer __P((usbd_request_handle));
129 usbd_status ohci_root_intr_start __P((usbd_request_handle));
130 void ohci_root_intr_abort __P((usbd_request_handle));
131 void ohci_root_intr_close __P((usbd_pipe_handle));
132
133 usbd_status ohci_device_ctrl_transfer __P((usbd_request_handle));
134 usbd_status ohci_device_ctrl_start __P((usbd_request_handle));
135 void ohci_device_ctrl_abort __P((usbd_request_handle));
136 void ohci_device_ctrl_close __P((usbd_pipe_handle));
137
138 usbd_status ohci_device_bulk_transfer __P((usbd_request_handle));
139 usbd_status ohci_device_bulk_start __P((usbd_request_handle));
140 void ohci_device_bulk_abort __P((usbd_request_handle));
141 void ohci_device_bulk_close __P((usbd_pipe_handle));
142
143 usbd_status ohci_device_intr_transfer __P((usbd_request_handle));
144 usbd_status ohci_device_intr_start __P((usbd_request_handle));
145 void ohci_device_intr_abort __P((usbd_request_handle));
146 void ohci_device_intr_close __P((usbd_pipe_handle));
147 usbd_status ohci_device_setintr __P((ohci_softc_t *sc,
148 struct ohci_pipe *pipe, int ival));
149
150 int ohci_str __P((usb_string_descriptor_t *, int, char *));
151
152 void ohci_timeout __P((void *));
153 void ohci_rhsc_able __P((ohci_softc_t *, int));
154
155 void ohci_close_pipe __P((usbd_pipe_handle pipe,
156 ohci_soft_ed_t *head));
157 void ohci_abort_request __P((usbd_request_handle reqh));
158
159 #ifdef USB_DEBUG
160 ohci_softc_t *thesc;
161 void ohci_dumpregs __P((ohci_softc_t *));
162 void ohci_dump_tds __P((ohci_soft_td_t *));
163 void ohci_dump_td __P((ohci_soft_td_t *));
164 void ohci_dump_ed __P((ohci_soft_ed_t *));
165 #endif
166
167 #define OWRITE4(sc, r, x) bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x))
168 #define OREAD4(sc, r) bus_space_read_4((sc)->iot, (sc)->ioh, (r))
169 #define OREAD2(sc, r) bus_space_read_2((sc)->iot, (sc)->ioh, (r))
170
171 /* Reverse the bits in a value 0 .. 31 */
172 static u_int8_t revbits[OHCI_NO_INTRS] =
173 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c,
174 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e,
175 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d,
176 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f };
177
178 struct ohci_pipe {
179 struct usbd_pipe pipe;
180 ohci_soft_ed_t *sed;
181 ohci_soft_td_t *tail;
182 /* Info needed for different pipe kinds. */
183 union {
184 /* Control pipe */
185 struct {
186 usb_dma_t datadma;
187 usb_dma_t reqdma;
188 u_int length;
189 ohci_soft_td_t *setup, *xfer, *stat;
190 } ctl;
191 /* Interrupt pipe */
192 struct {
193 usb_dma_t datadma;
194 int nslots;
195 int pos;
196 } intr;
197 /* Bulk pipe */
198 struct {
199 usb_dma_t datadma;
200 u_int length;
201 int isread;
202 } bulk;
203 } u;
204 };
205
206 #define OHCI_INTR_ENDPT 1
207
208 struct usbd_methods ohci_root_ctrl_methods = {
209 ohci_root_ctrl_transfer,
210 ohci_root_ctrl_start,
211 ohci_root_ctrl_abort,
212 ohci_root_ctrl_close,
213 0,
214 };
215
216 struct usbd_methods ohci_root_intr_methods = {
217 ohci_root_intr_transfer,
218 ohci_root_intr_start,
219 ohci_root_intr_abort,
220 ohci_root_intr_close,
221 0,
222 };
223
224 struct usbd_methods ohci_device_ctrl_methods = {
225 ohci_device_ctrl_transfer,
226 ohci_device_ctrl_start,
227 ohci_device_ctrl_abort,
228 ohci_device_ctrl_close,
229 0,
230 };
231
232 struct usbd_methods ohci_device_intr_methods = {
233 ohci_device_intr_transfer,
234 ohci_device_intr_start,
235 ohci_device_intr_abort,
236 ohci_device_intr_close,
237 };
238
239 struct usbd_methods ohci_device_bulk_methods = {
240 ohci_device_bulk_transfer,
241 ohci_device_bulk_start,
242 ohci_device_bulk_abort,
243 ohci_device_bulk_close,
244 0,
245 };
246
247 ohci_soft_ed_t *
248 ohci_alloc_sed(sc)
249 ohci_softc_t *sc;
250 {
251 ohci_soft_ed_t *sed;
252 usbd_status r;
253 int i, offs;
254 usb_dma_t dma;
255
256 if (!sc->sc_freeeds) {
257 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n"));
258 sed = malloc(sizeof(ohci_soft_ed_t) * OHCI_ED_CHUNK,
259 M_USBHC, M_NOWAIT);
260 if (!sed)
261 return 0;
262 r = usb_allocmem(sc->sc_dmatag, OHCI_ED_SIZE * OHCI_ED_CHUNK,
263 OHCI_ED_ALIGN, &dma);
264 if (r != USBD_NORMAL_COMPLETION) {
265 free(sed, M_USBHC);
266 return 0;
267 }
268 for(i = 0; i < OHCI_ED_CHUNK; i++, sed++) {
269 offs = i * OHCI_ED_SIZE;
270 sed->physaddr = DMAADDR(&dma) + offs;
271 sed->ed = (ohci_ed_t *)
272 ((char *)KERNADDR(&dma) + offs);
273 sed->next = sc->sc_freeeds;
274 sc->sc_freeeds = sed;
275 }
276 }
277 sed = sc->sc_freeeds;
278 sc->sc_freeeds = sed->next;
279 memset(sed->ed, 0, OHCI_ED_SIZE);
280 sed->next = 0;
281 return sed;
282 }
283
284 void
285 ohci_free_sed(sc, sed)
286 ohci_softc_t *sc;
287 ohci_soft_ed_t *sed;
288 {
289 sed->next = sc->sc_freeeds;
290 sc->sc_freeeds = sed;
291 }
292
293 ohci_soft_td_t *
294 ohci_alloc_std(sc)
295 ohci_softc_t *sc;
296 {
297 ohci_soft_td_t *std;
298 usbd_status r;
299 int i, offs;
300 usb_dma_t dma;
301
302 if (!sc->sc_freetds) {
303 DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n"));
304 std = malloc(sizeof(ohci_soft_td_t) * OHCI_TD_CHUNK,
305 M_USBHC, M_NOWAIT);
306 if (!std)
307 return 0;
308 r = usb_allocmem(sc->sc_dmatag, OHCI_TD_SIZE * OHCI_TD_CHUNK,
309 OHCI_TD_ALIGN, &dma);
310 if (r != USBD_NORMAL_COMPLETION) {
311 free(std, M_USBHC);
312 return 0;
313 }
314 for(i = 0; i < OHCI_TD_CHUNK; i++, std++) {
315 offs = i * OHCI_TD_SIZE;
316 std->physaddr = DMAADDR(&dma) + offs;
317 std->td = (ohci_td_t *)
318 ((char *)KERNADDR(&dma) + offs);
319 std->nexttd = sc->sc_freetds;
320 sc->sc_freetds = std;
321 }
322 }
323 std = sc->sc_freetds;
324 sc->sc_freetds = std->nexttd;
325 memset(std->td, 0, OHCI_TD_SIZE);
326 std->nexttd = 0;
327 return (std);
328 }
329
330 void
331 ohci_free_std(sc, std)
332 ohci_softc_t *sc;
333 ohci_soft_td_t *std;
334 {
335 std->nexttd = sc->sc_freetds;
336 sc->sc_freetds = std;
337 }
338
339 usbd_status
340 ohci_init(sc)
341 ohci_softc_t *sc;
342 {
343 ohci_soft_ed_t *sed, *psed;
344 usbd_status r;
345 int rev;
346 int i;
347 u_int32_t s, ctl, ival, hcr, fm, per;
348
349 DPRINTF(("ohci_init: start\n"));
350 rev = OREAD4(sc, OHCI_REVISION);
351 #if defined(__OpenBSD__)
352 printf(", OHCI version %d.%d%s\n",
353 #else
354 printf("%s: OHCI version %d.%d%s\n", USBDEVNAME(sc->sc_bus.bdev),
355 #endif
356 OHCI_REV_HI(rev), OHCI_REV_LO(rev),
357 OHCI_REV_LEGACY(rev) ? ", legacy support" : "");
358 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) {
359 printf("%s: unsupported OHCI revision\n",
360 USBDEVNAME(sc->sc_bus.bdev));
361 return (USBD_INVAL);
362 }
363
364 for (i = 0; i < OHCI_HASH_SIZE; i++)
365 LIST_INIT(&sc->sc_hash_tds[i]);
366
367 /* Allocate the HCCA area. */
368 r = usb_allocmem(sc->sc_dmatag, OHCI_HCCA_SIZE,
369 OHCI_HCCA_ALIGN, &sc->sc_hccadma);
370 if (r != USBD_NORMAL_COMPLETION)
371 return (r);
372 sc->sc_hcca = (struct ohci_hcca *)KERNADDR(&sc->sc_hccadma);
373 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE);
374
375 sc->sc_eintrs = OHCI_NORMAL_INTRS;
376
377 sc->sc_ctrl_head = ohci_alloc_sed(sc);
378 if (!sc->sc_ctrl_head) {
379 r = USBD_NOMEM;
380 goto bad1;
381 }
382 sc->sc_ctrl_head->ed->ed_flags |= LE(OHCI_ED_SKIP);
383
384 sc->sc_bulk_head = ohci_alloc_sed(sc);
385 if (!sc->sc_bulk_head) {
386 r = USBD_NOMEM;
387 goto bad2;
388 }
389 sc->sc_bulk_head->ed->ed_flags |= LE(OHCI_ED_SKIP);
390
391 /* Allocate all the dummy EDs that make up the interrupt tree. */
392 for (i = 0; i < OHCI_NO_EDS; i++) {
393 sed = ohci_alloc_sed(sc);
394 if (!sed) {
395 while (--i >= 0)
396 ohci_free_sed(sc, sc->sc_eds[i]);
397 r = USBD_NOMEM;
398 goto bad3;
399 }
400 /* All ED fields are set to 0. */
401 sc->sc_eds[i] = sed;
402 sed->ed->ed_flags |= LE(OHCI_ED_SKIP);
403 if (i != 0) {
404 psed = sc->sc_eds[(i-1) / 2];
405 sed->next = psed;
406 sed->ed->ed_nexted = LE(psed->physaddr);
407 }
408 }
409 /*
410 * Fill HCCA interrupt table. The bit reversal is to get
411 * the tree set up properly to spread the interrupts.
412 */
413 for (i = 0; i < OHCI_NO_INTRS; i++)
414 sc->sc_hcca->hcca_interrupt_table[revbits[i]] =
415 LE(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr);
416
417 /* Determine in what context we are running. */
418 ctl = OREAD4(sc, OHCI_CONTROL);
419 if (ctl & OHCI_IR) {
420 /* SMM active, request change */
421 DPRINTF(("ohci_init: SMM active, request owner change\n"));
422 s = OREAD4(sc, OHCI_COMMAND_STATUS);
423 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR);
424 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) {
425 delay(1000);
426 ctl = OREAD4(sc, OHCI_CONTROL);
427 }
428 if ((ctl & OHCI_IR) == 0) {
429 printf("%s: SMM does not respond, resetting\n",
430 USBDEVNAME(sc->sc_bus.bdev));
431 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
432 goto reset;
433 }
434 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) {
435 /* BIOS started controller. */
436 DPRINTF(("ohci_init: BIOS active\n"));
437 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) {
438 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL);
439 delay(USB_RESUME_DELAY * 1000);
440 }
441 } else {
442 DPRINTF(("ohci_init: cold started\n"));
443 reset:
444 /* Controller was cold started. */
445 delay(USB_BUS_RESET_DELAY * 1000);
446 }
447
448 /*
449 * This reset should not be necessary according to the OHCI spec, but
450 * without it some controllers do not start.
451 */
452 DPRINTF(("%s: resetting\n", USBDEVNAME(sc->sc_bus.bdev)));
453 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
454 delay(USB_BUS_RESET_DELAY * 1000);
455
456 /* We now own the host controller and the bus has been reset. */
457 ival = OHCI_GET_IVAL(OREAD4(sc, OHCI_FM_INTERVAL));
458
459 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */
460 /* Nominal time for a reset is 10 us. */
461 for (i = 0; i < 10; i++) {
462 delay(10);
463 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR;
464 if (!hcr)
465 break;
466 }
467 if (hcr) {
468 printf("%s: reset timeout\n", USBDEVNAME(sc->sc_bus.bdev));
469 r = USBD_IOERROR;
470 goto bad3;
471 }
472 #ifdef USB_DEBUG
473 thesc = sc;
474 if (ohcidebug > 15)
475 ohci_dumpregs(sc);
476 #endif
477
478 /* The controller is now in suspend state, we have 2ms to finish. */
479
480 /* Set up HC registers. */
481 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma));
482 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr);
483 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr);
484 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
485 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE);
486 ctl = OREAD4(sc, OHCI_CONTROL);
487 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR);
488 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE |
489 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL;
490 /* And finally start it! */
491 OWRITE4(sc, OHCI_CONTROL, ctl);
492
493 /*
494 * The controller is now OPERATIONAL. Set a some final
495 * registers that should be set earlier, but that the
496 * controller ignores when in the SUSPEND state.
497 */
498 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT;
499 fm |= OHCI_FSMPS(ival) | ival;
500 OWRITE4(sc, OHCI_FM_INTERVAL, fm);
501 per = OHCI_PERIODIC(ival); /* 90% periodic */
502 OWRITE4(sc, OHCI_PERIODIC_START, per);
503
504 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */
505
506 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A));
507
508 #ifdef USB_DEBUG
509 if (ohcidebug > 5)
510 ohci_dumpregs(sc);
511 #endif
512
513 /* Set up the bus struct. */
514 sc->sc_bus.open_pipe = ohci_open;
515 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe);
516 sc->sc_bus.do_poll = ohci_poll;
517
518 powerhook_establish(ohci_power, sc);
519
520 return (USBD_NORMAL_COMPLETION);
521
522 bad3:
523 ohci_free_sed(sc, sc->sc_ctrl_head);
524 bad2:
525 ohci_free_sed(sc, sc->sc_bulk_head);
526 bad1:
527 usb_freemem(sc->sc_dmatag, &sc->sc_hccadma);
528 return (r);
529 }
530
531 #if !defined(__OpenBSD__)
532 void
533 ohci_power(why, v)
534 int why;
535 void *v;
536 {
537 #ifdef USB_DEBUG
538 ohci_softc_t *sc = v;
539
540 printf("ohci_power: sc=%p, why=%d\n", sc, why);
541 /* XXX should suspend/resume */
542 ohci_dumpregs(sc);
543 #endif
544 }
545 #endif /* !defined(__OpenBSD__) */
546
547 #ifdef USB_DEBUG
548 void ohcidump(void);
549 void ohcidump(void) { ohci_dumpregs(thesc); }
550
551 void
552 ohci_dumpregs(sc)
553 ohci_softc_t *sc;
554 {
555 printf("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n",
556 OREAD4(sc, OHCI_REVISION),
557 OREAD4(sc, OHCI_CONTROL),
558 OREAD4(sc, OHCI_COMMAND_STATUS));
559 printf(" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n",
560 OREAD4(sc, OHCI_INTERRUPT_STATUS),
561 OREAD4(sc, OHCI_INTERRUPT_ENABLE),
562 OREAD4(sc, OHCI_INTERRUPT_DISABLE));
563 printf(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n",
564 OREAD4(sc, OHCI_HCCA),
565 OREAD4(sc, OHCI_PERIOD_CURRENT_ED),
566 OREAD4(sc, OHCI_CONTROL_HEAD_ED));
567 printf(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n",
568 OREAD4(sc, OHCI_CONTROL_CURRENT_ED),
569 OREAD4(sc, OHCI_BULK_HEAD_ED),
570 OREAD4(sc, OHCI_BULK_CURRENT_ED));
571 printf(" done=0x%08x fmival=0x%08x fmrem=0x%08x\n",
572 OREAD4(sc, OHCI_DONE_HEAD),
573 OREAD4(sc, OHCI_FM_INTERVAL),
574 OREAD4(sc, OHCI_FM_REMAINING));
575 printf(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n",
576 OREAD4(sc, OHCI_FM_NUMBER),
577 OREAD4(sc, OHCI_PERIODIC_START),
578 OREAD4(sc, OHCI_LS_THRESHOLD));
579 printf(" desca=0x%08x descb=0x%08x stat=0x%08x\n",
580 OREAD4(sc, OHCI_RH_DESCRIPTOR_A),
581 OREAD4(sc, OHCI_RH_DESCRIPTOR_B),
582 OREAD4(sc, OHCI_RH_STATUS));
583 printf(" port1=0x%08x port2=0x%08x\n",
584 OREAD4(sc, OHCI_RH_PORT_STATUS(1)),
585 OREAD4(sc, OHCI_RH_PORT_STATUS(2)));
586 printf(" HCCA: frame_number=0x%04x done_head=0x%08x\n",
587 LE(sc->sc_hcca->hcca_frame_number),
588 LE(sc->sc_hcca->hcca_done_head));
589 }
590 #endif
591
592 int
593 ohci_intr(p)
594 void *p;
595 {
596 ohci_softc_t *sc = p;
597 u_int32_t intrs, eintrs;
598 ohci_physaddr_t done;
599
600 /* In case the interrupt occurs before initialization has completed. */
601 if (sc == NULL || sc->sc_hcca == NULL) {
602 #ifdef DIAGNOSTIC
603 printf("ohci_intr: sc->sc_hcca == NULL\n");
604 #endif
605 return (0);
606 }
607
608 intrs = 0;
609 done = LE(sc->sc_hcca->hcca_done_head);
610 if (done != 0) {
611 sc->sc_hcca->hcca_done_head = 0;
612 if (done & ~OHCI_DONE_INTRS)
613 intrs = OHCI_WDH;
614 if (done & OHCI_DONE_INTRS)
615 intrs |= OREAD4(sc, OHCI_INTERRUPT_STATUS);
616 } else
617 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS);
618 if (!intrs)
619 return (0);
620 intrs &= ~OHCI_MIE;
621 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs); /* Acknowledge */
622 eintrs = intrs & sc->sc_eintrs;
623 if (!eintrs)
624 return (0);
625
626 sc->sc_intrs++;
627 DPRINTFN(7, ("ohci_intr: sc=%p intrs=%x(%x) eintr=%x\n",
628 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS),
629 (u_int)eintrs));
630
631 if (eintrs & OHCI_SO) {
632 printf("%s: scheduling overrun\n",USBDEVNAME(sc->sc_bus.bdev));
633 /* XXX do what */
634 intrs &= ~OHCI_SO;
635 }
636 if (eintrs & OHCI_WDH) {
637 ohci_process_done(sc, done &~ OHCI_DONE_INTRS);
638 intrs &= ~OHCI_WDH;
639 }
640 if (eintrs & OHCI_RD) {
641 printf("%s: resume detect\n", USBDEVNAME(sc->sc_bus.bdev));
642 /* XXX process resume detect */
643 }
644 if (eintrs & OHCI_UE) {
645 printf("%s: unrecoverable error, controller halted\n",
646 USBDEVNAME(sc->sc_bus.bdev));
647 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
648 /* XXX what else */
649 }
650 if (eintrs & OHCI_RHSC) {
651 ohci_rhsc(sc, sc->sc_intrreqh);
652 intrs &= ~OHCI_RHSC;
653
654 /*
655 * Disable RHSC interrupt for now, because it will be
656 * on until the port has been reset.
657 */
658 ohci_rhsc_able(sc, 0);
659 }
660
661 /* Block unprocessed interrupts. XXX */
662 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, intrs);
663 sc->sc_eintrs &= ~intrs;
664
665 return (1);
666 }
667
668 void
669 ohci_rhsc_able(sc, on)
670 ohci_softc_t *sc;
671 int on;
672 {
673 DPRINTFN(4, ("ohci_rhsc_able: on=%d\n", on));
674 if (on) {
675 sc->sc_eintrs |= OHCI_RHSC;
676 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC);
677 } else {
678 sc->sc_eintrs &= ~OHCI_RHSC;
679 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_RHSC);
680 }
681 }
682
683 #ifdef USB_DEBUG
684 char *ohci_cc_strs[] = {
685 "NO_ERROR",
686 "CRC",
687 "BIT_STUFFING",
688 "DATA_TOGGLE_MISMATCH",
689 "STALL",
690 "DEVICE_NOT_RESPONDING",
691 "PID_CHECK_FAILURE",
692 "UNEXPECTED_PID",
693 "DATA_OVERRUN",
694 "DATA_UNDERRUN",
695 "BUFFER_OVERRUN",
696 "BUFFER_UNDERRUN",
697 "NOT_ACCESSED",
698 };
699 #endif
700
701 void
702 ohci_process_done(sc, done)
703 ohci_softc_t *sc;
704 ohci_physaddr_t done;
705 {
706 ohci_soft_td_t *std, *sdone;
707 usbd_request_handle reqh;
708 int len, cc;
709
710 DPRINTFN(10,("ohci_process_done: done=0x%08lx\n", (u_long)done));
711
712 /* Reverse the done list. */
713 for (sdone = 0; done; done = LE(std->td->td_nexttd)) {
714 std = ohci_hash_find_td(sc, done);
715 std->dnext = sdone;
716 sdone = std;
717 }
718
719 #ifdef USB_DEBUG
720 if (ohcidebug > 10) {
721 printf("ohci_process_done: TD done:\n");
722 ohci_dump_tds(sdone);
723 }
724 #endif
725
726 for (std = sdone; std; std = std->dnext) {
727 reqh = std->reqh;
728 DPRINTFN(10, ("ohci_process_done: std=%p reqh=%p hcpriv=%p\n",
729 std, reqh, reqh->hcpriv));
730 cc = OHCI_TD_GET_CC(LE(std->td->td_flags));
731 if (reqh->status == USBD_CANCELLED ||
732 reqh->status == USBD_TIMEOUT) {
733 DPRINTF(("ohci_process_done: cancel/timeout %p\n",
734 reqh));
735 ohci_idone(sc, reqh);
736 } else if (cc == OHCI_CC_NO_ERROR) {
737 len = std->len;
738 if (std->td->td_cbp != 0)
739 len -= LE(std->td->td_be) -
740 LE(std->td->td_cbp) + 1;
741 if (std->flags & OHCI_SET_LEN)
742 reqh->actlen = len;
743 if (std->flags & OHCI_CALL_DONE) {
744 reqh->status = USBD_NORMAL_COMPLETION;
745 ohci_idone(sc, reqh);
746 }
747 } else {
748 ohci_soft_td_t *p, *n;
749 struct ohci_pipe *opipe =
750 (struct ohci_pipe *)reqh->pipe;
751 DPRINTFN(-1,("ohci_process_done: error cc=%d (%s)\n",
752 OHCI_TD_GET_CC(LE(std->td->td_flags)),
753 ohci_cc_strs[OHCI_TD_GET_CC(LE(std->td->td_flags))]));
754 /*
755 * Endpoint is halted. First unlink all the TDs
756 * belonging to the failed transfer, and then restart
757 * the endpoint.
758 */
759 for (p = std->nexttd; p->reqh == reqh; p = n) {
760 n = p->nexttd;
761 ohci_hash_rem_td(sc, p);
762 ohci_free_std(sc, p);
763 }
764 /* clear halt */
765 opipe->sed->ed->ed_headp = LE(p->physaddr);
766 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF);
767
768 if (cc == OHCI_CC_STALL)
769 reqh->status = USBD_STALLED;
770 else
771 reqh->status = USBD_IOERROR;
772 ohci_idone(sc, reqh);
773 }
774 ohci_hash_rem_td(sc, std);
775 ohci_free_std(sc, std);
776 }
777 }
778
779 void
780 ohci_idone(sc, reqh)
781 ohci_softc_t *sc;
782 usbd_request_handle reqh;
783 {
784 ohci_done(sc, reqh);
785 if (reqh->pipe->intrreqh != reqh)
786 usb_start_next(reqh->pipe);
787 }
788
789 void
790 ohci_done(sc, reqh)
791 ohci_softc_t *sc;
792 usbd_request_handle reqh;
793 {
794 usbd_pipe_handle pipe = reqh->pipe;
795
796 #ifdef DIAGNOSTIC
797 if (!reqh->hcpriv)
798 printf("ohci_done: reqh=%p, no hcpriv\n", reqh);
799 #endif
800 reqh->hcpriv = 0;
801
802 switch (pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
803 case UE_CONTROL:
804 ohci_ctrl_done(sc, reqh);
805 break;
806 case UE_INTERRUPT:
807 ohci_intr_done(sc, reqh);
808 break;
809 case UE_BULK:
810 ohci_bulk_done(sc, reqh);
811 break;
812 case UE_ISOCHRONOUS:
813 printf("ohci_process_done: ISO done?\n");
814 break;
815 }
816
817 /* Remove request from queue. */
818 SIMPLEQ_REMOVE_HEAD(&pipe->queue, reqh, next);
819
820 /* And finally execute callback. */
821 reqh->xfercb(reqh);
822 }
823
824 void
825 ohci_ctrl_done(sc, reqh)
826 ohci_softc_t *sc;
827 usbd_request_handle reqh;
828 {
829 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe;
830 u_int len = opipe->u.ctl.length;
831 usb_dma_t *dma;
832
833 DPRINTFN(10,("ohci_ctrl_done: reqh=%p\n", reqh));
834
835 if (!reqh->isreq) {
836 panic("ohci_ctrl_done: not a request\n");
837 return;
838 }
839
840 if (len != 0) {
841 dma = &opipe->u.ctl.datadma;
842 if (reqh->request.bmRequestType & UT_READ)
843 memcpy(reqh->buffer, KERNADDR(dma), len);
844 usb_freemem(sc->sc_dmatag, dma);
845 }
846 usb_untimeout(ohci_timeout, reqh, reqh->timo_handle);
847 }
848
849 void
850 ohci_intr_done(sc, reqh)
851 ohci_softc_t *sc;
852 usbd_request_handle reqh;
853 {
854 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe;
855 usb_dma_t *dma;
856 ohci_soft_ed_t *sed = opipe->sed;
857 ohci_soft_td_t *xfer, *tail;
858
859
860 DPRINTFN(10,("ohci_intr_done: reqh=%p, actlen=%d\n",
861 reqh, reqh->actlen));
862
863 dma = &opipe->u.intr.datadma;
864 memcpy(reqh->buffer, KERNADDR(dma), reqh->actlen);
865
866 if (reqh->pipe->intrreqh == reqh) {
867 xfer = opipe->tail;
868 tail = ohci_alloc_std(sc); /* XXX should reuse TD */
869 if (!tail) {
870 reqh->status = USBD_NOMEM;
871 return;
872 }
873 tail->reqh = 0;
874
875 xfer->td->td_flags = LE(
876 OHCI_TD_IN | OHCI_TD_NOCC |
877 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY);
878 if (reqh->flags & USBD_SHORT_XFER_OK)
879 xfer->td->td_flags |= LE(OHCI_TD_R);
880 xfer->td->td_cbp = LE(DMAADDR(dma));
881 xfer->nexttd = tail;
882 xfer->td->td_nexttd = LE(tail->physaddr);
883 xfer->td->td_be = LE(LE(xfer->td->td_cbp) + reqh->length - 1);
884 xfer->len = reqh->length;
885 xfer->reqh = reqh;
886 xfer->flags = OHCI_CALL_DONE | OHCI_SET_LEN;
887 reqh->hcpriv = xfer;
888
889 ohci_hash_add_td(sc, xfer);
890 sed->ed->ed_tailp = LE(tail->physaddr);
891 opipe->tail = tail;
892 } else {
893 usb_freemem(sc->sc_dmatag, dma);
894 }
895 }
896
897 void
898 ohci_bulk_done(sc, reqh)
899 ohci_softc_t *sc;
900 usbd_request_handle reqh;
901 {
902 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe;
903 u_int len = opipe->u.bulk.length;
904 usb_dma_t *dma;
905
906
907 DPRINTFN(10,("ohci_bulk_done: reqh=%p, actlen=%d\n",
908 reqh, reqh->actlen));
909
910 dma = &opipe->u.bulk.datadma;
911 if (opipe->u.bulk.isread)
912 memcpy(reqh->buffer, KERNADDR(dma), len);
913 usb_freemem(sc->sc_dmatag, dma);
914 usb_untimeout(ohci_timeout, reqh, reqh->timo_handle);
915 }
916
917 void
918 ohci_rhsc(sc, reqh)
919 ohci_softc_t *sc;
920 usbd_request_handle reqh;
921 {
922 usbd_pipe_handle pipe;
923 struct ohci_pipe *opipe;
924 u_char *p;
925 int i, m;
926 int hstatus;
927
928 hstatus = OREAD4(sc, OHCI_RH_STATUS);
929 DPRINTF(("ohci_rhsc: sc=%p reqh=%p hstatus=0x%08x\n",
930 sc, reqh, hstatus));
931
932 if (reqh == 0) {
933 /* Just ignore the change. */
934 return;
935 }
936
937 pipe = reqh->pipe;
938 opipe = (struct ohci_pipe *)pipe;
939
940 p = KERNADDR(&opipe->u.intr.datadma);
941 m = min(sc->sc_noport, reqh->length * 8 - 1);
942 memset(p, 0, reqh->length);
943 for (i = 1; i <= m; i++) {
944 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16)
945 p[i/8] |= 1 << (i%8);
946 }
947 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p));
948 reqh->actlen = reqh->length;
949 reqh->status = USBD_NORMAL_COMPLETION;
950 reqh->xfercb(reqh);
951
952 if (reqh->pipe->intrreqh != reqh) {
953 sc->sc_intrreqh = 0;
954 usb_freemem(sc->sc_dmatag, &opipe->u.intr.datadma);
955 usb_start_next(reqh->pipe);
956 }
957 }
958
959 /*
960 * Wait here until controller claims to have an interrupt.
961 * Then call ohci_intr and return. Use timeout to avoid waiting
962 * too long.
963 */
964 void
965 ohci_waitintr(sc, reqh)
966 ohci_softc_t *sc;
967 usbd_request_handle reqh;
968 {
969 int timo = reqh->timeout;
970 int usecs;
971 u_int32_t intrs;
972
973 reqh->status = USBD_IN_PROGRESS;
974 for (usecs = timo * 1000000 / hz; usecs > 0; usecs -= 1000) {
975 usb_delay_ms(&sc->sc_bus, 1);
976 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs;
977 DPRINTFN(15,("ohci_waitintr: 0x%04x\n", intrs));
978 #ifdef USB_DEBUG
979 if (ohcidebug > 15)
980 ohci_dumpregs(sc);
981 #endif
982 if (intrs) {
983 ohci_intr(sc);
984 if (reqh->status != USBD_IN_PROGRESS)
985 return;
986 }
987 }
988
989 /* Timeout */
990 DPRINTF(("ohci_waitintr: timeout\n"));
991 reqh->status = USBD_TIMEOUT;
992 ohci_idone(sc, reqh);
993 /* XXX should free TD */
994 }
995
996 void
997 ohci_poll(bus)
998 struct usbd_bus *bus;
999 {
1000 ohci_softc_t *sc = (ohci_softc_t *)bus;
1001
1002 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs)
1003 ohci_intr(sc);
1004 }
1005
1006 usbd_status
1007 ohci_device_request(reqh)
1008 usbd_request_handle reqh;
1009 {
1010 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe;
1011 usb_device_request_t *req = &reqh->request;
1012 usbd_device_handle dev = opipe->pipe.device;
1013 ohci_softc_t *sc = (ohci_softc_t *)dev->bus;
1014 int addr = dev->address;
1015 ohci_soft_td_t *setup, *xfer = 0, *stat, *next, *tail;
1016 ohci_soft_ed_t *sed;
1017 usb_dma_t *dmap;
1018 int isread;
1019 int len;
1020 usbd_status r;
1021 int s;
1022
1023 isread = req->bmRequestType & UT_READ;
1024 len = UGETW(req->wLength);
1025
1026 DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, "
1027 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n",
1028 req->bmRequestType, req->bRequest, UGETW(req->wValue),
1029 UGETW(req->wIndex), len, addr,
1030 opipe->pipe.endpoint->edesc->bEndpointAddress));
1031
1032 setup = opipe->tail;
1033 stat = ohci_alloc_std(sc);
1034 if (!stat) {
1035 r = USBD_NOMEM;
1036 goto bad1;
1037 }
1038 tail = ohci_alloc_std(sc);
1039 if (!tail) {
1040 r = USBD_NOMEM;
1041 goto bad2;
1042 }
1043 tail->reqh = 0;
1044
1045 sed = opipe->sed;
1046 dmap = &opipe->u.ctl.datadma;
1047 opipe->u.ctl.length = len;
1048
1049 /* Update device address and length since they may have changed. */
1050 /* XXX This only needs to be done once, but it's too early in open. */
1051 sed->ed->ed_flags = LE(
1052 (LE(sed->ed->ed_flags) & ~(OHCI_ED_ADDRMASK | OHCI_ED_MAXPMASK)) |
1053 OHCI_ED_SET_FA(addr) |
1054 OHCI_ED_SET_MAXP(UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize)));
1055
1056 /* Set up data transaction */
1057 if (len != 0) {
1058 xfer = ohci_alloc_std(sc);
1059 if (!xfer) {
1060 r = USBD_NOMEM;
1061 goto bad3;
1062 }
1063 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap);
1064 if (r != USBD_NORMAL_COMPLETION)
1065 goto bad4;
1066 xfer->td->td_flags = LE(
1067 (isread ? OHCI_TD_IN : OHCI_TD_OUT) | OHCI_TD_NOCC |
1068 OHCI_TD_TOGGLE_1 | OHCI_TD_NOINTR |
1069 (reqh->flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0));
1070 xfer->td->td_cbp = LE(DMAADDR(dmap));
1071 xfer->nexttd = stat;
1072 xfer->td->td_nexttd = LE(stat->physaddr);
1073 xfer->td->td_be = LE(LE(xfer->td->td_cbp) + len - 1);
1074 xfer->len = len;
1075 xfer->reqh = reqh;
1076 xfer->flags = OHCI_SET_LEN;
1077
1078 next = xfer;
1079 stat->flags = OHCI_CALL_DONE;
1080 } else {
1081 next = stat;
1082 stat->flags = OHCI_CALL_DONE | OHCI_SET_LEN;
1083 }
1084
1085 memcpy(KERNADDR(&opipe->u.ctl.reqdma), req, sizeof *req);
1086 if (!isread && len != 0)
1087 memcpy(KERNADDR(dmap), reqh->buffer, len);
1088
1089 setup->td->td_flags = LE(OHCI_TD_SETUP | OHCI_TD_NOCC |
1090 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR);
1091 setup->td->td_cbp = LE(DMAADDR(&opipe->u.ctl.reqdma));
1092 setup->nexttd = next;
1093 setup->td->td_nexttd = LE(next->physaddr);
1094 setup->td->td_be = LE(LE(setup->td->td_cbp) + sizeof *req - 1);
1095 setup->len = 0; /* XXX The number of byte we count */
1096 setup->reqh = reqh;
1097 setup->flags = 0;
1098 reqh->hcpriv = setup;
1099
1100 stat->td->td_flags = LE(
1101 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | OHCI_TD_NOCC |
1102 OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1));
1103 stat->td->td_cbp = 0;
1104 stat->nexttd = tail;
1105 stat->td->td_nexttd = LE(tail->physaddr);
1106 stat->td->td_be = 0;
1107 stat->len = 0;
1108 stat->reqh = reqh;
1109
1110 #if USB_DEBUG
1111 if (ohcidebug > 5) {
1112 printf("ohci_device_request:\n");
1113 ohci_dump_ed(sed);
1114 ohci_dump_tds(setup);
1115 }
1116 #endif
1117
1118 /* Insert ED in schedule */
1119 s = splusb();
1120 ohci_hash_add_td(sc, setup);
1121 if (len != 0)
1122 ohci_hash_add_td(sc, xfer);
1123 ohci_hash_add_td(sc, stat);
1124 sed->ed->ed_tailp = LE(tail->physaddr);
1125 opipe->tail = tail;
1126 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF);
1127 if (reqh->timeout && !sc->sc_bus.use_polling) {
1128 usb_timeout(ohci_timeout, reqh,
1129 MS_TO_TICKS(reqh->timeout), reqh->timo_handle);
1130 }
1131 splx(s);
1132
1133 #if USB_DEBUG
1134 if (ohcidebug > 5) {
1135 delay(5000);
1136 printf("ohci_device_request: status=%x\n",
1137 OREAD4(sc, OHCI_COMMAND_STATUS));
1138 ohci_dump_ed(sed);
1139 ohci_dump_tds(setup);
1140 }
1141 #endif
1142
1143 return (USBD_NORMAL_COMPLETION);
1144
1145 bad4:
1146 ohci_free_std(sc, xfer);
1147 bad3:
1148 ohci_free_std(sc, tail);
1149 bad2:
1150 ohci_free_std(sc, stat);
1151 bad1:
1152 return (r);
1153 }
1154
1155 /*
1156 * Add an ED to the schedule. Called at splusb().
1157 */
1158 void
1159 ohci_add_ed(sed, head)
1160 ohci_soft_ed_t *sed;
1161 ohci_soft_ed_t *head;
1162 {
1163 sed->next = head->next;
1164 sed->ed->ed_nexted = head->ed->ed_nexted;
1165 head->next = sed;
1166 head->ed->ed_nexted = LE(sed->physaddr);
1167 }
1168
1169 /*
1170 * Remove an ED from the schedule. Called at splusb().
1171 */
1172 void
1173 ohci_rem_ed(sed, head)
1174 ohci_soft_ed_t *sed;
1175 ohci_soft_ed_t *head;
1176 {
1177 ohci_soft_ed_t *p;
1178
1179 /* XXX */
1180 for (p = head; p && p->next != sed; p = p->next)
1181 ;
1182 if (!p)
1183 panic("ohci_rem_ed: ED not found\n");
1184 p->next = sed->next;
1185 p->ed->ed_nexted = sed->ed->ed_nexted;
1186 }
1187
1188 /*
1189 * When a transfer is completed the TD is added to the done queue by
1190 * the host controller. This queue is the processed by software.
1191 * Unfortunately the queue contains the physical address of the TD
1192 * and we have no simple way to translate this back to a kernel address.
1193 * To make the translation possible (and fast) we use a hash table of
1194 * TDs currently in the schedule. The physical address is used as the
1195 * hash value.
1196 */
1197
1198 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE)
1199 /* Called at splusb() */
1200 void
1201 ohci_hash_add_td(sc, std)
1202 ohci_softc_t *sc;
1203 ohci_soft_td_t *std;
1204 {
1205 int h = HASH(std->physaddr);
1206
1207 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext);
1208 }
1209
1210 /* Called at splusb() */
1211 void
1212 ohci_hash_rem_td(sc, std)
1213 ohci_softc_t *sc;
1214 ohci_soft_td_t *std;
1215 {
1216 LIST_REMOVE(std, hnext);
1217 }
1218
1219 ohci_soft_td_t *
1220 ohci_hash_find_td(sc, a)
1221 ohci_softc_t *sc;
1222 ohci_physaddr_t a;
1223 {
1224 int h = HASH(a);
1225 ohci_soft_td_t *std;
1226
1227 for (std = LIST_FIRST(&sc->sc_hash_tds[h]);
1228 std != 0;
1229 std = LIST_NEXT(std, hnext))
1230 if (std->physaddr == a)
1231 return (std);
1232 panic("ohci_hash_find_td: addr 0x%08lx not found\n", (u_long)a);
1233 }
1234
1235 void
1236 ohci_timeout(addr)
1237 void *addr;
1238 {
1239 #if 0
1240 usbd_request_handle *reqh = addr;
1241 int s;
1242
1243 DPRINTF(("ohci_timeout: reqh=%p\n", reqh));
1244 s = splusb();
1245 /* XXX need to inactivate TD before calling interrupt routine */
1246 ohci_XXX_done(reqh);
1247 splx(s);
1248 #endif
1249 }
1250
1251 #ifdef USB_DEBUG
1252 void
1253 ohci_dump_tds(std)
1254 ohci_soft_td_t *std;
1255 {
1256 for (; std; std = std->nexttd)
1257 ohci_dump_td(std);
1258 }
1259
1260 void
1261 ohci_dump_td(std)
1262 ohci_soft_td_t *std;
1263 {
1264 printf("TD(%p) at %08lx: %b delay=%d ec=%d cc=%d\ncbp=0x%08lx "
1265 "nexttd=0x%08lx be=0x%08lx\n",
1266 std, (u_long)std->physaddr,
1267 (int)LE(std->td->td_flags),
1268 "\20\23R\24OUT\25IN\31TOG1\32SETTOGGLE",
1269 OHCI_TD_GET_DI(LE(std->td->td_flags)),
1270 OHCI_TD_GET_EC(LE(std->td->td_flags)),
1271 OHCI_TD_GET_CC(LE(std->td->td_flags)),
1272 (u_long)LE(std->td->td_cbp),
1273 (u_long)LE(std->td->td_nexttd), (u_long)LE(std->td->td_be));
1274 }
1275
1276 void
1277 ohci_dump_ed(sed)
1278 ohci_soft_ed_t *sed;
1279 {
1280 printf("ED(%p) at %08lx: addr=%d endpt=%d maxp=%d %b\ntailp=0x%08lx "
1281 "headp=%b nexted=0x%08lx\n",
1282 sed, (u_long)sed->physaddr,
1283 OHCI_ED_GET_FA(LE(sed->ed->ed_flags)),
1284 OHCI_ED_GET_EN(LE(sed->ed->ed_flags)),
1285 OHCI_ED_GET_MAXP(LE(sed->ed->ed_flags)),
1286 (int)LE(sed->ed->ed_flags),
1287 "\20\14OUT\15IN\16LOWSPEED\17SKIP\20ISO",
1288 (u_long)LE(sed->ed->ed_tailp),
1289 (u_long)LE(sed->ed->ed_headp), "\20\1HALT\2CARRY",
1290 (u_long)LE(sed->ed->ed_nexted));
1291 }
1292 #endif
1293
1294 usbd_status
1295 ohci_open(pipe)
1296 usbd_pipe_handle pipe;
1297 {
1298 usbd_device_handle dev = pipe->device;
1299 ohci_softc_t *sc = (ohci_softc_t *)dev->bus;
1300 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc;
1301 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;
1302 u_int8_t addr = dev->address;
1303 ohci_soft_ed_t *sed;
1304 ohci_soft_td_t *std;
1305 usbd_status r;
1306 int s;
1307
1308 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n",
1309 pipe, addr, ed->bEndpointAddress, sc->sc_addr));
1310 if (addr == sc->sc_addr) {
1311 switch (ed->bEndpointAddress) {
1312 case USB_CONTROL_ENDPOINT:
1313 pipe->methods = &ohci_root_ctrl_methods;
1314 break;
1315 case UE_IN | OHCI_INTR_ENDPT:
1316 pipe->methods = &ohci_root_intr_methods;
1317 break;
1318 default:
1319 return (USBD_INVAL);
1320 }
1321 } else {
1322 sed = ohci_alloc_sed(sc);
1323 if (sed == 0)
1324 goto bad0;
1325 std = ohci_alloc_std(sc);
1326 if (std == 0)
1327 goto bad1;
1328 opipe->sed = sed;
1329 opipe->tail = std;
1330 sed->ed->ed_flags = LE(
1331 OHCI_ED_SET_FA(addr) |
1332 OHCI_ED_SET_EN(ed->bEndpointAddress) |
1333 OHCI_ED_DIR_TD |
1334 (dev->lowspeed ? OHCI_ED_SPEED : 0) |
1335 ((ed->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS ?
1336 OHCI_ED_FORMAT_ISO : OHCI_ED_FORMAT_GEN) |
1337 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize)));
1338 sed->ed->ed_headp = sed->ed->ed_tailp = LE(std->physaddr);
1339
1340 switch (ed->bmAttributes & UE_XFERTYPE) {
1341 case UE_CONTROL:
1342 pipe->methods = &ohci_device_ctrl_methods;
1343 r = usb_allocmem(sc->sc_dmatag,
1344 sizeof(usb_device_request_t),
1345 0, &opipe->u.ctl.reqdma);
1346 if (r != USBD_NORMAL_COMPLETION)
1347 goto bad;
1348 s = splusb();
1349 ohci_add_ed(sed, sc->sc_ctrl_head);
1350 splx(s);
1351 break;
1352 case UE_INTERRUPT:
1353 pipe->methods = &ohci_device_intr_methods;
1354 return (ohci_device_setintr(sc, opipe, ed->bInterval));
1355 case UE_ISOCHRONOUS:
1356 printf("ohci_open: open iso unimplemented\n");
1357 return (USBD_XXX);
1358 case UE_BULK:
1359 pipe->methods = &ohci_device_bulk_methods;
1360 s = splusb();
1361 ohci_add_ed(sed, sc->sc_bulk_head);
1362 splx(s);
1363 /* XXX is the right place and/or time */
1364 /* Make sure DATA0 toggle will be used next. */
1365 usbd_clear_endpoint_stall(pipe);
1366 break;
1367 }
1368 }
1369 return (USBD_NORMAL_COMPLETION);
1370
1371 bad:
1372 ohci_free_std(sc, std);
1373 bad1:
1374 ohci_free_sed(sc, sed);
1375 bad0:
1376 return (USBD_NOMEM);
1377
1378 }
1379
1380 /*
1381 * Close a reqular pipe.
1382 * Assumes that there are no pending transactions.
1383 */
1384 void
1385 ohci_close_pipe(pipe, head)
1386 usbd_pipe_handle pipe;
1387 ohci_soft_ed_t *head;
1388 {
1389 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;
1390 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus;
1391 ohci_soft_ed_t *sed = opipe->sed;
1392 int s;
1393
1394 s = splusb();
1395 #ifdef DIAGNOSTIC
1396 sed->ed->ed_flags |= LE(OHCI_ED_SKIP);
1397 if ((sed->ed->ed_tailp & LE(OHCI_TAILMASK)) !=
1398 (sed->ed->ed_headp & LE(OHCI_TAILMASK))) {
1399 ohci_physaddr_t td = sed->ed->ed_headp;
1400 ohci_soft_td_t *std;
1401 for (std = LIST_FIRST(&sc->sc_hash_tds[HASH(td)]);
1402 std != 0;
1403 std = LIST_NEXT(std, hnext))
1404 if (std->physaddr == td)
1405 break;
1406 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x "
1407 "tl=0x%x pipe=%p, std=%p\n", sed,
1408 (int)LE(sed->ed->ed_headp), (int)LE(sed->ed->ed_tailp),
1409 pipe, std);
1410 usb_delay_ms(&sc->sc_bus, 2);
1411 if ((sed->ed->ed_tailp & LE(OHCI_TAILMASK)) !=
1412 (sed->ed->ed_headp & LE(OHCI_TAILMASK)))
1413 printf("ohci_close_pipe: pipe still not empty\n");
1414 }
1415 #endif
1416 ohci_rem_ed(sed, head);
1417 splx(s);
1418 ohci_free_std(sc, opipe->tail);
1419 ohci_free_sed(sc, opipe->sed);
1420 }
1421
1422 /*
1423 * Abort a device request.
1424 * If this routine is called at splusb() it guarantees that the request
1425 * will be removed from the hardware scheduling and that the callback
1426 * for it will be called with USBD_CANCELLED status.
1427 * It's impossible to guarantee that the requested transfer will not
1428 * have happened since the hardware runs concurrently.
1429 * If the transaction has already happened we rely on the ordinary
1430 * interrupt processing to process it.
1431 */
1432 void
1433 ohci_abort_request(reqh)
1434 usbd_request_handle reqh;
1435 {
1436 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe;
1437 usbd_device_handle dev = opipe->pipe.device;
1438 ohci_softc_t *sc = (ohci_softc_t *)dev->bus;
1439 ohci_soft_ed_t *sed;
1440 ohci_soft_td_t *p, *n;
1441 int s;
1442
1443 DPRINTF(("ohci_abort_request: reqh=%p pipe=%p\n", reqh, opipe));
1444 s = splusb();
1445
1446 reqh->status = USBD_CANCELLED; /* mark as cancelled */
1447
1448 if (!reqh->hcpriv) {
1449 /* Not scheduled */
1450 reqh->xfercb(reqh);
1451 return;
1452 }
1453
1454 sed = opipe->sed;
1455 DPRINTFN(1,("ohci_abort_request: stop ed=%p\n", sed));
1456 sed->ed->ed_flags |= LE(OHCI_ED_SKIP); /* force hardware skip */
1457 delay(10); /* give HC hardware a little time */
1458
1459 /* if already processed by hardware let interrupt routine handle it */
1460 if ((sed->ed->ed_tailp & LE(OHCI_TAILMASK)) ==
1461 (sed->ed->ed_headp & LE(OHCI_TAILMASK))) {
1462 DPRINTF(("ohci_abort_request: request processed\n"));
1463 usb_delay_ms(dev->bus, 2);
1464 } else {
1465 p = reqh->hcpriv;
1466 #ifdef DIAGNOSTIC
1467 if (!p) {
1468 printf("ohci_abort_request: hcpriv==0\n");
1469 return;
1470 }
1471 #endif
1472 ohci_done(sc, reqh);
1473 for (; p->reqh == reqh; p = n) {
1474 n = p->nexttd;
1475 ohci_hash_rem_td(sc, p);
1476 ohci_free_std(sc, p);
1477 }
1478 DPRINTFN(2,("ohci_abort_request: set hd=%x, tl=%x\n",
1479 (int)LE(p->physaddr), (int)LE(sed->ed->ed_tailp)));
1480 sed->ed->ed_headp = p->physaddr; /* unlink TDs */
1481 }
1482
1483 sed->ed->ed_flags &= LE(~OHCI_ED_SKIP); /* remove hardware skip */
1484 splx(s);
1485 }
1486
1487 /*
1488 * Data structures and routines to emulate the root hub.
1489 */
1490 usb_device_descriptor_t ohci_devd = {
1491 USB_DEVICE_DESCRIPTOR_SIZE,
1492 UDESC_DEVICE, /* type */
1493 {0x00, 0x01}, /* USB version */
1494 UCLASS_HUB, /* class */
1495 USUBCLASS_HUB, /* subclass */
1496 0, /* protocol */
1497 64, /* max packet */
1498 {0},{0},{0x00,0x01}, /* device id */
1499 1,2,0, /* string indicies */
1500 1 /* # of configurations */
1501 };
1502
1503 usb_config_descriptor_t ohci_confd = {
1504 USB_CONFIG_DESCRIPTOR_SIZE,
1505 UDESC_CONFIG,
1506 {USB_CONFIG_DESCRIPTOR_SIZE +
1507 USB_INTERFACE_DESCRIPTOR_SIZE +
1508 USB_ENDPOINT_DESCRIPTOR_SIZE},
1509 1,
1510 1,
1511 0,
1512 UC_SELF_POWERED,
1513 0 /* max power */
1514 };
1515
1516 usb_interface_descriptor_t ohci_ifcd = {
1517 USB_INTERFACE_DESCRIPTOR_SIZE,
1518 UDESC_INTERFACE,
1519 0,
1520 0,
1521 1,
1522 UCLASS_HUB,
1523 USUBCLASS_HUB,
1524 0,
1525 0
1526 };
1527
1528 usb_endpoint_descriptor_t ohci_endpd = {
1529 USB_ENDPOINT_DESCRIPTOR_SIZE,
1530 UDESC_ENDPOINT,
1531 UE_IN | OHCI_INTR_ENDPT,
1532 UE_INTERRUPT,
1533 {8, 0}, /* max packet */
1534 255
1535 };
1536
1537 usb_hub_descriptor_t ohci_hubd = {
1538 USB_HUB_DESCRIPTOR_SIZE,
1539 UDESC_HUB,
1540 0,
1541 {0,0},
1542 0,
1543 0,
1544 {0},
1545 };
1546
1547 int
1548 ohci_str(p, l, s)
1549 usb_string_descriptor_t *p;
1550 int l;
1551 char *s;
1552 {
1553 int i;
1554
1555 if (l == 0)
1556 return (0);
1557 p->bLength = 2 * strlen(s) + 2;
1558 if (l == 1)
1559 return (1);
1560 p->bDescriptorType = UDESC_STRING;
1561 l -= 2;
1562 for (i = 0; s[i] && l > 1; i++, l -= 2)
1563 USETW2(p->bString[i], 0, s[i]);
1564 return (2*i+2);
1565 }
1566
1567 /*
1568 * Simulate a hardware hub by handling all the necessary requests.
1569 */
1570 usbd_status
1571 ohci_root_ctrl_transfer(reqh)
1572 usbd_request_handle reqh;
1573 {
1574 int s;
1575 usbd_status r;
1576
1577 s = splusb();
1578 r = usb_insert_transfer(reqh);
1579 splx(s);
1580 if (r != USBD_NORMAL_COMPLETION)
1581 return (r);
1582 else
1583 return (ohci_root_ctrl_start(reqh));
1584 }
1585
1586 usbd_status
1587 ohci_root_ctrl_start(reqh)
1588 usbd_request_handle reqh;
1589 {
1590 ohci_softc_t *sc = (ohci_softc_t *)reqh->pipe->device->bus;
1591 usb_device_request_t *req;
1592 void *buf;
1593 int port, i;
1594 int len, value, index, l, totlen = 0;
1595 usb_port_status_t ps;
1596 usb_hub_descriptor_t hubd;
1597 usbd_status r;
1598 u_int32_t v;
1599
1600 if (!reqh->isreq)
1601 /* XXX panic */
1602 return (USBD_INVAL);
1603 req = &reqh->request;
1604 buf = reqh->buffer;
1605
1606 DPRINTFN(4,("ohci_root_ctrl_control type=0x%02x request=%02x\n",
1607 req->bmRequestType, req->bRequest));
1608
1609 len = UGETW(req->wLength);
1610 value = UGETW(req->wValue);
1611 index = UGETW(req->wIndex);
1612 #define C(x,y) ((x) | ((y) << 8))
1613 switch(C(req->bRequest, req->bmRequestType)) {
1614 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
1615 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
1616 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
1617 /*
1618 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
1619 * for the integrated root hub.
1620 */
1621 break;
1622 case C(UR_GET_CONFIG, UT_READ_DEVICE):
1623 if (len > 0) {
1624 *(u_int8_t *)buf = sc->sc_conf;
1625 totlen = 1;
1626 }
1627 break;
1628 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
1629 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value));
1630 switch(value >> 8) {
1631 case UDESC_DEVICE:
1632 if ((value & 0xff) != 0) {
1633 r = USBD_IOERROR;
1634 goto ret;
1635 }
1636 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE);
1637 USETW(ohci_devd.idVendor, sc->sc_id_vendor);
1638 memcpy(buf, &ohci_devd, l);
1639 break;
1640 case UDESC_CONFIG:
1641 if ((value & 0xff) != 0) {
1642 r = USBD_IOERROR;
1643 goto ret;
1644 }
1645 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE);
1646 memcpy(buf, &ohci_confd, l);
1647 buf = (char *)buf + l;
1648 len -= l;
1649 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE);
1650 totlen += l;
1651 memcpy(buf, &ohci_ifcd, l);
1652 buf = (char *)buf + l;
1653 len -= l;
1654 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE);
1655 totlen += l;
1656 memcpy(buf, &ohci_endpd, l);
1657 break;
1658 case UDESC_STRING:
1659 if (len == 0)
1660 break;
1661 *(u_int8_t *)buf = 0;
1662 totlen = 1;
1663 switch (value & 0xff) {
1664 case 1: /* Vendor */
1665 totlen = ohci_str(buf, len, sc->sc_vendor);
1666 break;
1667 case 2: /* Product */
1668 totlen = ohci_str(buf, len, "OHCI root hub");
1669 break;
1670 }
1671 break;
1672 default:
1673 r = USBD_IOERROR;
1674 goto ret;
1675 }
1676 break;
1677 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
1678 if (len > 0) {
1679 *(u_int8_t *)buf = 0;
1680 totlen = 1;
1681 }
1682 break;
1683 case C(UR_GET_STATUS, UT_READ_DEVICE):
1684 if (len > 1) {
1685 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED);
1686 totlen = 2;
1687 }
1688 break;
1689 case C(UR_GET_STATUS, UT_READ_INTERFACE):
1690 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
1691 if (len > 1) {
1692 USETW(((usb_status_t *)buf)->wStatus, 0);
1693 totlen = 2;
1694 }
1695 break;
1696 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
1697 if (value >= USB_MAX_DEVICES) {
1698 r = USBD_IOERROR;
1699 goto ret;
1700 }
1701 sc->sc_addr = value;
1702 break;
1703 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
1704 if (value != 0 && value != 1) {
1705 r = USBD_IOERROR;
1706 goto ret;
1707 }
1708 sc->sc_conf = value;
1709 break;
1710 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
1711 break;
1712 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
1713 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
1714 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
1715 r = USBD_IOERROR;
1716 goto ret;
1717 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
1718 break;
1719 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
1720 break;
1721 /* Hub requests */
1722 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
1723 break;
1724 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
1725 DPRINTFN(8, ("ohci_root_ctrl_control: UR_CLEAR_PORT_FEATURE "
1726 "port=%d feature=%d\n",
1727 index, value));
1728 if (index < 1 || index > sc->sc_noport) {
1729 r = USBD_IOERROR;
1730 goto ret;
1731 }
1732 port = OHCI_RH_PORT_STATUS(index);
1733 switch(value) {
1734 case UHF_PORT_ENABLE:
1735 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS);
1736 break;
1737 case UHF_PORT_SUSPEND:
1738 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR);
1739 break;
1740 case UHF_PORT_POWER:
1741 OWRITE4(sc, port, UPS_LOW_SPEED);
1742 break;
1743 case UHF_C_PORT_CONNECTION:
1744 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16);
1745 break;
1746 case UHF_C_PORT_ENABLE:
1747 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16);
1748 break;
1749 case UHF_C_PORT_SUSPEND:
1750 OWRITE4(sc, port, UPS_C_SUSPEND << 16);
1751 break;
1752 case UHF_C_PORT_OVER_CURRENT:
1753 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16);
1754 break;
1755 case UHF_C_PORT_RESET:
1756 OWRITE4(sc, port, UPS_C_PORT_RESET << 16);
1757 break;
1758 default:
1759 r = USBD_IOERROR;
1760 goto ret;
1761 }
1762 switch(value) {
1763 case UHF_C_PORT_CONNECTION:
1764 case UHF_C_PORT_ENABLE:
1765 case UHF_C_PORT_SUSPEND:
1766 case UHF_C_PORT_OVER_CURRENT:
1767 case UHF_C_PORT_RESET:
1768 /* Enable RHSC interrupt if condition is cleared. */
1769 if ((OREAD4(sc, port) >> 16) == 0)
1770 ohci_rhsc_able(sc, 1);
1771 break;
1772 default:
1773 break;
1774 }
1775 break;
1776 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
1777 if (value != 0) {
1778 r = USBD_IOERROR;
1779 goto ret;
1780 }
1781 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A);
1782 hubd = ohci_hubd;
1783 hubd.bNbrPorts = sc->sc_noport;
1784 USETW(hubd.wHubCharacteristics,
1785 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH :
1786 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL)
1787 /* XXX overcurrent */
1788 );
1789 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v);
1790 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B);
1791 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8)
1792 hubd.DeviceRemovable[i++] = (u_int8_t)v;
1793 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i;
1794 l = min(len, hubd.bDescLength);
1795 totlen = l;
1796 memcpy(buf, &hubd, l);
1797 break;
1798 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
1799 if (len != 4) {
1800 r = USBD_IOERROR;
1801 goto ret;
1802 }
1803 memset(buf, 0, len); /* ? XXX */
1804 totlen = len;
1805 break;
1806 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
1807 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n",
1808 index));
1809 if (index < 1 || index > sc->sc_noport) {
1810 r = USBD_IOERROR;
1811 goto ret;
1812 }
1813 if (len != 4) {
1814 r = USBD_IOERROR;
1815 goto ret;
1816 }
1817 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index));
1818 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n",
1819 v));
1820 USETW(ps.wPortStatus, v);
1821 USETW(ps.wPortChange, v >> 16);
1822 l = min(len, sizeof ps);
1823 memcpy(buf, &ps, l);
1824 totlen = l;
1825 break;
1826 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
1827 r = USBD_IOERROR;
1828 goto ret;
1829 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
1830 break;
1831 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
1832 if (index < 1 || index > sc->sc_noport) {
1833 r = USBD_IOERROR;
1834 goto ret;
1835 }
1836 port = OHCI_RH_PORT_STATUS(index);
1837 switch(value) {
1838 case UHF_PORT_ENABLE:
1839 OWRITE4(sc, port, UPS_PORT_ENABLED);
1840 break;
1841 case UHF_PORT_SUSPEND:
1842 OWRITE4(sc, port, UPS_SUSPEND);
1843 break;
1844 case UHF_PORT_RESET:
1845 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n",
1846 index));
1847 OWRITE4(sc, port, UPS_RESET);
1848 for (i = 0; i < 10; i++) {
1849 usb_delay_ms(&sc->sc_bus, 10);
1850 if ((OREAD4(sc, port) & UPS_RESET) == 0)
1851 break;
1852 }
1853 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n",
1854 index, OREAD4(sc, port)));
1855 break;
1856 case UHF_PORT_POWER:
1857 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power "
1858 "%d\n", index));
1859 OWRITE4(sc, port, UPS_PORT_POWER);
1860 break;
1861 default:
1862 r = USBD_IOERROR;
1863 goto ret;
1864 }
1865 break;
1866 default:
1867 r = USBD_IOERROR;
1868 goto ret;
1869 }
1870 reqh->actlen = totlen;
1871 r = USBD_NORMAL_COMPLETION;
1872 ret:
1873 SIMPLEQ_REMOVE_HEAD(&reqh->pipe->queue, reqh, next);
1874 reqh->status = r;
1875 reqh->xfercb(reqh);
1876 usb_start_next(reqh->pipe);
1877 return (USBD_IN_PROGRESS);
1878 }
1879
1880 /* Abort a root control request. */
1881 void
1882 ohci_root_ctrl_abort(reqh)
1883 usbd_request_handle reqh;
1884 {
1885 /* Nothing to do, all transfers are synchronous. */
1886 }
1887
1888 /* Close the root pipe. */
1889 void
1890 ohci_root_ctrl_close(pipe)
1891 usbd_pipe_handle pipe;
1892 {
1893 DPRINTF(("ohci_root_ctrl_close\n"));
1894 /* Nothing to do. */
1895 }
1896
1897 usbd_status
1898 ohci_root_intr_transfer(reqh)
1899 usbd_request_handle reqh;
1900 {
1901 int s;
1902 usbd_status r;
1903
1904 s = splusb();
1905 r = usb_insert_transfer(reqh);
1906 splx(s);
1907 if (r != USBD_NORMAL_COMPLETION)
1908 return (r);
1909 else
1910 return (ohci_root_intr_start(reqh));
1911 }
1912
1913 usbd_status
1914 ohci_root_intr_start(reqh)
1915 usbd_request_handle reqh;
1916 {
1917 usbd_pipe_handle pipe = reqh->pipe;
1918 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus;
1919 struct ohci_pipe *upipe = (struct ohci_pipe *)pipe;
1920 usb_dma_t *dmap;
1921 usbd_status r;
1922 int len;
1923
1924 len = reqh->length;
1925 dmap = &upipe->u.intr.datadma;
1926 if (len == 0)
1927 return (USBD_INVAL); /* XXX should it be? */
1928
1929 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap);
1930 if (r != USBD_NORMAL_COMPLETION)
1931 return (r);
1932 sc->sc_intrreqh = reqh;
1933
1934 return (USBD_IN_PROGRESS);
1935 }
1936
1937 /* Abort a root interrupt request. */
1938 void
1939 ohci_root_intr_abort(reqh)
1940 usbd_request_handle reqh;
1941 {
1942 /* No need to abort. */
1943 }
1944
1945 /* Close the root pipe. */
1946 void
1947 ohci_root_intr_close(pipe)
1948 usbd_pipe_handle pipe;
1949 {
1950 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus;
1951
1952 DPRINTF(("ohci_root_intr_close\n"));
1953
1954 sc->sc_intrreqh = 0;
1955 }
1956
1957 /************************/
1958
1959 usbd_status
1960 ohci_device_ctrl_transfer(reqh)
1961 usbd_request_handle reqh;
1962 {
1963 int s;
1964 usbd_status r;
1965
1966 s = splusb();
1967 r = usb_insert_transfer(reqh);
1968 splx(s);
1969 if (r != USBD_NORMAL_COMPLETION)
1970 return (r);
1971 else
1972 return (ohci_device_ctrl_start(reqh));
1973 }
1974
1975 usbd_status
1976 ohci_device_ctrl_start(reqh)
1977 usbd_request_handle reqh;
1978 {
1979 ohci_softc_t *sc = (ohci_softc_t *)reqh->pipe->device->bus;
1980 usbd_status r;
1981
1982 if (!reqh->isreq) {
1983 /* XXX panic */
1984 printf("ohci_device_ctrl_transfer: not a request\n");
1985 return (USBD_INVAL);
1986 }
1987
1988 r = ohci_device_request(reqh);
1989 if (r != USBD_NORMAL_COMPLETION)
1990 return (r);
1991
1992 if (sc->sc_bus.use_polling)
1993 ohci_waitintr(sc, reqh);
1994 return (USBD_IN_PROGRESS);
1995 }
1996
1997 /* Abort a device control request. */
1998 void
1999 ohci_device_ctrl_abort(reqh)
2000 usbd_request_handle reqh;
2001 {
2002 DPRINTF(("ohci_device_ctrl_abort: reqh=%p\n", reqh));
2003 ohci_abort_request(reqh);
2004 }
2005
2006 /* Close a device control pipe. */
2007 void
2008 ohci_device_ctrl_close(pipe)
2009 usbd_pipe_handle pipe;
2010 {
2011 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus;
2012
2013 DPRINTF(("ohci_device_ctrl_close: pipe=%p\n", pipe));
2014 ohci_close_pipe(pipe, sc->sc_ctrl_head);
2015 }
2016
2017 /************************/
2018
2019 usbd_status
2020 ohci_device_bulk_transfer(reqh)
2021 usbd_request_handle reqh;
2022 {
2023 int s;
2024 usbd_status r;
2025
2026 s = splusb();
2027 r = usb_insert_transfer(reqh);
2028 splx(s);
2029 if (r != USBD_NORMAL_COMPLETION)
2030 return (r);
2031 else
2032 return (ohci_device_bulk_start(reqh));
2033 }
2034
2035 usbd_status
2036 ohci_device_bulk_start(reqh)
2037 usbd_request_handle reqh;
2038 {
2039 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe;
2040 usbd_device_handle dev = opipe->pipe.device;
2041 ohci_softc_t *sc = (ohci_softc_t *)dev->bus;
2042 int addr = dev->address;
2043 ohci_soft_td_t *xfer, *tail;
2044 ohci_soft_ed_t *sed;
2045 usb_dma_t *dmap;
2046 usbd_status r;
2047 int s, len, isread;
2048
2049 #ifdef DIAGNOSTIC
2050 if (reqh->isreq) {
2051 /* XXX panic */
2052 printf("ohci_device_bulk_start: a request\n");
2053 return (USBD_INVAL);
2054 }
2055 #endif
2056
2057 len = reqh->length;
2058 dmap = &opipe->u.bulk.datadma;
2059 isread = reqh->pipe->endpoint->edesc->bEndpointAddress & UE_IN;
2060 sed = opipe->sed;
2061
2062 DPRINTFN(4,("ohci_device_bulk_start: reqh=%p len=%d isread=%d "
2063 "flags=%d endpt=%d\n", reqh, len, isread, reqh->flags,
2064 reqh->pipe->endpoint->edesc->bEndpointAddress));
2065
2066 opipe->u.bulk.isread = isread;
2067 opipe->u.bulk.length = len;
2068
2069 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap);
2070 if (r != USBD_NORMAL_COMPLETION)
2071 goto ret1;
2072
2073 tail = ohci_alloc_std(sc);
2074 if (!tail) {
2075 r = USBD_NOMEM;
2076 goto ret2;
2077 }
2078 tail->reqh = 0;
2079
2080 /* Update device address */
2081 sed->ed->ed_flags = LE(
2082 (LE(sed->ed->ed_flags) & ~OHCI_ED_ADDRMASK) |
2083 OHCI_ED_SET_FA(addr));
2084
2085 /* Set up data transaction */
2086 xfer = opipe->tail;
2087 xfer->td->td_flags = LE(
2088 (isread ? OHCI_TD_IN : OHCI_TD_OUT) | OHCI_TD_NOCC |
2089 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY |
2090 (reqh->flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0));
2091 xfer->td->td_cbp = LE(DMAADDR(dmap));
2092 xfer->nexttd = tail;
2093 xfer->td->td_nexttd = LE(tail->physaddr);
2094 xfer->td->td_be = LE(LE(xfer->td->td_cbp) + len - 1);
2095 xfer->len = len;
2096 xfer->reqh = reqh;
2097 xfer->flags = OHCI_CALL_DONE | OHCI_SET_LEN;
2098 reqh->hcpriv = xfer;
2099
2100 if (!isread)
2101 memcpy(KERNADDR(dmap), reqh->buffer, len);
2102
2103 DPRINTFN(4,("ohci_device_bulk_start: ed_flags=0x%08x td_flags=0x%08x "
2104 "td_cbp=0x%08x td_be=0x%08x\n",
2105 (int)LE(sed->ed->ed_flags), (int)LE(xfer->td->td_flags),
2106 (int)LE(xfer->td->td_cbp), (int)LE(xfer->td->td_be)));
2107
2108 #ifdef USB_DEBUG
2109 if (ohcidebug > 4) {
2110 ohci_dump_ed(sed);
2111 ohci_dump_tds(xfer);
2112 }
2113 #endif
2114
2115 /* Insert ED in schedule */
2116 s = splusb();
2117 ohci_hash_add_td(sc, xfer);
2118 sed->ed->ed_tailp = LE(tail->physaddr);
2119 opipe->tail = tail;
2120 sed->ed->ed_flags &= LE(~OHCI_ED_SKIP);
2121 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF);
2122 if (reqh->timeout && !sc->sc_bus.use_polling) {
2123 usb_timeout(ohci_timeout, reqh,
2124 MS_TO_TICKS(reqh->timeout), reqh->timo_handle);
2125 }
2126
2127 #ifdef USB_DEBUG
2128 if (ohcidebug > 5) {
2129 delay(5000);
2130 printf("ohci_device_intr_transfer: status=%x\n",
2131 OREAD4(sc, OHCI_COMMAND_STATUS));
2132 ohci_dump_ed(sed);
2133 ohci_dump_tds(xfer);
2134 }
2135 #endif
2136
2137 splx(s);
2138
2139 return (USBD_IN_PROGRESS);
2140
2141 ret2:
2142 usb_freemem(sc->sc_dmatag, dmap);
2143 ret1:
2144 return (r);
2145 }
2146
2147 void
2148 ohci_device_bulk_abort(reqh)
2149 usbd_request_handle reqh;
2150 {
2151 DPRINTF(("ohci_device_bulk_abort: reqh=%p\n", reqh));
2152 ohci_abort_request(reqh);
2153 }
2154
2155 /*
2156 * Close a device bulk pipe.
2157 */
2158 void
2159 ohci_device_bulk_close(pipe)
2160 usbd_pipe_handle pipe;
2161 {
2162 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus;
2163
2164 DPRINTF(("ohci_device_bulk_close: pipe=%p\n", pipe));
2165 ohci_close_pipe(pipe, sc->sc_bulk_head);
2166 }
2167
2168 /************************/
2169
2170 usbd_status
2171 ohci_device_intr_transfer(reqh)
2172 usbd_request_handle reqh;
2173 {
2174 int s;
2175 usbd_status r;
2176
2177 s = splusb();
2178 r = usb_insert_transfer(reqh);
2179 splx(s);
2180 if (r != USBD_NORMAL_COMPLETION)
2181 return (r);
2182 else
2183 return (ohci_device_intr_start(reqh));
2184 }
2185
2186 usbd_status
2187 ohci_device_intr_start(reqh)
2188 usbd_request_handle reqh;
2189 {
2190 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe;
2191 usbd_device_handle dev = opipe->pipe.device;
2192 ohci_softc_t *sc = (ohci_softc_t *)dev->bus;
2193 ohci_soft_ed_t *sed = opipe->sed;
2194 ohci_soft_td_t *xfer, *tail;
2195 usb_dma_t *dmap;
2196 usbd_status r;
2197 int len;
2198 int s;
2199
2200 DPRINTFN(3, ("ohci_device_intr_transfer: reqh=%p buf=%p len=%d "
2201 "flags=%d priv=%p\n",
2202 reqh, reqh->buffer, reqh->length, reqh->flags, reqh->priv));
2203
2204 if (reqh->isreq)
2205 panic("ohci_device_intr_transfer: a request\n");
2206
2207 len = reqh->length;
2208 dmap = &opipe->u.intr.datadma;
2209 if (len == 0)
2210 return (USBD_INVAL); /* XXX should it be? */
2211
2212 xfer = opipe->tail;
2213 tail = ohci_alloc_std(sc);
2214 if (!tail) {
2215 r = USBD_NOMEM;
2216 goto ret1;
2217 }
2218 tail->reqh = 0;
2219
2220 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap);
2221 if (r != USBD_NORMAL_COMPLETION)
2222 goto ret2;
2223
2224 xfer->td->td_flags = LE(
2225 OHCI_TD_IN | OHCI_TD_NOCC |
2226 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY);
2227 if (reqh->flags & USBD_SHORT_XFER_OK)
2228 xfer->td->td_flags |= LE(OHCI_TD_R);
2229 xfer->td->td_cbp = LE(DMAADDR(dmap));
2230 xfer->nexttd = tail;
2231 xfer->td->td_nexttd = LE(tail->physaddr);
2232 xfer->td->td_be = LE(LE(xfer->td->td_cbp) + len - 1);
2233 xfer->len = len;
2234 xfer->reqh = reqh;
2235 xfer->flags = OHCI_CALL_DONE | OHCI_SET_LEN;
2236 reqh->hcpriv = xfer;
2237
2238 #if USB_DEBUG
2239 if (ohcidebug > 5) {
2240 printf("ohci_device_intr_transfer:\n");
2241 ohci_dump_ed(sed);
2242 ohci_dump_tds(xfer);
2243 }
2244 #endif
2245
2246 /* Insert ED in schedule */
2247 s = splusb();
2248 ohci_hash_add_td(sc, xfer);
2249 sed->ed->ed_tailp = LE(tail->physaddr);
2250 opipe->tail = tail;
2251 #if 0
2252 if (reqh->timeout && !sc->sc_bus.use_polling) {
2253 usb_timeout(ohci_timeout, reqh,
2254 MS_TO_TICKS(reqh->timeout), reqh->timo_handle);
2255 }
2256 #endif
2257 sed->ed->ed_flags &= LE(~OHCI_ED_SKIP);
2258
2259 #ifdef USB_DEBUG
2260 if (ohcidebug > 5) {
2261 delay(5000);
2262 printf("ohci_device_intr_transfer: status=%x\n",
2263 OREAD4(sc, OHCI_COMMAND_STATUS));
2264 ohci_dump_ed(sed);
2265 ohci_dump_tds(xfer);
2266 }
2267 #endif
2268 splx(s);
2269
2270 return (USBD_IN_PROGRESS);
2271
2272 ret2:
2273 ohci_free_std(sc, xfer);
2274 ret1:
2275 return (r);
2276 }
2277
2278 /* Abort a device control request. */
2279 void
2280 ohci_device_intr_abort(reqh)
2281 usbd_request_handle reqh;
2282 {
2283 if (reqh->pipe->intrreqh == reqh) {
2284 DPRINTF(("ohci_device_intr_abort: remove\n"));
2285 reqh->pipe->intrreqh = 0;
2286 }
2287 ohci_abort_request(reqh);
2288 }
2289
2290 /* Close a device interrupt pipe. */
2291 void
2292 ohci_device_intr_close(pipe)
2293 usbd_pipe_handle pipe;
2294 {
2295 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;
2296 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus;
2297 int nslots = opipe->u.intr.nslots;
2298 int pos = opipe->u.intr.pos;
2299 int j;
2300 ohci_soft_ed_t *p, *sed = opipe->sed;
2301 int s;
2302
2303 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n",
2304 pipe, nslots, pos));
2305 s = splusb();
2306 sed->ed->ed_flags |= LE(OHCI_ED_SKIP);
2307 if ((sed->ed->ed_tailp & LE(OHCI_TAILMASK)) !=
2308 (sed->ed->ed_headp & LE(OHCI_TAILMASK)))
2309 usb_delay_ms(&sc->sc_bus, 2);
2310
2311 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next)
2312 ;
2313 if (!p)
2314 panic("ohci_device_intr_close: ED not found\n");
2315 p->next = sed->next;
2316 p->ed->ed_nexted = sed->ed->ed_nexted;
2317 splx(s);
2318
2319 for (j = 0; j < nslots; j++)
2320 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS];
2321
2322 ohci_free_std(sc, opipe->tail);
2323 ohci_free_sed(sc, opipe->sed);
2324 }
2325
2326 usbd_status
2327 ohci_device_setintr(sc, opipe, ival)
2328 ohci_softc_t *sc;
2329 struct ohci_pipe *opipe;
2330 int ival;
2331 {
2332 int i, j, s, best;
2333 u_int npoll, slow, shigh, nslots;
2334 u_int bestbw, bw;
2335 ohci_soft_ed_t *hsed, *sed = opipe->sed;
2336
2337 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe));
2338 if (ival == 0) {
2339 printf("ohci_setintr: 0 interval\n");
2340 return (USBD_INVAL);
2341 }
2342
2343 npoll = OHCI_NO_INTRS;
2344 while (npoll > ival)
2345 npoll /= 2;
2346 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll));
2347
2348 /*
2349 * We now know which level in the tree the ED must go into.
2350 * Figure out which slot has most bandwidth left over.
2351 * Slots to examine:
2352 * npoll
2353 * 1 0
2354 * 2 1 2
2355 * 4 3 4 5 6
2356 * 8 7 8 9 10 11 12 13 14
2357 * N (N-1) .. (N-1+N-1)
2358 */
2359 slow = npoll-1;
2360 shigh = slow + npoll;
2361 nslots = OHCI_NO_INTRS / npoll;
2362 for (best = i = slow, bestbw = ~0; i < shigh; i++) {
2363 bw = 0;
2364 for (j = 0; j < nslots; j++)
2365 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS];
2366 if (bw < bestbw) {
2367 best = i;
2368 bestbw = bw;
2369 }
2370 }
2371 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n",
2372 best, slow, shigh, bestbw));
2373
2374 s = splusb();
2375 hsed = sc->sc_eds[best];
2376 sed->next = hsed->next;
2377 sed->ed->ed_nexted = hsed->ed->ed_nexted;
2378 hsed->next = sed;
2379 hsed->ed->ed_nexted = LE(sed->physaddr);
2380 splx(s);
2381
2382 for (j = 0; j < nslots; j++)
2383 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS];
2384 opipe->u.intr.nslots = nslots;
2385 opipe->u.intr.pos = best;
2386
2387 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe));
2388 return (USBD_NORMAL_COMPLETION);
2389 }
2390
2391