ohci.c revision 1.46
1 /* $NetBSD: ohci.c,v 1.46 1999/09/13 21:33:25 augustss Exp $ */ 2 3 /* 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (augustss (at) carlstedt.se) at 9 * Carlstedt Research & Technology. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * USB Open Host Controller driver. 42 * 43 * OHCI spec: ftp://ftp.compaq.com/pub/supportinformation/papers/hcir1_0a.exe 44 * USB spec: http://www.usb.org/developers/data/usb11.pdf 45 */ 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/malloc.h> 51 #if defined(__NetBSD__) || defined(__OpenBSD__) 52 #include <sys/device.h> 53 #elif defined(__FreeBSD__) 54 #include <sys/module.h> 55 #include <sys/bus.h> 56 #endif 57 #include <sys/proc.h> 58 #include <sys/queue.h> 59 #include <sys/select.h> 60 61 #include <machine/bus.h> 62 #include <machine/endian.h> 63 64 #include <dev/usb/usb.h> 65 #include <dev/usb/usbdi.h> 66 #include <dev/usb/usbdivar.h> 67 #include <dev/usb/usb_mem.h> 68 #include <dev/usb/usb_quirks.h> 69 70 #include <dev/usb/ohcireg.h> 71 #include <dev/usb/ohcivar.h> 72 73 #if defined(__FreeBSD__) 74 #include <machine/clock.h> 75 76 #define delay(d) DELAY(d) 77 78 #endif 79 80 #if defined(__OpenBSD__) 81 struct cfdriver ohci_cd = { 82 NULL, "ohci", DV_DULL 83 }; 84 #endif 85 86 /* 87 * The OHCI controller is little endian, so on big endian machines 88 * the data strored in memory needs to be swapped. 89 */ 90 #if BYTE_ORDER == BIG_ENDIAN 91 #define LE(x) (bswap32(x)) 92 #else 93 #define LE(x) (x) 94 #endif 95 96 struct ohci_pipe; 97 98 ohci_soft_ed_t *ohci_alloc_sed __P((ohci_softc_t *)); 99 void ohci_free_sed __P((ohci_softc_t *, ohci_soft_ed_t *)); 100 101 ohci_soft_td_t *ohci_alloc_std __P((ohci_softc_t *)); 102 void ohci_free_std __P((ohci_softc_t *, ohci_soft_td_t *)); 103 104 void ohci_power __P((int, void *)); 105 usbd_status ohci_open __P((usbd_pipe_handle)); 106 void ohci_poll __P((struct usbd_bus *)); 107 void ohci_waitintr __P((ohci_softc_t *, usbd_request_handle)); 108 void ohci_rhsc __P((ohci_softc_t *, usbd_request_handle)); 109 void ohci_process_done __P((ohci_softc_t *, ohci_physaddr_t)); 110 111 usbd_status ohci_device_request __P((usbd_request_handle reqh)); 112 void ohci_add_ed __P((ohci_soft_ed_t *, ohci_soft_ed_t *)); 113 void ohci_rem_ed __P((ohci_soft_ed_t *, ohci_soft_ed_t *)); 114 void ohci_hash_add_td __P((ohci_softc_t *, ohci_soft_td_t *)); 115 void ohci_hash_rem_td __P((ohci_softc_t *, ohci_soft_td_t *)); 116 ohci_soft_td_t *ohci_hash_find_td __P((ohci_softc_t *, ohci_physaddr_t)); 117 118 usbd_status ohci_allocm __P((struct usbd_bus *, usb_dma_t *, u_int32_t)); 119 void ohci_freem __P((struct usbd_bus *, usb_dma_t *)); 120 121 usbd_status ohci_root_ctrl_transfer __P((usbd_request_handle)); 122 usbd_status ohci_root_ctrl_start __P((usbd_request_handle)); 123 void ohci_root_ctrl_abort __P((usbd_request_handle)); 124 void ohci_root_ctrl_close __P((usbd_pipe_handle)); 125 126 usbd_status ohci_root_intr_transfer __P((usbd_request_handle)); 127 usbd_status ohci_root_intr_start __P((usbd_request_handle)); 128 void ohci_root_intr_abort __P((usbd_request_handle)); 129 void ohci_root_intr_close __P((usbd_pipe_handle)); 130 void ohci_root_intr_done __P((usbd_request_handle)); 131 132 usbd_status ohci_device_ctrl_transfer __P((usbd_request_handle)); 133 usbd_status ohci_device_ctrl_start __P((usbd_request_handle)); 134 void ohci_device_ctrl_abort __P((usbd_request_handle)); 135 void ohci_device_ctrl_close __P((usbd_pipe_handle)); 136 void ohci_device_ctrl_done __P((usbd_request_handle)); 137 138 usbd_status ohci_device_bulk_transfer __P((usbd_request_handle)); 139 usbd_status ohci_device_bulk_start __P((usbd_request_handle)); 140 void ohci_device_bulk_abort __P((usbd_request_handle)); 141 void ohci_device_bulk_close __P((usbd_pipe_handle)); 142 void ohci_device_bulk_done __P((usbd_request_handle)); 143 144 usbd_status ohci_device_intr_transfer __P((usbd_request_handle)); 145 usbd_status ohci_device_intr_start __P((usbd_request_handle)); 146 void ohci_device_intr_abort __P((usbd_request_handle)); 147 void ohci_device_intr_close __P((usbd_pipe_handle)); 148 void ohci_device_intr_done __P((usbd_request_handle)); 149 150 usbd_status ohci_device_isoc_transfer __P((usbd_request_handle)); 151 usbd_status ohci_device_isoc_start __P((usbd_request_handle)); 152 void ohci_device_isoc_abort __P((usbd_request_handle)); 153 void ohci_device_isoc_close __P((usbd_pipe_handle)); 154 void ohci_device_isoc_done __P((usbd_request_handle)); 155 156 usbd_status ohci_device_setintr __P((ohci_softc_t *sc, 157 struct ohci_pipe *pipe, int ival)); 158 159 int ohci_str __P((usb_string_descriptor_t *, int, char *)); 160 161 void ohci_timeout __P((void *)); 162 void ohci_rhsc_able __P((ohci_softc_t *, int)); 163 164 void ohci_close_pipe __P((usbd_pipe_handle pipe, 165 ohci_soft_ed_t *head)); 166 void ohci_abort_req __P((usbd_request_handle reqh, 167 usbd_status status)); 168 void ohci_abort_req_end __P((void *)); 169 170 void ohci_device_clear_toggle __P((usbd_pipe_handle pipe)); 171 void ohci_noop __P((usbd_pipe_handle pipe)); 172 173 #ifdef USB_DEBUG 174 ohci_softc_t *thesc; 175 void ohci_dumpregs __P((ohci_softc_t *)); 176 void ohci_dump_tds __P((ohci_soft_td_t *)); 177 void ohci_dump_td __P((ohci_soft_td_t *)); 178 void ohci_dump_ed __P((ohci_soft_ed_t *)); 179 #endif 180 181 #define OWRITE4(sc, r, x) bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)) 182 #define OREAD4(sc, r) bus_space_read_4((sc)->iot, (sc)->ioh, (r)) 183 #define OREAD2(sc, r) bus_space_read_2((sc)->iot, (sc)->ioh, (r)) 184 185 /* Reverse the bits in a value 0 .. 31 */ 186 static u_int8_t revbits[OHCI_NO_INTRS] = 187 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 188 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 189 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 190 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 191 192 struct ohci_pipe { 193 struct usbd_pipe pipe; 194 ohci_soft_ed_t *sed; 195 ohci_soft_td_t *tail; 196 /* Info needed for different pipe kinds. */ 197 union { 198 /* Control pipe */ 199 struct { 200 usb_dma_t reqdma; 201 u_int length; 202 ohci_soft_td_t *setup, *xfer, *stat; 203 } ctl; 204 /* Interrupt pipe */ 205 struct { 206 int nslots; 207 int pos; 208 } intr; 209 /* Bulk pipe */ 210 struct { 211 u_int length; 212 int isread; 213 } bulk; 214 /* Iso pipe */ 215 struct iso { 216 int xxxxx; 217 } iso; 218 } u; 219 }; 220 221 #define OHCI_INTR_ENDPT 1 222 223 struct usbd_bus_methods ohci_bus_methods = { 224 ohci_open, 225 ohci_poll, 226 ohci_allocm, 227 ohci_freem, 228 }; 229 230 struct usbd_pipe_methods ohci_root_ctrl_methods = { 231 ohci_root_ctrl_transfer, 232 ohci_root_ctrl_start, 233 ohci_root_ctrl_abort, 234 ohci_root_ctrl_close, 235 ohci_noop, 236 0, 237 }; 238 239 struct usbd_pipe_methods ohci_root_intr_methods = { 240 ohci_root_intr_transfer, 241 ohci_root_intr_start, 242 ohci_root_intr_abort, 243 ohci_root_intr_close, 244 ohci_noop, 245 ohci_root_intr_done, 246 }; 247 248 struct usbd_pipe_methods ohci_device_ctrl_methods = { 249 ohci_device_ctrl_transfer, 250 ohci_device_ctrl_start, 251 ohci_device_ctrl_abort, 252 ohci_device_ctrl_close, 253 ohci_noop, 254 ohci_device_ctrl_done, 255 }; 256 257 struct usbd_pipe_methods ohci_device_intr_methods = { 258 ohci_device_intr_transfer, 259 ohci_device_intr_start, 260 ohci_device_intr_abort, 261 ohci_device_intr_close, 262 ohci_device_clear_toggle, 263 ohci_device_intr_done, 264 }; 265 266 struct usbd_pipe_methods ohci_device_bulk_methods = { 267 ohci_device_bulk_transfer, 268 ohci_device_bulk_start, 269 ohci_device_bulk_abort, 270 ohci_device_bulk_close, 271 ohci_device_clear_toggle, 272 ohci_device_bulk_done, 273 }; 274 275 #if 0 276 struct usbd_pipe_methods ohci_device_isoc_methods = { 277 ohci_device_isoc_transfer, 278 ohci_device_isoc_start, 279 ohci_device_isoc_abort, 280 ohci_device_isoc_close, 281 ohci_noop, 282 ohci_device_isoc_done, 283 }; 284 #endif 285 286 ohci_soft_ed_t * 287 ohci_alloc_sed(sc) 288 ohci_softc_t *sc; 289 { 290 ohci_soft_ed_t *sed; 291 usbd_status r; 292 int i, offs; 293 usb_dma_t dma; 294 295 if (!sc->sc_freeeds) { 296 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n")); 297 r = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 298 OHCI_ED_ALIGN, &dma); 299 if (r != USBD_NORMAL_COMPLETION) 300 return (0); 301 for(i = 0; i < OHCI_SED_CHUNK; i++) { 302 offs = i * OHCI_SED_SIZE; 303 sed = (ohci_soft_ed_t *)((char *)KERNADDR(&dma) +offs); 304 sed->physaddr = DMAADDR(&dma) + offs; 305 sed->next = sc->sc_freeeds; 306 sc->sc_freeeds = sed; 307 } 308 } 309 sed = sc->sc_freeeds; 310 sc->sc_freeeds = sed->next; 311 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 312 sed->next = 0; 313 return (sed); 314 } 315 316 void 317 ohci_free_sed(sc, sed) 318 ohci_softc_t *sc; 319 ohci_soft_ed_t *sed; 320 { 321 sed->next = sc->sc_freeeds; 322 sc->sc_freeeds = sed; 323 } 324 325 ohci_soft_td_t * 326 ohci_alloc_std(sc) 327 ohci_softc_t *sc; 328 { 329 ohci_soft_td_t *std; 330 usbd_status r; 331 int i, offs; 332 usb_dma_t dma; 333 334 if (!sc->sc_freetds) { 335 DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n")); 336 r = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 337 OHCI_TD_ALIGN, &dma); 338 if (r != USBD_NORMAL_COMPLETION) 339 return (0); 340 for(i = 0; i < OHCI_STD_CHUNK; i++) { 341 offs = i * OHCI_STD_SIZE; 342 std = (ohci_soft_td_t *)((char *)KERNADDR(&dma) +offs); 343 std->physaddr = DMAADDR(&dma) + offs; 344 std->nexttd = sc->sc_freetds; 345 sc->sc_freetds = std; 346 } 347 } 348 std = sc->sc_freetds; 349 sc->sc_freetds = std->nexttd; 350 memset(&std->td, 0, sizeof(ohci_td_t)); 351 std->nexttd = 0; 352 return (std); 353 } 354 355 void 356 ohci_free_std(sc, std) 357 ohci_softc_t *sc; 358 ohci_soft_td_t *std; 359 { 360 std->nexttd = sc->sc_freetds; 361 sc->sc_freetds = std; 362 } 363 364 usbd_status 365 ohci_init(sc) 366 ohci_softc_t *sc; 367 { 368 ohci_soft_ed_t *sed, *psed; 369 usbd_status r; 370 int rev; 371 int i; 372 u_int32_t s, ctl, ival, hcr, fm, per; 373 374 DPRINTF(("ohci_init: start\n")); 375 rev = OREAD4(sc, OHCI_REVISION); 376 #if defined(__OpenBSD__) 377 printf(", OHCI version %d.%d%s\n", 378 #else 379 printf("%s: OHCI version %d.%d%s\n", USBDEVNAME(sc->sc_bus.bdev), 380 #endif 381 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 382 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 383 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 384 printf("%s: unsupported OHCI revision\n", 385 USBDEVNAME(sc->sc_bus.bdev)); 386 return (USBD_INVAL); 387 } 388 389 for (i = 0; i < OHCI_HASH_SIZE; i++) 390 LIST_INIT(&sc->sc_hash_tds[i]); 391 392 /* Allocate the HCCA area. */ 393 r = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 394 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 395 if (r != USBD_NORMAL_COMPLETION) 396 return (r); 397 sc->sc_hcca = (struct ohci_hcca *)KERNADDR(&sc->sc_hccadma); 398 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 399 400 sc->sc_eintrs = OHCI_NORMAL_INTRS; 401 402 sc->sc_ctrl_head = ohci_alloc_sed(sc); 403 if (!sc->sc_ctrl_head) { 404 r = USBD_NOMEM; 405 goto bad1; 406 } 407 sc->sc_ctrl_head->ed.ed_flags |= LE(OHCI_ED_SKIP); 408 409 sc->sc_bulk_head = ohci_alloc_sed(sc); 410 if (!sc->sc_bulk_head) { 411 r = USBD_NOMEM; 412 goto bad2; 413 } 414 sc->sc_bulk_head->ed.ed_flags |= LE(OHCI_ED_SKIP); 415 416 /* Allocate all the dummy EDs that make up the interrupt tree. */ 417 for (i = 0; i < OHCI_NO_EDS; i++) { 418 sed = ohci_alloc_sed(sc); 419 if (!sed) { 420 while (--i >= 0) 421 ohci_free_sed(sc, sc->sc_eds[i]); 422 r = USBD_NOMEM; 423 goto bad3; 424 } 425 /* All ED fields are set to 0. */ 426 sc->sc_eds[i] = sed; 427 sed->ed.ed_flags |= LE(OHCI_ED_SKIP); 428 if (i != 0) { 429 psed = sc->sc_eds[(i-1) / 2]; 430 sed->next = psed; 431 sed->ed.ed_nexted = LE(psed->physaddr); 432 } 433 } 434 /* 435 * Fill HCCA interrupt table. The bit reversal is to get 436 * the tree set up properly to spread the interrupts. 437 */ 438 for (i = 0; i < OHCI_NO_INTRS; i++) 439 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 440 LE(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 441 442 /* Determine in what context we are running. */ 443 ctl = OREAD4(sc, OHCI_CONTROL); 444 if (ctl & OHCI_IR) { 445 /* SMM active, request change */ 446 DPRINTF(("ohci_init: SMM active, request owner change\n")); 447 s = OREAD4(sc, OHCI_COMMAND_STATUS); 448 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 449 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 450 delay(1000); 451 ctl = OREAD4(sc, OHCI_CONTROL); 452 } 453 if ((ctl & OHCI_IR) == 0) { 454 printf("%s: SMM does not respond, resetting\n", 455 USBDEVNAME(sc->sc_bus.bdev)); 456 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 457 goto reset; 458 } 459 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 460 /* BIOS started controller. */ 461 DPRINTF(("ohci_init: BIOS active\n")); 462 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 463 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL); 464 delay(USB_RESUME_DELAY * 1000); 465 } 466 } else { 467 DPRINTF(("ohci_init: cold started\n")); 468 reset: 469 /* Controller was cold started. */ 470 delay(USB_BUS_RESET_DELAY * 1000); 471 } 472 473 /* 474 * This reset should not be necessary according to the OHCI spec, but 475 * without it some controllers do not start. 476 */ 477 DPRINTF(("%s: resetting\n", USBDEVNAME(sc->sc_bus.bdev))); 478 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 479 delay(USB_BUS_RESET_DELAY * 1000); 480 481 /* We now own the host controller and the bus has been reset. */ 482 ival = OHCI_GET_IVAL(OREAD4(sc, OHCI_FM_INTERVAL)); 483 484 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 485 /* Nominal time for a reset is 10 us. */ 486 for (i = 0; i < 10; i++) { 487 delay(10); 488 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 489 if (!hcr) 490 break; 491 } 492 if (hcr) { 493 printf("%s: reset timeout\n", USBDEVNAME(sc->sc_bus.bdev)); 494 r = USBD_IOERROR; 495 goto bad3; 496 } 497 #ifdef USB_DEBUG 498 thesc = sc; 499 if (ohcidebug > 15) 500 ohci_dumpregs(sc); 501 #endif 502 503 /* The controller is now in suspend state, we have 2ms to finish. */ 504 505 /* Set up HC registers. */ 506 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma)); 507 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 508 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 509 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 510 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 511 ctl = OREAD4(sc, OHCI_CONTROL); 512 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 513 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 514 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL; 515 /* And finally start it! */ 516 OWRITE4(sc, OHCI_CONTROL, ctl); 517 518 /* 519 * The controller is now OPERATIONAL. Set a some final 520 * registers that should be set earlier, but that the 521 * controller ignores when in the SUSPEND state. 522 */ 523 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 524 fm |= OHCI_FSMPS(ival) | ival; 525 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 526 per = OHCI_PERIODIC(ival); /* 90% periodic */ 527 OWRITE4(sc, OHCI_PERIODIC_START, per); 528 529 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 530 531 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 532 533 #ifdef USB_DEBUG 534 if (ohcidebug > 5) 535 ohci_dumpregs(sc); 536 #endif 537 538 /* Set up the bus struct. */ 539 sc->sc_bus.methods = &ohci_bus_methods; 540 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe); 541 542 powerhook_establish(ohci_power, sc); 543 544 return (USBD_NORMAL_COMPLETION); 545 546 bad3: 547 ohci_free_sed(sc, sc->sc_ctrl_head); 548 bad2: 549 ohci_free_sed(sc, sc->sc_bulk_head); 550 bad1: 551 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 552 return (r); 553 } 554 555 usbd_status 556 ohci_allocm(bus, dma, size) 557 struct usbd_bus *bus; 558 usb_dma_t *dma; 559 u_int32_t size; 560 { 561 struct ohci_softc *sc = (struct ohci_softc *)bus; 562 563 return (usb_allocmem(&sc->sc_bus, size, 0, dma)); 564 } 565 566 void 567 ohci_freem(bus, dma) 568 struct usbd_bus *bus; 569 usb_dma_t *dma; 570 { 571 struct ohci_softc *sc = (struct ohci_softc *)bus; 572 573 usb_freemem(&sc->sc_bus, dma); 574 } 575 576 #if !defined(__OpenBSD__) 577 void 578 ohci_power(why, v) 579 int why; 580 void *v; 581 { 582 #ifdef USB_DEBUG 583 ohci_softc_t *sc = v; 584 585 DPRINTF(("ohci_power: sc=%p, why=%d\n", sc, why)); 586 /* XXX should suspend/resume */ 587 ohci_dumpregs(sc); 588 #endif 589 } 590 #endif /* !defined(__OpenBSD__) */ 591 592 #ifdef USB_DEBUG 593 void ohcidump(void); 594 void ohcidump(void) { ohci_dumpregs(thesc); } 595 596 void 597 ohci_dumpregs(sc) 598 ohci_softc_t *sc; 599 { 600 DPRINTF(("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 601 OREAD4(sc, OHCI_REVISION), 602 OREAD4(sc, OHCI_CONTROL), 603 OREAD4(sc, OHCI_COMMAND_STATUS))); 604 DPRINTF((" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 605 OREAD4(sc, OHCI_INTERRUPT_STATUS), 606 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 607 OREAD4(sc, OHCI_INTERRUPT_DISABLE))); 608 DPRINTF((" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 609 OREAD4(sc, OHCI_HCCA), 610 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 611 OREAD4(sc, OHCI_CONTROL_HEAD_ED))); 612 DPRINTF((" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 613 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 614 OREAD4(sc, OHCI_BULK_HEAD_ED), 615 OREAD4(sc, OHCI_BULK_CURRENT_ED))); 616 DPRINTF((" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 617 OREAD4(sc, OHCI_DONE_HEAD), 618 OREAD4(sc, OHCI_FM_INTERVAL), 619 OREAD4(sc, OHCI_FM_REMAINING))); 620 DPRINTF((" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 621 OREAD4(sc, OHCI_FM_NUMBER), 622 OREAD4(sc, OHCI_PERIODIC_START), 623 OREAD4(sc, OHCI_LS_THRESHOLD))); 624 DPRINTF((" desca=0x%08x descb=0x%08x stat=0x%08x\n", 625 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 626 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 627 OREAD4(sc, OHCI_RH_STATUS))); 628 DPRINTF((" port1=0x%08x port2=0x%08x\n", 629 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 630 OREAD4(sc, OHCI_RH_PORT_STATUS(2)))); 631 DPRINTF((" HCCA: frame_number=0x%04x done_head=0x%08x\n", 632 LE(sc->sc_hcca->hcca_frame_number), 633 LE(sc->sc_hcca->hcca_done_head))); 634 } 635 #endif 636 637 int 638 ohci_intr(p) 639 void *p; 640 { 641 ohci_softc_t *sc = p; 642 u_int32_t intrs, eintrs; 643 ohci_physaddr_t done; 644 645 /* In case the interrupt occurs before initialization has completed. */ 646 if (sc == NULL || sc->sc_hcca == NULL) { 647 #ifdef DIAGNOSTIC 648 printf("ohci_intr: sc->sc_hcca == NULL\n"); 649 #endif 650 return (0); 651 } 652 653 intrs = 0; 654 done = LE(sc->sc_hcca->hcca_done_head); 655 if (done != 0) { 656 sc->sc_hcca->hcca_done_head = 0; 657 if (done & ~OHCI_DONE_INTRS) 658 intrs = OHCI_WDH; 659 if (done & OHCI_DONE_INTRS) 660 intrs |= OREAD4(sc, OHCI_INTERRUPT_STATUS); 661 } else 662 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 663 if (!intrs) 664 return (0); 665 intrs &= ~OHCI_MIE; 666 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs); /* Acknowledge */ 667 eintrs = intrs & sc->sc_eintrs; 668 if (!eintrs) 669 return (0); 670 671 sc->sc_bus.intr_context++; 672 sc->sc_bus.no_intrs++; 673 DPRINTFN(7, ("ohci_intr: sc=%p intrs=%x(%x) eintr=%x\n", 674 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), 675 (u_int)eintrs)); 676 677 if (eintrs & OHCI_SO) { 678 printf("%s: scheduling overrun\n",USBDEVNAME(sc->sc_bus.bdev)); 679 /* XXX do what */ 680 intrs &= ~OHCI_SO; 681 } 682 if (eintrs & OHCI_WDH) { 683 ohci_process_done(sc, done &~ OHCI_DONE_INTRS); 684 intrs &= ~OHCI_WDH; 685 } 686 if (eintrs & OHCI_RD) { 687 printf("%s: resume detect\n", USBDEVNAME(sc->sc_bus.bdev)); 688 /* XXX process resume detect */ 689 } 690 if (eintrs & OHCI_UE) { 691 printf("%s: unrecoverable error, controller halted\n", 692 USBDEVNAME(sc->sc_bus.bdev)); 693 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 694 /* XXX what else */ 695 } 696 if (eintrs & OHCI_RHSC) { 697 ohci_rhsc(sc, sc->sc_intrreqh); 698 intrs &= ~OHCI_RHSC; 699 700 /* 701 * Disable RHSC interrupt for now, because it will be 702 * on until the port has been reset. 703 */ 704 ohci_rhsc_able(sc, 0); 705 } 706 707 sc->sc_bus.intr_context--; 708 709 /* Block unprocessed interrupts. XXX */ 710 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, intrs); 711 sc->sc_eintrs &= ~intrs; 712 713 return (1); 714 } 715 716 void 717 ohci_rhsc_able(sc, on) 718 ohci_softc_t *sc; 719 int on; 720 { 721 DPRINTFN(4, ("ohci_rhsc_able: on=%d\n", on)); 722 if (on) { 723 sc->sc_eintrs |= OHCI_RHSC; 724 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 725 } else { 726 sc->sc_eintrs &= ~OHCI_RHSC; 727 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_RHSC); 728 } 729 } 730 731 #ifdef USB_DEBUG 732 char *ohci_cc_strs[] = { 733 "NO_ERROR", 734 "CRC", 735 "BIT_STUFFING", 736 "DATA_TOGGLE_MISMATCH", 737 "STALL", 738 "DEVICE_NOT_RESPONDING", 739 "PID_CHECK_FAILURE", 740 "UNEXPECTED_PID", 741 "DATA_OVERRUN", 742 "DATA_UNDERRUN", 743 "BUFFER_OVERRUN", 744 "BUFFER_UNDERRUN", 745 "NOT_ACCESSED", 746 }; 747 #endif 748 749 void 750 ohci_process_done(sc, done) 751 ohci_softc_t *sc; 752 ohci_physaddr_t done; 753 { 754 ohci_soft_td_t *std, *sdone; 755 usbd_request_handle reqh; 756 int len, cc; 757 758 DPRINTFN(10,("ohci_process_done: done=0x%08lx\n", (u_long)done)); 759 760 /* Reverse the done list. */ 761 for (sdone = 0; done; done = LE(std->td.td_nexttd)) { 762 std = ohci_hash_find_td(sc, done); 763 std->dnext = sdone; 764 sdone = std; 765 } 766 767 #ifdef USB_DEBUG 768 if (ohcidebug > 10) { 769 DPRINTF(("ohci_process_done: TD done:\n")); 770 ohci_dump_tds(sdone); 771 } 772 #endif 773 774 for (std = sdone; std; std = std->dnext) { 775 reqh = std->reqh; 776 DPRINTFN(10, ("ohci_process_done: std=%p reqh=%p hcpriv=%p\n", 777 std, reqh, reqh->hcpriv)); 778 cc = OHCI_TD_GET_CC(LE(std->td.td_flags)); 779 usb_untimeout(ohci_timeout, reqh, reqh->timo_handle); 780 if (reqh->status == USBD_CANCELLED || 781 reqh->status == USBD_TIMEOUT) { 782 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 783 reqh)); 784 /* Handled by abort routine. */ 785 continue; 786 } else if (cc == OHCI_CC_NO_ERROR) { 787 len = std->len; 788 if (std->td.td_cbp != 0) 789 len -= LE(std->td.td_be) - 790 LE(std->td.td_cbp) + 1; 791 if (std->flags & OHCI_SET_LEN) 792 reqh->actlen = len; 793 if (std->flags & OHCI_CALL_DONE) { 794 reqh->status = USBD_NORMAL_COMPLETION; 795 usb_transfer_complete(reqh); 796 } 797 } else { 798 ohci_soft_td_t *p, *n; 799 struct ohci_pipe *opipe = 800 (struct ohci_pipe *)reqh->pipe; 801 DPRINTFN(-1,("ohci_process_done: error cc=%d (%s)\n", 802 OHCI_TD_GET_CC(LE(std->td.td_flags)), 803 ohci_cc_strs[OHCI_TD_GET_CC(LE(std->td.td_flags))])); 804 /* 805 * Endpoint is halted. First unlink all the TDs 806 * belonging to the failed transfer, and then restart 807 * the endpoint. 808 */ 809 for (p = std->nexttd; p->reqh == reqh; p = n) { 810 n = p->nexttd; 811 ohci_hash_rem_td(sc, p); 812 ohci_free_std(sc, p); 813 } 814 /* clear halt */ 815 opipe->sed->ed.ed_headp = LE(p->physaddr); 816 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 817 818 if (cc == OHCI_CC_STALL) 819 reqh->status = USBD_STALLED; 820 else 821 reqh->status = USBD_IOERROR; 822 usb_transfer_complete(reqh); 823 } 824 ohci_hash_rem_td(sc, std); 825 ohci_free_std(sc, std); 826 } 827 } 828 829 void 830 ohci_device_ctrl_done(reqh) 831 usbd_request_handle reqh; 832 { 833 DPRINTFN(10,("ohci_ctrl_done: reqh=%p\n", reqh)); 834 835 #ifdef DIAGNOSTIC 836 if (!(reqh->rqflags & URQ_REQUEST)) { 837 panic("ohci_ctrl_done: not a request\n"); 838 } 839 #endif 840 reqh->hcpriv = 0; 841 } 842 843 void 844 ohci_device_intr_done(reqh) 845 usbd_request_handle reqh; 846 { 847 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 848 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 849 ohci_soft_ed_t *sed = opipe->sed; 850 ohci_soft_td_t *xfer, *tail; 851 852 853 DPRINTFN(10,("ohci_intr_done: reqh=%p, actlen=%d\n", 854 reqh, reqh->actlen)); 855 856 reqh->hcpriv = 0; 857 858 if (reqh->pipe->repeat) { 859 xfer = opipe->tail; 860 tail = ohci_alloc_std(sc); /* XXX should reuse TD */ 861 if (!tail) { 862 reqh->status = USBD_NOMEM; 863 return; 864 } 865 tail->reqh = 0; 866 867 xfer->td.td_flags = LE( 868 OHCI_TD_IN | OHCI_TD_NOCC | 869 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 870 if (reqh->flags & USBD_SHORT_XFER_OK) 871 xfer->td.td_flags |= LE(OHCI_TD_R); 872 xfer->td.td_cbp = LE(DMAADDR(&reqh->dmabuf)); 873 xfer->nexttd = tail; 874 xfer->td.td_nexttd = LE(tail->physaddr); 875 xfer->td.td_be = LE(LE(xfer->td.td_cbp) + reqh->length - 1); 876 xfer->len = reqh->length; 877 xfer->reqh = reqh; 878 xfer->flags = OHCI_CALL_DONE | OHCI_SET_LEN; 879 reqh->hcpriv = xfer; 880 881 ohci_hash_add_td(sc, xfer); 882 sed->ed.ed_tailp = LE(tail->physaddr); 883 opipe->tail = tail; 884 } 885 } 886 887 void 888 ohci_device_bulk_done(reqh) 889 usbd_request_handle reqh; 890 { 891 DPRINTFN(10,("ohci_bulk_done: reqh=%p, actlen=%d\n", 892 reqh, reqh->actlen)); 893 894 reqh->hcpriv = 0; 895 } 896 897 void 898 ohci_rhsc(sc, reqh) 899 ohci_softc_t *sc; 900 usbd_request_handle reqh; 901 { 902 usbd_pipe_handle pipe; 903 struct ohci_pipe *opipe; 904 u_char *p; 905 int i, m; 906 int hstatus; 907 908 hstatus = OREAD4(sc, OHCI_RH_STATUS); 909 DPRINTF(("ohci_rhsc: sc=%p reqh=%p hstatus=0x%08x\n", 910 sc, reqh, hstatus)); 911 912 if (reqh == 0) { 913 /* Just ignore the change. */ 914 return; 915 } 916 917 pipe = reqh->pipe; 918 opipe = (struct ohci_pipe *)pipe; 919 920 p = KERNADDR(&reqh->dmabuf); 921 m = min(sc->sc_noport, reqh->length * 8 - 1); 922 memset(p, 0, reqh->length); 923 for (i = 1; i <= m; i++) { 924 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 925 p[i/8] |= 1 << (i%8); 926 } 927 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p)); 928 reqh->actlen = reqh->length; 929 reqh->status = USBD_NORMAL_COMPLETION; 930 931 usb_transfer_complete(reqh); 932 } 933 934 void 935 ohci_root_intr_done(reqh) 936 usbd_request_handle reqh; 937 { 938 reqh->hcpriv = 0; 939 } 940 941 /* 942 * Wait here until controller claims to have an interrupt. 943 * Then call ohci_intr and return. Use timeout to avoid waiting 944 * too long. 945 */ 946 void 947 ohci_waitintr(sc, reqh) 948 ohci_softc_t *sc; 949 usbd_request_handle reqh; 950 { 951 int timo = reqh->timeout; 952 int usecs; 953 u_int32_t intrs; 954 955 reqh->status = USBD_IN_PROGRESS; 956 for (usecs = timo * 1000000 / hz; usecs > 0; usecs -= 1000) { 957 usb_delay_ms(&sc->sc_bus, 1); 958 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 959 DPRINTFN(15,("ohci_waitintr: 0x%04x\n", intrs)); 960 #ifdef USB_DEBUG 961 if (ohcidebug > 15) 962 ohci_dumpregs(sc); 963 #endif 964 if (intrs) { 965 ohci_intr(sc); 966 if (reqh->status != USBD_IN_PROGRESS) 967 return; 968 } 969 } 970 971 /* Timeout */ 972 DPRINTF(("ohci_waitintr: timeout\n")); 973 reqh->status = USBD_TIMEOUT; 974 usb_transfer_complete(reqh); 975 /* XXX should free TD */ 976 } 977 978 void 979 ohci_poll(bus) 980 struct usbd_bus *bus; 981 { 982 ohci_softc_t *sc = (ohci_softc_t *)bus; 983 984 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) 985 ohci_intr(sc); 986 } 987 988 usbd_status 989 ohci_device_request(reqh) 990 usbd_request_handle reqh; 991 { 992 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 993 usb_device_request_t *req = &reqh->request; 994 usbd_device_handle dev = opipe->pipe.device; 995 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 996 int addr = dev->address; 997 ohci_soft_td_t *setup, *xfer = 0, *stat, *next, *tail; 998 ohci_soft_ed_t *sed; 999 int isread; 1000 int len; 1001 usbd_status r; 1002 int s; 1003 1004 isread = req->bmRequestType & UT_READ; 1005 len = UGETW(req->wLength); 1006 1007 DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, " 1008 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 1009 req->bmRequestType, req->bRequest, UGETW(req->wValue), 1010 UGETW(req->wIndex), len, addr, 1011 opipe->pipe.endpoint->edesc->bEndpointAddress)); 1012 1013 setup = opipe->tail; 1014 stat = ohci_alloc_std(sc); 1015 if (!stat) { 1016 r = USBD_NOMEM; 1017 goto bad1; 1018 } 1019 tail = ohci_alloc_std(sc); 1020 if (!tail) { 1021 r = USBD_NOMEM; 1022 goto bad2; 1023 } 1024 tail->reqh = 0; 1025 1026 sed = opipe->sed; 1027 opipe->u.ctl.length = len; 1028 1029 /* Update device address and length since they may have changed. */ 1030 /* XXX This only needs to be done once, but it's too early in open. */ 1031 sed->ed.ed_flags = LE( 1032 (LE(sed->ed.ed_flags) & ~(OHCI_ED_ADDRMASK | OHCI_ED_MAXPMASK)) | 1033 OHCI_ED_SET_FA(addr) | 1034 OHCI_ED_SET_MAXP(UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize))); 1035 1036 /* Set up data transaction */ 1037 if (len != 0) { 1038 xfer = ohci_alloc_std(sc); 1039 if (!xfer) { 1040 r = USBD_NOMEM; 1041 goto bad3; 1042 } 1043 xfer->td.td_flags = LE( 1044 (isread ? OHCI_TD_IN : OHCI_TD_OUT) | OHCI_TD_NOCC | 1045 OHCI_TD_TOGGLE_1 | OHCI_TD_NOINTR | 1046 (reqh->flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0)); 1047 xfer->td.td_cbp = LE(DMAADDR(&reqh->dmabuf)); 1048 xfer->nexttd = stat; 1049 xfer->td.td_nexttd = LE(stat->physaddr); 1050 xfer->td.td_be = LE(LE(xfer->td.td_cbp) + len - 1); 1051 xfer->len = len; 1052 xfer->reqh = reqh; 1053 xfer->flags = OHCI_SET_LEN; 1054 1055 next = xfer; 1056 stat->flags = OHCI_CALL_DONE; 1057 } else { 1058 next = stat; 1059 stat->flags = OHCI_CALL_DONE | OHCI_SET_LEN; 1060 } 1061 1062 memcpy(KERNADDR(&opipe->u.ctl.reqdma), req, sizeof *req); 1063 1064 setup->td.td_flags = LE(OHCI_TD_SETUP | OHCI_TD_NOCC | 1065 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1066 setup->td.td_cbp = LE(DMAADDR(&opipe->u.ctl.reqdma)); 1067 setup->nexttd = next; 1068 setup->td.td_nexttd = LE(next->physaddr); 1069 setup->td.td_be = LE(LE(setup->td.td_cbp) + sizeof *req - 1); 1070 setup->len = 0; /* XXX The number of byte we count */ 1071 setup->reqh = reqh; 1072 setup->flags = 0; 1073 reqh->hcpriv = setup; 1074 1075 stat->td.td_flags = LE( 1076 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | OHCI_TD_NOCC | 1077 OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1078 stat->td.td_cbp = 0; 1079 stat->nexttd = tail; 1080 stat->td.td_nexttd = LE(tail->physaddr); 1081 stat->td.td_be = 0; 1082 stat->len = 0; 1083 stat->reqh = reqh; 1084 1085 #if USB_DEBUG 1086 if (ohcidebug > 5) { 1087 DPRINTF(("ohci_device_request:\n")); 1088 ohci_dump_ed(sed); 1089 ohci_dump_tds(setup); 1090 } 1091 #endif 1092 1093 /* Insert ED in schedule */ 1094 s = splusb(); 1095 ohci_hash_add_td(sc, setup); 1096 if (len != 0) 1097 ohci_hash_add_td(sc, xfer); 1098 ohci_hash_add_td(sc, stat); 1099 sed->ed.ed_tailp = LE(tail->physaddr); 1100 opipe->tail = tail; 1101 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1102 if (reqh->timeout && !sc->sc_bus.use_polling) { 1103 usb_timeout(ohci_timeout, reqh, 1104 MS_TO_TICKS(reqh->timeout), reqh->timo_handle); 1105 } 1106 splx(s); 1107 1108 #if USB_DEBUG 1109 if (ohcidebug > 5) { 1110 delay(5000); 1111 DPRINTF(("ohci_device_request: status=%x\n", 1112 OREAD4(sc, OHCI_COMMAND_STATUS))); 1113 ohci_dump_ed(sed); 1114 ohci_dump_tds(setup); 1115 } 1116 #endif 1117 1118 return (USBD_NORMAL_COMPLETION); 1119 1120 bad3: 1121 ohci_free_std(sc, tail); 1122 bad2: 1123 ohci_free_std(sc, stat); 1124 bad1: 1125 return (r); 1126 } 1127 1128 /* 1129 * Add an ED to the schedule. Called at splusb(). 1130 */ 1131 void 1132 ohci_add_ed(sed, head) 1133 ohci_soft_ed_t *sed; 1134 ohci_soft_ed_t *head; 1135 { 1136 SPLUSBCHECK; 1137 sed->next = head->next; 1138 sed->ed.ed_nexted = head->ed.ed_nexted; 1139 head->next = sed; 1140 head->ed.ed_nexted = LE(sed->physaddr); 1141 } 1142 1143 /* 1144 * Remove an ED from the schedule. Called at splusb(). 1145 */ 1146 void 1147 ohci_rem_ed(sed, head) 1148 ohci_soft_ed_t *sed; 1149 ohci_soft_ed_t *head; 1150 { 1151 ohci_soft_ed_t *p; 1152 1153 SPLUSBCHECK; 1154 1155 /* XXX */ 1156 for (p = head; p && p->next != sed; p = p->next) 1157 ; 1158 if (!p) 1159 panic("ohci_rem_ed: ED not found\n"); 1160 p->next = sed->next; 1161 p->ed.ed_nexted = sed->ed.ed_nexted; 1162 } 1163 1164 /* 1165 * When a transfer is completed the TD is added to the done queue by 1166 * the host controller. This queue is the processed by software. 1167 * Unfortunately the queue contains the physical address of the TD 1168 * and we have no simple way to translate this back to a kernel address. 1169 * To make the translation possible (and fast) we use a hash table of 1170 * TDs currently in the schedule. The physical address is used as the 1171 * hash value. 1172 */ 1173 1174 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1175 /* Called at splusb() */ 1176 void 1177 ohci_hash_add_td(sc, std) 1178 ohci_softc_t *sc; 1179 ohci_soft_td_t *std; 1180 { 1181 int h = HASH(std->physaddr); 1182 1183 SPLUSBCHECK; 1184 1185 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1186 } 1187 1188 /* Called at splusb() */ 1189 void 1190 ohci_hash_rem_td(sc, std) 1191 ohci_softc_t *sc; 1192 ohci_soft_td_t *std; 1193 { 1194 SPLUSBCHECK; 1195 1196 LIST_REMOVE(std, hnext); 1197 } 1198 1199 ohci_soft_td_t * 1200 ohci_hash_find_td(sc, a) 1201 ohci_softc_t *sc; 1202 ohci_physaddr_t a; 1203 { 1204 int h = HASH(a); 1205 ohci_soft_td_t *std; 1206 1207 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1208 std != 0; 1209 std = LIST_NEXT(std, hnext)) 1210 if (std->physaddr == a) 1211 return (std); 1212 panic("ohci_hash_find_td: addr 0x%08lx not found\n", (u_long)a); 1213 } 1214 1215 void 1216 ohci_timeout(addr) 1217 void *addr; 1218 { 1219 usbd_request_handle reqh = addr; 1220 1221 DPRINTF(("ohci_timeout: reqh=%p\n", reqh)); 1222 1223 reqh->device->bus->intr_context++; 1224 ohci_abort_req(reqh, USBD_TIMEOUT); 1225 reqh->device->bus->intr_context--; 1226 } 1227 1228 #ifdef USB_DEBUG 1229 void 1230 ohci_dump_tds(std) 1231 ohci_soft_td_t *std; 1232 { 1233 for (; std; std = std->nexttd) 1234 ohci_dump_td(std); 1235 } 1236 1237 void 1238 ohci_dump_td(std) 1239 ohci_soft_td_t *std; 1240 { 1241 DPRINTF(("TD(%p) at %08lx: %b delay=%d ec=%d cc=%d\ncbp=0x%08lx " 1242 "nexttd=0x%08lx be=0x%08lx\n", 1243 std, (u_long)std->physaddr, 1244 (int)LE(std->td.td_flags), 1245 "\20\23R\24OUT\25IN\31TOG1\32SETTOGGLE", 1246 OHCI_TD_GET_DI(LE(std->td.td_flags)), 1247 OHCI_TD_GET_EC(LE(std->td.td_flags)), 1248 OHCI_TD_GET_CC(LE(std->td.td_flags)), 1249 (u_long)LE(std->td.td_cbp), 1250 (u_long)LE(std->td.td_nexttd), (u_long)LE(std->td.td_be))); 1251 } 1252 1253 void 1254 ohci_dump_ed(sed) 1255 ohci_soft_ed_t *sed; 1256 { 1257 DPRINTF(("ED(%p) at %08lx: addr=%d endpt=%d maxp=%d %b\ntailp=0x%08lx " 1258 "headp=%b nexted=0x%08lx\n", 1259 sed, (u_long)sed->physaddr, 1260 OHCI_ED_GET_FA(LE(sed->ed.ed_flags)), 1261 OHCI_ED_GET_EN(LE(sed->ed.ed_flags)), 1262 OHCI_ED_GET_MAXP(LE(sed->ed.ed_flags)), 1263 (int)LE(sed->ed.ed_flags), 1264 "\20\14OUT\15IN\16LOWSPEED\17SKIP\20ISO", 1265 (u_long)LE(sed->ed.ed_tailp), 1266 (u_long)LE(sed->ed.ed_headp), "\20\1HALT\2CARRY", 1267 (u_long)LE(sed->ed.ed_nexted))); 1268 } 1269 #endif 1270 1271 usbd_status 1272 ohci_open(pipe) 1273 usbd_pipe_handle pipe; 1274 { 1275 usbd_device_handle dev = pipe->device; 1276 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 1277 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1278 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 1279 u_int8_t addr = dev->address; 1280 ohci_soft_ed_t *sed; 1281 ohci_soft_td_t *std; 1282 usbd_status r; 1283 int s; 1284 1285 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1286 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1287 if (addr == sc->sc_addr) { 1288 switch (ed->bEndpointAddress) { 1289 case USB_CONTROL_ENDPOINT: 1290 pipe->methods = &ohci_root_ctrl_methods; 1291 break; 1292 case UE_DIR_IN | OHCI_INTR_ENDPT: 1293 pipe->methods = &ohci_root_intr_methods; 1294 break; 1295 default: 1296 return (USBD_INVAL); 1297 } 1298 } else { 1299 sed = ohci_alloc_sed(sc); 1300 if (sed == 0) 1301 goto bad0; 1302 std = ohci_alloc_std(sc); 1303 if (std == 0) 1304 goto bad1; 1305 opipe->sed = sed; 1306 opipe->tail = std; 1307 sed->ed.ed_flags = LE( 1308 OHCI_ED_SET_FA(addr) | 1309 OHCI_ED_SET_EN(ed->bEndpointAddress) | 1310 OHCI_ED_DIR_TD | 1311 (dev->lowspeed ? OHCI_ED_SPEED : 0) | 1312 ((ed->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS ? 1313 OHCI_ED_FORMAT_ISO : OHCI_ED_FORMAT_GEN) | 1314 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 1315 sed->ed.ed_headp = sed->ed.ed_tailp = LE(std->physaddr); 1316 1317 switch (ed->bmAttributes & UE_XFERTYPE) { 1318 case UE_CONTROL: 1319 pipe->methods = &ohci_device_ctrl_methods; 1320 r = usb_allocmem(&sc->sc_bus, 1321 sizeof(usb_device_request_t), 1322 0, &opipe->u.ctl.reqdma); 1323 if (r != USBD_NORMAL_COMPLETION) 1324 goto bad; 1325 s = splusb(); 1326 ohci_add_ed(sed, sc->sc_ctrl_head); 1327 splx(s); 1328 break; 1329 case UE_INTERRUPT: 1330 pipe->methods = &ohci_device_intr_methods; 1331 return (ohci_device_setintr(sc, opipe, ed->bInterval)); 1332 case UE_ISOCHRONOUS: 1333 printf("ohci_open: open iso unimplemented\n"); 1334 return (USBD_INVAL); 1335 case UE_BULK: 1336 pipe->methods = &ohci_device_bulk_methods; 1337 s = splusb(); 1338 ohci_add_ed(sed, sc->sc_bulk_head); 1339 splx(s); 1340 break; 1341 } 1342 } 1343 return (USBD_NORMAL_COMPLETION); 1344 1345 bad: 1346 ohci_free_std(sc, std); 1347 bad1: 1348 ohci_free_sed(sc, sed); 1349 bad0: 1350 return (USBD_NOMEM); 1351 1352 } 1353 1354 /* 1355 * Close a reqular pipe. 1356 * Assumes that there are no pending transactions. 1357 */ 1358 void 1359 ohci_close_pipe(pipe, head) 1360 usbd_pipe_handle pipe; 1361 ohci_soft_ed_t *head; 1362 { 1363 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 1364 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 1365 ohci_soft_ed_t *sed = opipe->sed; 1366 int s; 1367 1368 s = splusb(); 1369 #ifdef DIAGNOSTIC 1370 sed->ed.ed_flags |= LE(OHCI_ED_SKIP); 1371 if ((sed->ed.ed_tailp & LE(OHCI_TAILMASK)) != 1372 (sed->ed.ed_headp & LE(OHCI_TAILMASK))) { 1373 ohci_physaddr_t td = sed->ed.ed_headp; 1374 ohci_soft_td_t *std; 1375 for (std = LIST_FIRST(&sc->sc_hash_tds[HASH(td)]); 1376 std != 0; 1377 std = LIST_NEXT(std, hnext)) 1378 if (std->physaddr == td) 1379 break; 1380 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 1381 "tl=0x%x pipe=%p, std=%p\n", sed, 1382 (int)LE(sed->ed.ed_headp), (int)LE(sed->ed.ed_tailp), 1383 pipe, std); 1384 usb_delay_ms(&sc->sc_bus, 2); 1385 if ((sed->ed.ed_tailp & LE(OHCI_TAILMASK)) != 1386 (sed->ed.ed_headp & LE(OHCI_TAILMASK))) 1387 printf("ohci_close_pipe: pipe still not empty\n"); 1388 } 1389 #endif 1390 ohci_rem_ed(sed, head); 1391 splx(s); 1392 ohci_free_std(sc, opipe->tail); 1393 ohci_free_sed(sc, opipe->sed); 1394 } 1395 1396 /* 1397 * Abort a device request. 1398 * If this routine is called at splusb() it guarantees that the request 1399 * will be removed from the hardware scheduling and that the callback 1400 * for it will be called with USBD_CANCELLED status. 1401 * It's impossible to guarantee that the requested transfer will not 1402 * have happened since the hardware runs concurrently. 1403 * If the transaction has already happened we rely on the ordinary 1404 * interrupt processing to process it. 1405 */ 1406 void 1407 ohci_abort_req(reqh, status) 1408 usbd_request_handle reqh; 1409 usbd_status status; 1410 { 1411 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 1412 ohci_soft_ed_t *sed; 1413 1414 SPLUSBCHECK; 1415 1416 DPRINTF(("ohci_abort_req: reqh=%p pipe=%p\n", reqh, opipe)); 1417 1418 reqh->status = status; 1419 1420 usb_untimeout(ohci_timeout, reqh, reqh->timo_handle); 1421 1422 sed = opipe->sed; 1423 DPRINTFN(1,("ohci_abort_req: stop ed=%p\n", sed)); 1424 sed->ed.ed_flags |= LE(OHCI_ED_SKIP); /* force hardware skip */ 1425 1426 if (reqh->device->bus->intr_context) { 1427 /* We have no process context, so we can't use tsleep(). */ 1428 timeout(ohci_abort_req_end, reqh, hz / USB_FRAMES_PER_SECOND); 1429 } else { 1430 usb_delay_ms(opipe->pipe.device->bus, 1); 1431 ohci_abort_req_end(reqh); 1432 } 1433 } 1434 1435 void 1436 ohci_abort_req_end(v) 1437 void *v; 1438 { 1439 usbd_request_handle reqh = v; 1440 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 1441 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 1442 ohci_soft_ed_t *sed; 1443 ohci_soft_td_t *p, *n; 1444 int s; 1445 1446 s = splusb(); 1447 1448 p = reqh->hcpriv; 1449 #ifdef DIAGNOSTIC 1450 if (!p) { 1451 printf("ohci_abort_req: hcpriv==0\n"); 1452 return; 1453 } 1454 #endif 1455 for (; p->reqh == reqh; p = n) { 1456 n = p->nexttd; 1457 ohci_hash_rem_td(sc, p); 1458 ohci_free_std(sc, p); 1459 } 1460 1461 sed = opipe->sed; 1462 DPRINTFN(2,("ohci_abort_req: set hd=%x, tl=%x\n", 1463 (int)LE(p->physaddr), (int)LE(sed->ed.ed_tailp))); 1464 sed->ed.ed_headp = p->physaddr; /* unlink TDs */ 1465 sed->ed.ed_flags &= LE(~OHCI_ED_SKIP); /* remove hardware skip */ 1466 1467 usb_transfer_complete(reqh); 1468 1469 splx(s); 1470 } 1471 1472 /* 1473 * Data structures and routines to emulate the root hub. 1474 */ 1475 usb_device_descriptor_t ohci_devd = { 1476 USB_DEVICE_DESCRIPTOR_SIZE, 1477 UDESC_DEVICE, /* type */ 1478 {0x00, 0x01}, /* USB version */ 1479 UCLASS_HUB, /* class */ 1480 USUBCLASS_HUB, /* subclass */ 1481 0, /* protocol */ 1482 64, /* max packet */ 1483 {0},{0},{0x00,0x01}, /* device id */ 1484 1,2,0, /* string indicies */ 1485 1 /* # of configurations */ 1486 }; 1487 1488 usb_config_descriptor_t ohci_confd = { 1489 USB_CONFIG_DESCRIPTOR_SIZE, 1490 UDESC_CONFIG, 1491 {USB_CONFIG_DESCRIPTOR_SIZE + 1492 USB_INTERFACE_DESCRIPTOR_SIZE + 1493 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1494 1, 1495 1, 1496 0, 1497 UC_SELF_POWERED, 1498 0 /* max power */ 1499 }; 1500 1501 usb_interface_descriptor_t ohci_ifcd = { 1502 USB_INTERFACE_DESCRIPTOR_SIZE, 1503 UDESC_INTERFACE, 1504 0, 1505 0, 1506 1, 1507 UCLASS_HUB, 1508 USUBCLASS_HUB, 1509 0, 1510 0 1511 }; 1512 1513 usb_endpoint_descriptor_t ohci_endpd = { 1514 USB_ENDPOINT_DESCRIPTOR_SIZE, 1515 UDESC_ENDPOINT, 1516 UE_DIR_IN | OHCI_INTR_ENDPT, 1517 UE_INTERRUPT, 1518 {8, 0}, /* max packet */ 1519 255 1520 }; 1521 1522 usb_hub_descriptor_t ohci_hubd = { 1523 USB_HUB_DESCRIPTOR_SIZE, 1524 UDESC_HUB, 1525 0, 1526 {0,0}, 1527 0, 1528 0, 1529 {0}, 1530 }; 1531 1532 int 1533 ohci_str(p, l, s) 1534 usb_string_descriptor_t *p; 1535 int l; 1536 char *s; 1537 { 1538 int i; 1539 1540 if (l == 0) 1541 return (0); 1542 p->bLength = 2 * strlen(s) + 2; 1543 if (l == 1) 1544 return (1); 1545 p->bDescriptorType = UDESC_STRING; 1546 l -= 2; 1547 for (i = 0; s[i] && l > 1; i++, l -= 2) 1548 USETW2(p->bString[i], 0, s[i]); 1549 return (2*i+2); 1550 } 1551 1552 /* 1553 * Simulate a hardware hub by handling all the necessary requests. 1554 */ 1555 usbd_status 1556 ohci_root_ctrl_transfer(reqh) 1557 usbd_request_handle reqh; 1558 { 1559 usbd_status r; 1560 1561 /* Insert last in queue. */ 1562 r = usb_insert_transfer(reqh); 1563 if (r != USBD_NORMAL_COMPLETION) 1564 return (r); 1565 1566 /* Pipe isn't running, start first */ 1567 return (ohci_root_ctrl_start(SIMPLEQ_FIRST(&reqh->pipe->queue))); 1568 } 1569 1570 usbd_status 1571 ohci_root_ctrl_start(reqh) 1572 usbd_request_handle reqh; 1573 { 1574 ohci_softc_t *sc = (ohci_softc_t *)reqh->pipe->device->bus; 1575 usb_device_request_t *req; 1576 void *buf; 1577 int port, i; 1578 int s, len, value, index, l, totlen = 0; 1579 usb_port_status_t ps; 1580 usb_hub_descriptor_t hubd; 1581 usbd_status r; 1582 u_int32_t v; 1583 1584 #ifdef DIAGNOSTIC 1585 if (!(reqh->rqflags & URQ_REQUEST)) 1586 /* XXX panic */ 1587 return (USBD_INVAL); 1588 #endif 1589 req = &reqh->request; 1590 1591 DPRINTFN(4,("ohci_root_ctrl_control type=0x%02x request=%02x\n", 1592 req->bmRequestType, req->bRequest)); 1593 1594 len = UGETW(req->wLength); 1595 value = UGETW(req->wValue); 1596 index = UGETW(req->wIndex); 1597 1598 if (len != 0) 1599 buf = KERNADDR(&reqh->dmabuf); 1600 #ifdef DIAGNOSTIC 1601 else 1602 buf = 0; 1603 #endif 1604 1605 #define C(x,y) ((x) | ((y) << 8)) 1606 switch(C(req->bRequest, req->bmRequestType)) { 1607 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 1608 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 1609 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 1610 /* 1611 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 1612 * for the integrated root hub. 1613 */ 1614 break; 1615 case C(UR_GET_CONFIG, UT_READ_DEVICE): 1616 if (len > 0) { 1617 *(u_int8_t *)buf = sc->sc_conf; 1618 totlen = 1; 1619 } 1620 break; 1621 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 1622 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value)); 1623 switch(value >> 8) { 1624 case UDESC_DEVICE: 1625 if ((value & 0xff) != 0) { 1626 r = USBD_IOERROR; 1627 goto ret; 1628 } 1629 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1630 USETW(ohci_devd.idVendor, sc->sc_id_vendor); 1631 memcpy(buf, &ohci_devd, l); 1632 break; 1633 case UDESC_CONFIG: 1634 if ((value & 0xff) != 0) { 1635 r = USBD_IOERROR; 1636 goto ret; 1637 } 1638 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 1639 memcpy(buf, &ohci_confd, l); 1640 buf = (char *)buf + l; 1641 len -= l; 1642 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 1643 totlen += l; 1644 memcpy(buf, &ohci_ifcd, l); 1645 buf = (char *)buf + l; 1646 len -= l; 1647 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 1648 totlen += l; 1649 memcpy(buf, &ohci_endpd, l); 1650 break; 1651 case UDESC_STRING: 1652 if (len == 0) 1653 break; 1654 *(u_int8_t *)buf = 0; 1655 totlen = 1; 1656 switch (value & 0xff) { 1657 case 1: /* Vendor */ 1658 totlen = ohci_str(buf, len, sc->sc_vendor); 1659 break; 1660 case 2: /* Product */ 1661 totlen = ohci_str(buf, len, "OHCI root hub"); 1662 break; 1663 } 1664 break; 1665 default: 1666 r = USBD_IOERROR; 1667 goto ret; 1668 } 1669 break; 1670 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 1671 if (len > 0) { 1672 *(u_int8_t *)buf = 0; 1673 totlen = 1; 1674 } 1675 break; 1676 case C(UR_GET_STATUS, UT_READ_DEVICE): 1677 if (len > 1) { 1678 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 1679 totlen = 2; 1680 } 1681 break; 1682 case C(UR_GET_STATUS, UT_READ_INTERFACE): 1683 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 1684 if (len > 1) { 1685 USETW(((usb_status_t *)buf)->wStatus, 0); 1686 totlen = 2; 1687 } 1688 break; 1689 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 1690 if (value >= USB_MAX_DEVICES) { 1691 r = USBD_IOERROR; 1692 goto ret; 1693 } 1694 sc->sc_addr = value; 1695 break; 1696 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 1697 if (value != 0 && value != 1) { 1698 r = USBD_IOERROR; 1699 goto ret; 1700 } 1701 sc->sc_conf = value; 1702 break; 1703 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 1704 break; 1705 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 1706 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 1707 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 1708 r = USBD_IOERROR; 1709 goto ret; 1710 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 1711 break; 1712 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 1713 break; 1714 /* Hub requests */ 1715 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 1716 break; 1717 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 1718 DPRINTFN(8, ("ohci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 1719 "port=%d feature=%d\n", 1720 index, value)); 1721 if (index < 1 || index > sc->sc_noport) { 1722 r = USBD_IOERROR; 1723 goto ret; 1724 } 1725 port = OHCI_RH_PORT_STATUS(index); 1726 switch(value) { 1727 case UHF_PORT_ENABLE: 1728 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 1729 break; 1730 case UHF_PORT_SUSPEND: 1731 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 1732 break; 1733 case UHF_PORT_POWER: 1734 OWRITE4(sc, port, UPS_LOW_SPEED); 1735 break; 1736 case UHF_C_PORT_CONNECTION: 1737 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 1738 break; 1739 case UHF_C_PORT_ENABLE: 1740 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 1741 break; 1742 case UHF_C_PORT_SUSPEND: 1743 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 1744 break; 1745 case UHF_C_PORT_OVER_CURRENT: 1746 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 1747 break; 1748 case UHF_C_PORT_RESET: 1749 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 1750 break; 1751 default: 1752 r = USBD_IOERROR; 1753 goto ret; 1754 } 1755 switch(value) { 1756 case UHF_C_PORT_CONNECTION: 1757 case UHF_C_PORT_ENABLE: 1758 case UHF_C_PORT_SUSPEND: 1759 case UHF_C_PORT_OVER_CURRENT: 1760 case UHF_C_PORT_RESET: 1761 /* Enable RHSC interrupt if condition is cleared. */ 1762 if ((OREAD4(sc, port) >> 16) == 0) 1763 ohci_rhsc_able(sc, 1); 1764 break; 1765 default: 1766 break; 1767 } 1768 break; 1769 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 1770 if (value != 0) { 1771 r = USBD_IOERROR; 1772 goto ret; 1773 } 1774 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 1775 hubd = ohci_hubd; 1776 hubd.bNbrPorts = sc->sc_noport; 1777 USETW(hubd.wHubCharacteristics, 1778 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 1779 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 1780 /* XXX overcurrent */ 1781 ); 1782 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 1783 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 1784 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 1785 hubd.DeviceRemovable[i++] = (u_int8_t)v; 1786 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 1787 l = min(len, hubd.bDescLength); 1788 totlen = l; 1789 memcpy(buf, &hubd, l); 1790 break; 1791 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 1792 if (len != 4) { 1793 r = USBD_IOERROR; 1794 goto ret; 1795 } 1796 memset(buf, 0, len); /* ? XXX */ 1797 totlen = len; 1798 break; 1799 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 1800 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n", 1801 index)); 1802 if (index < 1 || index > sc->sc_noport) { 1803 r = USBD_IOERROR; 1804 goto ret; 1805 } 1806 if (len != 4) { 1807 r = USBD_IOERROR; 1808 goto ret; 1809 } 1810 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 1811 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n", 1812 v)); 1813 USETW(ps.wPortStatus, v); 1814 USETW(ps.wPortChange, v >> 16); 1815 l = min(len, sizeof ps); 1816 memcpy(buf, &ps, l); 1817 totlen = l; 1818 break; 1819 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 1820 r = USBD_IOERROR; 1821 goto ret; 1822 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 1823 break; 1824 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 1825 if (index < 1 || index > sc->sc_noport) { 1826 r = USBD_IOERROR; 1827 goto ret; 1828 } 1829 port = OHCI_RH_PORT_STATUS(index); 1830 switch(value) { 1831 case UHF_PORT_ENABLE: 1832 OWRITE4(sc, port, UPS_PORT_ENABLED); 1833 break; 1834 case UHF_PORT_SUSPEND: 1835 OWRITE4(sc, port, UPS_SUSPEND); 1836 break; 1837 case UHF_PORT_RESET: 1838 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n", 1839 index)); 1840 OWRITE4(sc, port, UPS_RESET); 1841 for (i = 0; i < 10; i++) { 1842 usb_delay_ms(&sc->sc_bus, 10); 1843 if ((OREAD4(sc, port) & UPS_RESET) == 0) 1844 break; 1845 } 1846 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n", 1847 index, OREAD4(sc, port))); 1848 break; 1849 case UHF_PORT_POWER: 1850 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power " 1851 "%d\n", index)); 1852 OWRITE4(sc, port, UPS_PORT_POWER); 1853 break; 1854 default: 1855 r = USBD_IOERROR; 1856 goto ret; 1857 } 1858 break; 1859 default: 1860 r = USBD_IOERROR; 1861 goto ret; 1862 } 1863 reqh->actlen = totlen; 1864 r = USBD_NORMAL_COMPLETION; 1865 ret: 1866 reqh->status = r; 1867 s = splusb(); 1868 usb_transfer_complete(reqh); 1869 splx(s); 1870 return (USBD_IN_PROGRESS); 1871 } 1872 1873 /* Abort a root control request. */ 1874 void 1875 ohci_root_ctrl_abort(reqh) 1876 usbd_request_handle reqh; 1877 { 1878 /* Nothing to do, all transfers are synchronous. */ 1879 } 1880 1881 /* Close the root pipe. */ 1882 void 1883 ohci_root_ctrl_close(pipe) 1884 usbd_pipe_handle pipe; 1885 { 1886 DPRINTF(("ohci_root_ctrl_close\n")); 1887 /* Nothing to do. */ 1888 } 1889 1890 usbd_status 1891 ohci_root_intr_transfer(reqh) 1892 usbd_request_handle reqh; 1893 { 1894 usbd_status r; 1895 1896 /* Insert last in queue. */ 1897 r = usb_insert_transfer(reqh); 1898 if (r != USBD_NORMAL_COMPLETION) 1899 return (r); 1900 1901 /* Pipe isn't running, start first */ 1902 return (ohci_root_intr_start(SIMPLEQ_FIRST(&reqh->pipe->queue))); 1903 } 1904 1905 usbd_status 1906 ohci_root_intr_start(reqh) 1907 usbd_request_handle reqh; 1908 { 1909 usbd_pipe_handle pipe = reqh->pipe; 1910 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 1911 1912 sc->sc_intrreqh = reqh; 1913 1914 return (USBD_IN_PROGRESS); 1915 } 1916 1917 /* Abort a root interrupt request. */ 1918 void 1919 ohci_root_intr_abort(reqh) 1920 usbd_request_handle reqh; 1921 { 1922 /* No need to abort. */ 1923 } 1924 1925 /* Close the root pipe. */ 1926 void 1927 ohci_root_intr_close(pipe) 1928 usbd_pipe_handle pipe; 1929 { 1930 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 1931 1932 DPRINTF(("ohci_root_intr_close\n")); 1933 1934 sc->sc_intrreqh = 0; 1935 } 1936 1937 /************************/ 1938 1939 usbd_status 1940 ohci_device_ctrl_transfer(reqh) 1941 usbd_request_handle reqh; 1942 { 1943 usbd_status r; 1944 1945 /* Insert last in queue. */ 1946 r = usb_insert_transfer(reqh); 1947 if (r != USBD_NORMAL_COMPLETION) 1948 return (r); 1949 1950 /* Pipe isn't running, start first */ 1951 return (ohci_device_ctrl_start(SIMPLEQ_FIRST(&reqh->pipe->queue))); 1952 } 1953 1954 usbd_status 1955 ohci_device_ctrl_start(reqh) 1956 usbd_request_handle reqh; 1957 { 1958 ohci_softc_t *sc = (ohci_softc_t *)reqh->pipe->device->bus; 1959 usbd_status r; 1960 1961 #ifdef DIAGNOSTIC 1962 if (!(reqh->rqflags & URQ_REQUEST)) { 1963 /* XXX panic */ 1964 printf("ohci_device_ctrl_transfer: not a request\n"); 1965 return (USBD_INVAL); 1966 } 1967 #endif 1968 1969 r = ohci_device_request(reqh); 1970 if (r != USBD_NORMAL_COMPLETION) 1971 return (r); 1972 1973 if (sc->sc_bus.use_polling) 1974 ohci_waitintr(sc, reqh); 1975 return (USBD_IN_PROGRESS); 1976 } 1977 1978 /* Abort a device control request. */ 1979 void 1980 ohci_device_ctrl_abort(reqh) 1981 usbd_request_handle reqh; 1982 { 1983 DPRINTF(("ohci_device_ctrl_abort: reqh=%p\n", reqh)); 1984 ohci_abort_req(reqh, USBD_CANCELLED); 1985 } 1986 1987 /* Close a device control pipe. */ 1988 void 1989 ohci_device_ctrl_close(pipe) 1990 usbd_pipe_handle pipe; 1991 { 1992 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 1993 1994 DPRINTF(("ohci_device_ctrl_close: pipe=%p\n", pipe)); 1995 ohci_close_pipe(pipe, sc->sc_ctrl_head); 1996 } 1997 1998 /************************/ 1999 2000 void 2001 ohci_device_clear_toggle(pipe) 2002 usbd_pipe_handle pipe; 2003 { 2004 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2005 2006 opipe->sed->ed.ed_tailp &= LE(~OHCI_TOGGLECARRY); 2007 } 2008 2009 void 2010 ohci_noop(pipe) 2011 usbd_pipe_handle pipe; 2012 { 2013 } 2014 2015 usbd_status 2016 ohci_device_bulk_transfer(reqh) 2017 usbd_request_handle reqh; 2018 { 2019 usbd_status r; 2020 2021 /* Insert last in queue. */ 2022 r = usb_insert_transfer(reqh); 2023 if (r != USBD_NORMAL_COMPLETION) 2024 return (r); 2025 2026 /* Pipe isn't running, start first */ 2027 return (ohci_device_bulk_start(SIMPLEQ_FIRST(&reqh->pipe->queue))); 2028 } 2029 2030 usbd_status 2031 ohci_device_bulk_start(reqh) 2032 usbd_request_handle reqh; 2033 { 2034 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 2035 usbd_device_handle dev = opipe->pipe.device; 2036 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 2037 int addr = dev->address; 2038 ohci_soft_td_t *xfer, *tail; 2039 ohci_soft_ed_t *sed; 2040 int s, len, isread, endpt; 2041 2042 #ifdef DIAGNOSTIC 2043 if (reqh->rqflags & URQ_REQUEST) { 2044 /* XXX panic */ 2045 printf("ohci_device_bulk_start: a request\n"); 2046 return (USBD_INVAL); 2047 } 2048 #endif 2049 2050 len = reqh->length; 2051 endpt = reqh->pipe->endpoint->edesc->bEndpointAddress; 2052 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2053 sed = opipe->sed; 2054 2055 DPRINTFN(4,("ohci_device_bulk_start: reqh=%p len=%d isread=%d " 2056 "flags=%d endpt=%d\n", reqh, len, isread, reqh->flags, 2057 endpt)); 2058 2059 opipe->u.bulk.isread = isread; 2060 opipe->u.bulk.length = len; 2061 2062 tail = ohci_alloc_std(sc); 2063 if (!tail) 2064 return (USBD_NOMEM); 2065 tail->reqh = 0; 2066 2067 /* Update device address */ 2068 sed->ed.ed_flags = LE( 2069 (LE(sed->ed.ed_flags) & ~OHCI_ED_ADDRMASK) | 2070 OHCI_ED_SET_FA(addr)); 2071 2072 /* Set up data transaction */ 2073 xfer = opipe->tail; 2074 xfer->td.td_flags = LE( 2075 (isread ? OHCI_TD_IN : OHCI_TD_OUT) | OHCI_TD_NOCC | 2076 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY | 2077 (reqh->flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0)); 2078 xfer->td.td_cbp = LE(DMAADDR(&reqh->dmabuf)); 2079 xfer->nexttd = tail; 2080 xfer->td.td_nexttd = LE(tail->physaddr); 2081 xfer->td.td_be = LE(LE(xfer->td.td_cbp) + len - 1); 2082 xfer->len = len; 2083 xfer->reqh = reqh; 2084 xfer->flags = OHCI_CALL_DONE | OHCI_SET_LEN; 2085 reqh->hcpriv = xfer; 2086 2087 DPRINTFN(4,("ohci_device_bulk_start: ed_flags=0x%08x td_flags=0x%08x " 2088 "td_cbp=0x%08x td_be=0x%08x\n", 2089 (int)LE(sed->ed.ed_flags), (int)LE(xfer->td.td_flags), 2090 (int)LE(xfer->td.td_cbp), (int)LE(xfer->td.td_be))); 2091 2092 #ifdef USB_DEBUG 2093 if (ohcidebug > 4) { 2094 ohci_dump_ed(sed); 2095 ohci_dump_tds(xfer); 2096 } 2097 #endif 2098 2099 /* Insert ED in schedule */ 2100 s = splusb(); 2101 ohci_hash_add_td(sc, xfer); 2102 sed->ed.ed_tailp = LE(tail->physaddr); 2103 opipe->tail = tail; 2104 sed->ed.ed_flags &= LE(~OHCI_ED_SKIP); 2105 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 2106 if (reqh->timeout && !sc->sc_bus.use_polling) { 2107 usb_timeout(ohci_timeout, reqh, 2108 MS_TO_TICKS(reqh->timeout), reqh->timo_handle); 2109 } 2110 2111 #ifdef USB_DEBUG 2112 if (ohcidebug > 5) { 2113 delay(5000); 2114 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 2115 OREAD4(sc, OHCI_COMMAND_STATUS))); 2116 ohci_dump_ed(sed); 2117 ohci_dump_tds(xfer); 2118 } 2119 #endif 2120 2121 splx(s); 2122 2123 return (USBD_IN_PROGRESS); 2124 } 2125 2126 void 2127 ohci_device_bulk_abort(reqh) 2128 usbd_request_handle reqh; 2129 { 2130 DPRINTF(("ohci_device_bulk_abort: reqh=%p\n", reqh)); 2131 ohci_abort_req(reqh, USBD_CANCELLED); 2132 } 2133 2134 /* 2135 * Close a device bulk pipe. 2136 */ 2137 void 2138 ohci_device_bulk_close(pipe) 2139 usbd_pipe_handle pipe; 2140 { 2141 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 2142 2143 DPRINTF(("ohci_device_bulk_close: pipe=%p\n", pipe)); 2144 ohci_close_pipe(pipe, sc->sc_bulk_head); 2145 } 2146 2147 /************************/ 2148 2149 usbd_status 2150 ohci_device_intr_transfer(reqh) 2151 usbd_request_handle reqh; 2152 { 2153 usbd_status r; 2154 2155 /* Insert last in queue. */ 2156 r = usb_insert_transfer(reqh); 2157 if (r != USBD_NORMAL_COMPLETION) 2158 return (r); 2159 2160 /* Pipe isn't running, start first */ 2161 return (ohci_device_intr_start(SIMPLEQ_FIRST(&reqh->pipe->queue))); 2162 } 2163 2164 usbd_status 2165 ohci_device_intr_start(reqh) 2166 usbd_request_handle reqh; 2167 { 2168 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 2169 usbd_device_handle dev = opipe->pipe.device; 2170 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 2171 ohci_soft_ed_t *sed = opipe->sed; 2172 ohci_soft_td_t *xfer, *tail; 2173 int len; 2174 int s; 2175 2176 DPRINTFN(3, ("ohci_device_intr_transfer: reqh=%p len=%d " 2177 "flags=%d priv=%p\n", 2178 reqh, reqh->length, reqh->flags, reqh->priv)); 2179 2180 #ifdef DIAGNOSTIC 2181 if (reqh->rqflags & URQ_REQUEST) 2182 panic("ohci_device_intr_transfer: a request\n"); 2183 #endif 2184 2185 len = reqh->length; 2186 2187 xfer = opipe->tail; 2188 tail = ohci_alloc_std(sc); 2189 if (!tail) 2190 return (USBD_NOMEM); 2191 tail->reqh = 0; 2192 2193 xfer->td.td_flags = LE( 2194 OHCI_TD_IN | OHCI_TD_NOCC | 2195 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 2196 if (reqh->flags & USBD_SHORT_XFER_OK) 2197 xfer->td.td_flags |= LE(OHCI_TD_R); 2198 xfer->td.td_cbp = LE(DMAADDR(&reqh->dmabuf)); 2199 xfer->nexttd = tail; 2200 xfer->td.td_nexttd = LE(tail->physaddr); 2201 xfer->td.td_be = LE(LE(xfer->td.td_cbp) + len - 1); 2202 xfer->len = len; 2203 xfer->reqh = reqh; 2204 xfer->flags = OHCI_CALL_DONE | OHCI_SET_LEN; 2205 reqh->hcpriv = xfer; 2206 2207 #if USB_DEBUG 2208 if (ohcidebug > 5) { 2209 DPRINTF(("ohci_device_intr_transfer:\n")); 2210 ohci_dump_ed(sed); 2211 ohci_dump_tds(xfer); 2212 } 2213 #endif 2214 2215 /* Insert ED in schedule */ 2216 s = splusb(); 2217 ohci_hash_add_td(sc, xfer); 2218 sed->ed.ed_tailp = LE(tail->physaddr); 2219 opipe->tail = tail; 2220 sed->ed.ed_flags &= LE(~OHCI_ED_SKIP); 2221 2222 #ifdef USB_DEBUG 2223 if (ohcidebug > 5) { 2224 delay(5000); 2225 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 2226 OREAD4(sc, OHCI_COMMAND_STATUS))); 2227 ohci_dump_ed(sed); 2228 ohci_dump_tds(xfer); 2229 } 2230 #endif 2231 splx(s); 2232 2233 return (USBD_IN_PROGRESS); 2234 } 2235 2236 /* Abort a device control request. */ 2237 void 2238 ohci_device_intr_abort(reqh) 2239 usbd_request_handle reqh; 2240 { 2241 if (reqh->pipe->intrreqh == reqh) { 2242 DPRINTF(("ohci_device_intr_abort: remove\n")); 2243 reqh->pipe->intrreqh = 0; 2244 } 2245 ohci_abort_req(reqh, USBD_CANCELLED); 2246 } 2247 2248 /* Close a device interrupt pipe. */ 2249 void 2250 ohci_device_intr_close(pipe) 2251 usbd_pipe_handle pipe; 2252 { 2253 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2254 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 2255 int nslots = opipe->u.intr.nslots; 2256 int pos = opipe->u.intr.pos; 2257 int j; 2258 ohci_soft_ed_t *p, *sed = opipe->sed; 2259 int s; 2260 2261 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n", 2262 pipe, nslots, pos)); 2263 s = splusb(); 2264 sed->ed.ed_flags |= LE(OHCI_ED_SKIP); 2265 if ((sed->ed.ed_tailp & LE(OHCI_TAILMASK)) != 2266 (sed->ed.ed_headp & LE(OHCI_TAILMASK))) 2267 usb_delay_ms(&sc->sc_bus, 2); 2268 2269 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 2270 ; 2271 if (!p) 2272 panic("ohci_device_intr_close: ED not found\n"); 2273 p->next = sed->next; 2274 p->ed.ed_nexted = sed->ed.ed_nexted; 2275 splx(s); 2276 2277 for (j = 0; j < nslots; j++) 2278 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 2279 2280 ohci_free_std(sc, opipe->tail); 2281 ohci_free_sed(sc, opipe->sed); 2282 } 2283 2284 usbd_status 2285 ohci_device_setintr(sc, opipe, ival) 2286 ohci_softc_t *sc; 2287 struct ohci_pipe *opipe; 2288 int ival; 2289 { 2290 int i, j, s, best; 2291 u_int npoll, slow, shigh, nslots; 2292 u_int bestbw, bw; 2293 ohci_soft_ed_t *hsed, *sed = opipe->sed; 2294 2295 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe)); 2296 if (ival == 0) { 2297 printf("ohci_setintr: 0 interval\n"); 2298 return (USBD_INVAL); 2299 } 2300 2301 npoll = OHCI_NO_INTRS; 2302 while (npoll > ival) 2303 npoll /= 2; 2304 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll)); 2305 2306 /* 2307 * We now know which level in the tree the ED must go into. 2308 * Figure out which slot has most bandwidth left over. 2309 * Slots to examine: 2310 * npoll 2311 * 1 0 2312 * 2 1 2 2313 * 4 3 4 5 6 2314 * 8 7 8 9 10 11 12 13 14 2315 * N (N-1) .. (N-1+N-1) 2316 */ 2317 slow = npoll-1; 2318 shigh = slow + npoll; 2319 nslots = OHCI_NO_INTRS / npoll; 2320 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 2321 bw = 0; 2322 for (j = 0; j < nslots; j++) 2323 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 2324 if (bw < bestbw) { 2325 best = i; 2326 bestbw = bw; 2327 } 2328 } 2329 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n", 2330 best, slow, shigh, bestbw)); 2331 2332 s = splusb(); 2333 hsed = sc->sc_eds[best]; 2334 sed->next = hsed->next; 2335 sed->ed.ed_nexted = hsed->ed.ed_nexted; 2336 hsed->next = sed; 2337 hsed->ed.ed_nexted = LE(sed->physaddr); 2338 splx(s); 2339 2340 for (j = 0; j < nslots; j++) 2341 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 2342 opipe->u.intr.nslots = nslots; 2343 opipe->u.intr.pos = best; 2344 2345 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe)); 2346 return (USBD_NORMAL_COMPLETION); 2347 } 2348 2349
Indexes created Thu Sep 25 02:09:54 GMT 2025