ohci.c revision 1.49
1 /* $NetBSD: ohci.c,v 1.49 1999/09/18 11:25:50 augustss Exp $ */ 2 3 /* 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (augustss (at) carlstedt.se) at 9 * Carlstedt Research & Technology. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * USB Open Host Controller driver. 42 * 43 * OHCI spec: ftp://ftp.compaq.com/pub/supportinformation/papers/hcir1_0a.exe 44 * USB spec: http://www.usb.org/developers/data/usb11.pdf 45 */ 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/malloc.h> 51 #if defined(__NetBSD__) || defined(__OpenBSD__) 52 #include <sys/device.h> 53 #elif defined(__FreeBSD__) 54 #include <sys/module.h> 55 #include <sys/bus.h> 56 #endif 57 #include <sys/proc.h> 58 #include <sys/queue.h> 59 #include <sys/select.h> 60 61 #include <machine/bus.h> 62 #include <machine/endian.h> 63 64 #include <dev/usb/usb.h> 65 #include <dev/usb/usbdi.h> 66 #include <dev/usb/usbdivar.h> 67 #include <dev/usb/usb_mem.h> 68 #include <dev/usb/usb_quirks.h> 69 70 #include <dev/usb/ohcireg.h> 71 #include <dev/usb/ohcivar.h> 72 73 #if defined(__FreeBSD__) 74 #include <machine/clock.h> 75 76 #define delay(d) DELAY(d) 77 78 #endif 79 80 #if defined(__OpenBSD__) 81 struct cfdriver ohci_cd = { 82 NULL, "ohci", DV_DULL 83 }; 84 #endif 85 86 /* 87 * The OHCI controller is little endian, so on big endian machines 88 * the data strored in memory needs to be swapped. 89 */ 90 #if BYTE_ORDER == BIG_ENDIAN 91 #define LE(x) (bswap32(x)) 92 #else 93 #define LE(x) (x) 94 #endif 95 96 struct ohci_pipe; 97 98 ohci_soft_ed_t *ohci_alloc_sed __P((ohci_softc_t *)); 99 void ohci_free_sed __P((ohci_softc_t *, ohci_soft_ed_t *)); 100 101 ohci_soft_td_t *ohci_alloc_std __P((ohci_softc_t *)); 102 void ohci_free_std __P((ohci_softc_t *, ohci_soft_td_t *)); 103 104 void ohci_free_std_chain __P((ohci_softc_t *, 105 ohci_soft_td_t *, ohci_soft_td_t *)); 106 usbd_status ohci_alloc_std_chain __P((struct ohci_pipe *, ohci_softc_t *, 107 int, int, int, usb_dma_t *, 108 ohci_soft_td_t *, 109 ohci_soft_td_t **)); 110 111 void ohci_power __P((int, void *)); 112 usbd_status ohci_open __P((usbd_pipe_handle)); 113 void ohci_poll __P((struct usbd_bus *)); 114 void ohci_waitintr __P((ohci_softc_t *, usbd_request_handle)); 115 void ohci_rhsc __P((ohci_softc_t *, usbd_request_handle)); 116 void ohci_process_done __P((ohci_softc_t *, ohci_physaddr_t)); 117 118 usbd_status ohci_device_request __P((usbd_request_handle reqh)); 119 void ohci_add_ed __P((ohci_soft_ed_t *, ohci_soft_ed_t *)); 120 void ohci_rem_ed __P((ohci_soft_ed_t *, ohci_soft_ed_t *)); 121 void ohci_hash_add_td __P((ohci_softc_t *, ohci_soft_td_t *)); 122 void ohci_hash_rem_td __P((ohci_softc_t *, ohci_soft_td_t *)); 123 ohci_soft_td_t *ohci_hash_find_td __P((ohci_softc_t *, ohci_physaddr_t)); 124 125 usbd_status ohci_allocm __P((struct usbd_bus *, usb_dma_t *, u_int32_t)); 126 void ohci_freem __P((struct usbd_bus *, usb_dma_t *)); 127 128 usbd_status ohci_root_ctrl_transfer __P((usbd_request_handle)); 129 usbd_status ohci_root_ctrl_start __P((usbd_request_handle)); 130 void ohci_root_ctrl_abort __P((usbd_request_handle)); 131 void ohci_root_ctrl_close __P((usbd_pipe_handle)); 132 133 usbd_status ohci_root_intr_transfer __P((usbd_request_handle)); 134 usbd_status ohci_root_intr_start __P((usbd_request_handle)); 135 void ohci_root_intr_abort __P((usbd_request_handle)); 136 void ohci_root_intr_close __P((usbd_pipe_handle)); 137 void ohci_root_intr_done __P((usbd_request_handle)); 138 139 usbd_status ohci_device_ctrl_transfer __P((usbd_request_handle)); 140 usbd_status ohci_device_ctrl_start __P((usbd_request_handle)); 141 void ohci_device_ctrl_abort __P((usbd_request_handle)); 142 void ohci_device_ctrl_close __P((usbd_pipe_handle)); 143 void ohci_device_ctrl_done __P((usbd_request_handle)); 144 145 usbd_status ohci_device_bulk_transfer __P((usbd_request_handle)); 146 usbd_status ohci_device_bulk_start __P((usbd_request_handle)); 147 void ohci_device_bulk_abort __P((usbd_request_handle)); 148 void ohci_device_bulk_close __P((usbd_pipe_handle)); 149 void ohci_device_bulk_done __P((usbd_request_handle)); 150 151 usbd_status ohci_device_intr_transfer __P((usbd_request_handle)); 152 usbd_status ohci_device_intr_start __P((usbd_request_handle)); 153 void ohci_device_intr_abort __P((usbd_request_handle)); 154 void ohci_device_intr_close __P((usbd_pipe_handle)); 155 void ohci_device_intr_done __P((usbd_request_handle)); 156 157 usbd_status ohci_device_isoc_transfer __P((usbd_request_handle)); 158 usbd_status ohci_device_isoc_start __P((usbd_request_handle)); 159 void ohci_device_isoc_abort __P((usbd_request_handle)); 160 void ohci_device_isoc_close __P((usbd_pipe_handle)); 161 void ohci_device_isoc_done __P((usbd_request_handle)); 162 163 usbd_status ohci_device_setintr __P((ohci_softc_t *sc, 164 struct ohci_pipe *pipe, int ival)); 165 166 int ohci_str __P((usb_string_descriptor_t *, int, char *)); 167 168 void ohci_timeout __P((void *)); 169 void ohci_rhsc_able __P((ohci_softc_t *, int)); 170 171 void ohci_close_pipe __P((usbd_pipe_handle pipe, 172 ohci_soft_ed_t *head)); 173 void ohci_abort_req __P((usbd_request_handle reqh, 174 usbd_status status)); 175 void ohci_abort_req_end __P((void *)); 176 177 void ohci_device_clear_toggle __P((usbd_pipe_handle pipe)); 178 void ohci_noop __P((usbd_pipe_handle pipe)); 179 180 #ifdef USB_DEBUG 181 ohci_softc_t *thesc; 182 void ohci_dumpregs __P((ohci_softc_t *)); 183 void ohci_dump_tds __P((ohci_soft_td_t *)); 184 void ohci_dump_td __P((ohci_soft_td_t *)); 185 void ohci_dump_ed __P((ohci_soft_ed_t *)); 186 #endif 187 188 #define OWRITE4(sc, r, x) bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)) 189 #define OREAD4(sc, r) bus_space_read_4((sc)->iot, (sc)->ioh, (r)) 190 #define OREAD2(sc, r) bus_space_read_2((sc)->iot, (sc)->ioh, (r)) 191 192 /* Reverse the bits in a value 0 .. 31 */ 193 static u_int8_t revbits[OHCI_NO_INTRS] = 194 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 195 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 196 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 197 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 198 199 struct ohci_pipe { 200 struct usbd_pipe pipe; 201 ohci_soft_ed_t *sed; 202 ohci_soft_td_t *tail; 203 /* Info needed for different pipe kinds. */ 204 union { 205 /* Control pipe */ 206 struct { 207 usb_dma_t reqdma; 208 u_int length; 209 ohci_soft_td_t *setup, *data, *stat; 210 } ctl; 211 /* Interrupt pipe */ 212 struct { 213 int nslots; 214 int pos; 215 } intr; 216 /* Bulk pipe */ 217 struct { 218 u_int length; 219 int isread; 220 } bulk; 221 /* Iso pipe */ 222 struct iso { 223 int xxxxx; 224 } iso; 225 } u; 226 }; 227 228 #define OHCI_INTR_ENDPT 1 229 230 struct usbd_bus_methods ohci_bus_methods = { 231 ohci_open, 232 ohci_poll, 233 ohci_allocm, 234 ohci_freem, 235 }; 236 237 struct usbd_pipe_methods ohci_root_ctrl_methods = { 238 ohci_root_ctrl_transfer, 239 ohci_root_ctrl_start, 240 ohci_root_ctrl_abort, 241 ohci_root_ctrl_close, 242 ohci_noop, 243 0, 244 }; 245 246 struct usbd_pipe_methods ohci_root_intr_methods = { 247 ohci_root_intr_transfer, 248 ohci_root_intr_start, 249 ohci_root_intr_abort, 250 ohci_root_intr_close, 251 ohci_noop, 252 ohci_root_intr_done, 253 }; 254 255 struct usbd_pipe_methods ohci_device_ctrl_methods = { 256 ohci_device_ctrl_transfer, 257 ohci_device_ctrl_start, 258 ohci_device_ctrl_abort, 259 ohci_device_ctrl_close, 260 ohci_noop, 261 ohci_device_ctrl_done, 262 }; 263 264 struct usbd_pipe_methods ohci_device_intr_methods = { 265 ohci_device_intr_transfer, 266 ohci_device_intr_start, 267 ohci_device_intr_abort, 268 ohci_device_intr_close, 269 ohci_device_clear_toggle, 270 ohci_device_intr_done, 271 }; 272 273 struct usbd_pipe_methods ohci_device_bulk_methods = { 274 ohci_device_bulk_transfer, 275 ohci_device_bulk_start, 276 ohci_device_bulk_abort, 277 ohci_device_bulk_close, 278 ohci_device_clear_toggle, 279 ohci_device_bulk_done, 280 }; 281 282 #if 0 283 struct usbd_pipe_methods ohci_device_isoc_methods = { 284 ohci_device_isoc_transfer, 285 ohci_device_isoc_start, 286 ohci_device_isoc_abort, 287 ohci_device_isoc_close, 288 ohci_noop, 289 ohci_device_isoc_done, 290 }; 291 #endif 292 293 int 294 ohci_activate(self, act) 295 device_ptr_t self; 296 enum devact act; 297 { 298 struct ohci_softc *sc = (struct ohci_softc *)self; 299 int rv = 0; 300 301 switch (act) { 302 case DVACT_ACTIVATE: 303 return (EOPNOTSUPP); 304 break; 305 306 case DVACT_DEACTIVATE: 307 if (sc->sc_child != NULL) 308 rv = config_deactivate(sc->sc_child); 309 break; 310 } 311 return (rv); 312 } 313 314 int 315 ohci_detach(self, flags) 316 device_ptr_t self; 317 int flags; 318 { 319 struct ohci_softc *sc = (struct ohci_softc *)self; 320 int rv = 0; 321 322 if (sc->sc_child != NULL) 323 rv = config_detach(sc->sc_child, flags); 324 325 if (rv != 0) 326 return (rv); 327 328 powerhook_disestablish(sc->sc_powerhook); 329 /* free data structures XXX */ 330 331 return (rv); 332 } 333 334 ohci_soft_ed_t * 335 ohci_alloc_sed(sc) 336 ohci_softc_t *sc; 337 { 338 ohci_soft_ed_t *sed; 339 usbd_status r; 340 int i, offs; 341 usb_dma_t dma; 342 343 if (!sc->sc_freeeds) { 344 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n")); 345 r = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 346 OHCI_ED_ALIGN, &dma); 347 if (r != USBD_NORMAL_COMPLETION) 348 return (0); 349 for(i = 0; i < OHCI_SED_CHUNK; i++) { 350 offs = i * OHCI_SED_SIZE; 351 sed = (ohci_soft_ed_t *)((char *)KERNADDR(&dma) +offs); 352 sed->physaddr = DMAADDR(&dma) + offs; 353 sed->next = sc->sc_freeeds; 354 sc->sc_freeeds = sed; 355 } 356 } 357 sed = sc->sc_freeeds; 358 sc->sc_freeeds = sed->next; 359 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 360 sed->next = 0; 361 return (sed); 362 } 363 364 void 365 ohci_free_sed(sc, sed) 366 ohci_softc_t *sc; 367 ohci_soft_ed_t *sed; 368 { 369 sed->next = sc->sc_freeeds; 370 sc->sc_freeeds = sed; 371 } 372 373 ohci_soft_td_t * 374 ohci_alloc_std(sc) 375 ohci_softc_t *sc; 376 { 377 ohci_soft_td_t *std; 378 usbd_status r; 379 int i, offs; 380 usb_dma_t dma; 381 382 if (!sc->sc_freetds) { 383 DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n")); 384 r = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 385 OHCI_TD_ALIGN, &dma); 386 if (r != USBD_NORMAL_COMPLETION) 387 return (0); 388 for(i = 0; i < OHCI_STD_CHUNK; i++) { 389 offs = i * OHCI_STD_SIZE; 390 std = (ohci_soft_td_t *)((char *)KERNADDR(&dma) +offs); 391 std->physaddr = DMAADDR(&dma) + offs; 392 std->nexttd = sc->sc_freetds; 393 sc->sc_freetds = std; 394 } 395 } 396 std = sc->sc_freetds; 397 sc->sc_freetds = std->nexttd; 398 memset(&std->td, 0, sizeof(ohci_td_t)); 399 std->nexttd = 0; 400 return (std); 401 } 402 403 void 404 ohci_free_std(sc, std) 405 ohci_softc_t *sc; 406 ohci_soft_td_t *std; 407 { 408 std->nexttd = sc->sc_freetds; 409 sc->sc_freetds = std; 410 } 411 412 usbd_status 413 ohci_alloc_std_chain(upipe, sc, len, rd, shortok, dma, sp, ep) 414 struct ohci_pipe *upipe; 415 ohci_softc_t *sc; 416 int len, rd, shortok; 417 usb_dma_t *dma; 418 ohci_soft_td_t *sp, **ep; 419 { 420 ohci_soft_td_t *next, *cur; 421 ohci_physaddr_t dataphys, dataphysend; 422 u_int32_t intr; 423 int curlen; 424 425 DPRINTFN(len >= 4096,("ohci_alloc_std_chain: start len=%d\n", len)); 426 cur = sp; 427 dataphys = DMAADDR(dma); 428 dataphysend = OHCI_PAGE(dataphys + len - 1); 429 for (;;) { 430 next = ohci_alloc_std(sc); 431 if (next == 0) { 432 /* XXX free chain */ 433 return (USBD_NOMEM); 434 } 435 436 /* The OHCI hardware can handle at most one page crossing. */ 437 if (OHCI_PAGE(dataphys) == dataphysend || 438 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 439 /* we can handle it in this TD */ 440 curlen = len; 441 } else { 442 /* must use multiple TDs, fill as much as possible. */ 443 curlen = 2 * OHCI_PAGE_SIZE - 444 (dataphys & (OHCI_PAGE_SIZE-1)); 445 } 446 DPRINTFN(4,("ohci_alloc_std_chain: dataphys=0x%08x " 447 "dataphysend=0x%08x len=%d curlen=%d\n", 448 dataphys, dataphysend, 449 len, curlen)); 450 len -= curlen; 451 452 intr = len == 0 ? OHCI_TD_SET_DI(1) : OHCI_TD_NOINTR; 453 cur->td.td_flags = LE( 454 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | OHCI_TD_NOCC | 455 intr | OHCI_TD_TOGGLE_CARRY | 456 (shortok ? OHCI_TD_R : 0)); 457 cur->td.td_cbp = LE(dataphys); 458 cur->nexttd = next; 459 cur->td.td_nexttd = LE(next->physaddr); 460 cur->td.td_be = LE(dataphys + curlen - 1); 461 cur->len = curlen; 462 cur->flags = OHCI_ADD_LEN; 463 DPRINTFN(10,("ohci_alloc_std_chain: cbp=0x%08x be=0x%08x\n", 464 dataphys, dataphys + curlen - 1)); 465 if (len == 0) 466 break; 467 DPRINTFN(10,("ohci_alloc_std_chain: extend chain\n")); 468 dataphys += curlen; 469 cur = next; 470 } 471 cur->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 472 *ep = next; 473 474 return (USBD_NORMAL_COMPLETION); 475 } 476 477 void 478 ohci_free_std_chain(sc, std, stdend) 479 ohci_softc_t *sc; 480 ohci_soft_td_t *std; 481 ohci_soft_td_t *stdend; 482 { 483 ohci_soft_td_t *p; 484 485 for (; std != stdend; std = p) { 486 p = std->nexttd; 487 ohci_free_std(sc, std); 488 } 489 } 490 491 usbd_status 492 ohci_init(sc) 493 ohci_softc_t *sc; 494 { 495 ohci_soft_ed_t *sed, *psed; 496 usbd_status r; 497 int rev; 498 int i; 499 u_int32_t s, ctl, ival, hcr, fm, per; 500 501 DPRINTF(("ohci_init: start\n")); 502 rev = OREAD4(sc, OHCI_REVISION); 503 #if defined(__OpenBSD__) 504 printf(", OHCI version %d.%d%s\n", 505 #else 506 printf("%s: OHCI version %d.%d%s\n", USBDEVNAME(sc->sc_bus.bdev), 507 #endif 508 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 509 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 510 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 511 printf("%s: unsupported OHCI revision\n", 512 USBDEVNAME(sc->sc_bus.bdev)); 513 return (USBD_INVAL); 514 } 515 516 for (i = 0; i < OHCI_HASH_SIZE; i++) 517 LIST_INIT(&sc->sc_hash_tds[i]); 518 519 /* Allocate the HCCA area. */ 520 r = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 521 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 522 if (r != USBD_NORMAL_COMPLETION) 523 return (r); 524 sc->sc_hcca = (struct ohci_hcca *)KERNADDR(&sc->sc_hccadma); 525 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 526 527 sc->sc_eintrs = OHCI_NORMAL_INTRS; 528 529 sc->sc_ctrl_head = ohci_alloc_sed(sc); 530 if (!sc->sc_ctrl_head) { 531 r = USBD_NOMEM; 532 goto bad1; 533 } 534 sc->sc_ctrl_head->ed.ed_flags |= LE(OHCI_ED_SKIP); 535 536 sc->sc_bulk_head = ohci_alloc_sed(sc); 537 if (!sc->sc_bulk_head) { 538 r = USBD_NOMEM; 539 goto bad2; 540 } 541 sc->sc_bulk_head->ed.ed_flags |= LE(OHCI_ED_SKIP); 542 543 /* Allocate all the dummy EDs that make up the interrupt tree. */ 544 for (i = 0; i < OHCI_NO_EDS; i++) { 545 sed = ohci_alloc_sed(sc); 546 if (!sed) { 547 while (--i >= 0) 548 ohci_free_sed(sc, sc->sc_eds[i]); 549 r = USBD_NOMEM; 550 goto bad3; 551 } 552 /* All ED fields are set to 0. */ 553 sc->sc_eds[i] = sed; 554 sed->ed.ed_flags |= LE(OHCI_ED_SKIP); 555 if (i != 0) { 556 psed = sc->sc_eds[(i-1) / 2]; 557 sed->next = psed; 558 sed->ed.ed_nexted = LE(psed->physaddr); 559 } 560 } 561 /* 562 * Fill HCCA interrupt table. The bit reversal is to get 563 * the tree set up properly to spread the interrupts. 564 */ 565 for (i = 0; i < OHCI_NO_INTRS; i++) 566 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 567 LE(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 568 569 /* Determine in what context we are running. */ 570 ctl = OREAD4(sc, OHCI_CONTROL); 571 if (ctl & OHCI_IR) { 572 /* SMM active, request change */ 573 DPRINTF(("ohci_init: SMM active, request owner change\n")); 574 s = OREAD4(sc, OHCI_COMMAND_STATUS); 575 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 576 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 577 delay(1000); 578 ctl = OREAD4(sc, OHCI_CONTROL); 579 } 580 if ((ctl & OHCI_IR) == 0) { 581 printf("%s: SMM does not respond, resetting\n", 582 USBDEVNAME(sc->sc_bus.bdev)); 583 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 584 goto reset; 585 } 586 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 587 /* BIOS started controller. */ 588 DPRINTF(("ohci_init: BIOS active\n")); 589 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 590 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL); 591 delay(USB_RESUME_DELAY * 1000); 592 } 593 } else { 594 DPRINTF(("ohci_init: cold started\n")); 595 reset: 596 /* Controller was cold started. */ 597 delay(USB_BUS_RESET_DELAY * 1000); 598 } 599 600 /* 601 * This reset should not be necessary according to the OHCI spec, but 602 * without it some controllers do not start. 603 */ 604 DPRINTF(("%s: resetting\n", USBDEVNAME(sc->sc_bus.bdev))); 605 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 606 delay(USB_BUS_RESET_DELAY * 1000); 607 608 /* We now own the host controller and the bus has been reset. */ 609 ival = OHCI_GET_IVAL(OREAD4(sc, OHCI_FM_INTERVAL)); 610 611 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 612 /* Nominal time for a reset is 10 us. */ 613 for (i = 0; i < 10; i++) { 614 delay(10); 615 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 616 if (!hcr) 617 break; 618 } 619 if (hcr) { 620 printf("%s: reset timeout\n", USBDEVNAME(sc->sc_bus.bdev)); 621 r = USBD_IOERROR; 622 goto bad3; 623 } 624 #ifdef USB_DEBUG 625 thesc = sc; 626 if (ohcidebug > 15) 627 ohci_dumpregs(sc); 628 #endif 629 630 /* The controller is now in suspend state, we have 2ms to finish. */ 631 632 /* Set up HC registers. */ 633 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma)); 634 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 635 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 636 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 637 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 638 ctl = OREAD4(sc, OHCI_CONTROL); 639 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 640 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 641 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL; 642 /* And finally start it! */ 643 OWRITE4(sc, OHCI_CONTROL, ctl); 644 645 /* 646 * The controller is now OPERATIONAL. Set a some final 647 * registers that should be set earlier, but that the 648 * controller ignores when in the SUSPEND state. 649 */ 650 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 651 fm |= OHCI_FSMPS(ival) | ival; 652 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 653 per = OHCI_PERIODIC(ival); /* 90% periodic */ 654 OWRITE4(sc, OHCI_PERIODIC_START, per); 655 656 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 657 658 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 659 660 #ifdef USB_DEBUG 661 if (ohcidebug > 5) 662 ohci_dumpregs(sc); 663 #endif 664 665 /* Set up the bus struct. */ 666 sc->sc_bus.methods = &ohci_bus_methods; 667 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe); 668 669 sc->sc_powerhook = powerhook_establish(ohci_power, sc); 670 671 return (USBD_NORMAL_COMPLETION); 672 673 bad3: 674 ohci_free_sed(sc, sc->sc_ctrl_head); 675 bad2: 676 ohci_free_sed(sc, sc->sc_bulk_head); 677 bad1: 678 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 679 return (r); 680 } 681 682 usbd_status 683 ohci_allocm(bus, dma, size) 684 struct usbd_bus *bus; 685 usb_dma_t *dma; 686 u_int32_t size; 687 { 688 struct ohci_softc *sc = (struct ohci_softc *)bus; 689 690 return (usb_allocmem(&sc->sc_bus, size, 0, dma)); 691 } 692 693 void 694 ohci_freem(bus, dma) 695 struct usbd_bus *bus; 696 usb_dma_t *dma; 697 { 698 struct ohci_softc *sc = (struct ohci_softc *)bus; 699 700 usb_freemem(&sc->sc_bus, dma); 701 } 702 703 #if !defined(__OpenBSD__) 704 void 705 ohci_power(why, v) 706 int why; 707 void *v; 708 { 709 #ifdef USB_DEBUG 710 ohci_softc_t *sc = v; 711 712 DPRINTF(("ohci_power: sc=%p, why=%d\n", sc, why)); 713 /* XXX should suspend/resume */ 714 ohci_dumpregs(sc); 715 #endif 716 } 717 #endif /* !defined(__OpenBSD__) */ 718 719 #ifdef USB_DEBUG 720 void ohcidump(void); 721 void ohcidump(void) { ohci_dumpregs(thesc); } 722 723 void 724 ohci_dumpregs(sc) 725 ohci_softc_t *sc; 726 { 727 DPRINTF(("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 728 OREAD4(sc, OHCI_REVISION), 729 OREAD4(sc, OHCI_CONTROL), 730 OREAD4(sc, OHCI_COMMAND_STATUS))); 731 DPRINTF((" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 732 OREAD4(sc, OHCI_INTERRUPT_STATUS), 733 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 734 OREAD4(sc, OHCI_INTERRUPT_DISABLE))); 735 DPRINTF((" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 736 OREAD4(sc, OHCI_HCCA), 737 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 738 OREAD4(sc, OHCI_CONTROL_HEAD_ED))); 739 DPRINTF((" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 740 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 741 OREAD4(sc, OHCI_BULK_HEAD_ED), 742 OREAD4(sc, OHCI_BULK_CURRENT_ED))); 743 DPRINTF((" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 744 OREAD4(sc, OHCI_DONE_HEAD), 745 OREAD4(sc, OHCI_FM_INTERVAL), 746 OREAD4(sc, OHCI_FM_REMAINING))); 747 DPRINTF((" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 748 OREAD4(sc, OHCI_FM_NUMBER), 749 OREAD4(sc, OHCI_PERIODIC_START), 750 OREAD4(sc, OHCI_LS_THRESHOLD))); 751 DPRINTF((" desca=0x%08x descb=0x%08x stat=0x%08x\n", 752 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 753 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 754 OREAD4(sc, OHCI_RH_STATUS))); 755 DPRINTF((" port1=0x%08x port2=0x%08x\n", 756 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 757 OREAD4(sc, OHCI_RH_PORT_STATUS(2)))); 758 DPRINTF((" HCCA: frame_number=0x%04x done_head=0x%08x\n", 759 LE(sc->sc_hcca->hcca_frame_number), 760 LE(sc->sc_hcca->hcca_done_head))); 761 } 762 #endif 763 764 int 765 ohci_intr(p) 766 void *p; 767 { 768 ohci_softc_t *sc = p; 769 u_int32_t intrs, eintrs; 770 ohci_physaddr_t done; 771 772 /* In case the interrupt occurs before initialization has completed. */ 773 if (sc == NULL || sc->sc_hcca == NULL) { 774 #ifdef DIAGNOSTIC 775 printf("ohci_intr: sc->sc_hcca == NULL\n"); 776 #endif 777 return (0); 778 } 779 780 intrs = 0; 781 done = LE(sc->sc_hcca->hcca_done_head); 782 if (done != 0) { 783 sc->sc_hcca->hcca_done_head = 0; 784 if (done & ~OHCI_DONE_INTRS) 785 intrs = OHCI_WDH; 786 if (done & OHCI_DONE_INTRS) 787 intrs |= OREAD4(sc, OHCI_INTERRUPT_STATUS); 788 } else 789 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 790 if (!intrs) 791 return (0); 792 intrs &= ~OHCI_MIE; 793 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs); /* Acknowledge */ 794 eintrs = intrs & sc->sc_eintrs; 795 if (!eintrs) 796 return (0); 797 798 sc->sc_bus.intr_context++; 799 sc->sc_bus.no_intrs++; 800 DPRINTFN(7, ("ohci_intr: sc=%p intrs=%x(%x) eintr=%x\n", 801 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), 802 (u_int)eintrs)); 803 804 if (eintrs & OHCI_SO) { 805 printf("%s: scheduling overrun\n",USBDEVNAME(sc->sc_bus.bdev)); 806 /* XXX do what */ 807 intrs &= ~OHCI_SO; 808 } 809 if (eintrs & OHCI_WDH) { 810 ohci_process_done(sc, done &~ OHCI_DONE_INTRS); 811 intrs &= ~OHCI_WDH; 812 } 813 if (eintrs & OHCI_RD) { 814 printf("%s: resume detect\n", USBDEVNAME(sc->sc_bus.bdev)); 815 /* XXX process resume detect */ 816 } 817 if (eintrs & OHCI_UE) { 818 printf("%s: unrecoverable error, controller halted\n", 819 USBDEVNAME(sc->sc_bus.bdev)); 820 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 821 /* XXX what else */ 822 } 823 if (eintrs & OHCI_RHSC) { 824 ohci_rhsc(sc, sc->sc_intrreqh); 825 intrs &= ~OHCI_RHSC; 826 827 /* 828 * Disable RHSC interrupt for now, because it will be 829 * on until the port has been reset. 830 */ 831 ohci_rhsc_able(sc, 0); 832 } 833 834 sc->sc_bus.intr_context--; 835 836 /* Block unprocessed interrupts. XXX */ 837 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, intrs); 838 sc->sc_eintrs &= ~intrs; 839 840 return (1); 841 } 842 843 void 844 ohci_rhsc_able(sc, on) 845 ohci_softc_t *sc; 846 int on; 847 { 848 DPRINTFN(4, ("ohci_rhsc_able: on=%d\n", on)); 849 if (on) { 850 sc->sc_eintrs |= OHCI_RHSC; 851 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 852 } else { 853 sc->sc_eintrs &= ~OHCI_RHSC; 854 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_RHSC); 855 } 856 } 857 858 #ifdef USB_DEBUG 859 char *ohci_cc_strs[] = { 860 "NO_ERROR", 861 "CRC", 862 "BIT_STUFFING", 863 "DATA_TOGGLE_MISMATCH", 864 "STALL", 865 "DEVICE_NOT_RESPONDING", 866 "PID_CHECK_FAILURE", 867 "UNEXPECTED_PID", 868 "DATA_OVERRUN", 869 "DATA_UNDERRUN", 870 "BUFFER_OVERRUN", 871 "BUFFER_UNDERRUN", 872 "NOT_ACCESSED", 873 }; 874 #endif 875 876 void 877 ohci_process_done(sc, done) 878 ohci_softc_t *sc; 879 ohci_physaddr_t done; 880 { 881 ohci_soft_td_t *std, *sdone, *stdnext; 882 usbd_request_handle reqh; 883 int len, cc; 884 885 DPRINTFN(10,("ohci_process_done: done=0x%08lx\n", (u_long)done)); 886 887 /* Reverse the done list. */ 888 for (sdone = 0; done; done = LE(std->td.td_nexttd)) { 889 std = ohci_hash_find_td(sc, done); 890 std->dnext = sdone; 891 sdone = std; 892 } 893 894 #ifdef USB_DEBUG 895 if (ohcidebug > 10) { 896 DPRINTF(("ohci_process_done: TD done:\n")); 897 ohci_dump_tds(sdone); 898 } 899 #endif 900 901 for (std = sdone; std; std = stdnext) { 902 reqh = std->reqh; 903 stdnext = std->dnext; 904 DPRINTFN(10, ("ohci_process_done: std=%p reqh=%p hcpriv=%p\n", 905 std, reqh, reqh->hcpriv)); 906 cc = OHCI_TD_GET_CC(LE(std->td.td_flags)); 907 usb_untimeout(ohci_timeout, reqh, reqh->timo_handle); 908 if (reqh->status == USBD_CANCELLED || 909 reqh->status == USBD_TIMEOUT) { 910 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 911 reqh)); 912 /* Handled by abort routine. */ 913 } else if (cc == OHCI_CC_NO_ERROR) { 914 len = std->len; 915 if (std->td.td_cbp != 0) 916 len -= LE(std->td.td_be) - 917 LE(std->td.td_cbp) + 1; 918 if (std->flags & OHCI_ADD_LEN) 919 reqh->actlen += len; 920 if (std->flags & OHCI_CALL_DONE) { 921 reqh->status = USBD_NORMAL_COMPLETION; 922 usb_transfer_complete(reqh); 923 } 924 ohci_hash_rem_td(sc, std); 925 ohci_free_std(sc, std); 926 } else { 927 /* 928 * Endpoint is halted. First unlink all the TDs 929 * belonging to the failed transfer, and then restart 930 * the endpoint. 931 */ 932 ohci_soft_td_t *p, *n; 933 struct ohci_pipe *opipe = 934 (struct ohci_pipe *)reqh->pipe; 935 936 DPRINTFN(-1,("ohci_process_done: error cc=%d (%s)\n", 937 OHCI_TD_GET_CC(LE(std->td.td_flags)), 938 ohci_cc_strs[OHCI_TD_GET_CC(LE(std->td.td_flags))])); 939 940 /* remove TDs */ 941 for (p = std; p->reqh == reqh; p = n) { 942 n = p->nexttd; 943 ohci_hash_rem_td(sc, p); 944 ohci_free_std(sc, p); 945 } 946 947 /* clear halt */ 948 opipe->sed->ed.ed_headp = LE(p->physaddr); 949 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 950 951 if (cc == OHCI_CC_STALL) 952 reqh->status = USBD_STALLED; 953 else 954 reqh->status = USBD_IOERROR; 955 usb_transfer_complete(reqh); 956 } 957 } 958 } 959 960 void 961 ohci_device_ctrl_done(reqh) 962 usbd_request_handle reqh; 963 { 964 DPRINTFN(10,("ohci_ctrl_done: reqh=%p\n", reqh)); 965 966 #ifdef DIAGNOSTIC 967 if (!(reqh->rqflags & URQ_REQUEST)) { 968 panic("ohci_ctrl_done: not a request\n"); 969 } 970 #endif 971 reqh->hcpriv = 0; 972 } 973 974 void 975 ohci_device_intr_done(reqh) 976 usbd_request_handle reqh; 977 { 978 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 979 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 980 ohci_soft_ed_t *sed = opipe->sed; 981 ohci_soft_td_t *data, *tail; 982 983 984 DPRINTFN(10,("ohci_intr_done: reqh=%p, actlen=%d\n", 985 reqh, reqh->actlen)); 986 987 reqh->hcpriv = 0; 988 989 if (reqh->pipe->repeat) { 990 data = opipe->tail; 991 tail = ohci_alloc_std(sc); /* XXX should reuse TD */ 992 if (!tail) { 993 reqh->status = USBD_NOMEM; 994 return; 995 } 996 tail->reqh = 0; 997 998 data->td.td_flags = LE( 999 OHCI_TD_IN | OHCI_TD_NOCC | 1000 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 1001 if (reqh->flags & USBD_SHORT_XFER_OK) 1002 data->td.td_flags |= LE(OHCI_TD_R); 1003 data->td.td_cbp = LE(DMAADDR(&reqh->dmabuf)); 1004 data->nexttd = tail; 1005 data->td.td_nexttd = LE(tail->physaddr); 1006 data->td.td_be = LE(LE(data->td.td_cbp) + reqh->length - 1); 1007 data->len = reqh->length; 1008 data->reqh = reqh; 1009 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 1010 reqh->hcpriv = data; 1011 reqh->actlen = 0; 1012 1013 ohci_hash_add_td(sc, data); 1014 sed->ed.ed_tailp = LE(tail->physaddr); 1015 opipe->tail = tail; 1016 } 1017 } 1018 1019 void 1020 ohci_device_bulk_done(reqh) 1021 usbd_request_handle reqh; 1022 { 1023 DPRINTFN(10,("ohci_bulk_done: reqh=%p, actlen=%d\n", 1024 reqh, reqh->actlen)); 1025 1026 reqh->hcpriv = 0; 1027 } 1028 1029 void 1030 ohci_rhsc(sc, reqh) 1031 ohci_softc_t *sc; 1032 usbd_request_handle reqh; 1033 { 1034 usbd_pipe_handle pipe; 1035 struct ohci_pipe *opipe; 1036 u_char *p; 1037 int i, m; 1038 int hstatus; 1039 1040 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1041 DPRINTF(("ohci_rhsc: sc=%p reqh=%p hstatus=0x%08x\n", 1042 sc, reqh, hstatus)); 1043 1044 if (reqh == 0) { 1045 /* Just ignore the change. */ 1046 return; 1047 } 1048 1049 pipe = reqh->pipe; 1050 opipe = (struct ohci_pipe *)pipe; 1051 1052 p = KERNADDR(&reqh->dmabuf); 1053 m = min(sc->sc_noport, reqh->length * 8 - 1); 1054 memset(p, 0, reqh->length); 1055 for (i = 1; i <= m; i++) { 1056 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1057 p[i/8] |= 1 << (i%8); 1058 } 1059 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p)); 1060 reqh->actlen = reqh->length; 1061 reqh->status = USBD_NORMAL_COMPLETION; 1062 1063 usb_transfer_complete(reqh); 1064 } 1065 1066 void 1067 ohci_root_intr_done(reqh) 1068 usbd_request_handle reqh; 1069 { 1070 reqh->hcpriv = 0; 1071 } 1072 1073 /* 1074 * Wait here until controller claims to have an interrupt. 1075 * Then call ohci_intr and return. Use timeout to avoid waiting 1076 * too long. 1077 */ 1078 void 1079 ohci_waitintr(sc, reqh) 1080 ohci_softc_t *sc; 1081 usbd_request_handle reqh; 1082 { 1083 int timo = reqh->timeout; 1084 int usecs; 1085 u_int32_t intrs; 1086 1087 reqh->status = USBD_IN_PROGRESS; 1088 for (usecs = timo * 1000000 / hz; usecs > 0; usecs -= 1000) { 1089 usb_delay_ms(&sc->sc_bus, 1); 1090 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 1091 DPRINTFN(15,("ohci_waitintr: 0x%04x\n", intrs)); 1092 #ifdef USB_DEBUG 1093 if (ohcidebug > 15) 1094 ohci_dumpregs(sc); 1095 #endif 1096 if (intrs) { 1097 ohci_intr(sc); 1098 if (reqh->status != USBD_IN_PROGRESS) 1099 return; 1100 } 1101 } 1102 1103 /* Timeout */ 1104 DPRINTF(("ohci_waitintr: timeout\n")); 1105 reqh->status = USBD_TIMEOUT; 1106 usb_transfer_complete(reqh); 1107 /* XXX should free TD */ 1108 } 1109 1110 void 1111 ohci_poll(bus) 1112 struct usbd_bus *bus; 1113 { 1114 ohci_softc_t *sc = (ohci_softc_t *)bus; 1115 1116 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) 1117 ohci_intr(sc); 1118 } 1119 1120 usbd_status 1121 ohci_device_request(reqh) 1122 usbd_request_handle reqh; 1123 { 1124 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 1125 usb_device_request_t *req = &reqh->request; 1126 usbd_device_handle dev = opipe->pipe.device; 1127 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 1128 int addr = dev->address; 1129 ohci_soft_td_t *setup, *data = 0, *stat, *next, *tail; 1130 ohci_soft_ed_t *sed; 1131 int isread; 1132 int len; 1133 usbd_status r; 1134 int s; 1135 1136 isread = req->bmRequestType & UT_READ; 1137 len = UGETW(req->wLength); 1138 1139 DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, " 1140 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 1141 req->bmRequestType, req->bRequest, UGETW(req->wValue), 1142 UGETW(req->wIndex), len, addr, 1143 opipe->pipe.endpoint->edesc->bEndpointAddress)); 1144 1145 setup = opipe->tail; 1146 stat = ohci_alloc_std(sc); 1147 if (!stat) { 1148 r = USBD_NOMEM; 1149 goto bad1; 1150 } 1151 tail = ohci_alloc_std(sc); 1152 if (!tail) { 1153 r = USBD_NOMEM; 1154 goto bad2; 1155 } 1156 tail->reqh = 0; 1157 1158 sed = opipe->sed; 1159 opipe->u.ctl.length = len; 1160 1161 /* Update device address and length since they may have changed. */ 1162 /* XXX This only needs to be done once, but it's too early in open. */ 1163 sed->ed.ed_flags = LE( 1164 (LE(sed->ed.ed_flags) & ~(OHCI_ED_ADDRMASK | OHCI_ED_MAXPMASK)) | 1165 OHCI_ED_SET_FA(addr) | 1166 OHCI_ED_SET_MAXP(UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize))); 1167 1168 /* Set up data transaction */ 1169 if (len != 0) { 1170 data = ohci_alloc_std(sc); 1171 if (!data) { 1172 r = USBD_NOMEM; 1173 goto bad3; 1174 } 1175 data->td.td_flags = LE( 1176 (isread ? OHCI_TD_IN : OHCI_TD_OUT) | OHCI_TD_NOCC | 1177 OHCI_TD_TOGGLE_1 | OHCI_TD_NOINTR | 1178 (reqh->flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0)); 1179 data->td.td_cbp = LE(DMAADDR(&reqh->dmabuf)); 1180 data->nexttd = stat; 1181 data->td.td_nexttd = LE(stat->physaddr); 1182 data->td.td_be = LE(LE(data->td.td_cbp) + len - 1); 1183 data->len = len; 1184 data->reqh = reqh; 1185 data->flags = OHCI_ADD_LEN; 1186 1187 next = data; 1188 stat->flags = OHCI_CALL_DONE; 1189 } else { 1190 next = stat; 1191 /* XXX ADD_LEN? */ 1192 stat->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 1193 } 1194 1195 memcpy(KERNADDR(&opipe->u.ctl.reqdma), req, sizeof *req); 1196 1197 setup->td.td_flags = LE(OHCI_TD_SETUP | OHCI_TD_NOCC | 1198 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1199 setup->td.td_cbp = LE(DMAADDR(&opipe->u.ctl.reqdma)); 1200 setup->nexttd = next; 1201 setup->td.td_nexttd = LE(next->physaddr); 1202 setup->td.td_be = LE(LE(setup->td.td_cbp) + sizeof *req - 1); 1203 setup->len = 0; /* XXX The number of byte we count */ 1204 setup->reqh = reqh; 1205 setup->flags = 0; 1206 reqh->hcpriv = setup; 1207 1208 stat->td.td_flags = LE( 1209 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | OHCI_TD_NOCC | 1210 OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1211 stat->td.td_cbp = 0; 1212 stat->nexttd = tail; 1213 stat->td.td_nexttd = LE(tail->physaddr); 1214 stat->td.td_be = 0; 1215 stat->len = 0; 1216 stat->reqh = reqh; 1217 1218 #if USB_DEBUG 1219 if (ohcidebug > 5) { 1220 DPRINTF(("ohci_device_request:\n")); 1221 ohci_dump_ed(sed); 1222 ohci_dump_tds(setup); 1223 } 1224 #endif 1225 1226 /* Insert ED in schedule */ 1227 s = splusb(); 1228 ohci_hash_add_td(sc, setup); 1229 if (len != 0) 1230 ohci_hash_add_td(sc, data); 1231 ohci_hash_add_td(sc, stat); 1232 sed->ed.ed_tailp = LE(tail->physaddr); 1233 opipe->tail = tail; 1234 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1235 if (reqh->timeout && !sc->sc_bus.use_polling) { 1236 usb_timeout(ohci_timeout, reqh, 1237 MS_TO_TICKS(reqh->timeout), reqh->timo_handle); 1238 } 1239 splx(s); 1240 1241 #if USB_DEBUG 1242 if (ohcidebug > 5) { 1243 delay(5000); 1244 DPRINTF(("ohci_device_request: status=%x\n", 1245 OREAD4(sc, OHCI_COMMAND_STATUS))); 1246 ohci_dump_ed(sed); 1247 ohci_dump_tds(setup); 1248 } 1249 #endif 1250 1251 return (USBD_NORMAL_COMPLETION); 1252 1253 bad3: 1254 ohci_free_std(sc, tail); 1255 bad2: 1256 ohci_free_std(sc, stat); 1257 bad1: 1258 return (r); 1259 } 1260 1261 /* 1262 * Add an ED to the schedule. Called at splusb(). 1263 */ 1264 void 1265 ohci_add_ed(sed, head) 1266 ohci_soft_ed_t *sed; 1267 ohci_soft_ed_t *head; 1268 { 1269 SPLUSBCHECK; 1270 sed->next = head->next; 1271 sed->ed.ed_nexted = head->ed.ed_nexted; 1272 head->next = sed; 1273 head->ed.ed_nexted = LE(sed->physaddr); 1274 } 1275 1276 /* 1277 * Remove an ED from the schedule. Called at splusb(). 1278 */ 1279 void 1280 ohci_rem_ed(sed, head) 1281 ohci_soft_ed_t *sed; 1282 ohci_soft_ed_t *head; 1283 { 1284 ohci_soft_ed_t *p; 1285 1286 SPLUSBCHECK; 1287 1288 /* XXX */ 1289 for (p = head; p && p->next != sed; p = p->next) 1290 ; 1291 if (!p) 1292 panic("ohci_rem_ed: ED not found\n"); 1293 p->next = sed->next; 1294 p->ed.ed_nexted = sed->ed.ed_nexted; 1295 } 1296 1297 /* 1298 * When a transfer is completed the TD is added to the done queue by 1299 * the host controller. This queue is the processed by software. 1300 * Unfortunately the queue contains the physical address of the TD 1301 * and we have no simple way to translate this back to a kernel address. 1302 * To make the translation possible (and fast) we use a hash table of 1303 * TDs currently in the schedule. The physical address is used as the 1304 * hash value. 1305 */ 1306 1307 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1308 /* Called at splusb() */ 1309 void 1310 ohci_hash_add_td(sc, std) 1311 ohci_softc_t *sc; 1312 ohci_soft_td_t *std; 1313 { 1314 int h = HASH(std->physaddr); 1315 1316 SPLUSBCHECK; 1317 1318 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1319 } 1320 1321 /* Called at splusb() */ 1322 void 1323 ohci_hash_rem_td(sc, std) 1324 ohci_softc_t *sc; 1325 ohci_soft_td_t *std; 1326 { 1327 SPLUSBCHECK; 1328 1329 LIST_REMOVE(std, hnext); 1330 } 1331 1332 ohci_soft_td_t * 1333 ohci_hash_find_td(sc, a) 1334 ohci_softc_t *sc; 1335 ohci_physaddr_t a; 1336 { 1337 int h = HASH(a); 1338 ohci_soft_td_t *std; 1339 1340 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1341 std != 0; 1342 std = LIST_NEXT(std, hnext)) 1343 if (std->physaddr == a) 1344 return (std); 1345 panic("ohci_hash_find_td: addr 0x%08lx not found\n", (u_long)a); 1346 } 1347 1348 void 1349 ohci_timeout(addr) 1350 void *addr; 1351 { 1352 usbd_request_handle reqh = addr; 1353 int s; 1354 1355 DPRINTF(("ohci_timeout: reqh=%p\n", reqh)); 1356 1357 s = splusb(); 1358 reqh->device->bus->intr_context++; 1359 ohci_abort_req(reqh, USBD_TIMEOUT); 1360 reqh->device->bus->intr_context--; 1361 splx(s); 1362 } 1363 1364 #ifdef USB_DEBUG 1365 void 1366 ohci_dump_tds(std) 1367 ohci_soft_td_t *std; 1368 { 1369 for (; std; std = std->nexttd) 1370 ohci_dump_td(std); 1371 } 1372 1373 void 1374 ohci_dump_td(std) 1375 ohci_soft_td_t *std; 1376 { 1377 DPRINTF(("TD(%p) at %08lx: %b delay=%d ec=%d cc=%d\ncbp=0x%08lx " 1378 "nexttd=0x%08lx be=0x%08lx\n", 1379 std, (u_long)std->physaddr, 1380 (int)LE(std->td.td_flags), 1381 "\20\23R\24OUT\25IN\31TOG1\32SETTOGGLE", 1382 OHCI_TD_GET_DI(LE(std->td.td_flags)), 1383 OHCI_TD_GET_EC(LE(std->td.td_flags)), 1384 OHCI_TD_GET_CC(LE(std->td.td_flags)), 1385 (u_long)LE(std->td.td_cbp), 1386 (u_long)LE(std->td.td_nexttd), (u_long)LE(std->td.td_be))); 1387 } 1388 1389 void 1390 ohci_dump_ed(sed) 1391 ohci_soft_ed_t *sed; 1392 { 1393 DPRINTF(("ED(%p) at %08lx: addr=%d endpt=%d maxp=%d %b\ntailp=0x%08lx " 1394 "headp=%b nexted=0x%08lx\n", 1395 sed, (u_long)sed->physaddr, 1396 OHCI_ED_GET_FA(LE(sed->ed.ed_flags)), 1397 OHCI_ED_GET_EN(LE(sed->ed.ed_flags)), 1398 OHCI_ED_GET_MAXP(LE(sed->ed.ed_flags)), 1399 (int)LE(sed->ed.ed_flags), 1400 "\20\14OUT\15IN\16LOWSPEED\17SKIP\20ISO", 1401 (u_long)LE(sed->ed.ed_tailp), 1402 (u_long)LE(sed->ed.ed_headp), "\20\1HALT\2CARRY", 1403 (u_long)LE(sed->ed.ed_nexted))); 1404 } 1405 #endif 1406 1407 usbd_status 1408 ohci_open(pipe) 1409 usbd_pipe_handle pipe; 1410 { 1411 usbd_device_handle dev = pipe->device; 1412 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 1413 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1414 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 1415 u_int8_t addr = dev->address; 1416 ohci_soft_ed_t *sed; 1417 ohci_soft_td_t *std; 1418 usbd_status r; 1419 int s; 1420 1421 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1422 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1423 if (addr == sc->sc_addr) { 1424 switch (ed->bEndpointAddress) { 1425 case USB_CONTROL_ENDPOINT: 1426 pipe->methods = &ohci_root_ctrl_methods; 1427 break; 1428 case UE_DIR_IN | OHCI_INTR_ENDPT: 1429 pipe->methods = &ohci_root_intr_methods; 1430 break; 1431 default: 1432 return (USBD_INVAL); 1433 } 1434 } else { 1435 sed = ohci_alloc_sed(sc); 1436 if (sed == 0) 1437 goto bad0; 1438 std = ohci_alloc_std(sc); 1439 if (std == 0) 1440 goto bad1; 1441 opipe->sed = sed; 1442 opipe->tail = std; 1443 sed->ed.ed_flags = LE( 1444 OHCI_ED_SET_FA(addr) | 1445 OHCI_ED_SET_EN(ed->bEndpointAddress) | 1446 OHCI_ED_DIR_TD | 1447 (dev->lowspeed ? OHCI_ED_SPEED : 0) | 1448 ((ed->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS ? 1449 OHCI_ED_FORMAT_ISO : OHCI_ED_FORMAT_GEN) | 1450 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 1451 sed->ed.ed_headp = sed->ed.ed_tailp = LE(std->physaddr); 1452 1453 switch (ed->bmAttributes & UE_XFERTYPE) { 1454 case UE_CONTROL: 1455 pipe->methods = &ohci_device_ctrl_methods; 1456 r = usb_allocmem(&sc->sc_bus, 1457 sizeof(usb_device_request_t), 1458 0, &opipe->u.ctl.reqdma); 1459 if (r != USBD_NORMAL_COMPLETION) 1460 goto bad; 1461 s = splusb(); 1462 ohci_add_ed(sed, sc->sc_ctrl_head); 1463 splx(s); 1464 break; 1465 case UE_INTERRUPT: 1466 pipe->methods = &ohci_device_intr_methods; 1467 return (ohci_device_setintr(sc, opipe, ed->bInterval)); 1468 case UE_ISOCHRONOUS: 1469 printf("ohci_open: open iso unimplemented\n"); 1470 return (USBD_INVAL); 1471 case UE_BULK: 1472 pipe->methods = &ohci_device_bulk_methods; 1473 s = splusb(); 1474 ohci_add_ed(sed, sc->sc_bulk_head); 1475 splx(s); 1476 break; 1477 } 1478 } 1479 return (USBD_NORMAL_COMPLETION); 1480 1481 bad: 1482 ohci_free_std(sc, std); 1483 bad1: 1484 ohci_free_sed(sc, sed); 1485 bad0: 1486 return (USBD_NOMEM); 1487 1488 } 1489 1490 /* 1491 * Close a reqular pipe. 1492 * Assumes that there are no pending transactions. 1493 */ 1494 void 1495 ohci_close_pipe(pipe, head) 1496 usbd_pipe_handle pipe; 1497 ohci_soft_ed_t *head; 1498 { 1499 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 1500 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 1501 ohci_soft_ed_t *sed = opipe->sed; 1502 int s; 1503 1504 s = splusb(); 1505 #ifdef DIAGNOSTIC 1506 sed->ed.ed_flags |= LE(OHCI_ED_SKIP); 1507 if ((sed->ed.ed_tailp & LE(OHCI_TAILMASK)) != 1508 (sed->ed.ed_headp & LE(OHCI_TAILMASK))) { 1509 ohci_physaddr_t td = sed->ed.ed_headp; 1510 ohci_soft_td_t *std; 1511 for (std = LIST_FIRST(&sc->sc_hash_tds[HASH(td)]); 1512 std != 0; 1513 std = LIST_NEXT(std, hnext)) 1514 if (std->physaddr == td) 1515 break; 1516 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 1517 "tl=0x%x pipe=%p, std=%p\n", sed, 1518 (int)LE(sed->ed.ed_headp), (int)LE(sed->ed.ed_tailp), 1519 pipe, std); 1520 usb_delay_ms(&sc->sc_bus, 2); 1521 if ((sed->ed.ed_tailp & LE(OHCI_TAILMASK)) != 1522 (sed->ed.ed_headp & LE(OHCI_TAILMASK))) 1523 printf("ohci_close_pipe: pipe still not empty\n"); 1524 } 1525 #endif 1526 ohci_rem_ed(sed, head); 1527 splx(s); 1528 ohci_free_std(sc, opipe->tail); 1529 ohci_free_sed(sc, opipe->sed); 1530 } 1531 1532 /* 1533 * Abort a device request. 1534 * If this routine is called at splusb() it guarantees that the request 1535 * will be removed from the hardware scheduling and that the callback 1536 * for it will be called with USBD_CANCELLED status. 1537 * It's impossible to guarantee that the requested transfer will not 1538 * have happened since the hardware runs concurrently. 1539 * If the transaction has already happened we rely on the ordinary 1540 * interrupt processing to process it. 1541 */ 1542 void 1543 ohci_abort_req(reqh, status) 1544 usbd_request_handle reqh; 1545 usbd_status status; 1546 { 1547 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 1548 ohci_soft_ed_t *sed; 1549 1550 DPRINTF(("ohci_abort_req: reqh=%p pipe=%p\n", reqh, opipe)); 1551 1552 reqh->status = status; 1553 1554 usb_untimeout(ohci_timeout, reqh, reqh->timo_handle); 1555 1556 sed = opipe->sed; 1557 DPRINTFN(1,("ohci_abort_req: stop ed=%p\n", sed)); 1558 sed->ed.ed_flags |= LE(OHCI_ED_SKIP); /* force hardware skip */ 1559 1560 if (reqh->device->bus->intr_context) { 1561 /* We have no process context, so we can't use tsleep(). */ 1562 timeout(ohci_abort_req_end, reqh, hz / USB_FRAMES_PER_SECOND); 1563 } else { 1564 usb_delay_ms(opipe->pipe.device->bus, 1); 1565 ohci_abort_req_end(reqh); 1566 } 1567 } 1568 1569 void 1570 ohci_abort_req_end(v) 1571 void *v; 1572 { 1573 usbd_request_handle reqh = v; 1574 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 1575 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 1576 ohci_soft_ed_t *sed; 1577 ohci_soft_td_t *p, *n; 1578 int s; 1579 1580 s = splusb(); 1581 1582 p = reqh->hcpriv; 1583 #ifdef DIAGNOSTIC 1584 if (!p) { 1585 printf("ohci_abort_req: hcpriv==0\n"); 1586 return; 1587 } 1588 #endif 1589 for (; p->reqh == reqh; p = n) { 1590 n = p->nexttd; 1591 ohci_hash_rem_td(sc, p); 1592 ohci_free_std(sc, p); 1593 } 1594 1595 sed = opipe->sed; 1596 DPRINTFN(2,("ohci_abort_req: set hd=%x, tl=%x\n", 1597 (int)LE(p->physaddr), (int)LE(sed->ed.ed_tailp))); 1598 sed->ed.ed_headp = p->physaddr; /* unlink TDs */ 1599 sed->ed.ed_flags &= LE(~OHCI_ED_SKIP); /* remove hardware skip */ 1600 1601 usb_transfer_complete(reqh); 1602 1603 splx(s); 1604 } 1605 1606 /* 1607 * Data structures and routines to emulate the root hub. 1608 */ 1609 usb_device_descriptor_t ohci_devd = { 1610 USB_DEVICE_DESCRIPTOR_SIZE, 1611 UDESC_DEVICE, /* type */ 1612 {0x00, 0x01}, /* USB version */ 1613 UCLASS_HUB, /* class */ 1614 USUBCLASS_HUB, /* subclass */ 1615 0, /* protocol */ 1616 64, /* max packet */ 1617 {0},{0},{0x00,0x01}, /* device id */ 1618 1,2,0, /* string indicies */ 1619 1 /* # of configurations */ 1620 }; 1621 1622 usb_config_descriptor_t ohci_confd = { 1623 USB_CONFIG_DESCRIPTOR_SIZE, 1624 UDESC_CONFIG, 1625 {USB_CONFIG_DESCRIPTOR_SIZE + 1626 USB_INTERFACE_DESCRIPTOR_SIZE + 1627 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1628 1, 1629 1, 1630 0, 1631 UC_SELF_POWERED, 1632 0 /* max power */ 1633 }; 1634 1635 usb_interface_descriptor_t ohci_ifcd = { 1636 USB_INTERFACE_DESCRIPTOR_SIZE, 1637 UDESC_INTERFACE, 1638 0, 1639 0, 1640 1, 1641 UCLASS_HUB, 1642 USUBCLASS_HUB, 1643 0, 1644 0 1645 }; 1646 1647 usb_endpoint_descriptor_t ohci_endpd = { 1648 USB_ENDPOINT_DESCRIPTOR_SIZE, 1649 UDESC_ENDPOINT, 1650 UE_DIR_IN | OHCI_INTR_ENDPT, 1651 UE_INTERRUPT, 1652 {8, 0}, /* max packet */ 1653 255 1654 }; 1655 1656 usb_hub_descriptor_t ohci_hubd = { 1657 USB_HUB_DESCRIPTOR_SIZE, 1658 UDESC_HUB, 1659 0, 1660 {0,0}, 1661 0, 1662 0, 1663 {0}, 1664 }; 1665 1666 int 1667 ohci_str(p, l, s) 1668 usb_string_descriptor_t *p; 1669 int l; 1670 char *s; 1671 { 1672 int i; 1673 1674 if (l == 0) 1675 return (0); 1676 p->bLength = 2 * strlen(s) + 2; 1677 if (l == 1) 1678 return (1); 1679 p->bDescriptorType = UDESC_STRING; 1680 l -= 2; 1681 for (i = 0; s[i] && l > 1; i++, l -= 2) 1682 USETW2(p->bString[i], 0, s[i]); 1683 return (2*i+2); 1684 } 1685 1686 /* 1687 * Simulate a hardware hub by handling all the necessary requests. 1688 */ 1689 usbd_status 1690 ohci_root_ctrl_transfer(reqh) 1691 usbd_request_handle reqh; 1692 { 1693 usbd_status r; 1694 1695 /* Insert last in queue. */ 1696 r = usb_insert_transfer(reqh); 1697 if (r != USBD_NORMAL_COMPLETION) 1698 return (r); 1699 1700 /* Pipe isn't running, start first */ 1701 return (ohci_root_ctrl_start(SIMPLEQ_FIRST(&reqh->pipe->queue))); 1702 } 1703 1704 usbd_status 1705 ohci_root_ctrl_start(reqh) 1706 usbd_request_handle reqh; 1707 { 1708 ohci_softc_t *sc = (ohci_softc_t *)reqh->pipe->device->bus; 1709 usb_device_request_t *req; 1710 void *buf; 1711 int port, i; 1712 int s, len, value, index, l, totlen = 0; 1713 usb_port_status_t ps; 1714 usb_hub_descriptor_t hubd; 1715 usbd_status r; 1716 u_int32_t v; 1717 1718 #ifdef DIAGNOSTIC 1719 if (!(reqh->rqflags & URQ_REQUEST)) 1720 /* XXX panic */ 1721 return (USBD_INVAL); 1722 #endif 1723 req = &reqh->request; 1724 1725 DPRINTFN(4,("ohci_root_ctrl_control type=0x%02x request=%02x\n", 1726 req->bmRequestType, req->bRequest)); 1727 1728 len = UGETW(req->wLength); 1729 value = UGETW(req->wValue); 1730 index = UGETW(req->wIndex); 1731 1732 if (len != 0) 1733 buf = KERNADDR(&reqh->dmabuf); 1734 #ifdef DIAGNOSTIC 1735 else 1736 buf = 0; 1737 #endif 1738 1739 #define C(x,y) ((x) | ((y) << 8)) 1740 switch(C(req->bRequest, req->bmRequestType)) { 1741 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 1742 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 1743 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 1744 /* 1745 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 1746 * for the integrated root hub. 1747 */ 1748 break; 1749 case C(UR_GET_CONFIG, UT_READ_DEVICE): 1750 if (len > 0) { 1751 *(u_int8_t *)buf = sc->sc_conf; 1752 totlen = 1; 1753 } 1754 break; 1755 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 1756 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value)); 1757 switch(value >> 8) { 1758 case UDESC_DEVICE: 1759 if ((value & 0xff) != 0) { 1760 r = USBD_IOERROR; 1761 goto ret; 1762 } 1763 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1764 USETW(ohci_devd.idVendor, sc->sc_id_vendor); 1765 memcpy(buf, &ohci_devd, l); 1766 break; 1767 case UDESC_CONFIG: 1768 if ((value & 0xff) != 0) { 1769 r = USBD_IOERROR; 1770 goto ret; 1771 } 1772 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 1773 memcpy(buf, &ohci_confd, l); 1774 buf = (char *)buf + l; 1775 len -= l; 1776 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 1777 totlen += l; 1778 memcpy(buf, &ohci_ifcd, l); 1779 buf = (char *)buf + l; 1780 len -= l; 1781 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 1782 totlen += l; 1783 memcpy(buf, &ohci_endpd, l); 1784 break; 1785 case UDESC_STRING: 1786 if (len == 0) 1787 break; 1788 *(u_int8_t *)buf = 0; 1789 totlen = 1; 1790 switch (value & 0xff) { 1791 case 1: /* Vendor */ 1792 totlen = ohci_str(buf, len, sc->sc_vendor); 1793 break; 1794 case 2: /* Product */ 1795 totlen = ohci_str(buf, len, "OHCI root hub"); 1796 break; 1797 } 1798 break; 1799 default: 1800 r = USBD_IOERROR; 1801 goto ret; 1802 } 1803 break; 1804 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 1805 if (len > 0) { 1806 *(u_int8_t *)buf = 0; 1807 totlen = 1; 1808 } 1809 break; 1810 case C(UR_GET_STATUS, UT_READ_DEVICE): 1811 if (len > 1) { 1812 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 1813 totlen = 2; 1814 } 1815 break; 1816 case C(UR_GET_STATUS, UT_READ_INTERFACE): 1817 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 1818 if (len > 1) { 1819 USETW(((usb_status_t *)buf)->wStatus, 0); 1820 totlen = 2; 1821 } 1822 break; 1823 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 1824 if (value >= USB_MAX_DEVICES) { 1825 r = USBD_IOERROR; 1826 goto ret; 1827 } 1828 sc->sc_addr = value; 1829 break; 1830 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 1831 if (value != 0 && value != 1) { 1832 r = USBD_IOERROR; 1833 goto ret; 1834 } 1835 sc->sc_conf = value; 1836 break; 1837 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 1838 break; 1839 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 1840 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 1841 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 1842 r = USBD_IOERROR; 1843 goto ret; 1844 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 1845 break; 1846 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 1847 break; 1848 /* Hub requests */ 1849 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 1850 break; 1851 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 1852 DPRINTFN(8, ("ohci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 1853 "port=%d feature=%d\n", 1854 index, value)); 1855 if (index < 1 || index > sc->sc_noport) { 1856 r = USBD_IOERROR; 1857 goto ret; 1858 } 1859 port = OHCI_RH_PORT_STATUS(index); 1860 switch(value) { 1861 case UHF_PORT_ENABLE: 1862 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 1863 break; 1864 case UHF_PORT_SUSPEND: 1865 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 1866 break; 1867 case UHF_PORT_POWER: 1868 OWRITE4(sc, port, UPS_LOW_SPEED); 1869 break; 1870 case UHF_C_PORT_CONNECTION: 1871 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 1872 break; 1873 case UHF_C_PORT_ENABLE: 1874 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 1875 break; 1876 case UHF_C_PORT_SUSPEND: 1877 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 1878 break; 1879 case UHF_C_PORT_OVER_CURRENT: 1880 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 1881 break; 1882 case UHF_C_PORT_RESET: 1883 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 1884 break; 1885 default: 1886 r = USBD_IOERROR; 1887 goto ret; 1888 } 1889 switch(value) { 1890 case UHF_C_PORT_CONNECTION: 1891 case UHF_C_PORT_ENABLE: 1892 case UHF_C_PORT_SUSPEND: 1893 case UHF_C_PORT_OVER_CURRENT: 1894 case UHF_C_PORT_RESET: 1895 /* Enable RHSC interrupt if condition is cleared. */ 1896 if ((OREAD4(sc, port) >> 16) == 0) 1897 ohci_rhsc_able(sc, 1); 1898 break; 1899 default: 1900 break; 1901 } 1902 break; 1903 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 1904 if (value != 0) { 1905 r = USBD_IOERROR; 1906 goto ret; 1907 } 1908 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 1909 hubd = ohci_hubd; 1910 hubd.bNbrPorts = sc->sc_noport; 1911 USETW(hubd.wHubCharacteristics, 1912 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 1913 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 1914 /* XXX overcurrent */ 1915 ); 1916 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 1917 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 1918 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 1919 hubd.DeviceRemovable[i++] = (u_int8_t)v; 1920 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 1921 l = min(len, hubd.bDescLength); 1922 totlen = l; 1923 memcpy(buf, &hubd, l); 1924 break; 1925 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 1926 if (len != 4) { 1927 r = USBD_IOERROR; 1928 goto ret; 1929 } 1930 memset(buf, 0, len); /* ? XXX */ 1931 totlen = len; 1932 break; 1933 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 1934 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n", 1935 index)); 1936 if (index < 1 || index > sc->sc_noport) { 1937 r = USBD_IOERROR; 1938 goto ret; 1939 } 1940 if (len != 4) { 1941 r = USBD_IOERROR; 1942 goto ret; 1943 } 1944 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 1945 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n", 1946 v)); 1947 USETW(ps.wPortStatus, v); 1948 USETW(ps.wPortChange, v >> 16); 1949 l = min(len, sizeof ps); 1950 memcpy(buf, &ps, l); 1951 totlen = l; 1952 break; 1953 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 1954 r = USBD_IOERROR; 1955 goto ret; 1956 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 1957 break; 1958 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 1959 if (index < 1 || index > sc->sc_noport) { 1960 r = USBD_IOERROR; 1961 goto ret; 1962 } 1963 port = OHCI_RH_PORT_STATUS(index); 1964 switch(value) { 1965 case UHF_PORT_ENABLE: 1966 OWRITE4(sc, port, UPS_PORT_ENABLED); 1967 break; 1968 case UHF_PORT_SUSPEND: 1969 OWRITE4(sc, port, UPS_SUSPEND); 1970 break; 1971 case UHF_PORT_RESET: 1972 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n", 1973 index)); 1974 OWRITE4(sc, port, UPS_RESET); 1975 for (i = 0; i < 10; i++) { 1976 usb_delay_ms(&sc->sc_bus, 10); 1977 if ((OREAD4(sc, port) & UPS_RESET) == 0) 1978 break; 1979 } 1980 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n", 1981 index, OREAD4(sc, port))); 1982 break; 1983 case UHF_PORT_POWER: 1984 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power " 1985 "%d\n", index)); 1986 OWRITE4(sc, port, UPS_PORT_POWER); 1987 break; 1988 default: 1989 r = USBD_IOERROR; 1990 goto ret; 1991 } 1992 break; 1993 default: 1994 r = USBD_IOERROR; 1995 goto ret; 1996 } 1997 reqh->actlen = totlen; 1998 r = USBD_NORMAL_COMPLETION; 1999 ret: 2000 reqh->status = r; 2001 s = splusb(); 2002 usb_transfer_complete(reqh); 2003 splx(s); 2004 return (USBD_IN_PROGRESS); 2005 } 2006 2007 /* Abort a root control request. */ 2008 void 2009 ohci_root_ctrl_abort(reqh) 2010 usbd_request_handle reqh; 2011 { 2012 /* Nothing to do, all transfers are synchronous. */ 2013 } 2014 2015 /* Close the root pipe. */ 2016 void 2017 ohci_root_ctrl_close(pipe) 2018 usbd_pipe_handle pipe; 2019 { 2020 DPRINTF(("ohci_root_ctrl_close\n")); 2021 /* Nothing to do. */ 2022 } 2023 2024 usbd_status 2025 ohci_root_intr_transfer(reqh) 2026 usbd_request_handle reqh; 2027 { 2028 usbd_status r; 2029 2030 /* Insert last in queue. */ 2031 r = usb_insert_transfer(reqh); 2032 if (r != USBD_NORMAL_COMPLETION) 2033 return (r); 2034 2035 /* Pipe isn't running, start first */ 2036 return (ohci_root_intr_start(SIMPLEQ_FIRST(&reqh->pipe->queue))); 2037 } 2038 2039 usbd_status 2040 ohci_root_intr_start(reqh) 2041 usbd_request_handle reqh; 2042 { 2043 usbd_pipe_handle pipe = reqh->pipe; 2044 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 2045 2046 sc->sc_intrreqh = reqh; 2047 2048 return (USBD_IN_PROGRESS); 2049 } 2050 2051 /* Abort a root interrupt request. */ 2052 void 2053 ohci_root_intr_abort(reqh) 2054 usbd_request_handle reqh; 2055 { 2056 /* No need to abort. */ 2057 } 2058 2059 /* Close the root pipe. */ 2060 void 2061 ohci_root_intr_close(pipe) 2062 usbd_pipe_handle pipe; 2063 { 2064 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 2065 2066 DPRINTF(("ohci_root_intr_close\n")); 2067 2068 sc->sc_intrreqh = 0; 2069 } 2070 2071 /************************/ 2072 2073 usbd_status 2074 ohci_device_ctrl_transfer(reqh) 2075 usbd_request_handle reqh; 2076 { 2077 usbd_status r; 2078 2079 /* Insert last in queue. */ 2080 r = usb_insert_transfer(reqh); 2081 if (r != USBD_NORMAL_COMPLETION) 2082 return (r); 2083 2084 /* Pipe isn't running, start first */ 2085 return (ohci_device_ctrl_start(SIMPLEQ_FIRST(&reqh->pipe->queue))); 2086 } 2087 2088 usbd_status 2089 ohci_device_ctrl_start(reqh) 2090 usbd_request_handle reqh; 2091 { 2092 ohci_softc_t *sc = (ohci_softc_t *)reqh->pipe->device->bus; 2093 usbd_status r; 2094 2095 #ifdef DIAGNOSTIC 2096 if (!(reqh->rqflags & URQ_REQUEST)) { 2097 /* XXX panic */ 2098 printf("ohci_device_ctrl_transfer: not a request\n"); 2099 return (USBD_INVAL); 2100 } 2101 #endif 2102 2103 r = ohci_device_request(reqh); 2104 if (r != USBD_NORMAL_COMPLETION) 2105 return (r); 2106 2107 if (sc->sc_bus.use_polling) 2108 ohci_waitintr(sc, reqh); 2109 return (USBD_IN_PROGRESS); 2110 } 2111 2112 /* Abort a device control request. */ 2113 void 2114 ohci_device_ctrl_abort(reqh) 2115 usbd_request_handle reqh; 2116 { 2117 DPRINTF(("ohci_device_ctrl_abort: reqh=%p\n", reqh)); 2118 ohci_abort_req(reqh, USBD_CANCELLED); 2119 } 2120 2121 /* Close a device control pipe. */ 2122 void 2123 ohci_device_ctrl_close(pipe) 2124 usbd_pipe_handle pipe; 2125 { 2126 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 2127 2128 DPRINTF(("ohci_device_ctrl_close: pipe=%p\n", pipe)); 2129 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2130 } 2131 2132 /************************/ 2133 2134 void 2135 ohci_device_clear_toggle(pipe) 2136 usbd_pipe_handle pipe; 2137 { 2138 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2139 2140 opipe->sed->ed.ed_tailp &= LE(~OHCI_TOGGLECARRY); 2141 } 2142 2143 void 2144 ohci_noop(pipe) 2145 usbd_pipe_handle pipe; 2146 { 2147 } 2148 2149 usbd_status 2150 ohci_device_bulk_transfer(reqh) 2151 usbd_request_handle reqh; 2152 { 2153 usbd_status r; 2154 2155 /* Insert last in queue. */ 2156 r = usb_insert_transfer(reqh); 2157 if (r != USBD_NORMAL_COMPLETION) 2158 return (r); 2159 2160 /* Pipe isn't running, start first */ 2161 return (ohci_device_bulk_start(SIMPLEQ_FIRST(&reqh->pipe->queue))); 2162 } 2163 2164 usbd_status 2165 ohci_device_bulk_start(reqh) 2166 usbd_request_handle reqh; 2167 { 2168 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 2169 usbd_device_handle dev = opipe->pipe.device; 2170 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 2171 int addr = dev->address; 2172 ohci_soft_td_t *data, *tail, *tdp; 2173 ohci_soft_ed_t *sed; 2174 int s, len, isread, endpt; 2175 usbd_status r; 2176 2177 #ifdef DIAGNOSTIC 2178 if (reqh->rqflags & URQ_REQUEST) { 2179 /* XXX panic */ 2180 printf("ohci_device_bulk_start: a request\n"); 2181 return (USBD_INVAL); 2182 } 2183 #endif 2184 2185 len = reqh->length; 2186 endpt = reqh->pipe->endpoint->edesc->bEndpointAddress; 2187 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2188 sed = opipe->sed; 2189 2190 DPRINTFN(4,("ohci_device_bulk_start: reqh=%p len=%d isread=%d " 2191 "flags=%d endpt=%d\n", reqh, len, isread, reqh->flags, 2192 endpt)); 2193 2194 opipe->u.bulk.isread = isread; 2195 opipe->u.bulk.length = len; 2196 2197 /* Update device address */ 2198 sed->ed.ed_flags = LE( 2199 (LE(sed->ed.ed_flags) & ~OHCI_ED_ADDRMASK) | 2200 OHCI_ED_SET_FA(addr)); 2201 2202 /* Allocate a chain of new TDs (including a new tail). */ 2203 data = opipe->tail; 2204 r = ohci_alloc_std_chain(opipe, sc, len, isread, 2205 reqh->flags & USBD_SHORT_XFER_OK, 2206 &reqh->dmabuf, data, &tail); 2207 if (r != USBD_NORMAL_COMPLETION) 2208 return (r); 2209 2210 tail->reqh = 0; 2211 reqh->hcpriv = data; 2212 2213 DPRINTFN(4,("ohci_device_bulk_start: ed_flags=0x%08x td_flags=0x%08x " 2214 "td_cbp=0x%08x td_be=0x%08x\n", 2215 (int)LE(sed->ed.ed_flags), (int)LE(data->td.td_flags), 2216 (int)LE(data->td.td_cbp), (int)LE(data->td.td_be))); 2217 2218 #ifdef USB_DEBUG 2219 if (ohcidebug > 4) { 2220 ohci_dump_ed(sed); 2221 ohci_dump_tds(data); 2222 } 2223 #endif 2224 2225 /* Insert ED in schedule */ 2226 s = splusb(); 2227 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 2228 tdp->reqh = reqh; 2229 ohci_hash_add_td(sc, tdp); 2230 } 2231 sed->ed.ed_tailp = LE(tail->physaddr); 2232 opipe->tail = tail; 2233 sed->ed.ed_flags &= LE(~OHCI_ED_SKIP); 2234 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 2235 if (reqh->timeout && !sc->sc_bus.use_polling) { 2236 usb_timeout(ohci_timeout, reqh, 2237 MS_TO_TICKS(reqh->timeout), reqh->timo_handle); 2238 } 2239 2240 #ifdef USB_DEBUG 2241 if (ohcidebug > 5) { 2242 delay(5000); 2243 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 2244 OREAD4(sc, OHCI_COMMAND_STATUS))); 2245 ohci_dump_ed(sed); 2246 ohci_dump_tds(data); 2247 } 2248 #endif 2249 2250 splx(s); 2251 2252 return (USBD_IN_PROGRESS); 2253 } 2254 2255 void 2256 ohci_device_bulk_abort(reqh) 2257 usbd_request_handle reqh; 2258 { 2259 DPRINTF(("ohci_device_bulk_abort: reqh=%p\n", reqh)); 2260 ohci_abort_req(reqh, USBD_CANCELLED); 2261 } 2262 2263 /* 2264 * Close a device bulk pipe. 2265 */ 2266 void 2267 ohci_device_bulk_close(pipe) 2268 usbd_pipe_handle pipe; 2269 { 2270 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 2271 2272 DPRINTF(("ohci_device_bulk_close: pipe=%p\n", pipe)); 2273 ohci_close_pipe(pipe, sc->sc_bulk_head); 2274 } 2275 2276 /************************/ 2277 2278 usbd_status 2279 ohci_device_intr_transfer(reqh) 2280 usbd_request_handle reqh; 2281 { 2282 usbd_status r; 2283 2284 /* Insert last in queue. */ 2285 r = usb_insert_transfer(reqh); 2286 if (r != USBD_NORMAL_COMPLETION) 2287 return (r); 2288 2289 /* Pipe isn't running, start first */ 2290 return (ohci_device_intr_start(SIMPLEQ_FIRST(&reqh->pipe->queue))); 2291 } 2292 2293 usbd_status 2294 ohci_device_intr_start(reqh) 2295 usbd_request_handle reqh; 2296 { 2297 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 2298 usbd_device_handle dev = opipe->pipe.device; 2299 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 2300 ohci_soft_ed_t *sed = opipe->sed; 2301 ohci_soft_td_t *data, *tail; 2302 int len; 2303 int s; 2304 2305 DPRINTFN(3, ("ohci_device_intr_transfer: reqh=%p len=%d " 2306 "flags=%d priv=%p\n", 2307 reqh, reqh->length, reqh->flags, reqh->priv)); 2308 2309 #ifdef DIAGNOSTIC 2310 if (reqh->rqflags & URQ_REQUEST) 2311 panic("ohci_device_intr_transfer: a request\n"); 2312 #endif 2313 2314 len = reqh->length; 2315 2316 data = opipe->tail; 2317 tail = ohci_alloc_std(sc); 2318 if (!tail) 2319 return (USBD_NOMEM); 2320 tail->reqh = 0; 2321 2322 data->td.td_flags = LE( 2323 OHCI_TD_IN | OHCI_TD_NOCC | 2324 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 2325 if (reqh->flags & USBD_SHORT_XFER_OK) 2326 data->td.td_flags |= LE(OHCI_TD_R); 2327 data->td.td_cbp = LE(DMAADDR(&reqh->dmabuf)); 2328 data->nexttd = tail; 2329 data->td.td_nexttd = LE(tail->physaddr); 2330 data->td.td_be = LE(LE(data->td.td_cbp) + len - 1); 2331 data->len = len; 2332 data->reqh = reqh; 2333 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 2334 reqh->hcpriv = data; 2335 2336 #if USB_DEBUG 2337 if (ohcidebug > 5) { 2338 DPRINTF(("ohci_device_intr_transfer:\n")); 2339 ohci_dump_ed(sed); 2340 ohci_dump_tds(data); 2341 } 2342 #endif 2343 2344 /* Insert ED in schedule */ 2345 s = splusb(); 2346 ohci_hash_add_td(sc, data); 2347 sed->ed.ed_tailp = LE(tail->physaddr); 2348 opipe->tail = tail; 2349 sed->ed.ed_flags &= LE(~OHCI_ED_SKIP); 2350 2351 #ifdef USB_DEBUG 2352 if (ohcidebug > 5) { 2353 delay(5000); 2354 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 2355 OREAD4(sc, OHCI_COMMAND_STATUS))); 2356 ohci_dump_ed(sed); 2357 ohci_dump_tds(data); 2358 } 2359 #endif 2360 splx(s); 2361 2362 return (USBD_IN_PROGRESS); 2363 } 2364 2365 /* Abort a device control request. */ 2366 void 2367 ohci_device_intr_abort(reqh) 2368 usbd_request_handle reqh; 2369 { 2370 if (reqh->pipe->intrreqh == reqh) { 2371 DPRINTF(("ohci_device_intr_abort: remove\n")); 2372 reqh->pipe->intrreqh = 0; 2373 } 2374 ohci_abort_req(reqh, USBD_CANCELLED); 2375 } 2376 2377 /* Close a device interrupt pipe. */ 2378 void 2379 ohci_device_intr_close(pipe) 2380 usbd_pipe_handle pipe; 2381 { 2382 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2383 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 2384 int nslots = opipe->u.intr.nslots; 2385 int pos = opipe->u.intr.pos; 2386 int j; 2387 ohci_soft_ed_t *p, *sed = opipe->sed; 2388 int s; 2389 2390 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n", 2391 pipe, nslots, pos)); 2392 s = splusb(); 2393 sed->ed.ed_flags |= LE(OHCI_ED_SKIP); 2394 if ((sed->ed.ed_tailp & LE(OHCI_TAILMASK)) != 2395 (sed->ed.ed_headp & LE(OHCI_TAILMASK))) 2396 usb_delay_ms(&sc->sc_bus, 2); 2397 2398 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 2399 ; 2400 if (!p) 2401 panic("ohci_device_intr_close: ED not found\n"); 2402 p->next = sed->next; 2403 p->ed.ed_nexted = sed->ed.ed_nexted; 2404 splx(s); 2405 2406 for (j = 0; j < nslots; j++) 2407 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 2408 2409 ohci_free_std(sc, opipe->tail); 2410 ohci_free_sed(sc, opipe->sed); 2411 } 2412 2413 usbd_status 2414 ohci_device_setintr(sc, opipe, ival) 2415 ohci_softc_t *sc; 2416 struct ohci_pipe *opipe; 2417 int ival; 2418 { 2419 int i, j, s, best; 2420 u_int npoll, slow, shigh, nslots; 2421 u_int bestbw, bw; 2422 ohci_soft_ed_t *hsed, *sed = opipe->sed; 2423 2424 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe)); 2425 if (ival == 0) { 2426 printf("ohci_setintr: 0 interval\n"); 2427 return (USBD_INVAL); 2428 } 2429 2430 npoll = OHCI_NO_INTRS; 2431 while (npoll > ival) 2432 npoll /= 2; 2433 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll)); 2434 2435 /* 2436 * We now know which level in the tree the ED must go into. 2437 * Figure out which slot has most bandwidth left over. 2438 * Slots to examine: 2439 * npoll 2440 * 1 0 2441 * 2 1 2 2442 * 4 3 4 5 6 2443 * 8 7 8 9 10 11 12 13 14 2444 * N (N-1) .. (N-1+N-1) 2445 */ 2446 slow = npoll-1; 2447 shigh = slow + npoll; 2448 nslots = OHCI_NO_INTRS / npoll; 2449 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 2450 bw = 0; 2451 for (j = 0; j < nslots; j++) 2452 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 2453 if (bw < bestbw) { 2454 best = i; 2455 bestbw = bw; 2456 } 2457 } 2458 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n", 2459 best, slow, shigh, bestbw)); 2460 2461 s = splusb(); 2462 hsed = sc->sc_eds[best]; 2463 sed->next = hsed->next; 2464 sed->ed.ed_nexted = hsed->ed.ed_nexted; 2465 hsed->next = sed; 2466 hsed->ed.ed_nexted = LE(sed->physaddr); 2467 splx(s); 2468 2469 for (j = 0; j < nslots; j++) 2470 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 2471 opipe->u.intr.nslots = nslots; 2472 opipe->u.intr.pos = best; 2473 2474 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe)); 2475 return (USBD_NORMAL_COMPLETION); 2476 } 2477 2478
Indexes created Thu Sep 25 16:09:42 GMT 2025