ohci.c revision 1.5
1 /* $NetBSD: ohci.c,v 1.5 1998/07/26 17:42:48 augustss Exp $ */ 2 3 /* 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Author: Lennart Augustsson <augustss (at) carlstedt.se> 8 * Carlstedt Research & Technology 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * USB Open Host Controller driver. 41 * 42 * OHCI spec: http://www.intel.com/design/usb/ohci11d.pdf 43 * USB spec: http://www.teleport.com/cgi-bin/mailmerge.cgi/~usb/cgiform.tpl 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/malloc.h> 50 #include <sys/device.h> 51 #include <sys/proc.h> 52 #include <sys/queue.h> 53 #include <sys/select.h> 54 55 #include <machine/bus.h> 56 57 #include <dev/usb/usb.h> 58 #include <dev/usb/usbdi.h> 59 #include <dev/usb/usbdivar.h> 60 #include <dev/usb/usb_quirks.h> 61 #include <dev/usb/usb_mem.h> 62 63 #include <dev/usb/ohcireg.h> 64 #include <dev/usb/ohcivar.h> 65 66 int ohcidebug = 0; 67 68 struct ohci_pipe; 69 70 ohci_soft_ed_t *ohci_alloc_sed __P((ohci_softc_t *)); 71 void ohci_free_sed __P((ohci_softc_t *, ohci_soft_ed_t *)); 72 73 ohci_soft_td_t *ohci_alloc_std __P((ohci_softc_t *)); 74 void ohci_free_std __P((ohci_softc_t *, ohci_soft_td_t *)); 75 76 usbd_status ohci_open __P((usbd_pipe_handle)); 77 void ohci_poll __P((struct usbd_bus *)); 78 void ohci_waitintr __P((ohci_softc_t *, usbd_request_handle)); 79 void ohci_rhsc __P((ohci_softc_t *, usbd_request_handle)); 80 void ohci_process_done __P((ohci_softc_t *, ohci_physaddr_t)); 81 void ohci_ctrl_done __P((ohci_softc_t *, usbd_request_handle)); 82 void ohci_intr_done __P((ohci_softc_t *, usbd_request_handle)); 83 void ohci_bulk_done __P((ohci_softc_t *, usbd_request_handle)); 84 85 usbd_status ohci_device_request __P((usbd_request_handle reqh)); 86 void ohci_add_ed __P((ohci_soft_ed_t *, ohci_soft_ed_t *)); 87 void ohci_rem_ed __P((ohci_soft_ed_t *, ohci_soft_ed_t *)); 88 void ohci_hash_add_td __P((ohci_softc_t *, ohci_soft_td_t *)); 89 void ohci_hash_rem_td __P((ohci_softc_t *, ohci_soft_td_t *)); 90 ohci_soft_td_t *ohci_hash_find_td __P((ohci_softc_t *, ohci_physaddr_t)); 91 92 usbd_status ohci_root_ctrl_transfer __P((usbd_request_handle)); 93 void ohci_root_ctrl_abort __P((usbd_request_handle)); 94 void ohci_root_ctrl_close __P((usbd_pipe_handle)); 95 96 usbd_status ohci_root_intr_transfer __P((usbd_request_handle)); 97 void ohci_root_intr_abort __P((usbd_request_handle)); 98 void ohci_root_intr_close __P((usbd_pipe_handle)); 99 100 usbd_status ohci_device_ctrl_transfer __P((usbd_request_handle)); 101 void ohci_device_ctrl_abort __P((usbd_request_handle)); 102 void ohci_device_ctrl_close __P((usbd_pipe_handle)); 103 104 usbd_status ohci_device_bulk_transfer __P((usbd_request_handle)); 105 void ohci_device_bulk_abort __P((usbd_request_handle)); 106 void ohci_device_bulk_close __P((usbd_pipe_handle)); 107 108 usbd_status ohci_device_intr_transfer __P((usbd_request_handle)); 109 void ohci_device_intr_abort __P((usbd_request_handle)); 110 void ohci_device_intr_close __P((usbd_pipe_handle)); 111 usbd_status ohci_device_setintr __P((ohci_softc_t *sc, 112 struct ohci_pipe *pipe, int ival)); 113 114 int ohci_str __P((usb_string_descriptor_t *, int, char *)); 115 116 void ohci_timeout __P((void *)); 117 void ohci_rhsc_able __P((ohci_softc_t *, int)); 118 119 #ifdef USB_DEBUG 120 ohci_softc_t *thesc; 121 void ohci_dumpregs __P((ohci_softc_t *)); 122 void ohci_dump_tds __P((ohci_soft_td_t *)); 123 void ohci_dump_td __P((ohci_soft_td_t *)); 124 void ohci_dump_ed __P((ohci_soft_ed_t *)); 125 #endif 126 127 #define OWRITE4(sc, r, x) bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)) 128 #define OREAD4(sc, r) bus_space_read_4((sc)->iot, (sc)->ioh, (r)) 129 #define OREAD2(sc, r) bus_space_read_2((sc)->iot, (sc)->ioh, (r)) 130 131 /* Reverse the bits in a value 0 .. 31 */ 132 static u_int8_t revbits[OHCI_NO_INTRS] = 133 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 134 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 135 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 136 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 137 138 struct ohci_pipe { 139 struct usbd_pipe pipe; 140 ohci_soft_ed_t *sed; 141 ohci_soft_td_t *tail; 142 /* Info needed for different pipe kinds. */ 143 union { 144 /* Control pipe */ 145 struct { 146 usb_dma_t datadma; 147 usb_dma_t reqdma; 148 u_int length; 149 ohci_soft_td_t *setup, *xfer, *stat; 150 } ctl; 151 /* Interrupt pipe */ 152 struct { 153 usb_dma_t datadma; 154 int nslots; 155 int pos; 156 } intr; 157 /* Bulk pipe */ 158 struct { 159 usb_dma_t datadma; 160 u_int length; 161 } bulk; 162 } u; 163 }; 164 165 #define OHCI_INTR_ENDPT 1 166 167 struct usbd_methods ohci_root_ctrl_methods = { 168 ohci_root_ctrl_transfer, 169 ohci_root_ctrl_abort, 170 ohci_root_ctrl_close, 171 }; 172 173 struct usbd_methods ohci_root_intr_methods = { 174 ohci_root_intr_transfer, 175 ohci_root_intr_abort, 176 ohci_root_intr_close, 177 }; 178 179 struct usbd_methods ohci_device_ctrl_methods = { 180 ohci_device_ctrl_transfer, 181 ohci_device_ctrl_abort, 182 ohci_device_ctrl_close, 183 }; 184 185 struct usbd_methods ohci_device_intr_methods = { 186 ohci_device_intr_transfer, 187 ohci_device_intr_abort, 188 ohci_device_intr_close, 189 }; 190 191 struct usbd_methods ohci_device_bulk_methods = { 192 ohci_device_bulk_transfer, 193 ohci_device_bulk_abort, 194 ohci_device_bulk_close, 195 }; 196 197 ohci_soft_ed_t * 198 ohci_alloc_sed(sc) 199 ohci_softc_t *sc; 200 { 201 ohci_soft_ed_t *sed; 202 usbd_status r; 203 int i, offs; 204 usb_dma_t dma; 205 206 if (!sc->sc_freeeds) { 207 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n")); 208 sed = malloc(sizeof(ohci_soft_ed_t) * OHCI_ED_CHUNK, 209 M_USBDEV, M_NOWAIT); 210 if (!sed) 211 return 0; 212 r = usb_allocmem(sc->sc_dmatag, OHCI_ED_SIZE * OHCI_ED_CHUNK, 213 OHCI_ED_ALIGN, &dma); 214 if (r != USBD_NORMAL_COMPLETION) { 215 free(sed, M_USBDEV); 216 return 0; 217 } 218 for(i = 0; i < OHCI_ED_CHUNK; i++, sed++) { 219 offs = i * OHCI_ED_SIZE; 220 sed->physaddr = DMAADDR(&dma) + offs; 221 sed->ed = (ohci_ed_t *) 222 ((char *)KERNADDR(&dma) + offs); 223 sed->next = sc->sc_freeeds; 224 sc->sc_freeeds = sed; 225 } 226 } 227 sed = sc->sc_freeeds; 228 sc->sc_freeeds = sed->next; 229 memset(sed->ed, 0, OHCI_ED_SIZE); 230 sed->next = 0; 231 return sed; 232 } 233 234 void 235 ohci_free_sed(sc, sed) 236 ohci_softc_t *sc; 237 ohci_soft_ed_t *sed; 238 { 239 sed->next = sc->sc_freeeds; 240 sc->sc_freeeds = sed; 241 } 242 243 ohci_soft_td_t * 244 ohci_alloc_std(sc) 245 ohci_softc_t *sc; 246 { 247 ohci_soft_td_t *std; 248 usbd_status r; 249 int i, offs; 250 usb_dma_t dma; 251 252 if (!sc->sc_freetds) { 253 DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n")); 254 std = malloc(sizeof(ohci_soft_td_t) * OHCI_TD_CHUNK, 255 M_USBDEV, M_NOWAIT); 256 if (!std) 257 return 0; 258 r = usb_allocmem(sc->sc_dmatag, OHCI_TD_SIZE * OHCI_TD_CHUNK, 259 OHCI_TD_ALIGN, &dma); 260 if (r != USBD_NORMAL_COMPLETION) { 261 free(std, M_USBDEV); 262 return 0; 263 } 264 for(i = 0; i < OHCI_TD_CHUNK; i++, std++) { 265 offs = i * OHCI_TD_SIZE; 266 std->physaddr = DMAADDR(&dma) + offs; 267 std->td = (ohci_td_t *) 268 ((char *)KERNADDR(&dma) + offs); 269 std->nexttd = sc->sc_freetds; 270 sc->sc_freetds = std; 271 } 272 } 273 std = sc->sc_freetds; 274 sc->sc_freetds = std->nexttd; 275 memset(std->td, 0, OHCI_TD_SIZE); 276 std->nexttd = 0; 277 return (std); 278 } 279 280 void 281 ohci_free_std(sc, std) 282 ohci_softc_t *sc; 283 ohci_soft_td_t *std; 284 { 285 std->nexttd = sc->sc_freetds; 286 sc->sc_freetds = std; 287 } 288 289 usbd_status 290 ohci_init(sc) 291 ohci_softc_t *sc; 292 { 293 ohci_soft_ed_t *sed, *psed; 294 usbd_status r; 295 int rev; 296 int i; 297 u_int32_t s, ctl, ival, hcr, fm, per; 298 299 DPRINTF(("ohci_init: start\n")); 300 rev = OREAD4(sc, OHCI_REVISION); 301 printf("%s: OHCI version %d.%d%s\n", sc->sc_bus.bdev.dv_xname, 302 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 303 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 304 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 305 printf("%s: unsupported OHCI revision\n", 306 sc->sc_bus.bdev.dv_xname); 307 return (USBD_INVAL); 308 } 309 310 for (i = 0; i < OHCI_HASH_SIZE; i++) 311 LIST_INIT(&sc->sc_hash_tds[i]); 312 313 /* Allocate the HCCA area. */ 314 r = usb_allocmem(sc->sc_dmatag, OHCI_HCCA_SIZE, 315 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 316 if (r != USBD_NORMAL_COMPLETION) 317 return (r); 318 sc->sc_hcca = (struct ohci_hcca *)KERNADDR(&sc->sc_hccadma); 319 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 320 321 sc->sc_eintrs = OHCI_NORMAL_INTRS; 322 323 sc->sc_ctrl_head = ohci_alloc_sed(sc); 324 if (!sc->sc_ctrl_head) { 325 r = USBD_NOMEM; 326 goto bad1; 327 } 328 sc->sc_ctrl_head->ed->ed_flags |= OHCI_ED_SKIP; 329 sc->sc_bulk_head = ohci_alloc_sed(sc); 330 if (!sc->sc_bulk_head) { 331 r = USBD_NOMEM; 332 goto bad2; 333 } 334 sc->sc_bulk_head->ed->ed_flags |= OHCI_ED_SKIP; 335 336 /* Allocate all the dummy EDs that make up the interrupt tree. */ 337 for (i = 0; i < OHCI_NO_EDS; i++) { 338 sed = ohci_alloc_sed(sc); 339 if (!sed) { 340 while (--i >= 0) 341 ohci_free_sed(sc, sc->sc_eds[i]); 342 r = USBD_NOMEM; 343 goto bad3; 344 } 345 /* All ED fields are set to 0. */ 346 sc->sc_eds[i] = sed; 347 sed->ed->ed_flags |= OHCI_ED_SKIP; 348 if (i != 0) { 349 psed = sc->sc_eds[(i-1) / 2]; 350 sed->next = psed; 351 sed->ed->ed_nexted = psed->physaddr; 352 } 353 } 354 /* 355 * Fill HCCA interrupt table. The bit reversal is to get 356 * the tree set up properly to spread the interrupts. 357 */ 358 for (i = 0; i < OHCI_NO_INTRS; i++) 359 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 360 sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr; 361 362 /* Determine in what context we are running. */ 363 ctl = OREAD4(sc, OHCI_CONTROL); 364 if (ctl & OHCI_IR) { 365 /* SMM active, request change */ 366 DPRINTF(("ohci_init: SMM active, request owner change\n")); 367 s = OREAD4(sc, OHCI_COMMAND_STATUS); 368 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 369 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 370 delay(1000); 371 ctl = OREAD4(sc, OHCI_CONTROL); 372 } 373 if ((ctl & OHCI_IR) == 0) { 374 printf("%s: SMM does not respond, resetting\n", 375 sc->sc_bus.bdev.dv_xname); 376 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 377 goto reset; 378 } 379 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 380 /* BIOS started controller. */ 381 DPRINTF(("ohci_init: BIOS active\n")); 382 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 383 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL); 384 delay(USB_RESUME_DELAY * 1000); 385 } 386 } else { 387 DPRINTF(("ohci_init: cold started\n")); 388 reset: 389 /* Controller was cold started. */ 390 delay(USB_RESET_DELAY * 1000); 391 } 392 393 /* We now own the host controller and the bus has been reset. */ 394 ival = OHCI_GET_IVAL(OREAD4(sc, OHCI_FM_INTERVAL)); 395 396 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 397 /* Nominal time for a reset is 10 us. */ 398 for (i = 0; i < 10; i++) { 399 delay(10); 400 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 401 if (!hcr) 402 break; 403 } 404 if (hcr) { 405 printf("%s: reset timeout\n", sc->sc_bus.bdev.dv_xname); 406 r = USBD_IOERROR; 407 goto bad3; 408 } 409 #ifdef USB_DEBUG 410 thesc = sc; 411 if (ohcidebug > 15) 412 ohci_dumpregs(sc); 413 #endif 414 415 /* The controller is now in suspend state, we have 2ms to finish. */ 416 417 /* Set up HC registers. */ 418 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma)); 419 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 420 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 421 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 422 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 423 ctl = OREAD4(sc, OHCI_CONTROL); 424 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 425 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 426 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL; 427 /* And finally start it! */ 428 OWRITE4(sc, OHCI_CONTROL, ctl); 429 430 /* 431 * The controller is now OPERATIONAL. Set a some final 432 * registers that should be set earlier, but that the 433 * controller ignores when in the SUSPEND state. 434 */ 435 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 436 fm |= OHCI_FSMPS(ival) | ival; 437 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 438 per = OHCI_PERIODIC(ival); /* 90% periodic */ 439 OWRITE4(sc, OHCI_PERIODIC_START, per); 440 441 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 442 443 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 444 printf("%s: %d downstream port%s\n", 445 sc->sc_bus.bdev.dv_xname, sc->sc_noport, 446 sc->sc_noport != 1 ? "s" : ""); 447 448 #ifdef USB_DEBUG 449 if (ohcidebug > 5) 450 ohci_dumpregs(sc); 451 #endif 452 453 /* Set up the bus struct. */ 454 sc->sc_bus.open_pipe = ohci_open; 455 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe); 456 sc->sc_bus.do_poll = ohci_poll; 457 458 return (USBD_NORMAL_COMPLETION); 459 460 bad3: 461 ohci_free_sed(sc, sc->sc_ctrl_head); 462 bad2: 463 ohci_free_sed(sc, sc->sc_bulk_head); 464 bad1: 465 usb_freemem(sc->sc_dmatag, &sc->sc_hccadma); 466 return (r); 467 } 468 469 #ifdef USB_DEBUG 470 void ohcidump(void); 471 void ohcidump(void) { ohci_dumpregs(thesc); } 472 473 void 474 ohci_dumpregs(sc) 475 ohci_softc_t *sc; 476 { 477 printf("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 478 OREAD4(sc, OHCI_REVISION), 479 OREAD4(sc, OHCI_CONTROL), 480 OREAD4(sc, OHCI_COMMAND_STATUS)); 481 printf(" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 482 OREAD4(sc, OHCI_INTERRUPT_STATUS), 483 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 484 OREAD4(sc, OHCI_INTERRUPT_DISABLE)); 485 printf(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 486 OREAD4(sc, OHCI_HCCA), 487 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 488 OREAD4(sc, OHCI_CONTROL_HEAD_ED)); 489 printf(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 490 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 491 OREAD4(sc, OHCI_BULK_HEAD_ED), 492 OREAD4(sc, OHCI_BULK_CURRENT_ED)); 493 printf(" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 494 OREAD4(sc, OHCI_DONE_HEAD), 495 OREAD4(sc, OHCI_FM_INTERVAL), 496 OREAD4(sc, OHCI_FM_REMAINING)); 497 printf(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 498 OREAD4(sc, OHCI_FM_NUMBER), 499 OREAD4(sc, OHCI_PERIODIC_START), 500 OREAD4(sc, OHCI_LS_THRESHOLD)); 501 printf(" desca=0x%08x descb=0x%08x stat=0x%08x\n", 502 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 503 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 504 OREAD4(sc, OHCI_RH_STATUS)); 505 printf(" port1=0x%08x port2=0x%08x\n", 506 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 507 OREAD4(sc, OHCI_RH_PORT_STATUS(2))); 508 printf(" HCCA: frame_number=0x%04x done_head=0x%08x\n", 509 sc->sc_hcca->hcca_frame_number, 510 sc->sc_hcca->hcca_done_head); 511 } 512 #endif 513 514 int 515 ohci_intr(p) 516 void *p; 517 { 518 ohci_softc_t *sc = p; 519 u_int32_t intrs, eintrs; 520 ohci_physaddr_t done; 521 522 done = sc->sc_hcca->hcca_done_head; 523 if (done != 0) { 524 intrs = OHCI_WDH; 525 if (done & OHCI_DONE_INTRS) 526 intrs |= OREAD4(sc, OHCI_INTERRUPT_STATUS); 527 } else 528 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 529 if (!intrs) 530 return (0); 531 intrs &= ~OHCI_MIE; 532 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs); /* Acknowledge */ 533 eintrs = intrs & sc->sc_eintrs; 534 if (!eintrs) 535 return (0); 536 537 sc->sc_intrs++; 538 DPRINTFN(7, ("ohci_intr: sc=%p intrs=%x(%x) eintr=%x\n", 539 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), 540 (u_int)eintrs)); 541 542 if (eintrs & OHCI_SO) { 543 printf("%s: scheduling overrun\n", sc->sc_bus.bdev.dv_xname); 544 /* XXX do what */ 545 intrs &= ~OHCI_SO; 546 } 547 if (eintrs & OHCI_WDH) { 548 ohci_process_done(sc, done &~ OHCI_DONE_INTRS); 549 sc->sc_hcca->hcca_done_head = 0; 550 intrs &= ~OHCI_WDH; 551 } 552 if (eintrs & OHCI_RD) { 553 /* XXX process resume detect */ 554 } 555 if (eintrs & OHCI_UE) { 556 printf("%s: unrecoverable error, controller halted\n", 557 sc->sc_bus.bdev.dv_xname); 558 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 559 /* XXX what else */ 560 } 561 if (eintrs & OHCI_RHSC) { 562 ohci_rhsc(sc, sc->sc_intrreqh); 563 intrs &= ~OHCI_RHSC; 564 565 /* 566 * Disable RHSC interrupt for now, because it will be 567 * on until the port has been reset. 568 */ 569 ohci_rhsc_able(sc, 0); 570 } 571 572 /* Block unprocessed interrupts. XXX */ 573 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, intrs); 574 sc->sc_eintrs &= ~intrs; 575 576 return (1); 577 } 578 579 void 580 ohci_rhsc_able(sc, on) 581 ohci_softc_t *sc; 582 int on; 583 { 584 DPRINTFN(4, ("ohci_rhsc_able: on=%d\n", on)); 585 if (on) { 586 sc->sc_eintrs |= OHCI_RHSC; 587 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 588 } else { 589 sc->sc_eintrs &= ~OHCI_RHSC; 590 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_RHSC); 591 } 592 } 593 594 void 595 ohci_process_done(sc, done) 596 ohci_softc_t *sc; 597 ohci_physaddr_t done; 598 { 599 ohci_soft_td_t *std, *sdone; 600 usbd_request_handle reqh; 601 int len, cc; 602 603 DPRINTFN(10,("ohci_process_done: done=0x%08lx\n", (u_long)done)); 604 605 /* Reverse the done list. */ 606 for (sdone = 0; done; done = std->td->td_nexttd) { 607 std = ohci_hash_find_td(sc, done); 608 std->dnext = sdone; 609 sdone = std; 610 } 611 612 #ifdef USB_DEBUG 613 if (ohcidebug > 10) { 614 printf("ohci_process_done: TD done:\n"); 615 ohci_dump_tds(sdone); 616 } 617 #endif 618 619 for (std = sdone; std; std = std->dnext) { 620 reqh = std->reqh; 621 DPRINTFN(10, ("ohci_process_done: std=%p reqh=%p\n",std,reqh)); 622 cc = OHCI_TD_GET_CC(std->td->td_flags); 623 if (cc == OHCI_CC_NO_ERROR) { 624 if (std->td->td_cbp == 0) 625 len = std->len; 626 else 627 len = std->td->td_be - std->td->td_cbp + 1; 628 reqh->actlen += len; 629 if (reqh->hcpriv == std) { 630 switch (reqh->pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 631 case UE_CONTROL: 632 ohci_ctrl_done(sc, reqh); 633 break; 634 case UE_INTERRUPT: 635 ohci_intr_done(sc, reqh); 636 break; 637 case UE_BULK: 638 ohci_bulk_done(sc, reqh); 639 break; 640 case UE_ISOCHRONOUS: 641 printf("ohci_process_done: ISO done?\n"); 642 break; 643 } 644 /* And finally execute callback. */ 645 reqh->status = USBD_NORMAL_COMPLETION; 646 reqh->xfercb(reqh); 647 } 648 } else { 649 ohci_soft_td_t *p, *n; 650 struct ohci_pipe *opipe = 651 (struct ohci_pipe *)reqh->pipe; 652 DPRINTFN(-1,("ohci_process_done: error cc=%d\n", 653 OHCI_TD_GET_CC(std->td->td_flags))); 654 /* 655 * Endpoint is halted. First unlink all the TDs 656 * belonging to the failed transfer, and then restart 657 * the endpoint. 658 */ 659 for (p = std->nexttd; p->reqh == reqh; p = n) { 660 n = p->nexttd; 661 ohci_hash_rem_td(sc, p); 662 ohci_free_std(sc, p); 663 } 664 opipe->sed->ed->ed_headp = p->physaddr;/* clear halt */ 665 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 666 667 if (cc == OHCI_CC_STALL) 668 reqh->status = USBD_STALLED; 669 else 670 reqh->status = USBD_IOERROR; 671 reqh->xfercb(reqh); 672 } 673 ohci_hash_rem_td(sc, std); 674 ohci_free_std(sc, std); 675 } 676 } 677 678 void 679 ohci_ctrl_done(sc, reqh) 680 ohci_softc_t *sc; 681 usbd_request_handle reqh; 682 { 683 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 684 u_int len = opipe->u.ctl.length; 685 usb_dma_t *dma; 686 687 DPRINTFN(10,("ohci_ctrl_done: reqh=%p\n", reqh)); 688 689 if (!reqh->isreq) { 690 panic("uhci_ctrl_done: not a request\n"); 691 return; 692 } 693 694 if (len != 0) { 695 dma = &opipe->u.ctl.datadma; 696 if (reqh->request.bmRequestType & UT_READ) 697 memcpy(reqh->buffer, KERNADDR(dma), len); 698 usb_freemem(sc->sc_dmatag, dma); 699 } 700 } 701 702 void 703 ohci_intr_done(sc, reqh) 704 ohci_softc_t *sc; 705 usbd_request_handle reqh; 706 { 707 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 708 usb_dma_t *dma; 709 ohci_soft_ed_t *sed = opipe->sed; 710 ohci_soft_td_t *xfer, *tail; 711 712 713 DPRINTFN(10,("ohci_intr_done: reqh=%p, actlen=%d\n", 714 reqh, reqh->actlen)); 715 716 dma = &opipe->u.intr.datadma; 717 memcpy(reqh->buffer, KERNADDR(dma), reqh->actlen); 718 719 if (reqh->pipe->intrreqh == reqh) { 720 xfer = opipe->tail; 721 tail = ohci_alloc_std(sc); /* XXX should reuse TD */ 722 if (!tail) { 723 reqh->status = USBD_NOMEM; 724 return; 725 } 726 tail->reqh = 0; 727 728 xfer->td->td_flags = OHCI_TD_IN | OHCI_TD_NOCC | 729 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY; 730 xfer->td->td_cbp = DMAADDR(dma); 731 xfer->nexttd = tail; 732 xfer->td->td_nexttd = tail->physaddr; 733 xfer->td->td_be = xfer->td->td_cbp + reqh->length - 1; 734 xfer->len = reqh->length; 735 xfer->reqh = reqh; 736 737 reqh->actlen = 0; 738 reqh->hcpriv = xfer; 739 740 ohci_hash_add_td(sc, xfer); 741 sed->ed->ed_tailp = tail->physaddr; 742 opipe->tail = tail; 743 } else { 744 usb_freemem(sc->sc_dmatag, dma); 745 } 746 } 747 748 void 749 ohci_bulk_done(sc, reqh) 750 ohci_softc_t *sc; 751 usbd_request_handle reqh; 752 { 753 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 754 usb_dma_t *dma; 755 756 757 DPRINTFN(10,("ohci_bulk_done: reqh=%p, actlen=%d\n", 758 reqh, reqh->actlen)); 759 760 dma = &opipe->u.bulk.datadma; 761 if (reqh->request.bmRequestType & UT_READ) 762 memcpy(reqh->buffer, KERNADDR(dma), reqh->actlen); 763 usb_freemem(sc->sc_dmatag, dma); 764 } 765 766 void 767 ohci_rhsc(sc, reqh) 768 ohci_softc_t *sc; 769 usbd_request_handle reqh; 770 { 771 usbd_pipe_handle pipe; 772 struct ohci_pipe *opipe; 773 u_char *p; 774 int i, m; 775 int hstatus; 776 777 hstatus = OREAD4(sc, OHCI_RH_STATUS); 778 DPRINTF(("ohci_rhsc: sc=%p reqh=%p hstatus=0x%08x\n", 779 sc, reqh, hstatus)); 780 781 if (reqh == 0) { 782 /* Just ignore the change. */ 783 return; 784 } 785 786 pipe = reqh->pipe; 787 opipe = (struct ohci_pipe *)pipe; 788 789 p = KERNADDR(&opipe->u.intr.datadma); 790 m = min(sc->sc_noport, reqh->length * 8 - 1); 791 memset(p, 0, reqh->length); 792 for (i = 1; i <= m; i++) { 793 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 794 p[i/8] |= 1 << (i%8); 795 } 796 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p)); 797 reqh->actlen = reqh->length; 798 reqh->status = USBD_NORMAL_COMPLETION; 799 reqh->xfercb(reqh); 800 801 if (reqh->pipe->intrreqh != reqh) { 802 sc->sc_intrreqh = 0; 803 usb_freemem(sc->sc_dmatag, &opipe->u.intr.datadma); 804 } 805 } 806 807 /* 808 * Wait here until controller claims to have an interrupt. 809 * Then call ohci_intr and return. Use timeout to avoid waiting 810 * too long. 811 */ 812 void 813 ohci_waitintr(sc, reqh) 814 ohci_softc_t *sc; 815 usbd_request_handle reqh; 816 { 817 int timo = reqh->timeout; 818 int usecs; 819 u_int32_t intrs; 820 821 reqh->status = USBD_IN_PROGRESS; 822 for (usecs = timo * 1000000 / hz; usecs > 0; usecs -= 1000) { 823 delay(1000); 824 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 825 DPRINTFN(10,("ohci_waitintr: 0x%04x\n", intrs)); 826 #ifdef USB_DEBUG 827 if (ohcidebug > 15) 828 ohci_dumpregs(sc); 829 #endif 830 if (intrs) { 831 ohci_intr(sc); 832 if (reqh->status != USBD_IN_PROGRESS) 833 return; 834 } 835 } 836 DPRINTF(("ohci_waitintr: timeout\n")); 837 reqh->status = USBD_TIMEOUT; 838 reqh->xfercb(reqh); 839 } 840 841 void 842 ohci_poll(bus) 843 struct usbd_bus *bus; 844 { 845 ohci_softc_t *sc = (ohci_softc_t *)bus; 846 847 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) 848 ohci_intr(sc); 849 } 850 851 usbd_status 852 ohci_device_request(reqh) 853 usbd_request_handle reqh; 854 { 855 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 856 usb_device_request_t *req = &reqh->request; 857 usbd_device_handle dev = opipe->pipe.device; 858 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 859 int addr = dev->address; 860 ohci_soft_td_t *setup, *xfer = 0, *stat, *next, *tail; 861 ohci_soft_ed_t *sed; 862 usb_dma_t *dmap; 863 int isread; 864 int len; 865 usbd_status r; 866 int s; 867 868 isread = req->bmRequestType & UT_READ; 869 len = UGETW(req->wLength); 870 871 DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 872 req->bmRequestType, req->bRequest, UGETW(req->wValue), 873 UGETW(req->wIndex), len, addr, 874 opipe->pipe.endpoint->edesc->bEndpointAddress)); 875 876 setup = opipe->tail; 877 stat = ohci_alloc_std(sc); 878 if (!stat) { 879 r = USBD_NOMEM; 880 goto bad1; 881 } 882 tail = ohci_alloc_std(sc); 883 if (!tail) { 884 r = USBD_NOMEM; 885 goto bad2; 886 } 887 tail->reqh = 0; 888 889 sed = opipe->sed; 890 dmap = &opipe->u.ctl.datadma; 891 opipe->u.ctl.length = len; 892 893 /* Update device address */ 894 sed->ed->ed_flags = 895 (sed->ed->ed_flags & ~OHCI_ED_ADDRMASK) | 896 OHCI_ED_SET_FA(addr); 897 898 /* Set up data transaction */ 899 if (len != 0) { 900 xfer = ohci_alloc_std(sc); 901 if (!xfer) { 902 r = USBD_NOMEM; 903 goto bad3; 904 } 905 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap); 906 if (r != USBD_NORMAL_COMPLETION) 907 goto bad4; 908 xfer->td->td_flags = 909 (isread ? OHCI_TD_IN : OHCI_TD_OUT) | OHCI_TD_NOCC | 910 OHCI_TD_TOGGLE_1 | OHCI_TD_NOINTR; 911 xfer->td->td_cbp = DMAADDR(dmap); 912 xfer->nexttd = stat; 913 xfer->td->td_nexttd = stat->physaddr; 914 xfer->td->td_be = xfer->td->td_cbp + len - 1; 915 xfer->len = len; 916 xfer->reqh = reqh; 917 918 next = xfer; 919 } else 920 next = stat; 921 922 memcpy(KERNADDR(&opipe->u.ctl.reqdma), req, sizeof *req); 923 if (!isread && len != 0) 924 memcpy(KERNADDR(dmap), reqh->buffer, len); 925 926 setup->td->td_flags = OHCI_TD_SETUP | OHCI_TD_NOCC | 927 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR; 928 setup->td->td_cbp = DMAADDR(&opipe->u.ctl.reqdma); 929 setup->nexttd = next; 930 setup->td->td_nexttd = next->physaddr; 931 setup->td->td_be = setup->td->td_cbp + sizeof *req - 1; 932 setup->len = 0; /* XXX The number of byte we count */ 933 setup->reqh = reqh; 934 935 stat->td->td_flags = 936 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | OHCI_TD_NOCC | 937 OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1); 938 stat->td->td_cbp = 0; 939 stat->nexttd = tail; 940 stat->td->td_nexttd = tail->physaddr; 941 stat->td->td_be = 0; 942 stat->len = 0; 943 stat->reqh = reqh; 944 945 reqh->actlen = 0; 946 reqh->hcpriv = stat; 947 948 #if USB_DEBUG 949 if (ohcidebug > 5) { 950 printf("ohci_device_request:\n"); 951 ohci_dump_ed(sed); 952 ohci_dump_tds(setup); 953 } 954 #endif 955 956 /* Insert ED in schedule */ 957 s = splusb(); 958 ohci_hash_add_td(sc, setup); 959 if (len != 0) 960 ohci_hash_add_td(sc, xfer); 961 ohci_hash_add_td(sc, stat); 962 sed->ed->ed_tailp = tail->physaddr; 963 opipe->tail = tail; 964 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 965 if (reqh->timeout && !usbd_use_polling) 966 timeout(ohci_timeout, reqh, MS_TO_TICKS(reqh->timeout)); 967 splx(s); 968 969 #if USB_DEBUG 970 if (ohcidebug > 5) { 971 delay(5000); 972 printf("ohci_device_request: status=%x\n", 973 OREAD4(sc, OHCI_COMMAND_STATUS)); 974 ohci_dump_ed(sed); 975 ohci_dump_tds(setup); 976 } 977 #endif 978 979 return (USBD_NORMAL_COMPLETION); 980 981 bad4: 982 ohci_free_std(sc, xfer); 983 bad3: 984 ohci_free_std(sc, tail); 985 bad2: 986 ohci_free_std(sc, stat); 987 bad1: 988 return (r); 989 } 990 991 /* 992 * Add an ED to the schedule. Called at splusb(). 993 */ 994 void 995 ohci_add_ed(sed, head) 996 ohci_soft_ed_t *sed; 997 ohci_soft_ed_t *head; 998 { 999 sed->next = head->next; 1000 sed->ed->ed_nexted = head->ed->ed_nexted; 1001 head->next = sed; 1002 head->ed->ed_nexted = sed->physaddr; 1003 } 1004 1005 /* 1006 * Remove an ED from the schedule. Called at splusb(). 1007 */ 1008 void 1009 ohci_rem_ed(sed, head) 1010 ohci_soft_ed_t *sed; 1011 ohci_soft_ed_t *head; 1012 { 1013 ohci_soft_ed_t *p; 1014 1015 /* XXX */ 1016 for (p = head; p && p->next != sed; p = p->next) 1017 ; 1018 if (!p) 1019 panic("ohci_rem_ed: ED not found\n"); 1020 p->next = sed->next; 1021 p->ed->ed_nexted = sed->ed->ed_nexted; 1022 } 1023 1024 /* 1025 * When a transfer is completed the TD is added to the done queue by 1026 * the host controller. This queue is the processed by software. 1027 * Unfortunately the queue contains the physical address of the TD 1028 * and we have no simple way to translate this back a kernel address. 1029 * To make the translation possible (and fast) we use a hash table of 1030 * TDs currently in the schedule. The physical address is used as the 1031 * hash value. 1032 */ 1033 1034 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1035 /* Called at splusb() */ 1036 void 1037 ohci_hash_add_td(sc, std) 1038 ohci_softc_t *sc; 1039 ohci_soft_td_t *std; 1040 { 1041 int h = HASH(std->physaddr); 1042 1043 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1044 } 1045 1046 /* Called at splusb() */ 1047 void 1048 ohci_hash_rem_td(sc, std) 1049 ohci_softc_t *sc; 1050 ohci_soft_td_t *std; 1051 { 1052 LIST_REMOVE(std, hnext); 1053 } 1054 1055 ohci_soft_td_t * 1056 ohci_hash_find_td(sc, a) 1057 ohci_softc_t *sc; 1058 ohci_physaddr_t a; 1059 { 1060 int h = HASH(a); 1061 ohci_soft_td_t *std; 1062 1063 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1064 std != 0; 1065 std = LIST_NEXT(std, hnext)) 1066 if (std->physaddr == a) 1067 return (std); 1068 panic("ohci_hash_find_td: addr 0x%08lx not found\n", (u_long)a); 1069 } 1070 1071 void 1072 ohci_timeout(addr) 1073 void *addr; 1074 { 1075 #if 0 1076 usbd_request_handle *reqh = addr; 1077 int s; 1078 1079 DPRINTF(("ohci_timeout: reqh=%p\n", reqh)); 1080 s = splusb(); 1081 /* XXX need to inactivate TD before calling interrupt routine */ 1082 ohci_XXX_done(reqh); 1083 splx(s); 1084 #endif 1085 } 1086 1087 #ifdef USB_DEBUG 1088 void 1089 ohci_dump_tds(std) 1090 ohci_soft_td_t *std; 1091 { 1092 for (; std; std = std->nexttd) 1093 ohci_dump_td(std); 1094 } 1095 1096 void 1097 ohci_dump_td(std) 1098 ohci_soft_td_t *std; 1099 { 1100 printf("TD(%p) at %08lx: %b delay=%d ec=%d cc=%d\ncbp=0x%08lx nexttd=0x%08lx be=0x%08lx\n", 1101 std, (u_long)std->physaddr, 1102 (u_long)std->td->td_flags, 1103 "\20\23R\24OUT\25IN\31TOG1\32SETTOGGLE", 1104 OHCI_TD_GET_DI(std->td->td_flags), 1105 OHCI_TD_GET_EC(std->td->td_flags), 1106 OHCI_TD_GET_CC(std->td->td_flags), 1107 (u_long)std->td->td_cbp, 1108 (u_long)std->td->td_nexttd, (u_long)std->td->td_be); 1109 } 1110 1111 void 1112 ohci_dump_ed(sed) 1113 ohci_soft_ed_t *sed; 1114 { 1115 printf("ED(%p) at %08lx: addr=%d endpt=%d maxp=%d %b\ntailp=0x%08lx headp=%b nexted=0x%08lx\n", 1116 sed, (u_long)sed->physaddr, 1117 OHCI_ED_GET_FA(sed->ed->ed_flags), 1118 OHCI_ED_GET_EN(sed->ed->ed_flags), 1119 OHCI_ED_GET_MAXP(sed->ed->ed_flags), 1120 (u_long)sed->ed->ed_flags, 1121 "\20\14OUT\15IN\16LOWSPEED\17SKIP\18ISO", 1122 (u_long)sed->ed->ed_tailp, 1123 (u_long)sed->ed->ed_headp, "\20\1HALT\2CARRY", 1124 (u_long)sed->ed->ed_nexted); 1125 } 1126 #endif 1127 1128 usbd_status 1129 ohci_open(pipe) 1130 usbd_pipe_handle pipe; 1131 { 1132 usbd_device_handle dev = pipe->device; 1133 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 1134 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1135 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 1136 u_int8_t addr = dev->address; 1137 ohci_soft_ed_t *sed; 1138 ohci_soft_td_t *std; 1139 usbd_status r; 1140 int s; 1141 1142 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1143 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1144 if (addr == sc->sc_addr) { 1145 switch (ed->bEndpointAddress) { 1146 case USB_CONTROL_ENDPOINT: 1147 pipe->methods = &ohci_root_ctrl_methods; 1148 break; 1149 case UE_IN | OHCI_INTR_ENDPT: 1150 pipe->methods = &ohci_root_intr_methods; 1151 break; 1152 default: 1153 return (USBD_INVAL); 1154 } 1155 } else { 1156 sed = ohci_alloc_sed(sc); 1157 if (sed == 0) 1158 goto bad0; 1159 std = ohci_alloc_std(sc); 1160 if (std == 0) 1161 goto bad1; 1162 opipe->sed = sed; 1163 opipe->tail = std; 1164 sed->ed->ed_flags = 1165 OHCI_ED_SET_FA(addr) | 1166 OHCI_ED_SET_EN(ed->bEndpointAddress) | 1167 OHCI_ED_DIR_TD | 1168 (dev->lowspeed ? OHCI_ED_SPEED : 0) | 1169 ((ed->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS ? 1170 OHCI_ED_FORMAT_ISO : OHCI_ED_FORMAT_GEN) | 1171 OHCI_ED_SET_MAXP(UGETW(pipe->endpoint->edesc->wMaxPacketSize)); 1172 sed->ed->ed_headp = sed->ed->ed_tailp = std->physaddr; 1173 1174 switch (ed->bmAttributes & UE_XFERTYPE) { 1175 case UE_CONTROL: 1176 pipe->methods = &ohci_device_ctrl_methods; 1177 r = usb_allocmem(sc->sc_dmatag, 1178 sizeof(usb_device_request_t), 1179 0, &opipe->u.ctl.reqdma); 1180 if (r != USBD_NORMAL_COMPLETION) 1181 goto bad; 1182 s = splusb(); 1183 ohci_add_ed(sed, sc->sc_ctrl_head); 1184 splx(s); 1185 break; 1186 case UE_INTERRUPT: 1187 pipe->methods = &ohci_device_intr_methods; 1188 return (ohci_device_setintr(sc, opipe, ed->bInterval)); 1189 case UE_ISOCHRONOUS: 1190 printf("ohci_open: open iso unimplemented\n"); 1191 return (USBD_XXX); 1192 case UE_BULK: 1193 pipe->methods = &ohci_device_bulk_methods; 1194 s = splusb(); 1195 ohci_add_ed(sed, sc->sc_bulk_head); 1196 splx(s); 1197 break; 1198 } 1199 } 1200 return (USBD_NORMAL_COMPLETION); 1201 1202 bad: 1203 ohci_free_std(sc, std); 1204 bad1: 1205 ohci_free_sed(sc, sed); 1206 bad0: 1207 return (USBD_NOMEM); 1208 1209 } 1210 1211 /* 1212 * Data structures and routines to emulate the root hub. 1213 */ 1214 usb_device_descriptor_t ohci_devd = { 1215 USB_DEVICE_DESCRIPTOR_SIZE, 1216 UDESC_DEVICE, /* type */ 1217 {0x00, 0x01}, /* USB version */ 1218 UCLASS_HUB, /* class */ 1219 USUBCLASS_HUB, /* subclass */ 1220 0, /* protocol */ 1221 64, /* max packet */ 1222 {0},{0},{0x00,0x01}, /* device id */ 1223 1,2,0, /* string indicies */ 1224 1 /* # of configurations */ 1225 }; 1226 1227 usb_config_descriptor_t ohci_confd = { 1228 USB_CONFIG_DESCRIPTOR_SIZE, 1229 UDESC_CONFIG, 1230 {USB_CONFIG_DESCRIPTOR_SIZE + 1231 USB_INTERFACE_DESCRIPTOR_SIZE + 1232 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1233 1, 1234 1, 1235 0, 1236 UC_SELF_POWERED, 1237 0 /* max power */ 1238 }; 1239 1240 usb_interface_descriptor_t ohci_ifcd = { 1241 USB_INTERFACE_DESCRIPTOR_SIZE, 1242 UDESC_INTERFACE, 1243 0, 1244 0, 1245 1, 1246 UCLASS_HUB, 1247 USUBCLASS_HUB, 1248 0, 1249 0 1250 }; 1251 1252 usb_endpoint_descriptor_t ohci_endpd = { 1253 USB_ENDPOINT_DESCRIPTOR_SIZE, 1254 UDESC_ENDPOINT, 1255 UE_IN | OHCI_INTR_ENDPT, 1256 UE_INTERRUPT, 1257 {8, 0}, /* max packet */ 1258 255 1259 }; 1260 1261 usb_hub_descriptor_t ohci_hubd = { 1262 USB_HUB_DESCRIPTOR_SIZE, 1263 UDESC_HUB, 1264 0, 1265 {0,0}, 1266 0, 1267 0, 1268 {0}, 1269 {0}, 1270 }; 1271 1272 int 1273 ohci_str(p, l, s) 1274 usb_string_descriptor_t *p; 1275 int l; 1276 char *s; 1277 { 1278 int i; 1279 1280 if (l == 0) 1281 return (0); 1282 p->bLength = 2 * strlen(s) + 2; 1283 if (l == 1) 1284 return (1); 1285 p->bDescriptorType = UDESC_STRING; 1286 l -= 2; 1287 for (i = 0; s[i] && l > 1; i++, l -= 2) 1288 USETW2(p->bString[i], 0, s[i]); 1289 return (2*i+2); 1290 } 1291 1292 /* 1293 * Simulate a hardware hub by handling all the necessary requests. 1294 */ 1295 usbd_status 1296 ohci_root_ctrl_transfer(reqh) 1297 usbd_request_handle reqh; 1298 { 1299 ohci_softc_t *sc = (ohci_softc_t *)reqh->pipe->device->bus; 1300 usb_device_request_t *req; 1301 void *buf; 1302 int port, i; 1303 int len, value, index, l, totlen = 0; 1304 usb_port_status_t ps; 1305 usb_hub_descriptor_t hubd; 1306 usbd_status r; 1307 u_int32_t v; 1308 1309 if (!reqh->isreq) 1310 /* XXX panic */ 1311 return (USBD_INVAL); 1312 req = &reqh->request; 1313 buf = reqh->buffer; 1314 1315 DPRINTFN(4,("ohci_root_ctrl_control type=0x%02x request=%02x\n", 1316 req->bmRequestType, req->bRequest)); 1317 1318 len = UGETW(req->wLength); 1319 value = UGETW(req->wValue); 1320 index = UGETW(req->wIndex); 1321 #define C(x,y) ((x) | ((y) << 8)) 1322 switch(C(req->bRequest, req->bmRequestType)) { 1323 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 1324 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 1325 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 1326 /* 1327 * DEVICE_REMOTE_WAKEUP and ENDPOINT_STALL are no-ops 1328 * for the integrated root hub. 1329 */ 1330 break; 1331 case C(UR_GET_CONFIG, UT_READ_DEVICE): 1332 if (len > 0) { 1333 *(u_int8_t *)buf = sc->sc_conf; 1334 totlen = 1; 1335 } 1336 break; 1337 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 1338 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value)); 1339 switch(value >> 8) { 1340 case UDESC_DEVICE: 1341 if ((value & 0xff) != 0) { 1342 r = USBD_IOERROR; 1343 goto ret; 1344 } 1345 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1346 memcpy(buf, &ohci_devd, l); 1347 break; 1348 case UDESC_CONFIG: 1349 if ((value & 0xff) != 0) { 1350 r = USBD_IOERROR; 1351 goto ret; 1352 } 1353 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 1354 memcpy(buf, &ohci_confd, l); 1355 buf = (char *)buf + l; 1356 len -= l; 1357 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 1358 totlen += l; 1359 memcpy(buf, &ohci_ifcd, l); 1360 buf = (char *)buf + l; 1361 len -= l; 1362 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 1363 totlen += l; 1364 memcpy(buf, &ohci_endpd, l); 1365 break; 1366 case UDESC_STRING: 1367 if (len == 0) 1368 break; 1369 *(u_int8_t *)buf = 0; 1370 totlen = 1; 1371 switch (value & 0xff) { 1372 case 1: /* Vendor */ 1373 totlen = ohci_str(buf, len, sc->sc_vendor); 1374 break; 1375 case 2: /* Product */ 1376 totlen = ohci_str(buf, len, "OHCI root hub"); 1377 break; 1378 } 1379 break; 1380 default: 1381 r = USBD_IOERROR; 1382 goto ret; 1383 } 1384 break; 1385 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 1386 if (len > 0) { 1387 *(u_int8_t *)buf = 0; 1388 totlen = 1; 1389 } 1390 break; 1391 case C(UR_GET_STATUS, UT_READ_DEVICE): 1392 if (len > 1) { 1393 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 1394 totlen = 2; 1395 } 1396 break; 1397 case C(UR_GET_STATUS, UT_READ_INTERFACE): 1398 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 1399 if (len > 1) { 1400 USETW(((usb_status_t *)buf)->wStatus, 0); 1401 totlen = 2; 1402 } 1403 break; 1404 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 1405 if (value >= USB_MAX_DEVICES) { 1406 r = USBD_IOERROR; 1407 goto ret; 1408 } 1409 sc->sc_addr = value; 1410 break; 1411 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 1412 if (value != 0 && value != 1) { 1413 r = USBD_IOERROR; 1414 goto ret; 1415 } 1416 sc->sc_conf = value; 1417 break; 1418 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 1419 break; 1420 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 1421 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 1422 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 1423 r = USBD_IOERROR; 1424 goto ret; 1425 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 1426 break; 1427 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 1428 break; 1429 /* Hub requests */ 1430 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 1431 break; 1432 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 1433 DPRINTFN(8, ("ohci_root_ctrl_control: UR_CLEAR_PORT_FEATURE port=%d feature=%d\n", 1434 index, value)); 1435 if (index < 1 || index > sc->sc_noport) { 1436 r = USBD_IOERROR; 1437 goto ret; 1438 } 1439 port = OHCI_RH_PORT_STATUS(index); 1440 switch(value) { 1441 case UHF_PORT_ENABLE: 1442 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 1443 break; 1444 case UHF_PORT_SUSPEND: 1445 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 1446 break; 1447 case UHF_PORT_POWER: 1448 OWRITE4(sc, port, UPS_LOW_SPEED); 1449 break; 1450 case UHF_C_PORT_CONNECTION: 1451 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 1452 break; 1453 case UHF_C_PORT_ENABLE: 1454 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 1455 break; 1456 case UHF_C_PORT_SUSPEND: 1457 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 1458 break; 1459 case UHF_C_PORT_OVER_CURRENT: 1460 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 1461 break; 1462 case UHF_C_PORT_RESET: 1463 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 1464 break; 1465 default: 1466 r = USBD_IOERROR; 1467 goto ret; 1468 } 1469 switch(value) { 1470 case UHF_C_PORT_CONNECTION: 1471 case UHF_C_PORT_ENABLE: 1472 case UHF_C_PORT_SUSPEND: 1473 case UHF_C_PORT_OVER_CURRENT: 1474 case UHF_C_PORT_RESET: 1475 /* Enable RHSC interrupt if condition is cleared. */ 1476 if ((OREAD4(sc, port) >> 16) == 0) 1477 ohci_rhsc_able(sc, 1); 1478 break; 1479 default: 1480 break; 1481 } 1482 break; 1483 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 1484 if (value != 0) { 1485 r = USBD_IOERROR; 1486 goto ret; 1487 } 1488 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 1489 hubd = ohci_hubd; 1490 hubd.bNbrPorts = sc->sc_noport; 1491 USETW(hubd.bHubCharacteristics, 1492 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 1493 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 1494 /* XXX overcurrent */ 1495 ); 1496 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 1497 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 1498 if (sc->sc_noport < 8) { 1499 hubd.DeviceRemovable[0] = (u_int8_t)v; 1500 hubd.PortPowerCtrlMask[0] = (u_int8_t)(v >> 16); 1501 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE; 1502 } else { 1503 hubd.DeviceRemovable[0] = (u_int8_t)v; 1504 hubd.DeviceRemovable[1] = (u_int8_t)(v>>8); 1505 hubd.PortPowerCtrlMask[1] = (u_int8_t)(v >> 16); 1506 hubd.PortPowerCtrlMask[2] = (u_int8_t)(v >> 24); 1507 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + 2; 1508 } 1509 l = min(len, hubd.bDescLength); 1510 totlen = l; 1511 memcpy(buf, &hubd, l); 1512 break; 1513 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 1514 if (len != 4) { 1515 r = USBD_IOERROR; 1516 goto ret; 1517 } 1518 memset(buf, 0, len); /* ? XXX */ 1519 totlen = len; 1520 break; 1521 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 1522 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n", 1523 index)); 1524 if (index < 1 || index > sc->sc_noport) { 1525 r = USBD_IOERROR; 1526 goto ret; 1527 } 1528 if (len != 4) { 1529 r = USBD_IOERROR; 1530 goto ret; 1531 } 1532 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 1533 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n", 1534 v)); 1535 USETW(ps.wPortStatus, v); 1536 USETW(ps.wPortChange, v >> 16); 1537 l = min(len, sizeof ps); 1538 memcpy(buf, &ps, l); 1539 totlen = l; 1540 break; 1541 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 1542 r = USBD_IOERROR; 1543 goto ret; 1544 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 1545 break; 1546 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 1547 if (index < 1 || index > sc->sc_noport) { 1548 r = USBD_IOERROR; 1549 goto ret; 1550 } 1551 port = OHCI_RH_PORT_STATUS(index); 1552 switch(value) { 1553 case UHF_PORT_ENABLE: 1554 OWRITE4(sc, port, UPS_PORT_ENABLED); 1555 break; 1556 case UHF_PORT_SUSPEND: 1557 OWRITE4(sc, port, UPS_SUSPEND); 1558 break; 1559 case UHF_PORT_RESET: 1560 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n", index)); 1561 OWRITE4(sc, port, UPS_RESET); 1562 for (i = 0; i < 10; i++) { 1563 usbd_delay_ms(10); 1564 if ((OREAD4(sc, port) & UPS_RESET) == 0) 1565 break; 1566 } 1567 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n", 1568 index, OREAD4(sc, port))); 1569 break; 1570 case UHF_PORT_POWER: 1571 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power %d\n", index)); 1572 OWRITE4(sc, port, UPS_PORT_POWER); 1573 break; 1574 default: 1575 r = USBD_IOERROR; 1576 goto ret; 1577 } 1578 break; 1579 default: 1580 r = USBD_IOERROR; 1581 goto ret; 1582 } 1583 reqh->actlen = totlen; 1584 r = USBD_NORMAL_COMPLETION; 1585 ret: 1586 reqh->status = r; 1587 reqh->xfercb(reqh); 1588 return (USBD_IN_PROGRESS); 1589 } 1590 1591 /* Abort a root control request. */ 1592 void 1593 ohci_root_ctrl_abort(reqh) 1594 usbd_request_handle reqh; 1595 { 1596 /* Nothing to do, all transfers are syncronous. */ 1597 } 1598 1599 /* Close the root pipe. */ 1600 void 1601 ohci_root_ctrl_close(pipe) 1602 usbd_pipe_handle pipe; 1603 { 1604 DPRINTF(("ohci_root_ctrl_close\n")); 1605 } 1606 1607 usbd_status 1608 ohci_root_intr_transfer(reqh) 1609 usbd_request_handle reqh; 1610 { 1611 usbd_pipe_handle pipe = reqh->pipe; 1612 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 1613 struct ohci_pipe *upipe = (struct ohci_pipe *)pipe; 1614 usb_dma_t *dmap; 1615 usbd_status r; 1616 int len; 1617 1618 len = reqh->length; 1619 dmap = &upipe->u.intr.datadma; 1620 if (len == 0) 1621 return (USBD_INVAL); /* XXX should it be? */ 1622 1623 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap); 1624 if (r != USBD_NORMAL_COMPLETION) 1625 return (r); 1626 sc->sc_intrreqh = reqh; 1627 1628 return (USBD_IN_PROGRESS); 1629 } 1630 1631 /* Abort a root interrupt request. */ 1632 void 1633 ohci_root_intr_abort(reqh) 1634 usbd_request_handle reqh; 1635 { 1636 /* No need to abort. */ 1637 } 1638 1639 /* Close the root pipe. */ 1640 void 1641 ohci_root_intr_close(pipe) 1642 usbd_pipe_handle pipe; 1643 { 1644 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 1645 sc->sc_intrreqh = 0; 1646 1647 DPRINTF(("ohci_root_intr_close\n")); 1648 } 1649 1650 /************************/ 1651 1652 usbd_status 1653 ohci_device_ctrl_transfer(reqh) 1654 usbd_request_handle reqh; 1655 { 1656 usbd_status r; 1657 1658 if (!reqh->isreq) { 1659 /* XXX panic */ 1660 printf("ohci_device_ctrl_transfer: not a request\n"); 1661 return (USBD_INVAL); 1662 } 1663 1664 r = ohci_device_request(reqh); 1665 if (r != USBD_NORMAL_COMPLETION) 1666 return (r); 1667 1668 if (usbd_use_polling) 1669 ohci_waitintr((ohci_softc_t *)reqh->pipe->device->bus, reqh); 1670 return (USBD_IN_PROGRESS); 1671 } 1672 1673 /* Abort a device control request. */ 1674 void 1675 ohci_device_ctrl_abort(reqh) 1676 usbd_request_handle reqh; 1677 { 1678 /* XXX inactivate */ 1679 usbd_delay_ms(1); /* make sure it is finished */ 1680 /* XXX call done */ 1681 } 1682 1683 /* Close a device control pipe. */ 1684 void 1685 ohci_device_ctrl_close(pipe) 1686 usbd_pipe_handle pipe; 1687 { 1688 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 1689 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 1690 ohci_soft_ed_t *sed = opipe->sed; 1691 int s; 1692 1693 s = splusb(); 1694 sed->ed->ed_flags |= OHCI_ED_SKIP; 1695 if ((sed->ed->ed_tailp & OHCI_TAILMASK) != sed->ed->ed_headp) 1696 usbd_delay_ms(2); 1697 ohci_rem_ed(sed, sc->sc_ctrl_head); 1698 splx(s); 1699 ohci_free_std(sc, opipe->tail); 1700 ohci_free_sed(sc, opipe->sed); 1701 /* XXX free other resources */ 1702 } 1703 1704 /************************/ 1705 1706 usbd_status 1707 ohci_device_bulk_transfer(reqh) 1708 usbd_request_handle reqh; 1709 { 1710 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 1711 usbd_device_handle dev = opipe->pipe.device; 1712 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 1713 int addr = dev->address; 1714 ohci_soft_td_t *xfer, *tail; 1715 ohci_soft_ed_t *sed; 1716 usb_dma_t *dmap; 1717 usbd_status r; 1718 int s, len, isread; 1719 1720 if (reqh->isreq) { 1721 /* XXX panic */ 1722 printf("ohci_device_bulk_transfer: a request\n"); 1723 return (USBD_INVAL); 1724 } 1725 1726 len = reqh->length; 1727 dmap = &opipe->u.bulk.datadma; 1728 isread = reqh->pipe->endpoint->edesc->bEndpointAddress & UE_IN; 1729 sed = opipe->sed; 1730 1731 opipe->u.bulk.length = len; 1732 1733 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap); 1734 if (r != USBD_NORMAL_COMPLETION) 1735 goto ret1; 1736 1737 tail = ohci_alloc_std(sc); 1738 if (!tail) { 1739 r = USBD_NOMEM; 1740 goto ret2; 1741 } 1742 tail->reqh = 0; 1743 1744 /* Update device address */ 1745 sed->ed->ed_flags = 1746 (sed->ed->ed_flags & ~OHCI_ED_ADDRMASK) | 1747 OHCI_ED_SET_FA(addr); 1748 1749 /* Set up data transaction */ 1750 xfer = opipe->tail; 1751 xfer->td->td_flags = 1752 (isread ? OHCI_TD_IN : OHCI_TD_OUT) | OHCI_TD_NOCC | 1753 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY; 1754 xfer->td->td_cbp = DMAADDR(dmap); 1755 xfer->nexttd = tail; 1756 xfer->td->td_nexttd = tail->physaddr; 1757 xfer->td->td_be = xfer->td->td_cbp + len - 1; 1758 xfer->len = len; 1759 xfer->reqh = reqh; 1760 1761 reqh->actlen = 0; 1762 reqh->hcpriv = xfer; 1763 1764 if (!isread) 1765 memcpy(KERNADDR(dmap), reqh->buffer, len); 1766 1767 /* Insert ED in schedule */ 1768 s = splusb(); 1769 ohci_hash_add_td(sc, xfer); 1770 sed->ed->ed_tailp = tail->physaddr; 1771 opipe->tail = tail; 1772 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 1773 if (reqh->timeout && !usbd_use_polling) 1774 timeout(ohci_timeout, reqh, MS_TO_TICKS(reqh->timeout)); 1775 splx(s); 1776 1777 return (USBD_IN_PROGRESS); 1778 1779 ret2: 1780 usb_freemem(sc->sc_dmatag, dmap); 1781 ret1: 1782 return (r); 1783 } 1784 1785 /* Abort a device bulk request. */ 1786 void 1787 ohci_device_bulk_abort(reqh) 1788 usbd_request_handle reqh; 1789 { 1790 #if 0 1791 sed->ed->ed_flags |= OHCI_ED_SKIP; 1792 if ((sed->ed->ed_tailp & OHCI_TAILMASK) != sed->ed->ed_headp) 1793 usbd_delay_ms(2); 1794 #endif 1795 /* XXX inactivate */ 1796 usbd_delay_ms(1); /* make sure it is finished */ 1797 /* XXX call done */ 1798 } 1799 1800 /* Close a device bulk pipe. */ 1801 void 1802 ohci_device_bulk_close(pipe) 1803 usbd_pipe_handle pipe; 1804 { 1805 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 1806 usbd_device_handle dev = opipe->pipe.device; 1807 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 1808 int s; 1809 1810 s = splusb(); 1811 ohci_rem_ed(opipe->sed, sc->sc_bulk_head); 1812 splx(s); 1813 ohci_free_std(sc, opipe->tail); 1814 ohci_free_sed(sc, opipe->sed); 1815 /* XXX free other resources */ 1816 } 1817 1818 /************************/ 1819 1820 usbd_status 1821 ohci_device_intr_transfer(reqh) 1822 usbd_request_handle reqh; 1823 { 1824 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 1825 usbd_device_handle dev = opipe->pipe.device; 1826 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 1827 ohci_soft_ed_t *sed = opipe->sed; 1828 ohci_soft_td_t *xfer, *tail; 1829 usb_dma_t *dmap; 1830 usbd_status r; 1831 int len; 1832 int s; 1833 1834 DPRINTFN(3, ("ohci_device_intr_transfer: reqh=%p buf=%p len=%d flags=%d priv=%p\n", 1835 reqh, reqh->buffer, reqh->length, reqh->flags, reqh->priv)); 1836 1837 if (reqh->isreq) 1838 panic("ohci_device_intr_transfer: a request\n"); 1839 1840 len = reqh->length; 1841 dmap = &opipe->u.intr.datadma; 1842 if (len == 0) 1843 return (USBD_INVAL); /* XXX should it be? */ 1844 1845 xfer = opipe->tail; 1846 tail = ohci_alloc_std(sc); 1847 if (!tail) { 1848 r = USBD_NOMEM; 1849 goto ret1; 1850 } 1851 tail->reqh = 0; 1852 1853 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap); 1854 if (r != USBD_NORMAL_COMPLETION) 1855 goto ret2; 1856 1857 xfer->td->td_flags = OHCI_TD_IN | OHCI_TD_NOCC | 1858 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY; 1859 xfer->td->td_cbp = DMAADDR(dmap); 1860 xfer->nexttd = tail; 1861 xfer->td->td_nexttd = tail->physaddr; 1862 xfer->td->td_be = xfer->td->td_cbp + len - 1; 1863 xfer->len = len; 1864 xfer->reqh = reqh; 1865 1866 reqh->actlen = 0; 1867 reqh->hcpriv = xfer; 1868 1869 #if USB_DEBUG 1870 if (ohcidebug > 5) { 1871 printf("ohci_device_intr_transfer:\n"); 1872 ohci_dump_ed(sed); 1873 ohci_dump_tds(xfer); 1874 } 1875 #endif 1876 1877 /* Insert ED in schedule */ 1878 s = splusb(); 1879 ohci_hash_add_td(sc, xfer); 1880 sed->ed->ed_tailp = tail->physaddr; 1881 opipe->tail = tail; 1882 #if 0 1883 if (reqh->timeout && !usbd_use_polling) 1884 timeout(ohci_timeout, reqh, MS_TO_TICKS(reqh->timeout)); 1885 #endif 1886 sed->ed->ed_flags &= ~OHCI_ED_SKIP; 1887 splx(s); 1888 1889 #ifdef USB_DEBUG 1890 if (ohcidebug > 5) { 1891 delay(5000); 1892 printf("ohci_device_intr_transfer: status=%x\n", 1893 OREAD4(sc, OHCI_COMMAND_STATUS)); 1894 ohci_dump_ed(sed); 1895 ohci_dump_tds(xfer); 1896 } 1897 #endif 1898 1899 return (USBD_IN_PROGRESS); 1900 1901 ret2: 1902 ohci_free_std(sc, xfer); 1903 ret1: 1904 return (r); 1905 } 1906 1907 /* Abort a device control request. */ 1908 void 1909 ohci_device_intr_abort(reqh) 1910 usbd_request_handle reqh; 1911 { 1912 struct uhci_pipe *opipe; 1913 1914 /* XXX inactivate */ 1915 usbd_delay_ms(1); /* make sure it is finished */ 1916 if (reqh->pipe->intrreqh == reqh) { 1917 DPRINTF(("ohci_device_intr_abort: remove\n")); 1918 reqh->pipe->intrreqh = 0; 1919 opipe = (struct uhci_pipe *)reqh->pipe; 1920 ohci_intr_done((ohci_softc_t *)reqh->pipe->device->bus, reqh); 1921 } 1922 } 1923 1924 /* Close a device interrupt pipe. */ 1925 void 1926 ohci_device_intr_close(pipe) 1927 usbd_pipe_handle pipe; 1928 { 1929 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 1930 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 1931 int nslots = opipe->u.intr.nslots; 1932 int pos = opipe->u.intr.pos; 1933 int j; 1934 ohci_soft_ed_t *p, *sed = opipe->sed; 1935 int s; 1936 1937 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n", 1938 pipe, nslots, pos)); 1939 s = splusb(); 1940 sed->ed->ed_flags |= OHCI_ED_SKIP; 1941 if ((sed->ed->ed_tailp & OHCI_TAILMASK) != sed->ed->ed_headp) 1942 usbd_delay_ms(2); 1943 1944 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 1945 ; 1946 if (!p) 1947 panic("ohci_device_intr_close: ED not found\n"); 1948 p->next = sed->next; 1949 p->ed->ed_nexted = sed->ed->ed_nexted; 1950 splx(s); 1951 1952 for (j = 0; j < nslots; j++) 1953 --sc->sc_bws[pos * nslots + j]; 1954 1955 ohci_free_std(sc, opipe->tail); 1956 ohci_free_sed(sc, opipe->sed); 1957 /* XXX free other resources */ 1958 } 1959 1960 usbd_status 1961 ohci_device_setintr(sc, opipe, ival) 1962 ohci_softc_t *sc; 1963 struct ohci_pipe *opipe; 1964 int ival; 1965 { 1966 int i, j, s, best; 1967 u_int npoll, slow, shigh, nslots; 1968 u_int bestbw, bw; 1969 ohci_soft_ed_t *hsed, *sed = opipe->sed; 1970 1971 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe)); 1972 if (ival == 0) { 1973 printf("ohci_setintr: 0 interval\n"); 1974 return (USBD_INVAL); 1975 } 1976 1977 npoll = OHCI_NO_INTRS; 1978 while (npoll > ival) 1979 npoll /= 2; 1980 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll)); 1981 1982 /* 1983 * We now know which level in the tree the ED must go into. 1984 * Figure out which slot has most bandwidth left over. 1985 * Slots to examine: 1986 * npoll 1987 * 1 0 1988 * 2 1 2 1989 * 4 3 4 5 6 1990 * 8 7 8 9 10 11 12 13 14 1991 * N (N-1) .. (N-1+N-1) 1992 */ 1993 slow = npoll-1; 1994 shigh = slow + npoll; 1995 nslots = OHCI_NO_INTRS / npoll; 1996 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 1997 bw = 0; 1998 for (j = 0; j < nslots; j++) 1999 bw += sc->sc_bws[i * nslots + j]; 2000 if (bw < bestbw) { 2001 best = i; 2002 bestbw = bw; 2003 } 2004 } 2005 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n", 2006 best, slow, shigh, bestbw)); 2007 2008 s = splusb(); 2009 hsed = sc->sc_eds[best]; 2010 sed->next = hsed->next; 2011 sed->ed->ed_nexted = hsed->ed->ed_nexted; 2012 hsed->next = sed; 2013 hsed->ed->ed_nexted = sed->physaddr; 2014 splx(s); 2015 2016 for (j = 0; j < nslots; j++) 2017 ++sc->sc_bws[best * nslots + j]; 2018 opipe->u.intr.nslots = nslots; 2019 opipe->u.intr.pos = best; 2020 2021 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe)); 2022 return (USBD_NORMAL_COMPLETION); 2023 } 2024 2025
Indexes created Wed Sep 24 05:09:52 GMT 2025