ohci.c revision 1.9
1 /* $NetBSD: ohci.c,v 1.9 1998/11/21 18:57:09 augustss Exp $ */ 2 3 /* 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Author: Lennart Augustsson <augustss (at) carlstedt.se> 8 * Carlstedt Research & Technology 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * USB Open Host Controller driver. 41 * 42 * OHCI spec: http://www.intel.com/design/usb/ohci11d.pdf 43 * USB spec: http://www.teleport.com/cgi-bin/mailmerge.cgi/~usb/cgiform.tpl 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/malloc.h> 50 #include <sys/device.h> 51 #include <sys/proc.h> 52 #include <sys/queue.h> 53 #include <sys/select.h> 54 55 #include <machine/bus.h> 56 57 #include <dev/usb/usb.h> 58 #include <dev/usb/usbdi.h> 59 #include <dev/usb/usbdivar.h> 60 #include <dev/usb/usb_quirks.h> 61 #include <dev/usb/usb_mem.h> 62 63 #include <dev/usb/ohcireg.h> 64 #include <dev/usb/ohcivar.h> 65 66 int ohcidebug = 0; 67 68 struct ohci_pipe; 69 70 ohci_soft_ed_t *ohci_alloc_sed __P((ohci_softc_t *)); 71 void ohci_free_sed __P((ohci_softc_t *, ohci_soft_ed_t *)); 72 73 ohci_soft_td_t *ohci_alloc_std __P((ohci_softc_t *)); 74 void ohci_free_std __P((ohci_softc_t *, ohci_soft_td_t *)); 75 76 usbd_status ohci_open __P((usbd_pipe_handle)); 77 void ohci_poll __P((struct usbd_bus *)); 78 void ohci_waitintr __P((ohci_softc_t *, usbd_request_handle)); 79 void ohci_rhsc __P((ohci_softc_t *, usbd_request_handle)); 80 void ohci_process_done __P((ohci_softc_t *, ohci_physaddr_t)); 81 void ohci_ctrl_done __P((ohci_softc_t *, usbd_request_handle)); 82 void ohci_intr_done __P((ohci_softc_t *, usbd_request_handle)); 83 void ohci_bulk_done __P((ohci_softc_t *, usbd_request_handle)); 84 85 usbd_status ohci_device_request __P((usbd_request_handle reqh)); 86 void ohci_add_ed __P((ohci_soft_ed_t *, ohci_soft_ed_t *)); 87 void ohci_rem_ed __P((ohci_soft_ed_t *, ohci_soft_ed_t *)); 88 void ohci_hash_add_td __P((ohci_softc_t *, ohci_soft_td_t *)); 89 void ohci_hash_rem_td __P((ohci_softc_t *, ohci_soft_td_t *)); 90 ohci_soft_td_t *ohci_hash_find_td __P((ohci_softc_t *, ohci_physaddr_t)); 91 92 usbd_status ohci_root_ctrl_transfer __P((usbd_request_handle)); 93 void ohci_root_ctrl_abort __P((usbd_request_handle)); 94 void ohci_root_ctrl_close __P((usbd_pipe_handle)); 95 96 usbd_status ohci_root_intr_transfer __P((usbd_request_handle)); 97 void ohci_root_intr_abort __P((usbd_request_handle)); 98 void ohci_root_intr_close __P((usbd_pipe_handle)); 99 100 usbd_status ohci_device_ctrl_transfer __P((usbd_request_handle)); 101 void ohci_device_ctrl_abort __P((usbd_request_handle)); 102 void ohci_device_ctrl_close __P((usbd_pipe_handle)); 103 104 usbd_status ohci_device_bulk_transfer __P((usbd_request_handle)); 105 void ohci_device_bulk_abort __P((usbd_request_handle)); 106 void ohci_device_bulk_close __P((usbd_pipe_handle)); 107 108 usbd_status ohci_device_intr_transfer __P((usbd_request_handle)); 109 void ohci_device_intr_abort __P((usbd_request_handle)); 110 void ohci_device_intr_close __P((usbd_pipe_handle)); 111 usbd_status ohci_device_setintr __P((ohci_softc_t *sc, 112 struct ohci_pipe *pipe, int ival)); 113 114 int ohci_str __P((usb_string_descriptor_t *, int, char *)); 115 116 void ohci_timeout __P((void *)); 117 void ohci_rhsc_able __P((ohci_softc_t *, int)); 118 119 #ifdef USB_DEBUG 120 ohci_softc_t *thesc; 121 void ohci_dumpregs __P((ohci_softc_t *)); 122 void ohci_dump_tds __P((ohci_soft_td_t *)); 123 void ohci_dump_td __P((ohci_soft_td_t *)); 124 void ohci_dump_ed __P((ohci_soft_ed_t *)); 125 #endif 126 127 #define OWRITE4(sc, r, x) bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)) 128 #define OREAD4(sc, r) bus_space_read_4((sc)->iot, (sc)->ioh, (r)) 129 #define OREAD2(sc, r) bus_space_read_2((sc)->iot, (sc)->ioh, (r)) 130 131 /* Reverse the bits in a value 0 .. 31 */ 132 static u_int8_t revbits[OHCI_NO_INTRS] = 133 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 134 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 135 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 136 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 137 138 struct ohci_pipe { 139 struct usbd_pipe pipe; 140 ohci_soft_ed_t *sed; 141 ohci_soft_td_t *tail; 142 /* Info needed for different pipe kinds. */ 143 union { 144 /* Control pipe */ 145 struct { 146 usb_dma_t datadma; 147 usb_dma_t reqdma; 148 u_int length; 149 ohci_soft_td_t *setup, *xfer, *stat; 150 } ctl; 151 /* Interrupt pipe */ 152 struct { 153 usb_dma_t datadma; 154 int nslots; 155 int pos; 156 } intr; 157 /* Bulk pipe */ 158 struct { 159 usb_dma_t datadma; 160 u_int length; 161 } bulk; 162 } u; 163 }; 164 165 #define OHCI_INTR_ENDPT 1 166 167 struct usbd_methods ohci_root_ctrl_methods = { 168 ohci_root_ctrl_transfer, 169 ohci_root_ctrl_abort, 170 ohci_root_ctrl_close, 171 0, 172 }; 173 174 struct usbd_methods ohci_root_intr_methods = { 175 ohci_root_intr_transfer, 176 ohci_root_intr_abort, 177 ohci_root_intr_close, 178 0, 179 }; 180 181 struct usbd_methods ohci_device_ctrl_methods = { 182 ohci_device_ctrl_transfer, 183 ohci_device_ctrl_abort, 184 ohci_device_ctrl_close, 185 0, 186 }; 187 188 struct usbd_methods ohci_device_intr_methods = { 189 ohci_device_intr_transfer, 190 ohci_device_intr_abort, 191 ohci_device_intr_close, 192 }; 193 194 struct usbd_methods ohci_device_bulk_methods = { 195 ohci_device_bulk_transfer, 196 ohci_device_bulk_abort, 197 ohci_device_bulk_close, 198 0, 199 }; 200 201 ohci_soft_ed_t * 202 ohci_alloc_sed(sc) 203 ohci_softc_t *sc; 204 { 205 ohci_soft_ed_t *sed; 206 usbd_status r; 207 int i, offs; 208 usb_dma_t dma; 209 210 if (!sc->sc_freeeds) { 211 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n")); 212 sed = malloc(sizeof(ohci_soft_ed_t) * OHCI_ED_CHUNK, 213 M_USBDEV, M_NOWAIT); 214 if (!sed) 215 return 0; 216 r = usb_allocmem(sc->sc_dmatag, OHCI_ED_SIZE * OHCI_ED_CHUNK, 217 OHCI_ED_ALIGN, &dma); 218 if (r != USBD_NORMAL_COMPLETION) { 219 free(sed, M_USBDEV); 220 return 0; 221 } 222 for(i = 0; i < OHCI_ED_CHUNK; i++, sed++) { 223 offs = i * OHCI_ED_SIZE; 224 sed->physaddr = DMAADDR(&dma) + offs; 225 sed->ed = (ohci_ed_t *) 226 ((char *)KERNADDR(&dma) + offs); 227 sed->next = sc->sc_freeeds; 228 sc->sc_freeeds = sed; 229 } 230 } 231 sed = sc->sc_freeeds; 232 sc->sc_freeeds = sed->next; 233 memset(sed->ed, 0, OHCI_ED_SIZE); 234 sed->next = 0; 235 return sed; 236 } 237 238 void 239 ohci_free_sed(sc, sed) 240 ohci_softc_t *sc; 241 ohci_soft_ed_t *sed; 242 { 243 sed->next = sc->sc_freeeds; 244 sc->sc_freeeds = sed; 245 } 246 247 ohci_soft_td_t * 248 ohci_alloc_std(sc) 249 ohci_softc_t *sc; 250 { 251 ohci_soft_td_t *std; 252 usbd_status r; 253 int i, offs; 254 usb_dma_t dma; 255 256 if (!sc->sc_freetds) { 257 DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n")); 258 std = malloc(sizeof(ohci_soft_td_t) * OHCI_TD_CHUNK, 259 M_USBDEV, M_NOWAIT); 260 if (!std) 261 return 0; 262 r = usb_allocmem(sc->sc_dmatag, OHCI_TD_SIZE * OHCI_TD_CHUNK, 263 OHCI_TD_ALIGN, &dma); 264 if (r != USBD_NORMAL_COMPLETION) { 265 free(std, M_USBDEV); 266 return 0; 267 } 268 for(i = 0; i < OHCI_TD_CHUNK; i++, std++) { 269 offs = i * OHCI_TD_SIZE; 270 std->physaddr = DMAADDR(&dma) + offs; 271 std->td = (ohci_td_t *) 272 ((char *)KERNADDR(&dma) + offs); 273 std->nexttd = sc->sc_freetds; 274 sc->sc_freetds = std; 275 } 276 } 277 std = sc->sc_freetds; 278 sc->sc_freetds = std->nexttd; 279 memset(std->td, 0, OHCI_TD_SIZE); 280 std->nexttd = 0; 281 return (std); 282 } 283 284 void 285 ohci_free_std(sc, std) 286 ohci_softc_t *sc; 287 ohci_soft_td_t *std; 288 { 289 std->nexttd = sc->sc_freetds; 290 sc->sc_freetds = std; 291 } 292 293 usbd_status 294 ohci_init(sc) 295 ohci_softc_t *sc; 296 { 297 ohci_soft_ed_t *sed, *psed; 298 usbd_status r; 299 int rev; 300 int i; 301 u_int32_t s, ctl, ival, hcr, fm, per; 302 303 DPRINTF(("ohci_init: start\n")); 304 rev = OREAD4(sc, OHCI_REVISION); 305 printf("%s: OHCI version %d.%d%s\n", sc->sc_bus.bdev.dv_xname, 306 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 307 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 308 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 309 printf("%s: unsupported OHCI revision\n", 310 sc->sc_bus.bdev.dv_xname); 311 return (USBD_INVAL); 312 } 313 314 for (i = 0; i < OHCI_HASH_SIZE; i++) 315 LIST_INIT(&sc->sc_hash_tds[i]); 316 317 /* Allocate the HCCA area. */ 318 r = usb_allocmem(sc->sc_dmatag, OHCI_HCCA_SIZE, 319 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 320 if (r != USBD_NORMAL_COMPLETION) 321 return (r); 322 sc->sc_hcca = (struct ohci_hcca *)KERNADDR(&sc->sc_hccadma); 323 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 324 325 sc->sc_eintrs = OHCI_NORMAL_INTRS; 326 327 sc->sc_ctrl_head = ohci_alloc_sed(sc); 328 if (!sc->sc_ctrl_head) { 329 r = USBD_NOMEM; 330 goto bad1; 331 } 332 sc->sc_ctrl_head->ed->ed_flags |= OHCI_ED_SKIP; 333 sc->sc_bulk_head = ohci_alloc_sed(sc); 334 if (!sc->sc_bulk_head) { 335 r = USBD_NOMEM; 336 goto bad2; 337 } 338 sc->sc_bulk_head->ed->ed_flags |= OHCI_ED_SKIP; 339 340 /* Allocate all the dummy EDs that make up the interrupt tree. */ 341 for (i = 0; i < OHCI_NO_EDS; i++) { 342 sed = ohci_alloc_sed(sc); 343 if (!sed) { 344 while (--i >= 0) 345 ohci_free_sed(sc, sc->sc_eds[i]); 346 r = USBD_NOMEM; 347 goto bad3; 348 } 349 /* All ED fields are set to 0. */ 350 sc->sc_eds[i] = sed; 351 sed->ed->ed_flags |= OHCI_ED_SKIP; 352 if (i != 0) { 353 psed = sc->sc_eds[(i-1) / 2]; 354 sed->next = psed; 355 sed->ed->ed_nexted = psed->physaddr; 356 } 357 } 358 /* 359 * Fill HCCA interrupt table. The bit reversal is to get 360 * the tree set up properly to spread the interrupts. 361 */ 362 for (i = 0; i < OHCI_NO_INTRS; i++) 363 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 364 sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr; 365 366 /* Determine in what context we are running. */ 367 ctl = OREAD4(sc, OHCI_CONTROL); 368 if (ctl & OHCI_IR) { 369 /* SMM active, request change */ 370 DPRINTF(("ohci_init: SMM active, request owner change\n")); 371 s = OREAD4(sc, OHCI_COMMAND_STATUS); 372 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 373 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 374 delay(1000); 375 ctl = OREAD4(sc, OHCI_CONTROL); 376 } 377 if ((ctl & OHCI_IR) == 0) { 378 printf("%s: SMM does not respond, resetting\n", 379 sc->sc_bus.bdev.dv_xname); 380 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 381 goto reset; 382 } 383 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 384 /* BIOS started controller. */ 385 DPRINTF(("ohci_init: BIOS active\n")); 386 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 387 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL); 388 delay(USB_RESUME_DELAY * 1000); 389 } 390 } else { 391 DPRINTF(("ohci_init: cold started\n")); 392 reset: 393 /* Controller was cold started. */ 394 delay(USB_RESET_DELAY * 1000); 395 } 396 397 /* We now own the host controller and the bus has been reset. */ 398 ival = OHCI_GET_IVAL(OREAD4(sc, OHCI_FM_INTERVAL)); 399 400 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 401 /* Nominal time for a reset is 10 us. */ 402 for (i = 0; i < 10; i++) { 403 delay(10); 404 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 405 if (!hcr) 406 break; 407 } 408 if (hcr) { 409 printf("%s: reset timeout\n", sc->sc_bus.bdev.dv_xname); 410 r = USBD_IOERROR; 411 goto bad3; 412 } 413 #ifdef USB_DEBUG 414 thesc = sc; 415 if (ohcidebug > 15) 416 ohci_dumpregs(sc); 417 #endif 418 419 /* The controller is now in suspend state, we have 2ms to finish. */ 420 421 /* Set up HC registers. */ 422 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma)); 423 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 424 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 425 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 426 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 427 ctl = OREAD4(sc, OHCI_CONTROL); 428 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 429 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 430 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL; 431 /* And finally start it! */ 432 OWRITE4(sc, OHCI_CONTROL, ctl); 433 434 /* 435 * The controller is now OPERATIONAL. Set a some final 436 * registers that should be set earlier, but that the 437 * controller ignores when in the SUSPEND state. 438 */ 439 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 440 fm |= OHCI_FSMPS(ival) | ival; 441 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 442 per = OHCI_PERIODIC(ival); /* 90% periodic */ 443 OWRITE4(sc, OHCI_PERIODIC_START, per); 444 445 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 446 447 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 448 printf("%s: %d downstream port%s\n", 449 sc->sc_bus.bdev.dv_xname, sc->sc_noport, 450 sc->sc_noport != 1 ? "s" : ""); 451 452 #ifdef USB_DEBUG 453 if (ohcidebug > 5) 454 ohci_dumpregs(sc); 455 #endif 456 457 /* Set up the bus struct. */ 458 sc->sc_bus.open_pipe = ohci_open; 459 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe); 460 sc->sc_bus.do_poll = ohci_poll; 461 462 return (USBD_NORMAL_COMPLETION); 463 464 bad3: 465 ohci_free_sed(sc, sc->sc_ctrl_head); 466 bad2: 467 ohci_free_sed(sc, sc->sc_bulk_head); 468 bad1: 469 usb_freemem(sc->sc_dmatag, &sc->sc_hccadma); 470 return (r); 471 } 472 473 #ifdef USB_DEBUG 474 void ohcidump(void); 475 void ohcidump(void) { ohci_dumpregs(thesc); } 476 477 void 478 ohci_dumpregs(sc) 479 ohci_softc_t *sc; 480 { 481 printf("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 482 OREAD4(sc, OHCI_REVISION), 483 OREAD4(sc, OHCI_CONTROL), 484 OREAD4(sc, OHCI_COMMAND_STATUS)); 485 printf(" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 486 OREAD4(sc, OHCI_INTERRUPT_STATUS), 487 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 488 OREAD4(sc, OHCI_INTERRUPT_DISABLE)); 489 printf(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 490 OREAD4(sc, OHCI_HCCA), 491 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 492 OREAD4(sc, OHCI_CONTROL_HEAD_ED)); 493 printf(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 494 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 495 OREAD4(sc, OHCI_BULK_HEAD_ED), 496 OREAD4(sc, OHCI_BULK_CURRENT_ED)); 497 printf(" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 498 OREAD4(sc, OHCI_DONE_HEAD), 499 OREAD4(sc, OHCI_FM_INTERVAL), 500 OREAD4(sc, OHCI_FM_REMAINING)); 501 printf(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 502 OREAD4(sc, OHCI_FM_NUMBER), 503 OREAD4(sc, OHCI_PERIODIC_START), 504 OREAD4(sc, OHCI_LS_THRESHOLD)); 505 printf(" desca=0x%08x descb=0x%08x stat=0x%08x\n", 506 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 507 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 508 OREAD4(sc, OHCI_RH_STATUS)); 509 printf(" port1=0x%08x port2=0x%08x\n", 510 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 511 OREAD4(sc, OHCI_RH_PORT_STATUS(2))); 512 printf(" HCCA: frame_number=0x%04x done_head=0x%08x\n", 513 sc->sc_hcca->hcca_frame_number, 514 sc->sc_hcca->hcca_done_head); 515 } 516 #endif 517 518 int 519 ohci_intr(p) 520 void *p; 521 { 522 ohci_softc_t *sc = p; 523 u_int32_t intrs, eintrs; 524 ohci_physaddr_t done; 525 526 done = sc->sc_hcca->hcca_done_head; 527 if (done != 0) { 528 intrs = OHCI_WDH; 529 if (done & OHCI_DONE_INTRS) 530 intrs |= OREAD4(sc, OHCI_INTERRUPT_STATUS); 531 } else 532 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 533 if (!intrs) 534 return (0); 535 intrs &= ~OHCI_MIE; 536 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs); /* Acknowledge */ 537 eintrs = intrs & sc->sc_eintrs; 538 if (!eintrs) 539 return (0); 540 541 sc->sc_intrs++; 542 DPRINTFN(7, ("ohci_intr: sc=%p intrs=%x(%x) eintr=%x\n", 543 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), 544 (u_int)eintrs)); 545 546 if (eintrs & OHCI_SO) { 547 printf("%s: scheduling overrun\n", sc->sc_bus.bdev.dv_xname); 548 /* XXX do what */ 549 intrs &= ~OHCI_SO; 550 } 551 if (eintrs & OHCI_WDH) { 552 ohci_process_done(sc, done &~ OHCI_DONE_INTRS); 553 sc->sc_hcca->hcca_done_head = 0; 554 intrs &= ~OHCI_WDH; 555 } 556 if (eintrs & OHCI_RD) { 557 /* XXX process resume detect */ 558 } 559 if (eintrs & OHCI_UE) { 560 printf("%s: unrecoverable error, controller halted\n", 561 sc->sc_bus.bdev.dv_xname); 562 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 563 /* XXX what else */ 564 } 565 if (eintrs & OHCI_RHSC) { 566 ohci_rhsc(sc, sc->sc_intrreqh); 567 intrs &= ~OHCI_RHSC; 568 569 /* 570 * Disable RHSC interrupt for now, because it will be 571 * on until the port has been reset. 572 */ 573 ohci_rhsc_able(sc, 0); 574 } 575 576 /* Block unprocessed interrupts. XXX */ 577 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, intrs); 578 sc->sc_eintrs &= ~intrs; 579 580 return (1); 581 } 582 583 void 584 ohci_rhsc_able(sc, on) 585 ohci_softc_t *sc; 586 int on; 587 { 588 DPRINTFN(4, ("ohci_rhsc_able: on=%d\n", on)); 589 if (on) { 590 sc->sc_eintrs |= OHCI_RHSC; 591 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 592 } else { 593 sc->sc_eintrs &= ~OHCI_RHSC; 594 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_RHSC); 595 } 596 } 597 598 void 599 ohci_process_done(sc, done) 600 ohci_softc_t *sc; 601 ohci_physaddr_t done; 602 { 603 ohci_soft_td_t *std, *sdone; 604 usbd_request_handle reqh; 605 int len, cc; 606 607 DPRINTFN(10,("ohci_process_done: done=0x%08lx\n", (u_long)done)); 608 609 /* Reverse the done list. */ 610 for (sdone = 0; done; done = std->td->td_nexttd) { 611 std = ohci_hash_find_td(sc, done); 612 std->dnext = sdone; 613 sdone = std; 614 } 615 616 #ifdef USB_DEBUG 617 if (ohcidebug > 10) { 618 printf("ohci_process_done: TD done:\n"); 619 ohci_dump_tds(sdone); 620 } 621 #endif 622 623 for (std = sdone; std; std = std->dnext) { 624 reqh = std->reqh; 625 DPRINTFN(10, ("ohci_process_done: std=%p reqh=%p\n",std,reqh)); 626 cc = OHCI_TD_GET_CC(std->td->td_flags); 627 if (cc == OHCI_CC_NO_ERROR) { 628 if (std->td->td_cbp == 0) 629 len = std->len; 630 else 631 len = std->td->td_be - std->td->td_cbp + 1; 632 reqh->actlen += len; 633 if (reqh->hcpriv == std) { 634 switch (reqh->pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 635 case UE_CONTROL: 636 ohci_ctrl_done(sc, reqh); 637 break; 638 case UE_INTERRUPT: 639 ohci_intr_done(sc, reqh); 640 break; 641 case UE_BULK: 642 ohci_bulk_done(sc, reqh); 643 break; 644 case UE_ISOCHRONOUS: 645 printf("ohci_process_done: ISO done?\n"); 646 break; 647 } 648 /* And finally execute callback. */ 649 reqh->status = USBD_NORMAL_COMPLETION; 650 reqh->xfercb(reqh); 651 } 652 } else { 653 ohci_soft_td_t *p, *n; 654 struct ohci_pipe *opipe = 655 (struct ohci_pipe *)reqh->pipe; 656 DPRINTFN(-1,("ohci_process_done: error cc=%d\n", 657 OHCI_TD_GET_CC(std->td->td_flags))); 658 /* 659 * Endpoint is halted. First unlink all the TDs 660 * belonging to the failed transfer, and then restart 661 * the endpoint. 662 */ 663 for (p = std->nexttd; p->reqh == reqh; p = n) { 664 n = p->nexttd; 665 ohci_hash_rem_td(sc, p); 666 ohci_free_std(sc, p); 667 } 668 opipe->sed->ed->ed_headp = p->physaddr;/* clear halt */ 669 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 670 671 if (cc == OHCI_CC_STALL) 672 reqh->status = USBD_STALLED; 673 else 674 reqh->status = USBD_IOERROR; 675 reqh->xfercb(reqh); 676 } 677 ohci_hash_rem_td(sc, std); 678 ohci_free_std(sc, std); 679 } 680 } 681 682 void 683 ohci_ctrl_done(sc, reqh) 684 ohci_softc_t *sc; 685 usbd_request_handle reqh; 686 { 687 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 688 u_int len = opipe->u.ctl.length; 689 usb_dma_t *dma; 690 691 DPRINTFN(10,("ohci_ctrl_done: reqh=%p\n", reqh)); 692 693 if (!reqh->isreq) { 694 panic("ohci_ctrl_done: not a request\n"); 695 return; 696 } 697 698 if (len != 0) { 699 dma = &opipe->u.ctl.datadma; 700 if (reqh->request.bmRequestType & UT_READ) 701 memcpy(reqh->buffer, KERNADDR(dma), len); 702 usb_freemem(sc->sc_dmatag, dma); 703 } 704 } 705 706 void 707 ohci_intr_done(sc, reqh) 708 ohci_softc_t *sc; 709 usbd_request_handle reqh; 710 { 711 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 712 usb_dma_t *dma; 713 ohci_soft_ed_t *sed = opipe->sed; 714 ohci_soft_td_t *xfer, *tail; 715 716 717 DPRINTFN(10,("ohci_intr_done: reqh=%p, actlen=%d\n", 718 reqh, reqh->actlen)); 719 720 dma = &opipe->u.intr.datadma; 721 memcpy(reqh->buffer, KERNADDR(dma), reqh->actlen); 722 723 if (reqh->pipe->intrreqh == reqh) { 724 xfer = opipe->tail; 725 tail = ohci_alloc_std(sc); /* XXX should reuse TD */ 726 if (!tail) { 727 reqh->status = USBD_NOMEM; 728 return; 729 } 730 tail->reqh = 0; 731 732 xfer->td->td_flags = OHCI_TD_IN | OHCI_TD_NOCC | 733 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY; 734 xfer->td->td_cbp = DMAADDR(dma); 735 xfer->nexttd = tail; 736 xfer->td->td_nexttd = tail->physaddr; 737 xfer->td->td_be = xfer->td->td_cbp + reqh->length - 1; 738 xfer->len = reqh->length; 739 xfer->reqh = reqh; 740 741 reqh->actlen = 0; 742 reqh->hcpriv = xfer; 743 744 ohci_hash_add_td(sc, xfer); 745 sed->ed->ed_tailp = tail->physaddr; 746 opipe->tail = tail; 747 } else { 748 usb_freemem(sc->sc_dmatag, dma); 749 } 750 } 751 752 void 753 ohci_bulk_done(sc, reqh) 754 ohci_softc_t *sc; 755 usbd_request_handle reqh; 756 { 757 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 758 usb_dma_t *dma; 759 760 761 DPRINTFN(10,("ohci_bulk_done: reqh=%p, actlen=%d\n", 762 reqh, reqh->actlen)); 763 764 dma = &opipe->u.bulk.datadma; 765 if (reqh->request.bmRequestType & UT_READ) 766 memcpy(reqh->buffer, KERNADDR(dma), reqh->actlen); 767 usb_freemem(sc->sc_dmatag, dma); 768 } 769 770 void 771 ohci_rhsc(sc, reqh) 772 ohci_softc_t *sc; 773 usbd_request_handle reqh; 774 { 775 usbd_pipe_handle pipe; 776 struct ohci_pipe *opipe; 777 u_char *p; 778 int i, m; 779 int hstatus; 780 781 hstatus = OREAD4(sc, OHCI_RH_STATUS); 782 DPRINTF(("ohci_rhsc: sc=%p reqh=%p hstatus=0x%08x\n", 783 sc, reqh, hstatus)); 784 785 if (reqh == 0) { 786 /* Just ignore the change. */ 787 return; 788 } 789 790 pipe = reqh->pipe; 791 opipe = (struct ohci_pipe *)pipe; 792 793 p = KERNADDR(&opipe->u.intr.datadma); 794 m = min(sc->sc_noport, reqh->length * 8 - 1); 795 memset(p, 0, reqh->length); 796 for (i = 1; i <= m; i++) { 797 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 798 p[i/8] |= 1 << (i%8); 799 } 800 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p)); 801 reqh->actlen = reqh->length; 802 reqh->status = USBD_NORMAL_COMPLETION; 803 reqh->xfercb(reqh); 804 805 if (reqh->pipe->intrreqh != reqh) { 806 sc->sc_intrreqh = 0; 807 usb_freemem(sc->sc_dmatag, &opipe->u.intr.datadma); 808 } 809 } 810 811 /* 812 * Wait here until controller claims to have an interrupt. 813 * Then call ohci_intr and return. Use timeout to avoid waiting 814 * too long. 815 */ 816 void 817 ohci_waitintr(sc, reqh) 818 ohci_softc_t *sc; 819 usbd_request_handle reqh; 820 { 821 int timo = reqh->timeout; 822 int usecs; 823 u_int32_t intrs; 824 825 reqh->status = USBD_IN_PROGRESS; 826 for (usecs = timo * 1000000 / hz; usecs > 0; usecs -= 1000) { 827 delay(1000); 828 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 829 DPRINTFN(10,("ohci_waitintr: 0x%04x\n", intrs)); 830 #ifdef USB_DEBUG 831 if (ohcidebug > 15) 832 ohci_dumpregs(sc); 833 #endif 834 if (intrs) { 835 ohci_intr(sc); 836 if (reqh->status != USBD_IN_PROGRESS) 837 return; 838 } 839 } 840 DPRINTF(("ohci_waitintr: timeout\n")); 841 reqh->status = USBD_TIMEOUT; 842 reqh->xfercb(reqh); 843 } 844 845 void 846 ohci_poll(bus) 847 struct usbd_bus *bus; 848 { 849 ohci_softc_t *sc = (ohci_softc_t *)bus; 850 851 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) 852 ohci_intr(sc); 853 } 854 855 usbd_status 856 ohci_device_request(reqh) 857 usbd_request_handle reqh; 858 { 859 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 860 usb_device_request_t *req = &reqh->request; 861 usbd_device_handle dev = opipe->pipe.device; 862 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 863 int addr = dev->address; 864 ohci_soft_td_t *setup, *xfer = 0, *stat, *next, *tail; 865 ohci_soft_ed_t *sed; 866 usb_dma_t *dmap; 867 int isread; 868 int len; 869 usbd_status r; 870 int s; 871 872 isread = req->bmRequestType & UT_READ; 873 len = UGETW(req->wLength); 874 875 DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 876 req->bmRequestType, req->bRequest, UGETW(req->wValue), 877 UGETW(req->wIndex), len, addr, 878 opipe->pipe.endpoint->edesc->bEndpointAddress)); 879 880 setup = opipe->tail; 881 stat = ohci_alloc_std(sc); 882 if (!stat) { 883 r = USBD_NOMEM; 884 goto bad1; 885 } 886 tail = ohci_alloc_std(sc); 887 if (!tail) { 888 r = USBD_NOMEM; 889 goto bad2; 890 } 891 tail->reqh = 0; 892 893 sed = opipe->sed; 894 dmap = &opipe->u.ctl.datadma; 895 opipe->u.ctl.length = len; 896 897 /* Update device address */ 898 sed->ed->ed_flags = 899 (sed->ed->ed_flags & ~OHCI_ED_ADDRMASK) | 900 OHCI_ED_SET_FA(addr); 901 902 /* Set up data transaction */ 903 if (len != 0) { 904 xfer = ohci_alloc_std(sc); 905 if (!xfer) { 906 r = USBD_NOMEM; 907 goto bad3; 908 } 909 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap); 910 if (r != USBD_NORMAL_COMPLETION) 911 goto bad4; 912 xfer->td->td_flags = 913 (isread ? OHCI_TD_IN : OHCI_TD_OUT) | OHCI_TD_NOCC | 914 OHCI_TD_TOGGLE_1 | OHCI_TD_NOINTR; 915 xfer->td->td_cbp = DMAADDR(dmap); 916 xfer->nexttd = stat; 917 xfer->td->td_nexttd = stat->physaddr; 918 xfer->td->td_be = xfer->td->td_cbp + len - 1; 919 xfer->len = len; 920 xfer->reqh = reqh; 921 922 next = xfer; 923 } else 924 next = stat; 925 926 memcpy(KERNADDR(&opipe->u.ctl.reqdma), req, sizeof *req); 927 if (!isread && len != 0) 928 memcpy(KERNADDR(dmap), reqh->buffer, len); 929 930 setup->td->td_flags = OHCI_TD_SETUP | OHCI_TD_NOCC | 931 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR; 932 setup->td->td_cbp = DMAADDR(&opipe->u.ctl.reqdma); 933 setup->nexttd = next; 934 setup->td->td_nexttd = next->physaddr; 935 setup->td->td_be = setup->td->td_cbp + sizeof *req - 1; 936 setup->len = 0; /* XXX The number of byte we count */ 937 setup->reqh = reqh; 938 939 stat->td->td_flags = 940 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | OHCI_TD_NOCC | 941 OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1); 942 stat->td->td_cbp = 0; 943 stat->nexttd = tail; 944 stat->td->td_nexttd = tail->physaddr; 945 stat->td->td_be = 0; 946 stat->len = 0; 947 stat->reqh = reqh; 948 949 reqh->actlen = 0; 950 reqh->hcpriv = stat; 951 952 #if USB_DEBUG 953 if (ohcidebug > 5) { 954 printf("ohci_device_request:\n"); 955 ohci_dump_ed(sed); 956 ohci_dump_tds(setup); 957 } 958 #endif 959 960 /* Insert ED in schedule */ 961 s = splusb(); 962 ohci_hash_add_td(sc, setup); 963 if (len != 0) 964 ohci_hash_add_td(sc, xfer); 965 ohci_hash_add_td(sc, stat); 966 sed->ed->ed_tailp = tail->physaddr; 967 opipe->tail = tail; 968 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 969 if (reqh->timeout && !sc->sc_bus.use_polling) 970 timeout(ohci_timeout, reqh, MS_TO_TICKS(reqh->timeout)); 971 splx(s); 972 973 #if USB_DEBUG 974 if (ohcidebug > 5) { 975 delay(5000); 976 printf("ohci_device_request: status=%x\n", 977 OREAD4(sc, OHCI_COMMAND_STATUS)); 978 ohci_dump_ed(sed); 979 ohci_dump_tds(setup); 980 } 981 #endif 982 983 return (USBD_NORMAL_COMPLETION); 984 985 bad4: 986 ohci_free_std(sc, xfer); 987 bad3: 988 ohci_free_std(sc, tail); 989 bad2: 990 ohci_free_std(sc, stat); 991 bad1: 992 return (r); 993 } 994 995 /* 996 * Add an ED to the schedule. Called at splusb(). 997 */ 998 void 999 ohci_add_ed(sed, head) 1000 ohci_soft_ed_t *sed; 1001 ohci_soft_ed_t *head; 1002 { 1003 sed->next = head->next; 1004 sed->ed->ed_nexted = head->ed->ed_nexted; 1005 head->next = sed; 1006 head->ed->ed_nexted = sed->physaddr; 1007 } 1008 1009 /* 1010 * Remove an ED from the schedule. Called at splusb(). 1011 */ 1012 void 1013 ohci_rem_ed(sed, head) 1014 ohci_soft_ed_t *sed; 1015 ohci_soft_ed_t *head; 1016 { 1017 ohci_soft_ed_t *p; 1018 1019 /* XXX */ 1020 for (p = head; p && p->next != sed; p = p->next) 1021 ; 1022 if (!p) 1023 panic("ohci_rem_ed: ED not found\n"); 1024 p->next = sed->next; 1025 p->ed->ed_nexted = sed->ed->ed_nexted; 1026 } 1027 1028 /* 1029 * When a transfer is completed the TD is added to the done queue by 1030 * the host controller. This queue is the processed by software. 1031 * Unfortunately the queue contains the physical address of the TD 1032 * and we have no simple way to translate this back to a kernel address. 1033 * To make the translation possible (and fast) we use a hash table of 1034 * TDs currently in the schedule. The physical address is used as the 1035 * hash value. 1036 */ 1037 1038 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1039 /* Called at splusb() */ 1040 void 1041 ohci_hash_add_td(sc, std) 1042 ohci_softc_t *sc; 1043 ohci_soft_td_t *std; 1044 { 1045 int h = HASH(std->physaddr); 1046 1047 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1048 } 1049 1050 /* Called at splusb() */ 1051 void 1052 ohci_hash_rem_td(sc, std) 1053 ohci_softc_t *sc; 1054 ohci_soft_td_t *std; 1055 { 1056 LIST_REMOVE(std, hnext); 1057 } 1058 1059 ohci_soft_td_t * 1060 ohci_hash_find_td(sc, a) 1061 ohci_softc_t *sc; 1062 ohci_physaddr_t a; 1063 { 1064 int h = HASH(a); 1065 ohci_soft_td_t *std; 1066 1067 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1068 std != 0; 1069 std = LIST_NEXT(std, hnext)) 1070 if (std->physaddr == a) 1071 return (std); 1072 panic("ohci_hash_find_td: addr 0x%08lx not found\n", (u_long)a); 1073 } 1074 1075 void 1076 ohci_timeout(addr) 1077 void *addr; 1078 { 1079 #if 0 1080 usbd_request_handle *reqh = addr; 1081 int s; 1082 1083 DPRINTF(("ohci_timeout: reqh=%p\n", reqh)); 1084 s = splusb(); 1085 /* XXX need to inactivate TD before calling interrupt routine */ 1086 ohci_XXX_done(reqh); 1087 splx(s); 1088 #endif 1089 } 1090 1091 #ifdef USB_DEBUG 1092 void 1093 ohci_dump_tds(std) 1094 ohci_soft_td_t *std; 1095 { 1096 for (; std; std = std->nexttd) 1097 ohci_dump_td(std); 1098 } 1099 1100 void 1101 ohci_dump_td(std) 1102 ohci_soft_td_t *std; 1103 { 1104 printf("TD(%p) at %08lx: %b delay=%d ec=%d cc=%d\ncbp=0x%08lx nexttd=0x%08lx be=0x%08lx\n", 1105 std, (u_long)std->physaddr, 1106 (u_long)std->td->td_flags, 1107 "\20\23R\24OUT\25IN\31TOG1\32SETTOGGLE", 1108 OHCI_TD_GET_DI(std->td->td_flags), 1109 OHCI_TD_GET_EC(std->td->td_flags), 1110 OHCI_TD_GET_CC(std->td->td_flags), 1111 (u_long)std->td->td_cbp, 1112 (u_long)std->td->td_nexttd, (u_long)std->td->td_be); 1113 } 1114 1115 void 1116 ohci_dump_ed(sed) 1117 ohci_soft_ed_t *sed; 1118 { 1119 printf("ED(%p) at %08lx: addr=%d endpt=%d maxp=%d %b\ntailp=0x%08lx headp=%b nexted=0x%08lx\n", 1120 sed, (u_long)sed->physaddr, 1121 OHCI_ED_GET_FA(sed->ed->ed_flags), 1122 OHCI_ED_GET_EN(sed->ed->ed_flags), 1123 OHCI_ED_GET_MAXP(sed->ed->ed_flags), 1124 (u_long)sed->ed->ed_flags, 1125 "\20\14OUT\15IN\16LOWSPEED\17SKIP\18ISO", 1126 (u_long)sed->ed->ed_tailp, 1127 (u_long)sed->ed->ed_headp, "\20\1HALT\2CARRY", 1128 (u_long)sed->ed->ed_nexted); 1129 } 1130 #endif 1131 1132 usbd_status 1133 ohci_open(pipe) 1134 usbd_pipe_handle pipe; 1135 { 1136 usbd_device_handle dev = pipe->device; 1137 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 1138 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1139 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 1140 u_int8_t addr = dev->address; 1141 ohci_soft_ed_t *sed; 1142 ohci_soft_td_t *std; 1143 usbd_status r; 1144 int s; 1145 1146 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1147 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1148 if (addr == sc->sc_addr) { 1149 switch (ed->bEndpointAddress) { 1150 case USB_CONTROL_ENDPOINT: 1151 pipe->methods = &ohci_root_ctrl_methods; 1152 break; 1153 case UE_IN | OHCI_INTR_ENDPT: 1154 pipe->methods = &ohci_root_intr_methods; 1155 break; 1156 default: 1157 return (USBD_INVAL); 1158 } 1159 } else { 1160 sed = ohci_alloc_sed(sc); 1161 if (sed == 0) 1162 goto bad0; 1163 std = ohci_alloc_std(sc); 1164 if (std == 0) 1165 goto bad1; 1166 opipe->sed = sed; 1167 opipe->tail = std; 1168 sed->ed->ed_flags = 1169 OHCI_ED_SET_FA(addr) | 1170 OHCI_ED_SET_EN(ed->bEndpointAddress) | 1171 OHCI_ED_DIR_TD | 1172 (dev->lowspeed ? OHCI_ED_SPEED : 0) | 1173 ((ed->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS ? 1174 OHCI_ED_FORMAT_ISO : OHCI_ED_FORMAT_GEN) | 1175 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize)); 1176 sed->ed->ed_headp = sed->ed->ed_tailp = std->physaddr; 1177 1178 switch (ed->bmAttributes & UE_XFERTYPE) { 1179 case UE_CONTROL: 1180 pipe->methods = &ohci_device_ctrl_methods; 1181 r = usb_allocmem(sc->sc_dmatag, 1182 sizeof(usb_device_request_t), 1183 0, &opipe->u.ctl.reqdma); 1184 if (r != USBD_NORMAL_COMPLETION) 1185 goto bad; 1186 s = splusb(); 1187 ohci_add_ed(sed, sc->sc_ctrl_head); 1188 splx(s); 1189 break; 1190 case UE_INTERRUPT: 1191 pipe->methods = &ohci_device_intr_methods; 1192 return (ohci_device_setintr(sc, opipe, ed->bInterval)); 1193 case UE_ISOCHRONOUS: 1194 printf("ohci_open: open iso unimplemented\n"); 1195 return (USBD_XXX); 1196 case UE_BULK: 1197 pipe->methods = &ohci_device_bulk_methods; 1198 s = splusb(); 1199 ohci_add_ed(sed, sc->sc_bulk_head); 1200 splx(s); 1201 break; 1202 } 1203 } 1204 return (USBD_NORMAL_COMPLETION); 1205 1206 bad: 1207 ohci_free_std(sc, std); 1208 bad1: 1209 ohci_free_sed(sc, sed); 1210 bad0: 1211 return (USBD_NOMEM); 1212 1213 } 1214 1215 /* 1216 * Data structures and routines to emulate the root hub. 1217 */ 1218 usb_device_descriptor_t ohci_devd = { 1219 USB_DEVICE_DESCRIPTOR_SIZE, 1220 UDESC_DEVICE, /* type */ 1221 {0x00, 0x01}, /* USB version */ 1222 UCLASS_HUB, /* class */ 1223 USUBCLASS_HUB, /* subclass */ 1224 0, /* protocol */ 1225 64, /* max packet */ 1226 {0},{0},{0x00,0x01}, /* device id */ 1227 1,2,0, /* string indicies */ 1228 1 /* # of configurations */ 1229 }; 1230 1231 usb_config_descriptor_t ohci_confd = { 1232 USB_CONFIG_DESCRIPTOR_SIZE, 1233 UDESC_CONFIG, 1234 {USB_CONFIG_DESCRIPTOR_SIZE + 1235 USB_INTERFACE_DESCRIPTOR_SIZE + 1236 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1237 1, 1238 1, 1239 0, 1240 UC_SELF_POWERED, 1241 0 /* max power */ 1242 }; 1243 1244 usb_interface_descriptor_t ohci_ifcd = { 1245 USB_INTERFACE_DESCRIPTOR_SIZE, 1246 UDESC_INTERFACE, 1247 0, 1248 0, 1249 1, 1250 UCLASS_HUB, 1251 USUBCLASS_HUB, 1252 0, 1253 0 1254 }; 1255 1256 usb_endpoint_descriptor_t ohci_endpd = { 1257 USB_ENDPOINT_DESCRIPTOR_SIZE, 1258 UDESC_ENDPOINT, 1259 UE_IN | OHCI_INTR_ENDPT, 1260 UE_INTERRUPT, 1261 {8, 0}, /* max packet */ 1262 255 1263 }; 1264 1265 usb_hub_descriptor_t ohci_hubd = { 1266 USB_HUB_DESCRIPTOR_SIZE, 1267 UDESC_HUB, 1268 0, 1269 {0,0}, 1270 0, 1271 0, 1272 {0}, 1273 {0}, 1274 }; 1275 1276 int 1277 ohci_str(p, l, s) 1278 usb_string_descriptor_t *p; 1279 int l; 1280 char *s; 1281 { 1282 int i; 1283 1284 if (l == 0) 1285 return (0); 1286 p->bLength = 2 * strlen(s) + 2; 1287 if (l == 1) 1288 return (1); 1289 p->bDescriptorType = UDESC_STRING; 1290 l -= 2; 1291 for (i = 0; s[i] && l > 1; i++, l -= 2) 1292 USETW2(p->bString[i], 0, s[i]); 1293 return (2*i+2); 1294 } 1295 1296 /* 1297 * Simulate a hardware hub by handling all the necessary requests. 1298 */ 1299 usbd_status 1300 ohci_root_ctrl_transfer(reqh) 1301 usbd_request_handle reqh; 1302 { 1303 ohci_softc_t *sc = (ohci_softc_t *)reqh->pipe->device->bus; 1304 usb_device_request_t *req; 1305 void *buf; 1306 int port, i; 1307 int len, value, index, l, totlen = 0; 1308 usb_port_status_t ps; 1309 usb_hub_descriptor_t hubd; 1310 usbd_status r; 1311 u_int32_t v; 1312 1313 if (!reqh->isreq) 1314 /* XXX panic */ 1315 return (USBD_INVAL); 1316 req = &reqh->request; 1317 buf = reqh->buffer; 1318 1319 DPRINTFN(4,("ohci_root_ctrl_control type=0x%02x request=%02x\n", 1320 req->bmRequestType, req->bRequest)); 1321 1322 len = UGETW(req->wLength); 1323 value = UGETW(req->wValue); 1324 index = UGETW(req->wIndex); 1325 #define C(x,y) ((x) | ((y) << 8)) 1326 switch(C(req->bRequest, req->bmRequestType)) { 1327 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 1328 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 1329 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 1330 /* 1331 * DEVICE_REMOTE_WAKEUP and ENDPOINT_STALL are no-ops 1332 * for the integrated root hub. 1333 */ 1334 break; 1335 case C(UR_GET_CONFIG, UT_READ_DEVICE): 1336 if (len > 0) { 1337 *(u_int8_t *)buf = sc->sc_conf; 1338 totlen = 1; 1339 } 1340 break; 1341 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 1342 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value)); 1343 switch(value >> 8) { 1344 case UDESC_DEVICE: 1345 if ((value & 0xff) != 0) { 1346 r = USBD_IOERROR; 1347 goto ret; 1348 } 1349 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1350 memcpy(buf, &ohci_devd, l); 1351 break; 1352 case UDESC_CONFIG: 1353 if ((value & 0xff) != 0) { 1354 r = USBD_IOERROR; 1355 goto ret; 1356 } 1357 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 1358 memcpy(buf, &ohci_confd, l); 1359 buf = (char *)buf + l; 1360 len -= l; 1361 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 1362 totlen += l; 1363 memcpy(buf, &ohci_ifcd, l); 1364 buf = (char *)buf + l; 1365 len -= l; 1366 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 1367 totlen += l; 1368 memcpy(buf, &ohci_endpd, l); 1369 break; 1370 case UDESC_STRING: 1371 if (len == 0) 1372 break; 1373 *(u_int8_t *)buf = 0; 1374 totlen = 1; 1375 switch (value & 0xff) { 1376 case 1: /* Vendor */ 1377 totlen = ohci_str(buf, len, sc->sc_vendor); 1378 break; 1379 case 2: /* Product */ 1380 totlen = ohci_str(buf, len, "OHCI root hub"); 1381 break; 1382 } 1383 break; 1384 default: 1385 r = USBD_IOERROR; 1386 goto ret; 1387 } 1388 break; 1389 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 1390 if (len > 0) { 1391 *(u_int8_t *)buf = 0; 1392 totlen = 1; 1393 } 1394 break; 1395 case C(UR_GET_STATUS, UT_READ_DEVICE): 1396 if (len > 1) { 1397 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 1398 totlen = 2; 1399 } 1400 break; 1401 case C(UR_GET_STATUS, UT_READ_INTERFACE): 1402 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 1403 if (len > 1) { 1404 USETW(((usb_status_t *)buf)->wStatus, 0); 1405 totlen = 2; 1406 } 1407 break; 1408 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 1409 if (value >= USB_MAX_DEVICES) { 1410 r = USBD_IOERROR; 1411 goto ret; 1412 } 1413 sc->sc_addr = value; 1414 break; 1415 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 1416 if (value != 0 && value != 1) { 1417 r = USBD_IOERROR; 1418 goto ret; 1419 } 1420 sc->sc_conf = value; 1421 break; 1422 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 1423 break; 1424 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 1425 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 1426 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 1427 r = USBD_IOERROR; 1428 goto ret; 1429 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 1430 break; 1431 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 1432 break; 1433 /* Hub requests */ 1434 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 1435 break; 1436 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 1437 DPRINTFN(8, ("ohci_root_ctrl_control: UR_CLEAR_PORT_FEATURE port=%d feature=%d\n", 1438 index, value)); 1439 if (index < 1 || index > sc->sc_noport) { 1440 r = USBD_IOERROR; 1441 goto ret; 1442 } 1443 port = OHCI_RH_PORT_STATUS(index); 1444 switch(value) { 1445 case UHF_PORT_ENABLE: 1446 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 1447 break; 1448 case UHF_PORT_SUSPEND: 1449 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 1450 break; 1451 case UHF_PORT_POWER: 1452 OWRITE4(sc, port, UPS_LOW_SPEED); 1453 break; 1454 case UHF_C_PORT_CONNECTION: 1455 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 1456 break; 1457 case UHF_C_PORT_ENABLE: 1458 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 1459 break; 1460 case UHF_C_PORT_SUSPEND: 1461 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 1462 break; 1463 case UHF_C_PORT_OVER_CURRENT: 1464 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 1465 break; 1466 case UHF_C_PORT_RESET: 1467 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 1468 break; 1469 default: 1470 r = USBD_IOERROR; 1471 goto ret; 1472 } 1473 switch(value) { 1474 case UHF_C_PORT_CONNECTION: 1475 case UHF_C_PORT_ENABLE: 1476 case UHF_C_PORT_SUSPEND: 1477 case UHF_C_PORT_OVER_CURRENT: 1478 case UHF_C_PORT_RESET: 1479 /* Enable RHSC interrupt if condition is cleared. */ 1480 if ((OREAD4(sc, port) >> 16) == 0) 1481 ohci_rhsc_able(sc, 1); 1482 break; 1483 default: 1484 break; 1485 } 1486 break; 1487 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 1488 if (value != 0) { 1489 r = USBD_IOERROR; 1490 goto ret; 1491 } 1492 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 1493 hubd = ohci_hubd; 1494 hubd.bNbrPorts = sc->sc_noport; 1495 USETW(hubd.bHubCharacteristics, 1496 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 1497 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 1498 /* XXX overcurrent */ 1499 ); 1500 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 1501 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 1502 if (sc->sc_noport < 8) { 1503 hubd.DeviceRemovable[0] = (u_int8_t)v; 1504 hubd.PortPowerCtrlMask[0] = (u_int8_t)(v >> 16); 1505 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE; 1506 } else { 1507 hubd.DeviceRemovable[0] = (u_int8_t)v; 1508 hubd.DeviceRemovable[1] = (u_int8_t)(v>>8); 1509 hubd.PortPowerCtrlMask[1] = (u_int8_t)(v >> 16); 1510 hubd.PortPowerCtrlMask[2] = (u_int8_t)(v >> 24); 1511 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + 2; 1512 } 1513 l = min(len, hubd.bDescLength); 1514 totlen = l; 1515 memcpy(buf, &hubd, l); 1516 break; 1517 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 1518 if (len != 4) { 1519 r = USBD_IOERROR; 1520 goto ret; 1521 } 1522 memset(buf, 0, len); /* ? XXX */ 1523 totlen = len; 1524 break; 1525 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 1526 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n", 1527 index)); 1528 if (index < 1 || index > sc->sc_noport) { 1529 r = USBD_IOERROR; 1530 goto ret; 1531 } 1532 if (len != 4) { 1533 r = USBD_IOERROR; 1534 goto ret; 1535 } 1536 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 1537 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n", 1538 v)); 1539 USETW(ps.wPortStatus, v); 1540 USETW(ps.wPortChange, v >> 16); 1541 l = min(len, sizeof ps); 1542 memcpy(buf, &ps, l); 1543 totlen = l; 1544 break; 1545 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 1546 r = USBD_IOERROR; 1547 goto ret; 1548 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 1549 break; 1550 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 1551 if (index < 1 || index > sc->sc_noport) { 1552 r = USBD_IOERROR; 1553 goto ret; 1554 } 1555 port = OHCI_RH_PORT_STATUS(index); 1556 switch(value) { 1557 case UHF_PORT_ENABLE: 1558 OWRITE4(sc, port, UPS_PORT_ENABLED); 1559 break; 1560 case UHF_PORT_SUSPEND: 1561 OWRITE4(sc, port, UPS_SUSPEND); 1562 break; 1563 case UHF_PORT_RESET: 1564 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n", index)); 1565 OWRITE4(sc, port, UPS_RESET); 1566 for (i = 0; i < 10; i++) { 1567 usbd_delay_ms(&sc->sc_bus, 10); 1568 if ((OREAD4(sc, port) & UPS_RESET) == 0) 1569 break; 1570 } 1571 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n", 1572 index, OREAD4(sc, port))); 1573 break; 1574 case UHF_PORT_POWER: 1575 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power %d\n", index)); 1576 OWRITE4(sc, port, UPS_PORT_POWER); 1577 break; 1578 default: 1579 r = USBD_IOERROR; 1580 goto ret; 1581 } 1582 break; 1583 default: 1584 r = USBD_IOERROR; 1585 goto ret; 1586 } 1587 reqh->actlen = totlen; 1588 r = USBD_NORMAL_COMPLETION; 1589 ret: 1590 reqh->status = r; 1591 reqh->xfercb(reqh); 1592 return (USBD_IN_PROGRESS); 1593 } 1594 1595 /* Abort a root control request. */ 1596 void 1597 ohci_root_ctrl_abort(reqh) 1598 usbd_request_handle reqh; 1599 { 1600 /* Nothing to do, all transfers are synchronous. */ 1601 } 1602 1603 /* Close the root pipe. */ 1604 void 1605 ohci_root_ctrl_close(pipe) 1606 usbd_pipe_handle pipe; 1607 { 1608 DPRINTF(("ohci_root_ctrl_close\n")); 1609 } 1610 1611 usbd_status 1612 ohci_root_intr_transfer(reqh) 1613 usbd_request_handle reqh; 1614 { 1615 usbd_pipe_handle pipe = reqh->pipe; 1616 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 1617 struct ohci_pipe *upipe = (struct ohci_pipe *)pipe; 1618 usb_dma_t *dmap; 1619 usbd_status r; 1620 int len; 1621 1622 len = reqh->length; 1623 dmap = &upipe->u.intr.datadma; 1624 if (len == 0) 1625 return (USBD_INVAL); /* XXX should it be? */ 1626 1627 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap); 1628 if (r != USBD_NORMAL_COMPLETION) 1629 return (r); 1630 sc->sc_intrreqh = reqh; 1631 1632 return (USBD_IN_PROGRESS); 1633 } 1634 1635 /* Abort a root interrupt request. */ 1636 void 1637 ohci_root_intr_abort(reqh) 1638 usbd_request_handle reqh; 1639 { 1640 /* No need to abort. */ 1641 } 1642 1643 /* Close the root pipe. */ 1644 void 1645 ohci_root_intr_close(pipe) 1646 usbd_pipe_handle pipe; 1647 { 1648 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 1649 sc->sc_intrreqh = 0; 1650 1651 DPRINTF(("ohci_root_intr_close\n")); 1652 } 1653 1654 /************************/ 1655 1656 usbd_status 1657 ohci_device_ctrl_transfer(reqh) 1658 usbd_request_handle reqh; 1659 { 1660 ohci_softc_t *sc = (ohci_softc_t *)reqh->pipe->device->bus; 1661 usbd_status r; 1662 1663 if (!reqh->isreq) { 1664 /* XXX panic */ 1665 printf("ohci_device_ctrl_transfer: not a request\n"); 1666 return (USBD_INVAL); 1667 } 1668 1669 r = ohci_device_request(reqh); 1670 if (r != USBD_NORMAL_COMPLETION) 1671 return (r); 1672 1673 if (sc->sc_bus.use_polling) 1674 ohci_waitintr(sc, reqh); 1675 return (USBD_IN_PROGRESS); 1676 } 1677 1678 /* Abort a device control request. */ 1679 void 1680 ohci_device_ctrl_abort(reqh) 1681 usbd_request_handle reqh; 1682 { 1683 /* XXX inactivate */ 1684 usbd_delay_ms(reqh->pipe->device->bus, 1); /* make sure it is finished */ 1685 /* XXX call done */ 1686 } 1687 1688 /* Close a device control pipe. */ 1689 void 1690 ohci_device_ctrl_close(pipe) 1691 usbd_pipe_handle pipe; 1692 { 1693 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 1694 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 1695 ohci_soft_ed_t *sed = opipe->sed; 1696 int s; 1697 1698 s = splusb(); 1699 sed->ed->ed_flags |= OHCI_ED_SKIP; 1700 if ((sed->ed->ed_tailp & OHCI_TAILMASK) != sed->ed->ed_headp) 1701 usbd_delay_ms(&sc->sc_bus, 2); 1702 ohci_rem_ed(sed, sc->sc_ctrl_head); 1703 splx(s); 1704 ohci_free_std(sc, opipe->tail); 1705 ohci_free_sed(sc, opipe->sed); 1706 /* XXX free other resources */ 1707 } 1708 1709 /************************/ 1710 1711 usbd_status 1712 ohci_device_bulk_transfer(reqh) 1713 usbd_request_handle reqh; 1714 { 1715 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 1716 usbd_device_handle dev = opipe->pipe.device; 1717 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 1718 int addr = dev->address; 1719 ohci_soft_td_t *xfer, *tail; 1720 ohci_soft_ed_t *sed; 1721 usb_dma_t *dmap; 1722 usbd_status r; 1723 int s, len, isread; 1724 1725 if (reqh->isreq) { 1726 /* XXX panic */ 1727 printf("ohci_device_bulk_transfer: a request\n"); 1728 return (USBD_INVAL); 1729 } 1730 1731 len = reqh->length; 1732 dmap = &opipe->u.bulk.datadma; 1733 isread = reqh->pipe->endpoint->edesc->bEndpointAddress & UE_IN; 1734 sed = opipe->sed; 1735 1736 opipe->u.bulk.length = len; 1737 1738 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap); 1739 if (r != USBD_NORMAL_COMPLETION) 1740 goto ret1; 1741 1742 tail = ohci_alloc_std(sc); 1743 if (!tail) { 1744 r = USBD_NOMEM; 1745 goto ret2; 1746 } 1747 tail->reqh = 0; 1748 1749 /* Update device address */ 1750 sed->ed->ed_flags = 1751 (sed->ed->ed_flags & ~OHCI_ED_ADDRMASK) | 1752 OHCI_ED_SET_FA(addr); 1753 1754 /* Set up data transaction */ 1755 xfer = opipe->tail; 1756 xfer->td->td_flags = 1757 (isread ? OHCI_TD_IN : OHCI_TD_OUT) | OHCI_TD_NOCC | 1758 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY; 1759 xfer->td->td_cbp = DMAADDR(dmap); 1760 xfer->nexttd = tail; 1761 xfer->td->td_nexttd = tail->physaddr; 1762 xfer->td->td_be = xfer->td->td_cbp + len - 1; 1763 xfer->len = len; 1764 xfer->reqh = reqh; 1765 1766 reqh->actlen = 0; 1767 reqh->hcpriv = xfer; 1768 1769 if (!isread) 1770 memcpy(KERNADDR(dmap), reqh->buffer, len); 1771 1772 /* Insert ED in schedule */ 1773 s = splusb(); 1774 ohci_hash_add_td(sc, xfer); 1775 sed->ed->ed_tailp = tail->physaddr; 1776 opipe->tail = tail; 1777 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 1778 if (reqh->timeout && !sc->sc_bus.use_polling) 1779 timeout(ohci_timeout, reqh, MS_TO_TICKS(reqh->timeout)); 1780 splx(s); 1781 1782 return (USBD_IN_PROGRESS); 1783 1784 ret2: 1785 usb_freemem(sc->sc_dmatag, dmap); 1786 ret1: 1787 return (r); 1788 } 1789 1790 /* Abort a device bulk request. */ 1791 void 1792 ohci_device_bulk_abort(reqh) 1793 usbd_request_handle reqh; 1794 { 1795 #if 0 1796 sed->ed->ed_flags |= OHCI_ED_SKIP; 1797 if ((sed->ed->ed_tailp & OHCI_TAILMASK) != sed->ed->ed_headp) 1798 usbd_delay_ms(reqh->pipe->device->bus, 2); 1799 #endif 1800 /* XXX inactivate */ 1801 usbd_delay_ms(reqh->pipe->device->bus, 1); /* make sure it is finished */ 1802 /* XXX call done */ 1803 } 1804 1805 /* Close a device bulk pipe. */ 1806 void 1807 ohci_device_bulk_close(pipe) 1808 usbd_pipe_handle pipe; 1809 { 1810 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 1811 usbd_device_handle dev = opipe->pipe.device; 1812 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 1813 int s; 1814 1815 s = splusb(); 1816 ohci_rem_ed(opipe->sed, sc->sc_bulk_head); 1817 splx(s); 1818 ohci_free_std(sc, opipe->tail); 1819 ohci_free_sed(sc, opipe->sed); 1820 /* XXX free other resources */ 1821 } 1822 1823 /************************/ 1824 1825 usbd_status 1826 ohci_device_intr_transfer(reqh) 1827 usbd_request_handle reqh; 1828 { 1829 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 1830 usbd_device_handle dev = opipe->pipe.device; 1831 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 1832 ohci_soft_ed_t *sed = opipe->sed; 1833 ohci_soft_td_t *xfer, *tail; 1834 usb_dma_t *dmap; 1835 usbd_status r; 1836 int len; 1837 int s; 1838 1839 DPRINTFN(3, ("ohci_device_intr_transfer: reqh=%p buf=%p len=%d flags=%d priv=%p\n", 1840 reqh, reqh->buffer, reqh->length, reqh->flags, reqh->priv)); 1841 1842 if (reqh->isreq) 1843 panic("ohci_device_intr_transfer: a request\n"); 1844 1845 len = reqh->length; 1846 dmap = &opipe->u.intr.datadma; 1847 if (len == 0) 1848 return (USBD_INVAL); /* XXX should it be? */ 1849 1850 xfer = opipe->tail; 1851 tail = ohci_alloc_std(sc); 1852 if (!tail) { 1853 r = USBD_NOMEM; 1854 goto ret1; 1855 } 1856 tail->reqh = 0; 1857 1858 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap); 1859 if (r != USBD_NORMAL_COMPLETION) 1860 goto ret2; 1861 1862 xfer->td->td_flags = OHCI_TD_IN | OHCI_TD_NOCC | 1863 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY; 1864 xfer->td->td_cbp = DMAADDR(dmap); 1865 xfer->nexttd = tail; 1866 xfer->td->td_nexttd = tail->physaddr; 1867 xfer->td->td_be = xfer->td->td_cbp + len - 1; 1868 xfer->len = len; 1869 xfer->reqh = reqh; 1870 1871 reqh->actlen = 0; 1872 reqh->hcpriv = xfer; 1873 1874 #if USB_DEBUG 1875 if (ohcidebug > 5) { 1876 printf("ohci_device_intr_transfer:\n"); 1877 ohci_dump_ed(sed); 1878 ohci_dump_tds(xfer); 1879 } 1880 #endif 1881 1882 /* Insert ED in schedule */ 1883 s = splusb(); 1884 ohci_hash_add_td(sc, xfer); 1885 sed->ed->ed_tailp = tail->physaddr; 1886 opipe->tail = tail; 1887 #if 0 1888 if (reqh->timeout && !sc->sc_bus.use_polling) 1889 timeout(ohci_timeout, reqh, MS_TO_TICKS(reqh->timeout)); 1890 #endif 1891 sed->ed->ed_flags &= ~OHCI_ED_SKIP; 1892 splx(s); 1893 1894 #ifdef USB_DEBUG 1895 if (ohcidebug > 5) { 1896 delay(5000); 1897 printf("ohci_device_intr_transfer: status=%x\n", 1898 OREAD4(sc, OHCI_COMMAND_STATUS)); 1899 ohci_dump_ed(sed); 1900 ohci_dump_tds(xfer); 1901 } 1902 #endif 1903 1904 return (USBD_IN_PROGRESS); 1905 1906 ret2: 1907 ohci_free_std(sc, xfer); 1908 ret1: 1909 return (r); 1910 } 1911 1912 /* Abort a device control request. */ 1913 void 1914 ohci_device_intr_abort(reqh) 1915 usbd_request_handle reqh; 1916 { 1917 /* XXX inactivate */ 1918 usbd_delay_ms(reqh->pipe->device->bus, 1); /* make sure it is finished */ 1919 if (reqh->pipe->intrreqh == reqh) { 1920 DPRINTF(("ohci_device_intr_abort: remove\n")); 1921 reqh->pipe->intrreqh = 0; 1922 ohci_intr_done((ohci_softc_t *)reqh->pipe->device->bus, reqh); 1923 } 1924 } 1925 1926 /* Close a device interrupt pipe. */ 1927 void 1928 ohci_device_intr_close(pipe) 1929 usbd_pipe_handle pipe; 1930 { 1931 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 1932 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 1933 int nslots = opipe->u.intr.nslots; 1934 int pos = opipe->u.intr.pos; 1935 int j; 1936 ohci_soft_ed_t *p, *sed = opipe->sed; 1937 int s; 1938 1939 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n", 1940 pipe, nslots, pos)); 1941 s = splusb(); 1942 sed->ed->ed_flags |= OHCI_ED_SKIP; 1943 if ((sed->ed->ed_tailp & OHCI_TAILMASK) != sed->ed->ed_headp) 1944 usbd_delay_ms(&sc->sc_bus, 2); 1945 1946 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 1947 ; 1948 if (!p) 1949 panic("ohci_device_intr_close: ED not found\n"); 1950 p->next = sed->next; 1951 p->ed->ed_nexted = sed->ed->ed_nexted; 1952 splx(s); 1953 1954 for (j = 0; j < nslots; j++) 1955 --sc->sc_bws[pos * nslots + j]; 1956 1957 ohci_free_std(sc, opipe->tail); 1958 ohci_free_sed(sc, opipe->sed); 1959 /* XXX free other resources */ 1960 } 1961 1962 usbd_status 1963 ohci_device_setintr(sc, opipe, ival) 1964 ohci_softc_t *sc; 1965 struct ohci_pipe *opipe; 1966 int ival; 1967 { 1968 int i, j, s, best; 1969 u_int npoll, slow, shigh, nslots; 1970 u_int bestbw, bw; 1971 ohci_soft_ed_t *hsed, *sed = opipe->sed; 1972 1973 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe)); 1974 if (ival == 0) { 1975 printf("ohci_setintr: 0 interval\n"); 1976 return (USBD_INVAL); 1977 } 1978 1979 npoll = OHCI_NO_INTRS; 1980 while (npoll > ival) 1981 npoll /= 2; 1982 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll)); 1983 1984 /* 1985 * We now know which level in the tree the ED must go into. 1986 * Figure out which slot has most bandwidth left over. 1987 * Slots to examine: 1988 * npoll 1989 * 1 0 1990 * 2 1 2 1991 * 4 3 4 5 6 1992 * 8 7 8 9 10 11 12 13 14 1993 * N (N-1) .. (N-1+N-1) 1994 */ 1995 slow = npoll-1; 1996 shigh = slow + npoll; 1997 nslots = OHCI_NO_INTRS / npoll; 1998 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 1999 bw = 0; 2000 for (j = 0; j < nslots; j++) 2001 bw += sc->sc_bws[i * nslots + j]; 2002 if (bw < bestbw) { 2003 best = i; 2004 bestbw = bw; 2005 } 2006 } 2007 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n", 2008 best, slow, shigh, bestbw)); 2009 2010 s = splusb(); 2011 hsed = sc->sc_eds[best]; 2012 sed->next = hsed->next; 2013 sed->ed->ed_nexted = hsed->ed->ed_nexted; 2014 hsed->next = sed; 2015 hsed->ed->ed_nexted = sed->physaddr; 2016 splx(s); 2017 2018 for (j = 0; j < nslots; j++) 2019 ++sc->sc_bws[best * nslots + j]; 2020 opipe->u.intr.nslots = nslots; 2021 opipe->u.intr.pos = best; 2022 2023 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe)); 2024 return (USBD_NORMAL_COMPLETION); 2025 } 2026 2027
Indexes created Tue Sep 23 14:10:03 GMT 2025