ohcireg.h revision 1.29
1 /* $NetBSD: ohcireg.h,v 1.29 2024/09/22 14:05:47 jmcneill Exp $ */ 2 /* $FreeBSD: src/sys/dev/usb/ohcireg.h,v 1.8 1999/11/17 22:33:40 n_hibma Exp $ */ 3 4 /* 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Lennart Augustsson (lennart (at) augustsson.net) at 10 * Carlstedt Research & Technology. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _DEV_USB_OHCIREG_H_ 35 #define _DEV_USB_OHCIREG_H_ 36 37 /*** PCI config registers ***/ 38 39 #define PCI_CBMEM 0x10 /* configuration base memory */ 40 41 #define PCI_INTERFACE_OHCI 0x10 42 43 /*** OHCI registers */ 44 45 #define OHCI_REVISION 0x00 /* OHCI revision # */ 46 #define OHCI_REV_LO_MASK __BITS(3,0) 47 #define OHCI_REV_HI_MASK __BITS(7,4) 48 #define OHCI_REV_LO(rev) __SHIFTOUT((rev), OHCI_REV_LO_MASK) 49 #define OHCI_REV_HI(rev) __SHIFTOUT((rev), OHCI_REV_HI_MASK) 50 #define OHCI_REV_LEGACY_MASK __BIT(8) 51 #define OHCI_REV_LEGACY(rev) __SHIFTOUT((rev), OHCI_REV_LEGACY_MASK) 52 53 #define OHCI_CONTROL 0x04 54 #define OHCI_CBSR_MASK __BITS(1,0) /* Control/Bulk Service Ratio */ 55 #define OHCI_CBSR_SET(x) __SHIFTIN((x), OHCI_CBSR_MASK) 56 #define OHCI_RATIO_1_1 0 57 #define OHCI_RATIO_1_2 1 58 #define OHCI_RATIO_1_3 2 59 #define OHCI_RATIO_1_4 3 60 #define OHCI_PLE __BIT(2) /* Periodic List Enable */ 61 #define OHCI_IE __BIT(3) /* Isochronous Enable */ 62 #define OHCI_CLE __BIT(4) /* Control List Enable */ 63 #define OHCI_BLE __BIT(5) /* Bulk List Enable */ 64 #define OHCI_HCFS_MASK __BITS(7,6) /* HostControllerFunctionalState */ 65 #define OHCI_SET_HCFS(x) __SHIFTIN((x), OHCI_HCFS_MASK) 66 #define OHCI_GET_HCFS(x) __SHIFTOUT((x), OHCI_HCFS_MASK) 67 #define OHCI_HCFS_RESET 0 68 #define OHCI_HCFS_RESUME 1 69 #define OHCI_HCFS_OPERATIONAL 2 70 #define OHCI_HCFS_SUSPEND 3 71 #define OHCI_IR __BIT(8) /* Interrupt Routing */ 72 #define OHCI_RWC __BIT(9) /* Remote Wakeup Connected */ 73 #define OHCI_RWE __BIT(10) /* Remote Wakeup Enabled */ 74 #define OHCI_COMMAND_STATUS 0x08 75 #define OHCI_HCR __BIT(0) /* Host Controller Reset */ 76 #define OHCI_CLF __BIT(1) /* Control List Filled */ 77 #define OHCI_BLF __BIT(2) /* Bulk List Filled */ 78 #define OHCI_OCR __BIT(3) /* Ownership Change Request */ 79 #define OHCI_SOC_MASK __BITS(17,16) /* Scheduling Overrun Count */ 80 #define OHCI_INTERRUPT_STATUS 0x0c 81 #define OHCI_SO __BIT(0) /* Scheduling Overrun */ 82 #define OHCI_WDH __BIT(1) /* Writeback Done Head */ 83 #define OHCI_SF __BIT(2) /* Start of Frame */ 84 #define OHCI_RD __BIT(3) /* Resume Detected */ 85 #define OHCI_UE __BIT(4) /* Unrecoverable Error */ 86 #define OHCI_FNO __BIT(5) /* Frame Number Overflow */ 87 #define OHCI_RHSC __BIT(6) /* Root Hub Status Change */ 88 #define OHCI_OC __BIT(30) /* Ownership Change */ 89 #define OHCI_MIE __BIT(31) /* Master Interrupt Enable */ 90 #define OHCI_INTERRUPT_ENABLE 0x10 91 #define OHCI_INTERRUPT_DISABLE 0x14 92 #define OHCI_HCCA 0x18 93 #define OHCI_PERIOD_CURRENT_ED 0x1c 94 #define OHCI_PERIOD_CURRENT_ED 0x1c 95 #define OHCI_CONTROL_HEAD_ED 0x20 96 #define OHCI_CONTROL_CURRENT_ED 0x24 97 #define OHCI_BULK_HEAD_ED 0x28 98 #define OHCI_BULK_CURRENT_ED 0x2c 99 #define OHCI_DONE_HEAD 0x30 100 #define OHCI_FM_INTERVAL 0x34 101 #define OHCI_FM_IVAL_MASK __BITS(13,0) 102 #define OHCI_FM_GET_IVAL(x) __SHIFTOUT((x), OHCI_FM_IVAL_MASK) 103 #define OHCI_FM_FSMPS_MASK __BITS(30,16) 104 #define OHCI_FM_GET_FSMPS(x) __SHIFTOUT((x), OHCI_FM_FSMPS_MASK) 105 #define OHCI_FM_SET_FSMPS(x) __SHIFTIN((x), OHCI_FM_FSMPS_MASK) 106 #define OHCI_FM_FIT __BIT(31) 107 #define OHCI_FM_REMAINING 0x38 108 #define OHCI_FM_NUMBER 0x3c 109 #define OHCI_PERIODIC_START 0x40 110 #define OHCI_LS_THRESHOLD 0x44 111 #define OHCI_RH_DESCRIPTOR_A 0x48 112 #define OHCI_RHD_NDP_MASK __BITS(7,0) 113 #define OHCI_RHD_GET_NDP(x) __SHIFTOUT((x), OHCI_RHD_NDP_MASK) 114 #define OHCI_RHD_PSM __BIT(8) /* Power Switching Mode */ 115 #define OHCI_RHD_NPS __BIT(9) /* No Power Switching */ 116 #define OHCI_RHD_DT __BIT(10) /* Device Type */ 117 #define OHCI_RHD_OCPM __BIT(11) /* Overcurrent Protection Mode */ 118 #define OHCI_RHD_NOCP __BIT(12) /* No Overcurrent Protection */ 119 #define OHCI_RHD_POTPGT_MASK __BITS(31,24) 120 #define OHCI_RHD_GET_POTPGT(x) __SHIFTOUT((x), OHCI_RHD_POTPGT_MASK) 121 #define OHCI_RHD_SET_POTPGT(x) __SHIFTIN((x), OHCI_RHD_POTPGT_MASK) 122 #define OHCI_RH_DESCRIPTOR_B 0x4c 123 #define OHCI_RH_STATUS 0x50 124 #define OHCI_RHS_LPS __BIT(0) /* Local Power Status */ 125 #define OHCI_RHS_OCI __BIT(1) /* OverCurrent Indicator */ 126 #define OHCI_RHS_DRWE __BIT(15) /* Device Remote Wakeup Enable */ 127 #define OHCI_RHS_LPSC __BIT(16) /* Local Power Status Change */ 128 #define OHCI_RHS_CCIC __BIT(17) /* OverCurrent Indicator Change */ 129 #define OHCI_RHS_CRWE __BIT(31) /* Clear Remote Wakeup Enable */ 130 #define OHCI_RH_PORT_STATUS(n) (0x50 + (n)*4) /* 1 based indexing */ 131 132 #define OHCI_LES (OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE) 133 #define OHCI_ALL_INTRS (OHCI_SO | OHCI_WDH | OHCI_SF | OHCI_RD | OHCI_UE | \ 134 OHCI_FNO | OHCI_RHSC | OHCI_OC) 135 #define OHCI_NORMAL_INTRS (OHCI_SO | OHCI_WDH | OHCI_RD | OHCI_UE | OHCI_RHSC) 136 137 #define OHCI_FSMPS(i) (((i-210)*6/7) << 16) 138 #define OHCI_PERIODIC(i) ((i)*9/10) 139 140 typedef uint32_t ohci_physaddr_t; 141 142 #define OHCI_NO_INTRS 32 143 struct ohci_hcca { 144 volatile ohci_physaddr_t hcca_interrupt_table[OHCI_NO_INTRS]; 145 volatile uint32_t hcca_frame_number; 146 volatile ohci_physaddr_t hcca_done_head; 147 #define OHCI_DONE_INTRS 1 148 }; 149 #define OHCI_HCCA_SIZE 256 150 #define OHCI_HCCA_ALIGN 256 151 152 #define OHCI_PAGE_SIZE 0x1000 153 #define OHCI_PAGE(x) ((x) &~ 0xfff) 154 #define OHCI_PAGE_OFFSET(x) ((x) & 0xfff) 155 156 typedef struct { 157 volatile uint32_t ed_flags; 158 #define OHCI_ED_ADDR_MASK __BITS(6,0) 159 #define OHCI_ED_GET_FA(x) __SHIFTOUT((x), OHCI_ED_ADDR_MASK) 160 #define OHCI_ED_SET_FA(x) __SHIFTIN((x), OHCI_ED_ADDR_MASK) 161 #define OHCI_ED_EN_MASK __BITS(10,7) 162 #define OHCI_ED_GET_EN(x) __SHIFTOUT((x), OHCI_ED_EN_MASK) 163 #define OHCI_ED_SET_EN(x) __SHIFTIN((x), OHCI_ED_EN_MASK) 164 #define OHCI_ED_DIR_MASK __BITS(12,11) 165 #define OHCI_ED_GET_DIR(x) __SHIFTOUT((x), OHCI_ED_DIR_MASK) 166 #define OHCI_ED_SET_DIR(x) __SHIFTIN((x), OHCI_ED_DIR_MASK) 167 #define OHCI_ED_DIR_TD 0 168 #define OHCI_ED_DIR_OUT 1 169 #define OHCI_ED_DIR_IN 2 170 #define OHCI_ED_SPEED __BIT(13) 171 #define OHCI_ED_SKIP __BIT(14) 172 #define OHCI_ED_FORMAT_MASK __BIT(15) 173 #define OHCI_ED_GET_FORMAT(x) __SHIFTOUT((x), OHCI_ED_FORMAT_MASK) 174 #define OHCI_ED_SET_FORMAT(x) __SHIFTIN((x), OHCI_ED_FORMAT_MASK) 175 #define OHCI_ED_FORMAT_GEN 0 176 #define OHCI_ED_FORMAT_ISO 1 177 #define OHCI_ED_MAXP_MASK __BITS(26,16) 178 #define OHCI_ED_GET_MAXP(x) __SHIFTOUT((x), OHCI_ED_MAXP_MASK) 179 #define OHCI_ED_SET_MAXP(x) __SHIFTIN((x), OHCI_ED_MAXP_MASK) 180 volatile ohci_physaddr_t ed_tailp; 181 volatile ohci_physaddr_t ed_headp; 182 #define OHCI_HALTED __BIT(0) 183 #define OHCI_TOGGLECARRY __BIT(1) 184 #define OHCI_HEADMASK __BITS(31,2) 185 volatile ohci_physaddr_t ed_nexted; 186 } ohci_ed_t; 187 /* #define OHCI_ED_SIZE 16 */ 188 #define OHCI_ED_ALIGN 16 189 #define OHCI_ED_ALLOC_ALIGN MAX(OHCI_ED_ALIGN, CACHE_LINE_SIZE) 190 #define OHCI_ED_SIZE (roundup(sizeof(ohci_ed_t), OHCI_ED_ALLOC_ALIGN)) 191 #define OHCI_ED_CHUNK (PAGE_SIZE / OHCI_ED_SIZE) 192 193 194 typedef struct { 195 volatile uint32_t td_flags; 196 #define OHCI_TD_R __BIT(18) /* Buffer Rounding */ 197 #define OHCI_TD_DP_MASK __BITS(20,19) /* Direction / PID */ 198 #define OHCI_TD_GET_DP(x) __SHIFTOUT((x), OHCI_TD_DP_MASK) 199 #define OHCI_TD_SET_DP(x) __SHIFTIN((x), OHCI_TD_DP_MASK) 200 #define OHCI_TD_DP_SETUP 0 201 #define OHCI_TD_DP_OUT 1 202 #define OHCI_TD_DP_IN 2 203 #define OHCI_TD_DI_MASK __BITS(23,21) /* Delay Interrupt */ 204 #define OHCI_TD_GET_DI(x) __SHIFTOUT((x), OHCI_TD_DI_MASK) 205 #define OHCI_TD_SET_DI(x) __SHIFTIN((x), OHCI_TD_DI_MASK) 206 #define OHCI_TD_NOINTR __SHIFTOUT_MASK(OHCI_TD_DI_MASK) 207 #define OHCI_TD_TOGGLE_MASK __BITS(25,24) /* Toggle */ 208 #define OHCI_TD_GET_TOGGLE(x) __SHIFTOUT((x), OHCI_TD_TOGGLE_MASK) 209 #define OHCI_TD_SET_TOGGLE(x) __SHIFTIN((x), OHCI_TD_TOGGLE_MASK) 210 #define OHCI_TD_TOGGLE_CARRY 0 211 #define OHCI_TD_TOGGLE_0 2 212 #define OHCI_TD_TOGGLE_1 3 213 #define OHCI_TD_EC_MASK __BITS(27,26) /* Error Count */ 214 #define OHCI_TD_GET_EC(x) __SHIFTOUT((x), OHCI_TD_EC_MASK) 215 #define OHCI_TD_CC_MASK __BITS(31,28) /* Condition Code */ 216 #define OHCI_TD_GET_CC(x) __SHIFTOUT((x), OHCI_TD_CC_MASK) 217 #define OHCI_TD_SET_CC(x) __SHIFTIN((x), OHCI_TD_CC_MASK) 218 219 #define OHCI_TD_NOCC __SHIFTOUT_MASK(OHCI_TD_CC_MASK) 220 221 volatile ohci_physaddr_t td_cbp; /* Current Buffer Pointer */ 222 volatile ohci_physaddr_t td_nexttd; /* Next TD */ 223 volatile ohci_physaddr_t td_be; /* Buffer End */ 224 } ohci_td_t; 225 /* #define OHCI_TD_SIZE 16 */ 226 #define OHCI_TD_ALIGN 16 227 #define OHCI_TD_ALLOC_ALIGN MAX(OHCI_TD_ALIGN, CACHE_LINE_SIZE) 228 #define OHCI_TD_SIZE (roundup(sizeof(ohci_td_t), OHCI_TD_ALLOC_ALIGN)) 229 #define OHCI_TD_CHUNK (PAGE_SIZE / OHCI_TD_SIZE) 230 231 232 #define OHCI_ITD_NOFFSET 8 233 typedef struct { 234 volatile uint32_t itd_flags; 235 #define OHCI_ITD_SF_MASK __BITS(15,0) 236 #define OHCI_ITD_GET_SF(x) __SHIFTOUT((x), OHCI_ITD_SF_MASK) 237 #define OHCI_ITD_SET_SF(x) __SHIFTIN((x), OHCI_ITD_SF_MASK) 238 #define OHCI_ITD_DI_MASK __BITS(23,21) /* Delay Interrupt */ 239 #define OHCI_ITD_GET_DI(x) __SHIFTOUT((x), OHCI_ITD_DI_MASK) 240 #define OHCI_ITD_SET_DI(x) __SHIFTIN((x), OHCI_ITD_DI_MASK) 241 #define OHCI_ITD_FC_MASK __BITS(26,24) /* Frame Count */ 242 #define OHCI_ITD_GET_FC(x) (__SHIFTOUT((x), OHCI_ITD_FC_MASK) + 1) 243 #define OHCI_ITD_SET_FC(x) __SHIFTIN(((x) - 1), OHCI_ITD_FC_MASK) 244 #define OHCI_ITD_CC_MASK __BITS(31,28) /* Condition Code */ 245 #define OHCI_ITD_GET_CC(x) __SHIFTOUT((x), OHCI_ITD_CC_MASK) 246 #define OHCI_ITD_SET_CC(x) __SHIFTIN((x), OHCI_ITD_CC_MASK) 247 #define OHCI_ITD_NOCC __SHIFTOUT_MASK(OHCI_ITD_CC_MASK) 248 volatile ohci_physaddr_t itd_bp0; /* Buffer Page 0 */ 249 volatile ohci_physaddr_t itd_nextitd; /* Next ITD */ 250 volatile ohci_physaddr_t itd_be; /* Buffer End */ 251 volatile uint16_t itd_offset[OHCI_ITD_NOFFSET];/* Buffer offsets */ 252 #define itd_pswn itd_offset /* Packet Status Word*/ 253 #define OHCI_ITD_PAGE_SELECT __BIT(12) 254 #define OHCI_ITD_MK_OFFS(len) (0xe000 | ((len) & 0x1fff)) 255 256 #define OHCI_ITD_PSW_SIZE_MASK __BITS(10,0) /* Transfer length */ 257 #define OHCI_ITD_PSW_SIZE(x) __SHIFTOUT((x), OHCI_ITD_PSW_SIZE_MASK) 258 #define OHCI_ITD_PSW_CC_MASK __BITS(15,12) /* Condition Code */ 259 #define OHCI_ITD_PSW_GET_CC(x) __SHIFTOUT((x), OHCI_ITD_PSW_CC_MASK) 260 } ohci_itd_t; 261 /* #define OHCI_ITD_SIZE 32 */ 262 #define OHCI_ITD_ALIGN 32 263 #define OHCI_ITD_ALLOC_ALIGN MAX(OHCI_ITD_ALIGN, CACHE_LINE_SIZE) 264 #define OHCI_ITD_SIZE (roundup(sizeof(ohci_itd_t), OHCI_ITD_ALLOC_ALIGN)) 265 #define OHCI_ITD_CHUNK (PAGE_SIZE / OHCI_ITD_SIZE) 266 267 268 #define OHCI_CC_NO_ERROR 0 269 #define OHCI_CC_CRC 1 270 #define OHCI_CC_BIT_STUFFING 2 271 #define OHCI_CC_DATA_TOGGLE_MISMATCH 3 272 #define OHCI_CC_STALL 4 273 #define OHCI_CC_DEVICE_NOT_RESPONDING 5 274 #define OHCI_CC_PID_CHECK_FAILURE 6 275 #define OHCI_CC_UNEXPECTED_PID 7 276 #define OHCI_CC_DATA_OVERRUN 8 277 #define OHCI_CC_DATA_UNDERRUN 9 278 #define OHCI_CC_BUFFER_OVERRUN 12 279 #define OHCI_CC_BUFFER_UNDERRUN 13 280 #define OHCI_CC_NOT_ACCESSED 14 281 #define OHCI_CC_NOT_ACCESSED_MASK 14 282 283 /* Some delay needed when changing certain registers. */ 284 #define OHCI_ENABLE_POWER_DELAY 5 285 #define OHCI_READ_DESC_DELAY 5 286 287 #endif /* _DEV_USB_OHCIREG_H_ */ 288
Indexes created Mon Sep 29 21:09:56 GMT 2025