uftdireg.h revision 1.12 1 1.12 andvar /* $NetBSD: uftdireg.h,v 1.12 2024/01/14 12:53:41 andvar Exp $ */
2 1.2 jhawk
3 1.1 augustss /*
4 1.6 augustss * Definitions for the FTDI USB Single Port Serial Converter -
5 1.6 augustss * known as FTDI_SIO (Serial Input/Output application of the chipset)
6 1.1 augustss *
7 1.6 augustss * The device is based on the FTDI FT8U100AX chip. It has a DB25 on one side,
8 1.1 augustss * USB on the other.
9 1.1 augustss *
10 1.9 rjs * Thanx to FTDI (http://www.ftdichip.com) for so kindly providing details
11 1.12 andvar * of the protocol required to talk to the device and ongoing assistance
12 1.1 augustss * during development.
13 1.1 augustss *
14 1.1 augustss * Bill Ryder - bryder (at) sgi.com of Silicon Graphics, Inc. is the original
15 1.1 augustss * author of this file.
16 1.1 augustss */
17 1.1 augustss /* Modified by Lennart Augustsson */
18 1.1 augustss
19 1.1 augustss /* Vendor Request Interface */
20 1.8 mlelstv #define FTDI_SIO_RESET 0 /* Reset the port */
21 1.8 mlelstv #define FTDI_SIO_MODEM_CTRL 1 /* Set the modem control register */
22 1.8 mlelstv #define FTDI_SIO_SET_FLOW_CTRL 2 /* Set flow control register */
23 1.8 mlelstv #define FTDI_SIO_SET_BAUD_RATE 3 /* Set baud rate */
24 1.8 mlelstv #define FTDI_SIO_SET_DATA 4 /* Set the data characteristics of the port */
25 1.8 mlelstv #define FTDI_SIO_GET_STATUS 5 /* Retrieve current value of status reg */
26 1.8 mlelstv #define FTDI_SIO_SET_EVENT_CHAR 6 /* Set the event character */
27 1.8 mlelstv #define FTDI_SIO_SET_ERROR_CHAR 7 /* Set the error character */
28 1.8 mlelstv #define FTDI_SIO_SET_BITMODE 11 /* Set FIFO/Serial mode */
29 1.1 augustss
30 1.1 augustss /* Port Identifier Table */
31 1.1 augustss #define FTDI_PIT_DEFAULT 0 /* SIOA */
32 1.1 augustss #define FTDI_PIT_SIOA 1 /* SIOA */
33 1.1 augustss #define FTDI_PIT_SIOB 2 /* SIOB */
34 1.1 augustss #define FTDI_PIT_PARALLEL 3 /* Parallel */
35 1.1 augustss
36 1.5 scw enum uftdi_type {
37 1.5 scw UFTDI_TYPE_SIO,
38 1.5 scw UFTDI_TYPE_8U232AM
39 1.5 scw };
40 1.5 scw
41 1.1 augustss /*
42 1.1 augustss * BmRequestType: 0100 0000B
43 1.1 augustss * bRequest: FTDI_SIO_RESET
44 1.6 augustss * wValue: Control Value
45 1.1 augustss * 0 = Reset SIO
46 1.1 augustss * 1 = Purge RX buffer
47 1.1 augustss * 2 = Purge TX buffer
48 1.1 augustss * wIndex: Port
49 1.1 augustss * wLength: 0
50 1.1 augustss * Data: None
51 1.1 augustss *
52 1.1 augustss * The Reset SIO command has this effect:
53 1.1 augustss *
54 1.1 augustss * Sets flow control set to 'none'
55 1.1 augustss * Event char = 0x0d
56 1.1 augustss * Event trigger = disabled
57 1.1 augustss * Purge RX buffer
58 1.1 augustss * Purge TX buffer
59 1.1 augustss * Clear DTR
60 1.1 augustss * Clear RTS
61 1.1 augustss * baud and data format not reset
62 1.1 augustss *
63 1.1 augustss * The Purge RX and TX buffer commands affect nothing except the buffers
64 1.1 augustss *
65 1.1 augustss */
66 1.1 augustss /* FTDI_SIO_RESET */
67 1.1 augustss #define FTDI_SIO_RESET_SIO 0
68 1.1 augustss #define FTDI_SIO_RESET_PURGE_RX 1
69 1.1 augustss #define FTDI_SIO_RESET_PURGE_TX 2
70 1.1 augustss
71 1.1 augustss
72 1.1 augustss /*
73 1.1 augustss * BmRequestType: 0100 0000B
74 1.1 augustss * bRequest: FTDI_SIO_SET_BAUDRATE
75 1.1 augustss * wValue: BaudRate value - see below
76 1.1 augustss * wIndex: Port
77 1.1 augustss * wLength: 0
78 1.1 augustss * Data: None
79 1.1 augustss */
80 1.1 augustss /* FTDI_SIO_SET_BAUDRATE */
81 1.1 augustss enum {
82 1.6 augustss ftdi_sio_b300 = 0,
83 1.6 augustss ftdi_sio_b600 = 1,
84 1.1 augustss ftdi_sio_b1200 = 2,
85 1.1 augustss ftdi_sio_b2400 = 3,
86 1.1 augustss ftdi_sio_b4800 = 4,
87 1.1 augustss ftdi_sio_b9600 = 5,
88 1.1 augustss ftdi_sio_b19200 = 6,
89 1.1 augustss ftdi_sio_b38400 = 7,
90 1.1 augustss ftdi_sio_b57600 = 8,
91 1.1 augustss ftdi_sio_b115200 = 9
92 1.1 augustss };
93 1.1 augustss
94 1.1 augustss /*
95 1.6 augustss * BmRequestType: 0100 0000B
96 1.1 augustss * bRequest: FTDI_SIO_SET_DATA
97 1.1 augustss * wValue: Data characteristics (see below)
98 1.1 augustss * wIndex: Port
99 1.1 augustss * wLength: 0
100 1.1 augustss * Data: No
101 1.1 augustss *
102 1.1 augustss * Data characteristics
103 1.1 augustss *
104 1.1 augustss * B0..7 Number of data bits
105 1.1 augustss * B8..10 Parity
106 1.1 augustss * 0 = None
107 1.1 augustss * 1 = Odd
108 1.1 augustss * 2 = Even
109 1.1 augustss * 3 = Mark
110 1.1 augustss * 4 = Space
111 1.1 augustss * B11..13 Stop Bits
112 1.1 augustss * 0 = 1
113 1.1 augustss * 1 = 1.5
114 1.1 augustss * 2 = 2
115 1.1 augustss * B14..15 Reserved
116 1.1 augustss *
117 1.1 augustss */
118 1.1 augustss /* FTDI_SIO_SET_DATA */
119 1.1 augustss #define FTDI_SIO_SET_DATA_BITS(n) (n)
120 1.1 augustss #define FTDI_SIO_SET_DATA_PARITY_NONE (0x0 << 8)
121 1.1 augustss #define FTDI_SIO_SET_DATA_PARITY_ODD (0x1 << 8)
122 1.1 augustss #define FTDI_SIO_SET_DATA_PARITY_EVEN (0x2 << 8)
123 1.1 augustss #define FTDI_SIO_SET_DATA_PARITY_MARK (0x3 << 8)
124 1.1 augustss #define FTDI_SIO_SET_DATA_PARITY_SPACE (0x4 << 8)
125 1.1 augustss #define FTDI_SIO_SET_DATA_STOP_BITS_1 (0x0 << 11)
126 1.1 augustss #define FTDI_SIO_SET_DATA_STOP_BITS_15 (0x1 << 11)
127 1.1 augustss #define FTDI_SIO_SET_DATA_STOP_BITS_2 (0x2 << 11)
128 1.4 ichiro #define FTDI_SIO_SET_BREAK (0x1 << 14)
129 1.1 augustss
130 1.1 augustss
131 1.6 augustss /*
132 1.1 augustss * BmRequestType: 0100 0000B
133 1.1 augustss * bRequest: FTDI_SIO_MODEM_CTRL
134 1.1 augustss * wValue: ControlValue (see below)
135 1.1 augustss * wIndex: Port
136 1.1 augustss * wLength: 0
137 1.1 augustss * Data: None
138 1.1 augustss *
139 1.1 augustss * NOTE: If the device is in RTS/CTS flow control, the RTS set by this
140 1.1 augustss * command will be IGNORED without an error being returned
141 1.1 augustss * Also - you can not set DTR and RTS with one control message
142 1.1 augustss *
143 1.1 augustss * ControlValue
144 1.1 augustss * B0 DTR state
145 1.1 augustss * 0 = reset
146 1.1 augustss * 1 = set
147 1.1 augustss * B1 RTS state
148 1.1 augustss * 0 = reset
149 1.1 augustss * 1 = set
150 1.1 augustss * B2..7 Reserved
151 1.1 augustss * B8 DTR state enable
152 1.1 augustss * 0 = ignore
153 1.1 augustss * 1 = use DTR state
154 1.1 augustss * B9 RTS state enable
155 1.1 augustss * 0 = ignore
156 1.1 augustss * 1 = use RTS state
157 1.1 augustss * B10..15 Reserved
158 1.1 augustss */
159 1.1 augustss /* FTDI_SIO_MODEM_CTRL */
160 1.1 augustss #define FTDI_SIO_SET_DTR_MASK 0x1
161 1.1 augustss #define FTDI_SIO_SET_DTR_HIGH (1 | ( FTDI_SIO_SET_DTR_MASK << 8))
162 1.1 augustss #define FTDI_SIO_SET_DTR_LOW (0 | ( FTDI_SIO_SET_DTR_MASK << 8))
163 1.1 augustss #define FTDI_SIO_SET_RTS_MASK 0x2
164 1.1 augustss #define FTDI_SIO_SET_RTS_HIGH (2 | ( FTDI_SIO_SET_RTS_MASK << 8))
165 1.1 augustss #define FTDI_SIO_SET_RTS_LOW (0 | ( FTDI_SIO_SET_RTS_MASK << 8))
166 1.1 augustss
167 1.1 augustss
168 1.1 augustss /*
169 1.1 augustss * BmRequestType: 0100 0000b
170 1.1 augustss * bRequest: FTDI_SIO_SET_FLOW_CTRL
171 1.1 augustss * wValue: Xoff/Xon
172 1.7 msaitoh * wIndex: Protocol/Port - hIndex is protocol / lIndex is port
173 1.6 augustss * wLength: 0
174 1.1 augustss * Data: None
175 1.1 augustss *
176 1.1 augustss * hIndex protocol is:
177 1.1 augustss * B0 Output handshaking using RTS/CTS
178 1.1 augustss * 0 = disabled
179 1.1 augustss * 1 = enabled
180 1.1 augustss * B1 Output handshaking using DTR/DSR
181 1.1 augustss * 0 = disabled
182 1.1 augustss * 1 = enabled
183 1.1 augustss * B2 Xon/Xoff handshaking
184 1.1 augustss * 0 = disabled
185 1.1 augustss * 1 = enabled
186 1.1 augustss *
187 1.1 augustss * A value of zero in the hIndex field disables handshaking
188 1.1 augustss *
189 1.1 augustss * If Xon/Xoff handshaking is specified, the hValue field should contain the
190 1.1 augustss * XOFF character and the lValue field contains the XON character.
191 1.6 augustss */
192 1.1 augustss /* FTDI_SIO_SET_FLOW_CTRL */
193 1.6 augustss #define FTDI_SIO_DISABLE_FLOW_CTRL 0x0
194 1.1 augustss #define FTDI_SIO_RTS_CTS_HS 0x1
195 1.1 augustss #define FTDI_SIO_DTR_DSR_HS 0x2
196 1.1 augustss #define FTDI_SIO_XON_XOFF_HS 0x4
197 1.1 augustss
198 1.6 augustss
199 1.6 augustss /*
200 1.1 augustss * BmRequestType: 0100 0000b
201 1.1 augustss * bRequest: FTDI_SIO_SET_EVENT_CHAR
202 1.1 augustss * wValue: Event Char
203 1.1 augustss * wIndex: Port
204 1.1 augustss * wLength: 0
205 1.1 augustss * Data: None
206 1.1 augustss *
207 1.1 augustss * wValue:
208 1.1 augustss * B0..7 Event Character
209 1.1 augustss * B8 Event Character Processing
210 1.1 augustss * 0 = disabled
211 1.1 augustss * 1 = enabled
212 1.1 augustss * B9..15 Reserved
213 1.1 augustss *
214 1.6 augustss * FTDI_SIO_SET_EVENT_CHAR
215 1.1 augustss *
216 1.1 augustss * Set the special event character for the specified communications port.
217 1.1 augustss * If the device sees this character it will immediately return the
218 1.1 augustss * data read so far - rather than wait 40ms or until 62 bytes are read
219 1.1 augustss * which is what normally happens.
220 1.1 augustss */
221 1.1 augustss
222 1.1 augustss
223 1.6 augustss
224 1.6 augustss /*
225 1.1 augustss * BmRequestType: 0100 0000b
226 1.1 augustss * bRequest: FTDI_SIO_SET_ERROR_CHAR
227 1.1 augustss * wValue: Error Char
228 1.1 augustss * wIndex: Port
229 1.1 augustss * wLength: 0
230 1.1 augustss * Data: None
231 1.1 augustss *
232 1.1 augustss * Error Char
233 1.1 augustss * B0..7 Error Character
234 1.1 augustss * B8 Error Character Processing
235 1.1 augustss * 0 = disabled
236 1.1 augustss * 1 = enabled
237 1.1 augustss * B9..15 Reserved
238 1.1 augustss *
239 1.1 augustss *
240 1.1 augustss * FTDI_SIO_SET_ERROR_CHAR
241 1.1 augustss * Set the parity error replacement character for the specified communications
242 1.1 augustss * port.
243 1.1 augustss */
244 1.1 augustss
245 1.1 augustss
246 1.6 augustss /*
247 1.1 augustss * BmRequestType: 1100 0000b
248 1.1 augustss * bRequest: FTDI_SIO_GET_MODEM_STATUS
249 1.1 augustss * wValue: zero
250 1.1 augustss * wIndex: Port
251 1.1 augustss * wLength: 1
252 1.1 augustss * Data: Status
253 1.6 augustss *
254 1.6 augustss * One byte of data is returned
255 1.1 augustss * B0..3 0
256 1.1 augustss * B4 CTS
257 1.1 augustss * 0 = inactive
258 1.1 augustss * 1 = active
259 1.1 augustss * B5 DSR
260 1.1 augustss * 0 = inactive
261 1.1 augustss * 1 = active
262 1.1 augustss * B6 Ring Indicator (RI)
263 1.1 augustss * 0 = inactive
264 1.1 augustss * 1 = active
265 1.1 augustss * B7 Receive Line Signal Detect (RLSD)
266 1.1 augustss * 0 = inactive
267 1.6 augustss * 1 = active
268 1.1 augustss *
269 1.1 augustss * FTDI_SIO_GET_MODEM_STATUS
270 1.3 wiz * Retrieve the current value of the modem status register.
271 1.1 augustss */
272 1.1 augustss #define FTDI_SIO_CTS_MASK 0x10
273 1.1 augustss #define FTDI_SIO_DSR_MASK 0x20
274 1.1 augustss #define FTDI_SIO_RI_MASK 0x40
275 1.1 augustss #define FTDI_SIO_RLSD_MASK 0x80
276 1.1 augustss
277 1.1 augustss
278 1.1 augustss
279 1.1 augustss /*
280 1.6 augustss *
281 1.1 augustss * DATA FORMAT
282 1.6 augustss *
283 1.1 augustss * IN Endpoint
284 1.6 augustss *
285 1.1 augustss * The device reserves the first two bytes of data on this endpoint to contain
286 1.1 augustss * the current values of the modem and line status registers. In the absence of
287 1.1 augustss * data, the device generates a message consisting of these two status bytes
288 1.1 augustss * every 40 ms.
289 1.6 augustss *
290 1.1 augustss * Byte 0: Modem Status
291 1.1 augustss * NOTE: 4 upper bits have same layout as the MSR register in a 16550
292 1.6 augustss *
293 1.1 augustss * Offset Description
294 1.1 augustss * B0..3 Port
295 1.1 augustss * B4 Clear to Send (CTS)
296 1.1 augustss * B5 Data Set Ready (DSR)
297 1.1 augustss * B6 Ring Indicator (RI)
298 1.1 augustss * B7 Receive Line Signal Detect (RLSD)
299 1.6 augustss *
300 1.1 augustss * Byte 1: Line Status
301 1.1 augustss * NOTE: same layout as the LSR register in a 16550
302 1.6 augustss *
303 1.1 augustss * Offset Description
304 1.1 augustss * B0 Data Ready (DR)
305 1.1 augustss * B1 Overrun Error (OE)
306 1.1 augustss * B2 Parity Error (PE)
307 1.1 augustss * B3 Framing Error (FE)
308 1.1 augustss * B4 Break Interrupt (BI)
309 1.1 augustss * B5 Transmitter Holding Register (THRE)
310 1.1 augustss * B6 Transmitter Empty (TEMT)
311 1.1 augustss * B7 Error in RCVR FIFO
312 1.1 augustss *
313 1.1 augustss *
314 1.1 augustss * OUT Endpoint
315 1.6 augustss *
316 1.1 augustss * This device reserves the first bytes of data on this endpoint contain the
317 1.1 augustss * length and port identifier of the message. For the FTDI USB Serial converter
318 1.1 augustss * the port identifier is always 1.
319 1.6 augustss *
320 1.1 augustss * Byte 0: Port & length
321 1.6 augustss *
322 1.1 augustss * Offset Description
323 1.1 augustss * B0..1 Port
324 1.1 augustss * B2..7 Length of message - (not including Byte 0)
325 1.6 augustss *
326 1.1 augustss */
327 1.1 augustss #define FTDI_PORT_MASK 0x0f
328 1.1 augustss #define FTDI_MSR_MASK 0xf0
329 1.1 augustss #define FTDI_GET_MSR(p) (((p)[0]) & FTDI_MSR_MASK)
330 1.1 augustss #define FTDI_GET_LSR(p) ((p)[1])
331 1.1 augustss #define FTDI_LSR_MASK (~0x60) /* interesting bits */
332 1.1 augustss #define FTDI_OUT_TAG(len, port) (((len) << 2) | (port))
333 1.8 mlelstv
334 1.8 mlelstv /*
335 1.8 mlelstv * BmRequestType: 0100 0000B
336 1.8 mlelstv * bRequest: FTDI_SIO_SET_BITMODE
337 1.8 mlelstv * wValue: Bitmode value - see below
338 1.8 mlelstv * wIndex: Port
339 1.8 mlelstv * wLength: 0
340 1.8 mlelstv * Data: None
341 1.8 mlelstv *
342 1.8 mlelstv * Not all modes are available on all chips
343 1.8 mlelstv */
344 1.8 mlelstv /* FTDI_SIO_SET_BITMODE */
345 1.8 mlelstv #define FTDI_BITMODE_RESET 0x00 /* UART mode */
346 1.12 andvar #define FTDI_BITMODE_BITBANG 0x01 /* asynchronous bitbang mode */
347 1.8 mlelstv #define FTDI_BITMODE_MPSSE 0x02 /* MPSSE mode */
348 1.8 mlelstv #define FTDI_BITMODE_SYNCBB 0x04 /* synchronous bitbang mode */
349 1.8 mlelstv #define FTDI_BITMODE_MCU 0x08 /* MCU Host Bus Emulation mode */
350 1.8 mlelstv #define FTDI_BITMODE_OPTO 0x10 /* Fast Opto-Isolated Serial Interface Mode */
351 1.8 mlelstv #define FTDI_BITMODE_CBUS 0x20 /* Bitbang on CBUS pins */
352 1.8 mlelstv #define FTDI_BITMODE_SYNCFF 0x40 /* Synchronous FIFO mode */
353 1.8 mlelstv
354