uhci.c revision 1.264.4.17 1 1.264.4.17 skrll /* $NetBSD: uhci.c,v 1.264.4.17 2015/02/01 11:13:46 skrll Exp $ */
2 1.1 augustss
3 1.1 augustss /*
4 1.248 mrg * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc.
5 1.1 augustss * All rights reserved.
6 1.1 augustss *
7 1.11 augustss * This code is derived from software contributed to The NetBSD Foundation
8 1.113 augustss * by Lennart Augustsson (lennart (at) augustsson.net) at
9 1.248 mrg * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca)
10 1.248 mrg * and Matthew R. Green (mrg (at) eterna.com.au).
11 1.1 augustss *
12 1.1 augustss * Redistribution and use in source and binary forms, with or without
13 1.1 augustss * modification, are permitted provided that the following conditions
14 1.1 augustss * are met:
15 1.1 augustss * 1. Redistributions of source code must retain the above copyright
16 1.1 augustss * notice, this list of conditions and the following disclaimer.
17 1.1 augustss * 2. Redistributions in binary form must reproduce the above copyright
18 1.1 augustss * notice, this list of conditions and the following disclaimer in the
19 1.1 augustss * documentation and/or other materials provided with the distribution.
20 1.1 augustss *
21 1.1 augustss * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22 1.1 augustss * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 1.1 augustss * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 1.1 augustss * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25 1.1 augustss * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 1.1 augustss * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 1.1 augustss * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 1.1 augustss * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 1.1 augustss * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 1.1 augustss * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 1.1 augustss * POSSIBILITY OF SUCH DAMAGE.
32 1.1 augustss */
33 1.1 augustss
34 1.1 augustss /*
35 1.1 augustss * USB Universal Host Controller driver.
36 1.28 augustss * Handles e.g. PIIX3 and PIIX4.
37 1.1 augustss *
38 1.229 uebayasi * UHCI spec: http://www.intel.com/technology/usb/spec.htm
39 1.229 uebayasi * USB spec: http://www.usb.org/developers/docs/
40 1.71 augustss * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf
41 1.71 augustss * ftp://download.intel.com/design/intarch/datashts/29056201.pdf
42 1.1 augustss */
43 1.143 lukem
44 1.143 lukem #include <sys/cdefs.h>
45 1.264.4.17 skrll __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.264.4.17 2015/02/01 11:13:46 skrll Exp $");
46 1.1 augustss
47 1.1 augustss #include <sys/param.h>
48 1.1 augustss #include <sys/systm.h>
49 1.1 augustss #include <sys/kernel.h>
50 1.248 mrg #include <sys/kmem.h>
51 1.1 augustss #include <sys/device.h>
52 1.67 augustss #include <sys/select.h>
53 1.183 fvdl #include <sys/extent.h>
54 1.1 augustss #include <sys/proc.h>
55 1.1 augustss #include <sys/queue.h>
56 1.211 ad #include <sys/bus.h>
57 1.247 mrg #include <sys/cpu.h>
58 1.1 augustss
59 1.39 augustss #include <machine/endian.h>
60 1.7 augustss
61 1.1 augustss #include <dev/usb/usb.h>
62 1.1 augustss #include <dev/usb/usbdi.h>
63 1.1 augustss #include <dev/usb/usbdivar.h>
64 1.7 augustss #include <dev/usb/usb_mem.h>
65 1.1 augustss #include <dev/usb/usb_quirks.h>
66 1.1 augustss
67 1.1 augustss #include <dev/usb/uhcireg.h>
68 1.1 augustss #include <dev/usb/uhcivar.h>
69 1.264.4.11 skrll #include <dev/usb/usbroothub.h>
70 1.1 augustss
71 1.125 augustss /* Use bandwidth reclamation for control transfers. Some devices choke on it. */
72 1.125 augustss /*#define UHCI_CTL_LOOP */
73 1.125 augustss
74 1.13 augustss
75 1.37 augustss
76 1.67 augustss #ifdef UHCI_DEBUG
77 1.92 augustss uhci_softc_t *thesc;
78 1.59 augustss #define DPRINTF(x) if (uhcidebug) printf x
79 1.59 augustss #define DPRINTFN(n,x) if (uhcidebug>(n)) printf x
80 1.67 augustss int uhcidebug = 0;
81 1.125 augustss int uhcinoloop = 0;
82 1.59 augustss #else
83 1.59 augustss #define DPRINTF(x)
84 1.59 augustss #define DPRINTFN(n,x)
85 1.59 augustss #endif
86 1.59 augustss
87 1.39 augustss /*
88 1.39 augustss * The UHCI controller is little endian, so on big endian machines
89 1.181 drochner * the data stored in memory needs to be swapped.
90 1.39 augustss */
91 1.39 augustss
92 1.1 augustss struct uhci_pipe {
93 1.1 augustss struct usbd_pipe pipe;
94 1.32 augustss int nexttoggle;
95 1.92 augustss
96 1.92 augustss u_char aborting;
97 1.92 augustss usbd_xfer_handle abortstart, abortend;
98 1.92 augustss
99 1.1 augustss /* Info needed for different pipe kinds. */
100 1.1 augustss union {
101 1.1 augustss /* Control pipe */
102 1.1 augustss struct {
103 1.1 augustss uhci_soft_qh_t *sqh;
104 1.7 augustss usb_dma_t reqdma;
105 1.16 augustss uhci_soft_td_t *setup, *stat;
106 1.1 augustss u_int length;
107 1.1 augustss } ctl;
108 1.1 augustss /* Interrupt pipe */
109 1.1 augustss struct {
110 1.1 augustss int npoll;
111 1.187 skrll int isread;
112 1.1 augustss uhci_soft_qh_t **qhs;
113 1.1 augustss } intr;
114 1.1 augustss /* Bulk pipe */
115 1.1 augustss struct {
116 1.1 augustss uhci_soft_qh_t *sqh;
117 1.1 augustss u_int length;
118 1.1 augustss int isread;
119 1.1 augustss } bulk;
120 1.16 augustss /* Iso pipe */
121 1.16 augustss struct iso {
122 1.16 augustss uhci_soft_td_t **stds;
123 1.48 augustss int next, inuse;
124 1.16 augustss } iso;
125 1.1 augustss } u;
126 1.1 augustss };
127 1.1 augustss
128 1.142 augustss Static void uhci_globalreset(uhci_softc_t *);
129 1.166 dsainty Static usbd_status uhci_portreset(uhci_softc_t*, int);
130 1.142 augustss Static void uhci_reset(uhci_softc_t *);
131 1.264.4.15 skrll Static usbd_status uhci_run(uhci_softc_t *, int, int);
132 1.123 augustss Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *);
133 1.119 augustss Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *);
134 1.123 augustss Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *);
135 1.119 augustss Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *);
136 1.16 augustss #if 0
137 1.119 augustss Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *,
138 1.119 augustss uhci_intr_info_t *);
139 1.119 augustss Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *);
140 1.16 augustss #endif
141 1.1 augustss
142 1.152 augustss Static void uhci_free_std_chain(uhci_softc_t *,
143 1.119 augustss uhci_soft_td_t *, uhci_soft_td_t *);
144 1.119 augustss Static usbd_status uhci_alloc_std_chain(struct uhci_pipe *,
145 1.264.4.1 skrll uhci_softc_t *, int, int, uint16_t, usb_dma_t *,
146 1.119 augustss uhci_soft_td_t **, uhci_soft_td_t **);
147 1.119 augustss Static void uhci_poll_hub(void *);
148 1.119 augustss Static void uhci_waitintr(uhci_softc_t *, usbd_xfer_handle);
149 1.119 augustss Static void uhci_check_intr(uhci_softc_t *, uhci_intr_info_t *);
150 1.119 augustss Static void uhci_idone(uhci_intr_info_t *);
151 1.119 augustss
152 1.264.4.15 skrll Static void uhci_abort_xfer(usbd_xfer_handle, usbd_status);
153 1.119 augustss
154 1.119 augustss Static void uhci_timeout(void *);
155 1.153 augustss Static void uhci_timeout_task(void *);
156 1.123 augustss Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *);
157 1.123 augustss Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *);
158 1.119 augustss Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *);
159 1.123 augustss Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *);
160 1.123 augustss Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *);
161 1.119 augustss Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *);
162 1.264.4.15 skrll Static void uhci_add_loop(uhci_softc_t *);
163 1.264.4.15 skrll Static void uhci_rem_loop(uhci_softc_t *);
164 1.119 augustss
165 1.264.4.15 skrll Static usbd_status uhci_setup_isoc(usbd_pipe_handle);
166 1.119 augustss Static void uhci_device_isoc_enter(usbd_xfer_handle);
167 1.119 augustss
168 1.119 augustss Static usbd_xfer_handle uhci_allocx(struct usbd_bus *);
169 1.119 augustss Static void uhci_freex(struct usbd_bus *, usbd_xfer_handle);
170 1.248 mrg Static void uhci_get_lock(struct usbd_bus *, kmutex_t **);
171 1.264.4.13 skrll Static int uhci_roothub_ctrl(struct usbd_bus *,
172 1.264.4.12 skrll usb_device_request_t *, void *, int);
173 1.119 augustss
174 1.119 augustss Static usbd_status uhci_device_ctrl_transfer(usbd_xfer_handle);
175 1.119 augustss Static usbd_status uhci_device_ctrl_start(usbd_xfer_handle);
176 1.119 augustss Static void uhci_device_ctrl_abort(usbd_xfer_handle);
177 1.119 augustss Static void uhci_device_ctrl_close(usbd_pipe_handle);
178 1.119 augustss Static void uhci_device_ctrl_done(usbd_xfer_handle);
179 1.119 augustss
180 1.119 augustss Static usbd_status uhci_device_intr_transfer(usbd_xfer_handle);
181 1.119 augustss Static usbd_status uhci_device_intr_start(usbd_xfer_handle);
182 1.119 augustss Static void uhci_device_intr_abort(usbd_xfer_handle);
183 1.119 augustss Static void uhci_device_intr_close(usbd_pipe_handle);
184 1.119 augustss Static void uhci_device_intr_done(usbd_xfer_handle);
185 1.119 augustss
186 1.119 augustss Static usbd_status uhci_device_bulk_transfer(usbd_xfer_handle);
187 1.119 augustss Static usbd_status uhci_device_bulk_start(usbd_xfer_handle);
188 1.119 augustss Static void uhci_device_bulk_abort(usbd_xfer_handle);
189 1.119 augustss Static void uhci_device_bulk_close(usbd_pipe_handle);
190 1.119 augustss Static void uhci_device_bulk_done(usbd_xfer_handle);
191 1.119 augustss
192 1.119 augustss Static usbd_status uhci_device_isoc_transfer(usbd_xfer_handle);
193 1.119 augustss Static usbd_status uhci_device_isoc_start(usbd_xfer_handle);
194 1.119 augustss Static void uhci_device_isoc_abort(usbd_xfer_handle);
195 1.119 augustss Static void uhci_device_isoc_close(usbd_pipe_handle);
196 1.119 augustss Static void uhci_device_isoc_done(usbd_xfer_handle);
197 1.119 augustss
198 1.119 augustss Static usbd_status uhci_root_intr_transfer(usbd_xfer_handle);
199 1.119 augustss Static usbd_status uhci_root_intr_start(usbd_xfer_handle);
200 1.119 augustss Static void uhci_root_intr_abort(usbd_xfer_handle);
201 1.119 augustss Static void uhci_root_intr_close(usbd_pipe_handle);
202 1.119 augustss Static void uhci_root_intr_done(usbd_xfer_handle);
203 1.119 augustss
204 1.119 augustss Static usbd_status uhci_open(usbd_pipe_handle);
205 1.119 augustss Static void uhci_poll(struct usbd_bus *);
206 1.133 augustss Static void uhci_softintr(void *);
207 1.119 augustss
208 1.264.4.15 skrll Static usbd_status uhci_device_request(usbd_xfer_handle);
209 1.119 augustss
210 1.119 augustss Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *);
211 1.158 augustss Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *);
212 1.264.4.15 skrll Static usbd_status uhci_device_setintr(uhci_softc_t *,
213 1.264.4.15 skrll struct uhci_pipe *, int);
214 1.119 augustss
215 1.264.4.15 skrll Static void uhci_device_clear_toggle(usbd_pipe_handle);
216 1.264.4.15 skrll Static void uhci_noop(usbd_pipe_handle);
217 1.119 augustss
218 1.240 jakllsch static inline uhci_soft_qh_t *uhci_find_prev_qh(uhci_soft_qh_t *,
219 1.119 augustss uhci_soft_qh_t *);
220 1.119 augustss
221 1.119 augustss #ifdef UHCI_DEBUG
222 1.119 augustss Static void uhci_dump_all(uhci_softc_t *);
223 1.119 augustss Static void uhci_dumpregs(uhci_softc_t *);
224 1.119 augustss Static void uhci_dump_qhs(uhci_soft_qh_t *);
225 1.119 augustss Static void uhci_dump_qh(uhci_soft_qh_t *);
226 1.119 augustss Static void uhci_dump_tds(uhci_soft_td_t *);
227 1.119 augustss Static void uhci_dump_td(uhci_soft_td_t *);
228 1.264.4.15 skrll Static void uhci_dump_ii(uhci_intr_info_t *);
229 1.119 augustss void uhci_dump(void);
230 1.1 augustss #endif
231 1.1 augustss
232 1.112 augustss #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \
233 1.112 augustss BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
234 1.112 augustss #define UWRITE1(sc, r, x) \
235 1.165 dsainty do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \
236 1.165 dsainty } while (/*CONSTCOND*/0)
237 1.112 augustss #define UWRITE2(sc, r, x) \
238 1.165 dsainty do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \
239 1.165 dsainty } while (/*CONSTCOND*/0)
240 1.112 augustss #define UWRITE4(sc, r, x) \
241 1.165 dsainty do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \
242 1.165 dsainty } while (/*CONSTCOND*/0)
243 1.196 mrg static __inline uint8_t
244 1.196 mrg UREAD1(uhci_softc_t *sc, bus_size_t r)
245 1.196 mrg {
246 1.196 mrg
247 1.196 mrg UBARR(sc);
248 1.196 mrg return bus_space_read_1(sc->iot, sc->ioh, r);
249 1.196 mrg }
250 1.196 mrg
251 1.196 mrg static __inline uint16_t
252 1.196 mrg UREAD2(uhci_softc_t *sc, bus_size_t r)
253 1.196 mrg {
254 1.196 mrg
255 1.196 mrg UBARR(sc);
256 1.196 mrg return bus_space_read_2(sc->iot, sc->ioh, r);
257 1.196 mrg }
258 1.196 mrg
259 1.260 joerg #ifdef UHCI_DEBUG
260 1.196 mrg static __inline uint32_t
261 1.196 mrg UREAD4(uhci_softc_t *sc, bus_size_t r)
262 1.196 mrg {
263 1.196 mrg
264 1.196 mrg UBARR(sc);
265 1.196 mrg return bus_space_read_4(sc->iot, sc->ioh, r);
266 1.196 mrg }
267 1.260 joerg #endif
268 1.1 augustss
269 1.1 augustss #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd)
270 1.1 augustss #define UHCISTS(sc) UREAD2(sc, UHCI_STS)
271 1.1 augustss
272 1.142 augustss #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */
273 1.1 augustss
274 1.1 augustss #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK)
275 1.1 augustss
276 1.208 drochner const struct usbd_bus_methods uhci_bus_methods = {
277 1.264.4.5 skrll .ubm_open = uhci_open,
278 1.264.4.5 skrll .ubm_softint = uhci_softintr,
279 1.264.4.5 skrll .ubm_dopoll = uhci_poll,
280 1.264.4.5 skrll .ubm_allocx = uhci_allocx,
281 1.264.4.5 skrll .ubm_freex = uhci_freex,
282 1.264.4.5 skrll .ubm_getlock = uhci_get_lock,
283 1.264.4.12 skrll .ubm_rhctrl = uhci_roothub_ctrl,
284 1.1 augustss };
285 1.1 augustss
286 1.208 drochner const struct usbd_pipe_methods uhci_root_intr_methods = {
287 1.264.4.5 skrll .upm_transfer = uhci_root_intr_transfer,
288 1.264.4.5 skrll .upm_start = uhci_root_intr_start,
289 1.264.4.5 skrll .upm_abort = uhci_root_intr_abort,
290 1.264.4.5 skrll .upm_close = uhci_root_intr_close,
291 1.264.4.5 skrll .upm_cleartoggle = uhci_noop,
292 1.264.4.5 skrll .upm_done = uhci_root_intr_done,
293 1.1 augustss };
294 1.1 augustss
295 1.208 drochner const struct usbd_pipe_methods uhci_device_ctrl_methods = {
296 1.264.4.5 skrll .upm_transfer = uhci_device_ctrl_transfer,
297 1.264.4.5 skrll .upm_start = uhci_device_ctrl_start,
298 1.264.4.5 skrll .upm_abort = uhci_device_ctrl_abort,
299 1.264.4.5 skrll .upm_close = uhci_device_ctrl_close,
300 1.264.4.5 skrll .upm_cleartoggle = uhci_noop,
301 1.264.4.5 skrll .upm_done = uhci_device_ctrl_done,
302 1.1 augustss };
303 1.1 augustss
304 1.208 drochner const struct usbd_pipe_methods uhci_device_intr_methods = {
305 1.264.4.5 skrll .upm_transfer = uhci_device_intr_transfer,
306 1.264.4.5 skrll .upm_start = uhci_device_intr_start,
307 1.264.4.5 skrll .upm_abort = uhci_device_intr_abort,
308 1.264.4.5 skrll .upm_close = uhci_device_intr_close,
309 1.264.4.5 skrll .upm_cleartoggle = uhci_device_clear_toggle,
310 1.264.4.5 skrll .upm_done = uhci_device_intr_done,
311 1.1 augustss };
312 1.1 augustss
313 1.208 drochner const struct usbd_pipe_methods uhci_device_bulk_methods = {
314 1.264.4.5 skrll .upm_transfer = uhci_device_bulk_transfer,
315 1.264.4.5 skrll .upm_start = uhci_device_bulk_start,
316 1.264.4.5 skrll .upm_abort = uhci_device_bulk_abort,
317 1.264.4.5 skrll .upm_close = uhci_device_bulk_close,
318 1.264.4.5 skrll .upm_cleartoggle = uhci_device_clear_toggle,
319 1.264.4.5 skrll .upm_done = uhci_device_bulk_done,
320 1.1 augustss };
321 1.1 augustss
322 1.208 drochner const struct usbd_pipe_methods uhci_device_isoc_methods = {
323 1.264.4.5 skrll .upm_transfer = uhci_device_isoc_transfer,
324 1.264.4.5 skrll .upm_start = uhci_device_isoc_start,
325 1.264.4.5 skrll .upm_abort = uhci_device_isoc_abort,
326 1.264.4.5 skrll .upm_close = uhci_device_isoc_close,
327 1.264.4.5 skrll .upm_cleartoggle = uhci_noop,
328 1.264.4.5 skrll .upm_done = uhci_device_isoc_done,
329 1.16 augustss };
330 1.16 augustss
331 1.92 augustss #define uhci_add_intr_info(sc, ii) \
332 1.169 augustss LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ii), list)
333 1.92 augustss #define uhci_del_intr_info(ii) \
334 1.169 augustss do { \
335 1.169 augustss LIST_REMOVE((ii), list); \
336 1.169 augustss (ii)->list.le_prev = NULL; \
337 1.169 augustss } while (0)
338 1.169 augustss #define uhci_active_intr_info(ii) ((ii)->list.le_prev != NULL)
339 1.92 augustss
340 1.240 jakllsch static inline uhci_soft_qh_t *
341 1.119 augustss uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh)
342 1.92 augustss {
343 1.92 augustss DPRINTFN(15,("uhci_find_prev_qh: pqh=%p sqh=%p\n", pqh, sqh));
344 1.92 augustss
345 1.92 augustss for (; pqh->hlink != sqh; pqh = pqh->hlink) {
346 1.152 augustss #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG)
347 1.223 bouyer usb_syncmem(&pqh->dma,
348 1.223 bouyer pqh->offs + offsetof(uhci_qh_t, qh_hlink),
349 1.223 bouyer sizeof(pqh->qh.qh_hlink),
350 1.223 bouyer BUS_DMASYNC_POSTWRITE);
351 1.92 augustss if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) {
352 1.102 augustss printf("uhci_find_prev_qh: QH not found\n");
353 1.264.4.13 skrll return NULL;
354 1.92 augustss }
355 1.92 augustss #endif
356 1.92 augustss }
357 1.264.4.13 skrll return pqh;
358 1.92 augustss }
359 1.92 augustss
360 1.1 augustss void
361 1.142 augustss uhci_globalreset(uhci_softc_t *sc)
362 1.1 augustss {
363 1.1 augustss UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */
364 1.20 augustss usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */
365 1.1 augustss UHCICMD(sc, 0); /* do nothing */
366 1.1 augustss }
367 1.1 augustss
368 1.264.4.14 skrll int
369 1.119 augustss uhci_init(uhci_softc_t *sc)
370 1.1 augustss {
371 1.63 augustss usbd_status err;
372 1.1 augustss int i, j;
373 1.123 augustss uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh;
374 1.1 augustss uhci_soft_td_t *std;
375 1.1 augustss
376 1.1 augustss DPRINTFN(1,("uhci_init: start\n"));
377 1.1 augustss
378 1.67 augustss #ifdef UHCI_DEBUG
379 1.92 augustss thesc = sc;
380 1.92 augustss
381 1.1 augustss if (uhcidebug > 2)
382 1.1 augustss uhci_dumpregs(sc);
383 1.1 augustss #endif
384 1.1 augustss
385 1.219 jmcneill sc->sc_suspend = PWR_RESUME;
386 1.219 jmcneill
387 1.1 augustss UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */
388 1.142 augustss uhci_globalreset(sc); /* reset the controller */
389 1.142 augustss uhci_reset(sc);
390 1.24 augustss
391 1.1 augustss /* Allocate and initialize real frame array. */
392 1.152 augustss err = usb_allocmem(&sc->sc_bus,
393 1.63 augustss UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t),
394 1.63 augustss UHCI_FRAMELIST_ALIGN, &sc->sc_dma);
395 1.63 augustss if (err)
396 1.264.4.13 skrll return err;
397 1.159 augustss sc->sc_pframes = KERNADDR(&sc->sc_dma, 0);
398 1.1 augustss UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */
399 1.160 augustss UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/
400 1.1 augustss
401 1.152 augustss /*
402 1.123 augustss * Allocate a TD, inactive, that hangs from the last QH.
403 1.123 augustss * This is to avoid a bug in the PIIX that makes it run berserk
404 1.123 augustss * otherwise.
405 1.123 augustss */
406 1.123 augustss std = uhci_alloc_std(sc);
407 1.123 augustss if (std == NULL)
408 1.264.4.14 skrll return ENOMEM;
409 1.123 augustss std->link.std = NULL;
410 1.123 augustss std->td.td_link = htole32(UHCI_PTR_T);
411 1.123 augustss std->td.td_status = htole32(0); /* inactive */
412 1.123 augustss std->td.td_token = htole32(0);
413 1.123 augustss std->td.td_buffer = htole32(0);
414 1.223 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
415 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
416 1.123 augustss
417 1.123 augustss /* Allocate the dummy QH marking the end and used for looping the QHs.*/
418 1.123 augustss lsqh = uhci_alloc_sqh(sc);
419 1.123 augustss if (lsqh == NULL)
420 1.264.4.14 skrll return ENOMEM;
421 1.123 augustss lsqh->hlink = NULL;
422 1.123 augustss lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */
423 1.123 augustss lsqh->elink = std;
424 1.123 augustss lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD);
425 1.123 augustss sc->sc_last_qh = lsqh;
426 1.223 bouyer usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh),
427 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
428 1.123 augustss
429 1.1 augustss /* Allocate the dummy QH where bulk traffic will be queued. */
430 1.1 augustss bsqh = uhci_alloc_sqh(sc);
431 1.63 augustss if (bsqh == NULL)
432 1.264.4.14 skrll return ENOMEM;
433 1.123 augustss bsqh->hlink = lsqh;
434 1.123 augustss bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH);
435 1.121 augustss bsqh->elink = NULL;
436 1.88 tsutsui bsqh->qh.qh_elink = htole32(UHCI_PTR_T);
437 1.1 augustss sc->sc_bulk_start = sc->sc_bulk_end = bsqh;
438 1.223 bouyer usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh),
439 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
440 1.1 augustss
441 1.123 augustss /* Allocate dummy QH where high speed control traffic will be queued. */
442 1.123 augustss chsqh = uhci_alloc_sqh(sc);
443 1.123 augustss if (chsqh == NULL)
444 1.264.4.14 skrll return ENOMEM;
445 1.123 augustss chsqh->hlink = bsqh;
446 1.123 augustss chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH);
447 1.123 augustss chsqh->elink = NULL;
448 1.123 augustss chsqh->qh.qh_elink = htole32(UHCI_PTR_T);
449 1.123 augustss sc->sc_hctl_start = sc->sc_hctl_end = chsqh;
450 1.223 bouyer usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh),
451 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
452 1.123 augustss
453 1.123 augustss /* Allocate dummy QH where control traffic will be queued. */
454 1.123 augustss clsqh = uhci_alloc_sqh(sc);
455 1.123 augustss if (clsqh == NULL)
456 1.264.4.14 skrll return ENOMEM;
457 1.220 bouyer clsqh->hlink = chsqh;
458 1.123 augustss clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH);
459 1.123 augustss clsqh->elink = NULL;
460 1.123 augustss clsqh->qh.qh_elink = htole32(UHCI_PTR_T);
461 1.123 augustss sc->sc_lctl_start = sc->sc_lctl_end = clsqh;
462 1.223 bouyer usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh),
463 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
464 1.1 augustss
465 1.152 augustss /*
466 1.1 augustss * Make all (virtual) frame list pointers point to the interrupt
467 1.1 augustss * queue heads and the interrupt queue heads at the control
468 1.1 augustss * queue head and point the physical frame list to the virtual.
469 1.1 augustss */
470 1.1 augustss for(i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
471 1.1 augustss std = uhci_alloc_std(sc);
472 1.1 augustss sqh = uhci_alloc_sqh(sc);
473 1.67 augustss if (std == NULL || sqh == NULL)
474 1.264.4.13 skrll return USBD_NOMEM;
475 1.42 augustss std->link.sqh = sqh;
476 1.121 augustss std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH);
477 1.88 tsutsui std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */
478 1.88 tsutsui std->td.td_token = htole32(0);
479 1.88 tsutsui std->td.td_buffer = htole32(0);
480 1.223 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
481 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
482 1.123 augustss sqh->hlink = clsqh;
483 1.123 augustss sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH);
484 1.121 augustss sqh->elink = NULL;
485 1.88 tsutsui sqh->qh.qh_elink = htole32(UHCI_PTR_T);
486 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
487 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
488 1.1 augustss sc->sc_vframes[i].htd = std;
489 1.1 augustss sc->sc_vframes[i].etd = std;
490 1.1 augustss sc->sc_vframes[i].hqh = sqh;
491 1.1 augustss sc->sc_vframes[i].eqh = sqh;
492 1.152 augustss for (j = i;
493 1.152 augustss j < UHCI_FRAMELIST_COUNT;
494 1.1 augustss j += UHCI_VFRAMELIST_COUNT)
495 1.88 tsutsui sc->sc_pframes[j] = htole32(std->physaddr);
496 1.1 augustss }
497 1.223 bouyer usb_syncmem(&sc->sc_dma, 0,
498 1.223 bouyer UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t),
499 1.223 bouyer BUS_DMASYNC_PREWRITE);
500 1.223 bouyer
501 1.1 augustss
502 1.1 augustss LIST_INIT(&sc->sc_intrhead);
503 1.1 augustss
504 1.253 christos sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0,
505 1.253 christos "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL);
506 1.76 augustss
507 1.248 mrg callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE);
508 1.248 mrg
509 1.248 mrg mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
510 1.248 mrg mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED);
511 1.248 mrg cv_init(&sc->sc_softwake_cv, "uhciab");
512 1.96 augustss
513 1.1 augustss /* Set up the bus struct. */
514 1.264.4.7 skrll sc->sc_bus.ub_methods = &uhci_bus_methods;
515 1.264.4.7 skrll sc->sc_bus.ub_pipesize = sizeof(struct uhci_pipe);
516 1.264.4.7 skrll sc->sc_bus.ub_usedma = true;
517 1.1 augustss
518 1.190 augustss UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */
519 1.190 augustss
520 1.1 augustss DPRINTFN(1,("uhci_init: enabling\n"));
521 1.225 bouyer
522 1.249 drochner err = uhci_run(sc, 1, 0); /* and here we go... */
523 1.152 augustss UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE |
524 1.1 augustss UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */
525 1.225 bouyer return err;
526 1.53 augustss }
527 1.53 augustss
528 1.53 augustss int
529 1.215 dyoung uhci_activate(device_t self, enum devact act)
530 1.53 augustss {
531 1.215 dyoung struct uhci_softc *sc = device_private(self);
532 1.53 augustss
533 1.53 augustss switch (act) {
534 1.53 augustss case DVACT_DEACTIVATE:
535 1.210 kiyohara sc->sc_dying = 1;
536 1.230 dyoung return 0;
537 1.230 dyoung default:
538 1.230 dyoung return EOPNOTSUPP;
539 1.53 augustss }
540 1.53 augustss }
541 1.53 augustss
542 1.215 dyoung void
543 1.215 dyoung uhci_childdet(device_t self, device_t child)
544 1.215 dyoung {
545 1.215 dyoung struct uhci_softc *sc = device_private(self);
546 1.215 dyoung
547 1.215 dyoung KASSERT(sc->sc_child == child);
548 1.215 dyoung sc->sc_child = NULL;
549 1.215 dyoung }
550 1.215 dyoung
551 1.53 augustss int
552 1.119 augustss uhci_detach(struct uhci_softc *sc, int flags)
553 1.53 augustss {
554 1.53 augustss int rv = 0;
555 1.53 augustss
556 1.53 augustss if (sc->sc_child != NULL)
557 1.53 augustss rv = config_detach(sc->sc_child, flags);
558 1.152 augustss
559 1.53 augustss if (rv != 0)
560 1.264.4.13 skrll return rv;
561 1.53 augustss
562 1.226 ad callout_halt(&sc->sc_poll_handle, NULL);
563 1.226 ad callout_destroy(&sc->sc_poll_handle);
564 1.226 ad
565 1.248 mrg cv_destroy(&sc->sc_softwake_cv);
566 1.248 mrg
567 1.248 mrg mutex_destroy(&sc->sc_lock);
568 1.248 mrg mutex_destroy(&sc->sc_intr_lock);
569 1.248 mrg
570 1.254 christos pool_cache_destroy(sc->sc_xferpool);
571 1.254 christos
572 1.76 augustss /* XXX free other data structures XXX */
573 1.53 augustss
574 1.264.4.13 skrll return rv;
575 1.1 augustss }
576 1.1 augustss
577 1.76 augustss usbd_xfer_handle
578 1.119 augustss uhci_allocx(struct usbd_bus *bus)
579 1.76 augustss {
580 1.264.4.7 skrll struct uhci_softc *sc = bus->ub_hcpriv;
581 1.76 augustss usbd_xfer_handle xfer;
582 1.76 augustss
583 1.253 christos xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT);
584 1.92 augustss if (xfer != NULL) {
585 1.253 christos memset(xfer, 0, sizeof(struct uhci_xfer));
586 1.254 christos UXFER(xfer)->iinfo.sc = sc;
587 1.92 augustss #ifdef DIAGNOSTIC
588 1.238 tsutsui UXFER(xfer)->iinfo.isdone = 1;
589 1.264.4.7 skrll xfer->ux_state = XFER_BUSY;
590 1.92 augustss #endif
591 1.92 augustss }
592 1.264.4.13 skrll return xfer;
593 1.76 augustss }
594 1.76 augustss
595 1.76 augustss void
596 1.119 augustss uhci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer)
597 1.76 augustss {
598 1.264.4.7 skrll struct uhci_softc *sc = bus->ub_hcpriv;
599 1.76 augustss
600 1.93 augustss #ifdef DIAGNOSTIC
601 1.264.4.7 skrll if (xfer->ux_state != XFER_BUSY) {
602 1.94 augustss printf("uhci_freex: xfer=%p not busy, 0x%08x\n", xfer,
603 1.264.4.7 skrll xfer->ux_state);
604 1.93 augustss }
605 1.264.4.7 skrll xfer->ux_state = XFER_FREE;
606 1.238 tsutsui if (!UXFER(xfer)->iinfo.isdone) {
607 1.96 augustss printf("uhci_freex: !isdone\n");
608 1.105 augustss }
609 1.93 augustss #endif
610 1.253 christos pool_cache_put(sc->sc_xferpool, xfer);
611 1.48 augustss }
612 1.48 augustss
613 1.248 mrg Static void
614 1.248 mrg uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock)
615 1.248 mrg {
616 1.264.4.7 skrll struct uhci_softc *sc = bus->ub_hcpriv;
617 1.248 mrg
618 1.248 mrg *lock = &sc->sc_lock;
619 1.248 mrg }
620 1.248 mrg
621 1.248 mrg
622 1.72 augustss /*
623 1.212 jmcneill * Handle suspend/resume.
624 1.212 jmcneill *
625 1.212 jmcneill * We need to switch to polling mode here, because this routine is
626 1.212 jmcneill * called from an interrupt context. This is all right since we
627 1.212 jmcneill * are almost suspended anyway.
628 1.72 augustss */
629 1.212 jmcneill bool
630 1.232 dyoung uhci_resume(device_t dv, const pmf_qual_t *qual)
631 1.72 augustss {
632 1.212 jmcneill uhci_softc_t *sc = device_private(dv);
633 1.212 jmcneill int cmd;
634 1.72 augustss
635 1.248 mrg mutex_spin_enter(&sc->sc_intr_lock);
636 1.193 augustss
637 1.212 jmcneill cmd = UREAD2(sc, UHCI_CMD);
638 1.264.4.7 skrll sc->sc_bus.ub_usepolling++;
639 1.214 smb UWRITE2(sc, UHCI_INTR, 0);
640 1.214 smb uhci_globalreset(sc);
641 1.214 smb uhci_reset(sc);
642 1.212 jmcneill if (cmd & UHCI_CMD_RS)
643 1.249 drochner uhci_run(sc, 0, 1);
644 1.212 jmcneill
645 1.212 jmcneill /* restore saved state */
646 1.212 jmcneill UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0));
647 1.212 jmcneill UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum);
648 1.212 jmcneill UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof);
649 1.212 jmcneill
650 1.212 jmcneill UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */
651 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock);
652 1.212 jmcneill UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */
653 1.212 jmcneill UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE |
654 1.212 jmcneill UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE);
655 1.214 smb UHCICMD(sc, UHCI_CMD_MAXP);
656 1.249 drochner uhci_run(sc, 1, 1); /* and start traffic again */
657 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock);
658 1.264.4.7 skrll sc->sc_bus.ub_usepolling--;
659 1.212 jmcneill if (sc->sc_intr_xfer != NULL)
660 1.234 dyoung callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub,
661 1.212 jmcneill sc->sc_intr_xfer);
662 1.212 jmcneill #ifdef UHCI_DEBUG
663 1.212 jmcneill if (uhcidebug > 2)
664 1.212 jmcneill uhci_dumpregs(sc);
665 1.212 jmcneill #endif
666 1.212 jmcneill
667 1.219 jmcneill sc->sc_suspend = PWR_RESUME;
668 1.248 mrg mutex_spin_exit(&sc->sc_intr_lock);
669 1.212 jmcneill
670 1.212 jmcneill return true;
671 1.72 augustss }
672 1.72 augustss
673 1.212 jmcneill bool
674 1.232 dyoung uhci_suspend(device_t dv, const pmf_qual_t *qual)
675 1.30 augustss {
676 1.212 jmcneill uhci_softc_t *sc = device_private(dv);
677 1.30 augustss int cmd;
678 1.30 augustss
679 1.248 mrg mutex_spin_enter(&sc->sc_intr_lock);
680 1.212 jmcneill
681 1.30 augustss cmd = UREAD2(sc, UHCI_CMD);
682 1.30 augustss
683 1.212 jmcneill #ifdef UHCI_DEBUG
684 1.212 jmcneill if (uhcidebug > 2)
685 1.212 jmcneill uhci_dumpregs(sc);
686 1.212 jmcneill #endif
687 1.212 jmcneill if (sc->sc_intr_xfer != NULL)
688 1.234 dyoung callout_stop(&sc->sc_poll_handle);
689 1.219 jmcneill sc->sc_suspend = PWR_SUSPEND;
690 1.264.4.7 skrll sc->sc_bus.ub_usepolling++;
691 1.219 jmcneill
692 1.249 drochner uhci_run(sc, 0, 1); /* stop the controller */
693 1.212 jmcneill cmd &= ~UHCI_CMD_RS;
694 1.212 jmcneill
695 1.212 jmcneill /* save some state if BIOS doesn't */
696 1.212 jmcneill sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM);
697 1.212 jmcneill sc->sc_saved_sof = UREAD1(sc, UHCI_SOF);
698 1.212 jmcneill
699 1.212 jmcneill UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */
700 1.30 augustss
701 1.212 jmcneill UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */
702 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock);
703 1.264.4.7 skrll sc->sc_bus.ub_usepolling--;
704 1.86 augustss
705 1.248 mrg mutex_spin_exit(&sc->sc_intr_lock);
706 1.212 jmcneill
707 1.212 jmcneill return true;
708 1.30 augustss }
709 1.30 augustss
710 1.59 augustss #ifdef UHCI_DEBUG
711 1.101 augustss Static void
712 1.119 augustss uhci_dumpregs(uhci_softc_t *sc)
713 1.1 augustss {
714 1.48 augustss DPRINTFN(-1,("%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, "
715 1.48 augustss "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n",
716 1.216 drochner device_xname(sc->sc_dev),
717 1.48 augustss UREAD2(sc, UHCI_CMD),
718 1.48 augustss UREAD2(sc, UHCI_STS),
719 1.48 augustss UREAD2(sc, UHCI_INTR),
720 1.48 augustss UREAD2(sc, UHCI_FRNUM),
721 1.48 augustss UREAD4(sc, UHCI_FLBASEADDR),
722 1.48 augustss UREAD1(sc, UHCI_SOF),
723 1.48 augustss UREAD2(sc, UHCI_PORTSC1),
724 1.48 augustss UREAD2(sc, UHCI_PORTSC2)));
725 1.1 augustss }
726 1.1 augustss
727 1.1 augustss void
728 1.119 augustss uhci_dump_td(uhci_soft_td_t *p)
729 1.1 augustss {
730 1.122 tv char sbuf[128], sbuf2[128];
731 1.122 tv
732 1.250 christos
733 1.223 bouyer usb_syncmem(&p->dma, p->offs, sizeof(p->td),
734 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
735 1.48 augustss DPRINTFN(-1,("TD(%p) at %08lx = link=0x%08lx status=0x%08lx "
736 1.48 augustss "token=0x%08lx buffer=0x%08lx\n",
737 1.48 augustss p, (long)p->physaddr,
738 1.88 tsutsui (long)le32toh(p->td.td_link),
739 1.88 tsutsui (long)le32toh(p->td.td_status),
740 1.88 tsutsui (long)le32toh(p->td.td_token),
741 1.88 tsutsui (long)le32toh(p->td.td_buffer)));
742 1.122 tv
743 1.224 christos snprintb(sbuf, sizeof(sbuf), "\20\1T\2Q\3VF",
744 1.264.4.1 skrll (uint32_t)le32toh(p->td.td_link));
745 1.224 christos snprintb(sbuf2, sizeof(sbuf2),
746 1.224 christos "\20\22BITSTUFF\23CRCTO\24NAK\25BABBLE\26DBUFFER\27"
747 1.224 christos "STALLED\30ACTIVE\31IOC\32ISO\33LS\36SPD",
748 1.264.4.1 skrll (uint32_t)le32toh(p->td.td_status));
749 1.122 tv
750 1.122 tv DPRINTFN(-1,(" %s %s,errcnt=%d,actlen=%d pid=%02x,addr=%d,endpt=%d,"
751 1.122 tv "D=%d,maxlen=%d\n", sbuf, sbuf2,
752 1.88 tsutsui UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)),
753 1.88 tsutsui UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)),
754 1.88 tsutsui UHCI_TD_GET_PID(le32toh(p->td.td_token)),
755 1.88 tsutsui UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)),
756 1.88 tsutsui UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)),
757 1.88 tsutsui UHCI_TD_GET_DT(le32toh(p->td.td_token)),
758 1.88 tsutsui UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token))));
759 1.223 bouyer usb_syncmem(&p->dma, p->offs, sizeof(p->td),
760 1.223 bouyer BUS_DMASYNC_PREREAD);
761 1.1 augustss }
762 1.1 augustss
763 1.1 augustss void
764 1.119 augustss uhci_dump_qh(uhci_soft_qh_t *sqh)
765 1.1 augustss {
766 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
767 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
768 1.67 augustss DPRINTFN(-1,("QH(%p) at %08x: hlink=%08x elink=%08x\n", sqh,
769 1.88 tsutsui (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink),
770 1.88 tsutsui le32toh(sqh->qh.qh_elink)));
771 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD);
772 1.1 augustss }
773 1.1 augustss
774 1.13 augustss
775 1.110 augustss #if 1
776 1.1 augustss void
777 1.119 augustss uhci_dump(void)
778 1.1 augustss {
779 1.110 augustss uhci_dump_all(thesc);
780 1.110 augustss }
781 1.110 augustss #endif
782 1.1 augustss
783 1.110 augustss void
784 1.119 augustss uhci_dump_all(uhci_softc_t *sc)
785 1.110 augustss {
786 1.1 augustss uhci_dumpregs(sc);
787 1.110 augustss /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/
788 1.261 skrll uhci_dump_qhs(sc->sc_lctl_start);
789 1.1 augustss }
790 1.1 augustss
791 1.67 augustss
792 1.67 augustss void
793 1.119 augustss uhci_dump_qhs(uhci_soft_qh_t *sqh)
794 1.67 augustss {
795 1.67 augustss uhci_dump_qh(sqh);
796 1.67 augustss
797 1.67 augustss /* uhci_dump_qhs displays all the QHs and TDs from the given QH onwards
798 1.67 augustss * Traverses sideways first, then down.
799 1.67 augustss *
800 1.67 augustss * QH1
801 1.67 augustss * QH2
802 1.67 augustss * No QH
803 1.67 augustss * TD2.1
804 1.67 augustss * TD2.2
805 1.67 augustss * TD1.1
806 1.67 augustss * etc.
807 1.67 augustss *
808 1.67 augustss * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1.
809 1.67 augustss */
810 1.67 augustss
811 1.67 augustss
812 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
813 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
814 1.88 tsutsui if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T))
815 1.67 augustss uhci_dump_qhs(sqh->hlink);
816 1.67 augustss else
817 1.67 augustss DPRINTF(("No QH\n"));
818 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD);
819 1.67 augustss
820 1.88 tsutsui if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T))
821 1.67 augustss uhci_dump_tds(sqh->elink);
822 1.67 augustss else
823 1.67 augustss DPRINTF(("No TD\n"));
824 1.67 augustss }
825 1.67 augustss
826 1.1 augustss void
827 1.119 augustss uhci_dump_tds(uhci_soft_td_t *std)
828 1.1 augustss {
829 1.67 augustss uhci_soft_td_t *td;
830 1.223 bouyer int stop;
831 1.67 augustss
832 1.67 augustss for(td = std; td != NULL; td = td->link.std) {
833 1.67 augustss uhci_dump_td(td);
834 1.1 augustss
835 1.67 augustss /* Check whether the link pointer in this TD marks
836 1.67 augustss * the link pointer as end of queue. This avoids
837 1.67 augustss * printing the free list in case the queue/TD has
838 1.67 augustss * already been moved there (seatbelt).
839 1.67 augustss */
840 1.223 bouyer usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link),
841 1.223 bouyer sizeof(td->td.td_link),
842 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
843 1.223 bouyer stop = (le32toh(td->td.td_link) & UHCI_PTR_T ||
844 1.223 bouyer le32toh(td->td.td_link) == 0);
845 1.223 bouyer usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link),
846 1.223 bouyer sizeof(td->td.td_link), BUS_DMASYNC_PREREAD);
847 1.223 bouyer if (stop)
848 1.67 augustss break;
849 1.67 augustss }
850 1.1 augustss }
851 1.92 augustss
852 1.101 augustss Static void
853 1.119 augustss uhci_dump_ii(uhci_intr_info_t *ii)
854 1.92 augustss {
855 1.95 augustss usbd_pipe_handle pipe;
856 1.95 augustss usb_endpoint_descriptor_t *ed;
857 1.95 augustss usbd_device_handle dev;
858 1.152 augustss
859 1.98 augustss #ifdef DIAGNOSTIC
860 1.98 augustss #define DONE ii->isdone
861 1.98 augustss #else
862 1.98 augustss #define DONE 0
863 1.98 augustss #endif
864 1.264.4.2 skrll if (ii == NULL) {
865 1.264.4.2 skrll printf("ii NULL\n");
866 1.264.4.2 skrll return;
867 1.264.4.2 skrll }
868 1.264.4.2 skrll if (ii->xfer == NULL) {
869 1.95 augustss printf("ii %p: done=%d xfer=NULL\n",
870 1.98 augustss ii, DONE);
871 1.264.4.2 skrll return;
872 1.264.4.2 skrll }
873 1.264.4.7 skrll pipe = ii->xfer->ux_pipe;
874 1.264.4.2 skrll if (pipe == NULL) {
875 1.95 augustss printf("ii %p: done=%d xfer=%p pipe=NULL\n",
876 1.264.4.2 skrll ii, DONE, ii->xfer);
877 1.264.4.2 skrll return;
878 1.139 augustss }
879 1.264.4.7 skrll if (pipe->up_endpoint == NULL) {
880 1.264.4.7 skrll printf("ii %p: done=%d xfer=%p pipe=%p pipe->up_endpoint=NULL\n",
881 1.139 augustss ii, DONE, ii->xfer, pipe);
882 1.264.4.2 skrll return;
883 1.139 augustss }
884 1.264.4.7 skrll if (pipe->up_dev == NULL) {
885 1.264.4.7 skrll printf("ii %p: done=%d xfer=%p pipe=%p pipe->up_dev=NULL\n",
886 1.139 augustss ii, DONE, ii->xfer, pipe);
887 1.264.4.2 skrll return;
888 1.95 augustss }
889 1.264.4.7 skrll ed = pipe->up_endpoint->ue_edesc;
890 1.264.4.7 skrll dev = pipe->up_dev;
891 1.152 augustss printf("ii %p: done=%d xfer=%p dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n",
892 1.152 augustss ii, DONE, ii->xfer, dev,
893 1.264.4.7 skrll UGETW(dev->ud_ddesc.idVendor),
894 1.264.4.7 skrll UGETW(dev->ud_ddesc.idProduct),
895 1.264.4.7 skrll dev->ud_addr, pipe,
896 1.92 augustss ed->bEndpointAddress, ed->bmAttributes);
897 1.98 augustss #undef DONE
898 1.92 augustss }
899 1.92 augustss
900 1.120 augustss void uhci_dump_iis(struct uhci_softc *sc);
901 1.92 augustss void
902 1.119 augustss uhci_dump_iis(struct uhci_softc *sc)
903 1.92 augustss {
904 1.92 augustss uhci_intr_info_t *ii;
905 1.92 augustss
906 1.92 augustss printf("intr_info list:\n");
907 1.92 augustss for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = LIST_NEXT(ii, list))
908 1.92 augustss uhci_dump_ii(ii);
909 1.92 augustss }
910 1.92 augustss
911 1.120 augustss void iidump(void);
912 1.119 augustss void iidump(void) { uhci_dump_iis(thesc); }
913 1.92 augustss
914 1.1 augustss #endif
915 1.1 augustss
916 1.1 augustss /*
917 1.1 augustss * This routine is executed periodically and simulates interrupts
918 1.1 augustss * from the root controller interrupt pipe for port status change.
919 1.1 augustss */
920 1.1 augustss void
921 1.119 augustss uhci_poll_hub(void *addr)
922 1.1 augustss {
923 1.63 augustss usbd_xfer_handle xfer = addr;
924 1.264.4.7 skrll usbd_pipe_handle pipe = xfer->ux_pipe;
925 1.227 martin uhci_softc_t *sc;
926 1.1 augustss u_char *p;
927 1.1 augustss
928 1.96 augustss DPRINTFN(20, ("uhci_poll_hub\n"));
929 1.1 augustss
930 1.264.4.7 skrll if (__predict_false(pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL))
931 1.228 martin return; /* device has detached */
932 1.264.4.7 skrll sc = pipe->up_dev->ud_bus->ub_hcpriv;
933 1.234 dyoung callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer);
934 1.41 augustss
935 1.264.4.7 skrll p = xfer->ux_buf;
936 1.1 augustss p[0] = 0;
937 1.1 augustss if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC))
938 1.1 augustss p[0] |= 1<<1;
939 1.1 augustss if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC))
940 1.1 augustss p[0] |= 1<<2;
941 1.41 augustss if (p[0] == 0)
942 1.41 augustss /* No change, try again in a while */
943 1.41 augustss return;
944 1.41 augustss
945 1.264.4.7 skrll xfer->ux_actlen = 1;
946 1.264.4.7 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
947 1.248 mrg mutex_enter(&sc->sc_lock);
948 1.63 augustss usb_transfer_complete(xfer);
949 1.248 mrg mutex_exit(&sc->sc_lock);
950 1.41 augustss }
951 1.41 augustss
952 1.41 augustss void
953 1.205 christos uhci_root_intr_done(usbd_xfer_handle xfer)
954 1.84 augustss {
955 1.84 augustss }
956 1.84 augustss
957 1.123 augustss /*
958 1.123 augustss * Let the last QH loop back to the high speed control transfer QH.
959 1.123 augustss * This is what intel calls "bandwidth reclamation" and improves
960 1.123 augustss * USB performance a lot for some devices.
961 1.123 augustss * If we are already looping, just count it.
962 1.123 augustss */
963 1.1 augustss void
964 1.264.4.17 skrll uhci_add_loop(uhci_softc_t *sc)
965 1.264.4.17 skrll {
966 1.125 augustss #ifdef UHCI_DEBUG
967 1.125 augustss if (uhcinoloop)
968 1.125 augustss return;
969 1.125 augustss #endif
970 1.123 augustss if (++sc->sc_loops == 1) {
971 1.125 augustss DPRINTFN(5,("uhci_start_loop: add\n"));
972 1.123 augustss /* Note, we don't loop back the soft pointer. */
973 1.152 augustss sc->sc_last_qh->qh.qh_hlink =
974 1.123 augustss htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH);
975 1.223 bouyer usb_syncmem(&sc->sc_last_qh->dma,
976 1.223 bouyer sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink),
977 1.223 bouyer sizeof(sc->sc_last_qh->qh.qh_hlink),
978 1.223 bouyer BUS_DMASYNC_PREWRITE);
979 1.123 augustss }
980 1.123 augustss }
981 1.123 augustss
982 1.123 augustss void
983 1.264.4.17 skrll uhci_rem_loop(uhci_softc_t *sc)
984 1.264.4.17 skrll {
985 1.125 augustss #ifdef UHCI_DEBUG
986 1.125 augustss if (uhcinoloop)
987 1.125 augustss return;
988 1.125 augustss #endif
989 1.123 augustss if (--sc->sc_loops == 0) {
990 1.123 augustss DPRINTFN(5,("uhci_end_loop: remove\n"));
991 1.123 augustss sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T);
992 1.223 bouyer usb_syncmem(&sc->sc_last_qh->dma,
993 1.223 bouyer sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink),
994 1.223 bouyer sizeof(sc->sc_last_qh->qh.qh_hlink),
995 1.223 bouyer BUS_DMASYNC_PREWRITE);
996 1.123 augustss }
997 1.123 augustss }
998 1.123 augustss
999 1.248 mrg /* Add high speed control QH, called with lock held. */
1000 1.123 augustss void
1001 1.123 augustss uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1002 1.1 augustss {
1003 1.42 augustss uhci_soft_qh_t *eqh;
1004 1.1 augustss
1005 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
1006 1.248 mrg
1007 1.1 augustss DPRINTFN(10, ("uhci_add_ctrl: sqh=%p\n", sqh));
1008 1.123 augustss eqh = sc->sc_hctl_end;
1009 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1010 1.223 bouyer sizeof(eqh->qh.qh_hlink),
1011 1.223 bouyer BUS_DMASYNC_POSTWRITE);
1012 1.42 augustss sqh->hlink = eqh->hlink;
1013 1.42 augustss sqh->qh.qh_hlink = eqh->qh.qh_hlink;
1014 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1015 1.223 bouyer BUS_DMASYNC_PREWRITE);
1016 1.42 augustss eqh->hlink = sqh;
1017 1.121 augustss eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
1018 1.123 augustss sc->sc_hctl_end = sqh;
1019 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1020 1.223 bouyer sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
1021 1.125 augustss #ifdef UHCI_CTL_LOOP
1022 1.123 augustss uhci_add_loop(sc);
1023 1.125 augustss #endif
1024 1.1 augustss }
1025 1.1 augustss
1026 1.248 mrg /* Remove high speed control QH, called with lock held. */
1027 1.1 augustss void
1028 1.123 augustss uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1029 1.1 augustss {
1030 1.1 augustss uhci_soft_qh_t *pqh;
1031 1.256 tsutsui uint32_t elink;
1032 1.1 augustss
1033 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
1034 1.248 mrg
1035 1.123 augustss DPRINTFN(10, ("uhci_remove_hs_ctrl: sqh=%p\n", sqh));
1036 1.125 augustss #ifdef UHCI_CTL_LOOP
1037 1.123 augustss uhci_rem_loop(sc);
1038 1.125 augustss #endif
1039 1.124 augustss /*
1040 1.124 augustss * The T bit should be set in the elink of the QH so that the HC
1041 1.124 augustss * doesn't follow the pointer. This condition may fail if the
1042 1.124 augustss * the transferred packet was short so that the QH still points
1043 1.124 augustss * at the last used TD.
1044 1.124 augustss * In this case we set the T bit and wait a little for the HC
1045 1.124 augustss * to stop looking at the TD.
1046 1.223 bouyer * Note that if the TD chain is large enough, the controller
1047 1.223 bouyer * may still be looking at the chain at the end of this function.
1048 1.223 bouyer * uhci_free_std_chain() will make sure the controller stops
1049 1.223 bouyer * looking at it quickly, but until then we should not change
1050 1.223 bouyer * sqh->hlink.
1051 1.124 augustss */
1052 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
1053 1.223 bouyer sizeof(sqh->qh.qh_elink),
1054 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1055 1.256 tsutsui elink = le32toh(sqh->qh.qh_elink);
1056 1.256 tsutsui usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
1057 1.256 tsutsui sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD);
1058 1.256 tsutsui if (!(elink & UHCI_PTR_T)) {
1059 1.124 augustss sqh->qh.qh_elink = htole32(UHCI_PTR_T);
1060 1.223 bouyer usb_syncmem(&sqh->dma,
1061 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
1062 1.223 bouyer sizeof(sqh->qh.qh_elink),
1063 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1064 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1065 1.124 augustss }
1066 1.124 augustss
1067 1.123 augustss pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh);
1068 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
1069 1.223 bouyer sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
1070 1.152 augustss pqh->hlink = sqh->hlink;
1071 1.42 augustss pqh->qh.qh_hlink = sqh->qh.qh_hlink;
1072 1.223 bouyer usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
1073 1.223 bouyer sizeof(pqh->qh.qh_hlink),
1074 1.223 bouyer BUS_DMASYNC_PREWRITE);
1075 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1076 1.123 augustss if (sc->sc_hctl_end == sqh)
1077 1.123 augustss sc->sc_hctl_end = pqh;
1078 1.123 augustss }
1079 1.123 augustss
1080 1.248 mrg /* Add low speed control QH, called with lock held. */
1081 1.123 augustss void
1082 1.123 augustss uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1083 1.123 augustss {
1084 1.123 augustss uhci_soft_qh_t *eqh;
1085 1.123 augustss
1086 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
1087 1.248 mrg
1088 1.123 augustss DPRINTFN(10, ("uhci_add_ls_ctrl: sqh=%p\n", sqh));
1089 1.123 augustss eqh = sc->sc_lctl_end;
1090 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1091 1.223 bouyer sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
1092 1.152 augustss sqh->hlink = eqh->hlink;
1093 1.123 augustss sqh->qh.qh_hlink = eqh->qh.qh_hlink;
1094 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1095 1.223 bouyer BUS_DMASYNC_PREWRITE);
1096 1.152 augustss eqh->hlink = sqh;
1097 1.123 augustss eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
1098 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1099 1.223 bouyer sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
1100 1.123 augustss sc->sc_lctl_end = sqh;
1101 1.123 augustss }
1102 1.123 augustss
1103 1.248 mrg /* Remove low speed control QH, called with lock held. */
1104 1.123 augustss void
1105 1.123 augustss uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1106 1.123 augustss {
1107 1.123 augustss uhci_soft_qh_t *pqh;
1108 1.256 tsutsui uint32_t elink;
1109 1.123 augustss
1110 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
1111 1.248 mrg
1112 1.123 augustss DPRINTFN(10, ("uhci_remove_ls_ctrl: sqh=%p\n", sqh));
1113 1.124 augustss /* See comment in uhci_remove_hs_ctrl() */
1114 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
1115 1.223 bouyer sizeof(sqh->qh.qh_elink),
1116 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1117 1.256 tsutsui elink = le32toh(sqh->qh.qh_elink);
1118 1.256 tsutsui usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
1119 1.256 tsutsui sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD);
1120 1.256 tsutsui if (!(elink & UHCI_PTR_T)) {
1121 1.124 augustss sqh->qh.qh_elink = htole32(UHCI_PTR_T);
1122 1.223 bouyer usb_syncmem(&sqh->dma,
1123 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
1124 1.223 bouyer sizeof(sqh->qh.qh_elink),
1125 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1126 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1127 1.124 augustss }
1128 1.123 augustss pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh);
1129 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
1130 1.223 bouyer sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
1131 1.152 augustss pqh->hlink = sqh->hlink;
1132 1.123 augustss pqh->qh.qh_hlink = sqh->qh.qh_hlink;
1133 1.223 bouyer usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
1134 1.223 bouyer sizeof(pqh->qh.qh_hlink),
1135 1.223 bouyer BUS_DMASYNC_PREWRITE);
1136 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1137 1.123 augustss if (sc->sc_lctl_end == sqh)
1138 1.123 augustss sc->sc_lctl_end = pqh;
1139 1.1 augustss }
1140 1.1 augustss
1141 1.248 mrg /* Add bulk QH, called with lock held. */
1142 1.1 augustss void
1143 1.119 augustss uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1144 1.1 augustss {
1145 1.42 augustss uhci_soft_qh_t *eqh;
1146 1.1 augustss
1147 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
1148 1.248 mrg
1149 1.1 augustss DPRINTFN(10, ("uhci_add_bulk: sqh=%p\n", sqh));
1150 1.42 augustss eqh = sc->sc_bulk_end;
1151 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1152 1.223 bouyer sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
1153 1.152 augustss sqh->hlink = eqh->hlink;
1154 1.42 augustss sqh->qh.qh_hlink = eqh->qh.qh_hlink;
1155 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1156 1.223 bouyer BUS_DMASYNC_PREWRITE);
1157 1.152 augustss eqh->hlink = sqh;
1158 1.121 augustss eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
1159 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1160 1.223 bouyer sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
1161 1.1 augustss sc->sc_bulk_end = sqh;
1162 1.123 augustss uhci_add_loop(sc);
1163 1.1 augustss }
1164 1.1 augustss
1165 1.248 mrg /* Remove bulk QH, called with lock held. */
1166 1.1 augustss void
1167 1.119 augustss uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1168 1.1 augustss {
1169 1.1 augustss uhci_soft_qh_t *pqh;
1170 1.1 augustss
1171 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
1172 1.248 mrg
1173 1.1 augustss DPRINTFN(10, ("uhci_remove_bulk: sqh=%p\n", sqh));
1174 1.123 augustss uhci_rem_loop(sc);
1175 1.124 augustss /* See comment in uhci_remove_hs_ctrl() */
1176 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
1177 1.223 bouyer sizeof(sqh->qh.qh_elink),
1178 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1179 1.124 augustss if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) {
1180 1.124 augustss sqh->qh.qh_elink = htole32(UHCI_PTR_T);
1181 1.223 bouyer usb_syncmem(&sqh->dma,
1182 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
1183 1.223 bouyer sizeof(sqh->qh.qh_elink),
1184 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1185 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1186 1.124 augustss }
1187 1.92 augustss pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh);
1188 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
1189 1.223 bouyer sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
1190 1.42 augustss pqh->hlink = sqh->hlink;
1191 1.42 augustss pqh->qh.qh_hlink = sqh->qh.qh_hlink;
1192 1.223 bouyer usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
1193 1.223 bouyer sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
1194 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1195 1.1 augustss if (sc->sc_bulk_end == sqh)
1196 1.1 augustss sc->sc_bulk_end = pqh;
1197 1.1 augustss }
1198 1.1 augustss
1199 1.141 augustss Static int uhci_intr1(uhci_softc_t *);
1200 1.141 augustss
1201 1.1 augustss int
1202 1.119 augustss uhci_intr(void *arg)
1203 1.1 augustss {
1204 1.44 augustss uhci_softc_t *sc = arg;
1205 1.248 mrg int ret = 0;
1206 1.248 mrg
1207 1.248 mrg mutex_spin_enter(&sc->sc_intr_lock);
1208 1.146 augustss
1209 1.216 drochner if (sc->sc_dying || !device_has_power(sc->sc_dev))
1210 1.248 mrg goto done;
1211 1.141 augustss
1212 1.264.4.7 skrll if (sc->sc_bus.ub_usepolling || UREAD2(sc, UHCI_INTR) == 0) {
1213 1.141 augustss #ifdef DIAGNOSTIC
1214 1.179 mycroft DPRINTFN(16, ("uhci_intr: ignored interrupt while polling\n"));
1215 1.141 augustss #endif
1216 1.248 mrg goto done;
1217 1.141 augustss }
1218 1.179 mycroft
1219 1.248 mrg ret = uhci_intr1(sc);
1220 1.248 mrg
1221 1.248 mrg done:
1222 1.248 mrg mutex_spin_exit(&sc->sc_intr_lock);
1223 1.248 mrg return ret;
1224 1.141 augustss }
1225 1.141 augustss
1226 1.141 augustss int
1227 1.141 augustss uhci_intr1(uhci_softc_t *sc)
1228 1.141 augustss {
1229 1.44 augustss int status;
1230 1.44 augustss int ack;
1231 1.1 augustss
1232 1.67 augustss #ifdef UHCI_DEBUG
1233 1.44 augustss if (uhcidebug > 15) {
1234 1.216 drochner DPRINTF(("%s: uhci_intr1\n", device_xname(sc->sc_dev)));
1235 1.1 augustss uhci_dumpregs(sc);
1236 1.1 augustss }
1237 1.1 augustss #endif
1238 1.117 augustss
1239 1.248 mrg KASSERT(mutex_owned(&sc->sc_intr_lock));
1240 1.248 mrg
1241 1.153 augustss status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS;
1242 1.127 soren if (status == 0) /* The interrupt was not for us. */
1243 1.264.4.13 skrll return 0;
1244 1.127 soren
1245 1.117 augustss if (sc->sc_suspend != PWR_RESUME) {
1246 1.201 jmcneill #ifdef DIAGNOSTIC
1247 1.117 augustss printf("%s: interrupt while not operating ignored\n",
1248 1.216 drochner device_xname(sc->sc_dev));
1249 1.201 jmcneill #endif
1250 1.134 augustss UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */
1251 1.264.4.13 skrll return 0;
1252 1.117 augustss }
1253 1.44 augustss
1254 1.44 augustss ack = 0;
1255 1.44 augustss if (status & UHCI_STS_USBINT)
1256 1.44 augustss ack |= UHCI_STS_USBINT;
1257 1.44 augustss if (status & UHCI_STS_USBEI)
1258 1.44 augustss ack |= UHCI_STS_USBEI;
1259 1.1 augustss if (status & UHCI_STS_RD) {
1260 1.44 augustss ack |= UHCI_STS_RD;
1261 1.118 augustss #ifdef UHCI_DEBUG
1262 1.216 drochner printf("%s: resume detect\n", device_xname(sc->sc_dev));
1263 1.118 augustss #endif
1264 1.1 augustss }
1265 1.1 augustss if (status & UHCI_STS_HSE) {
1266 1.44 augustss ack |= UHCI_STS_HSE;
1267 1.216 drochner printf("%s: host system error\n", device_xname(sc->sc_dev));
1268 1.1 augustss }
1269 1.1 augustss if (status & UHCI_STS_HCPE) {
1270 1.44 augustss ack |= UHCI_STS_HCPE;
1271 1.152 augustss printf("%s: host controller process error\n",
1272 1.216 drochner device_xname(sc->sc_dev));
1273 1.44 augustss }
1274 1.233 msaitoh
1275 1.233 msaitoh /* When HCHalted=1 and Run/Stop=0 , it is normal */
1276 1.233 msaitoh if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) {
1277 1.44 augustss /* no acknowledge needed */
1278 1.136 augustss if (!sc->sc_dying) {
1279 1.152 augustss printf("%s: host controller halted\n",
1280 1.216 drochner device_xname(sc->sc_dev));
1281 1.110 augustss #ifdef UHCI_DEBUG
1282 1.136 augustss uhci_dump_all(sc);
1283 1.110 augustss #endif
1284 1.136 augustss }
1285 1.136 augustss sc->sc_dying = 1;
1286 1.1 augustss }
1287 1.44 augustss
1288 1.132 augustss if (!ack)
1289 1.264.4.13 skrll return 0; /* nothing to acknowledge */
1290 1.132 augustss UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */
1291 1.1 augustss
1292 1.85 augustss usb_schedsoftintr(&sc->sc_bus);
1293 1.85 augustss
1294 1.216 drochner DPRINTFN(15, ("%s: uhci_intr: exit\n", device_xname(sc->sc_dev)));
1295 1.85 augustss
1296 1.264.4.13 skrll return 1;
1297 1.85 augustss }
1298 1.85 augustss
1299 1.85 augustss void
1300 1.133 augustss uhci_softintr(void *v)
1301 1.85 augustss {
1302 1.216 drochner struct usbd_bus *bus = v;
1303 1.264.4.7 skrll uhci_softc_t *sc = bus->ub_hcpriv;
1304 1.178 martin uhci_intr_info_t *ii, *nextii;
1305 1.85 augustss
1306 1.264.4.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1307 1.248 mrg
1308 1.247 mrg DPRINTFN(10,("%s: uhci_softintr\n", device_xname(sc->sc_dev)));
1309 1.50 augustss
1310 1.1 augustss /*
1311 1.1 augustss * Interrupts on UHCI really suck. When the host controller
1312 1.1 augustss * interrupts because a transfer is completed there is no
1313 1.1 augustss * way of knowing which transfer it was. You can scan down
1314 1.1 augustss * the TDs and QHs of the previous frame to limit the search,
1315 1.1 augustss * but that assumes that the interrupt was not delayed by more
1316 1.1 augustss * than 1 ms, which may not always be true (e.g. after debug
1317 1.1 augustss * output on a slow console).
1318 1.1 augustss * We scan all interrupt descriptors to see if any have
1319 1.1 augustss * completed.
1320 1.1 augustss */
1321 1.178 martin for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = nextii) {
1322 1.178 martin nextii = LIST_NEXT(ii, list);
1323 1.1 augustss uhci_check_intr(sc, ii);
1324 1.178 martin }
1325 1.1 augustss
1326 1.153 augustss if (sc->sc_softwake) {
1327 1.153 augustss sc->sc_softwake = 0;
1328 1.248 mrg cv_broadcast(&sc->sc_softwake_cv);
1329 1.153 augustss }
1330 1.1 augustss }
1331 1.1 augustss
1332 1.1 augustss /* Check for an interrupt. */
1333 1.1 augustss void
1334 1.205 christos uhci_check_intr(uhci_softc_t *sc, uhci_intr_info_t *ii)
1335 1.1 augustss {
1336 1.1 augustss uhci_soft_td_t *std, *lstd;
1337 1.264.4.1 skrll uint32_t status;
1338 1.1 augustss
1339 1.1 augustss DPRINTFN(15, ("uhci_check_intr: ii=%p\n", ii));
1340 1.1 augustss #ifdef DIAGNOSTIC
1341 1.63 augustss if (ii == NULL) {
1342 1.1 augustss printf("uhci_check_intr: no ii? %p\n", ii);
1343 1.1 augustss return;
1344 1.1 augustss }
1345 1.1 augustss #endif
1346 1.264.4.7 skrll if (ii->xfer->ux_status == USBD_CANCELLED ||
1347 1.264.4.7 skrll ii->xfer->ux_status == USBD_TIMEOUT) {
1348 1.155 augustss DPRINTF(("uhci_check_intr: aborted xfer=%p\n", ii->xfer));
1349 1.155 augustss return;
1350 1.155 augustss }
1351 1.155 augustss
1352 1.63 augustss if (ii->stdstart == NULL)
1353 1.1 augustss return;
1354 1.1 augustss lstd = ii->stdend;
1355 1.1 augustss #ifdef DIAGNOSTIC
1356 1.63 augustss if (lstd == NULL) {
1357 1.1 augustss printf("uhci_check_intr: std==0\n");
1358 1.1 augustss return;
1359 1.1 augustss }
1360 1.1 augustss #endif
1361 1.223 bouyer usb_syncmem(&lstd->dma,
1362 1.223 bouyer lstd->offs + offsetof(uhci_td_t, td_status),
1363 1.223 bouyer sizeof(lstd->td.td_status),
1364 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1365 1.256 tsutsui status = le32toh(lstd->td.td_status);
1366 1.256 tsutsui usb_syncmem(&lstd->dma,
1367 1.256 tsutsui lstd->offs + offsetof(uhci_td_t, td_status),
1368 1.256 tsutsui sizeof(lstd->td.td_status),
1369 1.256 tsutsui BUS_DMASYNC_PREREAD);
1370 1.258 skrll
1371 1.258 skrll /* If the last TD is not marked active we can complete */
1372 1.258 skrll if (!(status & UHCI_TD_ACTIVE)) {
1373 1.258 skrll done:
1374 1.258 skrll DPRINTFN(12, ("uhci_check_intr: ii=%p done\n", ii));
1375 1.264.4.7 skrll callout_stop(&ii->xfer->ux_callout);
1376 1.258 skrll uhci_idone(ii);
1377 1.258 skrll return;
1378 1.258 skrll }
1379 1.258 skrll
1380 1.258 skrll /*
1381 1.258 skrll * If the last TD is still active we need to check whether there
1382 1.258 skrll * is an error somewhere in the middle, or whether there was a
1383 1.258 skrll * short packet (SPD and not ACTIVE).
1384 1.258 skrll */
1385 1.258 skrll DPRINTFN(12, ("uhci_check_intr: active ii=%p\n", ii));
1386 1.258 skrll for (std = ii->stdstart; std != lstd; std = std->link.std) {
1387 1.258 skrll usb_syncmem(&std->dma,
1388 1.258 skrll std->offs + offsetof(uhci_td_t, td_status),
1389 1.258 skrll sizeof(std->td.td_status),
1390 1.258 skrll BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1391 1.258 skrll status = le32toh(std->td.td_status);
1392 1.258 skrll usb_syncmem(&std->dma,
1393 1.258 skrll std->offs + offsetof(uhci_td_t, td_status),
1394 1.258 skrll sizeof(std->td.td_status), BUS_DMASYNC_PREREAD);
1395 1.258 skrll
1396 1.258 skrll /* If there's an active TD the xfer isn't done. */
1397 1.258 skrll if (status & UHCI_TD_ACTIVE) {
1398 1.258 skrll DPRINTFN(12, ("%s: ii=%p std=%p still active\n",
1399 1.258 skrll __func__, ii, std));
1400 1.258 skrll return;
1401 1.258 skrll }
1402 1.258 skrll
1403 1.258 skrll /* Any kind of error makes the xfer done. */
1404 1.258 skrll if (status & UHCI_TD_STALLED)
1405 1.258 skrll goto done;
1406 1.258 skrll
1407 1.258 skrll /*
1408 1.258 skrll * If the data phase of a control transfer is short, we need
1409 1.258 skrll * to complete the status stage
1410 1.258 skrll */
1411 1.258 skrll usbd_xfer_handle xfer = ii->xfer;
1412 1.264.4.7 skrll usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc;
1413 1.258 skrll uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
1414 1.258 skrll
1415 1.258 skrll if ((status & UHCI_TD_SPD) && xfertype == UE_CONTROL) {
1416 1.258 skrll struct uhci_pipe *upipe =
1417 1.264.4.7 skrll (struct uhci_pipe *)xfer->ux_pipe;
1418 1.258 skrll uhci_soft_qh_t *sqh = upipe->u.ctl.sqh;
1419 1.258 skrll uhci_soft_td_t *stat = upipe->u.ctl.stat;
1420 1.258 skrll
1421 1.258 skrll DPRINTFN(12, ("%s: ii=%p std=%p control status"
1422 1.258 skrll "phase needs completion\n", __func__, ii,
1423 1.258 skrll ii->stdstart));
1424 1.258 skrll
1425 1.258 skrll sqh->qh.qh_elink =
1426 1.258 skrll htole32(stat->physaddr | UHCI_PTR_TD);
1427 1.258 skrll usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1428 1.258 skrll BUS_DMASYNC_PREWRITE);
1429 1.258 skrll break;
1430 1.258 skrll }
1431 1.258 skrll
1432 1.258 skrll /* We want short packets, and it is short: it's done */
1433 1.258 skrll usb_syncmem(&std->dma,
1434 1.258 skrll std->offs + offsetof(uhci_td_t, td_token),
1435 1.258 skrll sizeof(std->td.td_token),
1436 1.258 skrll BUS_DMASYNC_POSTWRITE);
1437 1.258 skrll
1438 1.258 skrll if ((status & UHCI_TD_SPD) &&
1439 1.258 skrll UHCI_TD_GET_ACTLEN(status) <
1440 1.258 skrll UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) {
1441 1.258 skrll goto done;
1442 1.18 augustss }
1443 1.1 augustss }
1444 1.1 augustss }
1445 1.1 augustss
1446 1.248 mrg /* Called with USB lock held. */
1447 1.1 augustss void
1448 1.119 augustss uhci_idone(uhci_intr_info_t *ii)
1449 1.1 augustss {
1450 1.63 augustss usbd_xfer_handle xfer = ii->xfer;
1451 1.264.4.7 skrll struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
1452 1.248 mrg #ifdef DIAGNOSTIC
1453 1.264.4.7 skrll uhci_softc_t *sc = upipe->pipe.up_dev->ud_bus->ub_hcpriv;
1454 1.248 mrg #endif
1455 1.1 augustss uhci_soft_td_t *std;
1456 1.264.4.1 skrll uint32_t status = 0, nstatus;
1457 1.26 augustss int actlen;
1458 1.1 augustss
1459 1.264.4.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1460 1.248 mrg
1461 1.140 augustss DPRINTFN(12, ("uhci_idone: ii=%p\n", ii));
1462 1.7 augustss #ifdef DIAGNOSTIC
1463 1.7 augustss {
1464 1.248 mrg /* XXX SMP? */
1465 1.7 augustss int s = splhigh();
1466 1.7 augustss if (ii->isdone) {
1467 1.26 augustss splx(s);
1468 1.92 augustss #ifdef UHCI_DEBUG
1469 1.92 augustss printf("uhci_idone: ii is done!\n ");
1470 1.92 augustss uhci_dump_ii(ii);
1471 1.92 augustss #else
1472 1.36 augustss printf("uhci_idone: ii=%p is done!\n", ii);
1473 1.92 augustss #endif
1474 1.7 augustss return;
1475 1.7 augustss }
1476 1.7 augustss ii->isdone = 1;
1477 1.7 augustss splx(s);
1478 1.7 augustss }
1479 1.7 augustss #endif
1480 1.48 augustss
1481 1.264.4.7 skrll if (xfer->ux_nframes != 0) {
1482 1.48 augustss /* Isoc transfer, do things differently. */
1483 1.48 augustss uhci_soft_td_t **stds = upipe->u.iso.stds;
1484 1.126 augustss int i, n, nframes, len;
1485 1.48 augustss
1486 1.48 augustss DPRINTFN(5,("uhci_idone: ii=%p isoc ready\n", ii));
1487 1.48 augustss
1488 1.264.4.7 skrll nframes = xfer->ux_nframes;
1489 1.48 augustss actlen = 0;
1490 1.92 augustss n = UXFER(xfer)->curframe;
1491 1.48 augustss for (i = 0; i < nframes; i++) {
1492 1.48 augustss std = stds[n];
1493 1.59 augustss #ifdef UHCI_DEBUG
1494 1.48 augustss if (uhcidebug > 5) {
1495 1.48 augustss DPRINTFN(-1,("uhci_idone: isoc TD %d\n", i));
1496 1.48 augustss uhci_dump_td(std);
1497 1.48 augustss }
1498 1.48 augustss #endif
1499 1.48 augustss if (++n >= UHCI_VFRAMELIST_COUNT)
1500 1.48 augustss n = 0;
1501 1.223 bouyer usb_syncmem(&std->dma,
1502 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
1503 1.223 bouyer sizeof(std->td.td_status),
1504 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1505 1.88 tsutsui status = le32toh(std->td.td_status);
1506 1.126 augustss len = UHCI_TD_GET_ACTLEN(status);
1507 1.264.4.7 skrll xfer->ux_frlengths[i] = len;
1508 1.126 augustss actlen += len;
1509 1.48 augustss }
1510 1.48 augustss upipe->u.iso.inuse -= nframes;
1511 1.264.4.7 skrll xfer->ux_actlen = actlen;
1512 1.264.4.7 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1513 1.140 augustss goto end;
1514 1.48 augustss }
1515 1.48 augustss
1516 1.59 augustss #ifdef UHCI_DEBUG
1517 1.65 augustss DPRINTFN(10, ("uhci_idone: ii=%p, xfer=%p, pipe=%p ready\n",
1518 1.65 augustss ii, xfer, upipe));
1519 1.48 augustss if (uhcidebug > 10)
1520 1.48 augustss uhci_dump_tds(ii->stdstart);
1521 1.48 augustss #endif
1522 1.48 augustss
1523 1.26 augustss /* The transfer is done, compute actual length and status. */
1524 1.26 augustss actlen = 0;
1525 1.63 augustss for (std = ii->stdstart; std != NULL; std = std->link.std) {
1526 1.223 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
1527 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1528 1.88 tsutsui nstatus = le32toh(std->td.td_status);
1529 1.64 augustss if (nstatus & UHCI_TD_ACTIVE)
1530 1.26 augustss break;
1531 1.67 augustss
1532 1.64 augustss status = nstatus;
1533 1.88 tsutsui if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) !=
1534 1.88 tsutsui UHCI_TD_PID_SETUP)
1535 1.26 augustss actlen += UHCI_TD_GET_ACTLEN(status);
1536 1.176 mycroft else {
1537 1.176 mycroft /*
1538 1.176 mycroft * UHCI will report CRCTO in addition to a STALL or NAK
1539 1.176 mycroft * for a SETUP transaction. See section 3.2.2, "TD
1540 1.176 mycroft * CONTROL AND STATUS".
1541 1.176 mycroft */
1542 1.176 mycroft if (status & (UHCI_TD_STALLED | UHCI_TD_NAK))
1543 1.176 mycroft status &= ~UHCI_TD_CRCTO;
1544 1.176 mycroft }
1545 1.1 augustss }
1546 1.38 augustss /* If there are left over TDs we need to update the toggle. */
1547 1.63 augustss if (std != NULL)
1548 1.88 tsutsui upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token));
1549 1.38 augustss
1550 1.1 augustss status &= UHCI_TD_ERROR;
1551 1.152 augustss DPRINTFN(10, ("uhci_idone: actlen=%d, status=0x%x\n",
1552 1.26 augustss actlen, status));
1553 1.264.4.7 skrll xfer->ux_actlen = actlen;
1554 1.1 augustss if (status != 0) {
1555 1.122 tv #ifdef UHCI_DEBUG
1556 1.122 tv char sbuf[128];
1557 1.122 tv
1558 1.224 christos snprintb(sbuf, sizeof(sbuf),
1559 1.224 christos "\20\22BITSTUFF\23CRCTO\24NAK\25"
1560 1.264.4.1 skrll "BABBLE\26DBUFFER\27STALLED\30ACTIVE",(uint32_t)status);
1561 1.122 tv
1562 1.75 augustss DPRINTFN((status == UHCI_TD_STALLED)*10,
1563 1.36 augustss ("uhci_idone: error, addr=%d, endpt=0x%02x, "
1564 1.122 tv "status 0x%s\n",
1565 1.264.4.7 skrll xfer->ux_pipe->up_dev->ud_addr,
1566 1.264.4.7 skrll xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress,
1567 1.122 tv sbuf));
1568 1.122 tv #endif
1569 1.122 tv
1570 1.1 augustss if (status == UHCI_TD_STALLED)
1571 1.264.4.7 skrll xfer->ux_status = USBD_STALLED;
1572 1.1 augustss else
1573 1.264.4.7 skrll xfer->ux_status = USBD_IOERROR; /* more info XXX */
1574 1.1 augustss } else {
1575 1.264.4.7 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1576 1.1 augustss }
1577 1.140 augustss
1578 1.140 augustss end:
1579 1.63 augustss usb_transfer_complete(xfer);
1580 1.264.4.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1581 1.140 augustss DPRINTFN(12, ("uhci_idone: ii=%p done\n", ii));
1582 1.1 augustss }
1583 1.1 augustss
1584 1.13 augustss /*
1585 1.13 augustss * Called when a request does not complete.
1586 1.13 augustss */
1587 1.1 augustss void
1588 1.119 augustss uhci_timeout(void *addr)
1589 1.1 augustss {
1590 1.1 augustss uhci_intr_info_t *ii = addr;
1591 1.153 augustss struct uhci_xfer *uxfer = UXFER(ii->xfer);
1592 1.264.4.7 skrll struct uhci_pipe *upipe = (struct uhci_pipe *)uxfer->xfer.ux_pipe;
1593 1.264.4.7 skrll uhci_softc_t *sc = upipe->pipe.up_dev->ud_bus->ub_hcpriv;
1594 1.153 augustss
1595 1.153 augustss DPRINTF(("uhci_timeout: uxfer=%p\n", uxfer));
1596 1.153 augustss
1597 1.153 augustss if (sc->sc_dying) {
1598 1.248 mrg mutex_enter(&sc->sc_lock);
1599 1.153 augustss uhci_abort_xfer(&uxfer->xfer, USBD_TIMEOUT);
1600 1.248 mrg mutex_exit(&sc->sc_lock);
1601 1.153 augustss return;
1602 1.153 augustss }
1603 1.1 augustss
1604 1.153 augustss /* Execute the abort in a process context. */
1605 1.252 jmcneill usb_init_task(&uxfer->abort_task, uhci_timeout_task, ii->xfer,
1606 1.252 jmcneill USB_TASKQ_MPSAFE);
1607 1.264.4.7 skrll usb_add_task(uxfer->xfer.ux_pipe->up_dev, &uxfer->abort_task,
1608 1.204 joerg USB_TASKQ_HC);
1609 1.153 augustss }
1610 1.51 augustss
1611 1.153 augustss void
1612 1.153 augustss uhci_timeout_task(void *addr)
1613 1.153 augustss {
1614 1.153 augustss usbd_xfer_handle xfer = addr;
1615 1.264.4.7 skrll uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
1616 1.153 augustss
1617 1.153 augustss DPRINTF(("uhci_timeout_task: xfer=%p\n", xfer));
1618 1.67 augustss
1619 1.248 mrg mutex_enter(&sc->sc_lock);
1620 1.153 augustss uhci_abort_xfer(xfer, USBD_TIMEOUT);
1621 1.248 mrg mutex_exit(&sc->sc_lock);
1622 1.1 augustss }
1623 1.1 augustss
1624 1.1 augustss /*
1625 1.1 augustss * Wait here until controller claims to have an interrupt.
1626 1.1 augustss * Then call uhci_intr and return. Use timeout to avoid waiting
1627 1.1 augustss * too long.
1628 1.13 augustss * Only used during boot when interrupts are not enabled yet.
1629 1.1 augustss */
1630 1.1 augustss void
1631 1.119 augustss uhci_waitintr(uhci_softc_t *sc, usbd_xfer_handle xfer)
1632 1.1 augustss {
1633 1.264.4.7 skrll int timo = xfer->ux_timeout;
1634 1.13 augustss uhci_intr_info_t *ii;
1635 1.13 augustss
1636 1.248 mrg mutex_enter(&sc->sc_lock);
1637 1.248 mrg
1638 1.26 augustss DPRINTFN(10,("uhci_waitintr: timeout = %dms\n", timo));
1639 1.1 augustss
1640 1.264.4.7 skrll xfer->ux_status = USBD_IN_PROGRESS;
1641 1.26 augustss for (; timo >= 0; timo--) {
1642 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_lock);
1643 1.26 augustss DPRINTFN(20,("uhci_waitintr: 0x%04x\n", UREAD2(sc, UHCI_STS)));
1644 1.1 augustss if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) {
1645 1.248 mrg mutex_spin_enter(&sc->sc_intr_lock);
1646 1.141 augustss uhci_intr1(sc);
1647 1.248 mrg mutex_spin_exit(&sc->sc_intr_lock);
1648 1.264.4.7 skrll if (xfer->ux_status != USBD_IN_PROGRESS)
1649 1.248 mrg goto done;
1650 1.1 augustss }
1651 1.1 augustss }
1652 1.13 augustss
1653 1.13 augustss /* Timeout */
1654 1.13 augustss DPRINTF(("uhci_waitintr: timeout\n"));
1655 1.13 augustss for (ii = LIST_FIRST(&sc->sc_intrhead);
1656 1.152 augustss ii != NULL && ii->xfer != xfer;
1657 1.13 augustss ii = LIST_NEXT(ii, list))
1658 1.13 augustss ;
1659 1.41 augustss #ifdef DIAGNOSTIC
1660 1.63 augustss if (ii == NULL)
1661 1.163 provos panic("uhci_waitintr: lost intr_info");
1662 1.41 augustss #endif
1663 1.41 augustss uhci_idone(ii);
1664 1.248 mrg
1665 1.248 mrg done:
1666 1.248 mrg mutex_exit(&sc->sc_lock);
1667 1.1 augustss }
1668 1.1 augustss
1669 1.8 augustss void
1670 1.119 augustss uhci_poll(struct usbd_bus *bus)
1671 1.8 augustss {
1672 1.264.4.7 skrll uhci_softc_t *sc = bus->ub_hcpriv;
1673 1.8 augustss
1674 1.248 mrg if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) {
1675 1.248 mrg mutex_spin_enter(&sc->sc_intr_lock);
1676 1.141 augustss uhci_intr1(sc);
1677 1.248 mrg mutex_spin_exit(&sc->sc_intr_lock);
1678 1.248 mrg }
1679 1.8 augustss }
1680 1.8 augustss
1681 1.1 augustss void
1682 1.119 augustss uhci_reset(uhci_softc_t *sc)
1683 1.1 augustss {
1684 1.1 augustss int n;
1685 1.1 augustss
1686 1.1 augustss UHCICMD(sc, UHCI_CMD_HCRESET);
1687 1.1 augustss /* The reset bit goes low when the controller is done. */
1688 1.152 augustss for (n = 0; n < UHCI_RESET_TIMEOUT &&
1689 1.1 augustss (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++)
1690 1.92 augustss usb_delay_ms(&sc->sc_bus, 1);
1691 1.1 augustss if (n >= UHCI_RESET_TIMEOUT)
1692 1.152 augustss printf("%s: controller did not reset\n",
1693 1.216 drochner device_xname(sc->sc_dev));
1694 1.1 augustss }
1695 1.1 augustss
1696 1.16 augustss usbd_status
1697 1.249 drochner uhci_run(uhci_softc_t *sc, int run, int locked)
1698 1.1 augustss {
1699 1.248 mrg int n, running;
1700 1.264.4.1 skrll uint16_t cmd;
1701 1.1 augustss
1702 1.1 augustss run = run != 0;
1703 1.249 drochner if (!locked)
1704 1.249 drochner mutex_spin_enter(&sc->sc_intr_lock);
1705 1.30 augustss DPRINTF(("uhci_run: setting run=%d\n", run));
1706 1.71 augustss cmd = UREAD2(sc, UHCI_CMD);
1707 1.71 augustss if (run)
1708 1.71 augustss cmd |= UHCI_CMD_RS;
1709 1.71 augustss else
1710 1.71 augustss cmd &= ~UHCI_CMD_RS;
1711 1.71 augustss UHCICMD(sc, cmd);
1712 1.13 augustss for(n = 0; n < 10; n++) {
1713 1.1 augustss running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH);
1714 1.1 augustss /* return when we've entered the state we want */
1715 1.1 augustss if (run == running) {
1716 1.249 drochner if (!locked)
1717 1.249 drochner mutex_spin_exit(&sc->sc_intr_lock);
1718 1.30 augustss DPRINTF(("uhci_run: done cmd=0x%x sts=0x%x\n",
1719 1.30 augustss UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS)));
1720 1.264.4.13 skrll return USBD_NORMAL_COMPLETION;
1721 1.1 augustss }
1722 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock);
1723 1.1 augustss }
1724 1.249 drochner if (!locked)
1725 1.249 drochner mutex_spin_exit(&sc->sc_intr_lock);
1726 1.216 drochner printf("%s: cannot %s\n", device_xname(sc->sc_dev),
1727 1.14 augustss run ? "start" : "stop");
1728 1.264.4.13 skrll return USBD_IOERROR;
1729 1.1 augustss }
1730 1.1 augustss
1731 1.1 augustss /*
1732 1.1 augustss * Memory management routines.
1733 1.1 augustss * uhci_alloc_std allocates TDs
1734 1.1 augustss * uhci_alloc_sqh allocates QHs
1735 1.7 augustss * These two routines do their own free list management,
1736 1.1 augustss * partly for speed, partly because allocating DMAable memory
1737 1.1 augustss * has page size granularaity so much memory would be wasted if
1738 1.16 augustss * only one TD/QH (32 bytes) was placed in each allocated chunk.
1739 1.1 augustss */
1740 1.1 augustss
1741 1.1 augustss uhci_soft_td_t *
1742 1.119 augustss uhci_alloc_std(uhci_softc_t *sc)
1743 1.1 augustss {
1744 1.1 augustss uhci_soft_td_t *std;
1745 1.63 augustss usbd_status err;
1746 1.42 augustss int i, offs;
1747 1.7 augustss usb_dma_t dma;
1748 1.1 augustss
1749 1.63 augustss if (sc->sc_freetds == NULL) {
1750 1.1 augustss DPRINTFN(2,("uhci_alloc_std: allocating chunk\n"));
1751 1.63 augustss err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK,
1752 1.63 augustss UHCI_TD_ALIGN, &dma);
1753 1.63 augustss if (err)
1754 1.264.4.13 skrll return 0;
1755 1.248 mrg for (i = 0; i < UHCI_STD_CHUNK; i++) {
1756 1.42 augustss offs = i * UHCI_STD_SIZE;
1757 1.159 augustss std = KERNADDR(&dma, offs);
1758 1.160 augustss std->physaddr = DMAADDR(&dma, offs);
1759 1.223 bouyer std->dma = dma;
1760 1.223 bouyer std->offs = offs;
1761 1.42 augustss std->link.std = sc->sc_freetds;
1762 1.1 augustss sc->sc_freetds = std;
1763 1.1 augustss }
1764 1.1 augustss }
1765 1.1 augustss std = sc->sc_freetds;
1766 1.42 augustss sc->sc_freetds = std->link.std;
1767 1.42 augustss memset(&std->td, 0, sizeof(uhci_td_t));
1768 1.1 augustss return std;
1769 1.1 augustss }
1770 1.1 augustss
1771 1.1 augustss void
1772 1.119 augustss uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std)
1773 1.1 augustss {
1774 1.7 augustss #ifdef DIAGNOSTIC
1775 1.7 augustss #define TD_IS_FREE 0x12345678
1776 1.88 tsutsui if (le32toh(std->td.td_token) == TD_IS_FREE) {
1777 1.7 augustss printf("uhci_free_std: freeing free TD %p\n", std);
1778 1.7 augustss return;
1779 1.7 augustss }
1780 1.88 tsutsui std->td.td_token = htole32(TD_IS_FREE);
1781 1.7 augustss #endif
1782 1.42 augustss std->link.std = sc->sc_freetds;
1783 1.1 augustss sc->sc_freetds = std;
1784 1.1 augustss }
1785 1.1 augustss
1786 1.1 augustss uhci_soft_qh_t *
1787 1.119 augustss uhci_alloc_sqh(uhci_softc_t *sc)
1788 1.1 augustss {
1789 1.1 augustss uhci_soft_qh_t *sqh;
1790 1.63 augustss usbd_status err;
1791 1.1 augustss int i, offs;
1792 1.7 augustss usb_dma_t dma;
1793 1.1 augustss
1794 1.63 augustss if (sc->sc_freeqhs == NULL) {
1795 1.1 augustss DPRINTFN(2, ("uhci_alloc_sqh: allocating chunk\n"));
1796 1.63 augustss err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK,
1797 1.63 augustss UHCI_QH_ALIGN, &dma);
1798 1.63 augustss if (err)
1799 1.264.4.13 skrll return 0;
1800 1.43 augustss for(i = 0; i < UHCI_SQH_CHUNK; i++) {
1801 1.42 augustss offs = i * UHCI_SQH_SIZE;
1802 1.159 augustss sqh = KERNADDR(&dma, offs);
1803 1.160 augustss sqh->physaddr = DMAADDR(&dma, offs);
1804 1.223 bouyer sqh->dma = dma;
1805 1.223 bouyer sqh->offs = offs;
1806 1.42 augustss sqh->hlink = sc->sc_freeqhs;
1807 1.1 augustss sc->sc_freeqhs = sqh;
1808 1.1 augustss }
1809 1.1 augustss }
1810 1.1 augustss sqh = sc->sc_freeqhs;
1811 1.42 augustss sc->sc_freeqhs = sqh->hlink;
1812 1.42 augustss memset(&sqh->qh, 0, sizeof(uhci_qh_t));
1813 1.264.4.13 skrll return sqh;
1814 1.1 augustss }
1815 1.1 augustss
1816 1.1 augustss void
1817 1.119 augustss uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1818 1.1 augustss {
1819 1.42 augustss sqh->hlink = sc->sc_freeqhs;
1820 1.1 augustss sc->sc_freeqhs = sqh;
1821 1.1 augustss }
1822 1.1 augustss
1823 1.1 augustss void
1824 1.119 augustss uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std,
1825 1.119 augustss uhci_soft_td_t *stdend)
1826 1.1 augustss {
1827 1.1 augustss uhci_soft_td_t *p;
1828 1.256 tsutsui uint32_t td_link;
1829 1.1 augustss
1830 1.223 bouyer /*
1831 1.223 bouyer * to avoid race condition with the controller which may be looking
1832 1.223 bouyer * at this chain, we need to first invalidate all links, and
1833 1.223 bouyer * then wait for the controller to move to another queue
1834 1.223 bouyer */
1835 1.223 bouyer for (p = std; p != stdend; p = p->link.std) {
1836 1.223 bouyer usb_syncmem(&p->dma,
1837 1.223 bouyer p->offs + offsetof(uhci_td_t, td_link),
1838 1.223 bouyer sizeof(p->td.td_link),
1839 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1840 1.256 tsutsui td_link = le32toh(p->td.td_link);
1841 1.256 tsutsui usb_syncmem(&p->dma,
1842 1.256 tsutsui p->offs + offsetof(uhci_td_t, td_link),
1843 1.256 tsutsui sizeof(p->td.td_link),
1844 1.256 tsutsui BUS_DMASYNC_PREREAD);
1845 1.256 tsutsui if ((td_link & UHCI_PTR_T) == 0) {
1846 1.255 tsutsui p->td.td_link = htole32(UHCI_PTR_T);
1847 1.223 bouyer usb_syncmem(&p->dma,
1848 1.223 bouyer p->offs + offsetof(uhci_td_t, td_link),
1849 1.223 bouyer sizeof(p->td.td_link),
1850 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1851 1.223 bouyer }
1852 1.223 bouyer }
1853 1.223 bouyer delay(UHCI_QH_REMOVE_DELAY);
1854 1.223 bouyer
1855 1.1 augustss for (; std != stdend; std = p) {
1856 1.42 augustss p = std->link.std;
1857 1.1 augustss uhci_free_std(sc, std);
1858 1.1 augustss }
1859 1.1 augustss }
1860 1.1 augustss
1861 1.1 augustss usbd_status
1862 1.119 augustss uhci_alloc_std_chain(struct uhci_pipe *upipe, uhci_softc_t *sc, int len,
1863 1.264.4.1 skrll int rd, uint16_t flags, usb_dma_t *dma,
1864 1.119 augustss uhci_soft_td_t **sp, uhci_soft_td_t **ep)
1865 1.1 augustss {
1866 1.1 augustss uhci_soft_td_t *p, *lastp;
1867 1.1 augustss uhci_physaddr_t lastlink;
1868 1.1 augustss int i, ntd, l, tog, maxp;
1869 1.264.4.1 skrll uint32_t status;
1870 1.264.4.7 skrll int addr = upipe->pipe.up_dev->ud_addr;
1871 1.264.4.7 skrll int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
1872 1.1 augustss
1873 1.144 augustss DPRINTFN(8, ("uhci_alloc_std_chain: addr=%d endpt=%d len=%d speed=%d "
1874 1.152 augustss "flags=0x%x\n", addr, UE_GET_ADDR(endpt), len,
1875 1.264.4.7 skrll upipe->pipe.up_dev->ud_speed, flags));
1876 1.248 mrg
1877 1.264.4.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1878 1.248 mrg
1879 1.264.4.7 skrll maxp = UGETW(upipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize);
1880 1.1 augustss if (maxp == 0) {
1881 1.1 augustss printf("uhci_alloc_std_chain: maxp=0\n");
1882 1.264.4.13 skrll return USBD_INVAL;
1883 1.1 augustss }
1884 1.1 augustss ntd = (len + maxp - 1) / maxp;
1885 1.73 augustss if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0)
1886 1.73 augustss ntd++;
1887 1.39 augustss DPRINTFN(10, ("uhci_alloc_std_chain: maxp=%d ntd=%d\n", maxp, ntd));
1888 1.73 augustss if (ntd == 0) {
1889 1.73 augustss *sp = *ep = 0;
1890 1.73 augustss DPRINTFN(-1,("uhci_alloc_std_chain: ntd=0\n"));
1891 1.264.4.13 skrll return USBD_NORMAL_COMPLETION;
1892 1.73 augustss }
1893 1.38 augustss tog = upipe->nexttoggle;
1894 1.1 augustss if (ntd % 2 == 0)
1895 1.1 augustss tog ^= 1;
1896 1.32 augustss upipe->nexttoggle = tog ^ 1;
1897 1.121 augustss lastp = NULL;
1898 1.1 augustss lastlink = UHCI_PTR_T;
1899 1.1 augustss ntd--;
1900 1.33 augustss status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE);
1901 1.264.4.7 skrll if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW)
1902 1.18 augustss status |= UHCI_TD_LS;
1903 1.73 augustss if (flags & USBD_SHORT_XFER_OK)
1904 1.18 augustss status |= UHCI_TD_SPD;
1905 1.223 bouyer usb_syncmem(dma, 0, len,
1906 1.223 bouyer rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
1907 1.1 augustss for (i = ntd; i >= 0; i--) {
1908 1.1 augustss p = uhci_alloc_std(sc);
1909 1.63 augustss if (p == NULL) {
1910 1.202 christos KASSERT(lastp != NULL);
1911 1.149 augustss uhci_free_std_chain(sc, lastp, NULL);
1912 1.264.4.13 skrll return USBD_NOMEM;
1913 1.1 augustss }
1914 1.42 augustss p->link.std = lastp;
1915 1.121 augustss p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD);
1916 1.1 augustss lastp = p;
1917 1.1 augustss lastlink = p->physaddr;
1918 1.88 tsutsui p->td.td_status = htole32(status);
1919 1.1 augustss if (i == ntd) {
1920 1.1 augustss /* last TD */
1921 1.1 augustss l = len % maxp;
1922 1.73 augustss if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER))
1923 1.73 augustss l = maxp;
1924 1.1 augustss *ep = p;
1925 1.1 augustss } else
1926 1.1 augustss l = maxp;
1927 1.152 augustss p->td.td_token =
1928 1.88 tsutsui htole32(rd ? UHCI_TD_IN (l, endpt, addr, tog) :
1929 1.88 tsutsui UHCI_TD_OUT(l, endpt, addr, tog));
1930 1.160 augustss p->td.td_buffer = htole32(DMAADDR(dma, i * maxp));
1931 1.223 bouyer usb_syncmem(&p->dma, p->offs, sizeof(p->td),
1932 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1933 1.1 augustss tog ^= 1;
1934 1.1 augustss }
1935 1.1 augustss *sp = lastp;
1936 1.152 augustss DPRINTFN(10, ("uhci_alloc_std_chain: nexttog=%d\n",
1937 1.38 augustss upipe->nexttoggle));
1938 1.264.4.13 skrll return USBD_NORMAL_COMPLETION;
1939 1.1 augustss }
1940 1.1 augustss
1941 1.38 augustss void
1942 1.119 augustss uhci_device_clear_toggle(usbd_pipe_handle pipe)
1943 1.38 augustss {
1944 1.38 augustss struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;
1945 1.38 augustss upipe->nexttoggle = 0;
1946 1.38 augustss }
1947 1.38 augustss
1948 1.38 augustss void
1949 1.205 christos uhci_noop(usbd_pipe_handle pipe)
1950 1.38 augustss {
1951 1.38 augustss }
1952 1.38 augustss
1953 1.1 augustss usbd_status
1954 1.119 augustss uhci_device_bulk_transfer(usbd_xfer_handle xfer)
1955 1.1 augustss {
1956 1.264.4.7 skrll uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
1957 1.63 augustss usbd_status err;
1958 1.16 augustss
1959 1.52 augustss /* Insert last in queue. */
1960 1.248 mrg mutex_enter(&sc->sc_lock);
1961 1.63 augustss err = usb_insert_transfer(xfer);
1962 1.248 mrg mutex_exit(&sc->sc_lock);
1963 1.63 augustss if (err)
1964 1.264.4.13 skrll return err;
1965 1.52 augustss
1966 1.152 augustss /*
1967 1.92 augustss * Pipe isn't running (otherwise err would be USBD_INPROG),
1968 1.92 augustss * so start it first.
1969 1.67 augustss */
1970 1.264.4.13 skrll return uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
1971 1.16 augustss }
1972 1.16 augustss
1973 1.16 augustss usbd_status
1974 1.119 augustss uhci_device_bulk_start(usbd_xfer_handle xfer)
1975 1.16 augustss {
1976 1.264.4.7 skrll struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
1977 1.264.4.7 skrll usbd_device_handle dev = upipe->pipe.up_dev;
1978 1.264.4.7 skrll uhci_softc_t *sc = dev->ud_bus->ub_hcpriv;
1979 1.92 augustss uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
1980 1.55 augustss uhci_soft_td_t *data, *dataend;
1981 1.1 augustss uhci_soft_qh_t *sqh;
1982 1.63 augustss usbd_status err;
1983 1.45 augustss int len, isread, endpt;
1984 1.1 augustss
1985 1.169 augustss DPRINTFN(3, ("uhci_device_bulk_start: xfer=%p len=%d flags=%d ii=%p\n",
1986 1.264.4.7 skrll xfer, xfer->ux_length, xfer->ux_flags, ii));
1987 1.1 augustss
1988 1.82 augustss if (sc->sc_dying)
1989 1.264.4.13 skrll return USBD_IOERROR;
1990 1.82 augustss
1991 1.48 augustss #ifdef DIAGNOSTIC
1992 1.264.4.7 skrll if (xfer->ux_rqflags & URQ_REQUEST)
1993 1.163 provos panic("uhci_device_bulk_transfer: a request");
1994 1.48 augustss #endif
1995 1.1 augustss
1996 1.248 mrg mutex_enter(&sc->sc_lock);
1997 1.248 mrg
1998 1.264.4.7 skrll len = xfer->ux_length;
1999 1.264.4.7 skrll endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
2000 1.45 augustss isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2001 1.1 augustss sqh = upipe->u.bulk.sqh;
2002 1.1 augustss
2003 1.1 augustss upipe->u.bulk.isread = isread;
2004 1.1 augustss upipe->u.bulk.length = len;
2005 1.1 augustss
2006 1.264.4.7 skrll err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->ux_flags,
2007 1.264.4.7 skrll &xfer->ux_dmabuf, &data, &dataend);
2008 1.248 mrg if (err) {
2009 1.248 mrg mutex_exit(&sc->sc_lock);
2010 1.264.4.13 skrll return err;
2011 1.248 mrg }
2012 1.88 tsutsui dataend->td.td_status |= htole32(UHCI_TD_IOC);
2013 1.223 bouyer usb_syncmem(&dataend->dma,
2014 1.223 bouyer dataend->offs + offsetof(uhci_td_t, td_status),
2015 1.223 bouyer sizeof(dataend->td.td_status),
2016 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2017 1.223 bouyer
2018 1.1 augustss
2019 1.59 augustss #ifdef UHCI_DEBUG
2020 1.33 augustss if (uhcidebug > 8) {
2021 1.55 augustss DPRINTF(("uhci_device_bulk_transfer: data(1)\n"));
2022 1.55 augustss uhci_dump_tds(data);
2023 1.1 augustss }
2024 1.1 augustss #endif
2025 1.1 augustss
2026 1.1 augustss /* Set up interrupt info. */
2027 1.63 augustss ii->xfer = xfer;
2028 1.55 augustss ii->stdstart = data;
2029 1.55 augustss ii->stdend = dataend;
2030 1.7 augustss #ifdef DIAGNOSTIC
2031 1.70 augustss if (!ii->isdone) {
2032 1.70 augustss printf("uhci_device_bulk_transfer: not done, ii=%p\n", ii);
2033 1.70 augustss }
2034 1.7 augustss ii->isdone = 0;
2035 1.7 augustss #endif
2036 1.1 augustss
2037 1.55 augustss sqh->elink = data;
2038 1.121 augustss sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD);
2039 1.223 bouyer /* uhci_add_bulk() will do usb_syncmem(sqh) */
2040 1.1 augustss
2041 1.1 augustss uhci_add_bulk(sc, sqh);
2042 1.92 augustss uhci_add_intr_info(sc, ii);
2043 1.1 augustss
2044 1.264.4.7 skrll if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
2045 1.264.4.7 skrll callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
2046 1.91 augustss uhci_timeout, ii);
2047 1.13 augustss }
2048 1.264.4.7 skrll xfer->ux_status = USBD_IN_PROGRESS;
2049 1.1 augustss
2050 1.59 augustss #ifdef UHCI_DEBUG
2051 1.1 augustss if (uhcidebug > 10) {
2052 1.55 augustss DPRINTF(("uhci_device_bulk_transfer: data(2)\n"));
2053 1.55 augustss uhci_dump_tds(data);
2054 1.1 augustss }
2055 1.1 augustss #endif
2056 1.1 augustss
2057 1.264.4.7 skrll if (sc->sc_bus.ub_usepolling)
2058 1.63 augustss uhci_waitintr(sc, xfer);
2059 1.26 augustss
2060 1.248 mrg mutex_exit(&sc->sc_lock);
2061 1.264.4.13 skrll return USBD_IN_PROGRESS;
2062 1.1 augustss }
2063 1.1 augustss
2064 1.1 augustss /* Abort a device bulk request. */
2065 1.1 augustss void
2066 1.119 augustss uhci_device_bulk_abort(usbd_xfer_handle xfer)
2067 1.1 augustss {
2068 1.248 mrg #ifdef DIAGNOSTIC
2069 1.264.4.7 skrll uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
2070 1.248 mrg #endif
2071 1.248 mrg
2072 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2073 1.248 mrg
2074 1.33 augustss DPRINTF(("uhci_device_bulk_abort:\n"));
2075 1.66 augustss uhci_abort_xfer(xfer, USBD_CANCELLED);
2076 1.33 augustss }
2077 1.33 augustss
2078 1.92 augustss /*
2079 1.154 augustss * Abort a device request.
2080 1.154 augustss * If this routine is called at splusb() it guarantees that the request
2081 1.154 augustss * will be removed from the hardware scheduling and that the callback
2082 1.154 augustss * for it will be called with USBD_CANCELLED status.
2083 1.154 augustss * It's impossible to guarantee that the requested transfer will not
2084 1.154 augustss * have happened since the hardware runs concurrently.
2085 1.154 augustss * If the transaction has already happened we rely on the ordinary
2086 1.154 augustss * interrupt processing to process it.
2087 1.248 mrg * XXX This is most probably wrong.
2088 1.248 mrg * XXXMRG this doesn't make sense anymore.
2089 1.92 augustss */
2090 1.33 augustss void
2091 1.119 augustss uhci_abort_xfer(usbd_xfer_handle xfer, usbd_status status)
2092 1.33 augustss {
2093 1.92 augustss uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
2094 1.264.4.7 skrll struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
2095 1.264.4.7 skrll uhci_softc_t *sc = upipe->pipe.up_dev->ud_bus->ub_hcpriv;
2096 1.33 augustss uhci_soft_td_t *std;
2097 1.188 augustss int wake;
2098 1.65 augustss
2099 1.106 augustss DPRINTFN(1,("uhci_abort_xfer: xfer=%p, status=%d\n", xfer, status));
2100 1.33 augustss
2101 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2102 1.264.4.3 skrll ASSERT_SLEEPABLE();
2103 1.248 mrg
2104 1.153 augustss if (sc->sc_dying) {
2105 1.153 augustss /* If we're dying, just do the software part. */
2106 1.264.4.7 skrll xfer->ux_status = status; /* make software ignore it */
2107 1.264.4.7 skrll callout_stop(&xfer->ux_callout);
2108 1.153 augustss usb_transfer_complete(xfer);
2109 1.194 christos return;
2110 1.92 augustss }
2111 1.92 augustss
2112 1.153 augustss /*
2113 1.188 augustss * If an abort is already in progress then just wait for it to
2114 1.188 augustss * complete and return.
2115 1.188 augustss */
2116 1.264.4.7 skrll if (xfer->ux_hcflags & UXFER_ABORTING) {
2117 1.188 augustss DPRINTFN(2, ("uhci_abort_xfer: already aborting\n"));
2118 1.188 augustss #ifdef DIAGNOSTIC
2119 1.188 augustss if (status == USBD_TIMEOUT)
2120 1.188 augustss printf("uhci_abort_xfer: TIMEOUT while aborting\n");
2121 1.188 augustss #endif
2122 1.188 augustss /* Override the status which might be USBD_TIMEOUT. */
2123 1.264.4.7 skrll xfer->ux_status = status;
2124 1.188 augustss DPRINTFN(2, ("uhci_abort_xfer: waiting for abort to finish\n"));
2125 1.264.4.7 skrll xfer->ux_hcflags |= UXFER_ABORTWAIT;
2126 1.264.4.7 skrll while (xfer->ux_hcflags & UXFER_ABORTING)
2127 1.264.4.7 skrll cv_wait(&xfer->ux_hccv, &sc->sc_lock);
2128 1.248 mrg goto done;
2129 1.188 augustss }
2130 1.264.4.7 skrll xfer->ux_hcflags |= UXFER_ABORTING;
2131 1.188 augustss
2132 1.188 augustss /*
2133 1.153 augustss * Step 1: Make interrupt routine and hardware ignore xfer.
2134 1.153 augustss */
2135 1.264.4.7 skrll xfer->ux_status = status; /* make software ignore it */
2136 1.264.4.7 skrll callout_stop(&xfer->ux_callout);
2137 1.153 augustss DPRINTFN(1,("uhci_abort_xfer: stop ii=%p\n", ii));
2138 1.223 bouyer for (std = ii->stdstart; std != NULL; std = std->link.std) {
2139 1.223 bouyer usb_syncmem(&std->dma,
2140 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
2141 1.223 bouyer sizeof(std->td.td_status),
2142 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2143 1.92 augustss std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC));
2144 1.223 bouyer usb_syncmem(&std->dma,
2145 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
2146 1.223 bouyer sizeof(std->td.td_status),
2147 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2148 1.223 bouyer }
2149 1.92 augustss
2150 1.162 augustss /*
2151 1.153 augustss * Step 2: Wait until we know hardware has finished any possible
2152 1.153 augustss * use of the xfer. Also make sure the soft interrupt routine
2153 1.153 augustss * has run.
2154 1.153 augustss */
2155 1.248 mrg /* Hardware finishes in 1ms */
2156 1.264.4.7 skrll usb_delay_ms_locked(upipe->pipe.up_dev->ud_bus, 2, &sc->sc_lock);
2157 1.153 augustss sc->sc_softwake = 1;
2158 1.153 augustss usb_schedsoftintr(&sc->sc_bus);
2159 1.248 mrg DPRINTFN(1,("uhci_abort_xfer: cv_wait\n"));
2160 1.248 mrg cv_wait(&sc->sc_softwake_cv, &sc->sc_lock);
2161 1.162 augustss
2162 1.153 augustss /*
2163 1.153 augustss * Step 3: Execute callback.
2164 1.153 augustss */
2165 1.154 augustss DPRINTFN(1,("uhci_abort_xfer: callback\n"));
2166 1.100 augustss #ifdef DIAGNOSTIC
2167 1.106 augustss ii->isdone = 1;
2168 1.100 augustss #endif
2169 1.264.4.7 skrll wake = xfer->ux_hcflags & UXFER_ABORTWAIT;
2170 1.264.4.7 skrll xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT);
2171 1.106 augustss usb_transfer_complete(xfer);
2172 1.188 augustss if (wake)
2173 1.264.4.7 skrll cv_broadcast(&xfer->ux_hccv);
2174 1.248 mrg done:
2175 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2176 1.1 augustss }
2177 1.1 augustss
2178 1.1 augustss /* Close a device bulk pipe. */
2179 1.1 augustss void
2180 1.119 augustss uhci_device_bulk_close(usbd_pipe_handle pipe)
2181 1.1 augustss {
2182 1.1 augustss struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;
2183 1.264.4.7 skrll usbd_device_handle dev = upipe->pipe.up_dev;
2184 1.264.4.7 skrll uhci_softc_t *sc = dev->ud_bus->ub_hcpriv;
2185 1.1 augustss
2186 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2187 1.248 mrg
2188 1.1 augustss uhci_free_sqh(sc, upipe->u.bulk.sqh);
2189 1.236 drochner
2190 1.264.4.7 skrll pipe->up_endpoint->ue_toggle = upipe->nexttoggle;
2191 1.1 augustss }
2192 1.1 augustss
2193 1.1 augustss usbd_status
2194 1.119 augustss uhci_device_ctrl_transfer(usbd_xfer_handle xfer)
2195 1.1 augustss {
2196 1.264.4.7 skrll uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
2197 1.63 augustss usbd_status err;
2198 1.16 augustss
2199 1.52 augustss /* Insert last in queue. */
2200 1.248 mrg mutex_enter(&sc->sc_lock);
2201 1.63 augustss err = usb_insert_transfer(xfer);
2202 1.248 mrg mutex_exit(&sc->sc_lock);
2203 1.63 augustss if (err)
2204 1.264.4.13 skrll return err;
2205 1.52 augustss
2206 1.152 augustss /*
2207 1.92 augustss * Pipe isn't running (otherwise err would be USBD_INPROG),
2208 1.92 augustss * so start it first.
2209 1.67 augustss */
2210 1.264.4.13 skrll return uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2211 1.16 augustss }
2212 1.16 augustss
2213 1.16 augustss usbd_status
2214 1.119 augustss uhci_device_ctrl_start(usbd_xfer_handle xfer)
2215 1.16 augustss {
2216 1.264.4.7 skrll uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
2217 1.63 augustss usbd_status err;
2218 1.1 augustss
2219 1.82 augustss if (sc->sc_dying)
2220 1.264.4.13 skrll return USBD_IOERROR;
2221 1.82 augustss
2222 1.48 augustss #ifdef DIAGNOSTIC
2223 1.264.4.7 skrll if (!(xfer->ux_rqflags & URQ_REQUEST))
2224 1.163 provos panic("uhci_device_ctrl_transfer: not a request");
2225 1.48 augustss #endif
2226 1.1 augustss
2227 1.248 mrg mutex_enter(&sc->sc_lock);
2228 1.63 augustss err = uhci_device_request(xfer);
2229 1.248 mrg mutex_exit(&sc->sc_lock);
2230 1.63 augustss if (err)
2231 1.264.4.13 skrll return err;
2232 1.1 augustss
2233 1.264.4.7 skrll if (sc->sc_bus.ub_usepolling)
2234 1.63 augustss uhci_waitintr(sc, xfer);
2235 1.264.4.13 skrll return USBD_IN_PROGRESS;
2236 1.1 augustss }
2237 1.1 augustss
2238 1.1 augustss usbd_status
2239 1.119 augustss uhci_device_intr_transfer(usbd_xfer_handle xfer)
2240 1.1 augustss {
2241 1.264.4.7 skrll uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
2242 1.63 augustss usbd_status err;
2243 1.16 augustss
2244 1.52 augustss /* Insert last in queue. */
2245 1.248 mrg mutex_enter(&sc->sc_lock);
2246 1.63 augustss err = usb_insert_transfer(xfer);
2247 1.248 mrg mutex_exit(&sc->sc_lock);
2248 1.63 augustss if (err)
2249 1.264.4.13 skrll return err;
2250 1.52 augustss
2251 1.152 augustss /*
2252 1.92 augustss * Pipe isn't running (otherwise err would be USBD_INPROG),
2253 1.92 augustss * so start it first.
2254 1.67 augustss */
2255 1.264.4.13 skrll return uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2256 1.16 augustss }
2257 1.16 augustss
2258 1.16 augustss usbd_status
2259 1.119 augustss uhci_device_intr_start(usbd_xfer_handle xfer)
2260 1.16 augustss {
2261 1.264.4.7 skrll struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
2262 1.264.4.7 skrll usbd_device_handle dev = upipe->pipe.up_dev;
2263 1.264.4.7 skrll uhci_softc_t *sc = dev->ud_bus->ub_hcpriv;
2264 1.92 augustss uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
2265 1.55 augustss uhci_soft_td_t *data, *dataend;
2266 1.1 augustss uhci_soft_qh_t *sqh;
2267 1.63 augustss usbd_status err;
2268 1.187 skrll int isread, endpt;
2269 1.248 mrg int i;
2270 1.1 augustss
2271 1.82 augustss if (sc->sc_dying)
2272 1.264.4.13 skrll return USBD_IOERROR;
2273 1.82 augustss
2274 1.63 augustss DPRINTFN(3,("uhci_device_intr_transfer: xfer=%p len=%d flags=%d\n",
2275 1.264.4.7 skrll xfer, xfer->ux_length, xfer->ux_flags));
2276 1.1 augustss
2277 1.48 augustss #ifdef DIAGNOSTIC
2278 1.264.4.7 skrll if (xfer->ux_rqflags & URQ_REQUEST)
2279 1.163 provos panic("uhci_device_intr_transfer: a request");
2280 1.48 augustss #endif
2281 1.1 augustss
2282 1.248 mrg mutex_enter(&sc->sc_lock);
2283 1.248 mrg
2284 1.264.4.7 skrll endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
2285 1.187 skrll isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2286 1.187 skrll
2287 1.187 skrll upipe->u.intr.isread = isread;
2288 1.187 skrll
2289 1.264.4.7 skrll err = uhci_alloc_std_chain(upipe, sc, xfer->ux_length, isread,
2290 1.264.4.7 skrll xfer->ux_flags, &xfer->ux_dmabuf, &data,
2291 1.187 skrll &dataend);
2292 1.248 mrg if (err) {
2293 1.248 mrg mutex_exit(&sc->sc_lock);
2294 1.264.4.13 skrll return err;
2295 1.248 mrg }
2296 1.248 mrg
2297 1.88 tsutsui dataend->td.td_status |= htole32(UHCI_TD_IOC);
2298 1.223 bouyer usb_syncmem(&dataend->dma,
2299 1.223 bouyer dataend->offs + offsetof(uhci_td_t, td_status),
2300 1.223 bouyer sizeof(dataend->td.td_status),
2301 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2302 1.1 augustss
2303 1.59 augustss #ifdef UHCI_DEBUG
2304 1.1 augustss if (uhcidebug > 10) {
2305 1.55 augustss DPRINTF(("uhci_device_intr_transfer: data(1)\n"));
2306 1.55 augustss uhci_dump_tds(data);
2307 1.1 augustss uhci_dump_qh(upipe->u.intr.qhs[0]);
2308 1.1 augustss }
2309 1.1 augustss #endif
2310 1.1 augustss
2311 1.1 augustss /* Set up interrupt info. */
2312 1.63 augustss ii->xfer = xfer;
2313 1.55 augustss ii->stdstart = data;
2314 1.55 augustss ii->stdend = dataend;
2315 1.7 augustss #ifdef DIAGNOSTIC
2316 1.70 augustss if (!ii->isdone) {
2317 1.70 augustss printf("uhci_device_intr_transfer: not done, ii=%p\n", ii);
2318 1.70 augustss }
2319 1.7 augustss ii->isdone = 0;
2320 1.7 augustss #endif
2321 1.1 augustss
2322 1.152 augustss DPRINTFN(10,("uhci_device_intr_transfer: qhs[0]=%p\n",
2323 1.12 augustss upipe->u.intr.qhs[0]));
2324 1.1 augustss for (i = 0; i < upipe->u.intr.npoll; i++) {
2325 1.1 augustss sqh = upipe->u.intr.qhs[i];
2326 1.55 augustss sqh->elink = data;
2327 1.121 augustss sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD);
2328 1.223 bouyer usb_syncmem(&sqh->dma,
2329 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
2330 1.223 bouyer sizeof(sqh->qh.qh_elink),
2331 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2332 1.1 augustss }
2333 1.92 augustss uhci_add_intr_info(sc, ii);
2334 1.264.4.7 skrll xfer->ux_status = USBD_IN_PROGRESS;
2335 1.248 mrg mutex_exit(&sc->sc_lock);
2336 1.1 augustss
2337 1.59 augustss #ifdef UHCI_DEBUG
2338 1.1 augustss if (uhcidebug > 10) {
2339 1.55 augustss DPRINTF(("uhci_device_intr_transfer: data(2)\n"));
2340 1.55 augustss uhci_dump_tds(data);
2341 1.1 augustss uhci_dump_qh(upipe->u.intr.qhs[0]);
2342 1.1 augustss }
2343 1.1 augustss #endif
2344 1.1 augustss
2345 1.264.4.13 skrll return USBD_IN_PROGRESS;
2346 1.1 augustss }
2347 1.1 augustss
2348 1.1 augustss /* Abort a device control request. */
2349 1.1 augustss void
2350 1.119 augustss uhci_device_ctrl_abort(usbd_xfer_handle xfer)
2351 1.1 augustss {
2352 1.248 mrg #ifdef DIAGNOSTIC
2353 1.264.4.7 skrll uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
2354 1.248 mrg #endif
2355 1.248 mrg
2356 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2357 1.248 mrg
2358 1.33 augustss DPRINTF(("uhci_device_ctrl_abort:\n"));
2359 1.66 augustss uhci_abort_xfer(xfer, USBD_CANCELLED);
2360 1.1 augustss }
2361 1.1 augustss
2362 1.1 augustss /* Close a device control pipe. */
2363 1.1 augustss void
2364 1.205 christos uhci_device_ctrl_close(usbd_pipe_handle pipe)
2365 1.1 augustss {
2366 1.1 augustss }
2367 1.1 augustss
2368 1.1 augustss /* Abort a device interrupt request. */
2369 1.1 augustss void
2370 1.119 augustss uhci_device_intr_abort(usbd_xfer_handle xfer)
2371 1.1 augustss {
2372 1.248 mrg #ifdef DIAGNOSTIC
2373 1.264.4.7 skrll uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
2374 1.248 mrg #endif
2375 1.248 mrg
2376 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2377 1.264.4.7 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
2378 1.248 mrg
2379 1.63 augustss DPRINTFN(1,("uhci_device_intr_abort: xfer=%p\n", xfer));
2380 1.264 skrll
2381 1.66 augustss uhci_abort_xfer(xfer, USBD_CANCELLED);
2382 1.1 augustss }
2383 1.1 augustss
2384 1.1 augustss /* Close a device interrupt pipe. */
2385 1.1 augustss void
2386 1.119 augustss uhci_device_intr_close(usbd_pipe_handle pipe)
2387 1.1 augustss {
2388 1.1 augustss struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;
2389 1.264.4.7 skrll uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv;
2390 1.92 augustss int i, npoll;
2391 1.248 mrg
2392 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2393 1.1 augustss
2394 1.1 augustss /* Unlink descriptors from controller data structures. */
2395 1.1 augustss npoll = upipe->u.intr.npoll;
2396 1.1 augustss for (i = 0; i < npoll; i++)
2397 1.92 augustss uhci_remove_intr(sc, upipe->u.intr.qhs[i]);
2398 1.1 augustss
2399 1.152 augustss /*
2400 1.1 augustss * We now have to wait for any activity on the physical
2401 1.1 augustss * descriptors to stop.
2402 1.1 augustss */
2403 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock);
2404 1.1 augustss
2405 1.1 augustss for(i = 0; i < npoll; i++)
2406 1.1 augustss uhci_free_sqh(sc, upipe->u.intr.qhs[i]);
2407 1.248 mrg kmem_free(upipe->u.intr.qhs, npoll * sizeof(uhci_soft_qh_t *));
2408 1.1 augustss
2409 1.1 augustss /* XXX free other resources */
2410 1.1 augustss }
2411 1.1 augustss
2412 1.1 augustss usbd_status
2413 1.119 augustss uhci_device_request(usbd_xfer_handle xfer)
2414 1.1 augustss {
2415 1.264.4.7 skrll struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
2416 1.264.4.7 skrll usb_device_request_t *req = &xfer->ux_request;
2417 1.264.4.7 skrll usbd_device_handle dev = upipe->pipe.up_dev;
2418 1.264.4.7 skrll uhci_softc_t *sc = dev->ud_bus->ub_hcpriv;
2419 1.264.4.7 skrll int addr = dev->ud_addr;
2420 1.264.4.7 skrll int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
2421 1.92 augustss uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
2422 1.55 augustss uhci_soft_td_t *setup, *data, *stat, *next, *dataend;
2423 1.1 augustss uhci_soft_qh_t *sqh;
2424 1.1 augustss int len;
2425 1.264.4.1 skrll uint32_t ls;
2426 1.63 augustss usbd_status err;
2427 1.1 augustss int isread;
2428 1.248 mrg
2429 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2430 1.1 augustss
2431 1.13 augustss DPRINTFN(3,("uhci_device_control type=0x%02x, request=0x%02x, "
2432 1.12 augustss "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n",
2433 1.1 augustss req->bmRequestType, req->bRequest, UGETW(req->wValue),
2434 1.1 augustss UGETW(req->wIndex), UGETW(req->wLength),
2435 1.1 augustss addr, endpt));
2436 1.1 augustss
2437 1.264.4.7 skrll ls = dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0;
2438 1.1 augustss isread = req->bmRequestType & UT_READ;
2439 1.1 augustss len = UGETW(req->wLength);
2440 1.1 augustss
2441 1.1 augustss setup = upipe->u.ctl.setup;
2442 1.1 augustss stat = upipe->u.ctl.stat;
2443 1.1 augustss sqh = upipe->u.ctl.sqh;
2444 1.1 augustss
2445 1.1 augustss /* Set up data transaction */
2446 1.1 augustss if (len != 0) {
2447 1.38 augustss upipe->nexttoggle = 1;
2448 1.264.4.7 skrll err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->ux_flags,
2449 1.264.4.7 skrll &xfer->ux_dmabuf, &data, &dataend);
2450 1.63 augustss if (err)
2451 1.264.4.13 skrll return err;
2452 1.55 augustss next = data;
2453 1.55 augustss dataend->link.std = stat;
2454 1.258 skrll dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD);
2455 1.223 bouyer usb_syncmem(&dataend->dma,
2456 1.223 bouyer dataend->offs + offsetof(uhci_td_t, td_link),
2457 1.223 bouyer sizeof(dataend->td.td_link),
2458 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2459 1.1 augustss } else {
2460 1.1 augustss next = stat;
2461 1.1 augustss }
2462 1.1 augustss upipe->u.ctl.length = len;
2463 1.1 augustss
2464 1.159 augustss memcpy(KERNADDR(&upipe->u.ctl.reqdma, 0), req, sizeof *req);
2465 1.223 bouyer usb_syncmem(&upipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE);
2466 1.1 augustss
2467 1.42 augustss setup->link.std = next;
2468 1.258 skrll setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD);
2469 1.88 tsutsui setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls |
2470 1.88 tsutsui UHCI_TD_ACTIVE);
2471 1.88 tsutsui setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof *req, endpt, addr));
2472 1.160 augustss setup->td.td_buffer = htole32(DMAADDR(&upipe->u.ctl.reqdma, 0));
2473 1.223 bouyer usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td),
2474 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2475 1.42 augustss
2476 1.92 augustss stat->link.std = NULL;
2477 1.88 tsutsui stat->td.td_link = htole32(UHCI_PTR_T);
2478 1.152 augustss stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls |
2479 1.39 augustss UHCI_TD_ACTIVE | UHCI_TD_IOC);
2480 1.152 augustss stat->td.td_token =
2481 1.88 tsutsui htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) :
2482 1.264.4.2 skrll UHCI_TD_IN (0, endpt, addr, 1));
2483 1.88 tsutsui stat->td.td_buffer = htole32(0);
2484 1.223 bouyer usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td),
2485 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2486 1.1 augustss
2487 1.59 augustss #ifdef UHCI_DEBUG
2488 1.67 augustss if (uhcidebug > 10) {
2489 1.47 augustss DPRINTF(("uhci_device_request: before transfer\n"));
2490 1.41 augustss uhci_dump_tds(setup);
2491 1.1 augustss }
2492 1.1 augustss #endif
2493 1.1 augustss
2494 1.1 augustss /* Set up interrupt info. */
2495 1.63 augustss ii->xfer = xfer;
2496 1.1 augustss ii->stdstart = setup;
2497 1.1 augustss ii->stdend = stat;
2498 1.7 augustss #ifdef DIAGNOSTIC
2499 1.70 augustss if (!ii->isdone) {
2500 1.70 augustss printf("uhci_device_request: not done, ii=%p\n", ii);
2501 1.70 augustss }
2502 1.7 augustss ii->isdone = 0;
2503 1.7 augustss #endif
2504 1.1 augustss
2505 1.42 augustss sqh->elink = setup;
2506 1.121 augustss sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD);
2507 1.223 bouyer /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */
2508 1.1 augustss
2509 1.264.4.7 skrll if (dev->ud_speed == USB_SPEED_LOW)
2510 1.123 augustss uhci_add_ls_ctrl(sc, sqh);
2511 1.123 augustss else
2512 1.123 augustss uhci_add_hs_ctrl(sc, sqh);
2513 1.92 augustss uhci_add_intr_info(sc, ii);
2514 1.59 augustss #ifdef UHCI_DEBUG
2515 1.1 augustss if (uhcidebug > 12) {
2516 1.1 augustss uhci_soft_td_t *std;
2517 1.1 augustss uhci_soft_qh_t *xqh;
2518 1.13 augustss uhci_soft_qh_t *sxqh;
2519 1.13 augustss int maxqh = 0;
2520 1.1 augustss uhci_physaddr_t link;
2521 1.47 augustss DPRINTF(("uhci_enter_ctl_q: follow from [0]\n"));
2522 1.1 augustss for (std = sc->sc_vframes[0].htd, link = 0;
2523 1.121 augustss (link & UHCI_PTR_QH) == 0;
2524 1.42 augustss std = std->link.std) {
2525 1.88 tsutsui link = le32toh(std->td.td_link);
2526 1.1 augustss uhci_dump_td(std);
2527 1.1 augustss }
2528 1.67 augustss sxqh = (uhci_soft_qh_t *)std;
2529 1.67 augustss uhci_dump_qh(sxqh);
2530 1.67 augustss for (xqh = sxqh;
2531 1.63 augustss xqh != NULL;
2532 1.152 augustss xqh = (maxqh++ == 5 || xqh->hlink == sxqh ||
2533 1.264.4.2 skrll xqh->hlink == xqh ? NULL : xqh->hlink)) {
2534 1.1 augustss uhci_dump_qh(xqh);
2535 1.13 augustss }
2536 1.47 augustss DPRINTF(("Enqueued QH:\n"));
2537 1.1 augustss uhci_dump_qh(sqh);
2538 1.42 augustss uhci_dump_tds(sqh->elink);
2539 1.1 augustss }
2540 1.1 augustss #endif
2541 1.264.4.7 skrll if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
2542 1.264.4.7 skrll callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
2543 1.91 augustss uhci_timeout, ii);
2544 1.13 augustss }
2545 1.264.4.7 skrll xfer->ux_status = USBD_IN_PROGRESS;
2546 1.1 augustss
2547 1.264.4.13 skrll return USBD_NORMAL_COMPLETION;
2548 1.1 augustss }
2549 1.1 augustss
2550 1.16 augustss usbd_status
2551 1.119 augustss uhci_device_isoc_transfer(usbd_xfer_handle xfer)
2552 1.16 augustss {
2553 1.264.4.7 skrll uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
2554 1.63 augustss usbd_status err;
2555 1.48 augustss
2556 1.63 augustss DPRINTFN(5,("uhci_device_isoc_transfer: xfer=%p\n", xfer));
2557 1.48 augustss
2558 1.48 augustss /* Put it on our queue, */
2559 1.248 mrg mutex_enter(&sc->sc_lock);
2560 1.63 augustss err = usb_insert_transfer(xfer);
2561 1.248 mrg mutex_exit(&sc->sc_lock);
2562 1.48 augustss
2563 1.48 augustss /* bail out on error, */
2564 1.63 augustss if (err && err != USBD_IN_PROGRESS)
2565 1.264.4.13 skrll return err;
2566 1.48 augustss
2567 1.48 augustss /* XXX should check inuse here */
2568 1.48 augustss
2569 1.48 augustss /* insert into schedule, */
2570 1.63 augustss uhci_device_isoc_enter(xfer);
2571 1.48 augustss
2572 1.102 augustss /* and start if the pipe wasn't running */
2573 1.67 augustss if (!err)
2574 1.264.4.7 skrll uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2575 1.48 augustss
2576 1.264.4.13 skrll return err;
2577 1.48 augustss }
2578 1.48 augustss
2579 1.48 augustss void
2580 1.119 augustss uhci_device_isoc_enter(usbd_xfer_handle xfer)
2581 1.48 augustss {
2582 1.264.4.7 skrll struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
2583 1.264.4.7 skrll usbd_device_handle dev = upipe->pipe.up_dev;
2584 1.264.4.7 skrll uhci_softc_t *sc = dev->ud_bus->ub_hcpriv;
2585 1.48 augustss struct iso *iso = &upipe->u.iso;
2586 1.152 augustss uhci_soft_td_t *std;
2587 1.264.4.1 skrll uint32_t buf, len, status, offs;
2588 1.248 mrg int i, next, nframes;
2589 1.264.4.7 skrll int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN;
2590 1.48 augustss
2591 1.63 augustss DPRINTFN(5,("uhci_device_isoc_enter: used=%d next=%d xfer=%p "
2592 1.48 augustss "nframes=%d\n",
2593 1.264.4.7 skrll iso->inuse, iso->next, xfer, xfer->ux_nframes));
2594 1.48 augustss
2595 1.82 augustss if (sc->sc_dying)
2596 1.82 augustss return;
2597 1.82 augustss
2598 1.264.4.7 skrll if (xfer->ux_status == USBD_IN_PROGRESS) {
2599 1.48 augustss /* This request has already been entered into the frame list */
2600 1.96 augustss printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer);
2601 1.68 augustss /* XXX */
2602 1.48 augustss }
2603 1.48 augustss
2604 1.48 augustss #ifdef DIAGNOSTIC
2605 1.48 augustss if (iso->inuse >= UHCI_VFRAMELIST_COUNT)
2606 1.48 augustss printf("uhci_device_isoc_enter: overflow!\n");
2607 1.19 augustss #endif
2608 1.16 augustss
2609 1.48 augustss next = iso->next;
2610 1.48 augustss if (next == -1) {
2611 1.48 augustss /* Not in use yet, schedule it a few frames ahead. */
2612 1.48 augustss next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT;
2613 1.48 augustss DPRINTFN(2,("uhci_device_isoc_enter: start next=%d\n", next));
2614 1.48 augustss }
2615 1.48 augustss
2616 1.264.4.7 skrll xfer->ux_status = USBD_IN_PROGRESS;
2617 1.92 augustss UXFER(xfer)->curframe = next;
2618 1.48 augustss
2619 1.264.4.7 skrll buf = DMAADDR(&xfer->ux_dmabuf, 0);
2620 1.223 bouyer offs = 0;
2621 1.88 tsutsui status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) |
2622 1.88 tsutsui UHCI_TD_ACTIVE |
2623 1.88 tsutsui UHCI_TD_IOS);
2624 1.264.4.7 skrll nframes = xfer->ux_nframes;
2625 1.248 mrg mutex_enter(&sc->sc_lock);
2626 1.48 augustss for (i = 0; i < nframes; i++) {
2627 1.48 augustss std = iso->stds[next];
2628 1.48 augustss if (++next >= UHCI_VFRAMELIST_COUNT)
2629 1.48 augustss next = 0;
2630 1.264.4.7 skrll len = xfer->ux_frlengths[i];
2631 1.88 tsutsui std->td.td_buffer = htole32(buf);
2632 1.264.4.7 skrll usb_syncmem(&xfer->ux_dmabuf, offs, len,
2633 1.223 bouyer rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
2634 1.48 augustss if (i == nframes - 1)
2635 1.88 tsutsui status |= UHCI_TD_IOC;
2636 1.88 tsutsui std->td.td_status = htole32(status);
2637 1.88 tsutsui std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK);
2638 1.88 tsutsui std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len));
2639 1.223 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
2640 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2641 1.59 augustss #ifdef UHCI_DEBUG
2642 1.48 augustss if (uhcidebug > 5) {
2643 1.48 augustss DPRINTFN(5,("uhci_device_isoc_enter: TD %d\n", i));
2644 1.48 augustss uhci_dump_td(std);
2645 1.48 augustss }
2646 1.48 augustss #endif
2647 1.48 augustss buf += len;
2648 1.223 bouyer offs += len;
2649 1.48 augustss }
2650 1.48 augustss iso->next = next;
2651 1.264.4.7 skrll iso->inuse += xfer->ux_nframes;
2652 1.16 augustss
2653 1.248 mrg mutex_exit(&sc->sc_lock);
2654 1.16 augustss }
2655 1.16 augustss
2656 1.16 augustss usbd_status
2657 1.119 augustss uhci_device_isoc_start(usbd_xfer_handle xfer)
2658 1.16 augustss {
2659 1.264.4.7 skrll struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
2660 1.264.4.7 skrll uhci_softc_t *sc = upipe->pipe.up_dev->ud_bus->ub_hcpriv;
2661 1.92 augustss uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
2662 1.48 augustss uhci_soft_td_t *end;
2663 1.248 mrg int i;
2664 1.48 augustss
2665 1.96 augustss DPRINTFN(5,("uhci_device_isoc_start: xfer=%p\n", xfer));
2666 1.96 augustss
2667 1.248 mrg mutex_enter(&sc->sc_lock);
2668 1.248 mrg
2669 1.248 mrg if (sc->sc_dying) {
2670 1.248 mrg mutex_exit(&sc->sc_lock);
2671 1.264.4.13 skrll return USBD_IOERROR;
2672 1.248 mrg }
2673 1.82 augustss
2674 1.48 augustss #ifdef DIAGNOSTIC
2675 1.264.4.7 skrll if (xfer->ux_status != USBD_IN_PROGRESS)
2676 1.63 augustss printf("uhci_device_isoc_start: not in progress %p\n", xfer);
2677 1.48 augustss #endif
2678 1.48 augustss
2679 1.48 augustss /* Find the last TD */
2680 1.264.4.7 skrll i = UXFER(xfer)->curframe + xfer->ux_nframes;
2681 1.48 augustss if (i >= UHCI_VFRAMELIST_COUNT)
2682 1.48 augustss i -= UHCI_VFRAMELIST_COUNT;
2683 1.48 augustss end = upipe->u.iso.stds[i];
2684 1.48 augustss
2685 1.96 augustss #ifdef DIAGNOSTIC
2686 1.96 augustss if (end == NULL) {
2687 1.96 augustss printf("uhci_device_isoc_start: end == NULL\n");
2688 1.264.4.13 skrll return USBD_INVAL;
2689 1.96 augustss }
2690 1.96 augustss #endif
2691 1.96 augustss
2692 1.48 augustss /* Set up interrupt info. */
2693 1.63 augustss ii->xfer = xfer;
2694 1.48 augustss ii->stdstart = end;
2695 1.48 augustss ii->stdend = end;
2696 1.48 augustss #ifdef DIAGNOSTIC
2697 1.102 augustss if (!ii->isdone)
2698 1.70 augustss printf("uhci_device_isoc_start: not done, ii=%p\n", ii);
2699 1.48 augustss ii->isdone = 0;
2700 1.48 augustss #endif
2701 1.92 augustss uhci_add_intr_info(sc, ii);
2702 1.152 augustss
2703 1.248 mrg mutex_exit(&sc->sc_lock);
2704 1.48 augustss
2705 1.264.4.13 skrll return USBD_IN_PROGRESS;
2706 1.16 augustss }
2707 1.16 augustss
2708 1.16 augustss void
2709 1.119 augustss uhci_device_isoc_abort(usbd_xfer_handle xfer)
2710 1.16 augustss {
2711 1.248 mrg #ifdef DIAGNOSTIC
2712 1.264.4.7 skrll uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
2713 1.248 mrg #endif
2714 1.264.4.7 skrll struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
2715 1.48 augustss uhci_soft_td_t **stds = upipe->u.iso.stds;
2716 1.48 augustss uhci_soft_td_t *std;
2717 1.248 mrg int i, n, nframes, maxlen, len;
2718 1.92 augustss
2719 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2720 1.92 augustss
2721 1.92 augustss /* Transfer is already done. */
2722 1.264.4.7 skrll if (xfer->ux_status != USBD_NOT_STARTED &&
2723 1.264.4.7 skrll xfer->ux_status != USBD_IN_PROGRESS) {
2724 1.92 augustss return;
2725 1.92 augustss }
2726 1.48 augustss
2727 1.92 augustss /* Give xfer the requested abort code. */
2728 1.264.4.7 skrll xfer->ux_status = USBD_CANCELLED;
2729 1.48 augustss
2730 1.48 augustss /* make hardware ignore it, */
2731 1.264.4.7 skrll nframes = xfer->ux_nframes;
2732 1.92 augustss n = UXFER(xfer)->curframe;
2733 1.92 augustss maxlen = 0;
2734 1.48 augustss for (i = 0; i < nframes; i++) {
2735 1.48 augustss std = stds[n];
2736 1.223 bouyer usb_syncmem(&std->dma,
2737 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
2738 1.223 bouyer sizeof(std->td.td_status),
2739 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2740 1.88 tsutsui std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC));
2741 1.223 bouyer usb_syncmem(&std->dma,
2742 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
2743 1.223 bouyer sizeof(std->td.td_status),
2744 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2745 1.223 bouyer usb_syncmem(&std->dma,
2746 1.223 bouyer std->offs + offsetof(uhci_td_t, td_token),
2747 1.223 bouyer sizeof(std->td.td_token),
2748 1.223 bouyer BUS_DMASYNC_POSTWRITE);
2749 1.130 tsutsui len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token));
2750 1.92 augustss if (len > maxlen)
2751 1.92 augustss maxlen = len;
2752 1.48 augustss if (++n >= UHCI_VFRAMELIST_COUNT)
2753 1.48 augustss n = 0;
2754 1.48 augustss }
2755 1.48 augustss
2756 1.92 augustss /* and wait until we are sure the hardware has finished. */
2757 1.92 augustss delay(maxlen);
2758 1.92 augustss
2759 1.96 augustss #ifdef DIAGNOSTIC
2760 1.96 augustss UXFER(xfer)->iinfo.isdone = 1;
2761 1.96 augustss #endif
2762 1.92 augustss /* Run callback and remove from interrupt list. */
2763 1.92 augustss usb_transfer_complete(xfer);
2764 1.48 augustss
2765 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2766 1.16 augustss }
2767 1.16 augustss
2768 1.16 augustss void
2769 1.119 augustss uhci_device_isoc_close(usbd_pipe_handle pipe)
2770 1.16 augustss {
2771 1.16 augustss struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;
2772 1.264.4.7 skrll usbd_device_handle dev = upipe->pipe.up_dev;
2773 1.264.4.7 skrll uhci_softc_t *sc = dev->ud_bus->ub_hcpriv;
2774 1.48 augustss uhci_soft_td_t *std, *vstd;
2775 1.16 augustss struct iso *iso;
2776 1.248 mrg int i;
2777 1.248 mrg
2778 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2779 1.16 augustss
2780 1.16 augustss /*
2781 1.16 augustss * Make sure all TDs are marked as inactive.
2782 1.16 augustss * Wait for completion.
2783 1.16 augustss * Unschedule.
2784 1.16 augustss * Deallocate.
2785 1.16 augustss */
2786 1.16 augustss iso = &upipe->u.iso;
2787 1.16 augustss
2788 1.223 bouyer for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
2789 1.223 bouyer std = iso->stds[i];
2790 1.223 bouyer usb_syncmem(&std->dma,
2791 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
2792 1.223 bouyer sizeof(std->td.td_status),
2793 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2794 1.223 bouyer std->td.td_status &= htole32(~UHCI_TD_ACTIVE);
2795 1.223 bouyer usb_syncmem(&std->dma,
2796 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
2797 1.223 bouyer sizeof(std->td.td_status),
2798 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2799 1.223 bouyer }
2800 1.248 mrg /* wait for completion */
2801 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock);
2802 1.16 augustss
2803 1.16 augustss for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
2804 1.16 augustss std = iso->stds[i];
2805 1.48 augustss for (vstd = sc->sc_vframes[i].htd;
2806 1.67 augustss vstd != NULL && vstd->link.std != std;
2807 1.42 augustss vstd = vstd->link.std)
2808 1.16 augustss ;
2809 1.67 augustss if (vstd == NULL) {
2810 1.16 augustss /*panic*/
2811 1.16 augustss printf("uhci_device_isoc_close: %p not found\n", std);
2812 1.248 mrg mutex_exit(&sc->sc_lock);
2813 1.16 augustss return;
2814 1.16 augustss }
2815 1.42 augustss vstd->link = std->link;
2816 1.223 bouyer usb_syncmem(&std->dma,
2817 1.223 bouyer std->offs + offsetof(uhci_td_t, td_link),
2818 1.223 bouyer sizeof(std->td.td_link),
2819 1.223 bouyer BUS_DMASYNC_POSTWRITE);
2820 1.42 augustss vstd->td.td_link = std->td.td_link;
2821 1.223 bouyer usb_syncmem(&vstd->dma,
2822 1.223 bouyer vstd->offs + offsetof(uhci_td_t, td_link),
2823 1.223 bouyer sizeof(vstd->td.td_link),
2824 1.223 bouyer BUS_DMASYNC_PREWRITE);
2825 1.16 augustss uhci_free_std(sc, std);
2826 1.16 augustss }
2827 1.16 augustss
2828 1.248 mrg kmem_free(iso->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *));
2829 1.16 augustss }
2830 1.16 augustss
2831 1.16 augustss usbd_status
2832 1.119 augustss uhci_setup_isoc(usbd_pipe_handle pipe)
2833 1.16 augustss {
2834 1.16 augustss struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;
2835 1.264.4.7 skrll usbd_device_handle dev = upipe->pipe.up_dev;
2836 1.264.4.7 skrll uhci_softc_t *sc = dev->ud_bus->ub_hcpriv;
2837 1.264.4.7 skrll int addr = upipe->pipe.up_dev->ud_addr;
2838 1.264.4.7 skrll int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
2839 1.45 augustss int rd = UE_GET_DIR(endpt) == UE_DIR_IN;
2840 1.48 augustss uhci_soft_td_t *std, *vstd;
2841 1.264.4.1 skrll uint32_t token;
2842 1.16 augustss struct iso *iso;
2843 1.248 mrg int i;
2844 1.16 augustss
2845 1.16 augustss iso = &upipe->u.iso;
2846 1.248 mrg iso->stds = kmem_alloc(UHCI_VFRAMELIST_COUNT *
2847 1.248 mrg sizeof (uhci_soft_td_t *),
2848 1.248 mrg KM_SLEEP);
2849 1.248 mrg if (iso->stds == NULL)
2850 1.248 mrg return USBD_NOMEM;
2851 1.16 augustss
2852 1.88 tsutsui token = rd ? UHCI_TD_IN (0, endpt, addr, 0) :
2853 1.88 tsutsui UHCI_TD_OUT(0, endpt, addr, 0);
2854 1.16 augustss
2855 1.248 mrg mutex_enter(&sc->sc_lock);
2856 1.248 mrg
2857 1.48 augustss /* Allocate the TDs and mark as inactive; */
2858 1.16 augustss for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
2859 1.48 augustss std = uhci_alloc_std(sc);
2860 1.48 augustss if (std == 0)
2861 1.48 augustss goto bad;
2862 1.88 tsutsui std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */
2863 1.88 tsutsui std->td.td_token = htole32(token);
2864 1.223 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
2865 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2866 1.48 augustss iso->stds[i] = std;
2867 1.16 augustss }
2868 1.16 augustss
2869 1.48 augustss /* Insert TDs into schedule. */
2870 1.16 augustss for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
2871 1.16 augustss std = iso->stds[i];
2872 1.48 augustss vstd = sc->sc_vframes[i].htd;
2873 1.223 bouyer usb_syncmem(&vstd->dma,
2874 1.223 bouyer vstd->offs + offsetof(uhci_td_t, td_link),
2875 1.223 bouyer sizeof(vstd->td.td_link),
2876 1.223 bouyer BUS_DMASYNC_POSTWRITE);
2877 1.42 augustss std->link = vstd->link;
2878 1.42 augustss std->td.td_link = vstd->td.td_link;
2879 1.223 bouyer usb_syncmem(&std->dma,
2880 1.223 bouyer std->offs + offsetof(uhci_td_t, td_link),
2881 1.223 bouyer sizeof(std->td.td_link),
2882 1.223 bouyer BUS_DMASYNC_PREWRITE);
2883 1.42 augustss vstd->link.std = std;
2884 1.121 augustss vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD);
2885 1.223 bouyer usb_syncmem(&vstd->dma,
2886 1.223 bouyer vstd->offs + offsetof(uhci_td_t, td_link),
2887 1.223 bouyer sizeof(vstd->td.td_link),
2888 1.223 bouyer BUS_DMASYNC_PREWRITE);
2889 1.16 augustss }
2890 1.248 mrg mutex_exit(&sc->sc_lock);
2891 1.16 augustss
2892 1.48 augustss iso->next = -1;
2893 1.48 augustss iso->inuse = 0;
2894 1.48 augustss
2895 1.264.4.13 skrll return USBD_NORMAL_COMPLETION;
2896 1.16 augustss
2897 1.48 augustss bad:
2898 1.16 augustss while (--i >= 0)
2899 1.16 augustss uhci_free_std(sc, iso->stds[i]);
2900 1.248 mrg mutex_exit(&sc->sc_lock);
2901 1.248 mrg kmem_free(iso->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *));
2902 1.264.4.13 skrll return USBD_NOMEM;
2903 1.16 augustss }
2904 1.16 augustss
2905 1.16 augustss void
2906 1.119 augustss uhci_device_isoc_done(usbd_xfer_handle xfer)
2907 1.16 augustss {
2908 1.92 augustss uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
2909 1.264.4.7 skrll struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
2910 1.223 bouyer int i, offs;
2911 1.264.4.7 skrll int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN;
2912 1.223 bouyer
2913 1.48 augustss
2914 1.264.4.7 skrll DPRINTFN(4, ("uhci_isoc_done: length=%d, ux_state=0x%08x\n",
2915 1.264.4.7 skrll xfer->ux_actlen, xfer->ux_state));
2916 1.93 augustss
2917 1.96 augustss if (ii->xfer != xfer)
2918 1.96 augustss /* Not on interrupt list, ignore it. */
2919 1.170 augustss return;
2920 1.170 augustss
2921 1.170 augustss if (!uhci_active_intr_info(ii))
2922 1.96 augustss return;
2923 1.96 augustss
2924 1.93 augustss #ifdef DIAGNOSTIC
2925 1.264.4.2 skrll if (ii->stdend == NULL) {
2926 1.264.4.2 skrll printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer);
2927 1.93 augustss #ifdef UHCI_DEBUG
2928 1.93 augustss uhci_dump_ii(ii);
2929 1.93 augustss #endif
2930 1.93 augustss return;
2931 1.93 augustss }
2932 1.93 augustss #endif
2933 1.48 augustss
2934 1.48 augustss /* Turn off the interrupt since it is active even if the TD is not. */
2935 1.223 bouyer usb_syncmem(&ii->stdend->dma,
2936 1.223 bouyer ii->stdend->offs + offsetof(uhci_td_t, td_status),
2937 1.223 bouyer sizeof(ii->stdend->td.td_status),
2938 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2939 1.88 tsutsui ii->stdend->td.td_status &= htole32(~UHCI_TD_IOC);
2940 1.223 bouyer usb_syncmem(&ii->stdend->dma,
2941 1.223 bouyer ii->stdend->offs + offsetof(uhci_td_t, td_status),
2942 1.223 bouyer sizeof(ii->stdend->td.td_status),
2943 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2944 1.48 augustss
2945 1.92 augustss uhci_del_intr_info(ii); /* remove from active list */
2946 1.223 bouyer
2947 1.223 bouyer offs = 0;
2948 1.264.4.7 skrll for (i = 0; i < xfer->ux_nframes; i++) {
2949 1.264.4.7 skrll usb_syncmem(&xfer->ux_dmabuf, offs, xfer->ux_frlengths[i],
2950 1.223 bouyer rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
2951 1.264.4.7 skrll offs += xfer->ux_frlengths[i];
2952 1.223 bouyer }
2953 1.16 augustss }
2954 1.16 augustss
2955 1.1 augustss void
2956 1.119 augustss uhci_device_intr_done(usbd_xfer_handle xfer)
2957 1.1 augustss {
2958 1.92 augustss uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
2959 1.1 augustss uhci_softc_t *sc = ii->sc;
2960 1.264.4.7 skrll struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
2961 1.1 augustss uhci_soft_qh_t *sqh;
2962 1.223 bouyer int i, npoll, isread;
2963 1.1 augustss
2964 1.264.4.7 skrll DPRINTFN(5, ("uhci_device_intr_done: length=%d\n", xfer->ux_actlen));
2965 1.1 augustss
2966 1.264.4.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
2967 1.248 mrg
2968 1.1 augustss npoll = upipe->u.intr.npoll;
2969 1.1 augustss for(i = 0; i < npoll; i++) {
2970 1.1 augustss sqh = upipe->u.intr.qhs[i];
2971 1.121 augustss sqh->elink = NULL;
2972 1.88 tsutsui sqh->qh.qh_elink = htole32(UHCI_PTR_T);
2973 1.223 bouyer usb_syncmem(&sqh->dma,
2974 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
2975 1.223 bouyer sizeof(sqh->qh.qh_elink),
2976 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2977 1.1 augustss }
2978 1.149 augustss uhci_free_std_chain(sc, ii->stdstart, NULL);
2979 1.1 augustss
2980 1.264.4.7 skrll isread = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN;
2981 1.264.4.7 skrll usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
2982 1.223 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
2983 1.223 bouyer
2984 1.1 augustss /* XXX Wasteful. */
2985 1.264.4.7 skrll if (xfer->ux_pipe->up_repeat) {
2986 1.55 augustss uhci_soft_td_t *data, *dataend;
2987 1.1 augustss
2988 1.92 augustss DPRINTFN(5,("uhci_device_intr_done: requeing\n"));
2989 1.92 augustss
2990 1.1 augustss /* This alloc cannot fail since we freed the chain above. */
2991 1.264.4.7 skrll uhci_alloc_std_chain(upipe, sc, xfer->ux_length,
2992 1.264.4.7 skrll upipe->u.intr.isread, xfer->ux_flags,
2993 1.264.4.7 skrll &xfer->ux_dmabuf, &data, &dataend);
2994 1.88 tsutsui dataend->td.td_status |= htole32(UHCI_TD_IOC);
2995 1.223 bouyer usb_syncmem(&dataend->dma,
2996 1.223 bouyer dataend->offs + offsetof(uhci_td_t, td_status),
2997 1.223 bouyer sizeof(dataend->td.td_status),
2998 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2999 1.1 augustss
3000 1.59 augustss #ifdef UHCI_DEBUG
3001 1.1 augustss if (uhcidebug > 10) {
3002 1.55 augustss DPRINTF(("uhci_device_intr_done: data(1)\n"));
3003 1.55 augustss uhci_dump_tds(data);
3004 1.1 augustss uhci_dump_qh(upipe->u.intr.qhs[0]);
3005 1.1 augustss }
3006 1.1 augustss #endif
3007 1.1 augustss
3008 1.55 augustss ii->stdstart = data;
3009 1.55 augustss ii->stdend = dataend;
3010 1.7 augustss #ifdef DIAGNOSTIC
3011 1.70 augustss if (!ii->isdone) {
3012 1.70 augustss printf("uhci_device_intr_done: not done, ii=%p\n", ii);
3013 1.70 augustss }
3014 1.7 augustss ii->isdone = 0;
3015 1.7 augustss #endif
3016 1.1 augustss for (i = 0; i < npoll; i++) {
3017 1.1 augustss sqh = upipe->u.intr.qhs[i];
3018 1.55 augustss sqh->elink = data;
3019 1.121 augustss sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD);
3020 1.223 bouyer usb_syncmem(&sqh->dma,
3021 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
3022 1.223 bouyer sizeof(sqh->qh.qh_elink),
3023 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3024 1.1 augustss }
3025 1.264.4.7 skrll xfer->ux_status = USBD_IN_PROGRESS;
3026 1.92 augustss /* The ii is already on the examined list, just leave it. */
3027 1.1 augustss } else {
3028 1.92 augustss DPRINTFN(5,("uhci_device_intr_done: removing\n"));
3029 1.169 augustss if (uhci_active_intr_info(ii))
3030 1.169 augustss uhci_del_intr_info(ii);
3031 1.1 augustss }
3032 1.1 augustss }
3033 1.1 augustss
3034 1.1 augustss /* Deallocate request data structures */
3035 1.1 augustss void
3036 1.119 augustss uhci_device_ctrl_done(usbd_xfer_handle xfer)
3037 1.1 augustss {
3038 1.92 augustss uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
3039 1.1 augustss uhci_softc_t *sc = ii->sc;
3040 1.264.4.7 skrll struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
3041 1.264.4.7 skrll int len = UGETW(xfer->ux_request.wLength);
3042 1.264.4.7 skrll int isread = (xfer->ux_request.bmRequestType & UT_READ);
3043 1.1 augustss
3044 1.264.4.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
3045 1.248 mrg
3046 1.7 augustss #ifdef DIAGNOSTIC
3047 1.264.4.7 skrll if (!(xfer->ux_rqflags & URQ_REQUEST))
3048 1.173 gson panic("uhci_device_ctrl_done: not a request");
3049 1.7 augustss #endif
3050 1.1 augustss
3051 1.169 augustss if (!uhci_active_intr_info(ii))
3052 1.169 augustss return;
3053 1.169 augustss
3054 1.92 augustss uhci_del_intr_info(ii); /* remove from active list */
3055 1.1 augustss
3056 1.264.4.7 skrll if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW)
3057 1.123 augustss uhci_remove_ls_ctrl(sc, upipe->u.ctl.sqh);
3058 1.123 augustss else
3059 1.123 augustss uhci_remove_hs_ctrl(sc, upipe->u.ctl.sqh);
3060 1.1 augustss
3061 1.49 augustss if (upipe->u.ctl.length != 0)
3062 1.42 augustss uhci_free_std_chain(sc, ii->stdstart->link.std, ii->stdend);
3063 1.49 augustss
3064 1.223 bouyer if (len) {
3065 1.264.4.7 skrll usb_syncmem(&xfer->ux_dmabuf, 0, len,
3066 1.223 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
3067 1.223 bouyer }
3068 1.223 bouyer usb_syncmem(&upipe->u.ctl.reqdma, 0,
3069 1.223 bouyer sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE);
3070 1.223 bouyer
3071 1.264.4.7 skrll DPRINTFN(5, ("uhci_device_ctrl_done: length=%d\n", xfer->ux_actlen));
3072 1.1 augustss }
3073 1.1 augustss
3074 1.1 augustss /* Deallocate request data structures */
3075 1.1 augustss void
3076 1.119 augustss uhci_device_bulk_done(usbd_xfer_handle xfer)
3077 1.1 augustss {
3078 1.92 augustss uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
3079 1.1 augustss uhci_softc_t *sc = ii->sc;
3080 1.264.4.7 skrll struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
3081 1.169 augustss
3082 1.173 gson DPRINTFN(5,("uhci_device_bulk_done: xfer=%p ii=%p sc=%p upipe=%p\n",
3083 1.169 augustss xfer, ii, sc, upipe));
3084 1.169 augustss
3085 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
3086 1.248 mrg
3087 1.169 augustss if (!uhci_active_intr_info(ii))
3088 1.169 augustss return;
3089 1.1 augustss
3090 1.92 augustss uhci_del_intr_info(ii); /* remove from active list */
3091 1.1 augustss
3092 1.1 augustss uhci_remove_bulk(sc, upipe->u.bulk.sqh);
3093 1.32 augustss
3094 1.149 augustss uhci_free_std_chain(sc, ii->stdstart, NULL);
3095 1.32 augustss
3096 1.264.4.7 skrll DPRINTFN(5, ("uhci_device_bulk_done: length=%d\n", xfer->ux_actlen));
3097 1.1 augustss }
3098 1.1 augustss
3099 1.1 augustss /* Add interrupt QH, called with vflock. */
3100 1.1 augustss void
3101 1.119 augustss uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
3102 1.1 augustss {
3103 1.92 augustss struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos];
3104 1.42 augustss uhci_soft_qh_t *eqh;
3105 1.1 augustss
3106 1.92 augustss DPRINTFN(4, ("uhci_add_intr: n=%d sqh=%p\n", sqh->pos, sqh));
3107 1.92 augustss
3108 1.42 augustss eqh = vf->eqh;
3109 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
3110 1.223 bouyer sizeof(eqh->qh.qh_hlink),
3111 1.223 bouyer BUS_DMASYNC_POSTWRITE);
3112 1.42 augustss sqh->hlink = eqh->hlink;
3113 1.42 augustss sqh->qh.qh_hlink = eqh->qh.qh_hlink;
3114 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
3115 1.223 bouyer sizeof(sqh->qh.qh_hlink),
3116 1.223 bouyer BUS_DMASYNC_PREWRITE);
3117 1.42 augustss eqh->hlink = sqh;
3118 1.121 augustss eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
3119 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
3120 1.223 bouyer sizeof(eqh->qh.qh_hlink),
3121 1.223 bouyer BUS_DMASYNC_PREWRITE);
3122 1.1 augustss vf->eqh = sqh;
3123 1.1 augustss vf->bandwidth++;
3124 1.1 augustss }
3125 1.1 augustss
3126 1.119 augustss /* Remove interrupt QH. */
3127 1.1 augustss void
3128 1.119 augustss uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
3129 1.1 augustss {
3130 1.92 augustss struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos];
3131 1.1 augustss uhci_soft_qh_t *pqh;
3132 1.1 augustss
3133 1.92 augustss DPRINTFN(4, ("uhci_remove_intr: n=%d sqh=%p\n", sqh->pos, sqh));
3134 1.1 augustss
3135 1.124 augustss /* See comment in uhci_remove_ctrl() */
3136 1.223 bouyer
3137 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
3138 1.223 bouyer sizeof(sqh->qh.qh_elink),
3139 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3140 1.124 augustss if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) {
3141 1.124 augustss sqh->qh.qh_elink = htole32(UHCI_PTR_T);
3142 1.223 bouyer usb_syncmem(&sqh->dma,
3143 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
3144 1.223 bouyer sizeof(sqh->qh.qh_elink),
3145 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3146 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
3147 1.124 augustss }
3148 1.124 augustss
3149 1.92 augustss pqh = uhci_find_prev_qh(vf->hqh, sqh);
3150 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
3151 1.223 bouyer sizeof(sqh->qh.qh_hlink),
3152 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3153 1.42 augustss pqh->hlink = sqh->hlink;
3154 1.42 augustss pqh->qh.qh_hlink = sqh->qh.qh_hlink;
3155 1.223 bouyer usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
3156 1.223 bouyer sizeof(pqh->qh.qh_hlink),
3157 1.223 bouyer BUS_DMASYNC_PREWRITE);
3158 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
3159 1.1 augustss if (vf->eqh == sqh)
3160 1.1 augustss vf->eqh = pqh;
3161 1.1 augustss vf->bandwidth--;
3162 1.1 augustss }
3163 1.1 augustss
3164 1.1 augustss usbd_status
3165 1.119 augustss uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival)
3166 1.1 augustss {
3167 1.1 augustss uhci_soft_qh_t *sqh;
3168 1.248 mrg int i, npoll;
3169 1.1 augustss u_int bestbw, bw, bestoffs, offs;
3170 1.1 augustss
3171 1.173 gson DPRINTFN(2, ("uhci_device_setintr: pipe=%p\n", upipe));
3172 1.1 augustss if (ival == 0) {
3173 1.173 gson printf("uhci_device_setintr: 0 interval\n");
3174 1.264.4.13 skrll return USBD_INVAL;
3175 1.1 augustss }
3176 1.1 augustss
3177 1.1 augustss if (ival > UHCI_VFRAMELIST_COUNT)
3178 1.1 augustss ival = UHCI_VFRAMELIST_COUNT;
3179 1.1 augustss npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival;
3180 1.173 gson DPRINTFN(2, ("uhci_device_setintr: ival=%d npoll=%d\n", ival, npoll));
3181 1.1 augustss
3182 1.1 augustss upipe->u.intr.npoll = npoll;
3183 1.152 augustss upipe->u.intr.qhs =
3184 1.248 mrg kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP);
3185 1.248 mrg if (upipe->u.intr.qhs == NULL)
3186 1.248 mrg return USBD_NOMEM;
3187 1.1 augustss
3188 1.152 augustss /*
3189 1.1 augustss * Figure out which offset in the schedule that has most
3190 1.1 augustss * bandwidth left over.
3191 1.1 augustss */
3192 1.1 augustss #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1))
3193 1.1 augustss for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) {
3194 1.1 augustss for (bw = i = 0; i < npoll; i++)
3195 1.1 augustss bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth;
3196 1.1 augustss if (bw < bestbw) {
3197 1.1 augustss bestbw = bw;
3198 1.1 augustss bestoffs = offs;
3199 1.1 augustss }
3200 1.1 augustss }
3201 1.173 gson DPRINTFN(1, ("uhci_device_setintr: bw=%d offs=%d\n", bestbw, bestoffs));
3202 1.1 augustss
3203 1.248 mrg mutex_enter(&sc->sc_lock);
3204 1.1 augustss for(i = 0; i < npoll; i++) {
3205 1.1 augustss upipe->u.intr.qhs[i] = sqh = uhci_alloc_sqh(sc);
3206 1.121 augustss sqh->elink = NULL;
3207 1.88 tsutsui sqh->qh.qh_elink = htole32(UHCI_PTR_T);
3208 1.223 bouyer usb_syncmem(&sqh->dma,
3209 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
3210 1.223 bouyer sizeof(sqh->qh.qh_elink),
3211 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3212 1.1 augustss sqh->pos = MOD(i * ival + bestoffs);
3213 1.1 augustss }
3214 1.1 augustss #undef MOD
3215 1.1 augustss
3216 1.1 augustss /* Enter QHs into the controller data structures. */
3217 1.1 augustss for(i = 0; i < npoll; i++)
3218 1.92 augustss uhci_add_intr(sc, upipe->u.intr.qhs[i]);
3219 1.248 mrg mutex_exit(&sc->sc_lock);
3220 1.1 augustss
3221 1.173 gson DPRINTFN(5, ("uhci_device_setintr: returns %p\n", upipe));
3222 1.264.4.13 skrll return USBD_NORMAL_COMPLETION;
3223 1.1 augustss }
3224 1.1 augustss
3225 1.1 augustss /* Open a new pipe. */
3226 1.1 augustss usbd_status
3227 1.119 augustss uhci_open(usbd_pipe_handle pipe)
3228 1.1 augustss {
3229 1.264.4.7 skrll uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv;
3230 1.264.4.12 skrll struct usbd_bus *bus = pipe->up_dev->ud_bus;
3231 1.1 augustss struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;
3232 1.264.4.7 skrll usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc;
3233 1.248 mrg usbd_status err = USBD_NOMEM;
3234 1.79 augustss int ival;
3235 1.1 augustss
3236 1.1 augustss DPRINTFN(1, ("uhci_open: pipe=%p, addr=%d, endpt=%d (%d)\n",
3237 1.264.4.7 skrll pipe, pipe->up_dev->ud_addr,
3238 1.264.4.12 skrll ed->bEndpointAddress, bus->ub_rhaddr));
3239 1.92 augustss
3240 1.248 mrg if (sc->sc_dying)
3241 1.248 mrg return USBD_IOERROR;
3242 1.248 mrg
3243 1.92 augustss upipe->aborting = 0;
3244 1.236 drochner /* toggle state needed for bulk endpoints */
3245 1.264.4.7 skrll upipe->nexttoggle = pipe->up_endpoint->ue_toggle;
3246 1.92 augustss
3247 1.264.4.12 skrll if (pipe->up_dev->ud_addr == bus->ub_rhaddr) {
3248 1.1 augustss switch (ed->bEndpointAddress) {
3249 1.1 augustss case USB_CONTROL_ENDPOINT:
3250 1.264.4.12 skrll pipe->up_methods = &roothub_ctrl_methods;
3251 1.1 augustss break;
3252 1.264.4.12 skrll case UE_DIR_IN | USBROOTHUB_INTR_ENDPT:
3253 1.264.4.7 skrll pipe->up_methods = &uhci_root_intr_methods;
3254 1.1 augustss break;
3255 1.1 augustss default:
3256 1.264.4.13 skrll return USBD_INVAL;
3257 1.1 augustss }
3258 1.1 augustss } else {
3259 1.1 augustss switch (ed->bmAttributes & UE_XFERTYPE) {
3260 1.1 augustss case UE_CONTROL:
3261 1.264.4.7 skrll pipe->up_methods = &uhci_device_ctrl_methods;
3262 1.1 augustss upipe->u.ctl.sqh = uhci_alloc_sqh(sc);
3263 1.63 augustss if (upipe->u.ctl.sqh == NULL)
3264 1.5 augustss goto bad;
3265 1.1 augustss upipe->u.ctl.setup = uhci_alloc_std(sc);
3266 1.63 augustss if (upipe->u.ctl.setup == NULL) {
3267 1.5 augustss uhci_free_sqh(sc, upipe->u.ctl.sqh);
3268 1.5 augustss goto bad;
3269 1.5 augustss }
3270 1.1 augustss upipe->u.ctl.stat = uhci_alloc_std(sc);
3271 1.63 augustss if (upipe->u.ctl.stat == NULL) {
3272 1.5 augustss uhci_free_sqh(sc, upipe->u.ctl.sqh);
3273 1.5 augustss uhci_free_std(sc, upipe->u.ctl.setup);
3274 1.5 augustss goto bad;
3275 1.5 augustss }
3276 1.152 augustss err = usb_allocmem(&sc->sc_bus,
3277 1.152 augustss sizeof(usb_device_request_t),
3278 1.63 augustss 0, &upipe->u.ctl.reqdma);
3279 1.63 augustss if (err) {
3280 1.5 augustss uhci_free_sqh(sc, upipe->u.ctl.sqh);
3281 1.5 augustss uhci_free_std(sc, upipe->u.ctl.setup);
3282 1.5 augustss uhci_free_std(sc, upipe->u.ctl.stat);
3283 1.5 augustss goto bad;
3284 1.5 augustss }
3285 1.1 augustss break;
3286 1.1 augustss case UE_INTERRUPT:
3287 1.264.4.7 skrll pipe->up_methods = &uhci_device_intr_methods;
3288 1.264.4.7 skrll ival = pipe->up_interval;
3289 1.79 augustss if (ival == USBD_DEFAULT_INTERVAL)
3290 1.79 augustss ival = ed->bInterval;
3291 1.264.4.13 skrll return uhci_device_setintr(sc, upipe, ival);
3292 1.1 augustss case UE_ISOCHRONOUS:
3293 1.264.4.7 skrll pipe->up_methods = &uhci_device_isoc_methods;
3294 1.264.4.13 skrll return uhci_setup_isoc(pipe);
3295 1.1 augustss case UE_BULK:
3296 1.264.4.7 skrll pipe->up_methods = &uhci_device_bulk_methods;
3297 1.1 augustss upipe->u.bulk.sqh = uhci_alloc_sqh(sc);
3298 1.63 augustss if (upipe->u.bulk.sqh == NULL)
3299 1.5 augustss goto bad;
3300 1.1 augustss break;
3301 1.1 augustss }
3302 1.1 augustss }
3303 1.264.4.13 skrll return USBD_NORMAL_COMPLETION;
3304 1.5 augustss
3305 1.5 augustss bad:
3306 1.248 mrg return USBD_NOMEM;
3307 1.1 augustss }
3308 1.1 augustss
3309 1.1 augustss /*
3310 1.1 augustss * Data structures and routines to emulate the root hub.
3311 1.1 augustss */
3312 1.1 augustss /*
3313 1.166 dsainty * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also
3314 1.166 dsainty * enables the port, and also states that SET_FEATURE(PORT_ENABLE)
3315 1.166 dsainty * should not be used by the USB subsystem. As we cannot issue a
3316 1.166 dsainty * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port
3317 1.166 dsainty * will be enabled as part of the reset.
3318 1.166 dsainty *
3319 1.166 dsainty * On the VT83C572, the port cannot be successfully enabled until the
3320 1.166 dsainty * outstanding "port enable change" and "connection status change"
3321 1.166 dsainty * events have been reset.
3322 1.166 dsainty */
3323 1.166 dsainty Static usbd_status
3324 1.166 dsainty uhci_portreset(uhci_softc_t *sc, int index)
3325 1.166 dsainty {
3326 1.166 dsainty int lim, port, x;
3327 1.166 dsainty
3328 1.166 dsainty if (index == 1)
3329 1.166 dsainty port = UHCI_PORTSC1;
3330 1.166 dsainty else if (index == 2)
3331 1.166 dsainty port = UHCI_PORTSC2;
3332 1.166 dsainty else
3333 1.264.4.13 skrll return USBD_IOERROR;
3334 1.166 dsainty
3335 1.166 dsainty x = URWMASK(UREAD2(sc, port));
3336 1.166 dsainty UWRITE2(sc, port, x | UHCI_PORTSC_PR);
3337 1.166 dsainty
3338 1.166 dsainty usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY);
3339 1.166 dsainty
3340 1.166 dsainty DPRINTFN(3,("uhci port %d reset, status0 = 0x%04x\n",
3341 1.166 dsainty index, UREAD2(sc, port)));
3342 1.166 dsainty
3343 1.166 dsainty x = URWMASK(UREAD2(sc, port));
3344 1.222 drochner UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP));
3345 1.166 dsainty
3346 1.166 dsainty delay(100);
3347 1.166 dsainty
3348 1.166 dsainty DPRINTFN(3,("uhci port %d reset, status1 = 0x%04x\n",
3349 1.166 dsainty index, UREAD2(sc, port)));
3350 1.166 dsainty
3351 1.166 dsainty x = URWMASK(UREAD2(sc, port));
3352 1.166 dsainty UWRITE2(sc, port, x | UHCI_PORTSC_PE);
3353 1.166 dsainty
3354 1.166 dsainty for (lim = 10; --lim > 0;) {
3355 1.166 dsainty usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY);
3356 1.166 dsainty
3357 1.166 dsainty x = UREAD2(sc, port);
3358 1.166 dsainty
3359 1.166 dsainty DPRINTFN(3,("uhci port %d iteration %u, status = 0x%04x\n",
3360 1.166 dsainty index, lim, x));
3361 1.166 dsainty
3362 1.166 dsainty if (!(x & UHCI_PORTSC_CCS)) {
3363 1.166 dsainty /*
3364 1.166 dsainty * No device is connected (or was disconnected
3365 1.166 dsainty * during reset). Consider the port reset.
3366 1.166 dsainty * The delay must be long enough to ensure on
3367 1.166 dsainty * the initial iteration that the device
3368 1.166 dsainty * connection will have been registered. 50ms
3369 1.166 dsainty * appears to be sufficient, but 20ms is not.
3370 1.166 dsainty */
3371 1.166 dsainty DPRINTFN(3,("uhci port %d loop %u, device detached\n",
3372 1.166 dsainty index, lim));
3373 1.166 dsainty break;
3374 1.166 dsainty }
3375 1.166 dsainty
3376 1.166 dsainty if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) {
3377 1.166 dsainty /*
3378 1.166 dsainty * Port enabled changed and/or connection
3379 1.166 dsainty * status changed were set. Reset either or
3380 1.166 dsainty * both raised flags (by writing a 1 to that
3381 1.166 dsainty * bit), and wait again for state to settle.
3382 1.166 dsainty */
3383 1.166 dsainty UWRITE2(sc, port, URWMASK(x) |
3384 1.166 dsainty (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)));
3385 1.166 dsainty continue;
3386 1.166 dsainty }
3387 1.166 dsainty
3388 1.166 dsainty if (x & UHCI_PORTSC_PE)
3389 1.166 dsainty /* Port is enabled */
3390 1.166 dsainty break;
3391 1.166 dsainty
3392 1.166 dsainty UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE);
3393 1.166 dsainty }
3394 1.166 dsainty
3395 1.166 dsainty DPRINTFN(3,("uhci port %d reset, status2 = 0x%04x\n",
3396 1.166 dsainty index, UREAD2(sc, port)));
3397 1.166 dsainty
3398 1.166 dsainty if (lim <= 0) {
3399 1.166 dsainty DPRINTFN(1,("uhci port %d reset timed out\n", index));
3400 1.264.4.13 skrll return USBD_TIMEOUT;
3401 1.166 dsainty }
3402 1.184 perry
3403 1.166 dsainty sc->sc_isreset = 1;
3404 1.264.4.13 skrll return USBD_NORMAL_COMPLETION;
3405 1.166 dsainty }
3406 1.166 dsainty
3407 1.264.4.12 skrll Static int
3408 1.264.4.12 skrll uhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req,
3409 1.264.4.12 skrll void *buf, int buflen)
3410 1.1 augustss {
3411 1.264.4.12 skrll uhci_softc_t *sc = bus->ub_hcpriv;
3412 1.1 augustss int port, x;
3413 1.264.4.12 skrll int status, change, totlen = 0;
3414 1.264.4.12 skrll uint16_t len, value, index;
3415 1.1 augustss usb_port_status_t ps;
3416 1.63 augustss usbd_status err;
3417 1.1 augustss
3418 1.82 augustss if (sc->sc_dying)
3419 1.264.4.12 skrll return -1;
3420 1.1 augustss
3421 1.264.4.12 skrll DPRINTFN(2,("%s: type=0x%02x request=%02x\n", __func__,
3422 1.264.4.12 skrll req->bmRequestType, req->bRequest));
3423 1.1 augustss
3424 1.1 augustss len = UGETW(req->wLength);
3425 1.1 augustss value = UGETW(req->wValue);
3426 1.1 augustss index = UGETW(req->wIndex);
3427 1.49 augustss
3428 1.1 augustss #define C(x,y) ((x) | ((y) << 8))
3429 1.264.4.12 skrll switch (C(req->bRequest, req->bmRequestType)) {
3430 1.1 augustss case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3431 1.264.4.12 skrll DPRINTFN(2,("%s: wValue=0x%04x\n", __func__, value));
3432 1.195 christos if (len == 0)
3433 1.195 christos break;
3434 1.264.4.12 skrll switch (value) {
3435 1.264.4.12 skrll case C(0, UDESC_DEVICE): {
3436 1.264.4.12 skrll usb_device_descriptor_t devd;
3437 1.264.4.12 skrll
3438 1.264.4.12 skrll totlen = min(buflen, sizeof(devd));
3439 1.264.4.12 skrll memcpy(&devd, buf, totlen);
3440 1.264.4.12 skrll USETW(devd.idVendor, sc->sc_id_vendor);
3441 1.264.4.12 skrll memcpy(buf, &devd, totlen);
3442 1.1 augustss break;
3443 1.264.4.12 skrll }
3444 1.264.4.12 skrll case C(1, UDESC_STRING):
3445 1.213 drochner #define sd ((usb_string_descriptor_t *)buf)
3446 1.264.4.12 skrll /* Vendor */
3447 1.264.4.12 skrll totlen = usb_makestrdesc(sd, len, sc->sc_vendor);
3448 1.264.4.12 skrll break;
3449 1.264.4.12 skrll case C(2, UDESC_STRING):
3450 1.264.4.12 skrll /* Product */
3451 1.264.4.12 skrll totlen = usb_makestrdesc(sd, len, "UHCI root hub");
3452 1.1 augustss break;
3453 1.264.4.12 skrll #undef sd
3454 1.1 augustss default:
3455 1.264.4.12 skrll /* default from usbroothub */
3456 1.264.4.12 skrll return buflen;
3457 1.1 augustss }
3458 1.1 augustss break;
3459 1.264.4.12 skrll
3460 1.1 augustss /* Hub requests */
3461 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3462 1.1 augustss break;
3463 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3464 1.264.4.12 skrll DPRINTFN(3, ("%s: UR_CLEAR_PORT_FEATURE "
3465 1.264.4.12 skrll "port=%d feature=%d\n", __func__,
3466 1.1 augustss index, value));
3467 1.1 augustss if (index == 1)
3468 1.1 augustss port = UHCI_PORTSC1;
3469 1.1 augustss else if (index == 2)
3470 1.1 augustss port = UHCI_PORTSC2;
3471 1.1 augustss else {
3472 1.264.4.12 skrll return -1;
3473 1.1 augustss }
3474 1.1 augustss switch(value) {
3475 1.1 augustss case UHF_PORT_ENABLE:
3476 1.137 augustss x = URWMASK(UREAD2(sc, port));
3477 1.1 augustss UWRITE2(sc, port, x & ~UHCI_PORTSC_PE);
3478 1.1 augustss break;
3479 1.1 augustss case UHF_PORT_SUSPEND:
3480 1.137 augustss x = URWMASK(UREAD2(sc, port));
3481 1.222 drochner if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */
3482 1.222 drochner break;
3483 1.222 drochner UWRITE2(sc, port, x | UHCI_PORTSC_RD);
3484 1.222 drochner /* see USB2 spec ch. 7.1.7.7 */
3485 1.222 drochner usb_delay_ms(&sc->sc_bus, 20);
3486 1.1 augustss UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP);
3487 1.222 drochner /* 10ms resume delay must be provided by caller */
3488 1.1 augustss break;
3489 1.1 augustss case UHF_PORT_RESET:
3490 1.137 augustss x = URWMASK(UREAD2(sc, port));
3491 1.1 augustss UWRITE2(sc, port, x & ~UHCI_PORTSC_PR);
3492 1.1 augustss break;
3493 1.1 augustss case UHF_C_PORT_CONNECTION:
3494 1.137 augustss x = URWMASK(UREAD2(sc, port));
3495 1.1 augustss UWRITE2(sc, port, x | UHCI_PORTSC_CSC);
3496 1.1 augustss break;
3497 1.1 augustss case UHF_C_PORT_ENABLE:
3498 1.137 augustss x = URWMASK(UREAD2(sc, port));
3499 1.1 augustss UWRITE2(sc, port, x | UHCI_PORTSC_POEDC);
3500 1.1 augustss break;
3501 1.1 augustss case UHF_C_PORT_OVER_CURRENT:
3502 1.137 augustss x = URWMASK(UREAD2(sc, port));
3503 1.1 augustss UWRITE2(sc, port, x | UHCI_PORTSC_OCIC);
3504 1.1 augustss break;
3505 1.1 augustss case UHF_C_PORT_RESET:
3506 1.1 augustss sc->sc_isreset = 0;
3507 1.264.4.16 skrll break;
3508 1.1 augustss case UHF_PORT_CONNECTION:
3509 1.1 augustss case UHF_PORT_OVER_CURRENT:
3510 1.1 augustss case UHF_PORT_POWER:
3511 1.1 augustss case UHF_PORT_LOW_SPEED:
3512 1.1 augustss case UHF_C_PORT_SUSPEND:
3513 1.1 augustss default:
3514 1.264.4.12 skrll return -1;
3515 1.1 augustss }
3516 1.1 augustss break;
3517 1.1 augustss case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER):
3518 1.1 augustss if (index == 1)
3519 1.1 augustss port = UHCI_PORTSC1;
3520 1.1 augustss else if (index == 2)
3521 1.1 augustss port = UHCI_PORTSC2;
3522 1.1 augustss else {
3523 1.264.4.12 skrll return -1;
3524 1.1 augustss }
3525 1.1 augustss if (len > 0) {
3526 1.264.4.1 skrll *(uint8_t *)buf =
3527 1.1 augustss (UREAD2(sc, port) & UHCI_PORTSC_LS) >>
3528 1.1 augustss UHCI_PORTSC_LS_SHIFT;
3529 1.1 augustss totlen = 1;
3530 1.1 augustss }
3531 1.1 augustss break;
3532 1.1 augustss case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3533 1.195 christos if (len == 0)
3534 1.195 christos break;
3535 1.177 toshii if ((value & 0xff) != 0) {
3536 1.264.4.12 skrll return -1;
3537 1.1 augustss }
3538 1.264.4.12 skrll usb_hub_descriptor_t hubd;
3539 1.264.4.12 skrll
3540 1.264.4.12 skrll totlen = min(buflen, sizeof(hubd));
3541 1.264.4.12 skrll memcpy(&hubd, buf, totlen);
3542 1.264.4.12 skrll hubd.bNbrPorts = 2;
3543 1.264.4.12 skrll memcpy(buf, &hubd, totlen);
3544 1.1 augustss break;
3545 1.1 augustss case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3546 1.1 augustss if (len != 4) {
3547 1.264.4.12 skrll return -1;
3548 1.1 augustss }
3549 1.1 augustss memset(buf, 0, len);
3550 1.1 augustss totlen = len;
3551 1.1 augustss break;
3552 1.1 augustss case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3553 1.1 augustss if (index == 1)
3554 1.1 augustss port = UHCI_PORTSC1;
3555 1.1 augustss else if (index == 2)
3556 1.1 augustss port = UHCI_PORTSC2;
3557 1.1 augustss else {
3558 1.264.4.12 skrll return -1;
3559 1.1 augustss }
3560 1.1 augustss if (len != 4) {
3561 1.264.4.12 skrll return -1;
3562 1.1 augustss }
3563 1.1 augustss x = UREAD2(sc, port);
3564 1.1 augustss status = change = 0;
3565 1.142 augustss if (x & UHCI_PORTSC_CCS)
3566 1.1 augustss status |= UPS_CURRENT_CONNECT_STATUS;
3567 1.152 augustss if (x & UHCI_PORTSC_CSC)
3568 1.1 augustss change |= UPS_C_CONNECT_STATUS;
3569 1.152 augustss if (x & UHCI_PORTSC_PE)
3570 1.1 augustss status |= UPS_PORT_ENABLED;
3571 1.152 augustss if (x & UHCI_PORTSC_POEDC)
3572 1.1 augustss change |= UPS_C_PORT_ENABLED;
3573 1.152 augustss if (x & UHCI_PORTSC_OCI)
3574 1.1 augustss status |= UPS_OVERCURRENT_INDICATOR;
3575 1.152 augustss if (x & UHCI_PORTSC_OCIC)
3576 1.1 augustss change |= UPS_C_OVERCURRENT_INDICATOR;
3577 1.152 augustss if (x & UHCI_PORTSC_SUSP)
3578 1.1 augustss status |= UPS_SUSPEND;
3579 1.152 augustss if (x & UHCI_PORTSC_LSDA)
3580 1.1 augustss status |= UPS_LOW_SPEED;
3581 1.1 augustss status |= UPS_PORT_POWER;
3582 1.1 augustss if (sc->sc_isreset)
3583 1.1 augustss change |= UPS_C_PORT_RESET;
3584 1.1 augustss USETW(ps.wPortStatus, status);
3585 1.1 augustss USETW(ps.wPortChange, change);
3586 1.264.4.12 skrll totlen = min(len, sizeof(ps));
3587 1.264.4.12 skrll memcpy(buf, &ps, totlen);
3588 1.1 augustss break;
3589 1.1 augustss case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3590 1.264.4.12 skrll return -1;
3591 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3592 1.1 augustss break;
3593 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3594 1.1 augustss if (index == 1)
3595 1.1 augustss port = UHCI_PORTSC1;
3596 1.1 augustss else if (index == 2)
3597 1.1 augustss port = UHCI_PORTSC2;
3598 1.1 augustss else {
3599 1.264.4.12 skrll return -1;
3600 1.1 augustss }
3601 1.1 augustss switch(value) {
3602 1.1 augustss case UHF_PORT_ENABLE:
3603 1.137 augustss x = URWMASK(UREAD2(sc, port));
3604 1.1 augustss UWRITE2(sc, port, x | UHCI_PORTSC_PE);
3605 1.1 augustss break;
3606 1.1 augustss case UHF_PORT_SUSPEND:
3607 1.137 augustss x = URWMASK(UREAD2(sc, port));
3608 1.1 augustss UWRITE2(sc, port, x | UHCI_PORTSC_SUSP);
3609 1.1 augustss break;
3610 1.1 augustss case UHF_PORT_RESET:
3611 1.166 dsainty err = uhci_portreset(sc, index);
3612 1.264.4.12 skrll if (err != USBD_NORMAL_COMPLETION)
3613 1.264.4.12 skrll return -1;
3614 1.264.4.12 skrll return 0;
3615 1.111 augustss case UHF_PORT_POWER:
3616 1.111 augustss /* Pretend we turned on power */
3617 1.264.4.12 skrll return 0;
3618 1.1 augustss case UHF_C_PORT_CONNECTION:
3619 1.1 augustss case UHF_C_PORT_ENABLE:
3620 1.1 augustss case UHF_C_PORT_OVER_CURRENT:
3621 1.1 augustss case UHF_PORT_CONNECTION:
3622 1.1 augustss case UHF_PORT_OVER_CURRENT:
3623 1.1 augustss case UHF_PORT_LOW_SPEED:
3624 1.1 augustss case UHF_C_PORT_SUSPEND:
3625 1.1 augustss case UHF_C_PORT_RESET:
3626 1.1 augustss default:
3627 1.264.4.12 skrll return -1;
3628 1.1 augustss }
3629 1.1 augustss break;
3630 1.1 augustss default:
3631 1.264.4.12 skrll /* default from usbroothub */
3632 1.264.4.12 skrll return buflen;
3633 1.1 augustss }
3634 1.1 augustss
3635 1.264.4.12 skrll return totlen;
3636 1.1 augustss }
3637 1.1 augustss
3638 1.1 augustss /* Abort a root interrupt request. */
3639 1.1 augustss void
3640 1.119 augustss uhci_root_intr_abort(usbd_xfer_handle xfer)
3641 1.1 augustss {
3642 1.264.4.7 skrll uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
3643 1.30 augustss
3644 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
3645 1.264.4.7 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
3646 1.248 mrg
3647 1.234 dyoung callout_stop(&sc->sc_poll_handle);
3648 1.96 augustss sc->sc_intr_xfer = NULL;
3649 1.58 augustss
3650 1.264.4.7 skrll xfer->ux_status = USBD_CANCELLED;
3651 1.96 augustss #ifdef DIAGNOSTIC
3652 1.96 augustss UXFER(xfer)->iinfo.isdone = 1;
3653 1.96 augustss #endif
3654 1.63 augustss usb_transfer_complete(xfer);
3655 1.1 augustss }
3656 1.1 augustss
3657 1.16 augustss usbd_status
3658 1.119 augustss uhci_root_intr_transfer(usbd_xfer_handle xfer)
3659 1.16 augustss {
3660 1.264.4.7 skrll uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
3661 1.63 augustss usbd_status err;
3662 1.16 augustss
3663 1.52 augustss /* Insert last in queue. */
3664 1.248 mrg mutex_enter(&sc->sc_lock);
3665 1.63 augustss err = usb_insert_transfer(xfer);
3666 1.248 mrg mutex_exit(&sc->sc_lock);
3667 1.63 augustss if (err)
3668 1.264.4.13 skrll return err;
3669 1.52 augustss
3670 1.186 skrll /*
3671 1.186 skrll * Pipe isn't running (otherwise err would be USBD_INPROG),
3672 1.67 augustss * start first
3673 1.67 augustss */
3674 1.264.4.13 skrll return uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
3675 1.16 augustss }
3676 1.16 augustss
3677 1.1 augustss /* Start a transfer on the root interrupt pipe */
3678 1.1 augustss usbd_status
3679 1.119 augustss uhci_root_intr_start(usbd_xfer_handle xfer)
3680 1.1 augustss {
3681 1.264.4.7 skrll usbd_pipe_handle pipe = xfer->ux_pipe;
3682 1.264.4.7 skrll uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv;
3683 1.174 drochner unsigned int ival;
3684 1.1 augustss
3685 1.173 gson DPRINTFN(3, ("uhci_root_intr_start: xfer=%p len=%d flags=%d\n",
3686 1.264.4.7 skrll xfer, xfer->ux_length, xfer->ux_flags));
3687 1.82 augustss
3688 1.82 augustss if (sc->sc_dying)
3689 1.264.4.13 skrll return USBD_IOERROR;
3690 1.1 augustss
3691 1.174 drochner /* XXX temporary variable needed to avoid gcc3 warning */
3692 1.264.4.7 skrll ival = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval;
3693 1.174 drochner sc->sc_ival = mstohz(ival);
3694 1.234 dyoung callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer);
3695 1.96 augustss sc->sc_intr_xfer = xfer;
3696 1.264.4.13 skrll return USBD_IN_PROGRESS;
3697 1.1 augustss }
3698 1.1 augustss
3699 1.1 augustss /* Close the root interrupt pipe. */
3700 1.1 augustss void
3701 1.119 augustss uhci_root_intr_close(usbd_pipe_handle pipe)
3702 1.1 augustss {
3703 1.264.4.7 skrll uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv;
3704 1.30 augustss
3705 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
3706 1.248 mrg
3707 1.234 dyoung callout_stop(&sc->sc_poll_handle);
3708 1.96 augustss sc->sc_intr_xfer = NULL;
3709 1.1 augustss DPRINTF(("uhci_root_intr_close\n"));
3710 1.1 augustss }
3711