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uhci.c revision 1.264.4.20
      1  1.264.4.20     skrll /*	$NetBSD: uhci.c,v 1.264.4.20 2015/02/20 09:16:49 skrll Exp $	*/
      2         1.1  augustss 
      3         1.1  augustss /*
      4       1.248       mrg  * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc.
      5         1.1  augustss  * All rights reserved.
      6         1.1  augustss  *
      7        1.11  augustss  * This code is derived from software contributed to The NetBSD Foundation
      8       1.113  augustss  * by Lennart Augustsson (lennart (at) augustsson.net) at
      9       1.248       mrg  * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca)
     10       1.248       mrg  * and Matthew R. Green (mrg (at) eterna.com.au).
     11         1.1  augustss  *
     12         1.1  augustss  * Redistribution and use in source and binary forms, with or without
     13         1.1  augustss  * modification, are permitted provided that the following conditions
     14         1.1  augustss  * are met:
     15         1.1  augustss  * 1. Redistributions of source code must retain the above copyright
     16         1.1  augustss  *    notice, this list of conditions and the following disclaimer.
     17         1.1  augustss  * 2. Redistributions in binary form must reproduce the above copyright
     18         1.1  augustss  *    notice, this list of conditions and the following disclaimer in the
     19         1.1  augustss  *    documentation and/or other materials provided with the distribution.
     20         1.1  augustss  *
     21         1.1  augustss  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     22         1.1  augustss  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     23         1.1  augustss  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     24         1.1  augustss  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     25         1.1  augustss  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     26         1.1  augustss  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     27         1.1  augustss  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     28         1.1  augustss  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     29         1.1  augustss  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     30         1.1  augustss  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     31         1.1  augustss  * POSSIBILITY OF SUCH DAMAGE.
     32         1.1  augustss  */
     33         1.1  augustss 
     34         1.1  augustss /*
     35         1.1  augustss  * USB Universal Host Controller driver.
     36        1.28  augustss  * Handles e.g. PIIX3 and PIIX4.
     37         1.1  augustss  *
     38       1.229  uebayasi  * UHCI spec: http://www.intel.com/technology/usb/spec.htm
     39       1.229  uebayasi  * USB spec: http://www.usb.org/developers/docs/
     40        1.71  augustss  * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf
     41        1.71  augustss  *             ftp://download.intel.com/design/intarch/datashts/29056201.pdf
     42         1.1  augustss  */
     43       1.143     lukem 
     44       1.143     lukem #include <sys/cdefs.h>
     45  1.264.4.20     skrll __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.264.4.20 2015/02/20 09:16:49 skrll Exp $");
     46         1.1  augustss 
     47         1.1  augustss #include <sys/param.h>
     48  1.264.4.20     skrll 
     49  1.264.4.20     skrll #include <sys/bus.h>
     50  1.264.4.20     skrll #include <sys/cpu.h>
     51  1.264.4.20     skrll #include <sys/device.h>
     52         1.1  augustss #include <sys/kernel.h>
     53       1.248       mrg #include <sys/kmem.h>
     54  1.264.4.20     skrll #include <sys/mutex.h>
     55         1.1  augustss #include <sys/proc.h>
     56         1.1  augustss #include <sys/queue.h>
     57  1.264.4.20     skrll #include <sys/select.h>
     58  1.264.4.20     skrll #include <sys/sysctl.h>
     59  1.264.4.20     skrll #include <sys/systm.h>
     60         1.1  augustss 
     61        1.39  augustss #include <machine/endian.h>
     62         1.7  augustss 
     63         1.1  augustss #include <dev/usb/usb.h>
     64         1.1  augustss #include <dev/usb/usbdi.h>
     65         1.1  augustss #include <dev/usb/usbdivar.h>
     66         1.7  augustss #include <dev/usb/usb_mem.h>
     67         1.1  augustss #include <dev/usb/usb_quirks.h>
     68         1.1  augustss 
     69         1.1  augustss #include <dev/usb/uhcireg.h>
     70         1.1  augustss #include <dev/usb/uhcivar.h>
     71  1.264.4.11     skrll #include <dev/usb/usbroothub.h>
     72         1.1  augustss 
     73       1.125  augustss /* Use bandwidth reclamation for control transfers. Some devices choke on it. */
     74       1.125  augustss /*#define UHCI_CTL_LOOP */
     75       1.125  augustss 
     76        1.13  augustss 
     77        1.37  augustss 
     78        1.67  augustss #ifdef UHCI_DEBUG
     79        1.92  augustss uhci_softc_t *thesc;
     80        1.59  augustss #define DPRINTF(x)	if (uhcidebug) printf x
     81        1.59  augustss #define DPRINTFN(n,x)	if (uhcidebug>(n)) printf x
     82        1.67  augustss int uhcidebug = 0;
     83       1.125  augustss int uhcinoloop = 0;
     84        1.59  augustss #else
     85        1.59  augustss #define DPRINTF(x)
     86        1.59  augustss #define DPRINTFN(n,x)
     87        1.59  augustss #endif
     88        1.59  augustss 
     89        1.39  augustss /*
     90        1.39  augustss  * The UHCI controller is little endian, so on big endian machines
     91       1.181  drochner  * the data stored in memory needs to be swapped.
     92        1.39  augustss  */
     93        1.39  augustss 
     94         1.1  augustss struct uhci_pipe {
     95         1.1  augustss 	struct usbd_pipe pipe;
     96        1.32  augustss 	int nexttoggle;
     97        1.92  augustss 
     98        1.92  augustss 	u_char aborting;
     99        1.92  augustss 	usbd_xfer_handle abortstart, abortend;
    100        1.92  augustss 
    101         1.1  augustss 	/* Info needed for different pipe kinds. */
    102         1.1  augustss 	union {
    103         1.1  augustss 		/* Control pipe */
    104         1.1  augustss 		struct {
    105         1.1  augustss 			uhci_soft_qh_t *sqh;
    106         1.7  augustss 			usb_dma_t reqdma;
    107        1.16  augustss 			uhci_soft_td_t *setup, *stat;
    108         1.1  augustss 			u_int length;
    109         1.1  augustss 		} ctl;
    110         1.1  augustss 		/* Interrupt pipe */
    111         1.1  augustss 		struct {
    112         1.1  augustss 			int npoll;
    113       1.187     skrll 			int isread;
    114         1.1  augustss 			uhci_soft_qh_t **qhs;
    115         1.1  augustss 		} intr;
    116         1.1  augustss 		/* Bulk pipe */
    117         1.1  augustss 		struct {
    118         1.1  augustss 			uhci_soft_qh_t *sqh;
    119         1.1  augustss 			u_int length;
    120         1.1  augustss 			int isread;
    121         1.1  augustss 		} bulk;
    122        1.16  augustss 		/* Iso pipe */
    123        1.16  augustss 		struct iso {
    124        1.16  augustss 			uhci_soft_td_t **stds;
    125        1.48  augustss 			int next, inuse;
    126        1.16  augustss 		} iso;
    127         1.1  augustss 	} u;
    128         1.1  augustss };
    129         1.1  augustss 
    130       1.142  augustss Static void		uhci_globalreset(uhci_softc_t *);
    131       1.166   dsainty Static usbd_status	uhci_portreset(uhci_softc_t*, int);
    132       1.142  augustss Static void		uhci_reset(uhci_softc_t *);
    133  1.264.4.15     skrll Static usbd_status	uhci_run(uhci_softc_t *, int, int);
    134       1.123  augustss Static uhci_soft_td_t  *uhci_alloc_std(uhci_softc_t *);
    135       1.119  augustss Static void		uhci_free_std(uhci_softc_t *, uhci_soft_td_t *);
    136       1.123  augustss Static uhci_soft_qh_t  *uhci_alloc_sqh(uhci_softc_t *);
    137       1.119  augustss Static void		uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *);
    138        1.16  augustss #if 0
    139       1.119  augustss Static void		uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *,
    140       1.119  augustss 					 uhci_intr_info_t *);
    141       1.119  augustss Static void		uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *);
    142        1.16  augustss #endif
    143         1.1  augustss 
    144       1.152  augustss Static void		uhci_free_std_chain(uhci_softc_t *,
    145       1.119  augustss 					    uhci_soft_td_t *, uhci_soft_td_t *);
    146       1.119  augustss Static usbd_status	uhci_alloc_std_chain(struct uhci_pipe *,
    147   1.264.4.1     skrll 			    uhci_softc_t *, int, int, uint16_t, usb_dma_t *,
    148       1.119  augustss 			    uhci_soft_td_t **, uhci_soft_td_t **);
    149       1.119  augustss Static void		uhci_poll_hub(void *);
    150       1.119  augustss Static void		uhci_waitintr(uhci_softc_t *, usbd_xfer_handle);
    151       1.119  augustss Static void		uhci_check_intr(uhci_softc_t *, uhci_intr_info_t *);
    152       1.119  augustss Static void		uhci_idone(uhci_intr_info_t *);
    153       1.119  augustss 
    154  1.264.4.15     skrll Static void		uhci_abort_xfer(usbd_xfer_handle, usbd_status);
    155       1.119  augustss 
    156       1.119  augustss Static void		uhci_timeout(void *);
    157       1.153  augustss Static void		uhci_timeout_task(void *);
    158       1.123  augustss Static void		uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *);
    159       1.123  augustss Static void		uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *);
    160       1.119  augustss Static void		uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *);
    161       1.123  augustss Static void		uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *);
    162       1.123  augustss Static void		uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *);
    163       1.119  augustss Static void		uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *);
    164  1.264.4.15     skrll Static void		uhci_add_loop(uhci_softc_t *);
    165  1.264.4.15     skrll Static void		uhci_rem_loop(uhci_softc_t *);
    166       1.119  augustss 
    167  1.264.4.15     skrll Static usbd_status	uhci_setup_isoc(usbd_pipe_handle);
    168       1.119  augustss Static void		uhci_device_isoc_enter(usbd_xfer_handle);
    169       1.119  augustss 
    170       1.119  augustss Static usbd_xfer_handle	uhci_allocx(struct usbd_bus *);
    171       1.119  augustss Static void		uhci_freex(struct usbd_bus *, usbd_xfer_handle);
    172       1.248       mrg Static void		uhci_get_lock(struct usbd_bus *, kmutex_t **);
    173  1.264.4.13     skrll Static int		uhci_roothub_ctrl(struct usbd_bus *,
    174  1.264.4.12     skrll     usb_device_request_t *, void *, int);
    175       1.119  augustss 
    176       1.119  augustss Static usbd_status	uhci_device_ctrl_transfer(usbd_xfer_handle);
    177       1.119  augustss Static usbd_status	uhci_device_ctrl_start(usbd_xfer_handle);
    178       1.119  augustss Static void		uhci_device_ctrl_abort(usbd_xfer_handle);
    179       1.119  augustss Static void		uhci_device_ctrl_close(usbd_pipe_handle);
    180       1.119  augustss Static void		uhci_device_ctrl_done(usbd_xfer_handle);
    181       1.119  augustss 
    182       1.119  augustss Static usbd_status	uhci_device_intr_transfer(usbd_xfer_handle);
    183       1.119  augustss Static usbd_status	uhci_device_intr_start(usbd_xfer_handle);
    184       1.119  augustss Static void		uhci_device_intr_abort(usbd_xfer_handle);
    185       1.119  augustss Static void		uhci_device_intr_close(usbd_pipe_handle);
    186       1.119  augustss Static void		uhci_device_intr_done(usbd_xfer_handle);
    187       1.119  augustss 
    188       1.119  augustss Static usbd_status	uhci_device_bulk_transfer(usbd_xfer_handle);
    189       1.119  augustss Static usbd_status	uhci_device_bulk_start(usbd_xfer_handle);
    190       1.119  augustss Static void		uhci_device_bulk_abort(usbd_xfer_handle);
    191       1.119  augustss Static void		uhci_device_bulk_close(usbd_pipe_handle);
    192       1.119  augustss Static void		uhci_device_bulk_done(usbd_xfer_handle);
    193       1.119  augustss 
    194       1.119  augustss Static usbd_status	uhci_device_isoc_transfer(usbd_xfer_handle);
    195       1.119  augustss Static usbd_status	uhci_device_isoc_start(usbd_xfer_handle);
    196       1.119  augustss Static void		uhci_device_isoc_abort(usbd_xfer_handle);
    197       1.119  augustss Static void		uhci_device_isoc_close(usbd_pipe_handle);
    198       1.119  augustss Static void		uhci_device_isoc_done(usbd_xfer_handle);
    199       1.119  augustss 
    200       1.119  augustss Static usbd_status	uhci_root_intr_transfer(usbd_xfer_handle);
    201       1.119  augustss Static usbd_status	uhci_root_intr_start(usbd_xfer_handle);
    202       1.119  augustss Static void		uhci_root_intr_abort(usbd_xfer_handle);
    203       1.119  augustss Static void		uhci_root_intr_close(usbd_pipe_handle);
    204       1.119  augustss Static void		uhci_root_intr_done(usbd_xfer_handle);
    205       1.119  augustss 
    206       1.119  augustss Static usbd_status	uhci_open(usbd_pipe_handle);
    207       1.119  augustss Static void		uhci_poll(struct usbd_bus *);
    208       1.133  augustss Static void		uhci_softintr(void *);
    209       1.119  augustss 
    210  1.264.4.15     skrll Static usbd_status	uhci_device_request(usbd_xfer_handle);
    211       1.119  augustss 
    212       1.119  augustss Static void		uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *);
    213       1.158  augustss Static void		uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *);
    214  1.264.4.15     skrll Static usbd_status	uhci_device_setintr(uhci_softc_t *,
    215  1.264.4.15     skrll 			    struct uhci_pipe *, int);
    216       1.119  augustss 
    217  1.264.4.15     skrll Static void		uhci_device_clear_toggle(usbd_pipe_handle);
    218  1.264.4.15     skrll Static void		uhci_noop(usbd_pipe_handle);
    219       1.119  augustss 
    220       1.240  jakllsch static inline uhci_soft_qh_t *uhci_find_prev_qh(uhci_soft_qh_t *,
    221       1.119  augustss 						    uhci_soft_qh_t *);
    222       1.119  augustss 
    223       1.119  augustss #ifdef UHCI_DEBUG
    224       1.119  augustss Static void		uhci_dump_all(uhci_softc_t *);
    225       1.119  augustss Static void		uhci_dumpregs(uhci_softc_t *);
    226       1.119  augustss Static void		uhci_dump_qhs(uhci_soft_qh_t *);
    227       1.119  augustss Static void		uhci_dump_qh(uhci_soft_qh_t *);
    228       1.119  augustss Static void		uhci_dump_tds(uhci_soft_td_t *);
    229       1.119  augustss Static void		uhci_dump_td(uhci_soft_td_t *);
    230  1.264.4.15     skrll Static void		uhci_dump_ii(uhci_intr_info_t *);
    231       1.119  augustss void			uhci_dump(void);
    232         1.1  augustss #endif
    233         1.1  augustss 
    234       1.112  augustss #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \
    235       1.112  augustss 			BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
    236       1.112  augustss #define UWRITE1(sc, r, x) \
    237       1.165   dsainty  do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \
    238       1.165   dsainty  } while (/*CONSTCOND*/0)
    239       1.112  augustss #define UWRITE2(sc, r, x) \
    240       1.165   dsainty  do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \
    241       1.165   dsainty  } while (/*CONSTCOND*/0)
    242       1.112  augustss #define UWRITE4(sc, r, x) \
    243       1.165   dsainty  do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \
    244       1.165   dsainty  } while (/*CONSTCOND*/0)
    245       1.196       mrg static __inline uint8_t
    246       1.196       mrg UREAD1(uhci_softc_t *sc, bus_size_t r)
    247       1.196       mrg {
    248       1.196       mrg 
    249       1.196       mrg 	UBARR(sc);
    250       1.196       mrg 	return bus_space_read_1(sc->iot, sc->ioh, r);
    251       1.196       mrg }
    252       1.196       mrg 
    253       1.196       mrg static __inline uint16_t
    254       1.196       mrg UREAD2(uhci_softc_t *sc, bus_size_t r)
    255       1.196       mrg {
    256       1.196       mrg 
    257       1.196       mrg 	UBARR(sc);
    258       1.196       mrg 	return bus_space_read_2(sc->iot, sc->ioh, r);
    259       1.196       mrg }
    260       1.196       mrg 
    261       1.260     joerg #ifdef UHCI_DEBUG
    262       1.196       mrg static __inline uint32_t
    263       1.196       mrg UREAD4(uhci_softc_t *sc, bus_size_t r)
    264       1.196       mrg {
    265       1.196       mrg 
    266       1.196       mrg 	UBARR(sc);
    267       1.196       mrg 	return bus_space_read_4(sc->iot, sc->ioh, r);
    268       1.196       mrg }
    269       1.260     joerg #endif
    270         1.1  augustss 
    271         1.1  augustss #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd)
    272         1.1  augustss #define UHCISTS(sc) UREAD2(sc, UHCI_STS)
    273         1.1  augustss 
    274       1.142  augustss #define UHCI_RESET_TIMEOUT 100	/* ms, reset timeout */
    275         1.1  augustss 
    276         1.1  augustss #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK)
    277         1.1  augustss 
    278       1.208  drochner const struct usbd_bus_methods uhci_bus_methods = {
    279   1.264.4.5     skrll 	.ubm_open =	uhci_open,
    280   1.264.4.5     skrll 	.ubm_softint =	uhci_softintr,
    281   1.264.4.5     skrll 	.ubm_dopoll =	uhci_poll,
    282   1.264.4.5     skrll 	.ubm_allocx =	uhci_allocx,
    283   1.264.4.5     skrll 	.ubm_freex =	uhci_freex,
    284   1.264.4.5     skrll 	.ubm_getlock =	uhci_get_lock,
    285  1.264.4.12     skrll 	.ubm_rhctrl =	uhci_roothub_ctrl,
    286         1.1  augustss };
    287         1.1  augustss 
    288       1.208  drochner const struct usbd_pipe_methods uhci_root_intr_methods = {
    289   1.264.4.5     skrll 	.upm_transfer =	uhci_root_intr_transfer,
    290   1.264.4.5     skrll 	.upm_start =	uhci_root_intr_start,
    291   1.264.4.5     skrll 	.upm_abort =	uhci_root_intr_abort,
    292   1.264.4.5     skrll 	.upm_close =	uhci_root_intr_close,
    293   1.264.4.5     skrll 	.upm_cleartoggle =	uhci_noop,
    294   1.264.4.5     skrll 	.upm_done =	uhci_root_intr_done,
    295         1.1  augustss };
    296         1.1  augustss 
    297       1.208  drochner const struct usbd_pipe_methods uhci_device_ctrl_methods = {
    298   1.264.4.5     skrll 	.upm_transfer =	uhci_device_ctrl_transfer,
    299   1.264.4.5     skrll 	.upm_start =	uhci_device_ctrl_start,
    300   1.264.4.5     skrll 	.upm_abort =	uhci_device_ctrl_abort,
    301   1.264.4.5     skrll 	.upm_close =	uhci_device_ctrl_close,
    302   1.264.4.5     skrll 	.upm_cleartoggle =	uhci_noop,
    303   1.264.4.5     skrll 	.upm_done =	uhci_device_ctrl_done,
    304         1.1  augustss };
    305         1.1  augustss 
    306       1.208  drochner const struct usbd_pipe_methods uhci_device_intr_methods = {
    307   1.264.4.5     skrll 	.upm_transfer =	uhci_device_intr_transfer,
    308   1.264.4.5     skrll 	.upm_start =	uhci_device_intr_start,
    309   1.264.4.5     skrll 	.upm_abort =	uhci_device_intr_abort,
    310   1.264.4.5     skrll 	.upm_close =	uhci_device_intr_close,
    311   1.264.4.5     skrll 	.upm_cleartoggle =	uhci_device_clear_toggle,
    312   1.264.4.5     skrll 	.upm_done =	uhci_device_intr_done,
    313         1.1  augustss };
    314         1.1  augustss 
    315       1.208  drochner const struct usbd_pipe_methods uhci_device_bulk_methods = {
    316   1.264.4.5     skrll 	.upm_transfer =	uhci_device_bulk_transfer,
    317   1.264.4.5     skrll 	.upm_start =	uhci_device_bulk_start,
    318   1.264.4.5     skrll 	.upm_abort =	uhci_device_bulk_abort,
    319   1.264.4.5     skrll 	.upm_close =	uhci_device_bulk_close,
    320   1.264.4.5     skrll 	.upm_cleartoggle =	uhci_device_clear_toggle,
    321   1.264.4.5     skrll 	.upm_done =	uhci_device_bulk_done,
    322         1.1  augustss };
    323         1.1  augustss 
    324       1.208  drochner const struct usbd_pipe_methods uhci_device_isoc_methods = {
    325   1.264.4.5     skrll 	.upm_transfer =	uhci_device_isoc_transfer,
    326   1.264.4.5     skrll 	.upm_start =	uhci_device_isoc_start,
    327   1.264.4.5     skrll 	.upm_abort =	uhci_device_isoc_abort,
    328   1.264.4.5     skrll 	.upm_close =	uhci_device_isoc_close,
    329   1.264.4.5     skrll 	.upm_cleartoggle =	uhci_noop,
    330   1.264.4.5     skrll 	.upm_done =	uhci_device_isoc_done,
    331        1.16  augustss };
    332        1.16  augustss 
    333        1.92  augustss #define uhci_add_intr_info(sc, ii) \
    334       1.169  augustss 	LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ii), list)
    335        1.92  augustss #define uhci_del_intr_info(ii) \
    336       1.169  augustss 	do { \
    337       1.169  augustss 		LIST_REMOVE((ii), list); \
    338       1.169  augustss 		(ii)->list.le_prev = NULL; \
    339       1.169  augustss 	} while (0)
    340       1.169  augustss #define uhci_active_intr_info(ii) ((ii)->list.le_prev != NULL)
    341        1.92  augustss 
    342       1.240  jakllsch static inline uhci_soft_qh_t *
    343       1.119  augustss uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh)
    344        1.92  augustss {
    345        1.92  augustss 	DPRINTFN(15,("uhci_find_prev_qh: pqh=%p sqh=%p\n", pqh, sqh));
    346        1.92  augustss 
    347        1.92  augustss 	for (; pqh->hlink != sqh; pqh = pqh->hlink) {
    348       1.152  augustss #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG)
    349       1.223    bouyer 		usb_syncmem(&pqh->dma,
    350       1.223    bouyer 		    pqh->offs + offsetof(uhci_qh_t, qh_hlink),
    351       1.223    bouyer 		    sizeof(pqh->qh.qh_hlink),
    352       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE);
    353        1.92  augustss 		if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) {
    354       1.102  augustss 			printf("uhci_find_prev_qh: QH not found\n");
    355  1.264.4.13     skrll 			return NULL;
    356        1.92  augustss 		}
    357        1.92  augustss #endif
    358        1.92  augustss 	}
    359  1.264.4.13     skrll 	return pqh;
    360        1.92  augustss }
    361        1.92  augustss 
    362         1.1  augustss void
    363       1.142  augustss uhci_globalreset(uhci_softc_t *sc)
    364         1.1  augustss {
    365         1.1  augustss 	UHCICMD(sc, UHCI_CMD_GRESET);	/* global reset */
    366        1.20  augustss 	usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */
    367         1.1  augustss 	UHCICMD(sc, 0);			/* do nothing */
    368         1.1  augustss }
    369         1.1  augustss 
    370  1.264.4.14     skrll int
    371       1.119  augustss uhci_init(uhci_softc_t *sc)
    372         1.1  augustss {
    373        1.63  augustss 	usbd_status err;
    374         1.1  augustss 	int i, j;
    375       1.123  augustss 	uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh;
    376         1.1  augustss 	uhci_soft_td_t *std;
    377         1.1  augustss 
    378         1.1  augustss 	DPRINTFN(1,("uhci_init: start\n"));
    379         1.1  augustss 
    380        1.67  augustss #ifdef UHCI_DEBUG
    381        1.92  augustss 	thesc = sc;
    382        1.92  augustss 
    383         1.1  augustss 	if (uhcidebug > 2)
    384         1.1  augustss 		uhci_dumpregs(sc);
    385         1.1  augustss #endif
    386         1.1  augustss 
    387       1.219  jmcneill 	sc->sc_suspend = PWR_RESUME;
    388       1.219  jmcneill 
    389         1.1  augustss 	UWRITE2(sc, UHCI_INTR, 0);		/* disable interrupts */
    390       1.142  augustss 	uhci_globalreset(sc);			/* reset the controller */
    391       1.142  augustss 	uhci_reset(sc);
    392        1.24  augustss 
    393         1.1  augustss 	/* Allocate and initialize real frame array. */
    394       1.152  augustss 	err = usb_allocmem(&sc->sc_bus,
    395        1.63  augustss 		  UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t),
    396        1.63  augustss 		  UHCI_FRAMELIST_ALIGN, &sc->sc_dma);
    397        1.63  augustss 	if (err)
    398  1.264.4.13     skrll 		return err;
    399       1.159  augustss 	sc->sc_pframes = KERNADDR(&sc->sc_dma, 0);
    400         1.1  augustss 	UWRITE2(sc, UHCI_FRNUM, 0);		/* set frame number to 0 */
    401       1.160  augustss 	UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/
    402         1.1  augustss 
    403       1.152  augustss 	/*
    404       1.123  augustss 	 * Allocate a TD, inactive, that hangs from the last QH.
    405       1.123  augustss 	 * This is to avoid a bug in the PIIX that makes it run berserk
    406       1.123  augustss 	 * otherwise.
    407       1.123  augustss 	 */
    408       1.123  augustss 	std = uhci_alloc_std(sc);
    409       1.123  augustss 	if (std == NULL)
    410  1.264.4.14     skrll 		return ENOMEM;
    411       1.123  augustss 	std->link.std = NULL;
    412       1.123  augustss 	std->td.td_link = htole32(UHCI_PTR_T);
    413       1.123  augustss 	std->td.td_status = htole32(0); /* inactive */
    414       1.123  augustss 	std->td.td_token = htole32(0);
    415       1.123  augustss 	std->td.td_buffer = htole32(0);
    416       1.223    bouyer 	usb_syncmem(&std->dma, std->offs, sizeof(std->td),
    417       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
    418       1.123  augustss 
    419       1.123  augustss 	/* Allocate the dummy QH marking the end and used for looping the QHs.*/
    420       1.123  augustss 	lsqh = uhci_alloc_sqh(sc);
    421       1.123  augustss 	if (lsqh == NULL)
    422  1.264.4.14     skrll 		return ENOMEM;
    423       1.123  augustss 	lsqh->hlink = NULL;
    424       1.123  augustss 	lsqh->qh.qh_hlink = htole32(UHCI_PTR_T);	/* end of QH chain */
    425       1.123  augustss 	lsqh->elink = std;
    426       1.123  augustss 	lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD);
    427       1.123  augustss 	sc->sc_last_qh = lsqh;
    428       1.223    bouyer 	usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh),
    429       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
    430       1.123  augustss 
    431         1.1  augustss 	/* Allocate the dummy QH where bulk traffic will be queued. */
    432         1.1  augustss 	bsqh = uhci_alloc_sqh(sc);
    433        1.63  augustss 	if (bsqh == NULL)
    434  1.264.4.14     skrll 		return ENOMEM;
    435       1.123  augustss 	bsqh->hlink = lsqh;
    436       1.123  augustss 	bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH);
    437       1.121  augustss 	bsqh->elink = NULL;
    438        1.88   tsutsui 	bsqh->qh.qh_elink = htole32(UHCI_PTR_T);
    439         1.1  augustss 	sc->sc_bulk_start = sc->sc_bulk_end = bsqh;
    440       1.223    bouyer 	usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh),
    441       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
    442         1.1  augustss 
    443       1.123  augustss 	/* Allocate dummy QH where high speed control traffic will be queued. */
    444       1.123  augustss 	chsqh = uhci_alloc_sqh(sc);
    445       1.123  augustss 	if (chsqh == NULL)
    446  1.264.4.14     skrll 		return ENOMEM;
    447       1.123  augustss 	chsqh->hlink = bsqh;
    448       1.123  augustss 	chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH);
    449       1.123  augustss 	chsqh->elink = NULL;
    450       1.123  augustss 	chsqh->qh.qh_elink = htole32(UHCI_PTR_T);
    451       1.123  augustss 	sc->sc_hctl_start = sc->sc_hctl_end = chsqh;
    452       1.223    bouyer 	usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh),
    453       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
    454       1.123  augustss 
    455       1.123  augustss 	/* Allocate dummy QH where control traffic will be queued. */
    456       1.123  augustss 	clsqh = uhci_alloc_sqh(sc);
    457       1.123  augustss 	if (clsqh == NULL)
    458  1.264.4.14     skrll 		return ENOMEM;
    459       1.220    bouyer 	clsqh->hlink = chsqh;
    460       1.123  augustss 	clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH);
    461       1.123  augustss 	clsqh->elink = NULL;
    462       1.123  augustss 	clsqh->qh.qh_elink = htole32(UHCI_PTR_T);
    463       1.123  augustss 	sc->sc_lctl_start = sc->sc_lctl_end = clsqh;
    464       1.223    bouyer 	usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh),
    465       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
    466         1.1  augustss 
    467       1.152  augustss 	/*
    468         1.1  augustss 	 * Make all (virtual) frame list pointers point to the interrupt
    469         1.1  augustss 	 * queue heads and the interrupt queue heads at the control
    470         1.1  augustss 	 * queue head and point the physical frame list to the virtual.
    471         1.1  augustss 	 */
    472         1.1  augustss 	for(i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
    473         1.1  augustss 		std = uhci_alloc_std(sc);
    474         1.1  augustss 		sqh = uhci_alloc_sqh(sc);
    475        1.67  augustss 		if (std == NULL || sqh == NULL)
    476  1.264.4.13     skrll 			return USBD_NOMEM;
    477        1.42  augustss 		std->link.sqh = sqh;
    478       1.121  augustss 		std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH);
    479        1.88   tsutsui 		std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */
    480        1.88   tsutsui 		std->td.td_token = htole32(0);
    481        1.88   tsutsui 		std->td.td_buffer = htole32(0);
    482       1.223    bouyer 		usb_syncmem(&std->dma, std->offs, sizeof(std->td),
    483       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
    484       1.123  augustss 		sqh->hlink = clsqh;
    485       1.123  augustss 		sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH);
    486       1.121  augustss 		sqh->elink = NULL;
    487        1.88   tsutsui 		sqh->qh.qh_elink = htole32(UHCI_PTR_T);
    488       1.223    bouyer 		usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
    489       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
    490         1.1  augustss 		sc->sc_vframes[i].htd = std;
    491         1.1  augustss 		sc->sc_vframes[i].etd = std;
    492         1.1  augustss 		sc->sc_vframes[i].hqh = sqh;
    493         1.1  augustss 		sc->sc_vframes[i].eqh = sqh;
    494       1.152  augustss 		for (j = i;
    495       1.152  augustss 		     j < UHCI_FRAMELIST_COUNT;
    496         1.1  augustss 		     j += UHCI_VFRAMELIST_COUNT)
    497        1.88   tsutsui 			sc->sc_pframes[j] = htole32(std->physaddr);
    498         1.1  augustss 	}
    499       1.223    bouyer 	usb_syncmem(&sc->sc_dma, 0,
    500       1.223    bouyer 	    UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t),
    501       1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
    502       1.223    bouyer 
    503         1.1  augustss 
    504         1.1  augustss 	LIST_INIT(&sc->sc_intrhead);
    505         1.1  augustss 
    506       1.253  christos 	sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0,
    507       1.253  christos 	    "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL);
    508        1.76  augustss 
    509       1.248       mrg 	callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE);
    510       1.248       mrg 
    511       1.248       mrg 	mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
    512       1.248       mrg 	mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED);
    513       1.248       mrg 	cv_init(&sc->sc_softwake_cv, "uhciab");
    514        1.96  augustss 
    515         1.1  augustss 	/* Set up the bus struct. */
    516   1.264.4.7     skrll 	sc->sc_bus.ub_methods = &uhci_bus_methods;
    517   1.264.4.7     skrll 	sc->sc_bus.ub_pipesize = sizeof(struct uhci_pipe);
    518   1.264.4.7     skrll 	sc->sc_bus.ub_usedma = true;
    519         1.1  augustss 
    520       1.190  augustss 	UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */
    521       1.190  augustss 
    522         1.1  augustss 	DPRINTFN(1,("uhci_init: enabling\n"));
    523       1.225    bouyer 
    524       1.249  drochner 	err =  uhci_run(sc, 1, 0);		/* and here we go... */
    525       1.152  augustss 	UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE |
    526         1.1  augustss 		UHCI_INTR_IOCE | UHCI_INTR_SPIE);	/* enable interrupts */
    527       1.225    bouyer 	return err;
    528        1.53  augustss }
    529        1.53  augustss 
    530        1.53  augustss int
    531       1.215    dyoung uhci_activate(device_t self, enum devact act)
    532        1.53  augustss {
    533       1.215    dyoung 	struct uhci_softc *sc = device_private(self);
    534        1.53  augustss 
    535        1.53  augustss 	switch (act) {
    536        1.53  augustss 	case DVACT_DEACTIVATE:
    537       1.210  kiyohara 		sc->sc_dying = 1;
    538       1.230    dyoung 		return 0;
    539       1.230    dyoung 	default:
    540       1.230    dyoung 		return EOPNOTSUPP;
    541        1.53  augustss 	}
    542        1.53  augustss }
    543        1.53  augustss 
    544       1.215    dyoung void
    545       1.215    dyoung uhci_childdet(device_t self, device_t child)
    546       1.215    dyoung {
    547       1.215    dyoung 	struct uhci_softc *sc = device_private(self);
    548       1.215    dyoung 
    549       1.215    dyoung 	KASSERT(sc->sc_child == child);
    550       1.215    dyoung 	sc->sc_child = NULL;
    551       1.215    dyoung }
    552       1.215    dyoung 
    553        1.53  augustss int
    554       1.119  augustss uhci_detach(struct uhci_softc *sc, int flags)
    555        1.53  augustss {
    556        1.53  augustss 	int rv = 0;
    557        1.53  augustss 
    558        1.53  augustss 	if (sc->sc_child != NULL)
    559        1.53  augustss 		rv = config_detach(sc->sc_child, flags);
    560       1.152  augustss 
    561        1.53  augustss 	if (rv != 0)
    562  1.264.4.13     skrll 		return rv;
    563        1.53  augustss 
    564       1.226        ad 	callout_halt(&sc->sc_poll_handle, NULL);
    565       1.226        ad 	callout_destroy(&sc->sc_poll_handle);
    566       1.226        ad 
    567       1.248       mrg 	cv_destroy(&sc->sc_softwake_cv);
    568       1.248       mrg 
    569       1.248       mrg 	mutex_destroy(&sc->sc_lock);
    570       1.248       mrg 	mutex_destroy(&sc->sc_intr_lock);
    571       1.248       mrg 
    572       1.254  christos 	pool_cache_destroy(sc->sc_xferpool);
    573       1.254  christos 
    574        1.76  augustss 	/* XXX free other data structures XXX */
    575        1.53  augustss 
    576  1.264.4.13     skrll 	return rv;
    577         1.1  augustss }
    578         1.1  augustss 
    579        1.76  augustss usbd_xfer_handle
    580       1.119  augustss uhci_allocx(struct usbd_bus *bus)
    581        1.76  augustss {
    582   1.264.4.7     skrll 	struct uhci_softc *sc = bus->ub_hcpriv;
    583        1.76  augustss 	usbd_xfer_handle xfer;
    584        1.76  augustss 
    585       1.253  christos 	xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT);
    586        1.92  augustss 	if (xfer != NULL) {
    587       1.253  christos 		memset(xfer, 0, sizeof(struct uhci_xfer));
    588       1.254  christos 		UXFER(xfer)->iinfo.sc = sc;
    589        1.92  augustss #ifdef DIAGNOSTIC
    590       1.238   tsutsui 		UXFER(xfer)->iinfo.isdone = 1;
    591   1.264.4.7     skrll 		xfer->ux_state = XFER_BUSY;
    592        1.92  augustss #endif
    593        1.92  augustss 	}
    594  1.264.4.13     skrll 	return xfer;
    595        1.76  augustss }
    596        1.76  augustss 
    597        1.76  augustss void
    598       1.119  augustss uhci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer)
    599        1.76  augustss {
    600   1.264.4.7     skrll 	struct uhci_softc *sc = bus->ub_hcpriv;
    601        1.76  augustss 
    602        1.93  augustss #ifdef DIAGNOSTIC
    603   1.264.4.7     skrll 	if (xfer->ux_state != XFER_BUSY) {
    604        1.94  augustss 		printf("uhci_freex: xfer=%p not busy, 0x%08x\n", xfer,
    605   1.264.4.7     skrll 		       xfer->ux_state);
    606        1.93  augustss 	}
    607   1.264.4.7     skrll 	xfer->ux_state = XFER_FREE;
    608       1.238   tsutsui 	if (!UXFER(xfer)->iinfo.isdone) {
    609        1.96  augustss 		printf("uhci_freex: !isdone\n");
    610       1.105  augustss 	}
    611        1.93  augustss #endif
    612       1.253  christos 	pool_cache_put(sc->sc_xferpool, xfer);
    613        1.48  augustss }
    614        1.48  augustss 
    615       1.248       mrg Static void
    616       1.248       mrg uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock)
    617       1.248       mrg {
    618   1.264.4.7     skrll 	struct uhci_softc *sc = bus->ub_hcpriv;
    619       1.248       mrg 
    620       1.248       mrg 	*lock = &sc->sc_lock;
    621       1.248       mrg }
    622       1.248       mrg 
    623       1.248       mrg 
    624        1.72  augustss /*
    625       1.212  jmcneill  * Handle suspend/resume.
    626       1.212  jmcneill  *
    627       1.212  jmcneill  * We need to switch to polling mode here, because this routine is
    628       1.212  jmcneill  * called from an interrupt context.  This is all right since we
    629       1.212  jmcneill  * are almost suspended anyway.
    630        1.72  augustss  */
    631       1.212  jmcneill bool
    632       1.232    dyoung uhci_resume(device_t dv, const pmf_qual_t *qual)
    633        1.72  augustss {
    634       1.212  jmcneill 	uhci_softc_t *sc = device_private(dv);
    635       1.212  jmcneill 	int cmd;
    636        1.72  augustss 
    637       1.248       mrg 	mutex_spin_enter(&sc->sc_intr_lock);
    638       1.193  augustss 
    639       1.212  jmcneill 	cmd = UREAD2(sc, UHCI_CMD);
    640   1.264.4.7     skrll 	sc->sc_bus.ub_usepolling++;
    641       1.214       smb 	UWRITE2(sc, UHCI_INTR, 0);
    642       1.214       smb 	uhci_globalreset(sc);
    643       1.214       smb 	uhci_reset(sc);
    644       1.212  jmcneill 	if (cmd & UHCI_CMD_RS)
    645       1.249  drochner 		uhci_run(sc, 0, 1);
    646       1.212  jmcneill 
    647       1.212  jmcneill 	/* restore saved state */
    648       1.212  jmcneill 	UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0));
    649       1.212  jmcneill 	UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum);
    650       1.212  jmcneill 	UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof);
    651       1.212  jmcneill 
    652       1.212  jmcneill 	UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */
    653       1.248       mrg 	usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock);
    654       1.212  jmcneill 	UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */
    655       1.212  jmcneill 	UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE |
    656       1.212  jmcneill 	    UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE);
    657       1.214       smb 	UHCICMD(sc, UHCI_CMD_MAXP);
    658       1.249  drochner 	uhci_run(sc, 1, 1); /* and start traffic again */
    659       1.248       mrg 	usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock);
    660   1.264.4.7     skrll 	sc->sc_bus.ub_usepolling--;
    661       1.212  jmcneill 	if (sc->sc_intr_xfer != NULL)
    662       1.234    dyoung 		callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub,
    663       1.212  jmcneill 		    sc->sc_intr_xfer);
    664       1.212  jmcneill #ifdef UHCI_DEBUG
    665       1.212  jmcneill 	if (uhcidebug > 2)
    666       1.212  jmcneill 		uhci_dumpregs(sc);
    667       1.212  jmcneill #endif
    668       1.212  jmcneill 
    669       1.219  jmcneill 	sc->sc_suspend = PWR_RESUME;
    670       1.248       mrg 	mutex_spin_exit(&sc->sc_intr_lock);
    671       1.212  jmcneill 
    672       1.212  jmcneill 	return true;
    673        1.72  augustss }
    674        1.72  augustss 
    675       1.212  jmcneill bool
    676       1.232    dyoung uhci_suspend(device_t dv, const pmf_qual_t *qual)
    677        1.30  augustss {
    678       1.212  jmcneill 	uhci_softc_t *sc = device_private(dv);
    679        1.30  augustss 	int cmd;
    680        1.30  augustss 
    681       1.248       mrg 	mutex_spin_enter(&sc->sc_intr_lock);
    682       1.212  jmcneill 
    683        1.30  augustss 	cmd = UREAD2(sc, UHCI_CMD);
    684        1.30  augustss 
    685       1.212  jmcneill #ifdef UHCI_DEBUG
    686       1.212  jmcneill 	if (uhcidebug > 2)
    687       1.212  jmcneill 		uhci_dumpregs(sc);
    688       1.212  jmcneill #endif
    689       1.212  jmcneill 	if (sc->sc_intr_xfer != NULL)
    690       1.234    dyoung 		callout_stop(&sc->sc_poll_handle);
    691       1.219  jmcneill 	sc->sc_suspend = PWR_SUSPEND;
    692   1.264.4.7     skrll 	sc->sc_bus.ub_usepolling++;
    693       1.219  jmcneill 
    694       1.249  drochner 	uhci_run(sc, 0, 1); /* stop the controller */
    695       1.212  jmcneill 	cmd &= ~UHCI_CMD_RS;
    696       1.212  jmcneill 
    697       1.212  jmcneill 	/* save some state if BIOS doesn't */
    698       1.212  jmcneill 	sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM);
    699       1.212  jmcneill 	sc->sc_saved_sof = UREAD1(sc, UHCI_SOF);
    700       1.212  jmcneill 
    701       1.212  jmcneill 	UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */
    702        1.30  augustss 
    703       1.212  jmcneill 	UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */
    704       1.248       mrg 	usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock);
    705   1.264.4.7     skrll 	sc->sc_bus.ub_usepolling--;
    706        1.86  augustss 
    707       1.248       mrg 	mutex_spin_exit(&sc->sc_intr_lock);
    708       1.212  jmcneill 
    709       1.212  jmcneill 	return true;
    710        1.30  augustss }
    711        1.30  augustss 
    712        1.59  augustss #ifdef UHCI_DEBUG
    713       1.101  augustss Static void
    714       1.119  augustss uhci_dumpregs(uhci_softc_t *sc)
    715         1.1  augustss {
    716        1.48  augustss 	DPRINTFN(-1,("%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, "
    717        1.48  augustss 		     "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n",
    718       1.216  drochner 		     device_xname(sc->sc_dev),
    719        1.48  augustss 		     UREAD2(sc, UHCI_CMD),
    720        1.48  augustss 		     UREAD2(sc, UHCI_STS),
    721        1.48  augustss 		     UREAD2(sc, UHCI_INTR),
    722        1.48  augustss 		     UREAD2(sc, UHCI_FRNUM),
    723        1.48  augustss 		     UREAD4(sc, UHCI_FLBASEADDR),
    724        1.48  augustss 		     UREAD1(sc, UHCI_SOF),
    725        1.48  augustss 		     UREAD2(sc, UHCI_PORTSC1),
    726        1.48  augustss 		     UREAD2(sc, UHCI_PORTSC2)));
    727         1.1  augustss }
    728         1.1  augustss 
    729         1.1  augustss void
    730       1.119  augustss uhci_dump_td(uhci_soft_td_t *p)
    731         1.1  augustss {
    732       1.122        tv 	char sbuf[128], sbuf2[128];
    733       1.122        tv 
    734       1.250  christos 
    735       1.223    bouyer 	usb_syncmem(&p->dma, p->offs, sizeof(p->td),
    736       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
    737        1.48  augustss 	DPRINTFN(-1,("TD(%p) at %08lx = link=0x%08lx status=0x%08lx "
    738        1.48  augustss 		     "token=0x%08lx buffer=0x%08lx\n",
    739        1.48  augustss 		     p, (long)p->physaddr,
    740        1.88   tsutsui 		     (long)le32toh(p->td.td_link),
    741        1.88   tsutsui 		     (long)le32toh(p->td.td_status),
    742        1.88   tsutsui 		     (long)le32toh(p->td.td_token),
    743        1.88   tsutsui 		     (long)le32toh(p->td.td_buffer)));
    744       1.122        tv 
    745       1.224  christos 	snprintb(sbuf, sizeof(sbuf), "\20\1T\2Q\3VF",
    746   1.264.4.1     skrll 	    (uint32_t)le32toh(p->td.td_link));
    747       1.224  christos 	snprintb(sbuf2, sizeof(sbuf2),
    748       1.224  christos 	    "\20\22BITSTUFF\23CRCTO\24NAK\25BABBLE\26DBUFFER\27"
    749       1.224  christos 	    "STALLED\30ACTIVE\31IOC\32ISO\33LS\36SPD",
    750   1.264.4.1     skrll 	    (uint32_t)le32toh(p->td.td_status));
    751       1.122        tv 
    752       1.122        tv 	DPRINTFN(-1,("  %s %s,errcnt=%d,actlen=%d pid=%02x,addr=%d,endpt=%d,"
    753       1.122        tv 		     "D=%d,maxlen=%d\n", sbuf, sbuf2,
    754        1.88   tsutsui 		     UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)),
    755        1.88   tsutsui 		     UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)),
    756        1.88   tsutsui 		     UHCI_TD_GET_PID(le32toh(p->td.td_token)),
    757        1.88   tsutsui 		     UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)),
    758        1.88   tsutsui 		     UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)),
    759        1.88   tsutsui 		     UHCI_TD_GET_DT(le32toh(p->td.td_token)),
    760        1.88   tsutsui 		     UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token))));
    761       1.223    bouyer 	usb_syncmem(&p->dma, p->offs, sizeof(p->td),
    762       1.223    bouyer 	    BUS_DMASYNC_PREREAD);
    763         1.1  augustss }
    764         1.1  augustss 
    765         1.1  augustss void
    766       1.119  augustss uhci_dump_qh(uhci_soft_qh_t *sqh)
    767         1.1  augustss {
    768       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
    769       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
    770        1.67  augustss 	DPRINTFN(-1,("QH(%p) at %08x: hlink=%08x elink=%08x\n", sqh,
    771        1.88   tsutsui 	    (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink),
    772        1.88   tsutsui 	    le32toh(sqh->qh.qh_elink)));
    773       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD);
    774         1.1  augustss }
    775         1.1  augustss 
    776        1.13  augustss 
    777       1.110  augustss #if 1
    778         1.1  augustss void
    779       1.119  augustss uhci_dump(void)
    780         1.1  augustss {
    781       1.110  augustss 	uhci_dump_all(thesc);
    782       1.110  augustss }
    783       1.110  augustss #endif
    784         1.1  augustss 
    785       1.110  augustss void
    786       1.119  augustss uhci_dump_all(uhci_softc_t *sc)
    787       1.110  augustss {
    788         1.1  augustss 	uhci_dumpregs(sc);
    789       1.110  augustss 	/*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/
    790       1.261     skrll 	uhci_dump_qhs(sc->sc_lctl_start);
    791         1.1  augustss }
    792         1.1  augustss 
    793        1.67  augustss 
    794        1.67  augustss void
    795       1.119  augustss uhci_dump_qhs(uhci_soft_qh_t *sqh)
    796        1.67  augustss {
    797        1.67  augustss 	uhci_dump_qh(sqh);
    798        1.67  augustss 
    799  1.264.4.18     skrll 	/*
    800  1.264.4.18     skrll 	 * uhci_dump_qhs displays all the QHs and TDs from the given QH onwards
    801        1.67  augustss 	 * Traverses sideways first, then down.
    802        1.67  augustss 	 *
    803        1.67  augustss 	 * QH1
    804        1.67  augustss 	 * QH2
    805        1.67  augustss 	 * No QH
    806        1.67  augustss 	 * TD2.1
    807        1.67  augustss 	 * TD2.2
    808        1.67  augustss 	 * TD1.1
    809        1.67  augustss 	 * etc.
    810        1.67  augustss 	 *
    811        1.67  augustss 	 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1.
    812        1.67  augustss 	 */
    813        1.67  augustss 
    814        1.67  augustss 
    815       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
    816       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
    817        1.88   tsutsui 	if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T))
    818        1.67  augustss 		uhci_dump_qhs(sqh->hlink);
    819        1.67  augustss 	else
    820        1.67  augustss 		DPRINTF(("No QH\n"));
    821       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD);
    822        1.67  augustss 
    823        1.88   tsutsui 	if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T))
    824        1.67  augustss 		uhci_dump_tds(sqh->elink);
    825        1.67  augustss 	else
    826        1.67  augustss 		DPRINTF(("No TD\n"));
    827        1.67  augustss }
    828        1.67  augustss 
    829         1.1  augustss void
    830       1.119  augustss uhci_dump_tds(uhci_soft_td_t *std)
    831         1.1  augustss {
    832        1.67  augustss 	uhci_soft_td_t *td;
    833       1.223    bouyer 	int stop;
    834        1.67  augustss 
    835        1.67  augustss 	for(td = std; td != NULL; td = td->link.std) {
    836        1.67  augustss 		uhci_dump_td(td);
    837         1.1  augustss 
    838  1.264.4.18     skrll 		/*
    839  1.264.4.18     skrll 		 * Check whether the link pointer in this TD marks
    840        1.67  augustss 		 * the link pointer as end of queue. This avoids
    841        1.67  augustss 		 * printing the free list in case the queue/TD has
    842        1.67  augustss 		 * already been moved there (seatbelt).
    843        1.67  augustss 		 */
    844       1.223    bouyer 		usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link),
    845       1.223    bouyer 		    sizeof(td->td.td_link),
    846       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
    847       1.223    bouyer 		stop = (le32toh(td->td.td_link) & UHCI_PTR_T ||
    848       1.223    bouyer 			le32toh(td->td.td_link) == 0);
    849       1.223    bouyer 		usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link),
    850       1.223    bouyer 		    sizeof(td->td.td_link), BUS_DMASYNC_PREREAD);
    851       1.223    bouyer 		if (stop)
    852        1.67  augustss 			break;
    853        1.67  augustss 	}
    854         1.1  augustss }
    855        1.92  augustss 
    856       1.101  augustss Static void
    857       1.119  augustss uhci_dump_ii(uhci_intr_info_t *ii)
    858        1.92  augustss {
    859        1.95  augustss 	usbd_pipe_handle pipe;
    860        1.95  augustss 	usb_endpoint_descriptor_t *ed;
    861        1.95  augustss 	usbd_device_handle dev;
    862       1.152  augustss 
    863        1.98  augustss #ifdef DIAGNOSTIC
    864        1.98  augustss #define DONE ii->isdone
    865        1.98  augustss #else
    866        1.98  augustss #define DONE 0
    867        1.98  augustss #endif
    868   1.264.4.2     skrll 	if (ii == NULL) {
    869   1.264.4.2     skrll 		printf("ii NULL\n");
    870   1.264.4.2     skrll 		return;
    871   1.264.4.2     skrll 	}
    872   1.264.4.2     skrll 	if (ii->xfer == NULL) {
    873        1.95  augustss 		printf("ii %p: done=%d xfer=NULL\n",
    874        1.98  augustss 		       ii, DONE);
    875   1.264.4.2     skrll 		return;
    876   1.264.4.2     skrll 	}
    877   1.264.4.7     skrll 	pipe = ii->xfer->ux_pipe;
    878   1.264.4.2     skrll 	if (pipe == NULL) {
    879        1.95  augustss 		printf("ii %p: done=%d xfer=%p pipe=NULL\n",
    880   1.264.4.2     skrll 		    ii, DONE, ii->xfer);
    881   1.264.4.2     skrll 		return;
    882       1.139  augustss 	}
    883   1.264.4.7     skrll 	if (pipe->up_endpoint == NULL) {
    884   1.264.4.7     skrll 		printf("ii %p: done=%d xfer=%p pipe=%p pipe->up_endpoint=NULL\n",
    885       1.139  augustss 		       ii, DONE, ii->xfer, pipe);
    886   1.264.4.2     skrll 		return;
    887       1.139  augustss 	}
    888   1.264.4.7     skrll 	if (pipe->up_dev == NULL) {
    889   1.264.4.7     skrll 		printf("ii %p: done=%d xfer=%p pipe=%p pipe->up_dev=NULL\n",
    890       1.139  augustss 		       ii, DONE, ii->xfer, pipe);
    891   1.264.4.2     skrll 		return;
    892        1.95  augustss 	}
    893   1.264.4.7     skrll 	ed = pipe->up_endpoint->ue_edesc;
    894   1.264.4.7     skrll 	dev = pipe->up_dev;
    895       1.152  augustss 	printf("ii %p: done=%d xfer=%p dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n",
    896       1.152  augustss 	       ii, DONE, ii->xfer, dev,
    897   1.264.4.7     skrll 	       UGETW(dev->ud_ddesc.idVendor),
    898   1.264.4.7     skrll 	       UGETW(dev->ud_ddesc.idProduct),
    899   1.264.4.7     skrll 	       dev->ud_addr, pipe,
    900        1.92  augustss 	       ed->bEndpointAddress, ed->bmAttributes);
    901        1.98  augustss #undef DONE
    902        1.92  augustss }
    903        1.92  augustss 
    904       1.120  augustss void uhci_dump_iis(struct uhci_softc *sc);
    905        1.92  augustss void
    906       1.119  augustss uhci_dump_iis(struct uhci_softc *sc)
    907        1.92  augustss {
    908        1.92  augustss 	uhci_intr_info_t *ii;
    909        1.92  augustss 
    910        1.92  augustss 	printf("intr_info list:\n");
    911        1.92  augustss 	for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = LIST_NEXT(ii, list))
    912        1.92  augustss 		uhci_dump_ii(ii);
    913        1.92  augustss }
    914        1.92  augustss 
    915       1.120  augustss void iidump(void);
    916       1.119  augustss void iidump(void) { uhci_dump_iis(thesc); }
    917        1.92  augustss 
    918         1.1  augustss #endif
    919         1.1  augustss 
    920         1.1  augustss /*
    921         1.1  augustss  * This routine is executed periodically and simulates interrupts
    922         1.1  augustss  * from the root controller interrupt pipe for port status change.
    923         1.1  augustss  */
    924         1.1  augustss void
    925       1.119  augustss uhci_poll_hub(void *addr)
    926         1.1  augustss {
    927        1.63  augustss 	usbd_xfer_handle xfer = addr;
    928   1.264.4.7     skrll 	usbd_pipe_handle pipe = xfer->ux_pipe;
    929       1.227    martin 	uhci_softc_t *sc;
    930         1.1  augustss 	u_char *p;
    931         1.1  augustss 
    932        1.96  augustss 	DPRINTFN(20, ("uhci_poll_hub\n"));
    933         1.1  augustss 
    934   1.264.4.7     skrll 	if (__predict_false(pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL))
    935       1.228    martin 		return;	/* device has detached */
    936   1.264.4.7     skrll 	sc = pipe->up_dev->ud_bus->ub_hcpriv;
    937       1.234    dyoung 	callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer);
    938        1.41  augustss 
    939   1.264.4.7     skrll 	p = xfer->ux_buf;
    940         1.1  augustss 	p[0] = 0;
    941         1.1  augustss 	if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC))
    942         1.1  augustss 		p[0] |= 1<<1;
    943         1.1  augustss 	if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC))
    944         1.1  augustss 		p[0] |= 1<<2;
    945        1.41  augustss 	if (p[0] == 0)
    946        1.41  augustss 		/* No change, try again in a while */
    947        1.41  augustss 		return;
    948        1.41  augustss 
    949   1.264.4.7     skrll 	xfer->ux_actlen = 1;
    950   1.264.4.7     skrll 	xfer->ux_status = USBD_NORMAL_COMPLETION;
    951       1.248       mrg 	mutex_enter(&sc->sc_lock);
    952        1.63  augustss 	usb_transfer_complete(xfer);
    953       1.248       mrg 	mutex_exit(&sc->sc_lock);
    954        1.41  augustss }
    955        1.41  augustss 
    956        1.41  augustss void
    957       1.205  christos uhci_root_intr_done(usbd_xfer_handle xfer)
    958        1.84  augustss {
    959        1.84  augustss }
    960        1.84  augustss 
    961       1.123  augustss /*
    962       1.123  augustss  * Let the last QH loop back to the high speed control transfer QH.
    963       1.123  augustss  * This is what intel calls "bandwidth reclamation" and improves
    964       1.123  augustss  * USB performance a lot for some devices.
    965       1.123  augustss  * If we are already looping, just count it.
    966       1.123  augustss  */
    967         1.1  augustss void
    968  1.264.4.17     skrll uhci_add_loop(uhci_softc_t *sc)
    969  1.264.4.17     skrll {
    970       1.125  augustss #ifdef UHCI_DEBUG
    971       1.125  augustss 	if (uhcinoloop)
    972       1.125  augustss 		return;
    973       1.125  augustss #endif
    974       1.123  augustss 	if (++sc->sc_loops == 1) {
    975       1.125  augustss 		DPRINTFN(5,("uhci_start_loop: add\n"));
    976       1.123  augustss 		/* Note, we don't loop back the soft pointer. */
    977       1.152  augustss 		sc->sc_last_qh->qh.qh_hlink =
    978       1.123  augustss 		    htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH);
    979       1.223    bouyer 		usb_syncmem(&sc->sc_last_qh->dma,
    980       1.223    bouyer 		    sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink),
    981       1.223    bouyer 		    sizeof(sc->sc_last_qh->qh.qh_hlink),
    982       1.223    bouyer 		    BUS_DMASYNC_PREWRITE);
    983       1.123  augustss 	}
    984       1.123  augustss }
    985       1.123  augustss 
    986       1.123  augustss void
    987  1.264.4.17     skrll uhci_rem_loop(uhci_softc_t *sc)
    988  1.264.4.17     skrll {
    989       1.125  augustss #ifdef UHCI_DEBUG
    990       1.125  augustss 	if (uhcinoloop)
    991       1.125  augustss 		return;
    992       1.125  augustss #endif
    993       1.123  augustss 	if (--sc->sc_loops == 0) {
    994       1.123  augustss 		DPRINTFN(5,("uhci_end_loop: remove\n"));
    995       1.123  augustss 		sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T);
    996       1.223    bouyer 		usb_syncmem(&sc->sc_last_qh->dma,
    997       1.223    bouyer 		    sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink),
    998       1.223    bouyer 		    sizeof(sc->sc_last_qh->qh.qh_hlink),
    999       1.223    bouyer 		    BUS_DMASYNC_PREWRITE);
   1000       1.123  augustss 	}
   1001       1.123  augustss }
   1002       1.123  augustss 
   1003       1.248       mrg /* Add high speed control QH, called with lock held. */
   1004       1.123  augustss void
   1005       1.123  augustss uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   1006         1.1  augustss {
   1007        1.42  augustss 	uhci_soft_qh_t *eqh;
   1008         1.1  augustss 
   1009       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   1010       1.248       mrg 
   1011         1.1  augustss 	DPRINTFN(10, ("uhci_add_ctrl: sqh=%p\n", sqh));
   1012       1.123  augustss 	eqh = sc->sc_hctl_end;
   1013       1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1014       1.223    bouyer 	    sizeof(eqh->qh.qh_hlink),
   1015       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE);
   1016        1.42  augustss 	sqh->hlink       = eqh->hlink;
   1017        1.42  augustss 	sqh->qh.qh_hlink = eqh->qh.qh_hlink;
   1018       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
   1019       1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   1020        1.42  augustss 	eqh->hlink       = sqh;
   1021       1.121  augustss 	eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
   1022       1.123  augustss 	sc->sc_hctl_end = sqh;
   1023       1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1024       1.223    bouyer 	    sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
   1025       1.125  augustss #ifdef UHCI_CTL_LOOP
   1026       1.123  augustss 	uhci_add_loop(sc);
   1027       1.125  augustss #endif
   1028         1.1  augustss }
   1029         1.1  augustss 
   1030       1.248       mrg /* Remove high speed control QH, called with lock held. */
   1031         1.1  augustss void
   1032       1.123  augustss uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   1033         1.1  augustss {
   1034         1.1  augustss 	uhci_soft_qh_t *pqh;
   1035       1.256   tsutsui 	uint32_t elink;
   1036         1.1  augustss 
   1037       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   1038       1.248       mrg 
   1039       1.123  augustss 	DPRINTFN(10, ("uhci_remove_hs_ctrl: sqh=%p\n", sqh));
   1040       1.125  augustss #ifdef UHCI_CTL_LOOP
   1041       1.123  augustss 	uhci_rem_loop(sc);
   1042       1.125  augustss #endif
   1043       1.124  augustss 	/*
   1044       1.124  augustss 	 * The T bit should be set in the elink of the QH so that the HC
   1045       1.124  augustss 	 * doesn't follow the pointer.  This condition may fail if the
   1046       1.124  augustss 	 * the transferred packet was short so that the QH still points
   1047       1.124  augustss 	 * at the last used TD.
   1048       1.124  augustss 	 * In this case we set the T bit and wait a little for the HC
   1049       1.124  augustss 	 * to stop looking at the TD.
   1050       1.223    bouyer 	 * Note that if the TD chain is large enough, the controller
   1051       1.223    bouyer 	 * may still be looking at the chain at the end of this function.
   1052       1.223    bouyer 	 * uhci_free_std_chain() will make sure the controller stops
   1053       1.223    bouyer 	 * looking at it quickly, but until then we should not change
   1054       1.223    bouyer 	 * sqh->hlink.
   1055       1.124  augustss 	 */
   1056       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1057       1.223    bouyer 	    sizeof(sqh->qh.qh_elink),
   1058       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1059       1.256   tsutsui 	elink = le32toh(sqh->qh.qh_elink);
   1060       1.256   tsutsui 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1061       1.256   tsutsui 	    sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD);
   1062       1.256   tsutsui 	if (!(elink & UHCI_PTR_T)) {
   1063       1.124  augustss 		sqh->qh.qh_elink = htole32(UHCI_PTR_T);
   1064       1.223    bouyer 		usb_syncmem(&sqh->dma,
   1065       1.223    bouyer 		    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1066       1.223    bouyer 		    sizeof(sqh->qh.qh_elink),
   1067       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   1068       1.124  augustss 		delay(UHCI_QH_REMOVE_DELAY);
   1069       1.124  augustss 	}
   1070       1.124  augustss 
   1071       1.123  augustss 	pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh);
   1072       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1073       1.223    bouyer 	    sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
   1074       1.152  augustss 	pqh->hlink = sqh->hlink;
   1075        1.42  augustss 	pqh->qh.qh_hlink = sqh->qh.qh_hlink;
   1076       1.223    bouyer 	usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1077       1.223    bouyer 	    sizeof(pqh->qh.qh_hlink),
   1078       1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   1079       1.124  augustss 	delay(UHCI_QH_REMOVE_DELAY);
   1080       1.123  augustss 	if (sc->sc_hctl_end == sqh)
   1081       1.123  augustss 		sc->sc_hctl_end = pqh;
   1082       1.123  augustss }
   1083       1.123  augustss 
   1084       1.248       mrg /* Add low speed control QH, called with lock held. */
   1085       1.123  augustss void
   1086       1.123  augustss uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   1087       1.123  augustss {
   1088       1.123  augustss 	uhci_soft_qh_t *eqh;
   1089       1.123  augustss 
   1090       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   1091       1.248       mrg 
   1092       1.123  augustss 	DPRINTFN(10, ("uhci_add_ls_ctrl: sqh=%p\n", sqh));
   1093       1.123  augustss 	eqh = sc->sc_lctl_end;
   1094       1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1095       1.223    bouyer 	    sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
   1096       1.152  augustss 	sqh->hlink = eqh->hlink;
   1097       1.123  augustss 	sqh->qh.qh_hlink = eqh->qh.qh_hlink;
   1098       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
   1099       1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   1100       1.152  augustss 	eqh->hlink = sqh;
   1101       1.123  augustss 	eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
   1102       1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1103       1.223    bouyer 	    sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
   1104       1.123  augustss 	sc->sc_lctl_end = sqh;
   1105       1.123  augustss }
   1106       1.123  augustss 
   1107       1.248       mrg /* Remove low speed control QH, called with lock held. */
   1108       1.123  augustss void
   1109       1.123  augustss uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   1110       1.123  augustss {
   1111       1.123  augustss 	uhci_soft_qh_t *pqh;
   1112       1.256   tsutsui 	uint32_t elink;
   1113       1.123  augustss 
   1114       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   1115       1.248       mrg 
   1116       1.123  augustss 	DPRINTFN(10, ("uhci_remove_ls_ctrl: sqh=%p\n", sqh));
   1117       1.124  augustss 	/* See comment in uhci_remove_hs_ctrl() */
   1118       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1119       1.223    bouyer 	    sizeof(sqh->qh.qh_elink),
   1120       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1121       1.256   tsutsui 	elink = le32toh(sqh->qh.qh_elink);
   1122       1.256   tsutsui 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1123       1.256   tsutsui 	    sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD);
   1124       1.256   tsutsui 	if (!(elink & UHCI_PTR_T)) {
   1125       1.124  augustss 		sqh->qh.qh_elink = htole32(UHCI_PTR_T);
   1126       1.223    bouyer 		usb_syncmem(&sqh->dma,
   1127       1.223    bouyer 		    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1128       1.223    bouyer 		    sizeof(sqh->qh.qh_elink),
   1129       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   1130       1.124  augustss 		delay(UHCI_QH_REMOVE_DELAY);
   1131       1.124  augustss 	}
   1132       1.123  augustss 	pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh);
   1133       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1134       1.223    bouyer 	    sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
   1135       1.152  augustss 	pqh->hlink = sqh->hlink;
   1136       1.123  augustss 	pqh->qh.qh_hlink = sqh->qh.qh_hlink;
   1137       1.223    bouyer 	usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1138       1.223    bouyer 	    sizeof(pqh->qh.qh_hlink),
   1139       1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   1140       1.124  augustss 	delay(UHCI_QH_REMOVE_DELAY);
   1141       1.123  augustss 	if (sc->sc_lctl_end == sqh)
   1142       1.123  augustss 		sc->sc_lctl_end = pqh;
   1143         1.1  augustss }
   1144         1.1  augustss 
   1145       1.248       mrg /* Add bulk QH, called with lock held. */
   1146         1.1  augustss void
   1147       1.119  augustss uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   1148         1.1  augustss {
   1149        1.42  augustss 	uhci_soft_qh_t *eqh;
   1150         1.1  augustss 
   1151       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   1152       1.248       mrg 
   1153         1.1  augustss 	DPRINTFN(10, ("uhci_add_bulk: sqh=%p\n", sqh));
   1154        1.42  augustss 	eqh = sc->sc_bulk_end;
   1155       1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1156       1.223    bouyer 	    sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
   1157       1.152  augustss 	sqh->hlink = eqh->hlink;
   1158        1.42  augustss 	sqh->qh.qh_hlink = eqh->qh.qh_hlink;
   1159       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
   1160       1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   1161       1.152  augustss 	eqh->hlink = sqh;
   1162       1.121  augustss 	eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
   1163       1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1164       1.223    bouyer 	    sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
   1165         1.1  augustss 	sc->sc_bulk_end = sqh;
   1166       1.123  augustss 	uhci_add_loop(sc);
   1167         1.1  augustss }
   1168         1.1  augustss 
   1169       1.248       mrg /* Remove bulk QH, called with lock held. */
   1170         1.1  augustss void
   1171       1.119  augustss uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   1172         1.1  augustss {
   1173         1.1  augustss 	uhci_soft_qh_t *pqh;
   1174         1.1  augustss 
   1175       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   1176       1.248       mrg 
   1177         1.1  augustss 	DPRINTFN(10, ("uhci_remove_bulk: sqh=%p\n", sqh));
   1178       1.123  augustss 	uhci_rem_loop(sc);
   1179       1.124  augustss 	/* See comment in uhci_remove_hs_ctrl() */
   1180       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1181       1.223    bouyer 	    sizeof(sqh->qh.qh_elink),
   1182       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1183       1.124  augustss 	if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) {
   1184       1.124  augustss 		sqh->qh.qh_elink = htole32(UHCI_PTR_T);
   1185       1.223    bouyer 		usb_syncmem(&sqh->dma,
   1186       1.223    bouyer 		    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1187       1.223    bouyer 		    sizeof(sqh->qh.qh_elink),
   1188       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   1189       1.124  augustss 		delay(UHCI_QH_REMOVE_DELAY);
   1190       1.124  augustss 	}
   1191        1.92  augustss 	pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh);
   1192       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1193       1.223    bouyer 	    sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
   1194        1.42  augustss 	pqh->hlink       = sqh->hlink;
   1195        1.42  augustss 	pqh->qh.qh_hlink = sqh->qh.qh_hlink;
   1196       1.223    bouyer 	usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1197       1.223    bouyer 	    sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
   1198       1.124  augustss 	delay(UHCI_QH_REMOVE_DELAY);
   1199         1.1  augustss 	if (sc->sc_bulk_end == sqh)
   1200         1.1  augustss 		sc->sc_bulk_end = pqh;
   1201         1.1  augustss }
   1202         1.1  augustss 
   1203       1.141  augustss Static int uhci_intr1(uhci_softc_t *);
   1204       1.141  augustss 
   1205         1.1  augustss int
   1206       1.119  augustss uhci_intr(void *arg)
   1207         1.1  augustss {
   1208        1.44  augustss 	uhci_softc_t *sc = arg;
   1209       1.248       mrg 	int ret = 0;
   1210       1.248       mrg 
   1211       1.248       mrg 	mutex_spin_enter(&sc->sc_intr_lock);
   1212       1.146  augustss 
   1213       1.216  drochner 	if (sc->sc_dying || !device_has_power(sc->sc_dev))
   1214       1.248       mrg 		goto done;
   1215       1.141  augustss 
   1216   1.264.4.7     skrll 	if (sc->sc_bus.ub_usepolling || UREAD2(sc, UHCI_INTR) == 0) {
   1217       1.141  augustss #ifdef DIAGNOSTIC
   1218       1.179   mycroft 		DPRINTFN(16, ("uhci_intr: ignored interrupt while polling\n"));
   1219       1.141  augustss #endif
   1220       1.248       mrg 		goto done;
   1221       1.141  augustss 	}
   1222       1.179   mycroft 
   1223       1.248       mrg 	ret = uhci_intr1(sc);
   1224       1.248       mrg 
   1225       1.248       mrg  done:
   1226       1.248       mrg 	mutex_spin_exit(&sc->sc_intr_lock);
   1227       1.248       mrg 	return ret;
   1228       1.141  augustss }
   1229       1.141  augustss 
   1230       1.141  augustss int
   1231       1.141  augustss uhci_intr1(uhci_softc_t *sc)
   1232       1.141  augustss {
   1233        1.44  augustss 	int status;
   1234        1.44  augustss 	int ack;
   1235         1.1  augustss 
   1236        1.67  augustss #ifdef UHCI_DEBUG
   1237        1.44  augustss 	if (uhcidebug > 15) {
   1238       1.216  drochner 		DPRINTF(("%s: uhci_intr1\n", device_xname(sc->sc_dev)));
   1239         1.1  augustss 		uhci_dumpregs(sc);
   1240         1.1  augustss 	}
   1241         1.1  augustss #endif
   1242       1.117  augustss 
   1243       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_intr_lock));
   1244       1.248       mrg 
   1245       1.153  augustss 	status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS;
   1246       1.127     soren 	if (status == 0)	/* The interrupt was not for us. */
   1247  1.264.4.13     skrll 		return 0;
   1248       1.127     soren 
   1249       1.117  augustss 	if (sc->sc_suspend != PWR_RESUME) {
   1250       1.201  jmcneill #ifdef DIAGNOSTIC
   1251       1.117  augustss 		printf("%s: interrupt while not operating ignored\n",
   1252       1.216  drochner 		       device_xname(sc->sc_dev));
   1253       1.201  jmcneill #endif
   1254       1.134  augustss 		UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */
   1255  1.264.4.13     skrll 		return 0;
   1256       1.117  augustss 	}
   1257        1.44  augustss 
   1258        1.44  augustss 	ack = 0;
   1259        1.44  augustss 	if (status & UHCI_STS_USBINT)
   1260        1.44  augustss 		ack |= UHCI_STS_USBINT;
   1261        1.44  augustss 	if (status & UHCI_STS_USBEI)
   1262        1.44  augustss 		ack |= UHCI_STS_USBEI;
   1263         1.1  augustss 	if (status & UHCI_STS_RD) {
   1264        1.44  augustss 		ack |= UHCI_STS_RD;
   1265       1.118  augustss #ifdef UHCI_DEBUG
   1266       1.216  drochner 		printf("%s: resume detect\n", device_xname(sc->sc_dev));
   1267       1.118  augustss #endif
   1268         1.1  augustss 	}
   1269         1.1  augustss 	if (status & UHCI_STS_HSE) {
   1270        1.44  augustss 		ack |= UHCI_STS_HSE;
   1271       1.216  drochner 		printf("%s: host system error\n", device_xname(sc->sc_dev));
   1272         1.1  augustss 	}
   1273         1.1  augustss 	if (status & UHCI_STS_HCPE) {
   1274        1.44  augustss 		ack |= UHCI_STS_HCPE;
   1275       1.152  augustss 		printf("%s: host controller process error\n",
   1276       1.216  drochner 		       device_xname(sc->sc_dev));
   1277        1.44  augustss 	}
   1278       1.233   msaitoh 
   1279       1.233   msaitoh 	/* When HCHalted=1 and Run/Stop=0 , it is normal */
   1280       1.233   msaitoh 	if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) {
   1281        1.44  augustss 		/* no acknowledge needed */
   1282       1.136  augustss 		if (!sc->sc_dying) {
   1283       1.152  augustss 			printf("%s: host controller halted\n",
   1284       1.216  drochner 			    device_xname(sc->sc_dev));
   1285       1.110  augustss #ifdef UHCI_DEBUG
   1286       1.136  augustss 			uhci_dump_all(sc);
   1287       1.110  augustss #endif
   1288       1.136  augustss 		}
   1289       1.136  augustss 		sc->sc_dying = 1;
   1290         1.1  augustss 	}
   1291        1.44  augustss 
   1292       1.132  augustss 	if (!ack)
   1293  1.264.4.13     skrll 		return 0;	/* nothing to acknowledge */
   1294       1.132  augustss 	UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */
   1295         1.1  augustss 
   1296        1.85  augustss 	usb_schedsoftintr(&sc->sc_bus);
   1297        1.85  augustss 
   1298       1.216  drochner 	DPRINTFN(15, ("%s: uhci_intr: exit\n", device_xname(sc->sc_dev)));
   1299        1.85  augustss 
   1300  1.264.4.13     skrll 	return 1;
   1301        1.85  augustss }
   1302        1.85  augustss 
   1303        1.85  augustss void
   1304       1.133  augustss uhci_softintr(void *v)
   1305        1.85  augustss {
   1306       1.216  drochner 	struct usbd_bus *bus = v;
   1307   1.264.4.7     skrll 	uhci_softc_t *sc = bus->ub_hcpriv;
   1308       1.178    martin 	uhci_intr_info_t *ii, *nextii;
   1309        1.85  augustss 
   1310   1.264.4.7     skrll 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
   1311       1.248       mrg 
   1312       1.247       mrg 	DPRINTFN(10,("%s: uhci_softintr\n", device_xname(sc->sc_dev)));
   1313        1.50  augustss 
   1314         1.1  augustss 	/*
   1315         1.1  augustss 	 * Interrupts on UHCI really suck.  When the host controller
   1316         1.1  augustss 	 * interrupts because a transfer is completed there is no
   1317         1.1  augustss 	 * way of knowing which transfer it was.  You can scan down
   1318         1.1  augustss 	 * the TDs and QHs of the previous frame to limit the search,
   1319         1.1  augustss 	 * but that assumes that the interrupt was not delayed by more
   1320         1.1  augustss 	 * than 1 ms, which may not always be true (e.g. after debug
   1321         1.1  augustss 	 * output on a slow console).
   1322         1.1  augustss 	 * We scan all interrupt descriptors to see if any have
   1323         1.1  augustss 	 * completed.
   1324         1.1  augustss 	 */
   1325       1.178    martin 	for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = nextii) {
   1326       1.178    martin 		nextii = LIST_NEXT(ii, list);
   1327         1.1  augustss 		uhci_check_intr(sc, ii);
   1328       1.178    martin 	}
   1329         1.1  augustss 
   1330       1.153  augustss 	if (sc->sc_softwake) {
   1331       1.153  augustss 		sc->sc_softwake = 0;
   1332       1.248       mrg 		cv_broadcast(&sc->sc_softwake_cv);
   1333       1.153  augustss 	}
   1334         1.1  augustss }
   1335         1.1  augustss 
   1336         1.1  augustss /* Check for an interrupt. */
   1337         1.1  augustss void
   1338       1.205  christos uhci_check_intr(uhci_softc_t *sc, uhci_intr_info_t *ii)
   1339         1.1  augustss {
   1340         1.1  augustss 	uhci_soft_td_t *std, *lstd;
   1341   1.264.4.1     skrll 	uint32_t status;
   1342         1.1  augustss 
   1343         1.1  augustss 	DPRINTFN(15, ("uhci_check_intr: ii=%p\n", ii));
   1344         1.1  augustss #ifdef DIAGNOSTIC
   1345        1.63  augustss 	if (ii == NULL) {
   1346         1.1  augustss 		printf("uhci_check_intr: no ii? %p\n", ii);
   1347         1.1  augustss 		return;
   1348         1.1  augustss 	}
   1349         1.1  augustss #endif
   1350   1.264.4.7     skrll 	if (ii->xfer->ux_status == USBD_CANCELLED ||
   1351   1.264.4.7     skrll 	    ii->xfer->ux_status == USBD_TIMEOUT) {
   1352       1.155  augustss 		DPRINTF(("uhci_check_intr: aborted xfer=%p\n", ii->xfer));
   1353       1.155  augustss 		return;
   1354       1.155  augustss 	}
   1355       1.155  augustss 
   1356        1.63  augustss 	if (ii->stdstart == NULL)
   1357         1.1  augustss 		return;
   1358         1.1  augustss 	lstd = ii->stdend;
   1359         1.1  augustss #ifdef DIAGNOSTIC
   1360        1.63  augustss 	if (lstd == NULL) {
   1361         1.1  augustss 		printf("uhci_check_intr: std==0\n");
   1362         1.1  augustss 		return;
   1363         1.1  augustss 	}
   1364         1.1  augustss #endif
   1365       1.223    bouyer 	usb_syncmem(&lstd->dma,
   1366       1.223    bouyer 	    lstd->offs + offsetof(uhci_td_t, td_status),
   1367       1.223    bouyer 	    sizeof(lstd->td.td_status),
   1368       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1369       1.256   tsutsui 	status = le32toh(lstd->td.td_status);
   1370       1.256   tsutsui 	usb_syncmem(&lstd->dma,
   1371       1.256   tsutsui 	    lstd->offs + offsetof(uhci_td_t, td_status),
   1372       1.256   tsutsui 	    sizeof(lstd->td.td_status),
   1373       1.256   tsutsui 	    BUS_DMASYNC_PREREAD);
   1374       1.258     skrll 
   1375       1.258     skrll 	/* If the last TD is not marked active we can complete */
   1376       1.258     skrll 	if (!(status & UHCI_TD_ACTIVE)) {
   1377       1.258     skrll  done:
   1378       1.258     skrll 		DPRINTFN(12, ("uhci_check_intr: ii=%p done\n", ii));
   1379   1.264.4.7     skrll 		callout_stop(&ii->xfer->ux_callout);
   1380       1.258     skrll 		uhci_idone(ii);
   1381       1.258     skrll 		return;
   1382       1.258     skrll 	}
   1383       1.258     skrll 
   1384       1.258     skrll 	/*
   1385       1.258     skrll 	 * If the last TD is still active we need to check whether there
   1386       1.258     skrll 	 * is an error somewhere in the middle, or whether there was a
   1387       1.258     skrll 	 * short packet (SPD and not ACTIVE).
   1388       1.258     skrll 	 */
   1389       1.258     skrll 	DPRINTFN(12, ("uhci_check_intr: active ii=%p\n", ii));
   1390       1.258     skrll 	for (std = ii->stdstart; std != lstd; std = std->link.std) {
   1391       1.258     skrll 		usb_syncmem(&std->dma,
   1392       1.258     skrll 		    std->offs + offsetof(uhci_td_t, td_status),
   1393       1.258     skrll 		    sizeof(std->td.td_status),
   1394       1.258     skrll 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1395       1.258     skrll 		status = le32toh(std->td.td_status);
   1396       1.258     skrll 		usb_syncmem(&std->dma,
   1397       1.258     skrll 		    std->offs + offsetof(uhci_td_t, td_status),
   1398       1.258     skrll 		    sizeof(std->td.td_status), BUS_DMASYNC_PREREAD);
   1399       1.258     skrll 
   1400       1.258     skrll 		/* If there's an active TD the xfer isn't done. */
   1401       1.258     skrll 		if (status & UHCI_TD_ACTIVE) {
   1402       1.258     skrll 			DPRINTFN(12, ("%s: ii=%p std=%p still active\n",
   1403       1.258     skrll 			    __func__, ii, std));
   1404       1.258     skrll 			return;
   1405       1.258     skrll 		}
   1406       1.258     skrll 
   1407       1.258     skrll 		/* Any kind of error makes the xfer done. */
   1408       1.258     skrll 		if (status & UHCI_TD_STALLED)
   1409       1.258     skrll 			goto done;
   1410       1.258     skrll 
   1411       1.258     skrll 		/*
   1412       1.258     skrll 		 * If the data phase of a control transfer is short, we need
   1413       1.258     skrll 		 * to complete the status stage
   1414       1.258     skrll 		 */
   1415       1.258     skrll 		usbd_xfer_handle xfer = ii->xfer;
   1416   1.264.4.7     skrll 		usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc;
   1417       1.258     skrll 		uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
   1418       1.258     skrll 
   1419       1.258     skrll 		if ((status & UHCI_TD_SPD) && xfertype == UE_CONTROL) {
   1420       1.258     skrll 			struct uhci_pipe *upipe =
   1421   1.264.4.7     skrll 			    (struct uhci_pipe *)xfer->ux_pipe;
   1422       1.258     skrll 			uhci_soft_qh_t *sqh = upipe->u.ctl.sqh;
   1423       1.258     skrll 			uhci_soft_td_t *stat = upipe->u.ctl.stat;
   1424       1.258     skrll 
   1425       1.258     skrll 			DPRINTFN(12, ("%s: ii=%p std=%p control status"
   1426       1.258     skrll 			    "phase needs completion\n", __func__, ii,
   1427       1.258     skrll 			    ii->stdstart));
   1428       1.258     skrll 
   1429       1.258     skrll 			sqh->qh.qh_elink =
   1430       1.258     skrll 			    htole32(stat->physaddr | UHCI_PTR_TD);
   1431       1.258     skrll 			usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
   1432       1.258     skrll 			    BUS_DMASYNC_PREWRITE);
   1433       1.258     skrll 			break;
   1434       1.258     skrll 		}
   1435       1.258     skrll 
   1436       1.258     skrll 		/* We want short packets, and it is short: it's done */
   1437       1.258     skrll 		usb_syncmem(&std->dma,
   1438       1.258     skrll 		    std->offs + offsetof(uhci_td_t, td_token),
   1439       1.258     skrll 		    sizeof(std->td.td_token),
   1440       1.258     skrll 		    BUS_DMASYNC_POSTWRITE);
   1441       1.258     skrll 
   1442       1.258     skrll 		if ((status & UHCI_TD_SPD) &&
   1443       1.258     skrll 			UHCI_TD_GET_ACTLEN(status) <
   1444       1.258     skrll 			UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) {
   1445       1.258     skrll 			goto done;
   1446        1.18  augustss 		}
   1447         1.1  augustss 	}
   1448         1.1  augustss }
   1449         1.1  augustss 
   1450       1.248       mrg /* Called with USB lock held. */
   1451         1.1  augustss void
   1452       1.119  augustss uhci_idone(uhci_intr_info_t *ii)
   1453         1.1  augustss {
   1454        1.63  augustss 	usbd_xfer_handle xfer = ii->xfer;
   1455   1.264.4.7     skrll 	struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
   1456       1.248       mrg #ifdef DIAGNOSTIC
   1457   1.264.4.7     skrll 	uhci_softc_t *sc = upipe->pipe.up_dev->ud_bus->ub_hcpriv;
   1458       1.248       mrg #endif
   1459         1.1  augustss 	uhci_soft_td_t *std;
   1460   1.264.4.1     skrll 	uint32_t status = 0, nstatus;
   1461        1.26  augustss 	int actlen;
   1462         1.1  augustss 
   1463   1.264.4.7     skrll 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
   1464       1.248       mrg 
   1465       1.140  augustss 	DPRINTFN(12, ("uhci_idone: ii=%p\n", ii));
   1466         1.7  augustss #ifdef DIAGNOSTIC
   1467         1.7  augustss 	{
   1468       1.248       mrg 		/* XXX SMP? */
   1469         1.7  augustss 		int s = splhigh();
   1470         1.7  augustss 		if (ii->isdone) {
   1471        1.26  augustss 			splx(s);
   1472        1.92  augustss #ifdef UHCI_DEBUG
   1473        1.92  augustss 			printf("uhci_idone: ii is done!\n   ");
   1474        1.92  augustss 			uhci_dump_ii(ii);
   1475        1.92  augustss #else
   1476        1.36  augustss 			printf("uhci_idone: ii=%p is done!\n", ii);
   1477        1.92  augustss #endif
   1478         1.7  augustss 			return;
   1479         1.7  augustss 		}
   1480         1.7  augustss 		ii->isdone = 1;
   1481         1.7  augustss 		splx(s);
   1482         1.7  augustss 	}
   1483         1.7  augustss #endif
   1484        1.48  augustss 
   1485   1.264.4.7     skrll 	if (xfer->ux_nframes != 0) {
   1486        1.48  augustss 		/* Isoc transfer, do things differently. */
   1487        1.48  augustss 		uhci_soft_td_t **stds = upipe->u.iso.stds;
   1488       1.126  augustss 		int i, n, nframes, len;
   1489        1.48  augustss 
   1490        1.48  augustss 		DPRINTFN(5,("uhci_idone: ii=%p isoc ready\n", ii));
   1491        1.48  augustss 
   1492   1.264.4.7     skrll 		nframes = xfer->ux_nframes;
   1493        1.48  augustss 		actlen = 0;
   1494        1.92  augustss 		n = UXFER(xfer)->curframe;
   1495        1.48  augustss 		for (i = 0; i < nframes; i++) {
   1496        1.48  augustss 			std = stds[n];
   1497        1.59  augustss #ifdef UHCI_DEBUG
   1498        1.48  augustss 			if (uhcidebug > 5) {
   1499        1.48  augustss 				DPRINTFN(-1,("uhci_idone: isoc TD %d\n", i));
   1500        1.48  augustss 				uhci_dump_td(std);
   1501        1.48  augustss 			}
   1502        1.48  augustss #endif
   1503        1.48  augustss 			if (++n >= UHCI_VFRAMELIST_COUNT)
   1504        1.48  augustss 				n = 0;
   1505       1.223    bouyer 			usb_syncmem(&std->dma,
   1506       1.223    bouyer 			    std->offs + offsetof(uhci_td_t, td_status),
   1507       1.223    bouyer 			    sizeof(std->td.td_status),
   1508       1.223    bouyer 			    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1509        1.88   tsutsui 			status = le32toh(std->td.td_status);
   1510       1.126  augustss 			len = UHCI_TD_GET_ACTLEN(status);
   1511   1.264.4.7     skrll 			xfer->ux_frlengths[i] = len;
   1512       1.126  augustss 			actlen += len;
   1513        1.48  augustss 		}
   1514        1.48  augustss 		upipe->u.iso.inuse -= nframes;
   1515   1.264.4.7     skrll 		xfer->ux_actlen = actlen;
   1516   1.264.4.7     skrll 		xfer->ux_status = USBD_NORMAL_COMPLETION;
   1517       1.140  augustss 		goto end;
   1518        1.48  augustss 	}
   1519        1.48  augustss 
   1520        1.59  augustss #ifdef UHCI_DEBUG
   1521        1.65  augustss 	DPRINTFN(10, ("uhci_idone: ii=%p, xfer=%p, pipe=%p ready\n",
   1522        1.65  augustss 		      ii, xfer, upipe));
   1523        1.48  augustss 	if (uhcidebug > 10)
   1524        1.48  augustss 		uhci_dump_tds(ii->stdstart);
   1525        1.48  augustss #endif
   1526        1.48  augustss 
   1527        1.26  augustss 	/* The transfer is done, compute actual length and status. */
   1528        1.26  augustss 	actlen = 0;
   1529        1.63  augustss 	for (std = ii->stdstart; std != NULL; std = std->link.std) {
   1530       1.223    bouyer 		usb_syncmem(&std->dma, std->offs, sizeof(std->td),
   1531       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1532        1.88   tsutsui 		nstatus = le32toh(std->td.td_status);
   1533        1.64  augustss 		if (nstatus & UHCI_TD_ACTIVE)
   1534        1.26  augustss 			break;
   1535        1.67  augustss 
   1536        1.64  augustss 		status = nstatus;
   1537        1.88   tsutsui 		if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) !=
   1538        1.88   tsutsui 			UHCI_TD_PID_SETUP)
   1539        1.26  augustss 			actlen += UHCI_TD_GET_ACTLEN(status);
   1540       1.176   mycroft 		else {
   1541       1.176   mycroft 			/*
   1542       1.176   mycroft 			 * UHCI will report CRCTO in addition to a STALL or NAK
   1543       1.176   mycroft 			 * for a SETUP transaction.  See section 3.2.2, "TD
   1544       1.176   mycroft 			 * CONTROL AND STATUS".
   1545       1.176   mycroft 			 */
   1546       1.176   mycroft 			if (status & (UHCI_TD_STALLED | UHCI_TD_NAK))
   1547       1.176   mycroft 				status &= ~UHCI_TD_CRCTO;
   1548       1.176   mycroft 		}
   1549         1.1  augustss 	}
   1550        1.38  augustss 	/* If there are left over TDs we need to update the toggle. */
   1551        1.63  augustss 	if (std != NULL)
   1552        1.88   tsutsui 		upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token));
   1553        1.38  augustss 
   1554         1.1  augustss 	status &= UHCI_TD_ERROR;
   1555       1.152  augustss 	DPRINTFN(10, ("uhci_idone: actlen=%d, status=0x%x\n",
   1556        1.26  augustss 		      actlen, status));
   1557   1.264.4.7     skrll 	xfer->ux_actlen = actlen;
   1558         1.1  augustss 	if (status != 0) {
   1559       1.122        tv #ifdef UHCI_DEBUG
   1560       1.122        tv 		char sbuf[128];
   1561       1.122        tv 
   1562       1.224  christos 		snprintb(sbuf, sizeof(sbuf),
   1563       1.224  christos 		    "\20\22BITSTUFF\23CRCTO\24NAK\25"
   1564   1.264.4.1     skrll 		    "BABBLE\26DBUFFER\27STALLED\30ACTIVE",(uint32_t)status);
   1565       1.122        tv 
   1566        1.75  augustss 		DPRINTFN((status == UHCI_TD_STALLED)*10,
   1567        1.36  augustss 			 ("uhci_idone: error, addr=%d, endpt=0x%02x, "
   1568       1.122        tv 			  "status 0x%s\n",
   1569   1.264.4.7     skrll 			  xfer->ux_pipe->up_dev->ud_addr,
   1570   1.264.4.7     skrll 			  xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress,
   1571       1.122        tv 			  sbuf));
   1572       1.122        tv #endif
   1573       1.122        tv 
   1574         1.1  augustss 		if (status == UHCI_TD_STALLED)
   1575   1.264.4.7     skrll 			xfer->ux_status = USBD_STALLED;
   1576         1.1  augustss 		else
   1577   1.264.4.7     skrll 			xfer->ux_status = USBD_IOERROR; /* more info XXX */
   1578         1.1  augustss 	} else {
   1579   1.264.4.7     skrll 		xfer->ux_status = USBD_NORMAL_COMPLETION;
   1580         1.1  augustss 	}
   1581       1.140  augustss 
   1582       1.140  augustss  end:
   1583        1.63  augustss 	usb_transfer_complete(xfer);
   1584   1.264.4.7     skrll 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
   1585       1.140  augustss 	DPRINTFN(12, ("uhci_idone: ii=%p done\n", ii));
   1586         1.1  augustss }
   1587         1.1  augustss 
   1588        1.13  augustss /*
   1589        1.13  augustss  * Called when a request does not complete.
   1590        1.13  augustss  */
   1591         1.1  augustss void
   1592       1.119  augustss uhci_timeout(void *addr)
   1593         1.1  augustss {
   1594         1.1  augustss 	uhci_intr_info_t *ii = addr;
   1595       1.153  augustss 	struct uhci_xfer *uxfer = UXFER(ii->xfer);
   1596   1.264.4.7     skrll 	struct uhci_pipe *upipe = (struct uhci_pipe *)uxfer->xfer.ux_pipe;
   1597   1.264.4.7     skrll 	uhci_softc_t *sc = upipe->pipe.up_dev->ud_bus->ub_hcpriv;
   1598       1.153  augustss 
   1599       1.153  augustss 	DPRINTF(("uhci_timeout: uxfer=%p\n", uxfer));
   1600       1.153  augustss 
   1601       1.153  augustss 	if (sc->sc_dying) {
   1602       1.248       mrg 		mutex_enter(&sc->sc_lock);
   1603       1.153  augustss 		uhci_abort_xfer(&uxfer->xfer, USBD_TIMEOUT);
   1604       1.248       mrg 		mutex_exit(&sc->sc_lock);
   1605       1.153  augustss 		return;
   1606       1.153  augustss 	}
   1607         1.1  augustss 
   1608       1.153  augustss 	/* Execute the abort in a process context. */
   1609       1.252  jmcneill 	usb_init_task(&uxfer->abort_task, uhci_timeout_task, ii->xfer,
   1610       1.252  jmcneill 	    USB_TASKQ_MPSAFE);
   1611   1.264.4.7     skrll 	usb_add_task(uxfer->xfer.ux_pipe->up_dev, &uxfer->abort_task,
   1612       1.204     joerg 	    USB_TASKQ_HC);
   1613       1.153  augustss }
   1614        1.51  augustss 
   1615       1.153  augustss void
   1616       1.153  augustss uhci_timeout_task(void *addr)
   1617       1.153  augustss {
   1618       1.153  augustss 	usbd_xfer_handle xfer = addr;
   1619   1.264.4.7     skrll 	uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
   1620       1.153  augustss 
   1621       1.153  augustss 	DPRINTF(("uhci_timeout_task: xfer=%p\n", xfer));
   1622        1.67  augustss 
   1623       1.248       mrg 	mutex_enter(&sc->sc_lock);
   1624       1.153  augustss 	uhci_abort_xfer(xfer, USBD_TIMEOUT);
   1625       1.248       mrg 	mutex_exit(&sc->sc_lock);
   1626         1.1  augustss }
   1627         1.1  augustss 
   1628         1.1  augustss /*
   1629         1.1  augustss  * Wait here until controller claims to have an interrupt.
   1630         1.1  augustss  * Then call uhci_intr and return.  Use timeout to avoid waiting
   1631         1.1  augustss  * too long.
   1632        1.13  augustss  * Only used during boot when interrupts are not enabled yet.
   1633         1.1  augustss  */
   1634         1.1  augustss void
   1635       1.119  augustss uhci_waitintr(uhci_softc_t *sc, usbd_xfer_handle xfer)
   1636         1.1  augustss {
   1637   1.264.4.7     skrll 	int timo = xfer->ux_timeout;
   1638        1.13  augustss 	uhci_intr_info_t *ii;
   1639        1.13  augustss 
   1640       1.248       mrg 	mutex_enter(&sc->sc_lock);
   1641       1.248       mrg 
   1642        1.26  augustss 	DPRINTFN(10,("uhci_waitintr: timeout = %dms\n", timo));
   1643         1.1  augustss 
   1644   1.264.4.7     skrll 	xfer->ux_status = USBD_IN_PROGRESS;
   1645        1.26  augustss 	for (; timo >= 0; timo--) {
   1646       1.248       mrg 		usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_lock);
   1647        1.26  augustss 		DPRINTFN(20,("uhci_waitintr: 0x%04x\n", UREAD2(sc, UHCI_STS)));
   1648         1.1  augustss 		if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) {
   1649       1.248       mrg 			mutex_spin_enter(&sc->sc_intr_lock);
   1650       1.141  augustss 			uhci_intr1(sc);
   1651       1.248       mrg 			mutex_spin_exit(&sc->sc_intr_lock);
   1652   1.264.4.7     skrll 			if (xfer->ux_status != USBD_IN_PROGRESS)
   1653       1.248       mrg 				goto done;
   1654         1.1  augustss 		}
   1655         1.1  augustss 	}
   1656        1.13  augustss 
   1657        1.13  augustss 	/* Timeout */
   1658        1.13  augustss 	DPRINTF(("uhci_waitintr: timeout\n"));
   1659        1.13  augustss 	for (ii = LIST_FIRST(&sc->sc_intrhead);
   1660       1.152  augustss 	     ii != NULL && ii->xfer != xfer;
   1661        1.13  augustss 	     ii = LIST_NEXT(ii, list))
   1662        1.13  augustss 		;
   1663        1.41  augustss #ifdef DIAGNOSTIC
   1664        1.63  augustss 	if (ii == NULL)
   1665       1.163    provos 		panic("uhci_waitintr: lost intr_info");
   1666        1.41  augustss #endif
   1667        1.41  augustss 	uhci_idone(ii);
   1668       1.248       mrg 
   1669       1.248       mrg done:
   1670       1.248       mrg 	mutex_exit(&sc->sc_lock);
   1671         1.1  augustss }
   1672         1.1  augustss 
   1673         1.8  augustss void
   1674       1.119  augustss uhci_poll(struct usbd_bus *bus)
   1675         1.8  augustss {
   1676   1.264.4.7     skrll 	uhci_softc_t *sc = bus->ub_hcpriv;
   1677         1.8  augustss 
   1678       1.248       mrg 	if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) {
   1679       1.248       mrg 		mutex_spin_enter(&sc->sc_intr_lock);
   1680       1.141  augustss 		uhci_intr1(sc);
   1681       1.248       mrg 		mutex_spin_exit(&sc->sc_intr_lock);
   1682       1.248       mrg 	}
   1683         1.8  augustss }
   1684         1.8  augustss 
   1685         1.1  augustss void
   1686       1.119  augustss uhci_reset(uhci_softc_t *sc)
   1687         1.1  augustss {
   1688         1.1  augustss 	int n;
   1689         1.1  augustss 
   1690         1.1  augustss 	UHCICMD(sc, UHCI_CMD_HCRESET);
   1691         1.1  augustss 	/* The reset bit goes low when the controller is done. */
   1692       1.152  augustss 	for (n = 0; n < UHCI_RESET_TIMEOUT &&
   1693         1.1  augustss 		    (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++)
   1694        1.92  augustss 		usb_delay_ms(&sc->sc_bus, 1);
   1695         1.1  augustss 	if (n >= UHCI_RESET_TIMEOUT)
   1696       1.152  augustss 		printf("%s: controller did not reset\n",
   1697       1.216  drochner 		       device_xname(sc->sc_dev));
   1698         1.1  augustss }
   1699         1.1  augustss 
   1700        1.16  augustss usbd_status
   1701       1.249  drochner uhci_run(uhci_softc_t *sc, int run, int locked)
   1702         1.1  augustss {
   1703       1.248       mrg 	int n, running;
   1704   1.264.4.1     skrll 	uint16_t cmd;
   1705         1.1  augustss 
   1706         1.1  augustss 	run = run != 0;
   1707       1.249  drochner 	if (!locked)
   1708       1.249  drochner 		mutex_spin_enter(&sc->sc_intr_lock);
   1709        1.30  augustss 	DPRINTF(("uhci_run: setting run=%d\n", run));
   1710        1.71  augustss 	cmd = UREAD2(sc, UHCI_CMD);
   1711        1.71  augustss 	if (run)
   1712        1.71  augustss 		cmd |= UHCI_CMD_RS;
   1713        1.71  augustss 	else
   1714        1.71  augustss 		cmd &= ~UHCI_CMD_RS;
   1715        1.71  augustss 	UHCICMD(sc, cmd);
   1716        1.13  augustss 	for(n = 0; n < 10; n++) {
   1717         1.1  augustss 		running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH);
   1718         1.1  augustss 		/* return when we've entered the state we want */
   1719         1.1  augustss 		if (run == running) {
   1720       1.249  drochner 			if (!locked)
   1721       1.249  drochner 				mutex_spin_exit(&sc->sc_intr_lock);
   1722        1.30  augustss 			DPRINTF(("uhci_run: done cmd=0x%x sts=0x%x\n",
   1723        1.30  augustss 				 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS)));
   1724  1.264.4.13     skrll 			return USBD_NORMAL_COMPLETION;
   1725         1.1  augustss 		}
   1726       1.248       mrg 		usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock);
   1727         1.1  augustss 	}
   1728       1.249  drochner 	if (!locked)
   1729       1.249  drochner 		mutex_spin_exit(&sc->sc_intr_lock);
   1730       1.216  drochner 	printf("%s: cannot %s\n", device_xname(sc->sc_dev),
   1731        1.14  augustss 	       run ? "start" : "stop");
   1732  1.264.4.13     skrll 	return USBD_IOERROR;
   1733         1.1  augustss }
   1734         1.1  augustss 
   1735         1.1  augustss /*
   1736         1.1  augustss  * Memory management routines.
   1737         1.1  augustss  *  uhci_alloc_std allocates TDs
   1738         1.1  augustss  *  uhci_alloc_sqh allocates QHs
   1739         1.7  augustss  * These two routines do their own free list management,
   1740         1.1  augustss  * partly for speed, partly because allocating DMAable memory
   1741         1.1  augustss  * has page size granularaity so much memory would be wasted if
   1742        1.16  augustss  * only one TD/QH (32 bytes) was placed in each allocated chunk.
   1743         1.1  augustss  */
   1744         1.1  augustss 
   1745         1.1  augustss uhci_soft_td_t *
   1746       1.119  augustss uhci_alloc_std(uhci_softc_t *sc)
   1747         1.1  augustss {
   1748         1.1  augustss 	uhci_soft_td_t *std;
   1749        1.63  augustss 	usbd_status err;
   1750        1.42  augustss 	int i, offs;
   1751         1.7  augustss 	usb_dma_t dma;
   1752         1.1  augustss 
   1753        1.63  augustss 	if (sc->sc_freetds == NULL) {
   1754         1.1  augustss 		DPRINTFN(2,("uhci_alloc_std: allocating chunk\n"));
   1755        1.63  augustss 		err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK,
   1756        1.63  augustss 			  UHCI_TD_ALIGN, &dma);
   1757        1.63  augustss 		if (err)
   1758  1.264.4.13     skrll 			return 0;
   1759       1.248       mrg 		for (i = 0; i < UHCI_STD_CHUNK; i++) {
   1760        1.42  augustss 			offs = i * UHCI_STD_SIZE;
   1761       1.159  augustss 			std = KERNADDR(&dma, offs);
   1762       1.160  augustss 			std->physaddr = DMAADDR(&dma, offs);
   1763       1.223    bouyer 			std->dma = dma;
   1764       1.223    bouyer 			std->offs = offs;
   1765        1.42  augustss 			std->link.std = sc->sc_freetds;
   1766         1.1  augustss 			sc->sc_freetds = std;
   1767         1.1  augustss 		}
   1768         1.1  augustss 	}
   1769         1.1  augustss 	std = sc->sc_freetds;
   1770        1.42  augustss 	sc->sc_freetds = std->link.std;
   1771        1.42  augustss 	memset(&std->td, 0, sizeof(uhci_td_t));
   1772         1.1  augustss 	return std;
   1773         1.1  augustss }
   1774         1.1  augustss 
   1775         1.1  augustss void
   1776       1.119  augustss uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std)
   1777         1.1  augustss {
   1778         1.7  augustss #ifdef DIAGNOSTIC
   1779         1.7  augustss #define TD_IS_FREE 0x12345678
   1780        1.88   tsutsui 	if (le32toh(std->td.td_token) == TD_IS_FREE) {
   1781         1.7  augustss 		printf("uhci_free_std: freeing free TD %p\n", std);
   1782         1.7  augustss 		return;
   1783         1.7  augustss 	}
   1784        1.88   tsutsui 	std->td.td_token = htole32(TD_IS_FREE);
   1785         1.7  augustss #endif
   1786        1.42  augustss 	std->link.std = sc->sc_freetds;
   1787         1.1  augustss 	sc->sc_freetds = std;
   1788         1.1  augustss }
   1789         1.1  augustss 
   1790         1.1  augustss uhci_soft_qh_t *
   1791       1.119  augustss uhci_alloc_sqh(uhci_softc_t *sc)
   1792         1.1  augustss {
   1793         1.1  augustss 	uhci_soft_qh_t *sqh;
   1794        1.63  augustss 	usbd_status err;
   1795         1.1  augustss 	int i, offs;
   1796         1.7  augustss 	usb_dma_t dma;
   1797         1.1  augustss 
   1798        1.63  augustss 	if (sc->sc_freeqhs == NULL) {
   1799         1.1  augustss 		DPRINTFN(2, ("uhci_alloc_sqh: allocating chunk\n"));
   1800        1.63  augustss 		err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK,
   1801        1.63  augustss 			  UHCI_QH_ALIGN, &dma);
   1802        1.63  augustss 		if (err)
   1803  1.264.4.13     skrll 			return 0;
   1804        1.43  augustss 		for(i = 0; i < UHCI_SQH_CHUNK; i++) {
   1805        1.42  augustss 			offs = i * UHCI_SQH_SIZE;
   1806       1.159  augustss 			sqh = KERNADDR(&dma, offs);
   1807       1.160  augustss 			sqh->physaddr = DMAADDR(&dma, offs);
   1808       1.223    bouyer 			sqh->dma = dma;
   1809       1.223    bouyer 			sqh->offs = offs;
   1810        1.42  augustss 			sqh->hlink = sc->sc_freeqhs;
   1811         1.1  augustss 			sc->sc_freeqhs = sqh;
   1812         1.1  augustss 		}
   1813         1.1  augustss 	}
   1814         1.1  augustss 	sqh = sc->sc_freeqhs;
   1815        1.42  augustss 	sc->sc_freeqhs = sqh->hlink;
   1816        1.42  augustss 	memset(&sqh->qh, 0, sizeof(uhci_qh_t));
   1817  1.264.4.13     skrll 	return sqh;
   1818         1.1  augustss }
   1819         1.1  augustss 
   1820         1.1  augustss void
   1821       1.119  augustss uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   1822         1.1  augustss {
   1823        1.42  augustss 	sqh->hlink = sc->sc_freeqhs;
   1824         1.1  augustss 	sc->sc_freeqhs = sqh;
   1825         1.1  augustss }
   1826         1.1  augustss 
   1827         1.1  augustss void
   1828       1.119  augustss uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std,
   1829       1.119  augustss 		    uhci_soft_td_t *stdend)
   1830         1.1  augustss {
   1831         1.1  augustss 	uhci_soft_td_t *p;
   1832       1.256   tsutsui 	uint32_t td_link;
   1833         1.1  augustss 
   1834       1.223    bouyer 	/*
   1835       1.223    bouyer 	 * to avoid race condition with the controller which may be looking
   1836       1.223    bouyer 	 * at this chain, we need to first invalidate all links, and
   1837       1.223    bouyer 	 * then wait for the controller to move to another queue
   1838       1.223    bouyer 	 */
   1839       1.223    bouyer 	for (p = std; p != stdend; p = p->link.std) {
   1840       1.223    bouyer 		usb_syncmem(&p->dma,
   1841       1.223    bouyer 		    p->offs + offsetof(uhci_td_t, td_link),
   1842       1.223    bouyer 		    sizeof(p->td.td_link),
   1843       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1844       1.256   tsutsui 		td_link = le32toh(p->td.td_link);
   1845       1.256   tsutsui 		usb_syncmem(&p->dma,
   1846       1.256   tsutsui 		    p->offs + offsetof(uhci_td_t, td_link),
   1847       1.256   tsutsui 		    sizeof(p->td.td_link),
   1848       1.256   tsutsui 		    BUS_DMASYNC_PREREAD);
   1849       1.256   tsutsui 		if ((td_link & UHCI_PTR_T) == 0) {
   1850       1.255   tsutsui 			p->td.td_link = htole32(UHCI_PTR_T);
   1851       1.223    bouyer 			usb_syncmem(&p->dma,
   1852       1.223    bouyer 			    p->offs + offsetof(uhci_td_t, td_link),
   1853       1.223    bouyer 			    sizeof(p->td.td_link),
   1854       1.223    bouyer 			    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   1855       1.223    bouyer 		}
   1856       1.223    bouyer 	}
   1857       1.223    bouyer 	delay(UHCI_QH_REMOVE_DELAY);
   1858       1.223    bouyer 
   1859         1.1  augustss 	for (; std != stdend; std = p) {
   1860        1.42  augustss 		p = std->link.std;
   1861         1.1  augustss 		uhci_free_std(sc, std);
   1862         1.1  augustss 	}
   1863         1.1  augustss }
   1864         1.1  augustss 
   1865         1.1  augustss usbd_status
   1866       1.119  augustss uhci_alloc_std_chain(struct uhci_pipe *upipe, uhci_softc_t *sc, int len,
   1867   1.264.4.1     skrll 		     int rd, uint16_t flags, usb_dma_t *dma,
   1868       1.119  augustss 		     uhci_soft_td_t **sp, uhci_soft_td_t **ep)
   1869         1.1  augustss {
   1870         1.1  augustss 	uhci_soft_td_t *p, *lastp;
   1871         1.1  augustss 	uhci_physaddr_t lastlink;
   1872         1.1  augustss 	int i, ntd, l, tog, maxp;
   1873   1.264.4.1     skrll 	uint32_t status;
   1874   1.264.4.7     skrll 	int addr = upipe->pipe.up_dev->ud_addr;
   1875   1.264.4.7     skrll 	int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
   1876         1.1  augustss 
   1877       1.144  augustss 	DPRINTFN(8, ("uhci_alloc_std_chain: addr=%d endpt=%d len=%d speed=%d "
   1878       1.152  augustss 		      "flags=0x%x\n", addr, UE_GET_ADDR(endpt), len,
   1879   1.264.4.7     skrll 		      upipe->pipe.up_dev->ud_speed, flags));
   1880       1.248       mrg 
   1881   1.264.4.7     skrll 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
   1882       1.248       mrg 
   1883   1.264.4.7     skrll 	maxp = UGETW(upipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize);
   1884         1.1  augustss 	if (maxp == 0) {
   1885         1.1  augustss 		printf("uhci_alloc_std_chain: maxp=0\n");
   1886  1.264.4.13     skrll 		return USBD_INVAL;
   1887         1.1  augustss 	}
   1888         1.1  augustss 	ntd = (len + maxp - 1) / maxp;
   1889        1.73  augustss 	if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0)
   1890        1.73  augustss 		ntd++;
   1891        1.39  augustss 	DPRINTFN(10, ("uhci_alloc_std_chain: maxp=%d ntd=%d\n", maxp, ntd));
   1892        1.73  augustss 	if (ntd == 0) {
   1893        1.73  augustss 		*sp = *ep = 0;
   1894        1.73  augustss 		DPRINTFN(-1,("uhci_alloc_std_chain: ntd=0\n"));
   1895  1.264.4.13     skrll 		return USBD_NORMAL_COMPLETION;
   1896        1.73  augustss 	}
   1897        1.38  augustss 	tog = upipe->nexttoggle;
   1898         1.1  augustss 	if (ntd % 2 == 0)
   1899         1.1  augustss 		tog ^= 1;
   1900        1.32  augustss 	upipe->nexttoggle = tog ^ 1;
   1901       1.121  augustss 	lastp = NULL;
   1902         1.1  augustss 	lastlink = UHCI_PTR_T;
   1903         1.1  augustss 	ntd--;
   1904        1.33  augustss 	status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE);
   1905   1.264.4.7     skrll 	if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW)
   1906        1.18  augustss 		status |= UHCI_TD_LS;
   1907        1.73  augustss 	if (flags & USBD_SHORT_XFER_OK)
   1908        1.18  augustss 		status |= UHCI_TD_SPD;
   1909       1.223    bouyer 	usb_syncmem(dma, 0, len,
   1910       1.223    bouyer 	    rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
   1911         1.1  augustss 	for (i = ntd; i >= 0; i--) {
   1912         1.1  augustss 		p = uhci_alloc_std(sc);
   1913        1.63  augustss 		if (p == NULL) {
   1914       1.202  christos 			KASSERT(lastp != NULL);
   1915       1.149  augustss 			uhci_free_std_chain(sc, lastp, NULL);
   1916  1.264.4.13     skrll 			return USBD_NOMEM;
   1917         1.1  augustss 		}
   1918        1.42  augustss 		p->link.std = lastp;
   1919       1.121  augustss 		p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD);
   1920         1.1  augustss 		lastp = p;
   1921         1.1  augustss 		lastlink = p->physaddr;
   1922        1.88   tsutsui 		p->td.td_status = htole32(status);
   1923         1.1  augustss 		if (i == ntd) {
   1924         1.1  augustss 			/* last TD */
   1925         1.1  augustss 			l = len % maxp;
   1926        1.73  augustss 			if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER))
   1927        1.73  augustss 				l = maxp;
   1928         1.1  augustss 			*ep = p;
   1929         1.1  augustss 		} else
   1930         1.1  augustss 			l = maxp;
   1931       1.152  augustss 		p->td.td_token =
   1932        1.88   tsutsui 		    htole32(rd ? UHCI_TD_IN (l, endpt, addr, tog) :
   1933        1.88   tsutsui 				 UHCI_TD_OUT(l, endpt, addr, tog));
   1934       1.160  augustss 		p->td.td_buffer = htole32(DMAADDR(dma, i * maxp));
   1935       1.223    bouyer 		usb_syncmem(&p->dma, p->offs, sizeof(p->td),
   1936       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   1937         1.1  augustss 		tog ^= 1;
   1938         1.1  augustss 	}
   1939         1.1  augustss 	*sp = lastp;
   1940       1.152  augustss 	DPRINTFN(10, ("uhci_alloc_std_chain: nexttog=%d\n",
   1941        1.38  augustss 		      upipe->nexttoggle));
   1942  1.264.4.13     skrll 	return USBD_NORMAL_COMPLETION;
   1943         1.1  augustss }
   1944         1.1  augustss 
   1945        1.38  augustss void
   1946       1.119  augustss uhci_device_clear_toggle(usbd_pipe_handle pipe)
   1947        1.38  augustss {
   1948        1.38  augustss 	struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;
   1949        1.38  augustss 	upipe->nexttoggle = 0;
   1950        1.38  augustss }
   1951        1.38  augustss 
   1952        1.38  augustss void
   1953       1.205  christos uhci_noop(usbd_pipe_handle pipe)
   1954        1.38  augustss {
   1955        1.38  augustss }
   1956        1.38  augustss 
   1957         1.1  augustss usbd_status
   1958       1.119  augustss uhci_device_bulk_transfer(usbd_xfer_handle xfer)
   1959         1.1  augustss {
   1960   1.264.4.7     skrll 	uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
   1961        1.63  augustss 	usbd_status err;
   1962        1.16  augustss 
   1963        1.52  augustss 	/* Insert last in queue. */
   1964       1.248       mrg 	mutex_enter(&sc->sc_lock);
   1965        1.63  augustss 	err = usb_insert_transfer(xfer);
   1966       1.248       mrg 	mutex_exit(&sc->sc_lock);
   1967        1.63  augustss 	if (err)
   1968  1.264.4.13     skrll 		return err;
   1969        1.52  augustss 
   1970       1.152  augustss 	/*
   1971        1.92  augustss 	 * Pipe isn't running (otherwise err would be USBD_INPROG),
   1972        1.92  augustss 	 * so start it first.
   1973        1.67  augustss 	 */
   1974  1.264.4.13     skrll 	return uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
   1975        1.16  augustss }
   1976        1.16  augustss 
   1977        1.16  augustss usbd_status
   1978       1.119  augustss uhci_device_bulk_start(usbd_xfer_handle xfer)
   1979        1.16  augustss {
   1980   1.264.4.7     skrll 	struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
   1981   1.264.4.7     skrll 	usbd_device_handle dev = upipe->pipe.up_dev;
   1982   1.264.4.7     skrll 	uhci_softc_t *sc = dev->ud_bus->ub_hcpriv;
   1983        1.92  augustss 	uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
   1984        1.55  augustss 	uhci_soft_td_t *data, *dataend;
   1985         1.1  augustss 	uhci_soft_qh_t *sqh;
   1986        1.63  augustss 	usbd_status err;
   1987        1.45  augustss 	int len, isread, endpt;
   1988         1.1  augustss 
   1989       1.169  augustss 	DPRINTFN(3, ("uhci_device_bulk_start: xfer=%p len=%d flags=%d ii=%p\n",
   1990   1.264.4.7     skrll 		     xfer, xfer->ux_length, xfer->ux_flags, ii));
   1991         1.1  augustss 
   1992        1.82  augustss 	if (sc->sc_dying)
   1993  1.264.4.13     skrll 		return USBD_IOERROR;
   1994        1.82  augustss 
   1995        1.48  augustss #ifdef DIAGNOSTIC
   1996   1.264.4.7     skrll 	if (xfer->ux_rqflags & URQ_REQUEST)
   1997       1.163    provos 		panic("uhci_device_bulk_transfer: a request");
   1998        1.48  augustss #endif
   1999         1.1  augustss 
   2000       1.248       mrg 	mutex_enter(&sc->sc_lock);
   2001       1.248       mrg 
   2002   1.264.4.7     skrll 	len = xfer->ux_length;
   2003   1.264.4.7     skrll 	endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
   2004        1.45  augustss 	isread = UE_GET_DIR(endpt) == UE_DIR_IN;
   2005         1.1  augustss 	sqh = upipe->u.bulk.sqh;
   2006         1.1  augustss 
   2007         1.1  augustss 	upipe->u.bulk.isread = isread;
   2008         1.1  augustss 	upipe->u.bulk.length = len;
   2009         1.1  augustss 
   2010   1.264.4.7     skrll 	err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->ux_flags,
   2011   1.264.4.7     skrll 				   &xfer->ux_dmabuf, &data, &dataend);
   2012       1.248       mrg 	if (err) {
   2013       1.248       mrg 		mutex_exit(&sc->sc_lock);
   2014  1.264.4.13     skrll 		return err;
   2015       1.248       mrg 	}
   2016        1.88   tsutsui 	dataend->td.td_status |= htole32(UHCI_TD_IOC);
   2017       1.223    bouyer 	usb_syncmem(&dataend->dma,
   2018       1.223    bouyer 	    dataend->offs + offsetof(uhci_td_t, td_status),
   2019       1.223    bouyer 	    sizeof(dataend->td.td_status),
   2020       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2021       1.223    bouyer 
   2022         1.1  augustss 
   2023        1.59  augustss #ifdef UHCI_DEBUG
   2024        1.33  augustss 	if (uhcidebug > 8) {
   2025        1.55  augustss 		DPRINTF(("uhci_device_bulk_transfer: data(1)\n"));
   2026        1.55  augustss 		uhci_dump_tds(data);
   2027         1.1  augustss 	}
   2028         1.1  augustss #endif
   2029         1.1  augustss 
   2030         1.1  augustss 	/* Set up interrupt info. */
   2031        1.63  augustss 	ii->xfer = xfer;
   2032        1.55  augustss 	ii->stdstart = data;
   2033        1.55  augustss 	ii->stdend = dataend;
   2034         1.7  augustss #ifdef DIAGNOSTIC
   2035        1.70  augustss 	if (!ii->isdone) {
   2036        1.70  augustss 		printf("uhci_device_bulk_transfer: not done, ii=%p\n", ii);
   2037        1.70  augustss 	}
   2038         1.7  augustss 	ii->isdone = 0;
   2039         1.7  augustss #endif
   2040         1.1  augustss 
   2041        1.55  augustss 	sqh->elink = data;
   2042       1.121  augustss 	sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD);
   2043       1.223    bouyer 	/* uhci_add_bulk() will do usb_syncmem(sqh) */
   2044         1.1  augustss 
   2045         1.1  augustss 	uhci_add_bulk(sc, sqh);
   2046        1.92  augustss 	uhci_add_intr_info(sc, ii);
   2047         1.1  augustss 
   2048   1.264.4.7     skrll 	if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
   2049   1.264.4.7     skrll 		callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
   2050        1.91  augustss 			    uhci_timeout, ii);
   2051        1.13  augustss 	}
   2052   1.264.4.7     skrll 	xfer->ux_status = USBD_IN_PROGRESS;
   2053         1.1  augustss 
   2054        1.59  augustss #ifdef UHCI_DEBUG
   2055         1.1  augustss 	if (uhcidebug > 10) {
   2056        1.55  augustss 		DPRINTF(("uhci_device_bulk_transfer: data(2)\n"));
   2057        1.55  augustss 		uhci_dump_tds(data);
   2058         1.1  augustss 	}
   2059         1.1  augustss #endif
   2060         1.1  augustss 
   2061   1.264.4.7     skrll 	if (sc->sc_bus.ub_usepolling)
   2062        1.63  augustss 		uhci_waitintr(sc, xfer);
   2063        1.26  augustss 
   2064       1.248       mrg 	mutex_exit(&sc->sc_lock);
   2065  1.264.4.13     skrll 	return USBD_IN_PROGRESS;
   2066         1.1  augustss }
   2067         1.1  augustss 
   2068         1.1  augustss /* Abort a device bulk request. */
   2069         1.1  augustss void
   2070       1.119  augustss uhci_device_bulk_abort(usbd_xfer_handle xfer)
   2071         1.1  augustss {
   2072       1.248       mrg #ifdef DIAGNOSTIC
   2073   1.264.4.7     skrll 	uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
   2074       1.248       mrg #endif
   2075       1.248       mrg 
   2076       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2077       1.248       mrg 
   2078        1.33  augustss 	DPRINTF(("uhci_device_bulk_abort:\n"));
   2079        1.66  augustss 	uhci_abort_xfer(xfer, USBD_CANCELLED);
   2080        1.33  augustss }
   2081        1.33  augustss 
   2082        1.92  augustss /*
   2083       1.154  augustss  * Abort a device request.
   2084       1.154  augustss  * If this routine is called at splusb() it guarantees that the request
   2085       1.154  augustss  * will be removed from the hardware scheduling and that the callback
   2086       1.154  augustss  * for it will be called with USBD_CANCELLED status.
   2087       1.154  augustss  * It's impossible to guarantee that the requested transfer will not
   2088       1.154  augustss  * have happened since the hardware runs concurrently.
   2089       1.154  augustss  * If the transaction has already happened we rely on the ordinary
   2090       1.154  augustss  * interrupt processing to process it.
   2091       1.248       mrg  * XXX This is most probably wrong.
   2092       1.248       mrg  * XXXMRG this doesn't make sense anymore.
   2093        1.92  augustss  */
   2094        1.33  augustss void
   2095       1.119  augustss uhci_abort_xfer(usbd_xfer_handle xfer, usbd_status status)
   2096        1.33  augustss {
   2097        1.92  augustss 	uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
   2098   1.264.4.7     skrll 	struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
   2099   1.264.4.7     skrll 	uhci_softc_t *sc = upipe->pipe.up_dev->ud_bus->ub_hcpriv;
   2100        1.33  augustss 	uhci_soft_td_t *std;
   2101       1.188  augustss 	int wake;
   2102        1.65  augustss 
   2103       1.106  augustss 	DPRINTFN(1,("uhci_abort_xfer: xfer=%p, status=%d\n", xfer, status));
   2104        1.33  augustss 
   2105       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2106   1.264.4.3     skrll 	ASSERT_SLEEPABLE();
   2107       1.248       mrg 
   2108       1.153  augustss 	if (sc->sc_dying) {
   2109       1.153  augustss 		/* If we're dying, just do the software part. */
   2110   1.264.4.7     skrll 		xfer->ux_status = status;	/* make software ignore it */
   2111   1.264.4.7     skrll 		callout_stop(&xfer->ux_callout);
   2112       1.153  augustss 		usb_transfer_complete(xfer);
   2113       1.194  christos 		return;
   2114        1.92  augustss 	}
   2115        1.92  augustss 
   2116       1.153  augustss 	/*
   2117       1.188  augustss 	 * If an abort is already in progress then just wait for it to
   2118       1.188  augustss 	 * complete and return.
   2119       1.188  augustss 	 */
   2120   1.264.4.7     skrll 	if (xfer->ux_hcflags & UXFER_ABORTING) {
   2121       1.188  augustss 		DPRINTFN(2, ("uhci_abort_xfer: already aborting\n"));
   2122       1.188  augustss #ifdef DIAGNOSTIC
   2123       1.188  augustss 		if (status == USBD_TIMEOUT)
   2124       1.188  augustss 			printf("uhci_abort_xfer: TIMEOUT while aborting\n");
   2125       1.188  augustss #endif
   2126       1.188  augustss 		/* Override the status which might be USBD_TIMEOUT. */
   2127   1.264.4.7     skrll 		xfer->ux_status = status;
   2128       1.188  augustss 		DPRINTFN(2, ("uhci_abort_xfer: waiting for abort to finish\n"));
   2129   1.264.4.7     skrll 		xfer->ux_hcflags |= UXFER_ABORTWAIT;
   2130   1.264.4.7     skrll 		while (xfer->ux_hcflags & UXFER_ABORTING)
   2131   1.264.4.7     skrll 			cv_wait(&xfer->ux_hccv, &sc->sc_lock);
   2132       1.248       mrg 		goto done;
   2133       1.188  augustss 	}
   2134   1.264.4.7     skrll 	xfer->ux_hcflags |= UXFER_ABORTING;
   2135       1.188  augustss 
   2136       1.188  augustss 	/*
   2137       1.153  augustss 	 * Step 1: Make interrupt routine and hardware ignore xfer.
   2138       1.153  augustss 	 */
   2139   1.264.4.7     skrll 	xfer->ux_status = status;	/* make software ignore it */
   2140   1.264.4.7     skrll 	callout_stop(&xfer->ux_callout);
   2141       1.153  augustss 	DPRINTFN(1,("uhci_abort_xfer: stop ii=%p\n", ii));
   2142       1.223    bouyer 	for (std = ii->stdstart; std != NULL; std = std->link.std) {
   2143       1.223    bouyer 		usb_syncmem(&std->dma,
   2144       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_status),
   2145       1.223    bouyer 		    sizeof(std->td.td_status),
   2146       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   2147        1.92  augustss 		std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC));
   2148       1.223    bouyer 		usb_syncmem(&std->dma,
   2149       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_status),
   2150       1.223    bouyer 		    sizeof(std->td.td_status),
   2151       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2152       1.223    bouyer 	}
   2153        1.92  augustss 
   2154       1.162  augustss 	/*
   2155       1.153  augustss 	 * Step 2: Wait until we know hardware has finished any possible
   2156       1.153  augustss 	 * use of the xfer.  Also make sure the soft interrupt routine
   2157       1.153  augustss 	 * has run.
   2158       1.153  augustss 	 */
   2159       1.248       mrg 	/* Hardware finishes in 1ms */
   2160   1.264.4.7     skrll 	usb_delay_ms_locked(upipe->pipe.up_dev->ud_bus, 2, &sc->sc_lock);
   2161       1.153  augustss 	sc->sc_softwake = 1;
   2162       1.153  augustss 	usb_schedsoftintr(&sc->sc_bus);
   2163       1.248       mrg 	DPRINTFN(1,("uhci_abort_xfer: cv_wait\n"));
   2164       1.248       mrg 	cv_wait(&sc->sc_softwake_cv, &sc->sc_lock);
   2165       1.162  augustss 
   2166       1.153  augustss 	/*
   2167       1.153  augustss 	 * Step 3: Execute callback.
   2168       1.153  augustss 	 */
   2169       1.154  augustss 	DPRINTFN(1,("uhci_abort_xfer: callback\n"));
   2170       1.100  augustss #ifdef DIAGNOSTIC
   2171       1.106  augustss 	ii->isdone = 1;
   2172       1.100  augustss #endif
   2173   1.264.4.7     skrll 	wake = xfer->ux_hcflags & UXFER_ABORTWAIT;
   2174   1.264.4.7     skrll 	xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT);
   2175       1.106  augustss 	usb_transfer_complete(xfer);
   2176       1.188  augustss 	if (wake)
   2177   1.264.4.7     skrll 		cv_broadcast(&xfer->ux_hccv);
   2178       1.248       mrg done:
   2179       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2180         1.1  augustss }
   2181         1.1  augustss 
   2182         1.1  augustss /* Close a device bulk pipe. */
   2183         1.1  augustss void
   2184       1.119  augustss uhci_device_bulk_close(usbd_pipe_handle pipe)
   2185         1.1  augustss {
   2186         1.1  augustss 	struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;
   2187   1.264.4.7     skrll 	usbd_device_handle dev = upipe->pipe.up_dev;
   2188   1.264.4.7     skrll 	uhci_softc_t *sc = dev->ud_bus->ub_hcpriv;
   2189         1.1  augustss 
   2190       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2191       1.248       mrg 
   2192         1.1  augustss 	uhci_free_sqh(sc, upipe->u.bulk.sqh);
   2193       1.236  drochner 
   2194   1.264.4.7     skrll 	pipe->up_endpoint->ue_toggle = upipe->nexttoggle;
   2195         1.1  augustss }
   2196         1.1  augustss 
   2197         1.1  augustss usbd_status
   2198       1.119  augustss uhci_device_ctrl_transfer(usbd_xfer_handle xfer)
   2199         1.1  augustss {
   2200   1.264.4.7     skrll 	uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
   2201        1.63  augustss 	usbd_status err;
   2202        1.16  augustss 
   2203        1.52  augustss 	/* Insert last in queue. */
   2204       1.248       mrg 	mutex_enter(&sc->sc_lock);
   2205        1.63  augustss 	err = usb_insert_transfer(xfer);
   2206       1.248       mrg 	mutex_exit(&sc->sc_lock);
   2207        1.63  augustss 	if (err)
   2208  1.264.4.13     skrll 		return err;
   2209        1.52  augustss 
   2210       1.152  augustss 	/*
   2211        1.92  augustss 	 * Pipe isn't running (otherwise err would be USBD_INPROG),
   2212        1.92  augustss 	 * so start it first.
   2213        1.67  augustss 	 */
   2214  1.264.4.13     skrll 	return uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
   2215        1.16  augustss }
   2216        1.16  augustss 
   2217        1.16  augustss usbd_status
   2218       1.119  augustss uhci_device_ctrl_start(usbd_xfer_handle xfer)
   2219        1.16  augustss {
   2220   1.264.4.7     skrll 	uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
   2221        1.63  augustss 	usbd_status err;
   2222         1.1  augustss 
   2223        1.82  augustss 	if (sc->sc_dying)
   2224  1.264.4.13     skrll 		return USBD_IOERROR;
   2225        1.82  augustss 
   2226        1.48  augustss #ifdef DIAGNOSTIC
   2227   1.264.4.7     skrll 	if (!(xfer->ux_rqflags & URQ_REQUEST))
   2228       1.163    provos 		panic("uhci_device_ctrl_transfer: not a request");
   2229        1.48  augustss #endif
   2230         1.1  augustss 
   2231       1.248       mrg 	mutex_enter(&sc->sc_lock);
   2232        1.63  augustss 	err = uhci_device_request(xfer);
   2233       1.248       mrg 	mutex_exit(&sc->sc_lock);
   2234        1.63  augustss 	if (err)
   2235  1.264.4.13     skrll 		return err;
   2236         1.1  augustss 
   2237   1.264.4.7     skrll 	if (sc->sc_bus.ub_usepolling)
   2238        1.63  augustss 		uhci_waitintr(sc, xfer);
   2239  1.264.4.13     skrll 	return USBD_IN_PROGRESS;
   2240         1.1  augustss }
   2241         1.1  augustss 
   2242         1.1  augustss usbd_status
   2243       1.119  augustss uhci_device_intr_transfer(usbd_xfer_handle xfer)
   2244         1.1  augustss {
   2245   1.264.4.7     skrll 	uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
   2246        1.63  augustss 	usbd_status err;
   2247        1.16  augustss 
   2248        1.52  augustss 	/* Insert last in queue. */
   2249       1.248       mrg 	mutex_enter(&sc->sc_lock);
   2250        1.63  augustss 	err = usb_insert_transfer(xfer);
   2251       1.248       mrg 	mutex_exit(&sc->sc_lock);
   2252        1.63  augustss 	if (err)
   2253  1.264.4.13     skrll 		return err;
   2254        1.52  augustss 
   2255       1.152  augustss 	/*
   2256        1.92  augustss 	 * Pipe isn't running (otherwise err would be USBD_INPROG),
   2257        1.92  augustss 	 * so start it first.
   2258        1.67  augustss 	 */
   2259  1.264.4.13     skrll 	return uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
   2260        1.16  augustss }
   2261        1.16  augustss 
   2262        1.16  augustss usbd_status
   2263       1.119  augustss uhci_device_intr_start(usbd_xfer_handle xfer)
   2264        1.16  augustss {
   2265   1.264.4.7     skrll 	struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
   2266   1.264.4.7     skrll 	usbd_device_handle dev = upipe->pipe.up_dev;
   2267   1.264.4.7     skrll 	uhci_softc_t *sc = dev->ud_bus->ub_hcpriv;
   2268        1.92  augustss 	uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
   2269        1.55  augustss 	uhci_soft_td_t *data, *dataend;
   2270         1.1  augustss 	uhci_soft_qh_t *sqh;
   2271        1.63  augustss 	usbd_status err;
   2272       1.187     skrll 	int isread, endpt;
   2273       1.248       mrg 	int i;
   2274         1.1  augustss 
   2275        1.82  augustss 	if (sc->sc_dying)
   2276  1.264.4.13     skrll 		return USBD_IOERROR;
   2277        1.82  augustss 
   2278        1.63  augustss 	DPRINTFN(3,("uhci_device_intr_transfer: xfer=%p len=%d flags=%d\n",
   2279   1.264.4.7     skrll 		    xfer, xfer->ux_length, xfer->ux_flags));
   2280         1.1  augustss 
   2281        1.48  augustss #ifdef DIAGNOSTIC
   2282   1.264.4.7     skrll 	if (xfer->ux_rqflags & URQ_REQUEST)
   2283       1.163    provos 		panic("uhci_device_intr_transfer: a request");
   2284        1.48  augustss #endif
   2285         1.1  augustss 
   2286       1.248       mrg 	mutex_enter(&sc->sc_lock);
   2287       1.248       mrg 
   2288   1.264.4.7     skrll 	endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
   2289       1.187     skrll 	isread = UE_GET_DIR(endpt) == UE_DIR_IN;
   2290       1.187     skrll 
   2291       1.187     skrll 	upipe->u.intr.isread = isread;
   2292       1.187     skrll 
   2293   1.264.4.7     skrll 	err = uhci_alloc_std_chain(upipe, sc, xfer->ux_length, isread,
   2294   1.264.4.7     skrll 				   xfer->ux_flags, &xfer->ux_dmabuf, &data,
   2295       1.187     skrll 				   &dataend);
   2296       1.248       mrg 	if (err) {
   2297       1.248       mrg 		mutex_exit(&sc->sc_lock);
   2298  1.264.4.13     skrll 		return err;
   2299       1.248       mrg 	}
   2300       1.248       mrg 
   2301        1.88   tsutsui 	dataend->td.td_status |= htole32(UHCI_TD_IOC);
   2302       1.223    bouyer 	usb_syncmem(&dataend->dma,
   2303       1.223    bouyer 	    dataend->offs + offsetof(uhci_td_t, td_status),
   2304       1.223    bouyer 	    sizeof(dataend->td.td_status),
   2305       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2306         1.1  augustss 
   2307        1.59  augustss #ifdef UHCI_DEBUG
   2308         1.1  augustss 	if (uhcidebug > 10) {
   2309        1.55  augustss 		DPRINTF(("uhci_device_intr_transfer: data(1)\n"));
   2310        1.55  augustss 		uhci_dump_tds(data);
   2311         1.1  augustss 		uhci_dump_qh(upipe->u.intr.qhs[0]);
   2312         1.1  augustss 	}
   2313         1.1  augustss #endif
   2314         1.1  augustss 
   2315         1.1  augustss 	/* Set up interrupt info. */
   2316        1.63  augustss 	ii->xfer = xfer;
   2317        1.55  augustss 	ii->stdstart = data;
   2318        1.55  augustss 	ii->stdend = dataend;
   2319         1.7  augustss #ifdef DIAGNOSTIC
   2320        1.70  augustss 	if (!ii->isdone) {
   2321        1.70  augustss 		printf("uhci_device_intr_transfer: not done, ii=%p\n", ii);
   2322        1.70  augustss 	}
   2323         1.7  augustss 	ii->isdone = 0;
   2324         1.7  augustss #endif
   2325         1.1  augustss 
   2326       1.152  augustss 	DPRINTFN(10,("uhci_device_intr_transfer: qhs[0]=%p\n",
   2327        1.12  augustss 		     upipe->u.intr.qhs[0]));
   2328         1.1  augustss 	for (i = 0; i < upipe->u.intr.npoll; i++) {
   2329         1.1  augustss 		sqh = upipe->u.intr.qhs[i];
   2330        1.55  augustss 		sqh->elink = data;
   2331       1.121  augustss 		sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD);
   2332       1.223    bouyer 		usb_syncmem(&sqh->dma,
   2333       1.223    bouyer 		    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   2334       1.223    bouyer 		    sizeof(sqh->qh.qh_elink),
   2335       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2336         1.1  augustss 	}
   2337        1.92  augustss 	uhci_add_intr_info(sc, ii);
   2338   1.264.4.7     skrll 	xfer->ux_status = USBD_IN_PROGRESS;
   2339       1.248       mrg 	mutex_exit(&sc->sc_lock);
   2340         1.1  augustss 
   2341        1.59  augustss #ifdef UHCI_DEBUG
   2342         1.1  augustss 	if (uhcidebug > 10) {
   2343        1.55  augustss 		DPRINTF(("uhci_device_intr_transfer: data(2)\n"));
   2344        1.55  augustss 		uhci_dump_tds(data);
   2345         1.1  augustss 		uhci_dump_qh(upipe->u.intr.qhs[0]);
   2346         1.1  augustss 	}
   2347         1.1  augustss #endif
   2348         1.1  augustss 
   2349  1.264.4.13     skrll 	return USBD_IN_PROGRESS;
   2350         1.1  augustss }
   2351         1.1  augustss 
   2352         1.1  augustss /* Abort a device control request. */
   2353         1.1  augustss void
   2354       1.119  augustss uhci_device_ctrl_abort(usbd_xfer_handle xfer)
   2355         1.1  augustss {
   2356       1.248       mrg #ifdef DIAGNOSTIC
   2357   1.264.4.7     skrll 	uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
   2358       1.248       mrg #endif
   2359       1.248       mrg 
   2360       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2361       1.248       mrg 
   2362        1.33  augustss 	DPRINTF(("uhci_device_ctrl_abort:\n"));
   2363        1.66  augustss 	uhci_abort_xfer(xfer, USBD_CANCELLED);
   2364         1.1  augustss }
   2365         1.1  augustss 
   2366         1.1  augustss /* Close a device control pipe. */
   2367         1.1  augustss void
   2368       1.205  christos uhci_device_ctrl_close(usbd_pipe_handle pipe)
   2369         1.1  augustss {
   2370         1.1  augustss }
   2371         1.1  augustss 
   2372         1.1  augustss /* Abort a device interrupt request. */
   2373         1.1  augustss void
   2374       1.119  augustss uhci_device_intr_abort(usbd_xfer_handle xfer)
   2375         1.1  augustss {
   2376       1.248       mrg #ifdef DIAGNOSTIC
   2377   1.264.4.7     skrll 	uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
   2378       1.248       mrg #endif
   2379       1.248       mrg 
   2380       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2381   1.264.4.7     skrll 	KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
   2382       1.248       mrg 
   2383        1.63  augustss 	DPRINTFN(1,("uhci_device_intr_abort: xfer=%p\n", xfer));
   2384       1.264     skrll 
   2385        1.66  augustss 	uhci_abort_xfer(xfer, USBD_CANCELLED);
   2386         1.1  augustss }
   2387         1.1  augustss 
   2388         1.1  augustss /* Close a device interrupt pipe. */
   2389         1.1  augustss void
   2390       1.119  augustss uhci_device_intr_close(usbd_pipe_handle pipe)
   2391         1.1  augustss {
   2392         1.1  augustss 	struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;
   2393   1.264.4.7     skrll 	uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv;
   2394        1.92  augustss 	int i, npoll;
   2395       1.248       mrg 
   2396       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2397         1.1  augustss 
   2398         1.1  augustss 	/* Unlink descriptors from controller data structures. */
   2399         1.1  augustss 	npoll = upipe->u.intr.npoll;
   2400         1.1  augustss 	for (i = 0; i < npoll; i++)
   2401        1.92  augustss 		uhci_remove_intr(sc, upipe->u.intr.qhs[i]);
   2402         1.1  augustss 
   2403       1.152  augustss 	/*
   2404         1.1  augustss 	 * We now have to wait for any activity on the physical
   2405         1.1  augustss 	 * descriptors to stop.
   2406         1.1  augustss 	 */
   2407       1.248       mrg 	usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock);
   2408         1.1  augustss 
   2409         1.1  augustss 	for(i = 0; i < npoll; i++)
   2410         1.1  augustss 		uhci_free_sqh(sc, upipe->u.intr.qhs[i]);
   2411       1.248       mrg 	kmem_free(upipe->u.intr.qhs, npoll * sizeof(uhci_soft_qh_t *));
   2412         1.1  augustss 
   2413         1.1  augustss 	/* XXX free other resources */
   2414         1.1  augustss }
   2415         1.1  augustss 
   2416         1.1  augustss usbd_status
   2417       1.119  augustss uhci_device_request(usbd_xfer_handle xfer)
   2418         1.1  augustss {
   2419   1.264.4.7     skrll 	struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
   2420   1.264.4.7     skrll 	usb_device_request_t *req = &xfer->ux_request;
   2421   1.264.4.7     skrll 	usbd_device_handle dev = upipe->pipe.up_dev;
   2422   1.264.4.7     skrll 	uhci_softc_t *sc = dev->ud_bus->ub_hcpriv;
   2423   1.264.4.7     skrll 	int addr = dev->ud_addr;
   2424   1.264.4.7     skrll 	int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
   2425        1.92  augustss 	uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
   2426        1.55  augustss 	uhci_soft_td_t *setup, *data, *stat, *next, *dataend;
   2427         1.1  augustss 	uhci_soft_qh_t *sqh;
   2428         1.1  augustss 	int len;
   2429   1.264.4.1     skrll 	uint32_t ls;
   2430        1.63  augustss 	usbd_status err;
   2431         1.1  augustss 	int isread;
   2432       1.248       mrg 
   2433       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2434         1.1  augustss 
   2435        1.13  augustss 	DPRINTFN(3,("uhci_device_control type=0x%02x, request=0x%02x, "
   2436        1.12  augustss 		    "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n",
   2437         1.1  augustss 		    req->bmRequestType, req->bRequest, UGETW(req->wValue),
   2438         1.1  augustss 		    UGETW(req->wIndex), UGETW(req->wLength),
   2439         1.1  augustss 		    addr, endpt));
   2440         1.1  augustss 
   2441   1.264.4.7     skrll 	ls = dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0;
   2442         1.1  augustss 	isread = req->bmRequestType & UT_READ;
   2443         1.1  augustss 	len = UGETW(req->wLength);
   2444         1.1  augustss 
   2445         1.1  augustss 	setup = upipe->u.ctl.setup;
   2446         1.1  augustss 	stat = upipe->u.ctl.stat;
   2447         1.1  augustss 	sqh = upipe->u.ctl.sqh;
   2448         1.1  augustss 
   2449         1.1  augustss 	/* Set up data transaction */
   2450         1.1  augustss 	if (len != 0) {
   2451        1.38  augustss 		upipe->nexttoggle = 1;
   2452   1.264.4.7     skrll 		err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->ux_flags,
   2453   1.264.4.7     skrll 					   &xfer->ux_dmabuf, &data, &dataend);
   2454        1.63  augustss 		if (err)
   2455  1.264.4.13     skrll 			return err;
   2456        1.55  augustss 		next = data;
   2457        1.55  augustss 		dataend->link.std = stat;
   2458       1.258     skrll 		dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD);
   2459       1.223    bouyer 		usb_syncmem(&dataend->dma,
   2460       1.223    bouyer 		    dataend->offs + offsetof(uhci_td_t, td_link),
   2461       1.223    bouyer 		    sizeof(dataend->td.td_link),
   2462       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2463         1.1  augustss 	} else {
   2464         1.1  augustss 		next = stat;
   2465         1.1  augustss 	}
   2466         1.1  augustss 	upipe->u.ctl.length = len;
   2467         1.1  augustss 
   2468       1.159  augustss 	memcpy(KERNADDR(&upipe->u.ctl.reqdma, 0), req, sizeof *req);
   2469       1.223    bouyer 	usb_syncmem(&upipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE);
   2470         1.1  augustss 
   2471        1.42  augustss 	setup->link.std = next;
   2472       1.258     skrll 	setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD);
   2473        1.88   tsutsui 	setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls |
   2474        1.88   tsutsui 		UHCI_TD_ACTIVE);
   2475        1.88   tsutsui 	setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof *req, endpt, addr));
   2476       1.160  augustss 	setup->td.td_buffer = htole32(DMAADDR(&upipe->u.ctl.reqdma, 0));
   2477       1.223    bouyer 	usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td),
   2478       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2479        1.42  augustss 
   2480        1.92  augustss 	stat->link.std = NULL;
   2481        1.88   tsutsui 	stat->td.td_link = htole32(UHCI_PTR_T);
   2482       1.152  augustss 	stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls |
   2483        1.39  augustss 		UHCI_TD_ACTIVE | UHCI_TD_IOC);
   2484       1.152  augustss 	stat->td.td_token =
   2485        1.88   tsutsui 		htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) :
   2486   1.264.4.2     skrll 				 UHCI_TD_IN (0, endpt, addr, 1));
   2487        1.88   tsutsui 	stat->td.td_buffer = htole32(0);
   2488       1.223    bouyer 	usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td),
   2489       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2490         1.1  augustss 
   2491        1.59  augustss #ifdef UHCI_DEBUG
   2492        1.67  augustss 	if (uhcidebug > 10) {
   2493        1.47  augustss 		DPRINTF(("uhci_device_request: before transfer\n"));
   2494        1.41  augustss 		uhci_dump_tds(setup);
   2495         1.1  augustss 	}
   2496         1.1  augustss #endif
   2497         1.1  augustss 
   2498         1.1  augustss 	/* Set up interrupt info. */
   2499        1.63  augustss 	ii->xfer = xfer;
   2500         1.1  augustss 	ii->stdstart = setup;
   2501         1.1  augustss 	ii->stdend = stat;
   2502         1.7  augustss #ifdef DIAGNOSTIC
   2503        1.70  augustss 	if (!ii->isdone) {
   2504        1.70  augustss 		printf("uhci_device_request: not done, ii=%p\n", ii);
   2505        1.70  augustss 	}
   2506         1.7  augustss 	ii->isdone = 0;
   2507         1.7  augustss #endif
   2508         1.1  augustss 
   2509        1.42  augustss 	sqh->elink = setup;
   2510       1.121  augustss 	sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD);
   2511       1.223    bouyer 	/* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */
   2512         1.1  augustss 
   2513   1.264.4.7     skrll 	if (dev->ud_speed == USB_SPEED_LOW)
   2514       1.123  augustss 		uhci_add_ls_ctrl(sc, sqh);
   2515       1.123  augustss 	else
   2516       1.123  augustss 		uhci_add_hs_ctrl(sc, sqh);
   2517        1.92  augustss 	uhci_add_intr_info(sc, ii);
   2518        1.59  augustss #ifdef UHCI_DEBUG
   2519         1.1  augustss 	if (uhcidebug > 12) {
   2520         1.1  augustss 		uhci_soft_td_t *std;
   2521         1.1  augustss 		uhci_soft_qh_t *xqh;
   2522        1.13  augustss 		uhci_soft_qh_t *sxqh;
   2523        1.13  augustss 		int maxqh = 0;
   2524         1.1  augustss 		uhci_physaddr_t link;
   2525        1.47  augustss 		DPRINTF(("uhci_enter_ctl_q: follow from [0]\n"));
   2526         1.1  augustss 		for (std = sc->sc_vframes[0].htd, link = 0;
   2527       1.121  augustss 		     (link & UHCI_PTR_QH) == 0;
   2528        1.42  augustss 		     std = std->link.std) {
   2529        1.88   tsutsui 			link = le32toh(std->td.td_link);
   2530         1.1  augustss 			uhci_dump_td(std);
   2531         1.1  augustss 		}
   2532        1.67  augustss 		sxqh = (uhci_soft_qh_t *)std;
   2533        1.67  augustss 		uhci_dump_qh(sxqh);
   2534        1.67  augustss 		for (xqh = sxqh;
   2535        1.63  augustss 		     xqh != NULL;
   2536       1.152  augustss 		     xqh = (maxqh++ == 5 || xqh->hlink == sxqh ||
   2537   1.264.4.2     skrll 			xqh->hlink == xqh ? NULL : xqh->hlink)) {
   2538         1.1  augustss 			uhci_dump_qh(xqh);
   2539        1.13  augustss 		}
   2540        1.47  augustss 		DPRINTF(("Enqueued QH:\n"));
   2541         1.1  augustss 		uhci_dump_qh(sqh);
   2542        1.42  augustss 		uhci_dump_tds(sqh->elink);
   2543         1.1  augustss 	}
   2544         1.1  augustss #endif
   2545   1.264.4.7     skrll 	if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
   2546   1.264.4.7     skrll 		callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
   2547        1.91  augustss 			    uhci_timeout, ii);
   2548        1.13  augustss 	}
   2549   1.264.4.7     skrll 	xfer->ux_status = USBD_IN_PROGRESS;
   2550         1.1  augustss 
   2551  1.264.4.13     skrll 	return USBD_NORMAL_COMPLETION;
   2552         1.1  augustss }
   2553         1.1  augustss 
   2554        1.16  augustss usbd_status
   2555       1.119  augustss uhci_device_isoc_transfer(usbd_xfer_handle xfer)
   2556        1.16  augustss {
   2557   1.264.4.7     skrll 	uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
   2558        1.63  augustss 	usbd_status err;
   2559        1.48  augustss 
   2560        1.63  augustss 	DPRINTFN(5,("uhci_device_isoc_transfer: xfer=%p\n", xfer));
   2561        1.48  augustss 
   2562        1.48  augustss 	/* Put it on our queue, */
   2563       1.248       mrg 	mutex_enter(&sc->sc_lock);
   2564        1.63  augustss 	err = usb_insert_transfer(xfer);
   2565       1.248       mrg 	mutex_exit(&sc->sc_lock);
   2566        1.48  augustss 
   2567        1.48  augustss 	/* bail out on error, */
   2568        1.63  augustss 	if (err && err != USBD_IN_PROGRESS)
   2569  1.264.4.13     skrll 		return err;
   2570        1.48  augustss 
   2571        1.48  augustss 	/* XXX should check inuse here */
   2572        1.48  augustss 
   2573        1.48  augustss 	/* insert into schedule, */
   2574        1.63  augustss 	uhci_device_isoc_enter(xfer);
   2575        1.48  augustss 
   2576       1.102  augustss 	/* and start if the pipe wasn't running */
   2577        1.67  augustss 	if (!err)
   2578   1.264.4.7     skrll 		uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
   2579        1.48  augustss 
   2580  1.264.4.13     skrll 	return err;
   2581        1.48  augustss }
   2582        1.48  augustss 
   2583        1.48  augustss void
   2584       1.119  augustss uhci_device_isoc_enter(usbd_xfer_handle xfer)
   2585        1.48  augustss {
   2586   1.264.4.7     skrll 	struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
   2587   1.264.4.7     skrll 	usbd_device_handle dev = upipe->pipe.up_dev;
   2588   1.264.4.7     skrll 	uhci_softc_t *sc = dev->ud_bus->ub_hcpriv;
   2589        1.48  augustss 	struct iso *iso = &upipe->u.iso;
   2590       1.152  augustss 	uhci_soft_td_t *std;
   2591   1.264.4.1     skrll 	uint32_t buf, len, status, offs;
   2592       1.248       mrg 	int i, next, nframes;
   2593   1.264.4.7     skrll 	int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN;
   2594        1.48  augustss 
   2595        1.63  augustss 	DPRINTFN(5,("uhci_device_isoc_enter: used=%d next=%d xfer=%p "
   2596        1.48  augustss 		    "nframes=%d\n",
   2597   1.264.4.7     skrll 		    iso->inuse, iso->next, xfer, xfer->ux_nframes));
   2598        1.48  augustss 
   2599        1.82  augustss 	if (sc->sc_dying)
   2600        1.82  augustss 		return;
   2601        1.82  augustss 
   2602   1.264.4.7     skrll 	if (xfer->ux_status == USBD_IN_PROGRESS) {
   2603        1.48  augustss 		/* This request has already been entered into the frame list */
   2604        1.96  augustss 		printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer);
   2605        1.68  augustss 		/* XXX */
   2606        1.48  augustss 	}
   2607        1.48  augustss 
   2608        1.48  augustss #ifdef DIAGNOSTIC
   2609        1.48  augustss 	if (iso->inuse >= UHCI_VFRAMELIST_COUNT)
   2610        1.48  augustss 		printf("uhci_device_isoc_enter: overflow!\n");
   2611        1.19  augustss #endif
   2612        1.16  augustss 
   2613        1.48  augustss 	next = iso->next;
   2614        1.48  augustss 	if (next == -1) {
   2615        1.48  augustss 		/* Not in use yet, schedule it a few frames ahead. */
   2616        1.48  augustss 		next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT;
   2617        1.48  augustss 		DPRINTFN(2,("uhci_device_isoc_enter: start next=%d\n", next));
   2618        1.48  augustss 	}
   2619        1.48  augustss 
   2620   1.264.4.7     skrll 	xfer->ux_status = USBD_IN_PROGRESS;
   2621        1.92  augustss 	UXFER(xfer)->curframe = next;
   2622        1.48  augustss 
   2623   1.264.4.7     skrll 	buf = DMAADDR(&xfer->ux_dmabuf, 0);
   2624       1.223    bouyer 	offs = 0;
   2625        1.88   tsutsui 	status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) |
   2626        1.88   tsutsui 				     UHCI_TD_ACTIVE |
   2627        1.88   tsutsui 				     UHCI_TD_IOS);
   2628   1.264.4.7     skrll 	nframes = xfer->ux_nframes;
   2629       1.248       mrg 	mutex_enter(&sc->sc_lock);
   2630        1.48  augustss 	for (i = 0; i < nframes; i++) {
   2631        1.48  augustss 		std = iso->stds[next];
   2632        1.48  augustss 		if (++next >= UHCI_VFRAMELIST_COUNT)
   2633        1.48  augustss 			next = 0;
   2634   1.264.4.7     skrll 		len = xfer->ux_frlengths[i];
   2635        1.88   tsutsui 		std->td.td_buffer = htole32(buf);
   2636   1.264.4.7     skrll 		usb_syncmem(&xfer->ux_dmabuf, offs, len,
   2637       1.223    bouyer 		    rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
   2638        1.48  augustss 		if (i == nframes - 1)
   2639        1.88   tsutsui 			status |= UHCI_TD_IOC;
   2640        1.88   tsutsui 		std->td.td_status = htole32(status);
   2641        1.88   tsutsui 		std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK);
   2642        1.88   tsutsui 		std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len));
   2643       1.223    bouyer 		usb_syncmem(&std->dma, std->offs, sizeof(std->td),
   2644       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2645        1.59  augustss #ifdef UHCI_DEBUG
   2646        1.48  augustss 		if (uhcidebug > 5) {
   2647        1.48  augustss 			DPRINTFN(5,("uhci_device_isoc_enter: TD %d\n", i));
   2648        1.48  augustss 			uhci_dump_td(std);
   2649        1.48  augustss 		}
   2650        1.48  augustss #endif
   2651        1.48  augustss 		buf += len;
   2652       1.223    bouyer 		offs += len;
   2653        1.48  augustss 	}
   2654        1.48  augustss 	iso->next = next;
   2655   1.264.4.7     skrll 	iso->inuse += xfer->ux_nframes;
   2656        1.16  augustss 
   2657       1.248       mrg 	mutex_exit(&sc->sc_lock);
   2658        1.16  augustss }
   2659        1.16  augustss 
   2660        1.16  augustss usbd_status
   2661       1.119  augustss uhci_device_isoc_start(usbd_xfer_handle xfer)
   2662        1.16  augustss {
   2663   1.264.4.7     skrll 	struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
   2664   1.264.4.7     skrll 	uhci_softc_t *sc = upipe->pipe.up_dev->ud_bus->ub_hcpriv;
   2665        1.92  augustss 	uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
   2666        1.48  augustss 	uhci_soft_td_t *end;
   2667       1.248       mrg 	int i;
   2668        1.48  augustss 
   2669        1.96  augustss 	DPRINTFN(5,("uhci_device_isoc_start: xfer=%p\n", xfer));
   2670        1.96  augustss 
   2671       1.248       mrg 	mutex_enter(&sc->sc_lock);
   2672       1.248       mrg 
   2673       1.248       mrg 	if (sc->sc_dying) {
   2674       1.248       mrg 		mutex_exit(&sc->sc_lock);
   2675  1.264.4.13     skrll 		return USBD_IOERROR;
   2676       1.248       mrg 	}
   2677        1.82  augustss 
   2678        1.48  augustss #ifdef DIAGNOSTIC
   2679   1.264.4.7     skrll 	if (xfer->ux_status != USBD_IN_PROGRESS)
   2680        1.63  augustss 		printf("uhci_device_isoc_start: not in progress %p\n", xfer);
   2681        1.48  augustss #endif
   2682        1.48  augustss 
   2683        1.48  augustss 	/* Find the last TD */
   2684   1.264.4.7     skrll 	i = UXFER(xfer)->curframe + xfer->ux_nframes;
   2685        1.48  augustss 	if (i >= UHCI_VFRAMELIST_COUNT)
   2686        1.48  augustss 		i -= UHCI_VFRAMELIST_COUNT;
   2687        1.48  augustss 	end = upipe->u.iso.stds[i];
   2688        1.48  augustss 
   2689        1.96  augustss #ifdef DIAGNOSTIC
   2690        1.96  augustss 	if (end == NULL) {
   2691        1.96  augustss 		printf("uhci_device_isoc_start: end == NULL\n");
   2692  1.264.4.13     skrll 		return USBD_INVAL;
   2693        1.96  augustss 	}
   2694        1.96  augustss #endif
   2695        1.96  augustss 
   2696        1.48  augustss 	/* Set up interrupt info. */
   2697        1.63  augustss 	ii->xfer = xfer;
   2698        1.48  augustss 	ii->stdstart = end;
   2699        1.48  augustss 	ii->stdend = end;
   2700        1.48  augustss #ifdef DIAGNOSTIC
   2701       1.102  augustss 	if (!ii->isdone)
   2702        1.70  augustss 		printf("uhci_device_isoc_start: not done, ii=%p\n", ii);
   2703        1.48  augustss 	ii->isdone = 0;
   2704        1.48  augustss #endif
   2705        1.92  augustss 	uhci_add_intr_info(sc, ii);
   2706       1.152  augustss 
   2707       1.248       mrg 	mutex_exit(&sc->sc_lock);
   2708        1.48  augustss 
   2709  1.264.4.13     skrll 	return USBD_IN_PROGRESS;
   2710        1.16  augustss }
   2711        1.16  augustss 
   2712        1.16  augustss void
   2713       1.119  augustss uhci_device_isoc_abort(usbd_xfer_handle xfer)
   2714        1.16  augustss {
   2715       1.248       mrg #ifdef DIAGNOSTIC
   2716   1.264.4.7     skrll 	uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
   2717       1.248       mrg #endif
   2718   1.264.4.7     skrll 	struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
   2719        1.48  augustss 	uhci_soft_td_t **stds = upipe->u.iso.stds;
   2720        1.48  augustss 	uhci_soft_td_t *std;
   2721       1.248       mrg 	int i, n, nframes, maxlen, len;
   2722        1.92  augustss 
   2723       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2724        1.92  augustss 
   2725        1.92  augustss 	/* Transfer is already done. */
   2726   1.264.4.7     skrll 	if (xfer->ux_status != USBD_NOT_STARTED &&
   2727   1.264.4.7     skrll 	    xfer->ux_status != USBD_IN_PROGRESS) {
   2728        1.92  augustss 		return;
   2729        1.92  augustss 	}
   2730        1.48  augustss 
   2731        1.92  augustss 	/* Give xfer the requested abort code. */
   2732   1.264.4.7     skrll 	xfer->ux_status = USBD_CANCELLED;
   2733        1.48  augustss 
   2734        1.48  augustss 	/* make hardware ignore it, */
   2735   1.264.4.7     skrll 	nframes = xfer->ux_nframes;
   2736        1.92  augustss 	n = UXFER(xfer)->curframe;
   2737        1.92  augustss 	maxlen = 0;
   2738        1.48  augustss 	for (i = 0; i < nframes; i++) {
   2739        1.48  augustss 		std = stds[n];
   2740       1.223    bouyer 		usb_syncmem(&std->dma,
   2741       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_status),
   2742       1.223    bouyer 		    sizeof(std->td.td_status),
   2743       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   2744        1.88   tsutsui 		std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC));
   2745       1.223    bouyer 		usb_syncmem(&std->dma,
   2746       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_status),
   2747       1.223    bouyer 		    sizeof(std->td.td_status),
   2748       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2749       1.223    bouyer 		usb_syncmem(&std->dma,
   2750       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_token),
   2751       1.223    bouyer 		    sizeof(std->td.td_token),
   2752       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE);
   2753       1.130   tsutsui 		len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token));
   2754        1.92  augustss 		if (len > maxlen)
   2755        1.92  augustss 			maxlen = len;
   2756        1.48  augustss 		if (++n >= UHCI_VFRAMELIST_COUNT)
   2757        1.48  augustss 			n = 0;
   2758        1.48  augustss 	}
   2759        1.48  augustss 
   2760        1.92  augustss 	/* and wait until we are sure the hardware has finished. */
   2761        1.92  augustss 	delay(maxlen);
   2762        1.92  augustss 
   2763        1.96  augustss #ifdef DIAGNOSTIC
   2764        1.96  augustss 	UXFER(xfer)->iinfo.isdone = 1;
   2765        1.96  augustss #endif
   2766        1.92  augustss 	/* Run callback and remove from interrupt list. */
   2767        1.92  augustss 	usb_transfer_complete(xfer);
   2768        1.48  augustss 
   2769       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2770        1.16  augustss }
   2771        1.16  augustss 
   2772        1.16  augustss void
   2773       1.119  augustss uhci_device_isoc_close(usbd_pipe_handle pipe)
   2774        1.16  augustss {
   2775        1.16  augustss 	struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;
   2776   1.264.4.7     skrll 	usbd_device_handle dev = upipe->pipe.up_dev;
   2777   1.264.4.7     skrll 	uhci_softc_t *sc = dev->ud_bus->ub_hcpriv;
   2778        1.48  augustss 	uhci_soft_td_t *std, *vstd;
   2779        1.16  augustss 	struct iso *iso;
   2780       1.248       mrg 	int i;
   2781       1.248       mrg 
   2782       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2783        1.16  augustss 
   2784        1.16  augustss 	/*
   2785        1.16  augustss 	 * Make sure all TDs are marked as inactive.
   2786        1.16  augustss 	 * Wait for completion.
   2787        1.16  augustss 	 * Unschedule.
   2788        1.16  augustss 	 * Deallocate.
   2789        1.16  augustss 	 */
   2790        1.16  augustss 	iso = &upipe->u.iso;
   2791        1.16  augustss 
   2792       1.223    bouyer 	for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
   2793       1.223    bouyer 		std = iso->stds[i];
   2794       1.223    bouyer 		usb_syncmem(&std->dma,
   2795       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_status),
   2796       1.223    bouyer 		    sizeof(std->td.td_status),
   2797       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   2798       1.223    bouyer 		std->td.td_status &= htole32(~UHCI_TD_ACTIVE);
   2799       1.223    bouyer 		usb_syncmem(&std->dma,
   2800       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_status),
   2801       1.223    bouyer 		    sizeof(std->td.td_status),
   2802       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2803       1.223    bouyer 	}
   2804       1.248       mrg 	/* wait for completion */
   2805       1.248       mrg 	usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock);
   2806        1.16  augustss 
   2807        1.16  augustss 	for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
   2808        1.16  augustss 		std = iso->stds[i];
   2809        1.48  augustss 		for (vstd = sc->sc_vframes[i].htd;
   2810        1.67  augustss 		     vstd != NULL && vstd->link.std != std;
   2811        1.42  augustss 		     vstd = vstd->link.std)
   2812        1.16  augustss 			;
   2813        1.67  augustss 		if (vstd == NULL) {
   2814        1.16  augustss 			/*panic*/
   2815        1.16  augustss 			printf("uhci_device_isoc_close: %p not found\n", std);
   2816       1.248       mrg 			mutex_exit(&sc->sc_lock);
   2817        1.16  augustss 			return;
   2818        1.16  augustss 		}
   2819        1.42  augustss 		vstd->link = std->link;
   2820       1.223    bouyer 		usb_syncmem(&std->dma,
   2821       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_link),
   2822       1.223    bouyer 		    sizeof(std->td.td_link),
   2823       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE);
   2824        1.42  augustss 		vstd->td.td_link = std->td.td_link;
   2825       1.223    bouyer 		usb_syncmem(&vstd->dma,
   2826       1.223    bouyer 		    vstd->offs + offsetof(uhci_td_t, td_link),
   2827       1.223    bouyer 		    sizeof(vstd->td.td_link),
   2828       1.223    bouyer 		    BUS_DMASYNC_PREWRITE);
   2829        1.16  augustss 		uhci_free_std(sc, std);
   2830        1.16  augustss 	}
   2831        1.16  augustss 
   2832       1.248       mrg 	kmem_free(iso->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *));
   2833        1.16  augustss }
   2834        1.16  augustss 
   2835        1.16  augustss usbd_status
   2836       1.119  augustss uhci_setup_isoc(usbd_pipe_handle pipe)
   2837        1.16  augustss {
   2838        1.16  augustss 	struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;
   2839   1.264.4.7     skrll 	usbd_device_handle dev = upipe->pipe.up_dev;
   2840   1.264.4.7     skrll 	uhci_softc_t *sc = dev->ud_bus->ub_hcpriv;
   2841   1.264.4.7     skrll 	int addr = upipe->pipe.up_dev->ud_addr;
   2842   1.264.4.7     skrll 	int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
   2843        1.45  augustss 	int rd = UE_GET_DIR(endpt) == UE_DIR_IN;
   2844        1.48  augustss 	uhci_soft_td_t *std, *vstd;
   2845   1.264.4.1     skrll 	uint32_t token;
   2846        1.16  augustss 	struct iso *iso;
   2847       1.248       mrg 	int i;
   2848        1.16  augustss 
   2849        1.16  augustss 	iso = &upipe->u.iso;
   2850       1.248       mrg 	iso->stds = kmem_alloc(UHCI_VFRAMELIST_COUNT *
   2851       1.248       mrg 				 sizeof (uhci_soft_td_t *),
   2852       1.248       mrg 			       KM_SLEEP);
   2853       1.248       mrg 	if (iso->stds == NULL)
   2854       1.248       mrg 		return USBD_NOMEM;
   2855        1.16  augustss 
   2856        1.88   tsutsui 	token = rd ? UHCI_TD_IN (0, endpt, addr, 0) :
   2857        1.88   tsutsui 		     UHCI_TD_OUT(0, endpt, addr, 0);
   2858        1.16  augustss 
   2859       1.248       mrg 	mutex_enter(&sc->sc_lock);
   2860       1.248       mrg 
   2861        1.48  augustss 	/* Allocate the TDs and mark as inactive; */
   2862        1.16  augustss 	for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
   2863        1.48  augustss 		std = uhci_alloc_std(sc);
   2864        1.48  augustss 		if (std == 0)
   2865        1.48  augustss 			goto bad;
   2866        1.88   tsutsui 		std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */
   2867        1.88   tsutsui 		std->td.td_token = htole32(token);
   2868       1.223    bouyer 		usb_syncmem(&std->dma, std->offs, sizeof(std->td),
   2869       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2870        1.48  augustss 		iso->stds[i] = std;
   2871        1.16  augustss 	}
   2872        1.16  augustss 
   2873        1.48  augustss 	/* Insert TDs into schedule. */
   2874        1.16  augustss 	for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
   2875        1.16  augustss 		std = iso->stds[i];
   2876        1.48  augustss 		vstd = sc->sc_vframes[i].htd;
   2877       1.223    bouyer 		usb_syncmem(&vstd->dma,
   2878       1.223    bouyer 		    vstd->offs + offsetof(uhci_td_t, td_link),
   2879       1.223    bouyer 		    sizeof(vstd->td.td_link),
   2880       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE);
   2881        1.42  augustss 		std->link = vstd->link;
   2882        1.42  augustss 		std->td.td_link = vstd->td.td_link;
   2883       1.223    bouyer 		usb_syncmem(&std->dma,
   2884       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_link),
   2885       1.223    bouyer 		    sizeof(std->td.td_link),
   2886       1.223    bouyer 		    BUS_DMASYNC_PREWRITE);
   2887        1.42  augustss 		vstd->link.std = std;
   2888       1.121  augustss 		vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD);
   2889       1.223    bouyer 		usb_syncmem(&vstd->dma,
   2890       1.223    bouyer 		    vstd->offs + offsetof(uhci_td_t, td_link),
   2891       1.223    bouyer 		    sizeof(vstd->td.td_link),
   2892       1.223    bouyer 		    BUS_DMASYNC_PREWRITE);
   2893        1.16  augustss 	}
   2894       1.248       mrg 	mutex_exit(&sc->sc_lock);
   2895        1.16  augustss 
   2896        1.48  augustss 	iso->next = -1;
   2897        1.48  augustss 	iso->inuse = 0;
   2898        1.48  augustss 
   2899  1.264.4.13     skrll 	return USBD_NORMAL_COMPLETION;
   2900        1.16  augustss 
   2901        1.48  augustss  bad:
   2902        1.16  augustss 	while (--i >= 0)
   2903        1.16  augustss 		uhci_free_std(sc, iso->stds[i]);
   2904       1.248       mrg 	mutex_exit(&sc->sc_lock);
   2905       1.248       mrg 	kmem_free(iso->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *));
   2906  1.264.4.13     skrll 	return USBD_NOMEM;
   2907        1.16  augustss }
   2908        1.16  augustss 
   2909        1.16  augustss void
   2910       1.119  augustss uhci_device_isoc_done(usbd_xfer_handle xfer)
   2911        1.16  augustss {
   2912        1.92  augustss 	uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
   2913   1.264.4.7     skrll 	struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
   2914       1.223    bouyer 	int i, offs;
   2915   1.264.4.7     skrll 	int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN;
   2916       1.223    bouyer 
   2917        1.48  augustss 
   2918   1.264.4.7     skrll 	DPRINTFN(4, ("uhci_isoc_done: length=%d, ux_state=0x%08x\n",
   2919   1.264.4.7     skrll 			xfer->ux_actlen, xfer->ux_state));
   2920        1.93  augustss 
   2921        1.96  augustss 	if (ii->xfer != xfer)
   2922        1.96  augustss 		/* Not on interrupt list, ignore it. */
   2923       1.170  augustss 		return;
   2924       1.170  augustss 
   2925       1.170  augustss 	if (!uhci_active_intr_info(ii))
   2926        1.96  augustss 		return;
   2927        1.96  augustss 
   2928        1.93  augustss #ifdef DIAGNOSTIC
   2929   1.264.4.2     skrll 	if (ii->stdend == NULL) {
   2930   1.264.4.2     skrll 		printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer);
   2931        1.93  augustss #ifdef UHCI_DEBUG
   2932        1.93  augustss 		uhci_dump_ii(ii);
   2933        1.93  augustss #endif
   2934        1.93  augustss 		return;
   2935        1.93  augustss 	}
   2936        1.93  augustss #endif
   2937        1.48  augustss 
   2938        1.48  augustss 	/* Turn off the interrupt since it is active even if the TD is not. */
   2939       1.223    bouyer 	usb_syncmem(&ii->stdend->dma,
   2940       1.223    bouyer 	    ii->stdend->offs + offsetof(uhci_td_t, td_status),
   2941       1.223    bouyer 	    sizeof(ii->stdend->td.td_status),
   2942       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   2943        1.88   tsutsui 	ii->stdend->td.td_status &= htole32(~UHCI_TD_IOC);
   2944       1.223    bouyer 	usb_syncmem(&ii->stdend->dma,
   2945       1.223    bouyer 	    ii->stdend->offs + offsetof(uhci_td_t, td_status),
   2946       1.223    bouyer 	    sizeof(ii->stdend->td.td_status),
   2947       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2948        1.48  augustss 
   2949        1.92  augustss 	uhci_del_intr_info(ii);	/* remove from active list */
   2950       1.223    bouyer 
   2951       1.223    bouyer 	offs = 0;
   2952   1.264.4.7     skrll 	for (i = 0; i < xfer->ux_nframes; i++) {
   2953   1.264.4.7     skrll 		usb_syncmem(&xfer->ux_dmabuf, offs, xfer->ux_frlengths[i],
   2954       1.223    bouyer 		    rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
   2955   1.264.4.7     skrll 		offs += xfer->ux_frlengths[i];
   2956       1.223    bouyer 	}
   2957        1.16  augustss }
   2958        1.16  augustss 
   2959         1.1  augustss void
   2960       1.119  augustss uhci_device_intr_done(usbd_xfer_handle xfer)
   2961         1.1  augustss {
   2962        1.92  augustss 	uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
   2963         1.1  augustss 	uhci_softc_t *sc = ii->sc;
   2964   1.264.4.7     skrll 	struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
   2965         1.1  augustss 	uhci_soft_qh_t *sqh;
   2966       1.223    bouyer 	int i, npoll, isread;
   2967         1.1  augustss 
   2968   1.264.4.7     skrll 	DPRINTFN(5, ("uhci_device_intr_done: length=%d\n", xfer->ux_actlen));
   2969         1.1  augustss 
   2970   1.264.4.7     skrll 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
   2971       1.248       mrg 
   2972         1.1  augustss 	npoll = upipe->u.intr.npoll;
   2973         1.1  augustss 	for(i = 0; i < npoll; i++) {
   2974         1.1  augustss 		sqh = upipe->u.intr.qhs[i];
   2975       1.121  augustss 		sqh->elink = NULL;
   2976        1.88   tsutsui 		sqh->qh.qh_elink = htole32(UHCI_PTR_T);
   2977       1.223    bouyer 		usb_syncmem(&sqh->dma,
   2978       1.223    bouyer 		    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   2979       1.223    bouyer 		    sizeof(sqh->qh.qh_elink),
   2980       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2981         1.1  augustss 	}
   2982       1.149  augustss 	uhci_free_std_chain(sc, ii->stdstart, NULL);
   2983         1.1  augustss 
   2984   1.264.4.7     skrll 	isread = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN;
   2985   1.264.4.7     skrll 	usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
   2986       1.223    bouyer 	    isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
   2987       1.223    bouyer 
   2988         1.1  augustss 	/* XXX Wasteful. */
   2989   1.264.4.7     skrll 	if (xfer->ux_pipe->up_repeat) {
   2990        1.55  augustss 		uhci_soft_td_t *data, *dataend;
   2991         1.1  augustss 
   2992        1.92  augustss 		DPRINTFN(5,("uhci_device_intr_done: requeing\n"));
   2993        1.92  augustss 
   2994         1.1  augustss 		/* This alloc cannot fail since we freed the chain above. */
   2995   1.264.4.7     skrll 		uhci_alloc_std_chain(upipe, sc, xfer->ux_length,
   2996   1.264.4.7     skrll 				     upipe->u.intr.isread, xfer->ux_flags,
   2997   1.264.4.7     skrll 				     &xfer->ux_dmabuf, &data, &dataend);
   2998        1.88   tsutsui 		dataend->td.td_status |= htole32(UHCI_TD_IOC);
   2999       1.223    bouyer 		usb_syncmem(&dataend->dma,
   3000       1.223    bouyer 		    dataend->offs + offsetof(uhci_td_t, td_status),
   3001       1.223    bouyer 		    sizeof(dataend->td.td_status),
   3002       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   3003         1.1  augustss 
   3004        1.59  augustss #ifdef UHCI_DEBUG
   3005         1.1  augustss 		if (uhcidebug > 10) {
   3006        1.55  augustss 			DPRINTF(("uhci_device_intr_done: data(1)\n"));
   3007        1.55  augustss 			uhci_dump_tds(data);
   3008         1.1  augustss 			uhci_dump_qh(upipe->u.intr.qhs[0]);
   3009         1.1  augustss 		}
   3010         1.1  augustss #endif
   3011         1.1  augustss 
   3012        1.55  augustss 		ii->stdstart = data;
   3013        1.55  augustss 		ii->stdend = dataend;
   3014         1.7  augustss #ifdef DIAGNOSTIC
   3015        1.70  augustss 		if (!ii->isdone) {
   3016        1.70  augustss 			printf("uhci_device_intr_done: not done, ii=%p\n", ii);
   3017        1.70  augustss 		}
   3018         1.7  augustss 		ii->isdone = 0;
   3019         1.7  augustss #endif
   3020         1.1  augustss 		for (i = 0; i < npoll; i++) {
   3021         1.1  augustss 			sqh = upipe->u.intr.qhs[i];
   3022        1.55  augustss 			sqh->elink = data;
   3023       1.121  augustss 			sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD);
   3024       1.223    bouyer 			usb_syncmem(&sqh->dma,
   3025       1.223    bouyer 			    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   3026       1.223    bouyer 			    sizeof(sqh->qh.qh_elink),
   3027       1.223    bouyer 			    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   3028         1.1  augustss 		}
   3029   1.264.4.7     skrll 		xfer->ux_status = USBD_IN_PROGRESS;
   3030        1.92  augustss 		/* The ii is already on the examined list, just leave it. */
   3031         1.1  augustss 	} else {
   3032        1.92  augustss 		DPRINTFN(5,("uhci_device_intr_done: removing\n"));
   3033       1.169  augustss 		if (uhci_active_intr_info(ii))
   3034       1.169  augustss 			uhci_del_intr_info(ii);
   3035         1.1  augustss 	}
   3036         1.1  augustss }
   3037         1.1  augustss 
   3038         1.1  augustss /* Deallocate request data structures */
   3039         1.1  augustss void
   3040       1.119  augustss uhci_device_ctrl_done(usbd_xfer_handle xfer)
   3041         1.1  augustss {
   3042        1.92  augustss 	uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
   3043         1.1  augustss 	uhci_softc_t *sc = ii->sc;
   3044   1.264.4.7     skrll 	struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
   3045   1.264.4.7     skrll 	int len = UGETW(xfer->ux_request.wLength);
   3046   1.264.4.7     skrll 	int isread = (xfer->ux_request.bmRequestType & UT_READ);
   3047         1.1  augustss 
   3048   1.264.4.7     skrll 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
   3049       1.248       mrg 
   3050         1.7  augustss #ifdef DIAGNOSTIC
   3051   1.264.4.7     skrll 	if (!(xfer->ux_rqflags & URQ_REQUEST))
   3052       1.173      gson 		panic("uhci_device_ctrl_done: not a request");
   3053         1.7  augustss #endif
   3054         1.1  augustss 
   3055       1.169  augustss 	if (!uhci_active_intr_info(ii))
   3056       1.169  augustss 		return;
   3057       1.169  augustss 
   3058        1.92  augustss 	uhci_del_intr_info(ii);	/* remove from active list */
   3059         1.1  augustss 
   3060   1.264.4.7     skrll 	if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW)
   3061       1.123  augustss 		uhci_remove_ls_ctrl(sc, upipe->u.ctl.sqh);
   3062       1.123  augustss 	else
   3063       1.123  augustss 		uhci_remove_hs_ctrl(sc, upipe->u.ctl.sqh);
   3064         1.1  augustss 
   3065        1.49  augustss 	if (upipe->u.ctl.length != 0)
   3066        1.42  augustss 		uhci_free_std_chain(sc, ii->stdstart->link.std, ii->stdend);
   3067        1.49  augustss 
   3068       1.223    bouyer 	if (len) {
   3069   1.264.4.7     skrll 		usb_syncmem(&xfer->ux_dmabuf, 0, len,
   3070       1.223    bouyer 		    isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
   3071       1.223    bouyer 	}
   3072       1.223    bouyer 	usb_syncmem(&upipe->u.ctl.reqdma, 0,
   3073       1.223    bouyer 	    sizeof(usb_device_request_t),  BUS_DMASYNC_POSTWRITE);
   3074       1.223    bouyer 
   3075   1.264.4.7     skrll 	DPRINTFN(5, ("uhci_device_ctrl_done: length=%d\n", xfer->ux_actlen));
   3076         1.1  augustss }
   3077         1.1  augustss 
   3078         1.1  augustss /* Deallocate request data structures */
   3079         1.1  augustss void
   3080       1.119  augustss uhci_device_bulk_done(usbd_xfer_handle xfer)
   3081         1.1  augustss {
   3082        1.92  augustss 	uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
   3083         1.1  augustss 	uhci_softc_t *sc = ii->sc;
   3084   1.264.4.7     skrll 	struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
   3085       1.169  augustss 
   3086       1.173      gson 	DPRINTFN(5,("uhci_device_bulk_done: xfer=%p ii=%p sc=%p upipe=%p\n",
   3087       1.169  augustss 		    xfer, ii, sc, upipe));
   3088       1.169  augustss 
   3089       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   3090       1.248       mrg 
   3091       1.169  augustss 	if (!uhci_active_intr_info(ii))
   3092       1.169  augustss 		return;
   3093         1.1  augustss 
   3094        1.92  augustss 	uhci_del_intr_info(ii);	/* remove from active list */
   3095         1.1  augustss 
   3096         1.1  augustss 	uhci_remove_bulk(sc, upipe->u.bulk.sqh);
   3097        1.32  augustss 
   3098       1.149  augustss 	uhci_free_std_chain(sc, ii->stdstart, NULL);
   3099        1.32  augustss 
   3100   1.264.4.7     skrll 	DPRINTFN(5, ("uhci_device_bulk_done: length=%d\n", xfer->ux_actlen));
   3101         1.1  augustss }
   3102         1.1  augustss 
   3103         1.1  augustss /* Add interrupt QH, called with vflock. */
   3104         1.1  augustss void
   3105       1.119  augustss uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   3106         1.1  augustss {
   3107        1.92  augustss 	struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos];
   3108        1.42  augustss 	uhci_soft_qh_t *eqh;
   3109         1.1  augustss 
   3110        1.92  augustss 	DPRINTFN(4, ("uhci_add_intr: n=%d sqh=%p\n", sqh->pos, sqh));
   3111        1.92  augustss 
   3112        1.42  augustss 	eqh = vf->eqh;
   3113       1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   3114       1.223    bouyer 	    sizeof(eqh->qh.qh_hlink),
   3115       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE);
   3116        1.42  augustss 	sqh->hlink       = eqh->hlink;
   3117        1.42  augustss 	sqh->qh.qh_hlink = eqh->qh.qh_hlink;
   3118       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
   3119       1.223    bouyer 	    sizeof(sqh->qh.qh_hlink),
   3120       1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   3121        1.42  augustss 	eqh->hlink       = sqh;
   3122       1.121  augustss 	eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
   3123       1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   3124       1.223    bouyer 	    sizeof(eqh->qh.qh_hlink),
   3125       1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   3126         1.1  augustss 	vf->eqh = sqh;
   3127         1.1  augustss 	vf->bandwidth++;
   3128         1.1  augustss }
   3129         1.1  augustss 
   3130       1.119  augustss /* Remove interrupt QH. */
   3131         1.1  augustss void
   3132       1.119  augustss uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   3133         1.1  augustss {
   3134        1.92  augustss 	struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos];
   3135         1.1  augustss 	uhci_soft_qh_t *pqh;
   3136         1.1  augustss 
   3137        1.92  augustss 	DPRINTFN(4, ("uhci_remove_intr: n=%d sqh=%p\n", sqh->pos, sqh));
   3138         1.1  augustss 
   3139       1.124  augustss 	/* See comment in uhci_remove_ctrl() */
   3140       1.223    bouyer 
   3141       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
   3142       1.223    bouyer 	    sizeof(sqh->qh.qh_elink),
   3143       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   3144       1.124  augustss 	if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) {
   3145       1.124  augustss 		sqh->qh.qh_elink = htole32(UHCI_PTR_T);
   3146       1.223    bouyer 		usb_syncmem(&sqh->dma,
   3147       1.223    bouyer 		    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   3148       1.223    bouyer 		    sizeof(sqh->qh.qh_elink),
   3149       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   3150       1.124  augustss 		delay(UHCI_QH_REMOVE_DELAY);
   3151       1.124  augustss 	}
   3152       1.124  augustss 
   3153        1.92  augustss 	pqh = uhci_find_prev_qh(vf->hqh, sqh);
   3154       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
   3155       1.223    bouyer 	    sizeof(sqh->qh.qh_hlink),
   3156       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   3157        1.42  augustss 	pqh->hlink       = sqh->hlink;
   3158        1.42  augustss 	pqh->qh.qh_hlink = sqh->qh.qh_hlink;
   3159       1.223    bouyer 	usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
   3160       1.223    bouyer 	    sizeof(pqh->qh.qh_hlink),
   3161       1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   3162       1.124  augustss 	delay(UHCI_QH_REMOVE_DELAY);
   3163         1.1  augustss 	if (vf->eqh == sqh)
   3164         1.1  augustss 		vf->eqh = pqh;
   3165         1.1  augustss 	vf->bandwidth--;
   3166         1.1  augustss }
   3167         1.1  augustss 
   3168         1.1  augustss usbd_status
   3169       1.119  augustss uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival)
   3170         1.1  augustss {
   3171         1.1  augustss 	uhci_soft_qh_t *sqh;
   3172       1.248       mrg 	int i, npoll;
   3173         1.1  augustss 	u_int bestbw, bw, bestoffs, offs;
   3174         1.1  augustss 
   3175       1.173      gson 	DPRINTFN(2, ("uhci_device_setintr: pipe=%p\n", upipe));
   3176         1.1  augustss 	if (ival == 0) {
   3177       1.173      gson 		printf("uhci_device_setintr: 0 interval\n");
   3178  1.264.4.13     skrll 		return USBD_INVAL;
   3179         1.1  augustss 	}
   3180         1.1  augustss 
   3181         1.1  augustss 	if (ival > UHCI_VFRAMELIST_COUNT)
   3182         1.1  augustss 		ival = UHCI_VFRAMELIST_COUNT;
   3183         1.1  augustss 	npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival;
   3184       1.173      gson 	DPRINTFN(2, ("uhci_device_setintr: ival=%d npoll=%d\n", ival, npoll));
   3185         1.1  augustss 
   3186         1.1  augustss 	upipe->u.intr.npoll = npoll;
   3187       1.152  augustss 	upipe->u.intr.qhs =
   3188       1.248       mrg 		kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP);
   3189       1.248       mrg 	if (upipe->u.intr.qhs == NULL)
   3190       1.248       mrg 		return USBD_NOMEM;
   3191         1.1  augustss 
   3192       1.152  augustss 	/*
   3193         1.1  augustss 	 * Figure out which offset in the schedule that has most
   3194         1.1  augustss 	 * bandwidth left over.
   3195         1.1  augustss 	 */
   3196         1.1  augustss #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1))
   3197         1.1  augustss 	for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) {
   3198         1.1  augustss 		for (bw = i = 0; i < npoll; i++)
   3199         1.1  augustss 			bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth;
   3200         1.1  augustss 		if (bw < bestbw) {
   3201         1.1  augustss 			bestbw = bw;
   3202         1.1  augustss 			bestoffs = offs;
   3203         1.1  augustss 		}
   3204         1.1  augustss 	}
   3205       1.173      gson 	DPRINTFN(1, ("uhci_device_setintr: bw=%d offs=%d\n", bestbw, bestoffs));
   3206         1.1  augustss 
   3207       1.248       mrg 	mutex_enter(&sc->sc_lock);
   3208         1.1  augustss 	for(i = 0; i < npoll; i++) {
   3209         1.1  augustss 		upipe->u.intr.qhs[i] = sqh = uhci_alloc_sqh(sc);
   3210       1.121  augustss 		sqh->elink = NULL;
   3211        1.88   tsutsui 		sqh->qh.qh_elink = htole32(UHCI_PTR_T);
   3212       1.223    bouyer 		usb_syncmem(&sqh->dma,
   3213       1.223    bouyer 		    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   3214       1.223    bouyer 		    sizeof(sqh->qh.qh_elink),
   3215       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   3216         1.1  augustss 		sqh->pos = MOD(i * ival + bestoffs);
   3217         1.1  augustss 	}
   3218         1.1  augustss #undef MOD
   3219         1.1  augustss 
   3220         1.1  augustss 	/* Enter QHs into the controller data structures. */
   3221         1.1  augustss 	for(i = 0; i < npoll; i++)
   3222        1.92  augustss 		uhci_add_intr(sc, upipe->u.intr.qhs[i]);
   3223       1.248       mrg 	mutex_exit(&sc->sc_lock);
   3224         1.1  augustss 
   3225       1.173      gson 	DPRINTFN(5, ("uhci_device_setintr: returns %p\n", upipe));
   3226  1.264.4.13     skrll 	return USBD_NORMAL_COMPLETION;
   3227         1.1  augustss }
   3228         1.1  augustss 
   3229         1.1  augustss /* Open a new pipe. */
   3230         1.1  augustss usbd_status
   3231       1.119  augustss uhci_open(usbd_pipe_handle pipe)
   3232         1.1  augustss {
   3233   1.264.4.7     skrll 	uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv;
   3234  1.264.4.12     skrll 	struct usbd_bus *bus = pipe->up_dev->ud_bus;
   3235         1.1  augustss 	struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;
   3236   1.264.4.7     skrll 	usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc;
   3237       1.248       mrg 	usbd_status err = USBD_NOMEM;
   3238        1.79  augustss 	int ival;
   3239         1.1  augustss 
   3240         1.1  augustss 	DPRINTFN(1, ("uhci_open: pipe=%p, addr=%d, endpt=%d (%d)\n",
   3241   1.264.4.7     skrll 		     pipe, pipe->up_dev->ud_addr,
   3242  1.264.4.12     skrll 		     ed->bEndpointAddress, bus->ub_rhaddr));
   3243        1.92  augustss 
   3244       1.248       mrg 	if (sc->sc_dying)
   3245       1.248       mrg 		return USBD_IOERROR;
   3246       1.248       mrg 
   3247        1.92  augustss 	upipe->aborting = 0;
   3248       1.236  drochner 	/* toggle state needed for bulk endpoints */
   3249   1.264.4.7     skrll 	upipe->nexttoggle = pipe->up_endpoint->ue_toggle;
   3250        1.92  augustss 
   3251  1.264.4.12     skrll 	if (pipe->up_dev->ud_addr == bus->ub_rhaddr) {
   3252         1.1  augustss 		switch (ed->bEndpointAddress) {
   3253         1.1  augustss 		case USB_CONTROL_ENDPOINT:
   3254  1.264.4.12     skrll 			pipe->up_methods = &roothub_ctrl_methods;
   3255         1.1  augustss 			break;
   3256  1.264.4.12     skrll 		case UE_DIR_IN | USBROOTHUB_INTR_ENDPT:
   3257   1.264.4.7     skrll 			pipe->up_methods = &uhci_root_intr_methods;
   3258         1.1  augustss 			break;
   3259         1.1  augustss 		default:
   3260  1.264.4.13     skrll 			return USBD_INVAL;
   3261         1.1  augustss 		}
   3262         1.1  augustss 	} else {
   3263         1.1  augustss 		switch (ed->bmAttributes & UE_XFERTYPE) {
   3264         1.1  augustss 		case UE_CONTROL:
   3265   1.264.4.7     skrll 			pipe->up_methods = &uhci_device_ctrl_methods;
   3266         1.1  augustss 			upipe->u.ctl.sqh = uhci_alloc_sqh(sc);
   3267        1.63  augustss 			if (upipe->u.ctl.sqh == NULL)
   3268         1.5  augustss 				goto bad;
   3269         1.1  augustss 			upipe->u.ctl.setup = uhci_alloc_std(sc);
   3270        1.63  augustss 			if (upipe->u.ctl.setup == NULL) {
   3271         1.5  augustss 				uhci_free_sqh(sc, upipe->u.ctl.sqh);
   3272         1.5  augustss 				goto bad;
   3273         1.5  augustss 			}
   3274         1.1  augustss 			upipe->u.ctl.stat = uhci_alloc_std(sc);
   3275        1.63  augustss 			if (upipe->u.ctl.stat == NULL) {
   3276         1.5  augustss 				uhci_free_sqh(sc, upipe->u.ctl.sqh);
   3277         1.5  augustss 				uhci_free_std(sc, upipe->u.ctl.setup);
   3278         1.5  augustss 				goto bad;
   3279         1.5  augustss 			}
   3280       1.152  augustss 			err = usb_allocmem(&sc->sc_bus,
   3281       1.152  augustss 				  sizeof(usb_device_request_t),
   3282        1.63  augustss 				  0, &upipe->u.ctl.reqdma);
   3283        1.63  augustss 			if (err) {
   3284         1.5  augustss 				uhci_free_sqh(sc, upipe->u.ctl.sqh);
   3285         1.5  augustss 				uhci_free_std(sc, upipe->u.ctl.setup);
   3286         1.5  augustss 				uhci_free_std(sc, upipe->u.ctl.stat);
   3287         1.5  augustss 				goto bad;
   3288         1.5  augustss 			}
   3289         1.1  augustss 			break;
   3290         1.1  augustss 		case UE_INTERRUPT:
   3291   1.264.4.7     skrll 			pipe->up_methods = &uhci_device_intr_methods;
   3292   1.264.4.7     skrll 			ival = pipe->up_interval;
   3293        1.79  augustss 			if (ival == USBD_DEFAULT_INTERVAL)
   3294        1.79  augustss 				ival = ed->bInterval;
   3295  1.264.4.13     skrll 			return uhci_device_setintr(sc, upipe, ival);
   3296         1.1  augustss 		case UE_ISOCHRONOUS:
   3297   1.264.4.7     skrll 			pipe->up_methods = &uhci_device_isoc_methods;
   3298  1.264.4.13     skrll 			return uhci_setup_isoc(pipe);
   3299         1.1  augustss 		case UE_BULK:
   3300   1.264.4.7     skrll 			pipe->up_methods = &uhci_device_bulk_methods;
   3301         1.1  augustss 			upipe->u.bulk.sqh = uhci_alloc_sqh(sc);
   3302        1.63  augustss 			if (upipe->u.bulk.sqh == NULL)
   3303         1.5  augustss 				goto bad;
   3304         1.1  augustss 			break;
   3305         1.1  augustss 		}
   3306         1.1  augustss 	}
   3307  1.264.4.13     skrll 	return USBD_NORMAL_COMPLETION;
   3308         1.5  augustss 
   3309         1.5  augustss  bad:
   3310       1.248       mrg 	return USBD_NOMEM;
   3311         1.1  augustss }
   3312         1.1  augustss 
   3313         1.1  augustss /*
   3314         1.1  augustss  * Data structures and routines to emulate the root hub.
   3315         1.1  augustss  */
   3316         1.1  augustss /*
   3317       1.166   dsainty  * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also
   3318       1.166   dsainty  * enables the port, and also states that SET_FEATURE(PORT_ENABLE)
   3319       1.166   dsainty  * should not be used by the USB subsystem.  As we cannot issue a
   3320       1.166   dsainty  * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port
   3321       1.166   dsainty  * will be enabled as part of the reset.
   3322       1.166   dsainty  *
   3323       1.166   dsainty  * On the VT83C572, the port cannot be successfully enabled until the
   3324       1.166   dsainty  * outstanding "port enable change" and "connection status change"
   3325       1.166   dsainty  * events have been reset.
   3326       1.166   dsainty  */
   3327       1.166   dsainty Static usbd_status
   3328       1.166   dsainty uhci_portreset(uhci_softc_t *sc, int index)
   3329       1.166   dsainty {
   3330       1.166   dsainty 	int lim, port, x;
   3331       1.166   dsainty 
   3332       1.166   dsainty 	if (index == 1)
   3333       1.166   dsainty 		port = UHCI_PORTSC1;
   3334       1.166   dsainty 	else if (index == 2)
   3335       1.166   dsainty 		port = UHCI_PORTSC2;
   3336       1.166   dsainty 	else
   3337  1.264.4.13     skrll 		return USBD_IOERROR;
   3338       1.166   dsainty 
   3339       1.166   dsainty 	x = URWMASK(UREAD2(sc, port));
   3340       1.166   dsainty 	UWRITE2(sc, port, x | UHCI_PORTSC_PR);
   3341       1.166   dsainty 
   3342       1.166   dsainty 	usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY);
   3343       1.166   dsainty 
   3344       1.166   dsainty 	DPRINTFN(3,("uhci port %d reset, status0 = 0x%04x\n",
   3345       1.166   dsainty 		    index, UREAD2(sc, port)));
   3346       1.166   dsainty 
   3347       1.166   dsainty 	x = URWMASK(UREAD2(sc, port));
   3348       1.222  drochner 	UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP));
   3349       1.166   dsainty 
   3350       1.166   dsainty 	delay(100);
   3351       1.166   dsainty 
   3352       1.166   dsainty 	DPRINTFN(3,("uhci port %d reset, status1 = 0x%04x\n",
   3353       1.166   dsainty 		    index, UREAD2(sc, port)));
   3354       1.166   dsainty 
   3355       1.166   dsainty 	x = URWMASK(UREAD2(sc, port));
   3356       1.166   dsainty 	UWRITE2(sc, port, x  | UHCI_PORTSC_PE);
   3357       1.166   dsainty 
   3358       1.166   dsainty 	for (lim = 10; --lim > 0;) {
   3359       1.166   dsainty 		usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY);
   3360       1.166   dsainty 
   3361       1.166   dsainty 		x = UREAD2(sc, port);
   3362       1.166   dsainty 
   3363       1.166   dsainty 		DPRINTFN(3,("uhci port %d iteration %u, status = 0x%04x\n",
   3364       1.166   dsainty 			    index, lim, x));
   3365       1.166   dsainty 
   3366       1.166   dsainty 		if (!(x & UHCI_PORTSC_CCS)) {
   3367       1.166   dsainty 			/*
   3368       1.166   dsainty 			 * No device is connected (or was disconnected
   3369       1.166   dsainty 			 * during reset).  Consider the port reset.
   3370       1.166   dsainty 			 * The delay must be long enough to ensure on
   3371       1.166   dsainty 			 * the initial iteration that the device
   3372       1.166   dsainty 			 * connection will have been registered.  50ms
   3373       1.166   dsainty 			 * appears to be sufficient, but 20ms is not.
   3374       1.166   dsainty 			 */
   3375       1.166   dsainty 			DPRINTFN(3,("uhci port %d loop %u, device detached\n",
   3376       1.166   dsainty 				    index, lim));
   3377       1.166   dsainty 			break;
   3378       1.166   dsainty 		}
   3379       1.166   dsainty 
   3380       1.166   dsainty 		if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) {
   3381       1.166   dsainty 			/*
   3382       1.166   dsainty 			 * Port enabled changed and/or connection
   3383       1.166   dsainty 			 * status changed were set.  Reset either or
   3384       1.166   dsainty 			 * both raised flags (by writing a 1 to that
   3385       1.166   dsainty 			 * bit), and wait again for state to settle.
   3386       1.166   dsainty 			 */
   3387       1.166   dsainty 			UWRITE2(sc, port, URWMASK(x) |
   3388       1.166   dsainty 				(x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)));
   3389       1.166   dsainty 			continue;
   3390       1.166   dsainty 		}
   3391       1.166   dsainty 
   3392       1.166   dsainty 		if (x & UHCI_PORTSC_PE)
   3393       1.166   dsainty 			/* Port is enabled */
   3394       1.166   dsainty 			break;
   3395       1.166   dsainty 
   3396       1.166   dsainty 		UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE);
   3397       1.166   dsainty 	}
   3398       1.166   dsainty 
   3399       1.166   dsainty 	DPRINTFN(3,("uhci port %d reset, status2 = 0x%04x\n",
   3400       1.166   dsainty 		    index, UREAD2(sc, port)));
   3401       1.166   dsainty 
   3402       1.166   dsainty 	if (lim <= 0) {
   3403       1.166   dsainty 		DPRINTFN(1,("uhci port %d reset timed out\n", index));
   3404  1.264.4.13     skrll 		return USBD_TIMEOUT;
   3405       1.166   dsainty 	}
   3406       1.184     perry 
   3407       1.166   dsainty 	sc->sc_isreset = 1;
   3408  1.264.4.13     skrll 	return USBD_NORMAL_COMPLETION;
   3409       1.166   dsainty }
   3410       1.166   dsainty 
   3411  1.264.4.12     skrll Static int
   3412  1.264.4.12     skrll uhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req,
   3413  1.264.4.12     skrll     void *buf, int buflen)
   3414         1.1  augustss {
   3415  1.264.4.12     skrll 	uhci_softc_t *sc = bus->ub_hcpriv;
   3416         1.1  augustss 	int port, x;
   3417  1.264.4.12     skrll 	int status, change, totlen = 0;
   3418  1.264.4.12     skrll 	uint16_t len, value, index;
   3419         1.1  augustss 	usb_port_status_t ps;
   3420        1.63  augustss 	usbd_status err;
   3421         1.1  augustss 
   3422        1.82  augustss 	if (sc->sc_dying)
   3423  1.264.4.12     skrll 		return -1;
   3424         1.1  augustss 
   3425  1.264.4.12     skrll 	DPRINTFN(2,("%s: type=0x%02x request=%02x\n", __func__,
   3426  1.264.4.12     skrll 	    req->bmRequestType, req->bRequest));
   3427         1.1  augustss 
   3428         1.1  augustss 	len = UGETW(req->wLength);
   3429         1.1  augustss 	value = UGETW(req->wValue);
   3430         1.1  augustss 	index = UGETW(req->wIndex);
   3431        1.49  augustss 
   3432         1.1  augustss #define C(x,y) ((x) | ((y) << 8))
   3433  1.264.4.12     skrll 	switch (C(req->bRequest, req->bmRequestType)) {
   3434         1.1  augustss 	case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
   3435  1.264.4.12     skrll 		DPRINTFN(2,("%s: wValue=0x%04x\n", __func__, value));
   3436       1.195  christos 		if (len == 0)
   3437       1.195  christos 			break;
   3438  1.264.4.12     skrll 		switch (value) {
   3439  1.264.4.12     skrll 		case C(0, UDESC_DEVICE): {
   3440  1.264.4.12     skrll 			usb_device_descriptor_t devd;
   3441  1.264.4.12     skrll 
   3442  1.264.4.12     skrll 			totlen = min(buflen, sizeof(devd));
   3443  1.264.4.12     skrll 			memcpy(&devd, buf, totlen);
   3444  1.264.4.12     skrll 			USETW(devd.idVendor, sc->sc_id_vendor);
   3445  1.264.4.12     skrll 			memcpy(buf, &devd, totlen);
   3446         1.1  augustss 			break;
   3447  1.264.4.12     skrll 		}
   3448  1.264.4.12     skrll 		case C(1, UDESC_STRING):
   3449       1.213  drochner #define sd ((usb_string_descriptor_t *)buf)
   3450  1.264.4.12     skrll 			/* Vendor */
   3451  1.264.4.12     skrll 			totlen = usb_makestrdesc(sd, len, sc->sc_vendor);
   3452  1.264.4.12     skrll 			break;
   3453  1.264.4.12     skrll 		case C(2, UDESC_STRING):
   3454  1.264.4.12     skrll 			/* Product */
   3455  1.264.4.12     skrll 			totlen = usb_makestrdesc(sd, len, "UHCI root hub");
   3456         1.1  augustss 			break;
   3457  1.264.4.12     skrll #undef sd
   3458         1.1  augustss 		default:
   3459  1.264.4.12     skrll 			/* default from usbroothub */
   3460  1.264.4.12     skrll 			return buflen;
   3461         1.1  augustss 		}
   3462         1.1  augustss 		break;
   3463  1.264.4.12     skrll 
   3464         1.1  augustss 	/* Hub requests */
   3465         1.1  augustss 	case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
   3466         1.1  augustss 		break;
   3467         1.1  augustss 	case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
   3468  1.264.4.12     skrll 		DPRINTFN(3, ("%s: UR_CLEAR_PORT_FEATURE "
   3469  1.264.4.12     skrll 			     "port=%d feature=%d\n", __func__,
   3470         1.1  augustss 			     index, value));
   3471         1.1  augustss 		if (index == 1)
   3472         1.1  augustss 			port = UHCI_PORTSC1;
   3473         1.1  augustss 		else if (index == 2)
   3474         1.1  augustss 			port = UHCI_PORTSC2;
   3475         1.1  augustss 		else {
   3476  1.264.4.12     skrll 			return -1;
   3477         1.1  augustss 		}
   3478         1.1  augustss 		switch(value) {
   3479         1.1  augustss 		case UHF_PORT_ENABLE:
   3480       1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3481         1.1  augustss 			UWRITE2(sc, port, x & ~UHCI_PORTSC_PE);
   3482         1.1  augustss 			break;
   3483         1.1  augustss 		case UHF_PORT_SUSPEND:
   3484       1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3485       1.222  drochner 			if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */
   3486       1.222  drochner 				break;
   3487       1.222  drochner 			UWRITE2(sc, port, x | UHCI_PORTSC_RD);
   3488       1.222  drochner 			/* see USB2 spec ch. 7.1.7.7 */
   3489       1.222  drochner 			usb_delay_ms(&sc->sc_bus, 20);
   3490         1.1  augustss 			UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP);
   3491       1.222  drochner 			/* 10ms resume delay must be provided by caller */
   3492         1.1  augustss 			break;
   3493         1.1  augustss 		case UHF_PORT_RESET:
   3494       1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3495         1.1  augustss 			UWRITE2(sc, port, x & ~UHCI_PORTSC_PR);
   3496         1.1  augustss 			break;
   3497         1.1  augustss 		case UHF_C_PORT_CONNECTION:
   3498       1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3499         1.1  augustss 			UWRITE2(sc, port, x | UHCI_PORTSC_CSC);
   3500         1.1  augustss 			break;
   3501         1.1  augustss 		case UHF_C_PORT_ENABLE:
   3502       1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3503         1.1  augustss 			UWRITE2(sc, port, x | UHCI_PORTSC_POEDC);
   3504         1.1  augustss 			break;
   3505         1.1  augustss 		case UHF_C_PORT_OVER_CURRENT:
   3506       1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3507         1.1  augustss 			UWRITE2(sc, port, x | UHCI_PORTSC_OCIC);
   3508         1.1  augustss 			break;
   3509         1.1  augustss 		case UHF_C_PORT_RESET:
   3510         1.1  augustss 			sc->sc_isreset = 0;
   3511  1.264.4.16     skrll 			break;
   3512         1.1  augustss 		case UHF_PORT_CONNECTION:
   3513         1.1  augustss 		case UHF_PORT_OVER_CURRENT:
   3514         1.1  augustss 		case UHF_PORT_POWER:
   3515         1.1  augustss 		case UHF_PORT_LOW_SPEED:
   3516         1.1  augustss 		case UHF_C_PORT_SUSPEND:
   3517         1.1  augustss 		default:
   3518  1.264.4.12     skrll 			return -1;
   3519         1.1  augustss 		}
   3520         1.1  augustss 		break;
   3521         1.1  augustss 	case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER):
   3522         1.1  augustss 		if (index == 1)
   3523         1.1  augustss 			port = UHCI_PORTSC1;
   3524         1.1  augustss 		else if (index == 2)
   3525         1.1  augustss 			port = UHCI_PORTSC2;
   3526         1.1  augustss 		else {
   3527  1.264.4.12     skrll 			return -1;
   3528         1.1  augustss 		}
   3529         1.1  augustss 		if (len > 0) {
   3530   1.264.4.1     skrll 			*(uint8_t *)buf =
   3531         1.1  augustss 				(UREAD2(sc, port) & UHCI_PORTSC_LS) >>
   3532         1.1  augustss 				UHCI_PORTSC_LS_SHIFT;
   3533         1.1  augustss 			totlen = 1;
   3534         1.1  augustss 		}
   3535         1.1  augustss 		break;
   3536         1.1  augustss 	case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
   3537       1.195  christos 		if (len == 0)
   3538       1.195  christos 			break;
   3539       1.177    toshii 		if ((value & 0xff) != 0) {
   3540  1.264.4.12     skrll 			return -1;
   3541         1.1  augustss 		}
   3542  1.264.4.12     skrll 		usb_hub_descriptor_t hubd;
   3543  1.264.4.12     skrll 
   3544  1.264.4.12     skrll 		totlen = min(buflen, sizeof(hubd));
   3545  1.264.4.12     skrll 		memcpy(&hubd, buf, totlen);
   3546  1.264.4.12     skrll 		hubd.bNbrPorts = 2;
   3547  1.264.4.12     skrll 		memcpy(buf, &hubd, totlen);
   3548         1.1  augustss 		break;
   3549         1.1  augustss 	case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
   3550         1.1  augustss 		if (len != 4) {
   3551  1.264.4.12     skrll 			return -1;
   3552         1.1  augustss 		}
   3553         1.1  augustss 		memset(buf, 0, len);
   3554         1.1  augustss 		totlen = len;
   3555         1.1  augustss 		break;
   3556         1.1  augustss 	case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
   3557         1.1  augustss 		if (index == 1)
   3558         1.1  augustss 			port = UHCI_PORTSC1;
   3559         1.1  augustss 		else if (index == 2)
   3560         1.1  augustss 			port = UHCI_PORTSC2;
   3561         1.1  augustss 		else {
   3562  1.264.4.12     skrll 			return -1;
   3563         1.1  augustss 		}
   3564         1.1  augustss 		if (len != 4) {
   3565  1.264.4.12     skrll 			return -1;
   3566         1.1  augustss 		}
   3567         1.1  augustss 		x = UREAD2(sc, port);
   3568         1.1  augustss 		status = change = 0;
   3569       1.142  augustss 		if (x & UHCI_PORTSC_CCS)
   3570         1.1  augustss 			status |= UPS_CURRENT_CONNECT_STATUS;
   3571       1.152  augustss 		if (x & UHCI_PORTSC_CSC)
   3572         1.1  augustss 			change |= UPS_C_CONNECT_STATUS;
   3573       1.152  augustss 		if (x & UHCI_PORTSC_PE)
   3574         1.1  augustss 			status |= UPS_PORT_ENABLED;
   3575       1.152  augustss 		if (x & UHCI_PORTSC_POEDC)
   3576         1.1  augustss 			change |= UPS_C_PORT_ENABLED;
   3577       1.152  augustss 		if (x & UHCI_PORTSC_OCI)
   3578         1.1  augustss 			status |= UPS_OVERCURRENT_INDICATOR;
   3579       1.152  augustss 		if (x & UHCI_PORTSC_OCIC)
   3580         1.1  augustss 			change |= UPS_C_OVERCURRENT_INDICATOR;
   3581       1.152  augustss 		if (x & UHCI_PORTSC_SUSP)
   3582         1.1  augustss 			status |= UPS_SUSPEND;
   3583       1.152  augustss 		if (x & UHCI_PORTSC_LSDA)
   3584         1.1  augustss 			status |= UPS_LOW_SPEED;
   3585         1.1  augustss 		status |= UPS_PORT_POWER;
   3586         1.1  augustss 		if (sc->sc_isreset)
   3587         1.1  augustss 			change |= UPS_C_PORT_RESET;
   3588         1.1  augustss 		USETW(ps.wPortStatus, status);
   3589         1.1  augustss 		USETW(ps.wPortChange, change);
   3590  1.264.4.12     skrll 		totlen = min(len, sizeof(ps));
   3591  1.264.4.12     skrll 		memcpy(buf, &ps, totlen);
   3592         1.1  augustss 		break;
   3593         1.1  augustss 	case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
   3594  1.264.4.12     skrll 		return -1;
   3595         1.1  augustss 	case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
   3596         1.1  augustss 		break;
   3597         1.1  augustss 	case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
   3598         1.1  augustss 		if (index == 1)
   3599         1.1  augustss 			port = UHCI_PORTSC1;
   3600         1.1  augustss 		else if (index == 2)
   3601         1.1  augustss 			port = UHCI_PORTSC2;
   3602         1.1  augustss 		else {
   3603  1.264.4.12     skrll 			return -1;
   3604         1.1  augustss 		}
   3605         1.1  augustss 		switch(value) {
   3606         1.1  augustss 		case UHF_PORT_ENABLE:
   3607       1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3608         1.1  augustss 			UWRITE2(sc, port, x | UHCI_PORTSC_PE);
   3609         1.1  augustss 			break;
   3610         1.1  augustss 		case UHF_PORT_SUSPEND:
   3611       1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3612         1.1  augustss 			UWRITE2(sc, port, x | UHCI_PORTSC_SUSP);
   3613         1.1  augustss 			break;
   3614         1.1  augustss 		case UHF_PORT_RESET:
   3615       1.166   dsainty 			err = uhci_portreset(sc, index);
   3616  1.264.4.12     skrll 			if (err != USBD_NORMAL_COMPLETION)
   3617  1.264.4.12     skrll 				return -1;
   3618  1.264.4.12     skrll 			return 0;
   3619       1.111  augustss 		case UHF_PORT_POWER:
   3620       1.111  augustss 			/* Pretend we turned on power */
   3621  1.264.4.12     skrll 			return 0;
   3622         1.1  augustss 		case UHF_C_PORT_CONNECTION:
   3623         1.1  augustss 		case UHF_C_PORT_ENABLE:
   3624         1.1  augustss 		case UHF_C_PORT_OVER_CURRENT:
   3625         1.1  augustss 		case UHF_PORT_CONNECTION:
   3626         1.1  augustss 		case UHF_PORT_OVER_CURRENT:
   3627         1.1  augustss 		case UHF_PORT_LOW_SPEED:
   3628         1.1  augustss 		case UHF_C_PORT_SUSPEND:
   3629         1.1  augustss 		case UHF_C_PORT_RESET:
   3630         1.1  augustss 		default:
   3631  1.264.4.12     skrll 			return -1;
   3632         1.1  augustss 		}
   3633         1.1  augustss 		break;
   3634         1.1  augustss 	default:
   3635  1.264.4.12     skrll 		/* default from usbroothub */
   3636  1.264.4.12     skrll 		return buflen;
   3637         1.1  augustss 	}
   3638         1.1  augustss 
   3639  1.264.4.12     skrll 	return totlen;
   3640         1.1  augustss }
   3641         1.1  augustss 
   3642         1.1  augustss /* Abort a root interrupt request. */
   3643         1.1  augustss void
   3644       1.119  augustss uhci_root_intr_abort(usbd_xfer_handle xfer)
   3645         1.1  augustss {
   3646   1.264.4.7     skrll 	uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
   3647        1.30  augustss 
   3648       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   3649   1.264.4.7     skrll 	KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
   3650       1.248       mrg 
   3651       1.234    dyoung 	callout_stop(&sc->sc_poll_handle);
   3652        1.96  augustss 	sc->sc_intr_xfer = NULL;
   3653        1.58  augustss 
   3654   1.264.4.7     skrll 	xfer->ux_status = USBD_CANCELLED;
   3655        1.96  augustss #ifdef DIAGNOSTIC
   3656        1.96  augustss 	UXFER(xfer)->iinfo.isdone = 1;
   3657        1.96  augustss #endif
   3658        1.63  augustss 	usb_transfer_complete(xfer);
   3659         1.1  augustss }
   3660         1.1  augustss 
   3661        1.16  augustss usbd_status
   3662       1.119  augustss uhci_root_intr_transfer(usbd_xfer_handle xfer)
   3663        1.16  augustss {
   3664   1.264.4.7     skrll 	uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
   3665        1.63  augustss 	usbd_status err;
   3666        1.16  augustss 
   3667        1.52  augustss 	/* Insert last in queue. */
   3668       1.248       mrg 	mutex_enter(&sc->sc_lock);
   3669        1.63  augustss 	err = usb_insert_transfer(xfer);
   3670       1.248       mrg 	mutex_exit(&sc->sc_lock);
   3671        1.63  augustss 	if (err)
   3672  1.264.4.13     skrll 		return err;
   3673        1.52  augustss 
   3674       1.186     skrll 	/*
   3675       1.186     skrll 	 * Pipe isn't running (otherwise err would be USBD_INPROG),
   3676        1.67  augustss 	 * start first
   3677        1.67  augustss 	 */
   3678  1.264.4.13     skrll 	return uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
   3679        1.16  augustss }
   3680        1.16  augustss 
   3681         1.1  augustss /* Start a transfer on the root interrupt pipe */
   3682         1.1  augustss usbd_status
   3683       1.119  augustss uhci_root_intr_start(usbd_xfer_handle xfer)
   3684         1.1  augustss {
   3685   1.264.4.7     skrll 	usbd_pipe_handle pipe = xfer->ux_pipe;
   3686   1.264.4.7     skrll 	uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv;
   3687       1.174  drochner 	unsigned int ival;
   3688         1.1  augustss 
   3689       1.173      gson 	DPRINTFN(3, ("uhci_root_intr_start: xfer=%p len=%d flags=%d\n",
   3690   1.264.4.7     skrll 		     xfer, xfer->ux_length, xfer->ux_flags));
   3691        1.82  augustss 
   3692        1.82  augustss 	if (sc->sc_dying)
   3693  1.264.4.13     skrll 		return USBD_IOERROR;
   3694         1.1  augustss 
   3695       1.174  drochner 	/* XXX temporary variable needed to avoid gcc3 warning */
   3696   1.264.4.7     skrll 	ival = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval;
   3697       1.174  drochner 	sc->sc_ival = mstohz(ival);
   3698       1.234    dyoung 	callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer);
   3699        1.96  augustss 	sc->sc_intr_xfer = xfer;
   3700  1.264.4.13     skrll 	return USBD_IN_PROGRESS;
   3701         1.1  augustss }
   3702         1.1  augustss 
   3703         1.1  augustss /* Close the root interrupt pipe. */
   3704         1.1  augustss void
   3705       1.119  augustss uhci_root_intr_close(usbd_pipe_handle pipe)
   3706         1.1  augustss {
   3707   1.264.4.7     skrll 	uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv;
   3708        1.30  augustss 
   3709       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   3710       1.248       mrg 
   3711       1.234    dyoung 	callout_stop(&sc->sc_poll_handle);
   3712        1.96  augustss 	sc->sc_intr_xfer = NULL;
   3713         1.1  augustss 	DPRINTF(("uhci_root_intr_close\n"));
   3714         1.1  augustss }
   3715