uhci.c revision 1.264.4.28 1 1.264.4.28 skrll /* $NetBSD: uhci.c,v 1.264.4.28 2015/03/29 11:40:00 skrll Exp $ */
2 1.1 augustss
3 1.1 augustss /*
4 1.248 mrg * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc.
5 1.1 augustss * All rights reserved.
6 1.1 augustss *
7 1.11 augustss * This code is derived from software contributed to The NetBSD Foundation
8 1.113 augustss * by Lennart Augustsson (lennart (at) augustsson.net) at
9 1.248 mrg * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca)
10 1.248 mrg * and Matthew R. Green (mrg (at) eterna.com.au).
11 1.1 augustss *
12 1.1 augustss * Redistribution and use in source and binary forms, with or without
13 1.1 augustss * modification, are permitted provided that the following conditions
14 1.1 augustss * are met:
15 1.1 augustss * 1. Redistributions of source code must retain the above copyright
16 1.1 augustss * notice, this list of conditions and the following disclaimer.
17 1.1 augustss * 2. Redistributions in binary form must reproduce the above copyright
18 1.1 augustss * notice, this list of conditions and the following disclaimer in the
19 1.1 augustss * documentation and/or other materials provided with the distribution.
20 1.1 augustss *
21 1.1 augustss * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22 1.1 augustss * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 1.1 augustss * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 1.1 augustss * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25 1.1 augustss * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 1.1 augustss * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 1.1 augustss * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 1.1 augustss * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 1.1 augustss * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 1.1 augustss * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 1.1 augustss * POSSIBILITY OF SUCH DAMAGE.
32 1.1 augustss */
33 1.1 augustss
34 1.1 augustss /*
35 1.1 augustss * USB Universal Host Controller driver.
36 1.28 augustss * Handles e.g. PIIX3 and PIIX4.
37 1.1 augustss *
38 1.229 uebayasi * UHCI spec: http://www.intel.com/technology/usb/spec.htm
39 1.229 uebayasi * USB spec: http://www.usb.org/developers/docs/
40 1.71 augustss * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf
41 1.71 augustss * ftp://download.intel.com/design/intarch/datashts/29056201.pdf
42 1.1 augustss */
43 1.143 lukem
44 1.143 lukem #include <sys/cdefs.h>
45 1.264.4.28 skrll __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.264.4.28 2015/03/29 11:40:00 skrll Exp $");
46 1.1 augustss
47 1.1 augustss #include <sys/param.h>
48 1.264.4.20 skrll
49 1.264.4.20 skrll #include <sys/bus.h>
50 1.264.4.20 skrll #include <sys/cpu.h>
51 1.264.4.20 skrll #include <sys/device.h>
52 1.1 augustss #include <sys/kernel.h>
53 1.248 mrg #include <sys/kmem.h>
54 1.264.4.20 skrll #include <sys/mutex.h>
55 1.1 augustss #include <sys/proc.h>
56 1.1 augustss #include <sys/queue.h>
57 1.264.4.20 skrll #include <sys/select.h>
58 1.264.4.20 skrll #include <sys/sysctl.h>
59 1.264.4.20 skrll #include <sys/systm.h>
60 1.1 augustss
61 1.39 augustss #include <machine/endian.h>
62 1.7 augustss
63 1.1 augustss #include <dev/usb/usb.h>
64 1.1 augustss #include <dev/usb/usbdi.h>
65 1.1 augustss #include <dev/usb/usbdivar.h>
66 1.7 augustss #include <dev/usb/usb_mem.h>
67 1.1 augustss
68 1.1 augustss #include <dev/usb/uhcireg.h>
69 1.1 augustss #include <dev/usb/uhcivar.h>
70 1.264.4.11 skrll #include <dev/usb/usbroothub.h>
71 1.264.4.21 skrll #include <dev/usb/usbhist.h>
72 1.1 augustss
73 1.125 augustss /* Use bandwidth reclamation for control transfers. Some devices choke on it. */
74 1.125 augustss /*#define UHCI_CTL_LOOP */
75 1.125 augustss
76 1.67 augustss #ifdef UHCI_DEBUG
77 1.92 augustss uhci_softc_t *thesc;
78 1.125 augustss int uhcinoloop = 0;
79 1.59 augustss #endif
80 1.59 augustss
81 1.264.4.21 skrll #ifdef USB_DEBUG
82 1.264.4.21 skrll #ifndef UHCI_DEBUG
83 1.264.4.21 skrll #define uhcidebug 0
84 1.264.4.21 skrll #else
85 1.264.4.21 skrll static int uhcidebug = 0;
86 1.264.4.21 skrll
87 1.264.4.21 skrll SYSCTL_SETUP(sysctl_hw_uhci_setup, "sysctl hw.uhci setup")
88 1.264.4.21 skrll {
89 1.264.4.21 skrll int err;
90 1.264.4.21 skrll const struct sysctlnode *rnode;
91 1.264.4.21 skrll const struct sysctlnode *cnode;
92 1.264.4.21 skrll
93 1.264.4.21 skrll err = sysctl_createv(clog, 0, NULL, &rnode,
94 1.264.4.21 skrll CTLFLAG_PERMANENT, CTLTYPE_NODE, "uhci",
95 1.264.4.21 skrll SYSCTL_DESCR("uhci global controls"),
96 1.264.4.21 skrll NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
97 1.264.4.21 skrll
98 1.264.4.21 skrll if (err)
99 1.264.4.21 skrll goto fail;
100 1.264.4.21 skrll
101 1.264.4.21 skrll /* control debugging printfs */
102 1.264.4.21 skrll err = sysctl_createv(clog, 0, &rnode, &cnode,
103 1.264.4.21 skrll CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
104 1.264.4.21 skrll "debug", SYSCTL_DESCR("Enable debugging output"),
105 1.264.4.21 skrll NULL, 0, &uhcidebug, sizeof(uhcidebug), CTL_CREATE, CTL_EOL);
106 1.264.4.21 skrll if (err)
107 1.264.4.21 skrll goto fail;
108 1.264.4.21 skrll
109 1.264.4.21 skrll return;
110 1.264.4.21 skrll fail:
111 1.264.4.21 skrll aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err);
112 1.264.4.21 skrll }
113 1.264.4.21 skrll
114 1.264.4.21 skrll #endif /* UHCI_DEBUG */
115 1.264.4.21 skrll #endif /* USB_DEBUG */
116 1.264.4.21 skrll
117 1.264.4.27 skrll #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,1,FMT,A,B,C,D)
118 1.264.4.21 skrll #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,N,FMT,A,B,C,D)
119 1.264.4.21 skrll #define UHCIHIST_FUNC() USBHIST_FUNC()
120 1.264.4.21 skrll #define UHCIHIST_CALLED(name) USBHIST_CALLED(uhcidebug)
121 1.264.4.21 skrll
122 1.39 augustss /*
123 1.39 augustss * The UHCI controller is little endian, so on big endian machines
124 1.181 drochner * the data stored in memory needs to be swapped.
125 1.39 augustss */
126 1.39 augustss
127 1.1 augustss struct uhci_pipe {
128 1.1 augustss struct usbd_pipe pipe;
129 1.32 augustss int nexttoggle;
130 1.92 augustss
131 1.92 augustss u_char aborting;
132 1.264.4.25 skrll struct usbd_xfer *abortstart, abortend;
133 1.92 augustss
134 1.1 augustss /* Info needed for different pipe kinds. */
135 1.1 augustss union {
136 1.1 augustss /* Control pipe */
137 1.1 augustss struct {
138 1.1 augustss uhci_soft_qh_t *sqh;
139 1.7 augustss usb_dma_t reqdma;
140 1.16 augustss uhci_soft_td_t *setup, *stat;
141 1.1 augustss u_int length;
142 1.1 augustss } ctl;
143 1.1 augustss /* Interrupt pipe */
144 1.1 augustss struct {
145 1.1 augustss int npoll;
146 1.187 skrll int isread;
147 1.1 augustss uhci_soft_qh_t **qhs;
148 1.1 augustss } intr;
149 1.1 augustss /* Bulk pipe */
150 1.1 augustss struct {
151 1.1 augustss uhci_soft_qh_t *sqh;
152 1.1 augustss u_int length;
153 1.1 augustss int isread;
154 1.1 augustss } bulk;
155 1.16 augustss /* Iso pipe */
156 1.16 augustss struct iso {
157 1.16 augustss uhci_soft_td_t **stds;
158 1.48 augustss int next, inuse;
159 1.16 augustss } iso;
160 1.1 augustss } u;
161 1.1 augustss };
162 1.1 augustss
163 1.142 augustss Static void uhci_globalreset(uhci_softc_t *);
164 1.166 dsainty Static usbd_status uhci_portreset(uhci_softc_t*, int);
165 1.142 augustss Static void uhci_reset(uhci_softc_t *);
166 1.264.4.15 skrll Static usbd_status uhci_run(uhci_softc_t *, int, int);
167 1.123 augustss Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *);
168 1.119 augustss Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *);
169 1.123 augustss Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *);
170 1.119 augustss Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *);
171 1.16 augustss #if 0
172 1.119 augustss Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *,
173 1.119 augustss uhci_intr_info_t *);
174 1.119 augustss Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *);
175 1.16 augustss #endif
176 1.1 augustss
177 1.152 augustss Static void uhci_free_std_chain(uhci_softc_t *,
178 1.119 augustss uhci_soft_td_t *, uhci_soft_td_t *);
179 1.119 augustss Static usbd_status uhci_alloc_std_chain(struct uhci_pipe *,
180 1.264.4.1 skrll uhci_softc_t *, int, int, uint16_t, usb_dma_t *,
181 1.119 augustss uhci_soft_td_t **, uhci_soft_td_t **);
182 1.119 augustss Static void uhci_poll_hub(void *);
183 1.264.4.25 skrll Static void uhci_waitintr(uhci_softc_t *, struct usbd_xfer *);
184 1.119 augustss Static void uhci_check_intr(uhci_softc_t *, uhci_intr_info_t *);
185 1.119 augustss Static void uhci_idone(uhci_intr_info_t *);
186 1.119 augustss
187 1.264.4.25 skrll Static void uhci_abort_xfer(struct usbd_xfer *, usbd_status);
188 1.119 augustss
189 1.119 augustss Static void uhci_timeout(void *);
190 1.153 augustss Static void uhci_timeout_task(void *);
191 1.123 augustss Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *);
192 1.123 augustss Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *);
193 1.119 augustss Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *);
194 1.123 augustss Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *);
195 1.123 augustss Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *);
196 1.119 augustss Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *);
197 1.264.4.15 skrll Static void uhci_add_loop(uhci_softc_t *);
198 1.264.4.15 skrll Static void uhci_rem_loop(uhci_softc_t *);
199 1.119 augustss
200 1.264.4.25 skrll Static usbd_status uhci_setup_isoc(struct usbd_pipe *);
201 1.264.4.25 skrll Static void uhci_device_isoc_enter(struct usbd_xfer *);
202 1.119 augustss
203 1.264.4.25 skrll Static struct usbd_xfer * uhci_allocx(struct usbd_bus *);
204 1.264.4.25 skrll Static void uhci_freex(struct usbd_bus *, struct usbd_xfer *);
205 1.248 mrg Static void uhci_get_lock(struct usbd_bus *, kmutex_t **);
206 1.264.4.13 skrll Static int uhci_roothub_ctrl(struct usbd_bus *,
207 1.264.4.12 skrll usb_device_request_t *, void *, int);
208 1.119 augustss
209 1.264.4.25 skrll Static usbd_status uhci_device_ctrl_transfer(struct usbd_xfer *);
210 1.264.4.25 skrll Static usbd_status uhci_device_ctrl_start(struct usbd_xfer *);
211 1.264.4.25 skrll Static void uhci_device_ctrl_abort(struct usbd_xfer *);
212 1.264.4.25 skrll Static void uhci_device_ctrl_close(struct usbd_pipe *);
213 1.264.4.25 skrll Static void uhci_device_ctrl_done(struct usbd_xfer *);
214 1.264.4.25 skrll
215 1.264.4.25 skrll Static usbd_status uhci_device_intr_transfer(struct usbd_xfer *);
216 1.264.4.25 skrll Static usbd_status uhci_device_intr_start(struct usbd_xfer *);
217 1.264.4.25 skrll Static void uhci_device_intr_abort(struct usbd_xfer *);
218 1.264.4.25 skrll Static void uhci_device_intr_close(struct usbd_pipe *);
219 1.264.4.25 skrll Static void uhci_device_intr_done(struct usbd_xfer *);
220 1.264.4.25 skrll
221 1.264.4.25 skrll Static usbd_status uhci_device_bulk_transfer(struct usbd_xfer *);
222 1.264.4.25 skrll Static usbd_status uhci_device_bulk_start(struct usbd_xfer *);
223 1.264.4.25 skrll Static void uhci_device_bulk_abort(struct usbd_xfer *);
224 1.264.4.25 skrll Static void uhci_device_bulk_close(struct usbd_pipe *);
225 1.264.4.25 skrll Static void uhci_device_bulk_done(struct usbd_xfer *);
226 1.264.4.25 skrll
227 1.264.4.25 skrll Static usbd_status uhci_device_isoc_transfer(struct usbd_xfer *);
228 1.264.4.25 skrll Static usbd_status uhci_device_isoc_start(struct usbd_xfer *);
229 1.264.4.25 skrll Static void uhci_device_isoc_abort(struct usbd_xfer *);
230 1.264.4.25 skrll Static void uhci_device_isoc_close(struct usbd_pipe *);
231 1.264.4.25 skrll Static void uhci_device_isoc_done(struct usbd_xfer *);
232 1.264.4.25 skrll
233 1.264.4.25 skrll Static usbd_status uhci_root_intr_transfer(struct usbd_xfer *);
234 1.264.4.25 skrll Static usbd_status uhci_root_intr_start(struct usbd_xfer *);
235 1.264.4.25 skrll Static void uhci_root_intr_abort(struct usbd_xfer *);
236 1.264.4.25 skrll Static void uhci_root_intr_close(struct usbd_pipe *);
237 1.264.4.25 skrll Static void uhci_root_intr_done(struct usbd_xfer *);
238 1.119 augustss
239 1.264.4.25 skrll Static usbd_status uhci_open(struct usbd_pipe *);
240 1.119 augustss Static void uhci_poll(struct usbd_bus *);
241 1.133 augustss Static void uhci_softintr(void *);
242 1.119 augustss
243 1.264.4.25 skrll Static usbd_status uhci_device_request(struct usbd_xfer *);
244 1.119 augustss
245 1.119 augustss Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *);
246 1.158 augustss Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *);
247 1.264.4.15 skrll Static usbd_status uhci_device_setintr(uhci_softc_t *,
248 1.264.4.15 skrll struct uhci_pipe *, int);
249 1.119 augustss
250 1.264.4.25 skrll Static void uhci_device_clear_toggle(struct usbd_pipe *);
251 1.264.4.25 skrll Static void uhci_noop(struct usbd_pipe *);
252 1.119 augustss
253 1.240 jakllsch static inline uhci_soft_qh_t *uhci_find_prev_qh(uhci_soft_qh_t *,
254 1.119 augustss uhci_soft_qh_t *);
255 1.119 augustss
256 1.119 augustss #ifdef UHCI_DEBUG
257 1.119 augustss Static void uhci_dump_all(uhci_softc_t *);
258 1.119 augustss Static void uhci_dumpregs(uhci_softc_t *);
259 1.119 augustss Static void uhci_dump_qhs(uhci_soft_qh_t *);
260 1.119 augustss Static void uhci_dump_qh(uhci_soft_qh_t *);
261 1.119 augustss Static void uhci_dump_tds(uhci_soft_td_t *);
262 1.119 augustss Static void uhci_dump_td(uhci_soft_td_t *);
263 1.264.4.15 skrll Static void uhci_dump_ii(uhci_intr_info_t *);
264 1.119 augustss void uhci_dump(void);
265 1.1 augustss #endif
266 1.1 augustss
267 1.112 augustss #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \
268 1.112 augustss BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
269 1.112 augustss #define UWRITE1(sc, r, x) \
270 1.165 dsainty do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \
271 1.165 dsainty } while (/*CONSTCOND*/0)
272 1.112 augustss #define UWRITE2(sc, r, x) \
273 1.165 dsainty do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \
274 1.165 dsainty } while (/*CONSTCOND*/0)
275 1.112 augustss #define UWRITE4(sc, r, x) \
276 1.165 dsainty do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \
277 1.165 dsainty } while (/*CONSTCOND*/0)
278 1.196 mrg static __inline uint8_t
279 1.196 mrg UREAD1(uhci_softc_t *sc, bus_size_t r)
280 1.196 mrg {
281 1.196 mrg
282 1.196 mrg UBARR(sc);
283 1.196 mrg return bus_space_read_1(sc->iot, sc->ioh, r);
284 1.196 mrg }
285 1.196 mrg
286 1.196 mrg static __inline uint16_t
287 1.196 mrg UREAD2(uhci_softc_t *sc, bus_size_t r)
288 1.196 mrg {
289 1.196 mrg
290 1.196 mrg UBARR(sc);
291 1.196 mrg return bus_space_read_2(sc->iot, sc->ioh, r);
292 1.196 mrg }
293 1.196 mrg
294 1.260 joerg #ifdef UHCI_DEBUG
295 1.196 mrg static __inline uint32_t
296 1.196 mrg UREAD4(uhci_softc_t *sc, bus_size_t r)
297 1.196 mrg {
298 1.196 mrg
299 1.196 mrg UBARR(sc);
300 1.196 mrg return bus_space_read_4(sc->iot, sc->ioh, r);
301 1.196 mrg }
302 1.260 joerg #endif
303 1.1 augustss
304 1.1 augustss #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd)
305 1.1 augustss #define UHCISTS(sc) UREAD2(sc, UHCI_STS)
306 1.1 augustss
307 1.142 augustss #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */
308 1.1 augustss
309 1.1 augustss #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK)
310 1.1 augustss
311 1.208 drochner const struct usbd_bus_methods uhci_bus_methods = {
312 1.264.4.5 skrll .ubm_open = uhci_open,
313 1.264.4.5 skrll .ubm_softint = uhci_softintr,
314 1.264.4.5 skrll .ubm_dopoll = uhci_poll,
315 1.264.4.5 skrll .ubm_allocx = uhci_allocx,
316 1.264.4.5 skrll .ubm_freex = uhci_freex,
317 1.264.4.5 skrll .ubm_getlock = uhci_get_lock,
318 1.264.4.12 skrll .ubm_rhctrl = uhci_roothub_ctrl,
319 1.1 augustss };
320 1.1 augustss
321 1.208 drochner const struct usbd_pipe_methods uhci_root_intr_methods = {
322 1.264.4.5 skrll .upm_transfer = uhci_root_intr_transfer,
323 1.264.4.5 skrll .upm_start = uhci_root_intr_start,
324 1.264.4.5 skrll .upm_abort = uhci_root_intr_abort,
325 1.264.4.5 skrll .upm_close = uhci_root_intr_close,
326 1.264.4.5 skrll .upm_cleartoggle = uhci_noop,
327 1.264.4.5 skrll .upm_done = uhci_root_intr_done,
328 1.1 augustss };
329 1.1 augustss
330 1.208 drochner const struct usbd_pipe_methods uhci_device_ctrl_methods = {
331 1.264.4.5 skrll .upm_transfer = uhci_device_ctrl_transfer,
332 1.264.4.5 skrll .upm_start = uhci_device_ctrl_start,
333 1.264.4.5 skrll .upm_abort = uhci_device_ctrl_abort,
334 1.264.4.5 skrll .upm_close = uhci_device_ctrl_close,
335 1.264.4.5 skrll .upm_cleartoggle = uhci_noop,
336 1.264.4.5 skrll .upm_done = uhci_device_ctrl_done,
337 1.1 augustss };
338 1.1 augustss
339 1.208 drochner const struct usbd_pipe_methods uhci_device_intr_methods = {
340 1.264.4.5 skrll .upm_transfer = uhci_device_intr_transfer,
341 1.264.4.5 skrll .upm_start = uhci_device_intr_start,
342 1.264.4.5 skrll .upm_abort = uhci_device_intr_abort,
343 1.264.4.5 skrll .upm_close = uhci_device_intr_close,
344 1.264.4.5 skrll .upm_cleartoggle = uhci_device_clear_toggle,
345 1.264.4.5 skrll .upm_done = uhci_device_intr_done,
346 1.1 augustss };
347 1.1 augustss
348 1.208 drochner const struct usbd_pipe_methods uhci_device_bulk_methods = {
349 1.264.4.5 skrll .upm_transfer = uhci_device_bulk_transfer,
350 1.264.4.5 skrll .upm_start = uhci_device_bulk_start,
351 1.264.4.5 skrll .upm_abort = uhci_device_bulk_abort,
352 1.264.4.5 skrll .upm_close = uhci_device_bulk_close,
353 1.264.4.5 skrll .upm_cleartoggle = uhci_device_clear_toggle,
354 1.264.4.5 skrll .upm_done = uhci_device_bulk_done,
355 1.1 augustss };
356 1.1 augustss
357 1.208 drochner const struct usbd_pipe_methods uhci_device_isoc_methods = {
358 1.264.4.5 skrll .upm_transfer = uhci_device_isoc_transfer,
359 1.264.4.5 skrll .upm_start = uhci_device_isoc_start,
360 1.264.4.5 skrll .upm_abort = uhci_device_isoc_abort,
361 1.264.4.5 skrll .upm_close = uhci_device_isoc_close,
362 1.264.4.5 skrll .upm_cleartoggle = uhci_noop,
363 1.264.4.5 skrll .upm_done = uhci_device_isoc_done,
364 1.16 augustss };
365 1.16 augustss
366 1.92 augustss #define uhci_add_intr_info(sc, ii) \
367 1.169 augustss LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ii), list)
368 1.92 augustss #define uhci_del_intr_info(ii) \
369 1.169 augustss do { \
370 1.169 augustss LIST_REMOVE((ii), list); \
371 1.169 augustss (ii)->list.le_prev = NULL; \
372 1.169 augustss } while (0)
373 1.169 augustss #define uhci_active_intr_info(ii) ((ii)->list.le_prev != NULL)
374 1.92 augustss
375 1.240 jakllsch static inline uhci_soft_qh_t *
376 1.119 augustss uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh)
377 1.92 augustss {
378 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
379 1.264.4.21 skrll DPRINTFN(15, "pqh=%p sqh=%p", pqh, sqh, 0, 0);
380 1.92 augustss
381 1.92 augustss for (; pqh->hlink != sqh; pqh = pqh->hlink) {
382 1.152 augustss #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG)
383 1.223 bouyer usb_syncmem(&pqh->dma,
384 1.223 bouyer pqh->offs + offsetof(uhci_qh_t, qh_hlink),
385 1.223 bouyer sizeof(pqh->qh.qh_hlink),
386 1.223 bouyer BUS_DMASYNC_POSTWRITE);
387 1.92 augustss if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) {
388 1.102 augustss printf("uhci_find_prev_qh: QH not found\n");
389 1.264.4.13 skrll return NULL;
390 1.92 augustss }
391 1.92 augustss #endif
392 1.92 augustss }
393 1.264.4.13 skrll return pqh;
394 1.92 augustss }
395 1.92 augustss
396 1.1 augustss void
397 1.142 augustss uhci_globalreset(uhci_softc_t *sc)
398 1.1 augustss {
399 1.1 augustss UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */
400 1.20 augustss usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */
401 1.1 augustss UHCICMD(sc, 0); /* do nothing */
402 1.1 augustss }
403 1.1 augustss
404 1.264.4.14 skrll int
405 1.119 augustss uhci_init(uhci_softc_t *sc)
406 1.1 augustss {
407 1.63 augustss usbd_status err;
408 1.1 augustss int i, j;
409 1.123 augustss uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh;
410 1.1 augustss uhci_soft_td_t *std;
411 1.1 augustss
412 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
413 1.1 augustss
414 1.67 augustss #ifdef UHCI_DEBUG
415 1.92 augustss thesc = sc;
416 1.92 augustss
417 1.1 augustss if (uhcidebug > 2)
418 1.1 augustss uhci_dumpregs(sc);
419 1.1 augustss #endif
420 1.1 augustss
421 1.219 jmcneill sc->sc_suspend = PWR_RESUME;
422 1.219 jmcneill
423 1.1 augustss UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */
424 1.142 augustss uhci_globalreset(sc); /* reset the controller */
425 1.142 augustss uhci_reset(sc);
426 1.24 augustss
427 1.1 augustss /* Allocate and initialize real frame array. */
428 1.152 augustss err = usb_allocmem(&sc->sc_bus,
429 1.63 augustss UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t),
430 1.63 augustss UHCI_FRAMELIST_ALIGN, &sc->sc_dma);
431 1.63 augustss if (err)
432 1.264.4.13 skrll return err;
433 1.159 augustss sc->sc_pframes = KERNADDR(&sc->sc_dma, 0);
434 1.1 augustss UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */
435 1.160 augustss UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/
436 1.1 augustss
437 1.152 augustss /*
438 1.123 augustss * Allocate a TD, inactive, that hangs from the last QH.
439 1.123 augustss * This is to avoid a bug in the PIIX that makes it run berserk
440 1.123 augustss * otherwise.
441 1.123 augustss */
442 1.123 augustss std = uhci_alloc_std(sc);
443 1.123 augustss if (std == NULL)
444 1.264.4.14 skrll return ENOMEM;
445 1.123 augustss std->link.std = NULL;
446 1.123 augustss std->td.td_link = htole32(UHCI_PTR_T);
447 1.123 augustss std->td.td_status = htole32(0); /* inactive */
448 1.123 augustss std->td.td_token = htole32(0);
449 1.123 augustss std->td.td_buffer = htole32(0);
450 1.223 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
451 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
452 1.123 augustss
453 1.123 augustss /* Allocate the dummy QH marking the end and used for looping the QHs.*/
454 1.123 augustss lsqh = uhci_alloc_sqh(sc);
455 1.123 augustss if (lsqh == NULL)
456 1.264.4.14 skrll return ENOMEM;
457 1.123 augustss lsqh->hlink = NULL;
458 1.123 augustss lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */
459 1.123 augustss lsqh->elink = std;
460 1.123 augustss lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD);
461 1.123 augustss sc->sc_last_qh = lsqh;
462 1.223 bouyer usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh),
463 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
464 1.123 augustss
465 1.1 augustss /* Allocate the dummy QH where bulk traffic will be queued. */
466 1.1 augustss bsqh = uhci_alloc_sqh(sc);
467 1.63 augustss if (bsqh == NULL)
468 1.264.4.14 skrll return ENOMEM;
469 1.123 augustss bsqh->hlink = lsqh;
470 1.123 augustss bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH);
471 1.121 augustss bsqh->elink = NULL;
472 1.88 tsutsui bsqh->qh.qh_elink = htole32(UHCI_PTR_T);
473 1.1 augustss sc->sc_bulk_start = sc->sc_bulk_end = bsqh;
474 1.223 bouyer usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh),
475 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
476 1.1 augustss
477 1.123 augustss /* Allocate dummy QH where high speed control traffic will be queued. */
478 1.123 augustss chsqh = uhci_alloc_sqh(sc);
479 1.123 augustss if (chsqh == NULL)
480 1.264.4.14 skrll return ENOMEM;
481 1.123 augustss chsqh->hlink = bsqh;
482 1.123 augustss chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH);
483 1.123 augustss chsqh->elink = NULL;
484 1.123 augustss chsqh->qh.qh_elink = htole32(UHCI_PTR_T);
485 1.123 augustss sc->sc_hctl_start = sc->sc_hctl_end = chsqh;
486 1.223 bouyer usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh),
487 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
488 1.123 augustss
489 1.123 augustss /* Allocate dummy QH where control traffic will be queued. */
490 1.123 augustss clsqh = uhci_alloc_sqh(sc);
491 1.123 augustss if (clsqh == NULL)
492 1.264.4.14 skrll return ENOMEM;
493 1.220 bouyer clsqh->hlink = chsqh;
494 1.123 augustss clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH);
495 1.123 augustss clsqh->elink = NULL;
496 1.123 augustss clsqh->qh.qh_elink = htole32(UHCI_PTR_T);
497 1.123 augustss sc->sc_lctl_start = sc->sc_lctl_end = clsqh;
498 1.223 bouyer usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh),
499 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
500 1.1 augustss
501 1.152 augustss /*
502 1.1 augustss * Make all (virtual) frame list pointers point to the interrupt
503 1.1 augustss * queue heads and the interrupt queue heads at the control
504 1.1 augustss * queue head and point the physical frame list to the virtual.
505 1.1 augustss */
506 1.264.4.24 skrll for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
507 1.1 augustss std = uhci_alloc_std(sc);
508 1.1 augustss sqh = uhci_alloc_sqh(sc);
509 1.67 augustss if (std == NULL || sqh == NULL)
510 1.264.4.13 skrll return USBD_NOMEM;
511 1.42 augustss std->link.sqh = sqh;
512 1.121 augustss std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH);
513 1.88 tsutsui std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */
514 1.88 tsutsui std->td.td_token = htole32(0);
515 1.88 tsutsui std->td.td_buffer = htole32(0);
516 1.223 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
517 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
518 1.123 augustss sqh->hlink = clsqh;
519 1.123 augustss sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH);
520 1.121 augustss sqh->elink = NULL;
521 1.88 tsutsui sqh->qh.qh_elink = htole32(UHCI_PTR_T);
522 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
523 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
524 1.1 augustss sc->sc_vframes[i].htd = std;
525 1.1 augustss sc->sc_vframes[i].etd = std;
526 1.1 augustss sc->sc_vframes[i].hqh = sqh;
527 1.1 augustss sc->sc_vframes[i].eqh = sqh;
528 1.152 augustss for (j = i;
529 1.152 augustss j < UHCI_FRAMELIST_COUNT;
530 1.1 augustss j += UHCI_VFRAMELIST_COUNT)
531 1.88 tsutsui sc->sc_pframes[j] = htole32(std->physaddr);
532 1.1 augustss }
533 1.223 bouyer usb_syncmem(&sc->sc_dma, 0,
534 1.223 bouyer UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t),
535 1.223 bouyer BUS_DMASYNC_PREWRITE);
536 1.223 bouyer
537 1.1 augustss
538 1.1 augustss LIST_INIT(&sc->sc_intrhead);
539 1.1 augustss
540 1.253 christos sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0,
541 1.253 christos "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL);
542 1.76 augustss
543 1.248 mrg callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE);
544 1.248 mrg
545 1.248 mrg mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
546 1.248 mrg mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED);
547 1.248 mrg cv_init(&sc->sc_softwake_cv, "uhciab");
548 1.96 augustss
549 1.1 augustss /* Set up the bus struct. */
550 1.264.4.7 skrll sc->sc_bus.ub_methods = &uhci_bus_methods;
551 1.264.4.7 skrll sc->sc_bus.ub_pipesize = sizeof(struct uhci_pipe);
552 1.264.4.7 skrll sc->sc_bus.ub_usedma = true;
553 1.1 augustss
554 1.190 augustss UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */
555 1.190 augustss
556 1.264.4.27 skrll DPRINTF("Enabling...", 0, 0, 0, 0);
557 1.225 bouyer
558 1.264.4.24 skrll err = uhci_run(sc, 1, 0); /* and here we go... */
559 1.152 augustss UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE |
560 1.1 augustss UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */
561 1.225 bouyer return err;
562 1.53 augustss }
563 1.53 augustss
564 1.53 augustss int
565 1.215 dyoung uhci_activate(device_t self, enum devact act)
566 1.53 augustss {
567 1.215 dyoung struct uhci_softc *sc = device_private(self);
568 1.53 augustss
569 1.53 augustss switch (act) {
570 1.53 augustss case DVACT_DEACTIVATE:
571 1.210 kiyohara sc->sc_dying = 1;
572 1.230 dyoung return 0;
573 1.230 dyoung default:
574 1.230 dyoung return EOPNOTSUPP;
575 1.53 augustss }
576 1.53 augustss }
577 1.53 augustss
578 1.215 dyoung void
579 1.215 dyoung uhci_childdet(device_t self, device_t child)
580 1.215 dyoung {
581 1.215 dyoung struct uhci_softc *sc = device_private(self);
582 1.215 dyoung
583 1.215 dyoung KASSERT(sc->sc_child == child);
584 1.215 dyoung sc->sc_child = NULL;
585 1.215 dyoung }
586 1.215 dyoung
587 1.53 augustss int
588 1.119 augustss uhci_detach(struct uhci_softc *sc, int flags)
589 1.53 augustss {
590 1.53 augustss int rv = 0;
591 1.53 augustss
592 1.53 augustss if (sc->sc_child != NULL)
593 1.53 augustss rv = config_detach(sc->sc_child, flags);
594 1.152 augustss
595 1.53 augustss if (rv != 0)
596 1.264.4.13 skrll return rv;
597 1.53 augustss
598 1.226 ad callout_halt(&sc->sc_poll_handle, NULL);
599 1.226 ad callout_destroy(&sc->sc_poll_handle);
600 1.226 ad
601 1.248 mrg cv_destroy(&sc->sc_softwake_cv);
602 1.248 mrg
603 1.248 mrg mutex_destroy(&sc->sc_lock);
604 1.248 mrg mutex_destroy(&sc->sc_intr_lock);
605 1.248 mrg
606 1.254 christos pool_cache_destroy(sc->sc_xferpool);
607 1.254 christos
608 1.76 augustss /* XXX free other data structures XXX */
609 1.53 augustss
610 1.264.4.13 skrll return rv;
611 1.1 augustss }
612 1.1 augustss
613 1.264.4.25 skrll struct usbd_xfer *
614 1.119 augustss uhci_allocx(struct usbd_bus *bus)
615 1.76 augustss {
616 1.264.4.7 skrll struct uhci_softc *sc = bus->ub_hcpriv;
617 1.264.4.25 skrll struct usbd_xfer *xfer;
618 1.76 augustss
619 1.253 christos xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT);
620 1.92 augustss if (xfer != NULL) {
621 1.253 christos memset(xfer, 0, sizeof(struct uhci_xfer));
622 1.254 christos UXFER(xfer)->iinfo.sc = sc;
623 1.92 augustss #ifdef DIAGNOSTIC
624 1.238 tsutsui UXFER(xfer)->iinfo.isdone = 1;
625 1.264.4.7 skrll xfer->ux_state = XFER_BUSY;
626 1.92 augustss #endif
627 1.92 augustss }
628 1.264.4.13 skrll return xfer;
629 1.76 augustss }
630 1.76 augustss
631 1.76 augustss void
632 1.264.4.25 skrll uhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer)
633 1.76 augustss {
634 1.264.4.7 skrll struct uhci_softc *sc = bus->ub_hcpriv;
635 1.76 augustss
636 1.93 augustss #ifdef DIAGNOSTIC
637 1.264.4.7 skrll if (xfer->ux_state != XFER_BUSY) {
638 1.94 augustss printf("uhci_freex: xfer=%p not busy, 0x%08x\n", xfer,
639 1.264.4.7 skrll xfer->ux_state);
640 1.93 augustss }
641 1.264.4.7 skrll xfer->ux_state = XFER_FREE;
642 1.238 tsutsui if (!UXFER(xfer)->iinfo.isdone) {
643 1.96 augustss printf("uhci_freex: !isdone\n");
644 1.105 augustss }
645 1.93 augustss #endif
646 1.253 christos pool_cache_put(sc->sc_xferpool, xfer);
647 1.48 augustss }
648 1.48 augustss
649 1.248 mrg Static void
650 1.248 mrg uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock)
651 1.248 mrg {
652 1.264.4.7 skrll struct uhci_softc *sc = bus->ub_hcpriv;
653 1.248 mrg
654 1.248 mrg *lock = &sc->sc_lock;
655 1.248 mrg }
656 1.248 mrg
657 1.248 mrg
658 1.72 augustss /*
659 1.212 jmcneill * Handle suspend/resume.
660 1.212 jmcneill *
661 1.212 jmcneill * We need to switch to polling mode here, because this routine is
662 1.212 jmcneill * called from an interrupt context. This is all right since we
663 1.212 jmcneill * are almost suspended anyway.
664 1.72 augustss */
665 1.212 jmcneill bool
666 1.232 dyoung uhci_resume(device_t dv, const pmf_qual_t *qual)
667 1.72 augustss {
668 1.212 jmcneill uhci_softc_t *sc = device_private(dv);
669 1.212 jmcneill int cmd;
670 1.72 augustss
671 1.248 mrg mutex_spin_enter(&sc->sc_intr_lock);
672 1.193 augustss
673 1.212 jmcneill cmd = UREAD2(sc, UHCI_CMD);
674 1.264.4.7 skrll sc->sc_bus.ub_usepolling++;
675 1.214 smb UWRITE2(sc, UHCI_INTR, 0);
676 1.214 smb uhci_globalreset(sc);
677 1.214 smb uhci_reset(sc);
678 1.212 jmcneill if (cmd & UHCI_CMD_RS)
679 1.249 drochner uhci_run(sc, 0, 1);
680 1.212 jmcneill
681 1.212 jmcneill /* restore saved state */
682 1.212 jmcneill UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0));
683 1.212 jmcneill UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum);
684 1.212 jmcneill UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof);
685 1.212 jmcneill
686 1.212 jmcneill UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */
687 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock);
688 1.212 jmcneill UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */
689 1.212 jmcneill UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE |
690 1.212 jmcneill UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE);
691 1.214 smb UHCICMD(sc, UHCI_CMD_MAXP);
692 1.249 drochner uhci_run(sc, 1, 1); /* and start traffic again */
693 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock);
694 1.264.4.7 skrll sc->sc_bus.ub_usepolling--;
695 1.212 jmcneill if (sc->sc_intr_xfer != NULL)
696 1.234 dyoung callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub,
697 1.212 jmcneill sc->sc_intr_xfer);
698 1.212 jmcneill #ifdef UHCI_DEBUG
699 1.212 jmcneill if (uhcidebug > 2)
700 1.212 jmcneill uhci_dumpregs(sc);
701 1.212 jmcneill #endif
702 1.212 jmcneill
703 1.219 jmcneill sc->sc_suspend = PWR_RESUME;
704 1.248 mrg mutex_spin_exit(&sc->sc_intr_lock);
705 1.212 jmcneill
706 1.212 jmcneill return true;
707 1.72 augustss }
708 1.72 augustss
709 1.212 jmcneill bool
710 1.232 dyoung uhci_suspend(device_t dv, const pmf_qual_t *qual)
711 1.30 augustss {
712 1.212 jmcneill uhci_softc_t *sc = device_private(dv);
713 1.30 augustss int cmd;
714 1.30 augustss
715 1.248 mrg mutex_spin_enter(&sc->sc_intr_lock);
716 1.212 jmcneill
717 1.30 augustss cmd = UREAD2(sc, UHCI_CMD);
718 1.30 augustss
719 1.212 jmcneill #ifdef UHCI_DEBUG
720 1.212 jmcneill if (uhcidebug > 2)
721 1.212 jmcneill uhci_dumpregs(sc);
722 1.212 jmcneill #endif
723 1.212 jmcneill if (sc->sc_intr_xfer != NULL)
724 1.234 dyoung callout_stop(&sc->sc_poll_handle);
725 1.219 jmcneill sc->sc_suspend = PWR_SUSPEND;
726 1.264.4.7 skrll sc->sc_bus.ub_usepolling++;
727 1.219 jmcneill
728 1.249 drochner uhci_run(sc, 0, 1); /* stop the controller */
729 1.212 jmcneill cmd &= ~UHCI_CMD_RS;
730 1.212 jmcneill
731 1.212 jmcneill /* save some state if BIOS doesn't */
732 1.212 jmcneill sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM);
733 1.212 jmcneill sc->sc_saved_sof = UREAD1(sc, UHCI_SOF);
734 1.212 jmcneill
735 1.212 jmcneill UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */
736 1.30 augustss
737 1.212 jmcneill UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */
738 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock);
739 1.264.4.7 skrll sc->sc_bus.ub_usepolling--;
740 1.86 augustss
741 1.248 mrg mutex_spin_exit(&sc->sc_intr_lock);
742 1.212 jmcneill
743 1.212 jmcneill return true;
744 1.30 augustss }
745 1.30 augustss
746 1.59 augustss #ifdef UHCI_DEBUG
747 1.101 augustss Static void
748 1.119 augustss uhci_dumpregs(uhci_softc_t *sc)
749 1.1 augustss {
750 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
751 1.264.4.27 skrll DPRINTF("cmd =%04x sts =%04x intr =%04x frnum =%04x",
752 1.264.4.21 skrll UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS),
753 1.264.4.21 skrll UREAD2(sc, UHCI_INTR), UREAD2(sc, UHCI_FRNUM));
754 1.264.4.27 skrll DPRINTF("sof =%04x portsc1=%04x portsc2=%04x flbase=%08x",
755 1.264.4.21 skrll UREAD1(sc, UHCI_SOF), UREAD2(sc, UHCI_PORTSC1),
756 1.264.4.21 skrll UREAD2(sc, UHCI_PORTSC2), UREAD4(sc, UHCI_FLBASEADDR));
757 1.1 augustss }
758 1.1 augustss
759 1.1 augustss void
760 1.119 augustss uhci_dump_td(uhci_soft_td_t *p)
761 1.1 augustss {
762 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
763 1.250 christos
764 1.223 bouyer usb_syncmem(&p->dma, p->offs, sizeof(p->td),
765 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
766 1.264.4.21 skrll
767 1.264.4.27 skrll DPRINTF("TD(%p) at %08x", p, p->physaddr, 0, 0);
768 1.264.4.27 skrll DPRINTF(" link=0x%08x status=0x%08x "
769 1.264.4.21 skrll "token=0x%08x buffer=0x%08x",
770 1.264.4.21 skrll le32toh(p->td.td_link),
771 1.264.4.21 skrll le32toh(p->td.td_status),
772 1.264.4.21 skrll le32toh(p->td.td_token),
773 1.264.4.21 skrll le32toh(p->td.td_buffer));
774 1.264.4.21 skrll
775 1.264.4.27 skrll DPRINTF("bitstuff=%d crcto =%d nak =%d babble =%d",
776 1.264.4.21 skrll !!(le32toh(p->td.td_status) & UHCI_TD_BITSTUFF),
777 1.264.4.21 skrll !!(le32toh(p->td.td_status) & UHCI_TD_CRCTO),
778 1.264.4.21 skrll !!(le32toh(p->td.td_status) & UHCI_TD_NAK),
779 1.264.4.21 skrll !!(le32toh(p->td.td_status) & UHCI_TD_BABBLE));
780 1.264.4.27 skrll DPRINTF("dbuffer =%d stalled =%d active =%d ioc =%d",
781 1.264.4.21 skrll !!(le32toh(p->td.td_status) & UHCI_TD_DBUFFER),
782 1.264.4.21 skrll !!(le32toh(p->td.td_status) & UHCI_TD_STALLED),
783 1.264.4.21 skrll !!(le32toh(p->td.td_status) & UHCI_TD_ACTIVE),
784 1.264.4.21 skrll !!(le32toh(p->td.td_status) & UHCI_TD_IOC));
785 1.264.4.27 skrll DPRINTF("ios =%d ls =%d spd =%d",
786 1.264.4.21 skrll !!(le32toh(p->td.td_status) & UHCI_TD_IOS),
787 1.264.4.21 skrll !!(le32toh(p->td.td_status) & UHCI_TD_LS),
788 1.264.4.21 skrll !!(le32toh(p->td.td_status) & UHCI_TD_SPD), 0);
789 1.264.4.27 skrll DPRINTF("errcnt =%d actlen =%d pid=%02x",
790 1.264.4.21 skrll UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)),
791 1.264.4.21 skrll UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)),
792 1.264.4.21 skrll UHCI_TD_GET_PID(le32toh(p->td.td_token)), 0);
793 1.264.4.27 skrll DPRINTF("addr=%d endpt=%d D=%d maxlen=%d,",
794 1.264.4.21 skrll UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)),
795 1.264.4.21 skrll UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)),
796 1.264.4.21 skrll UHCI_TD_GET_DT(le32toh(p->td.td_token)),
797 1.264.4.21 skrll UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token)));
798 1.1 augustss }
799 1.1 augustss
800 1.1 augustss void
801 1.119 augustss uhci_dump_qh(uhci_soft_qh_t *sqh)
802 1.1 augustss {
803 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
804 1.264.4.21 skrll
805 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
806 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
807 1.264.4.21 skrll
808 1.264.4.27 skrll DPRINTF("QH(%p) at %08x: hlink=%08x elink=%08x", sqh,
809 1.88 tsutsui (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink),
810 1.264.4.21 skrll le32toh(sqh->qh.qh_elink));
811 1.264.4.21 skrll
812 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD);
813 1.1 augustss }
814 1.1 augustss
815 1.13 augustss
816 1.110 augustss #if 1
817 1.1 augustss void
818 1.119 augustss uhci_dump(void)
819 1.1 augustss {
820 1.110 augustss uhci_dump_all(thesc);
821 1.110 augustss }
822 1.110 augustss #endif
823 1.1 augustss
824 1.110 augustss void
825 1.119 augustss uhci_dump_all(uhci_softc_t *sc)
826 1.110 augustss {
827 1.1 augustss uhci_dumpregs(sc);
828 1.110 augustss /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/
829 1.261 skrll uhci_dump_qhs(sc->sc_lctl_start);
830 1.1 augustss }
831 1.1 augustss
832 1.67 augustss
833 1.67 augustss void
834 1.119 augustss uhci_dump_qhs(uhci_soft_qh_t *sqh)
835 1.67 augustss {
836 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
837 1.264.4.21 skrll
838 1.67 augustss uhci_dump_qh(sqh);
839 1.67 augustss
840 1.264.4.18 skrll /*
841 1.264.4.18 skrll * uhci_dump_qhs displays all the QHs and TDs from the given QH onwards
842 1.67 augustss * Traverses sideways first, then down.
843 1.67 augustss *
844 1.67 augustss * QH1
845 1.67 augustss * QH2
846 1.67 augustss * No QH
847 1.67 augustss * TD2.1
848 1.67 augustss * TD2.2
849 1.67 augustss * TD1.1
850 1.67 augustss * etc.
851 1.67 augustss *
852 1.67 augustss * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1.
853 1.67 augustss */
854 1.67 augustss
855 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
856 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
857 1.88 tsutsui if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T))
858 1.67 augustss uhci_dump_qhs(sqh->hlink);
859 1.67 augustss else
860 1.264.4.27 skrll DPRINTF("No QH", 0, 0, 0, 0);
861 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD);
862 1.67 augustss
863 1.88 tsutsui if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T))
864 1.67 augustss uhci_dump_tds(sqh->elink);
865 1.67 augustss else
866 1.264.4.27 skrll DPRINTF("No QH", 0, 0, 0, 0);
867 1.67 augustss }
868 1.67 augustss
869 1.1 augustss void
870 1.119 augustss uhci_dump_tds(uhci_soft_td_t *std)
871 1.1 augustss {
872 1.67 augustss uhci_soft_td_t *td;
873 1.223 bouyer int stop;
874 1.67 augustss
875 1.264.4.24 skrll for (td = std; td != NULL; td = td->link.std) {
876 1.67 augustss uhci_dump_td(td);
877 1.1 augustss
878 1.264.4.18 skrll /*
879 1.264.4.18 skrll * Check whether the link pointer in this TD marks
880 1.67 augustss * the link pointer as end of queue. This avoids
881 1.67 augustss * printing the free list in case the queue/TD has
882 1.67 augustss * already been moved there (seatbelt).
883 1.67 augustss */
884 1.223 bouyer usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link),
885 1.223 bouyer sizeof(td->td.td_link),
886 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
887 1.223 bouyer stop = (le32toh(td->td.td_link) & UHCI_PTR_T ||
888 1.223 bouyer le32toh(td->td.td_link) == 0);
889 1.223 bouyer usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link),
890 1.223 bouyer sizeof(td->td.td_link), BUS_DMASYNC_PREREAD);
891 1.223 bouyer if (stop)
892 1.67 augustss break;
893 1.67 augustss }
894 1.1 augustss }
895 1.92 augustss
896 1.101 augustss Static void
897 1.119 augustss uhci_dump_ii(uhci_intr_info_t *ii)
898 1.92 augustss {
899 1.264.4.25 skrll struct usbd_pipe *pipe;
900 1.95 augustss usb_endpoint_descriptor_t *ed;
901 1.264.4.25 skrll struct usbd_device *dev;
902 1.152 augustss
903 1.98 augustss #ifdef DIAGNOSTIC
904 1.98 augustss #define DONE ii->isdone
905 1.98 augustss #else
906 1.98 augustss #define DONE 0
907 1.98 augustss #endif
908 1.264.4.2 skrll if (ii == NULL) {
909 1.264.4.2 skrll printf("ii NULL\n");
910 1.264.4.2 skrll return;
911 1.264.4.2 skrll }
912 1.264.4.2 skrll if (ii->xfer == NULL) {
913 1.95 augustss printf("ii %p: done=%d xfer=NULL\n",
914 1.98 augustss ii, DONE);
915 1.264.4.2 skrll return;
916 1.264.4.2 skrll }
917 1.264.4.7 skrll pipe = ii->xfer->ux_pipe;
918 1.264.4.2 skrll if (pipe == NULL) {
919 1.95 augustss printf("ii %p: done=%d xfer=%p pipe=NULL\n",
920 1.264.4.2 skrll ii, DONE, ii->xfer);
921 1.264.4.2 skrll return;
922 1.139 augustss }
923 1.264.4.7 skrll if (pipe->up_endpoint == NULL) {
924 1.264.4.7 skrll printf("ii %p: done=%d xfer=%p pipe=%p pipe->up_endpoint=NULL\n",
925 1.139 augustss ii, DONE, ii->xfer, pipe);
926 1.264.4.2 skrll return;
927 1.139 augustss }
928 1.264.4.7 skrll if (pipe->up_dev == NULL) {
929 1.264.4.7 skrll printf("ii %p: done=%d xfer=%p pipe=%p pipe->up_dev=NULL\n",
930 1.139 augustss ii, DONE, ii->xfer, pipe);
931 1.264.4.2 skrll return;
932 1.95 augustss }
933 1.264.4.7 skrll ed = pipe->up_endpoint->ue_edesc;
934 1.264.4.7 skrll dev = pipe->up_dev;
935 1.152 augustss printf("ii %p: done=%d xfer=%p dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n",
936 1.152 augustss ii, DONE, ii->xfer, dev,
937 1.264.4.7 skrll UGETW(dev->ud_ddesc.idVendor),
938 1.264.4.7 skrll UGETW(dev->ud_ddesc.idProduct),
939 1.264.4.7 skrll dev->ud_addr, pipe,
940 1.92 augustss ed->bEndpointAddress, ed->bmAttributes);
941 1.98 augustss #undef DONE
942 1.92 augustss }
943 1.92 augustss
944 1.120 augustss void uhci_dump_iis(struct uhci_softc *sc);
945 1.92 augustss void
946 1.119 augustss uhci_dump_iis(struct uhci_softc *sc)
947 1.92 augustss {
948 1.92 augustss uhci_intr_info_t *ii;
949 1.92 augustss
950 1.92 augustss printf("intr_info list:\n");
951 1.92 augustss for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = LIST_NEXT(ii, list))
952 1.92 augustss uhci_dump_ii(ii);
953 1.92 augustss }
954 1.92 augustss
955 1.120 augustss void iidump(void);
956 1.119 augustss void iidump(void) { uhci_dump_iis(thesc); }
957 1.92 augustss
958 1.1 augustss #endif
959 1.1 augustss
960 1.1 augustss /*
961 1.1 augustss * This routine is executed periodically and simulates interrupts
962 1.1 augustss * from the root controller interrupt pipe for port status change.
963 1.1 augustss */
964 1.1 augustss void
965 1.119 augustss uhci_poll_hub(void *addr)
966 1.1 augustss {
967 1.264.4.25 skrll struct usbd_xfer *xfer = addr;
968 1.264.4.25 skrll struct usbd_pipe *pipe = xfer->ux_pipe;
969 1.227 martin uhci_softc_t *sc;
970 1.1 augustss u_char *p;
971 1.1 augustss
972 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
973 1.1 augustss
974 1.264.4.7 skrll if (__predict_false(pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL))
975 1.228 martin return; /* device has detached */
976 1.264.4.7 skrll sc = pipe->up_dev->ud_bus->ub_hcpriv;
977 1.234 dyoung callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer);
978 1.41 augustss
979 1.264.4.7 skrll p = xfer->ux_buf;
980 1.1 augustss p[0] = 0;
981 1.1 augustss if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC))
982 1.1 augustss p[0] |= 1<<1;
983 1.1 augustss if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC))
984 1.1 augustss p[0] |= 1<<2;
985 1.41 augustss if (p[0] == 0)
986 1.41 augustss /* No change, try again in a while */
987 1.41 augustss return;
988 1.41 augustss
989 1.264.4.7 skrll xfer->ux_actlen = 1;
990 1.264.4.7 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
991 1.248 mrg mutex_enter(&sc->sc_lock);
992 1.63 augustss usb_transfer_complete(xfer);
993 1.248 mrg mutex_exit(&sc->sc_lock);
994 1.41 augustss }
995 1.41 augustss
996 1.41 augustss void
997 1.264.4.25 skrll uhci_root_intr_done(struct usbd_xfer *xfer)
998 1.84 augustss {
999 1.84 augustss }
1000 1.84 augustss
1001 1.123 augustss /*
1002 1.123 augustss * Let the last QH loop back to the high speed control transfer QH.
1003 1.123 augustss * This is what intel calls "bandwidth reclamation" and improves
1004 1.123 augustss * USB performance a lot for some devices.
1005 1.123 augustss * If we are already looping, just count it.
1006 1.123 augustss */
1007 1.1 augustss void
1008 1.264.4.17 skrll uhci_add_loop(uhci_softc_t *sc)
1009 1.264.4.17 skrll {
1010 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1011 1.264.4.25 skrll
1012 1.125 augustss #ifdef UHCI_DEBUG
1013 1.125 augustss if (uhcinoloop)
1014 1.125 augustss return;
1015 1.125 augustss #endif
1016 1.123 augustss if (++sc->sc_loops == 1) {
1017 1.264.4.21 skrll DPRINTFN(5, "add loop", 0, 0, 0, 0);
1018 1.123 augustss /* Note, we don't loop back the soft pointer. */
1019 1.152 augustss sc->sc_last_qh->qh.qh_hlink =
1020 1.123 augustss htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH);
1021 1.223 bouyer usb_syncmem(&sc->sc_last_qh->dma,
1022 1.223 bouyer sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink),
1023 1.223 bouyer sizeof(sc->sc_last_qh->qh.qh_hlink),
1024 1.223 bouyer BUS_DMASYNC_PREWRITE);
1025 1.123 augustss }
1026 1.123 augustss }
1027 1.123 augustss
1028 1.123 augustss void
1029 1.264.4.17 skrll uhci_rem_loop(uhci_softc_t *sc)
1030 1.264.4.17 skrll {
1031 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1032 1.264.4.21 skrll
1033 1.125 augustss #ifdef UHCI_DEBUG
1034 1.125 augustss if (uhcinoloop)
1035 1.125 augustss return;
1036 1.125 augustss #endif
1037 1.123 augustss if (--sc->sc_loops == 0) {
1038 1.264.4.21 skrll DPRINTFN(5, "remove loop", 0, 0, 0, 0);
1039 1.123 augustss sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T);
1040 1.223 bouyer usb_syncmem(&sc->sc_last_qh->dma,
1041 1.223 bouyer sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink),
1042 1.223 bouyer sizeof(sc->sc_last_qh->qh.qh_hlink),
1043 1.223 bouyer BUS_DMASYNC_PREWRITE);
1044 1.123 augustss }
1045 1.123 augustss }
1046 1.123 augustss
1047 1.248 mrg /* Add high speed control QH, called with lock held. */
1048 1.123 augustss void
1049 1.123 augustss uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1050 1.1 augustss {
1051 1.42 augustss uhci_soft_qh_t *eqh;
1052 1.1 augustss
1053 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1054 1.264.4.21 skrll
1055 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
1056 1.248 mrg
1057 1.264.4.21 skrll DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
1058 1.123 augustss eqh = sc->sc_hctl_end;
1059 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1060 1.223 bouyer sizeof(eqh->qh.qh_hlink),
1061 1.223 bouyer BUS_DMASYNC_POSTWRITE);
1062 1.42 augustss sqh->hlink = eqh->hlink;
1063 1.42 augustss sqh->qh.qh_hlink = eqh->qh.qh_hlink;
1064 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1065 1.223 bouyer BUS_DMASYNC_PREWRITE);
1066 1.42 augustss eqh->hlink = sqh;
1067 1.121 augustss eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
1068 1.123 augustss sc->sc_hctl_end = sqh;
1069 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1070 1.223 bouyer sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
1071 1.125 augustss #ifdef UHCI_CTL_LOOP
1072 1.123 augustss uhci_add_loop(sc);
1073 1.125 augustss #endif
1074 1.1 augustss }
1075 1.1 augustss
1076 1.248 mrg /* Remove high speed control QH, called with lock held. */
1077 1.1 augustss void
1078 1.123 augustss uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1079 1.1 augustss {
1080 1.1 augustss uhci_soft_qh_t *pqh;
1081 1.256 tsutsui uint32_t elink;
1082 1.1 augustss
1083 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
1084 1.248 mrg
1085 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1086 1.264.4.21 skrll DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
1087 1.125 augustss #ifdef UHCI_CTL_LOOP
1088 1.123 augustss uhci_rem_loop(sc);
1089 1.125 augustss #endif
1090 1.124 augustss /*
1091 1.124 augustss * The T bit should be set in the elink of the QH so that the HC
1092 1.124 augustss * doesn't follow the pointer. This condition may fail if the
1093 1.124 augustss * the transferred packet was short so that the QH still points
1094 1.124 augustss * at the last used TD.
1095 1.124 augustss * In this case we set the T bit and wait a little for the HC
1096 1.124 augustss * to stop looking at the TD.
1097 1.223 bouyer * Note that if the TD chain is large enough, the controller
1098 1.223 bouyer * may still be looking at the chain at the end of this function.
1099 1.223 bouyer * uhci_free_std_chain() will make sure the controller stops
1100 1.223 bouyer * looking at it quickly, but until then we should not change
1101 1.223 bouyer * sqh->hlink.
1102 1.124 augustss */
1103 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
1104 1.223 bouyer sizeof(sqh->qh.qh_elink),
1105 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1106 1.256 tsutsui elink = le32toh(sqh->qh.qh_elink);
1107 1.256 tsutsui usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
1108 1.256 tsutsui sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD);
1109 1.256 tsutsui if (!(elink & UHCI_PTR_T)) {
1110 1.124 augustss sqh->qh.qh_elink = htole32(UHCI_PTR_T);
1111 1.223 bouyer usb_syncmem(&sqh->dma,
1112 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
1113 1.223 bouyer sizeof(sqh->qh.qh_elink),
1114 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1115 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1116 1.124 augustss }
1117 1.124 augustss
1118 1.123 augustss pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh);
1119 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
1120 1.223 bouyer sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
1121 1.152 augustss pqh->hlink = sqh->hlink;
1122 1.42 augustss pqh->qh.qh_hlink = sqh->qh.qh_hlink;
1123 1.223 bouyer usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
1124 1.223 bouyer sizeof(pqh->qh.qh_hlink),
1125 1.223 bouyer BUS_DMASYNC_PREWRITE);
1126 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1127 1.123 augustss if (sc->sc_hctl_end == sqh)
1128 1.123 augustss sc->sc_hctl_end = pqh;
1129 1.123 augustss }
1130 1.123 augustss
1131 1.248 mrg /* Add low speed control QH, called with lock held. */
1132 1.123 augustss void
1133 1.123 augustss uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1134 1.123 augustss {
1135 1.123 augustss uhci_soft_qh_t *eqh;
1136 1.123 augustss
1137 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
1138 1.248 mrg
1139 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1140 1.264.4.21 skrll DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
1141 1.264.4.21 skrll
1142 1.123 augustss eqh = sc->sc_lctl_end;
1143 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1144 1.223 bouyer sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
1145 1.152 augustss sqh->hlink = eqh->hlink;
1146 1.123 augustss sqh->qh.qh_hlink = eqh->qh.qh_hlink;
1147 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1148 1.223 bouyer BUS_DMASYNC_PREWRITE);
1149 1.152 augustss eqh->hlink = sqh;
1150 1.123 augustss eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
1151 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1152 1.223 bouyer sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
1153 1.123 augustss sc->sc_lctl_end = sqh;
1154 1.123 augustss }
1155 1.123 augustss
1156 1.248 mrg /* Remove low speed control QH, called with lock held. */
1157 1.123 augustss void
1158 1.123 augustss uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1159 1.123 augustss {
1160 1.123 augustss uhci_soft_qh_t *pqh;
1161 1.256 tsutsui uint32_t elink;
1162 1.123 augustss
1163 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
1164 1.248 mrg
1165 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1166 1.264.4.21 skrll DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
1167 1.264.4.21 skrll
1168 1.124 augustss /* See comment in uhci_remove_hs_ctrl() */
1169 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
1170 1.223 bouyer sizeof(sqh->qh.qh_elink),
1171 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1172 1.256 tsutsui elink = le32toh(sqh->qh.qh_elink);
1173 1.256 tsutsui usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
1174 1.256 tsutsui sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD);
1175 1.256 tsutsui if (!(elink & UHCI_PTR_T)) {
1176 1.124 augustss sqh->qh.qh_elink = htole32(UHCI_PTR_T);
1177 1.223 bouyer usb_syncmem(&sqh->dma,
1178 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
1179 1.223 bouyer sizeof(sqh->qh.qh_elink),
1180 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1181 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1182 1.124 augustss }
1183 1.123 augustss pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh);
1184 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
1185 1.223 bouyer sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
1186 1.152 augustss pqh->hlink = sqh->hlink;
1187 1.123 augustss pqh->qh.qh_hlink = sqh->qh.qh_hlink;
1188 1.223 bouyer usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
1189 1.223 bouyer sizeof(pqh->qh.qh_hlink),
1190 1.223 bouyer BUS_DMASYNC_PREWRITE);
1191 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1192 1.123 augustss if (sc->sc_lctl_end == sqh)
1193 1.123 augustss sc->sc_lctl_end = pqh;
1194 1.1 augustss }
1195 1.1 augustss
1196 1.248 mrg /* Add bulk QH, called with lock held. */
1197 1.1 augustss void
1198 1.119 augustss uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1199 1.1 augustss {
1200 1.42 augustss uhci_soft_qh_t *eqh;
1201 1.1 augustss
1202 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
1203 1.248 mrg
1204 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1205 1.264.4.21 skrll DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
1206 1.264.4.21 skrll
1207 1.42 augustss eqh = sc->sc_bulk_end;
1208 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1209 1.223 bouyer sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
1210 1.152 augustss sqh->hlink = eqh->hlink;
1211 1.42 augustss sqh->qh.qh_hlink = eqh->qh.qh_hlink;
1212 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1213 1.223 bouyer BUS_DMASYNC_PREWRITE);
1214 1.152 augustss eqh->hlink = sqh;
1215 1.121 augustss eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
1216 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1217 1.223 bouyer sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
1218 1.1 augustss sc->sc_bulk_end = sqh;
1219 1.123 augustss uhci_add_loop(sc);
1220 1.1 augustss }
1221 1.1 augustss
1222 1.248 mrg /* Remove bulk QH, called with lock held. */
1223 1.1 augustss void
1224 1.119 augustss uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1225 1.1 augustss {
1226 1.1 augustss uhci_soft_qh_t *pqh;
1227 1.1 augustss
1228 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
1229 1.248 mrg
1230 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1231 1.264.4.21 skrll DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
1232 1.264.4.21 skrll
1233 1.123 augustss uhci_rem_loop(sc);
1234 1.124 augustss /* See comment in uhci_remove_hs_ctrl() */
1235 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
1236 1.223 bouyer sizeof(sqh->qh.qh_elink),
1237 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1238 1.124 augustss if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) {
1239 1.124 augustss sqh->qh.qh_elink = htole32(UHCI_PTR_T);
1240 1.223 bouyer usb_syncmem(&sqh->dma,
1241 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
1242 1.223 bouyer sizeof(sqh->qh.qh_elink),
1243 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1244 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1245 1.124 augustss }
1246 1.92 augustss pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh);
1247 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
1248 1.223 bouyer sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
1249 1.42 augustss pqh->hlink = sqh->hlink;
1250 1.42 augustss pqh->qh.qh_hlink = sqh->qh.qh_hlink;
1251 1.223 bouyer usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
1252 1.223 bouyer sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
1253 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1254 1.1 augustss if (sc->sc_bulk_end == sqh)
1255 1.1 augustss sc->sc_bulk_end = pqh;
1256 1.1 augustss }
1257 1.1 augustss
1258 1.141 augustss Static int uhci_intr1(uhci_softc_t *);
1259 1.141 augustss
1260 1.1 augustss int
1261 1.119 augustss uhci_intr(void *arg)
1262 1.1 augustss {
1263 1.44 augustss uhci_softc_t *sc = arg;
1264 1.248 mrg int ret = 0;
1265 1.248 mrg
1266 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1267 1.264.4.21 skrll
1268 1.248 mrg mutex_spin_enter(&sc->sc_intr_lock);
1269 1.146 augustss
1270 1.216 drochner if (sc->sc_dying || !device_has_power(sc->sc_dev))
1271 1.248 mrg goto done;
1272 1.141 augustss
1273 1.264.4.7 skrll if (sc->sc_bus.ub_usepolling || UREAD2(sc, UHCI_INTR) == 0) {
1274 1.264.4.21 skrll DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0);
1275 1.248 mrg goto done;
1276 1.141 augustss }
1277 1.179 mycroft
1278 1.248 mrg ret = uhci_intr1(sc);
1279 1.248 mrg
1280 1.248 mrg done:
1281 1.248 mrg mutex_spin_exit(&sc->sc_intr_lock);
1282 1.248 mrg return ret;
1283 1.141 augustss }
1284 1.141 augustss
1285 1.141 augustss int
1286 1.141 augustss uhci_intr1(uhci_softc_t *sc)
1287 1.141 augustss {
1288 1.44 augustss int status;
1289 1.44 augustss int ack;
1290 1.1 augustss
1291 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1292 1.264.4.21 skrll
1293 1.67 augustss #ifdef UHCI_DEBUG
1294 1.44 augustss if (uhcidebug > 15) {
1295 1.264.4.27 skrll DPRINTF("sc %p", sc, 0, 0, 0);
1296 1.1 augustss uhci_dumpregs(sc);
1297 1.1 augustss }
1298 1.1 augustss #endif
1299 1.117 augustss
1300 1.248 mrg KASSERT(mutex_owned(&sc->sc_intr_lock));
1301 1.248 mrg
1302 1.153 augustss status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS;
1303 1.127 soren if (status == 0) /* The interrupt was not for us. */
1304 1.264.4.13 skrll return 0;
1305 1.127 soren
1306 1.117 augustss if (sc->sc_suspend != PWR_RESUME) {
1307 1.201 jmcneill #ifdef DIAGNOSTIC
1308 1.117 augustss printf("%s: interrupt while not operating ignored\n",
1309 1.216 drochner device_xname(sc->sc_dev));
1310 1.201 jmcneill #endif
1311 1.134 augustss UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */
1312 1.264.4.13 skrll return 0;
1313 1.117 augustss }
1314 1.44 augustss
1315 1.44 augustss ack = 0;
1316 1.44 augustss if (status & UHCI_STS_USBINT)
1317 1.44 augustss ack |= UHCI_STS_USBINT;
1318 1.44 augustss if (status & UHCI_STS_USBEI)
1319 1.44 augustss ack |= UHCI_STS_USBEI;
1320 1.1 augustss if (status & UHCI_STS_RD) {
1321 1.44 augustss ack |= UHCI_STS_RD;
1322 1.118 augustss #ifdef UHCI_DEBUG
1323 1.216 drochner printf("%s: resume detect\n", device_xname(sc->sc_dev));
1324 1.118 augustss #endif
1325 1.1 augustss }
1326 1.1 augustss if (status & UHCI_STS_HSE) {
1327 1.44 augustss ack |= UHCI_STS_HSE;
1328 1.216 drochner printf("%s: host system error\n", device_xname(sc->sc_dev));
1329 1.1 augustss }
1330 1.1 augustss if (status & UHCI_STS_HCPE) {
1331 1.44 augustss ack |= UHCI_STS_HCPE;
1332 1.152 augustss printf("%s: host controller process error\n",
1333 1.216 drochner device_xname(sc->sc_dev));
1334 1.44 augustss }
1335 1.233 msaitoh
1336 1.233 msaitoh /* When HCHalted=1 and Run/Stop=0 , it is normal */
1337 1.233 msaitoh if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) {
1338 1.44 augustss /* no acknowledge needed */
1339 1.136 augustss if (!sc->sc_dying) {
1340 1.152 augustss printf("%s: host controller halted\n",
1341 1.216 drochner device_xname(sc->sc_dev));
1342 1.110 augustss #ifdef UHCI_DEBUG
1343 1.136 augustss uhci_dump_all(sc);
1344 1.110 augustss #endif
1345 1.136 augustss }
1346 1.136 augustss sc->sc_dying = 1;
1347 1.1 augustss }
1348 1.44 augustss
1349 1.132 augustss if (!ack)
1350 1.264.4.13 skrll return 0; /* nothing to acknowledge */
1351 1.132 augustss UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */
1352 1.1 augustss
1353 1.85 augustss usb_schedsoftintr(&sc->sc_bus);
1354 1.85 augustss
1355 1.264.4.21 skrll DPRINTFN(15, "sc %p done", sc, 0, 0, 0);
1356 1.85 augustss
1357 1.264.4.13 skrll return 1;
1358 1.85 augustss }
1359 1.85 augustss
1360 1.85 augustss void
1361 1.133 augustss uhci_softintr(void *v)
1362 1.85 augustss {
1363 1.216 drochner struct usbd_bus *bus = v;
1364 1.264.4.7 skrll uhci_softc_t *sc = bus->ub_hcpriv;
1365 1.178 martin uhci_intr_info_t *ii, *nextii;
1366 1.85 augustss
1367 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1368 1.264.4.27 skrll DPRINTF("sc %p", sc, 0, 0, 0);
1369 1.248 mrg
1370 1.264.4.21 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1371 1.50 augustss
1372 1.1 augustss /*
1373 1.1 augustss * Interrupts on UHCI really suck. When the host controller
1374 1.1 augustss * interrupts because a transfer is completed there is no
1375 1.1 augustss * way of knowing which transfer it was. You can scan down
1376 1.1 augustss * the TDs and QHs of the previous frame to limit the search,
1377 1.1 augustss * but that assumes that the interrupt was not delayed by more
1378 1.1 augustss * than 1 ms, which may not always be true (e.g. after debug
1379 1.1 augustss * output on a slow console).
1380 1.1 augustss * We scan all interrupt descriptors to see if any have
1381 1.1 augustss * completed.
1382 1.1 augustss */
1383 1.178 martin for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = nextii) {
1384 1.178 martin nextii = LIST_NEXT(ii, list);
1385 1.1 augustss uhci_check_intr(sc, ii);
1386 1.178 martin }
1387 1.1 augustss
1388 1.153 augustss if (sc->sc_softwake) {
1389 1.153 augustss sc->sc_softwake = 0;
1390 1.248 mrg cv_broadcast(&sc->sc_softwake_cv);
1391 1.153 augustss }
1392 1.1 augustss }
1393 1.1 augustss
1394 1.1 augustss /* Check for an interrupt. */
1395 1.1 augustss void
1396 1.205 christos uhci_check_intr(uhci_softc_t *sc, uhci_intr_info_t *ii)
1397 1.1 augustss {
1398 1.1 augustss uhci_soft_td_t *std, *lstd;
1399 1.264.4.1 skrll uint32_t status;
1400 1.1 augustss
1401 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1402 1.264.4.21 skrll DPRINTFN(15, "ii %p", ii, 0, 0, 0);
1403 1.1 augustss #ifdef DIAGNOSTIC
1404 1.63 augustss if (ii == NULL) {
1405 1.1 augustss printf("uhci_check_intr: no ii? %p\n", ii);
1406 1.1 augustss return;
1407 1.1 augustss }
1408 1.1 augustss #endif
1409 1.264.4.7 skrll if (ii->xfer->ux_status == USBD_CANCELLED ||
1410 1.264.4.7 skrll ii->xfer->ux_status == USBD_TIMEOUT) {
1411 1.264.4.27 skrll DPRINTF("aborted xfer %p", ii->xfer, 0, 0, 0);
1412 1.155 augustss return;
1413 1.155 augustss }
1414 1.155 augustss
1415 1.63 augustss if (ii->stdstart == NULL)
1416 1.1 augustss return;
1417 1.1 augustss lstd = ii->stdend;
1418 1.1 augustss #ifdef DIAGNOSTIC
1419 1.63 augustss if (lstd == NULL) {
1420 1.1 augustss printf("uhci_check_intr: std==0\n");
1421 1.1 augustss return;
1422 1.1 augustss }
1423 1.1 augustss #endif
1424 1.223 bouyer usb_syncmem(&lstd->dma,
1425 1.223 bouyer lstd->offs + offsetof(uhci_td_t, td_status),
1426 1.223 bouyer sizeof(lstd->td.td_status),
1427 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1428 1.256 tsutsui status = le32toh(lstd->td.td_status);
1429 1.256 tsutsui usb_syncmem(&lstd->dma,
1430 1.256 tsutsui lstd->offs + offsetof(uhci_td_t, td_status),
1431 1.256 tsutsui sizeof(lstd->td.td_status),
1432 1.256 tsutsui BUS_DMASYNC_PREREAD);
1433 1.258 skrll
1434 1.258 skrll /* If the last TD is not marked active we can complete */
1435 1.258 skrll if (!(status & UHCI_TD_ACTIVE)) {
1436 1.258 skrll done:
1437 1.264.4.21 skrll DPRINTFN(12, "ii=%p done", ii, 0, 0, 0);
1438 1.264.4.21 skrll
1439 1.264.4.7 skrll callout_stop(&ii->xfer->ux_callout);
1440 1.258 skrll uhci_idone(ii);
1441 1.258 skrll return;
1442 1.258 skrll }
1443 1.258 skrll
1444 1.258 skrll /*
1445 1.258 skrll * If the last TD is still active we need to check whether there
1446 1.258 skrll * is an error somewhere in the middle, or whether there was a
1447 1.258 skrll * short packet (SPD and not ACTIVE).
1448 1.258 skrll */
1449 1.264.4.21 skrll DPRINTFN(12, "active ii=%p", ii, 0, 0, 0);
1450 1.258 skrll for (std = ii->stdstart; std != lstd; std = std->link.std) {
1451 1.258 skrll usb_syncmem(&std->dma,
1452 1.258 skrll std->offs + offsetof(uhci_td_t, td_status),
1453 1.258 skrll sizeof(std->td.td_status),
1454 1.258 skrll BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1455 1.258 skrll status = le32toh(std->td.td_status);
1456 1.258 skrll usb_syncmem(&std->dma,
1457 1.258 skrll std->offs + offsetof(uhci_td_t, td_status),
1458 1.258 skrll sizeof(std->td.td_status), BUS_DMASYNC_PREREAD);
1459 1.258 skrll
1460 1.258 skrll /* If there's an active TD the xfer isn't done. */
1461 1.258 skrll if (status & UHCI_TD_ACTIVE) {
1462 1.264.4.21 skrll DPRINTFN(12, "ii=%p std=%p still active",
1463 1.264.4.21 skrll ii, std, 0, 0);
1464 1.258 skrll return;
1465 1.258 skrll }
1466 1.258 skrll
1467 1.258 skrll /* Any kind of error makes the xfer done. */
1468 1.258 skrll if (status & UHCI_TD_STALLED)
1469 1.258 skrll goto done;
1470 1.258 skrll
1471 1.258 skrll /*
1472 1.258 skrll * If the data phase of a control transfer is short, we need
1473 1.258 skrll * to complete the status stage
1474 1.258 skrll */
1475 1.264.4.25 skrll struct usbd_xfer *xfer = ii->xfer;
1476 1.264.4.7 skrll usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc;
1477 1.258 skrll uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
1478 1.258 skrll
1479 1.258 skrll if ((status & UHCI_TD_SPD) && xfertype == UE_CONTROL) {
1480 1.258 skrll struct uhci_pipe *upipe =
1481 1.264.4.7 skrll (struct uhci_pipe *)xfer->ux_pipe;
1482 1.258 skrll uhci_soft_qh_t *sqh = upipe->u.ctl.sqh;
1483 1.258 skrll uhci_soft_td_t *stat = upipe->u.ctl.stat;
1484 1.258 skrll
1485 1.264.4.21 skrll DPRINTFN(12, "ii=%p std=%p control status"
1486 1.264.4.21 skrll "phase needs completion", ii, ii->stdstart, 0, 0);
1487 1.258 skrll
1488 1.258 skrll sqh->qh.qh_elink =
1489 1.258 skrll htole32(stat->physaddr | UHCI_PTR_TD);
1490 1.258 skrll usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1491 1.258 skrll BUS_DMASYNC_PREWRITE);
1492 1.258 skrll break;
1493 1.258 skrll }
1494 1.258 skrll
1495 1.258 skrll /* We want short packets, and it is short: it's done */
1496 1.258 skrll usb_syncmem(&std->dma,
1497 1.258 skrll std->offs + offsetof(uhci_td_t, td_token),
1498 1.258 skrll sizeof(std->td.td_token),
1499 1.258 skrll BUS_DMASYNC_POSTWRITE);
1500 1.258 skrll
1501 1.258 skrll if ((status & UHCI_TD_SPD) &&
1502 1.258 skrll UHCI_TD_GET_ACTLEN(status) <
1503 1.258 skrll UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) {
1504 1.258 skrll goto done;
1505 1.18 augustss }
1506 1.1 augustss }
1507 1.1 augustss }
1508 1.1 augustss
1509 1.248 mrg /* Called with USB lock held. */
1510 1.1 augustss void
1511 1.119 augustss uhci_idone(uhci_intr_info_t *ii)
1512 1.1 augustss {
1513 1.264.4.25 skrll struct usbd_xfer *xfer = ii->xfer;
1514 1.264.4.7 skrll struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
1515 1.248 mrg #ifdef DIAGNOSTIC
1516 1.264.4.7 skrll uhci_softc_t *sc = upipe->pipe.up_dev->ud_bus->ub_hcpriv;
1517 1.248 mrg #endif
1518 1.1 augustss uhci_soft_td_t *std;
1519 1.264.4.1 skrll uint32_t status = 0, nstatus;
1520 1.26 augustss int actlen;
1521 1.1 augustss
1522 1.264.4.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1523 1.248 mrg
1524 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1525 1.264.4.21 skrll DPRINTFN(12, "ii=%p", ii, 0, 0, 0);
1526 1.264.4.21 skrll
1527 1.7 augustss #ifdef DIAGNOSTIC
1528 1.7 augustss {
1529 1.248 mrg /* XXX SMP? */
1530 1.7 augustss int s = splhigh();
1531 1.7 augustss if (ii->isdone) {
1532 1.26 augustss splx(s);
1533 1.92 augustss #ifdef UHCI_DEBUG
1534 1.92 augustss printf("uhci_idone: ii is done!\n ");
1535 1.92 augustss uhci_dump_ii(ii);
1536 1.92 augustss #else
1537 1.36 augustss printf("uhci_idone: ii=%p is done!\n", ii);
1538 1.92 augustss #endif
1539 1.7 augustss return;
1540 1.7 augustss }
1541 1.7 augustss ii->isdone = 1;
1542 1.7 augustss splx(s);
1543 1.7 augustss }
1544 1.7 augustss #endif
1545 1.48 augustss
1546 1.264.4.7 skrll if (xfer->ux_nframes != 0) {
1547 1.48 augustss /* Isoc transfer, do things differently. */
1548 1.48 augustss uhci_soft_td_t **stds = upipe->u.iso.stds;
1549 1.126 augustss int i, n, nframes, len;
1550 1.48 augustss
1551 1.264.4.21 skrll DPRINTFN(5, "ii=%p isoc ready", ii, 0, 0, 0);
1552 1.48 augustss
1553 1.264.4.7 skrll nframes = xfer->ux_nframes;
1554 1.48 augustss actlen = 0;
1555 1.92 augustss n = UXFER(xfer)->curframe;
1556 1.48 augustss for (i = 0; i < nframes; i++) {
1557 1.48 augustss std = stds[n];
1558 1.59 augustss #ifdef UHCI_DEBUG
1559 1.48 augustss if (uhcidebug > 5) {
1560 1.264.4.27 skrll DPRINTF("isoc TD %d", i, 0, 0, 0);
1561 1.48 augustss uhci_dump_td(std);
1562 1.48 augustss }
1563 1.48 augustss #endif
1564 1.48 augustss if (++n >= UHCI_VFRAMELIST_COUNT)
1565 1.48 augustss n = 0;
1566 1.223 bouyer usb_syncmem(&std->dma,
1567 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
1568 1.223 bouyer sizeof(std->td.td_status),
1569 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1570 1.88 tsutsui status = le32toh(std->td.td_status);
1571 1.126 augustss len = UHCI_TD_GET_ACTLEN(status);
1572 1.264.4.7 skrll xfer->ux_frlengths[i] = len;
1573 1.126 augustss actlen += len;
1574 1.48 augustss }
1575 1.48 augustss upipe->u.iso.inuse -= nframes;
1576 1.264.4.7 skrll xfer->ux_actlen = actlen;
1577 1.264.4.7 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1578 1.140 augustss goto end;
1579 1.48 augustss }
1580 1.48 augustss
1581 1.59 augustss #ifdef UHCI_DEBUG
1582 1.264.4.21 skrll DPRINTFN(10, "ii=%p, xfer=%p, pipe=%p ready",
1583 1.264.4.21 skrll ii, xfer, upipe, 0);
1584 1.48 augustss if (uhcidebug > 10)
1585 1.48 augustss uhci_dump_tds(ii->stdstart);
1586 1.48 augustss #endif
1587 1.48 augustss
1588 1.26 augustss /* The transfer is done, compute actual length and status. */
1589 1.26 augustss actlen = 0;
1590 1.63 augustss for (std = ii->stdstart; std != NULL; std = std->link.std) {
1591 1.223 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
1592 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1593 1.88 tsutsui nstatus = le32toh(std->td.td_status);
1594 1.64 augustss if (nstatus & UHCI_TD_ACTIVE)
1595 1.26 augustss break;
1596 1.67 augustss
1597 1.64 augustss status = nstatus;
1598 1.88 tsutsui if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) !=
1599 1.88 tsutsui UHCI_TD_PID_SETUP)
1600 1.26 augustss actlen += UHCI_TD_GET_ACTLEN(status);
1601 1.176 mycroft else {
1602 1.176 mycroft /*
1603 1.176 mycroft * UHCI will report CRCTO in addition to a STALL or NAK
1604 1.176 mycroft * for a SETUP transaction. See section 3.2.2, "TD
1605 1.176 mycroft * CONTROL AND STATUS".
1606 1.176 mycroft */
1607 1.176 mycroft if (status & (UHCI_TD_STALLED | UHCI_TD_NAK))
1608 1.176 mycroft status &= ~UHCI_TD_CRCTO;
1609 1.176 mycroft }
1610 1.1 augustss }
1611 1.38 augustss /* If there are left over TDs we need to update the toggle. */
1612 1.63 augustss if (std != NULL)
1613 1.88 tsutsui upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token));
1614 1.38 augustss
1615 1.1 augustss status &= UHCI_TD_ERROR;
1616 1.264.4.21 skrll DPRINTFN(10, "actlen=%d, status=0x%x", actlen, status,
1617 1.264.4.21 skrll 0, 0);
1618 1.264.4.7 skrll xfer->ux_actlen = actlen;
1619 1.1 augustss if (status != 0) {
1620 1.122 tv
1621 1.264.4.21 skrll DPRINTFN((status == UHCI_TD_STALLED) * 10,
1622 1.264.4.21 skrll "error, addr=%d, endpt=0x%02x",
1623 1.264.4.21 skrll xfer->ux_pipe->up_dev->ud_addr,
1624 1.264.4.21 skrll xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress,
1625 1.264.4.21 skrll 0, 0);
1626 1.264.4.21 skrll DPRINTFN((status == UHCI_TD_STALLED) * 10,
1627 1.264.4.21 skrll "bitstuff=%d crcto =%d nak =%d babble =%d",
1628 1.264.4.21 skrll status & UHCI_TD_BITSTUFF,
1629 1.264.4.21 skrll status & UHCI_TD_CRCTO,
1630 1.264.4.21 skrll status & UHCI_TD_NAK,
1631 1.264.4.21 skrll status & UHCI_TD_BABBLE);
1632 1.264.4.21 skrll DPRINTFN((status == UHCI_TD_STALLED) * 10,
1633 1.264.4.21 skrll "dbuffer =%d stalled =%d active =%d",
1634 1.264.4.21 skrll status & UHCI_TD_DBUFFER,
1635 1.264.4.21 skrll status & UHCI_TD_STALLED,
1636 1.264.4.21 skrll status & UHCI_TD_ACTIVE,
1637 1.264.4.21 skrll 0);
1638 1.122 tv
1639 1.1 augustss if (status == UHCI_TD_STALLED)
1640 1.264.4.7 skrll xfer->ux_status = USBD_STALLED;
1641 1.1 augustss else
1642 1.264.4.7 skrll xfer->ux_status = USBD_IOERROR; /* more info XXX */
1643 1.1 augustss } else {
1644 1.264.4.7 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1645 1.1 augustss }
1646 1.140 augustss
1647 1.140 augustss end:
1648 1.63 augustss usb_transfer_complete(xfer);
1649 1.264.4.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1650 1.264.4.21 skrll DPRINTFN(12, "ii=%p done", ii, 0, 0, 0);
1651 1.1 augustss }
1652 1.1 augustss
1653 1.13 augustss /*
1654 1.13 augustss * Called when a request does not complete.
1655 1.13 augustss */
1656 1.1 augustss void
1657 1.119 augustss uhci_timeout(void *addr)
1658 1.1 augustss {
1659 1.1 augustss uhci_intr_info_t *ii = addr;
1660 1.153 augustss struct uhci_xfer *uxfer = UXFER(ii->xfer);
1661 1.264.4.7 skrll struct uhci_pipe *upipe = (struct uhci_pipe *)uxfer->xfer.ux_pipe;
1662 1.264.4.7 skrll uhci_softc_t *sc = upipe->pipe.up_dev->ud_bus->ub_hcpriv;
1663 1.153 augustss
1664 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1665 1.264.4.21 skrll
1666 1.264.4.27 skrll DPRINTF("uxfer %p", uxfer, 0, 0, 0);
1667 1.153 augustss
1668 1.153 augustss if (sc->sc_dying) {
1669 1.248 mrg mutex_enter(&sc->sc_lock);
1670 1.153 augustss uhci_abort_xfer(&uxfer->xfer, USBD_TIMEOUT);
1671 1.248 mrg mutex_exit(&sc->sc_lock);
1672 1.153 augustss return;
1673 1.153 augustss }
1674 1.1 augustss
1675 1.153 augustss /* Execute the abort in a process context. */
1676 1.252 jmcneill usb_init_task(&uxfer->abort_task, uhci_timeout_task, ii->xfer,
1677 1.252 jmcneill USB_TASKQ_MPSAFE);
1678 1.264.4.7 skrll usb_add_task(uxfer->xfer.ux_pipe->up_dev, &uxfer->abort_task,
1679 1.204 joerg USB_TASKQ_HC);
1680 1.153 augustss }
1681 1.51 augustss
1682 1.153 augustss void
1683 1.153 augustss uhci_timeout_task(void *addr)
1684 1.153 augustss {
1685 1.264.4.25 skrll struct usbd_xfer *xfer = addr;
1686 1.264.4.7 skrll uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
1687 1.153 augustss
1688 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1689 1.264.4.21 skrll
1690 1.264.4.27 skrll DPRINTF("xfer=%p", xfer, 0, 0, 0);
1691 1.67 augustss
1692 1.248 mrg mutex_enter(&sc->sc_lock);
1693 1.153 augustss uhci_abort_xfer(xfer, USBD_TIMEOUT);
1694 1.248 mrg mutex_exit(&sc->sc_lock);
1695 1.1 augustss }
1696 1.1 augustss
1697 1.1 augustss /*
1698 1.1 augustss * Wait here until controller claims to have an interrupt.
1699 1.1 augustss * Then call uhci_intr and return. Use timeout to avoid waiting
1700 1.1 augustss * too long.
1701 1.13 augustss * Only used during boot when interrupts are not enabled yet.
1702 1.1 augustss */
1703 1.1 augustss void
1704 1.264.4.25 skrll uhci_waitintr(uhci_softc_t *sc, struct usbd_xfer *xfer)
1705 1.1 augustss {
1706 1.264.4.7 skrll int timo = xfer->ux_timeout;
1707 1.13 augustss uhci_intr_info_t *ii;
1708 1.13 augustss
1709 1.248 mrg mutex_enter(&sc->sc_lock);
1710 1.248 mrg
1711 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1712 1.264.4.21 skrll DPRINTFN(10, "timeout = %dms", timo, 0, 0, 0);
1713 1.1 augustss
1714 1.264.4.7 skrll xfer->ux_status = USBD_IN_PROGRESS;
1715 1.26 augustss for (; timo >= 0; timo--) {
1716 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_lock);
1717 1.264.4.21 skrll DPRINTFN(20, "0x%04x",
1718 1.264.4.21 skrll UREAD2(sc, UHCI_STS), 0, 0, 0);
1719 1.1 augustss if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) {
1720 1.248 mrg mutex_spin_enter(&sc->sc_intr_lock);
1721 1.141 augustss uhci_intr1(sc);
1722 1.248 mrg mutex_spin_exit(&sc->sc_intr_lock);
1723 1.264.4.7 skrll if (xfer->ux_status != USBD_IN_PROGRESS)
1724 1.248 mrg goto done;
1725 1.1 augustss }
1726 1.1 augustss }
1727 1.13 augustss
1728 1.13 augustss /* Timeout */
1729 1.264.4.27 skrll DPRINTF("timeout", 0, 0, 0, 0);
1730 1.13 augustss for (ii = LIST_FIRST(&sc->sc_intrhead);
1731 1.152 augustss ii != NULL && ii->xfer != xfer;
1732 1.13 augustss ii = LIST_NEXT(ii, list))
1733 1.13 augustss ;
1734 1.41 augustss #ifdef DIAGNOSTIC
1735 1.63 augustss if (ii == NULL)
1736 1.163 provos panic("uhci_waitintr: lost intr_info");
1737 1.41 augustss #endif
1738 1.41 augustss uhci_idone(ii);
1739 1.248 mrg
1740 1.248 mrg done:
1741 1.248 mrg mutex_exit(&sc->sc_lock);
1742 1.1 augustss }
1743 1.1 augustss
1744 1.8 augustss void
1745 1.119 augustss uhci_poll(struct usbd_bus *bus)
1746 1.8 augustss {
1747 1.264.4.7 skrll uhci_softc_t *sc = bus->ub_hcpriv;
1748 1.8 augustss
1749 1.248 mrg if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) {
1750 1.248 mrg mutex_spin_enter(&sc->sc_intr_lock);
1751 1.141 augustss uhci_intr1(sc);
1752 1.248 mrg mutex_spin_exit(&sc->sc_intr_lock);
1753 1.248 mrg }
1754 1.8 augustss }
1755 1.8 augustss
1756 1.1 augustss void
1757 1.119 augustss uhci_reset(uhci_softc_t *sc)
1758 1.1 augustss {
1759 1.1 augustss int n;
1760 1.1 augustss
1761 1.1 augustss UHCICMD(sc, UHCI_CMD_HCRESET);
1762 1.1 augustss /* The reset bit goes low when the controller is done. */
1763 1.152 augustss for (n = 0; n < UHCI_RESET_TIMEOUT &&
1764 1.1 augustss (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++)
1765 1.92 augustss usb_delay_ms(&sc->sc_bus, 1);
1766 1.1 augustss if (n >= UHCI_RESET_TIMEOUT)
1767 1.152 augustss printf("%s: controller did not reset\n",
1768 1.216 drochner device_xname(sc->sc_dev));
1769 1.1 augustss }
1770 1.1 augustss
1771 1.16 augustss usbd_status
1772 1.249 drochner uhci_run(uhci_softc_t *sc, int run, int locked)
1773 1.1 augustss {
1774 1.248 mrg int n, running;
1775 1.264.4.1 skrll uint16_t cmd;
1776 1.1 augustss
1777 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1778 1.264.4.21 skrll
1779 1.1 augustss run = run != 0;
1780 1.249 drochner if (!locked)
1781 1.249 drochner mutex_spin_enter(&sc->sc_intr_lock);
1782 1.264.4.21 skrll
1783 1.264.4.27 skrll DPRINTF("setting run=%d", run, 0, 0, 0);
1784 1.71 augustss cmd = UREAD2(sc, UHCI_CMD);
1785 1.71 augustss if (run)
1786 1.71 augustss cmd |= UHCI_CMD_RS;
1787 1.71 augustss else
1788 1.71 augustss cmd &= ~UHCI_CMD_RS;
1789 1.71 augustss UHCICMD(sc, cmd);
1790 1.13 augustss for(n = 0; n < 10; n++) {
1791 1.1 augustss running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH);
1792 1.1 augustss /* return when we've entered the state we want */
1793 1.1 augustss if (run == running) {
1794 1.249 drochner if (!locked)
1795 1.249 drochner mutex_spin_exit(&sc->sc_intr_lock);
1796 1.264.4.27 skrll DPRINTF("done cmd=0x%x sts=0x%x",
1797 1.264.4.21 skrll UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 0, 0);
1798 1.264.4.13 skrll return USBD_NORMAL_COMPLETION;
1799 1.1 augustss }
1800 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock);
1801 1.1 augustss }
1802 1.249 drochner if (!locked)
1803 1.249 drochner mutex_spin_exit(&sc->sc_intr_lock);
1804 1.216 drochner printf("%s: cannot %s\n", device_xname(sc->sc_dev),
1805 1.14 augustss run ? "start" : "stop");
1806 1.264.4.13 skrll return USBD_IOERROR;
1807 1.1 augustss }
1808 1.1 augustss
1809 1.1 augustss /*
1810 1.1 augustss * Memory management routines.
1811 1.1 augustss * uhci_alloc_std allocates TDs
1812 1.1 augustss * uhci_alloc_sqh allocates QHs
1813 1.7 augustss * These two routines do their own free list management,
1814 1.1 augustss * partly for speed, partly because allocating DMAable memory
1815 1.264.4.28 skrll * has page size granularity so much memory would be wasted if
1816 1.16 augustss * only one TD/QH (32 bytes) was placed in each allocated chunk.
1817 1.1 augustss */
1818 1.1 augustss
1819 1.1 augustss uhci_soft_td_t *
1820 1.119 augustss uhci_alloc_std(uhci_softc_t *sc)
1821 1.1 augustss {
1822 1.1 augustss uhci_soft_td_t *std;
1823 1.63 augustss usbd_status err;
1824 1.42 augustss int i, offs;
1825 1.7 augustss usb_dma_t dma;
1826 1.1 augustss
1827 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1828 1.264.4.21 skrll
1829 1.63 augustss if (sc->sc_freetds == NULL) {
1830 1.264.4.21 skrll DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
1831 1.63 augustss err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK,
1832 1.63 augustss UHCI_TD_ALIGN, &dma);
1833 1.63 augustss if (err)
1834 1.264.4.13 skrll return 0;
1835 1.248 mrg for (i = 0; i < UHCI_STD_CHUNK; i++) {
1836 1.42 augustss offs = i * UHCI_STD_SIZE;
1837 1.159 augustss std = KERNADDR(&dma, offs);
1838 1.160 augustss std->physaddr = DMAADDR(&dma, offs);
1839 1.223 bouyer std->dma = dma;
1840 1.223 bouyer std->offs = offs;
1841 1.42 augustss std->link.std = sc->sc_freetds;
1842 1.1 augustss sc->sc_freetds = std;
1843 1.1 augustss }
1844 1.1 augustss }
1845 1.1 augustss std = sc->sc_freetds;
1846 1.42 augustss sc->sc_freetds = std->link.std;
1847 1.42 augustss memset(&std->td, 0, sizeof(uhci_td_t));
1848 1.1 augustss return std;
1849 1.1 augustss }
1850 1.1 augustss
1851 1.1 augustss void
1852 1.119 augustss uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std)
1853 1.1 augustss {
1854 1.7 augustss #ifdef DIAGNOSTIC
1855 1.7 augustss #define TD_IS_FREE 0x12345678
1856 1.88 tsutsui if (le32toh(std->td.td_token) == TD_IS_FREE) {
1857 1.7 augustss printf("uhci_free_std: freeing free TD %p\n", std);
1858 1.7 augustss return;
1859 1.7 augustss }
1860 1.88 tsutsui std->td.td_token = htole32(TD_IS_FREE);
1861 1.7 augustss #endif
1862 1.42 augustss std->link.std = sc->sc_freetds;
1863 1.1 augustss sc->sc_freetds = std;
1864 1.1 augustss }
1865 1.1 augustss
1866 1.1 augustss uhci_soft_qh_t *
1867 1.119 augustss uhci_alloc_sqh(uhci_softc_t *sc)
1868 1.1 augustss {
1869 1.1 augustss uhci_soft_qh_t *sqh;
1870 1.63 augustss usbd_status err;
1871 1.1 augustss int i, offs;
1872 1.7 augustss usb_dma_t dma;
1873 1.1 augustss
1874 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1875 1.264.4.21 skrll
1876 1.63 augustss if (sc->sc_freeqhs == NULL) {
1877 1.264.4.21 skrll DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
1878 1.63 augustss err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK,
1879 1.63 augustss UHCI_QH_ALIGN, &dma);
1880 1.63 augustss if (err)
1881 1.264.4.13 skrll return 0;
1882 1.43 augustss for(i = 0; i < UHCI_SQH_CHUNK; i++) {
1883 1.42 augustss offs = i * UHCI_SQH_SIZE;
1884 1.159 augustss sqh = KERNADDR(&dma, offs);
1885 1.160 augustss sqh->physaddr = DMAADDR(&dma, offs);
1886 1.223 bouyer sqh->dma = dma;
1887 1.223 bouyer sqh->offs = offs;
1888 1.42 augustss sqh->hlink = sc->sc_freeqhs;
1889 1.1 augustss sc->sc_freeqhs = sqh;
1890 1.1 augustss }
1891 1.1 augustss }
1892 1.1 augustss sqh = sc->sc_freeqhs;
1893 1.42 augustss sc->sc_freeqhs = sqh->hlink;
1894 1.42 augustss memset(&sqh->qh, 0, sizeof(uhci_qh_t));
1895 1.264.4.13 skrll return sqh;
1896 1.1 augustss }
1897 1.1 augustss
1898 1.1 augustss void
1899 1.119 augustss uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1900 1.1 augustss {
1901 1.42 augustss sqh->hlink = sc->sc_freeqhs;
1902 1.1 augustss sc->sc_freeqhs = sqh;
1903 1.1 augustss }
1904 1.1 augustss
1905 1.1 augustss void
1906 1.119 augustss uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std,
1907 1.119 augustss uhci_soft_td_t *stdend)
1908 1.1 augustss {
1909 1.1 augustss uhci_soft_td_t *p;
1910 1.256 tsutsui uint32_t td_link;
1911 1.1 augustss
1912 1.223 bouyer /*
1913 1.223 bouyer * to avoid race condition with the controller which may be looking
1914 1.223 bouyer * at this chain, we need to first invalidate all links, and
1915 1.223 bouyer * then wait for the controller to move to another queue
1916 1.223 bouyer */
1917 1.223 bouyer for (p = std; p != stdend; p = p->link.std) {
1918 1.223 bouyer usb_syncmem(&p->dma,
1919 1.223 bouyer p->offs + offsetof(uhci_td_t, td_link),
1920 1.223 bouyer sizeof(p->td.td_link),
1921 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1922 1.256 tsutsui td_link = le32toh(p->td.td_link);
1923 1.256 tsutsui usb_syncmem(&p->dma,
1924 1.256 tsutsui p->offs + offsetof(uhci_td_t, td_link),
1925 1.256 tsutsui sizeof(p->td.td_link),
1926 1.256 tsutsui BUS_DMASYNC_PREREAD);
1927 1.256 tsutsui if ((td_link & UHCI_PTR_T) == 0) {
1928 1.255 tsutsui p->td.td_link = htole32(UHCI_PTR_T);
1929 1.223 bouyer usb_syncmem(&p->dma,
1930 1.223 bouyer p->offs + offsetof(uhci_td_t, td_link),
1931 1.223 bouyer sizeof(p->td.td_link),
1932 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1933 1.223 bouyer }
1934 1.223 bouyer }
1935 1.223 bouyer delay(UHCI_QH_REMOVE_DELAY);
1936 1.223 bouyer
1937 1.1 augustss for (; std != stdend; std = p) {
1938 1.42 augustss p = std->link.std;
1939 1.1 augustss uhci_free_std(sc, std);
1940 1.1 augustss }
1941 1.1 augustss }
1942 1.1 augustss
1943 1.1 augustss usbd_status
1944 1.119 augustss uhci_alloc_std_chain(struct uhci_pipe *upipe, uhci_softc_t *sc, int len,
1945 1.264.4.1 skrll int rd, uint16_t flags, usb_dma_t *dma,
1946 1.119 augustss uhci_soft_td_t **sp, uhci_soft_td_t **ep)
1947 1.1 augustss {
1948 1.1 augustss uhci_soft_td_t *p, *lastp;
1949 1.1 augustss uhci_physaddr_t lastlink;
1950 1.1 augustss int i, ntd, l, tog, maxp;
1951 1.264.4.1 skrll uint32_t status;
1952 1.264.4.7 skrll int addr = upipe->pipe.up_dev->ud_addr;
1953 1.264.4.7 skrll int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
1954 1.1 augustss
1955 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1956 1.264.4.21 skrll
1957 1.264.4.21 skrll DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d",
1958 1.264.4.21 skrll addr, UE_GET_ADDR(endpt), len, upipe->pipe.up_dev->ud_speed);
1959 1.248 mrg
1960 1.264.4.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1961 1.248 mrg
1962 1.264.4.7 skrll maxp = UGETW(upipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize);
1963 1.1 augustss if (maxp == 0) {
1964 1.1 augustss printf("uhci_alloc_std_chain: maxp=0\n");
1965 1.264.4.13 skrll return USBD_INVAL;
1966 1.1 augustss }
1967 1.1 augustss ntd = (len + maxp - 1) / maxp;
1968 1.73 augustss if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0)
1969 1.73 augustss ntd++;
1970 1.264.4.21 skrll DPRINTFN(10, "maxp=%d ntd=%d",
1971 1.264.4.21 skrll maxp, ntd, 0, 0);
1972 1.264.4.21 skrll
1973 1.73 augustss if (ntd == 0) {
1974 1.264.4.26 skrll *sp = *ep = NULL;
1975 1.264.4.27 skrll DPRINTF("ntd=0", 0, 0, 0, 0);
1976 1.264.4.13 skrll return USBD_NORMAL_COMPLETION;
1977 1.73 augustss }
1978 1.38 augustss tog = upipe->nexttoggle;
1979 1.1 augustss if (ntd % 2 == 0)
1980 1.1 augustss tog ^= 1;
1981 1.32 augustss upipe->nexttoggle = tog ^ 1;
1982 1.121 augustss lastp = NULL;
1983 1.1 augustss lastlink = UHCI_PTR_T;
1984 1.1 augustss ntd--;
1985 1.33 augustss status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE);
1986 1.264.4.7 skrll if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW)
1987 1.18 augustss status |= UHCI_TD_LS;
1988 1.73 augustss if (flags & USBD_SHORT_XFER_OK)
1989 1.18 augustss status |= UHCI_TD_SPD;
1990 1.223 bouyer usb_syncmem(dma, 0, len,
1991 1.223 bouyer rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
1992 1.1 augustss for (i = ntd; i >= 0; i--) {
1993 1.1 augustss p = uhci_alloc_std(sc);
1994 1.63 augustss if (p == NULL) {
1995 1.202 christos KASSERT(lastp != NULL);
1996 1.149 augustss uhci_free_std_chain(sc, lastp, NULL);
1997 1.264.4.13 skrll return USBD_NOMEM;
1998 1.1 augustss }
1999 1.42 augustss p->link.std = lastp;
2000 1.121 augustss p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD);
2001 1.1 augustss lastp = p;
2002 1.1 augustss lastlink = p->physaddr;
2003 1.88 tsutsui p->td.td_status = htole32(status);
2004 1.1 augustss if (i == ntd) {
2005 1.1 augustss /* last TD */
2006 1.1 augustss l = len % maxp;
2007 1.73 augustss if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER))
2008 1.73 augustss l = maxp;
2009 1.1 augustss *ep = p;
2010 1.1 augustss } else
2011 1.1 augustss l = maxp;
2012 1.152 augustss p->td.td_token =
2013 1.88 tsutsui htole32(rd ? UHCI_TD_IN (l, endpt, addr, tog) :
2014 1.88 tsutsui UHCI_TD_OUT(l, endpt, addr, tog));
2015 1.160 augustss p->td.td_buffer = htole32(DMAADDR(dma, i * maxp));
2016 1.223 bouyer usb_syncmem(&p->dma, p->offs, sizeof(p->td),
2017 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2018 1.1 augustss tog ^= 1;
2019 1.1 augustss }
2020 1.1 augustss *sp = lastp;
2021 1.264.4.21 skrll DPRINTFN(10, "nexttog=%d", upipe->nexttoggle,
2022 1.264.4.21 skrll 0, 0, 0);
2023 1.264.4.21 skrll
2024 1.264.4.13 skrll return USBD_NORMAL_COMPLETION;
2025 1.1 augustss }
2026 1.1 augustss
2027 1.38 augustss void
2028 1.264.4.25 skrll uhci_device_clear_toggle(struct usbd_pipe *pipe)
2029 1.38 augustss {
2030 1.38 augustss struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;
2031 1.38 augustss upipe->nexttoggle = 0;
2032 1.38 augustss }
2033 1.38 augustss
2034 1.38 augustss void
2035 1.264.4.25 skrll uhci_noop(struct usbd_pipe *pipe)
2036 1.38 augustss {
2037 1.38 augustss }
2038 1.38 augustss
2039 1.1 augustss usbd_status
2040 1.264.4.25 skrll uhci_device_bulk_transfer(struct usbd_xfer *xfer)
2041 1.1 augustss {
2042 1.264.4.7 skrll uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
2043 1.63 augustss usbd_status err;
2044 1.16 augustss
2045 1.52 augustss /* Insert last in queue. */
2046 1.248 mrg mutex_enter(&sc->sc_lock);
2047 1.63 augustss err = usb_insert_transfer(xfer);
2048 1.248 mrg mutex_exit(&sc->sc_lock);
2049 1.63 augustss if (err)
2050 1.264.4.13 skrll return err;
2051 1.52 augustss
2052 1.152 augustss /*
2053 1.92 augustss * Pipe isn't running (otherwise err would be USBD_INPROG),
2054 1.92 augustss * so start it first.
2055 1.67 augustss */
2056 1.264.4.13 skrll return uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2057 1.16 augustss }
2058 1.16 augustss
2059 1.16 augustss usbd_status
2060 1.264.4.25 skrll uhci_device_bulk_start(struct usbd_xfer *xfer)
2061 1.16 augustss {
2062 1.264.4.7 skrll struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
2063 1.264.4.25 skrll struct usbd_device *dev = upipe->pipe.up_dev;
2064 1.264.4.7 skrll uhci_softc_t *sc = dev->ud_bus->ub_hcpriv;
2065 1.92 augustss uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
2066 1.55 augustss uhci_soft_td_t *data, *dataend;
2067 1.1 augustss uhci_soft_qh_t *sqh;
2068 1.63 augustss usbd_status err;
2069 1.45 augustss int len, isread, endpt;
2070 1.1 augustss
2071 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2072 1.264.4.21 skrll DPRINTFN(3, "xfer=%p len=%d flags=%d ii=%p",
2073 1.264.4.21 skrll xfer, xfer->ux_length, xfer->ux_flags, ii);
2074 1.1 augustss
2075 1.82 augustss if (sc->sc_dying)
2076 1.264.4.13 skrll return USBD_IOERROR;
2077 1.82 augustss
2078 1.48 augustss #ifdef DIAGNOSTIC
2079 1.264.4.7 skrll if (xfer->ux_rqflags & URQ_REQUEST)
2080 1.163 provos panic("uhci_device_bulk_transfer: a request");
2081 1.48 augustss #endif
2082 1.1 augustss
2083 1.248 mrg mutex_enter(&sc->sc_lock);
2084 1.248 mrg
2085 1.264.4.7 skrll len = xfer->ux_length;
2086 1.264.4.7 skrll endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
2087 1.45 augustss isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2088 1.1 augustss sqh = upipe->u.bulk.sqh;
2089 1.1 augustss
2090 1.1 augustss upipe->u.bulk.isread = isread;
2091 1.1 augustss upipe->u.bulk.length = len;
2092 1.1 augustss
2093 1.264.4.7 skrll err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->ux_flags,
2094 1.264.4.7 skrll &xfer->ux_dmabuf, &data, &dataend);
2095 1.248 mrg if (err) {
2096 1.248 mrg mutex_exit(&sc->sc_lock);
2097 1.264.4.13 skrll return err;
2098 1.248 mrg }
2099 1.88 tsutsui dataend->td.td_status |= htole32(UHCI_TD_IOC);
2100 1.223 bouyer usb_syncmem(&dataend->dma,
2101 1.223 bouyer dataend->offs + offsetof(uhci_td_t, td_status),
2102 1.223 bouyer sizeof(dataend->td.td_status),
2103 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2104 1.223 bouyer
2105 1.1 augustss
2106 1.59 augustss #ifdef UHCI_DEBUG
2107 1.33 augustss if (uhcidebug > 8) {
2108 1.264.4.21 skrll DPRINTFN(8, "data(1)", 0, 0, 0, 0);
2109 1.55 augustss uhci_dump_tds(data);
2110 1.1 augustss }
2111 1.1 augustss #endif
2112 1.1 augustss
2113 1.1 augustss /* Set up interrupt info. */
2114 1.63 augustss ii->xfer = xfer;
2115 1.55 augustss ii->stdstart = data;
2116 1.55 augustss ii->stdend = dataend;
2117 1.7 augustss #ifdef DIAGNOSTIC
2118 1.70 augustss if (!ii->isdone) {
2119 1.70 augustss printf("uhci_device_bulk_transfer: not done, ii=%p\n", ii);
2120 1.70 augustss }
2121 1.7 augustss ii->isdone = 0;
2122 1.7 augustss #endif
2123 1.1 augustss
2124 1.55 augustss sqh->elink = data;
2125 1.121 augustss sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD);
2126 1.223 bouyer /* uhci_add_bulk() will do usb_syncmem(sqh) */
2127 1.1 augustss
2128 1.1 augustss uhci_add_bulk(sc, sqh);
2129 1.92 augustss uhci_add_intr_info(sc, ii);
2130 1.1 augustss
2131 1.264.4.7 skrll if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
2132 1.264.4.7 skrll callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
2133 1.91 augustss uhci_timeout, ii);
2134 1.13 augustss }
2135 1.264.4.7 skrll xfer->ux_status = USBD_IN_PROGRESS;
2136 1.1 augustss
2137 1.59 augustss #ifdef UHCI_DEBUG
2138 1.1 augustss if (uhcidebug > 10) {
2139 1.264.4.21 skrll DPRINTFN(10, "data(2)", 0, 0, 0, 0);
2140 1.55 augustss uhci_dump_tds(data);
2141 1.1 augustss }
2142 1.1 augustss #endif
2143 1.1 augustss
2144 1.264.4.7 skrll if (sc->sc_bus.ub_usepolling)
2145 1.63 augustss uhci_waitintr(sc, xfer);
2146 1.26 augustss
2147 1.248 mrg mutex_exit(&sc->sc_lock);
2148 1.264.4.13 skrll return USBD_IN_PROGRESS;
2149 1.1 augustss }
2150 1.1 augustss
2151 1.1 augustss /* Abort a device bulk request. */
2152 1.1 augustss void
2153 1.264.4.25 skrll uhci_device_bulk_abort(struct usbd_xfer *xfer)
2154 1.1 augustss {
2155 1.248 mrg #ifdef DIAGNOSTIC
2156 1.264.4.7 skrll uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
2157 1.248 mrg #endif
2158 1.248 mrg
2159 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2160 1.248 mrg
2161 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2162 1.264.4.21 skrll
2163 1.66 augustss uhci_abort_xfer(xfer, USBD_CANCELLED);
2164 1.33 augustss }
2165 1.33 augustss
2166 1.92 augustss /*
2167 1.154 augustss * Abort a device request.
2168 1.154 augustss * If this routine is called at splusb() it guarantees that the request
2169 1.154 augustss * will be removed from the hardware scheduling and that the callback
2170 1.154 augustss * for it will be called with USBD_CANCELLED status.
2171 1.154 augustss * It's impossible to guarantee that the requested transfer will not
2172 1.154 augustss * have happened since the hardware runs concurrently.
2173 1.154 augustss * If the transaction has already happened we rely on the ordinary
2174 1.154 augustss * interrupt processing to process it.
2175 1.248 mrg * XXX This is most probably wrong.
2176 1.248 mrg * XXXMRG this doesn't make sense anymore.
2177 1.92 augustss */
2178 1.33 augustss void
2179 1.264.4.25 skrll uhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status)
2180 1.33 augustss {
2181 1.92 augustss uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
2182 1.264.4.7 skrll struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
2183 1.264.4.7 skrll uhci_softc_t *sc = upipe->pipe.up_dev->ud_bus->ub_hcpriv;
2184 1.33 augustss uhci_soft_td_t *std;
2185 1.188 augustss int wake;
2186 1.65 augustss
2187 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2188 1.264.4.21 skrll DPRINTFN(1,"xfer=%p, status=%d", xfer, status, 0, 0);
2189 1.33 augustss
2190 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2191 1.264.4.3 skrll ASSERT_SLEEPABLE();
2192 1.248 mrg
2193 1.153 augustss if (sc->sc_dying) {
2194 1.153 augustss /* If we're dying, just do the software part. */
2195 1.264.4.7 skrll xfer->ux_status = status; /* make software ignore it */
2196 1.264.4.7 skrll callout_stop(&xfer->ux_callout);
2197 1.153 augustss usb_transfer_complete(xfer);
2198 1.194 christos return;
2199 1.92 augustss }
2200 1.92 augustss
2201 1.153 augustss /*
2202 1.188 augustss * If an abort is already in progress then just wait for it to
2203 1.188 augustss * complete and return.
2204 1.188 augustss */
2205 1.264.4.7 skrll if (xfer->ux_hcflags & UXFER_ABORTING) {
2206 1.264.4.21 skrll DPRINTFN(2, "already aborting", 0, 0, 0, 0);
2207 1.188 augustss #ifdef DIAGNOSTIC
2208 1.188 augustss if (status == USBD_TIMEOUT)
2209 1.188 augustss printf("uhci_abort_xfer: TIMEOUT while aborting\n");
2210 1.188 augustss #endif
2211 1.188 augustss /* Override the status which might be USBD_TIMEOUT. */
2212 1.264.4.7 skrll xfer->ux_status = status;
2213 1.264.4.21 skrll DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0);
2214 1.264.4.7 skrll xfer->ux_hcflags |= UXFER_ABORTWAIT;
2215 1.264.4.7 skrll while (xfer->ux_hcflags & UXFER_ABORTING)
2216 1.264.4.7 skrll cv_wait(&xfer->ux_hccv, &sc->sc_lock);
2217 1.248 mrg goto done;
2218 1.188 augustss }
2219 1.264.4.7 skrll xfer->ux_hcflags |= UXFER_ABORTING;
2220 1.188 augustss
2221 1.188 augustss /*
2222 1.153 augustss * Step 1: Make interrupt routine and hardware ignore xfer.
2223 1.153 augustss */
2224 1.264.4.7 skrll xfer->ux_status = status; /* make software ignore it */
2225 1.264.4.7 skrll callout_stop(&xfer->ux_callout);
2226 1.264.4.27 skrll DPRINTF("stop ii=%p", ii, 0, 0, 0);
2227 1.223 bouyer for (std = ii->stdstart; std != NULL; std = std->link.std) {
2228 1.223 bouyer usb_syncmem(&std->dma,
2229 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
2230 1.223 bouyer sizeof(std->td.td_status),
2231 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2232 1.92 augustss std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC));
2233 1.223 bouyer usb_syncmem(&std->dma,
2234 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
2235 1.223 bouyer sizeof(std->td.td_status),
2236 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2237 1.223 bouyer }
2238 1.92 augustss
2239 1.162 augustss /*
2240 1.153 augustss * Step 2: Wait until we know hardware has finished any possible
2241 1.153 augustss * use of the xfer. Also make sure the soft interrupt routine
2242 1.153 augustss * has run.
2243 1.153 augustss */
2244 1.248 mrg /* Hardware finishes in 1ms */
2245 1.264.4.7 skrll usb_delay_ms_locked(upipe->pipe.up_dev->ud_bus, 2, &sc->sc_lock);
2246 1.153 augustss sc->sc_softwake = 1;
2247 1.153 augustss usb_schedsoftintr(&sc->sc_bus);
2248 1.264.4.27 skrll DPRINTF("cv_wait", 0, 0, 0, 0);
2249 1.248 mrg cv_wait(&sc->sc_softwake_cv, &sc->sc_lock);
2250 1.162 augustss
2251 1.153 augustss /*
2252 1.153 augustss * Step 3: Execute callback.
2253 1.153 augustss */
2254 1.264.4.27 skrll DPRINTF("callback", 0, 0, 0, 0);
2255 1.100 augustss #ifdef DIAGNOSTIC
2256 1.106 augustss ii->isdone = 1;
2257 1.100 augustss #endif
2258 1.264.4.7 skrll wake = xfer->ux_hcflags & UXFER_ABORTWAIT;
2259 1.264.4.7 skrll xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT);
2260 1.106 augustss usb_transfer_complete(xfer);
2261 1.188 augustss if (wake)
2262 1.264.4.7 skrll cv_broadcast(&xfer->ux_hccv);
2263 1.248 mrg done:
2264 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2265 1.1 augustss }
2266 1.1 augustss
2267 1.1 augustss /* Close a device bulk pipe. */
2268 1.1 augustss void
2269 1.264.4.25 skrll uhci_device_bulk_close(struct usbd_pipe *pipe)
2270 1.1 augustss {
2271 1.1 augustss struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;
2272 1.264.4.25 skrll struct usbd_device *dev = upipe->pipe.up_dev;
2273 1.264.4.7 skrll uhci_softc_t *sc = dev->ud_bus->ub_hcpriv;
2274 1.1 augustss
2275 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2276 1.248 mrg
2277 1.1 augustss uhci_free_sqh(sc, upipe->u.bulk.sqh);
2278 1.236 drochner
2279 1.264.4.7 skrll pipe->up_endpoint->ue_toggle = upipe->nexttoggle;
2280 1.1 augustss }
2281 1.1 augustss
2282 1.1 augustss usbd_status
2283 1.264.4.25 skrll uhci_device_ctrl_transfer(struct usbd_xfer *xfer)
2284 1.1 augustss {
2285 1.264.4.7 skrll uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
2286 1.63 augustss usbd_status err;
2287 1.16 augustss
2288 1.52 augustss /* Insert last in queue. */
2289 1.248 mrg mutex_enter(&sc->sc_lock);
2290 1.63 augustss err = usb_insert_transfer(xfer);
2291 1.248 mrg mutex_exit(&sc->sc_lock);
2292 1.63 augustss if (err)
2293 1.264.4.13 skrll return err;
2294 1.52 augustss
2295 1.152 augustss /*
2296 1.92 augustss * Pipe isn't running (otherwise err would be USBD_INPROG),
2297 1.92 augustss * so start it first.
2298 1.67 augustss */
2299 1.264.4.13 skrll return uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2300 1.16 augustss }
2301 1.16 augustss
2302 1.16 augustss usbd_status
2303 1.264.4.25 skrll uhci_device_ctrl_start(struct usbd_xfer *xfer)
2304 1.16 augustss {
2305 1.264.4.7 skrll uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
2306 1.63 augustss usbd_status err;
2307 1.1 augustss
2308 1.82 augustss if (sc->sc_dying)
2309 1.264.4.13 skrll return USBD_IOERROR;
2310 1.82 augustss
2311 1.48 augustss #ifdef DIAGNOSTIC
2312 1.264.4.7 skrll if (!(xfer->ux_rqflags & URQ_REQUEST))
2313 1.163 provos panic("uhci_device_ctrl_transfer: not a request");
2314 1.48 augustss #endif
2315 1.1 augustss
2316 1.248 mrg mutex_enter(&sc->sc_lock);
2317 1.63 augustss err = uhci_device_request(xfer);
2318 1.248 mrg mutex_exit(&sc->sc_lock);
2319 1.63 augustss if (err)
2320 1.264.4.13 skrll return err;
2321 1.1 augustss
2322 1.264.4.7 skrll if (sc->sc_bus.ub_usepolling)
2323 1.63 augustss uhci_waitintr(sc, xfer);
2324 1.264.4.13 skrll return USBD_IN_PROGRESS;
2325 1.1 augustss }
2326 1.1 augustss
2327 1.1 augustss usbd_status
2328 1.264.4.25 skrll uhci_device_intr_transfer(struct usbd_xfer *xfer)
2329 1.1 augustss {
2330 1.264.4.7 skrll uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
2331 1.63 augustss usbd_status err;
2332 1.16 augustss
2333 1.52 augustss /* Insert last in queue. */
2334 1.248 mrg mutex_enter(&sc->sc_lock);
2335 1.63 augustss err = usb_insert_transfer(xfer);
2336 1.248 mrg mutex_exit(&sc->sc_lock);
2337 1.63 augustss if (err)
2338 1.264.4.13 skrll return err;
2339 1.52 augustss
2340 1.152 augustss /*
2341 1.92 augustss * Pipe isn't running (otherwise err would be USBD_INPROG),
2342 1.92 augustss * so start it first.
2343 1.67 augustss */
2344 1.264.4.13 skrll return uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2345 1.16 augustss }
2346 1.16 augustss
2347 1.16 augustss usbd_status
2348 1.264.4.25 skrll uhci_device_intr_start(struct usbd_xfer *xfer)
2349 1.16 augustss {
2350 1.264.4.7 skrll struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
2351 1.264.4.25 skrll struct usbd_device *dev = upipe->pipe.up_dev;
2352 1.264.4.7 skrll uhci_softc_t *sc = dev->ud_bus->ub_hcpriv;
2353 1.92 augustss uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
2354 1.55 augustss uhci_soft_td_t *data, *dataend;
2355 1.1 augustss uhci_soft_qh_t *sqh;
2356 1.63 augustss usbd_status err;
2357 1.187 skrll int isread, endpt;
2358 1.248 mrg int i;
2359 1.1 augustss
2360 1.82 augustss if (sc->sc_dying)
2361 1.264.4.13 skrll return USBD_IOERROR;
2362 1.82 augustss
2363 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2364 1.264.4.21 skrll
2365 1.264.4.21 skrll DPRINTFN(3, "xfer=%p len=%d flags=%d",
2366 1.264.4.21 skrll xfer, xfer->ux_length, xfer->ux_flags, 0);
2367 1.1 augustss
2368 1.48 augustss #ifdef DIAGNOSTIC
2369 1.264.4.7 skrll if (xfer->ux_rqflags & URQ_REQUEST)
2370 1.163 provos panic("uhci_device_intr_transfer: a request");
2371 1.48 augustss #endif
2372 1.1 augustss
2373 1.248 mrg mutex_enter(&sc->sc_lock);
2374 1.248 mrg
2375 1.264.4.7 skrll endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
2376 1.187 skrll isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2377 1.187 skrll
2378 1.187 skrll upipe->u.intr.isread = isread;
2379 1.187 skrll
2380 1.264.4.7 skrll err = uhci_alloc_std_chain(upipe, sc, xfer->ux_length, isread,
2381 1.264.4.7 skrll xfer->ux_flags, &xfer->ux_dmabuf, &data,
2382 1.187 skrll &dataend);
2383 1.248 mrg if (err) {
2384 1.248 mrg mutex_exit(&sc->sc_lock);
2385 1.264.4.13 skrll return err;
2386 1.248 mrg }
2387 1.248 mrg
2388 1.88 tsutsui dataend->td.td_status |= htole32(UHCI_TD_IOC);
2389 1.223 bouyer usb_syncmem(&dataend->dma,
2390 1.223 bouyer dataend->offs + offsetof(uhci_td_t, td_status),
2391 1.223 bouyer sizeof(dataend->td.td_status),
2392 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2393 1.1 augustss
2394 1.264.4.21 skrll DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0);
2395 1.59 augustss #ifdef UHCI_DEBUG
2396 1.1 augustss if (uhcidebug > 10) {
2397 1.55 augustss uhci_dump_tds(data);
2398 1.1 augustss uhci_dump_qh(upipe->u.intr.qhs[0]);
2399 1.1 augustss }
2400 1.1 augustss #endif
2401 1.264.4.21 skrll DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0);
2402 1.1 augustss
2403 1.1 augustss /* Set up interrupt info. */
2404 1.63 augustss ii->xfer = xfer;
2405 1.55 augustss ii->stdstart = data;
2406 1.55 augustss ii->stdend = dataend;
2407 1.7 augustss #ifdef DIAGNOSTIC
2408 1.70 augustss if (!ii->isdone) {
2409 1.70 augustss printf("uhci_device_intr_transfer: not done, ii=%p\n", ii);
2410 1.70 augustss }
2411 1.7 augustss ii->isdone = 0;
2412 1.7 augustss #endif
2413 1.1 augustss
2414 1.264.4.21 skrll DPRINTFN(10, "qhs[0]=%p", upipe->u.intr.qhs[0], 0, 0, 0);
2415 1.1 augustss for (i = 0; i < upipe->u.intr.npoll; i++) {
2416 1.1 augustss sqh = upipe->u.intr.qhs[i];
2417 1.55 augustss sqh->elink = data;
2418 1.121 augustss sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD);
2419 1.223 bouyer usb_syncmem(&sqh->dma,
2420 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
2421 1.223 bouyer sizeof(sqh->qh.qh_elink),
2422 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2423 1.1 augustss }
2424 1.92 augustss uhci_add_intr_info(sc, ii);
2425 1.264.4.7 skrll xfer->ux_status = USBD_IN_PROGRESS;
2426 1.248 mrg mutex_exit(&sc->sc_lock);
2427 1.1 augustss
2428 1.264.4.21 skrll DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0);
2429 1.59 augustss #ifdef UHCI_DEBUG
2430 1.1 augustss if (uhcidebug > 10) {
2431 1.55 augustss uhci_dump_tds(data);
2432 1.1 augustss uhci_dump_qh(upipe->u.intr.qhs[0]);
2433 1.1 augustss }
2434 1.1 augustss #endif
2435 1.264.4.21 skrll DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0);
2436 1.1 augustss
2437 1.264.4.13 skrll return USBD_IN_PROGRESS;
2438 1.1 augustss }
2439 1.1 augustss
2440 1.1 augustss /* Abort a device control request. */
2441 1.1 augustss void
2442 1.264.4.25 skrll uhci_device_ctrl_abort(struct usbd_xfer *xfer)
2443 1.1 augustss {
2444 1.248 mrg #ifdef DIAGNOSTIC
2445 1.264.4.7 skrll uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
2446 1.248 mrg #endif
2447 1.248 mrg
2448 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2449 1.248 mrg
2450 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2451 1.66 augustss uhci_abort_xfer(xfer, USBD_CANCELLED);
2452 1.1 augustss }
2453 1.1 augustss
2454 1.1 augustss /* Close a device control pipe. */
2455 1.1 augustss void
2456 1.264.4.25 skrll uhci_device_ctrl_close(struct usbd_pipe *pipe)
2457 1.1 augustss {
2458 1.1 augustss }
2459 1.1 augustss
2460 1.1 augustss /* Abort a device interrupt request. */
2461 1.1 augustss void
2462 1.264.4.25 skrll uhci_device_intr_abort(struct usbd_xfer *xfer)
2463 1.1 augustss {
2464 1.248 mrg #ifdef DIAGNOSTIC
2465 1.264.4.7 skrll uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
2466 1.248 mrg #endif
2467 1.248 mrg
2468 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2469 1.264.4.7 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
2470 1.248 mrg
2471 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2472 1.264.4.27 skrll DPRINTF("xfer=%p", xfer, 0, 0, 0);
2473 1.264 skrll
2474 1.66 augustss uhci_abort_xfer(xfer, USBD_CANCELLED);
2475 1.1 augustss }
2476 1.1 augustss
2477 1.1 augustss /* Close a device interrupt pipe. */
2478 1.1 augustss void
2479 1.264.4.25 skrll uhci_device_intr_close(struct usbd_pipe *pipe)
2480 1.1 augustss {
2481 1.1 augustss struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;
2482 1.264.4.7 skrll uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv;
2483 1.92 augustss int i, npoll;
2484 1.248 mrg
2485 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2486 1.1 augustss
2487 1.1 augustss /* Unlink descriptors from controller data structures. */
2488 1.1 augustss npoll = upipe->u.intr.npoll;
2489 1.1 augustss for (i = 0; i < npoll; i++)
2490 1.92 augustss uhci_remove_intr(sc, upipe->u.intr.qhs[i]);
2491 1.1 augustss
2492 1.152 augustss /*
2493 1.1 augustss * We now have to wait for any activity on the physical
2494 1.1 augustss * descriptors to stop.
2495 1.1 augustss */
2496 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock);
2497 1.1 augustss
2498 1.1 augustss for(i = 0; i < npoll; i++)
2499 1.1 augustss uhci_free_sqh(sc, upipe->u.intr.qhs[i]);
2500 1.248 mrg kmem_free(upipe->u.intr.qhs, npoll * sizeof(uhci_soft_qh_t *));
2501 1.1 augustss
2502 1.1 augustss /* XXX free other resources */
2503 1.1 augustss }
2504 1.1 augustss
2505 1.1 augustss usbd_status
2506 1.264.4.25 skrll uhci_device_request(struct usbd_xfer *xfer)
2507 1.1 augustss {
2508 1.264.4.7 skrll struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
2509 1.264.4.7 skrll usb_device_request_t *req = &xfer->ux_request;
2510 1.264.4.25 skrll struct usbd_device *dev = upipe->pipe.up_dev;
2511 1.264.4.7 skrll uhci_softc_t *sc = dev->ud_bus->ub_hcpriv;
2512 1.264.4.7 skrll int addr = dev->ud_addr;
2513 1.264.4.7 skrll int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
2514 1.92 augustss uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
2515 1.55 augustss uhci_soft_td_t *setup, *data, *stat, *next, *dataend;
2516 1.1 augustss uhci_soft_qh_t *sqh;
2517 1.1 augustss int len;
2518 1.264.4.1 skrll uint32_t ls;
2519 1.63 augustss usbd_status err;
2520 1.1 augustss int isread;
2521 1.248 mrg
2522 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2523 1.1 augustss
2524 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2525 1.264.4.21 skrll DPRINTFN(3, "type=0x%02x, request=0x%02x, "
2526 1.264.4.21 skrll "wValue=0x%04x, wIndex=0x%04x",
2527 1.264.4.21 skrll req->bmRequestType, req->bRequest, UGETW(req->wValue),
2528 1.264.4.21 skrll UGETW(req->wIndex));
2529 1.264.4.21 skrll DPRINTFN(3, "len=%d, addr=%d, endpt=%d",
2530 1.264.4.21 skrll UGETW(req->wLength), dev->ud_addr, endpt, 0);
2531 1.1 augustss
2532 1.264.4.7 skrll ls = dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0;
2533 1.1 augustss isread = req->bmRequestType & UT_READ;
2534 1.1 augustss len = UGETW(req->wLength);
2535 1.1 augustss
2536 1.1 augustss setup = upipe->u.ctl.setup;
2537 1.1 augustss stat = upipe->u.ctl.stat;
2538 1.1 augustss sqh = upipe->u.ctl.sqh;
2539 1.1 augustss
2540 1.1 augustss /* Set up data transaction */
2541 1.1 augustss if (len != 0) {
2542 1.38 augustss upipe->nexttoggle = 1;
2543 1.264.4.7 skrll err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->ux_flags,
2544 1.264.4.7 skrll &xfer->ux_dmabuf, &data, &dataend);
2545 1.63 augustss if (err)
2546 1.264.4.13 skrll return err;
2547 1.55 augustss next = data;
2548 1.55 augustss dataend->link.std = stat;
2549 1.258 skrll dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD);
2550 1.223 bouyer usb_syncmem(&dataend->dma,
2551 1.223 bouyer dataend->offs + offsetof(uhci_td_t, td_link),
2552 1.223 bouyer sizeof(dataend->td.td_link),
2553 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2554 1.1 augustss } else {
2555 1.1 augustss next = stat;
2556 1.1 augustss }
2557 1.1 augustss upipe->u.ctl.length = len;
2558 1.1 augustss
2559 1.159 augustss memcpy(KERNADDR(&upipe->u.ctl.reqdma, 0), req, sizeof *req);
2560 1.223 bouyer usb_syncmem(&upipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE);
2561 1.1 augustss
2562 1.42 augustss setup->link.std = next;
2563 1.258 skrll setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD);
2564 1.88 tsutsui setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls |
2565 1.88 tsutsui UHCI_TD_ACTIVE);
2566 1.88 tsutsui setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof *req, endpt, addr));
2567 1.160 augustss setup->td.td_buffer = htole32(DMAADDR(&upipe->u.ctl.reqdma, 0));
2568 1.223 bouyer usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td),
2569 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2570 1.42 augustss
2571 1.92 augustss stat->link.std = NULL;
2572 1.88 tsutsui stat->td.td_link = htole32(UHCI_PTR_T);
2573 1.152 augustss stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls |
2574 1.39 augustss UHCI_TD_ACTIVE | UHCI_TD_IOC);
2575 1.152 augustss stat->td.td_token =
2576 1.88 tsutsui htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) :
2577 1.264.4.2 skrll UHCI_TD_IN (0, endpt, addr, 1));
2578 1.88 tsutsui stat->td.td_buffer = htole32(0);
2579 1.223 bouyer usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td),
2580 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2581 1.1 augustss
2582 1.264.4.21 skrll DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0);
2583 1.59 augustss #ifdef UHCI_DEBUG
2584 1.67 augustss if (uhcidebug > 10) {
2585 1.264.4.21 skrll DPRINTFN(10, "before transfer", 0, 0, 0, 0);
2586 1.41 augustss uhci_dump_tds(setup);
2587 1.1 augustss }
2588 1.1 augustss #endif
2589 1.264.4.21 skrll DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0);
2590 1.1 augustss
2591 1.1 augustss /* Set up interrupt info. */
2592 1.63 augustss ii->xfer = xfer;
2593 1.1 augustss ii->stdstart = setup;
2594 1.1 augustss ii->stdend = stat;
2595 1.7 augustss #ifdef DIAGNOSTIC
2596 1.70 augustss if (!ii->isdone) {
2597 1.70 augustss printf("uhci_device_request: not done, ii=%p\n", ii);
2598 1.70 augustss }
2599 1.7 augustss ii->isdone = 0;
2600 1.7 augustss #endif
2601 1.1 augustss
2602 1.42 augustss sqh->elink = setup;
2603 1.121 augustss sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD);
2604 1.223 bouyer /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */
2605 1.1 augustss
2606 1.264.4.7 skrll if (dev->ud_speed == USB_SPEED_LOW)
2607 1.123 augustss uhci_add_ls_ctrl(sc, sqh);
2608 1.123 augustss else
2609 1.123 augustss uhci_add_hs_ctrl(sc, sqh);
2610 1.92 augustss uhci_add_intr_info(sc, ii);
2611 1.264.4.21 skrll DPRINTFN(12, "--- dump start ---", 0, 0, 0, 0);
2612 1.59 augustss #ifdef UHCI_DEBUG
2613 1.1 augustss if (uhcidebug > 12) {
2614 1.1 augustss uhci_soft_td_t *std;
2615 1.1 augustss uhci_soft_qh_t *xqh;
2616 1.13 augustss uhci_soft_qh_t *sxqh;
2617 1.13 augustss int maxqh = 0;
2618 1.1 augustss uhci_physaddr_t link;
2619 1.264.4.21 skrll DPRINTFN(12, "follow from [0]", 0, 0, 0, 0);
2620 1.1 augustss for (std = sc->sc_vframes[0].htd, link = 0;
2621 1.121 augustss (link & UHCI_PTR_QH) == 0;
2622 1.42 augustss std = std->link.std) {
2623 1.88 tsutsui link = le32toh(std->td.td_link);
2624 1.1 augustss uhci_dump_td(std);
2625 1.1 augustss }
2626 1.67 augustss sxqh = (uhci_soft_qh_t *)std;
2627 1.67 augustss uhci_dump_qh(sxqh);
2628 1.67 augustss for (xqh = sxqh;
2629 1.63 augustss xqh != NULL;
2630 1.152 augustss xqh = (maxqh++ == 5 || xqh->hlink == sxqh ||
2631 1.264.4.2 skrll xqh->hlink == xqh ? NULL : xqh->hlink)) {
2632 1.1 augustss uhci_dump_qh(xqh);
2633 1.13 augustss }
2634 1.264.4.21 skrll DPRINTFN(12, "Enqueued QH:", 0, 0, 0, 0);
2635 1.1 augustss uhci_dump_qh(sqh);
2636 1.42 augustss uhci_dump_tds(sqh->elink);
2637 1.1 augustss }
2638 1.1 augustss #endif
2639 1.264.4.21 skrll DPRINTFN(12, "--- dump end ---", 0, 0, 0, 0);
2640 1.264.4.7 skrll if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
2641 1.264.4.7 skrll callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
2642 1.91 augustss uhci_timeout, ii);
2643 1.13 augustss }
2644 1.264.4.7 skrll xfer->ux_status = USBD_IN_PROGRESS;
2645 1.1 augustss
2646 1.264.4.13 skrll return USBD_NORMAL_COMPLETION;
2647 1.1 augustss }
2648 1.1 augustss
2649 1.16 augustss usbd_status
2650 1.264.4.25 skrll uhci_device_isoc_transfer(struct usbd_xfer *xfer)
2651 1.16 augustss {
2652 1.264.4.7 skrll uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
2653 1.63 augustss usbd_status err;
2654 1.48 augustss
2655 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2656 1.264.4.21 skrll DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0);
2657 1.48 augustss
2658 1.48 augustss /* Put it on our queue, */
2659 1.248 mrg mutex_enter(&sc->sc_lock);
2660 1.63 augustss err = usb_insert_transfer(xfer);
2661 1.248 mrg mutex_exit(&sc->sc_lock);
2662 1.48 augustss
2663 1.48 augustss /* bail out on error, */
2664 1.63 augustss if (err && err != USBD_IN_PROGRESS)
2665 1.264.4.13 skrll return err;
2666 1.48 augustss
2667 1.48 augustss /* XXX should check inuse here */
2668 1.48 augustss
2669 1.48 augustss /* insert into schedule, */
2670 1.63 augustss uhci_device_isoc_enter(xfer);
2671 1.48 augustss
2672 1.102 augustss /* and start if the pipe wasn't running */
2673 1.67 augustss if (!err)
2674 1.264.4.7 skrll uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2675 1.48 augustss
2676 1.264.4.13 skrll return err;
2677 1.48 augustss }
2678 1.48 augustss
2679 1.48 augustss void
2680 1.264.4.25 skrll uhci_device_isoc_enter(struct usbd_xfer *xfer)
2681 1.48 augustss {
2682 1.264.4.7 skrll struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
2683 1.264.4.25 skrll struct usbd_device *dev = upipe->pipe.up_dev;
2684 1.264.4.7 skrll uhci_softc_t *sc = dev->ud_bus->ub_hcpriv;
2685 1.48 augustss struct iso *iso = &upipe->u.iso;
2686 1.152 augustss uhci_soft_td_t *std;
2687 1.264.4.1 skrll uint32_t buf, len, status, offs;
2688 1.248 mrg int i, next, nframes;
2689 1.264.4.7 skrll int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN;
2690 1.48 augustss
2691 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2692 1.264.4.21 skrll DPRINTFN(5, "used=%d next=%d xfer=%p nframes=%d",
2693 1.264.4.21 skrll iso->inuse, iso->next, xfer, xfer->ux_nframes);
2694 1.48 augustss
2695 1.82 augustss if (sc->sc_dying)
2696 1.82 augustss return;
2697 1.82 augustss
2698 1.264.4.7 skrll if (xfer->ux_status == USBD_IN_PROGRESS) {
2699 1.48 augustss /* This request has already been entered into the frame list */
2700 1.96 augustss printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer);
2701 1.68 augustss /* XXX */
2702 1.48 augustss }
2703 1.48 augustss
2704 1.48 augustss #ifdef DIAGNOSTIC
2705 1.48 augustss if (iso->inuse >= UHCI_VFRAMELIST_COUNT)
2706 1.48 augustss printf("uhci_device_isoc_enter: overflow!\n");
2707 1.19 augustss #endif
2708 1.16 augustss
2709 1.48 augustss next = iso->next;
2710 1.48 augustss if (next == -1) {
2711 1.48 augustss /* Not in use yet, schedule it a few frames ahead. */
2712 1.48 augustss next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT;
2713 1.264.4.21 skrll DPRINTFN(2, "start next=%d", next, 0, 0, 0);
2714 1.48 augustss }
2715 1.48 augustss
2716 1.264.4.7 skrll xfer->ux_status = USBD_IN_PROGRESS;
2717 1.92 augustss UXFER(xfer)->curframe = next;
2718 1.48 augustss
2719 1.264.4.7 skrll buf = DMAADDR(&xfer->ux_dmabuf, 0);
2720 1.223 bouyer offs = 0;
2721 1.88 tsutsui status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) |
2722 1.88 tsutsui UHCI_TD_ACTIVE |
2723 1.88 tsutsui UHCI_TD_IOS);
2724 1.264.4.7 skrll nframes = xfer->ux_nframes;
2725 1.248 mrg mutex_enter(&sc->sc_lock);
2726 1.48 augustss for (i = 0; i < nframes; i++) {
2727 1.48 augustss std = iso->stds[next];
2728 1.48 augustss if (++next >= UHCI_VFRAMELIST_COUNT)
2729 1.48 augustss next = 0;
2730 1.264.4.7 skrll len = xfer->ux_frlengths[i];
2731 1.88 tsutsui std->td.td_buffer = htole32(buf);
2732 1.264.4.7 skrll usb_syncmem(&xfer->ux_dmabuf, offs, len,
2733 1.223 bouyer rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
2734 1.48 augustss if (i == nframes - 1)
2735 1.88 tsutsui status |= UHCI_TD_IOC;
2736 1.88 tsutsui std->td.td_status = htole32(status);
2737 1.88 tsutsui std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK);
2738 1.88 tsutsui std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len));
2739 1.223 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
2740 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2741 1.264.4.21 skrll DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0);
2742 1.59 augustss #ifdef UHCI_DEBUG
2743 1.48 augustss if (uhcidebug > 5) {
2744 1.264.4.27 skrll DPRINTF("TD %d", i, 0, 0, 0);
2745 1.48 augustss uhci_dump_td(std);
2746 1.48 augustss }
2747 1.48 augustss #endif
2748 1.264.4.21 skrll DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0);
2749 1.48 augustss buf += len;
2750 1.223 bouyer offs += len;
2751 1.48 augustss }
2752 1.48 augustss iso->next = next;
2753 1.264.4.7 skrll iso->inuse += xfer->ux_nframes;
2754 1.16 augustss
2755 1.248 mrg mutex_exit(&sc->sc_lock);
2756 1.16 augustss }
2757 1.16 augustss
2758 1.16 augustss usbd_status
2759 1.264.4.25 skrll uhci_device_isoc_start(struct usbd_xfer *xfer)
2760 1.16 augustss {
2761 1.264.4.7 skrll struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
2762 1.264.4.7 skrll uhci_softc_t *sc = upipe->pipe.up_dev->ud_bus->ub_hcpriv;
2763 1.92 augustss uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
2764 1.48 augustss uhci_soft_td_t *end;
2765 1.248 mrg int i;
2766 1.48 augustss
2767 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2768 1.264.4.21 skrll DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0);
2769 1.96 augustss
2770 1.248 mrg mutex_enter(&sc->sc_lock);
2771 1.248 mrg
2772 1.248 mrg if (sc->sc_dying) {
2773 1.248 mrg mutex_exit(&sc->sc_lock);
2774 1.264.4.13 skrll return USBD_IOERROR;
2775 1.248 mrg }
2776 1.82 augustss
2777 1.48 augustss #ifdef DIAGNOSTIC
2778 1.264.4.7 skrll if (xfer->ux_status != USBD_IN_PROGRESS)
2779 1.63 augustss printf("uhci_device_isoc_start: not in progress %p\n", xfer);
2780 1.48 augustss #endif
2781 1.48 augustss
2782 1.48 augustss /* Find the last TD */
2783 1.264.4.7 skrll i = UXFER(xfer)->curframe + xfer->ux_nframes;
2784 1.48 augustss if (i >= UHCI_VFRAMELIST_COUNT)
2785 1.48 augustss i -= UHCI_VFRAMELIST_COUNT;
2786 1.48 augustss end = upipe->u.iso.stds[i];
2787 1.48 augustss
2788 1.96 augustss #ifdef DIAGNOSTIC
2789 1.96 augustss if (end == NULL) {
2790 1.96 augustss printf("uhci_device_isoc_start: end == NULL\n");
2791 1.264.4.13 skrll return USBD_INVAL;
2792 1.96 augustss }
2793 1.96 augustss #endif
2794 1.96 augustss
2795 1.48 augustss /* Set up interrupt info. */
2796 1.63 augustss ii->xfer = xfer;
2797 1.48 augustss ii->stdstart = end;
2798 1.48 augustss ii->stdend = end;
2799 1.48 augustss #ifdef DIAGNOSTIC
2800 1.102 augustss if (!ii->isdone)
2801 1.70 augustss printf("uhci_device_isoc_start: not done, ii=%p\n", ii);
2802 1.48 augustss ii->isdone = 0;
2803 1.48 augustss #endif
2804 1.92 augustss uhci_add_intr_info(sc, ii);
2805 1.152 augustss
2806 1.248 mrg mutex_exit(&sc->sc_lock);
2807 1.48 augustss
2808 1.264.4.13 skrll return USBD_IN_PROGRESS;
2809 1.16 augustss }
2810 1.16 augustss
2811 1.16 augustss void
2812 1.264.4.25 skrll uhci_device_isoc_abort(struct usbd_xfer *xfer)
2813 1.16 augustss {
2814 1.248 mrg #ifdef DIAGNOSTIC
2815 1.264.4.7 skrll uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
2816 1.248 mrg #endif
2817 1.264.4.7 skrll struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
2818 1.48 augustss uhci_soft_td_t **stds = upipe->u.iso.stds;
2819 1.48 augustss uhci_soft_td_t *std;
2820 1.248 mrg int i, n, nframes, maxlen, len;
2821 1.92 augustss
2822 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2823 1.92 augustss
2824 1.92 augustss /* Transfer is already done. */
2825 1.264.4.7 skrll if (xfer->ux_status != USBD_NOT_STARTED &&
2826 1.264.4.7 skrll xfer->ux_status != USBD_IN_PROGRESS) {
2827 1.92 augustss return;
2828 1.92 augustss }
2829 1.48 augustss
2830 1.92 augustss /* Give xfer the requested abort code. */
2831 1.264.4.7 skrll xfer->ux_status = USBD_CANCELLED;
2832 1.48 augustss
2833 1.48 augustss /* make hardware ignore it, */
2834 1.264.4.7 skrll nframes = xfer->ux_nframes;
2835 1.92 augustss n = UXFER(xfer)->curframe;
2836 1.92 augustss maxlen = 0;
2837 1.48 augustss for (i = 0; i < nframes; i++) {
2838 1.48 augustss std = stds[n];
2839 1.223 bouyer usb_syncmem(&std->dma,
2840 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
2841 1.223 bouyer sizeof(std->td.td_status),
2842 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2843 1.88 tsutsui std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC));
2844 1.223 bouyer usb_syncmem(&std->dma,
2845 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
2846 1.223 bouyer sizeof(std->td.td_status),
2847 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2848 1.223 bouyer usb_syncmem(&std->dma,
2849 1.223 bouyer std->offs + offsetof(uhci_td_t, td_token),
2850 1.223 bouyer sizeof(std->td.td_token),
2851 1.223 bouyer BUS_DMASYNC_POSTWRITE);
2852 1.130 tsutsui len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token));
2853 1.92 augustss if (len > maxlen)
2854 1.92 augustss maxlen = len;
2855 1.48 augustss if (++n >= UHCI_VFRAMELIST_COUNT)
2856 1.48 augustss n = 0;
2857 1.48 augustss }
2858 1.48 augustss
2859 1.92 augustss /* and wait until we are sure the hardware has finished. */
2860 1.92 augustss delay(maxlen);
2861 1.92 augustss
2862 1.96 augustss #ifdef DIAGNOSTIC
2863 1.96 augustss UXFER(xfer)->iinfo.isdone = 1;
2864 1.96 augustss #endif
2865 1.92 augustss /* Run callback and remove from interrupt list. */
2866 1.92 augustss usb_transfer_complete(xfer);
2867 1.48 augustss
2868 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2869 1.16 augustss }
2870 1.16 augustss
2871 1.16 augustss void
2872 1.264.4.25 skrll uhci_device_isoc_close(struct usbd_pipe *pipe)
2873 1.16 augustss {
2874 1.16 augustss struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;
2875 1.264.4.25 skrll struct usbd_device *dev = upipe->pipe.up_dev;
2876 1.264.4.7 skrll uhci_softc_t *sc = dev->ud_bus->ub_hcpriv;
2877 1.48 augustss uhci_soft_td_t *std, *vstd;
2878 1.16 augustss struct iso *iso;
2879 1.248 mrg int i;
2880 1.248 mrg
2881 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2882 1.16 augustss
2883 1.16 augustss /*
2884 1.16 augustss * Make sure all TDs are marked as inactive.
2885 1.16 augustss * Wait for completion.
2886 1.16 augustss * Unschedule.
2887 1.16 augustss * Deallocate.
2888 1.16 augustss */
2889 1.16 augustss iso = &upipe->u.iso;
2890 1.16 augustss
2891 1.223 bouyer for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
2892 1.223 bouyer std = iso->stds[i];
2893 1.223 bouyer usb_syncmem(&std->dma,
2894 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
2895 1.223 bouyer sizeof(std->td.td_status),
2896 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2897 1.223 bouyer std->td.td_status &= htole32(~UHCI_TD_ACTIVE);
2898 1.223 bouyer usb_syncmem(&std->dma,
2899 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
2900 1.223 bouyer sizeof(std->td.td_status),
2901 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2902 1.223 bouyer }
2903 1.248 mrg /* wait for completion */
2904 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock);
2905 1.16 augustss
2906 1.16 augustss for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
2907 1.16 augustss std = iso->stds[i];
2908 1.48 augustss for (vstd = sc->sc_vframes[i].htd;
2909 1.67 augustss vstd != NULL && vstd->link.std != std;
2910 1.42 augustss vstd = vstd->link.std)
2911 1.16 augustss ;
2912 1.67 augustss if (vstd == NULL) {
2913 1.16 augustss /*panic*/
2914 1.16 augustss printf("uhci_device_isoc_close: %p not found\n", std);
2915 1.248 mrg mutex_exit(&sc->sc_lock);
2916 1.16 augustss return;
2917 1.16 augustss }
2918 1.42 augustss vstd->link = std->link;
2919 1.223 bouyer usb_syncmem(&std->dma,
2920 1.223 bouyer std->offs + offsetof(uhci_td_t, td_link),
2921 1.223 bouyer sizeof(std->td.td_link),
2922 1.223 bouyer BUS_DMASYNC_POSTWRITE);
2923 1.42 augustss vstd->td.td_link = std->td.td_link;
2924 1.223 bouyer usb_syncmem(&vstd->dma,
2925 1.223 bouyer vstd->offs + offsetof(uhci_td_t, td_link),
2926 1.223 bouyer sizeof(vstd->td.td_link),
2927 1.223 bouyer BUS_DMASYNC_PREWRITE);
2928 1.16 augustss uhci_free_std(sc, std);
2929 1.16 augustss }
2930 1.16 augustss
2931 1.248 mrg kmem_free(iso->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *));
2932 1.16 augustss }
2933 1.16 augustss
2934 1.16 augustss usbd_status
2935 1.264.4.25 skrll uhci_setup_isoc(struct usbd_pipe *pipe)
2936 1.16 augustss {
2937 1.16 augustss struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;
2938 1.264.4.25 skrll struct usbd_device *dev = upipe->pipe.up_dev;
2939 1.264.4.7 skrll uhci_softc_t *sc = dev->ud_bus->ub_hcpriv;
2940 1.264.4.7 skrll int addr = upipe->pipe.up_dev->ud_addr;
2941 1.264.4.7 skrll int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
2942 1.45 augustss int rd = UE_GET_DIR(endpt) == UE_DIR_IN;
2943 1.48 augustss uhci_soft_td_t *std, *vstd;
2944 1.264.4.1 skrll uint32_t token;
2945 1.16 augustss struct iso *iso;
2946 1.248 mrg int i;
2947 1.16 augustss
2948 1.16 augustss iso = &upipe->u.iso;
2949 1.248 mrg iso->stds = kmem_alloc(UHCI_VFRAMELIST_COUNT *
2950 1.248 mrg sizeof (uhci_soft_td_t *),
2951 1.248 mrg KM_SLEEP);
2952 1.248 mrg if (iso->stds == NULL)
2953 1.248 mrg return USBD_NOMEM;
2954 1.16 augustss
2955 1.88 tsutsui token = rd ? UHCI_TD_IN (0, endpt, addr, 0) :
2956 1.88 tsutsui UHCI_TD_OUT(0, endpt, addr, 0);
2957 1.16 augustss
2958 1.248 mrg mutex_enter(&sc->sc_lock);
2959 1.248 mrg
2960 1.48 augustss /* Allocate the TDs and mark as inactive; */
2961 1.16 augustss for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
2962 1.48 augustss std = uhci_alloc_std(sc);
2963 1.48 augustss if (std == 0)
2964 1.48 augustss goto bad;
2965 1.88 tsutsui std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */
2966 1.88 tsutsui std->td.td_token = htole32(token);
2967 1.223 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
2968 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2969 1.48 augustss iso->stds[i] = std;
2970 1.16 augustss }
2971 1.16 augustss
2972 1.48 augustss /* Insert TDs into schedule. */
2973 1.16 augustss for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
2974 1.16 augustss std = iso->stds[i];
2975 1.48 augustss vstd = sc->sc_vframes[i].htd;
2976 1.223 bouyer usb_syncmem(&vstd->dma,
2977 1.223 bouyer vstd->offs + offsetof(uhci_td_t, td_link),
2978 1.223 bouyer sizeof(vstd->td.td_link),
2979 1.223 bouyer BUS_DMASYNC_POSTWRITE);
2980 1.42 augustss std->link = vstd->link;
2981 1.42 augustss std->td.td_link = vstd->td.td_link;
2982 1.223 bouyer usb_syncmem(&std->dma,
2983 1.223 bouyer std->offs + offsetof(uhci_td_t, td_link),
2984 1.223 bouyer sizeof(std->td.td_link),
2985 1.223 bouyer BUS_DMASYNC_PREWRITE);
2986 1.42 augustss vstd->link.std = std;
2987 1.121 augustss vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD);
2988 1.223 bouyer usb_syncmem(&vstd->dma,
2989 1.223 bouyer vstd->offs + offsetof(uhci_td_t, td_link),
2990 1.223 bouyer sizeof(vstd->td.td_link),
2991 1.223 bouyer BUS_DMASYNC_PREWRITE);
2992 1.16 augustss }
2993 1.248 mrg mutex_exit(&sc->sc_lock);
2994 1.16 augustss
2995 1.48 augustss iso->next = -1;
2996 1.48 augustss iso->inuse = 0;
2997 1.48 augustss
2998 1.264.4.13 skrll return USBD_NORMAL_COMPLETION;
2999 1.16 augustss
3000 1.48 augustss bad:
3001 1.16 augustss while (--i >= 0)
3002 1.16 augustss uhci_free_std(sc, iso->stds[i]);
3003 1.248 mrg mutex_exit(&sc->sc_lock);
3004 1.248 mrg kmem_free(iso->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *));
3005 1.264.4.13 skrll return USBD_NOMEM;
3006 1.16 augustss }
3007 1.16 augustss
3008 1.16 augustss void
3009 1.264.4.25 skrll uhci_device_isoc_done(struct usbd_xfer *xfer)
3010 1.16 augustss {
3011 1.92 augustss uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
3012 1.264.4.7 skrll struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
3013 1.223 bouyer int i, offs;
3014 1.264.4.7 skrll int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN;
3015 1.223 bouyer
3016 1.48 augustss
3017 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3018 1.264.4.21 skrll DPRINTFN(4, "length=%d, ux_state=0x%08x",
3019 1.264.4.21 skrll xfer->ux_actlen, xfer->ux_state, 0, 0);
3020 1.93 augustss
3021 1.96 augustss if (ii->xfer != xfer)
3022 1.96 augustss /* Not on interrupt list, ignore it. */
3023 1.170 augustss return;
3024 1.170 augustss
3025 1.170 augustss if (!uhci_active_intr_info(ii))
3026 1.96 augustss return;
3027 1.96 augustss
3028 1.93 augustss #ifdef DIAGNOSTIC
3029 1.264.4.2 skrll if (ii->stdend == NULL) {
3030 1.264.4.2 skrll printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer);
3031 1.93 augustss #ifdef UHCI_DEBUG
3032 1.93 augustss uhci_dump_ii(ii);
3033 1.93 augustss #endif
3034 1.93 augustss return;
3035 1.93 augustss }
3036 1.93 augustss #endif
3037 1.48 augustss
3038 1.48 augustss /* Turn off the interrupt since it is active even if the TD is not. */
3039 1.223 bouyer usb_syncmem(&ii->stdend->dma,
3040 1.223 bouyer ii->stdend->offs + offsetof(uhci_td_t, td_status),
3041 1.223 bouyer sizeof(ii->stdend->td.td_status),
3042 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3043 1.88 tsutsui ii->stdend->td.td_status &= htole32(~UHCI_TD_IOC);
3044 1.223 bouyer usb_syncmem(&ii->stdend->dma,
3045 1.223 bouyer ii->stdend->offs + offsetof(uhci_td_t, td_status),
3046 1.223 bouyer sizeof(ii->stdend->td.td_status),
3047 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3048 1.48 augustss
3049 1.92 augustss uhci_del_intr_info(ii); /* remove from active list */
3050 1.223 bouyer
3051 1.223 bouyer offs = 0;
3052 1.264.4.7 skrll for (i = 0; i < xfer->ux_nframes; i++) {
3053 1.264.4.7 skrll usb_syncmem(&xfer->ux_dmabuf, offs, xfer->ux_frlengths[i],
3054 1.223 bouyer rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
3055 1.264.4.7 skrll offs += xfer->ux_frlengths[i];
3056 1.223 bouyer }
3057 1.16 augustss }
3058 1.16 augustss
3059 1.1 augustss void
3060 1.264.4.25 skrll uhci_device_intr_done(struct usbd_xfer *xfer)
3061 1.1 augustss {
3062 1.92 augustss uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
3063 1.1 augustss uhci_softc_t *sc = ii->sc;
3064 1.264.4.7 skrll struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
3065 1.1 augustss uhci_soft_qh_t *sqh;
3066 1.223 bouyer int i, npoll, isread;
3067 1.1 augustss
3068 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3069 1.264.4.21 skrll DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0);
3070 1.1 augustss
3071 1.264.4.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
3072 1.248 mrg
3073 1.1 augustss npoll = upipe->u.intr.npoll;
3074 1.1 augustss for(i = 0; i < npoll; i++) {
3075 1.1 augustss sqh = upipe->u.intr.qhs[i];
3076 1.121 augustss sqh->elink = NULL;
3077 1.88 tsutsui sqh->qh.qh_elink = htole32(UHCI_PTR_T);
3078 1.223 bouyer usb_syncmem(&sqh->dma,
3079 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
3080 1.223 bouyer sizeof(sqh->qh.qh_elink),
3081 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3082 1.1 augustss }
3083 1.149 augustss uhci_free_std_chain(sc, ii->stdstart, NULL);
3084 1.1 augustss
3085 1.264.4.7 skrll isread = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN;
3086 1.264.4.7 skrll usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
3087 1.223 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
3088 1.223 bouyer
3089 1.1 augustss /* XXX Wasteful. */
3090 1.264.4.7 skrll if (xfer->ux_pipe->up_repeat) {
3091 1.55 augustss uhci_soft_td_t *data, *dataend;
3092 1.1 augustss
3093 1.264.4.21 skrll DPRINTFN(5, "re-queueing", 0, 0, 0, 0);
3094 1.92 augustss
3095 1.1 augustss /* This alloc cannot fail since we freed the chain above. */
3096 1.264.4.7 skrll uhci_alloc_std_chain(upipe, sc, xfer->ux_length,
3097 1.264.4.7 skrll upipe->u.intr.isread, xfer->ux_flags,
3098 1.264.4.7 skrll &xfer->ux_dmabuf, &data, &dataend);
3099 1.88 tsutsui dataend->td.td_status |= htole32(UHCI_TD_IOC);
3100 1.223 bouyer usb_syncmem(&dataend->dma,
3101 1.223 bouyer dataend->offs + offsetof(uhci_td_t, td_status),
3102 1.223 bouyer sizeof(dataend->td.td_status),
3103 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3104 1.1 augustss
3105 1.264.4.21 skrll DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0);
3106 1.59 augustss #ifdef UHCI_DEBUG
3107 1.1 augustss if (uhcidebug > 10) {
3108 1.55 augustss uhci_dump_tds(data);
3109 1.1 augustss uhci_dump_qh(upipe->u.intr.qhs[0]);
3110 1.1 augustss }
3111 1.1 augustss #endif
3112 1.264.4.21 skrll DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0);
3113 1.1 augustss
3114 1.55 augustss ii->stdstart = data;
3115 1.55 augustss ii->stdend = dataend;
3116 1.7 augustss #ifdef DIAGNOSTIC
3117 1.70 augustss if (!ii->isdone) {
3118 1.70 augustss printf("uhci_device_intr_done: not done, ii=%p\n", ii);
3119 1.70 augustss }
3120 1.7 augustss ii->isdone = 0;
3121 1.7 augustss #endif
3122 1.1 augustss for (i = 0; i < npoll; i++) {
3123 1.1 augustss sqh = upipe->u.intr.qhs[i];
3124 1.55 augustss sqh->elink = data;
3125 1.121 augustss sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD);
3126 1.223 bouyer usb_syncmem(&sqh->dma,
3127 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
3128 1.223 bouyer sizeof(sqh->qh.qh_elink),
3129 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3130 1.1 augustss }
3131 1.264.4.7 skrll xfer->ux_status = USBD_IN_PROGRESS;
3132 1.92 augustss /* The ii is already on the examined list, just leave it. */
3133 1.1 augustss } else {
3134 1.264.4.21 skrll DPRINTFN(5, "removing", 0, 0, 0, 0);
3135 1.169 augustss if (uhci_active_intr_info(ii))
3136 1.169 augustss uhci_del_intr_info(ii);
3137 1.1 augustss }
3138 1.1 augustss }
3139 1.1 augustss
3140 1.1 augustss /* Deallocate request data structures */
3141 1.1 augustss void
3142 1.264.4.25 skrll uhci_device_ctrl_done(struct usbd_xfer *xfer)
3143 1.1 augustss {
3144 1.92 augustss uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
3145 1.1 augustss uhci_softc_t *sc = ii->sc;
3146 1.264.4.7 skrll struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
3147 1.264.4.7 skrll int len = UGETW(xfer->ux_request.wLength);
3148 1.264.4.7 skrll int isread = (xfer->ux_request.bmRequestType & UT_READ);
3149 1.1 augustss
3150 1.264.4.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
3151 1.248 mrg
3152 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3153 1.7 augustss #ifdef DIAGNOSTIC
3154 1.264.4.7 skrll if (!(xfer->ux_rqflags & URQ_REQUEST))
3155 1.173 gson panic("uhci_device_ctrl_done: not a request");
3156 1.7 augustss #endif
3157 1.1 augustss
3158 1.169 augustss if (!uhci_active_intr_info(ii))
3159 1.169 augustss return;
3160 1.169 augustss
3161 1.92 augustss uhci_del_intr_info(ii); /* remove from active list */
3162 1.1 augustss
3163 1.264.4.7 skrll if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW)
3164 1.123 augustss uhci_remove_ls_ctrl(sc, upipe->u.ctl.sqh);
3165 1.123 augustss else
3166 1.123 augustss uhci_remove_hs_ctrl(sc, upipe->u.ctl.sqh);
3167 1.1 augustss
3168 1.49 augustss if (upipe->u.ctl.length != 0)
3169 1.42 augustss uhci_free_std_chain(sc, ii->stdstart->link.std, ii->stdend);
3170 1.49 augustss
3171 1.223 bouyer if (len) {
3172 1.264.4.7 skrll usb_syncmem(&xfer->ux_dmabuf, 0, len,
3173 1.223 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
3174 1.223 bouyer }
3175 1.223 bouyer usb_syncmem(&upipe->u.ctl.reqdma, 0,
3176 1.223 bouyer sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE);
3177 1.223 bouyer
3178 1.264.4.27 skrll DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0);
3179 1.1 augustss }
3180 1.1 augustss
3181 1.1 augustss /* Deallocate request data structures */
3182 1.1 augustss void
3183 1.264.4.25 skrll uhci_device_bulk_done(struct usbd_xfer *xfer)
3184 1.1 augustss {
3185 1.92 augustss uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
3186 1.1 augustss uhci_softc_t *sc = ii->sc;
3187 1.264.4.7 skrll struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe;
3188 1.169 augustss
3189 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3190 1.264.4.21 skrll DPRINTFN(5, "xfer=%p ii=%p sc=%p upipe=%p", xfer, ii, sc,
3191 1.264.4.21 skrll upipe);
3192 1.169 augustss
3193 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
3194 1.248 mrg
3195 1.169 augustss if (!uhci_active_intr_info(ii))
3196 1.169 augustss return;
3197 1.1 augustss
3198 1.92 augustss uhci_del_intr_info(ii); /* remove from active list */
3199 1.1 augustss
3200 1.1 augustss uhci_remove_bulk(sc, upipe->u.bulk.sqh);
3201 1.32 augustss
3202 1.149 augustss uhci_free_std_chain(sc, ii->stdstart, NULL);
3203 1.32 augustss
3204 1.264.4.21 skrll DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0);
3205 1.1 augustss }
3206 1.1 augustss
3207 1.1 augustss /* Add interrupt QH, called with vflock. */
3208 1.1 augustss void
3209 1.119 augustss uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
3210 1.1 augustss {
3211 1.92 augustss struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos];
3212 1.42 augustss uhci_soft_qh_t *eqh;
3213 1.1 augustss
3214 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3215 1.264.4.21 skrll DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0);
3216 1.92 augustss
3217 1.42 augustss eqh = vf->eqh;
3218 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
3219 1.223 bouyer sizeof(eqh->qh.qh_hlink),
3220 1.223 bouyer BUS_DMASYNC_POSTWRITE);
3221 1.42 augustss sqh->hlink = eqh->hlink;
3222 1.42 augustss sqh->qh.qh_hlink = eqh->qh.qh_hlink;
3223 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
3224 1.223 bouyer sizeof(sqh->qh.qh_hlink),
3225 1.223 bouyer BUS_DMASYNC_PREWRITE);
3226 1.42 augustss eqh->hlink = sqh;
3227 1.121 augustss eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
3228 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
3229 1.223 bouyer sizeof(eqh->qh.qh_hlink),
3230 1.223 bouyer BUS_DMASYNC_PREWRITE);
3231 1.1 augustss vf->eqh = sqh;
3232 1.1 augustss vf->bandwidth++;
3233 1.1 augustss }
3234 1.1 augustss
3235 1.119 augustss /* Remove interrupt QH. */
3236 1.1 augustss void
3237 1.119 augustss uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
3238 1.1 augustss {
3239 1.92 augustss struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos];
3240 1.1 augustss uhci_soft_qh_t *pqh;
3241 1.1 augustss
3242 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3243 1.264.4.21 skrll DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0);
3244 1.1 augustss
3245 1.124 augustss /* See comment in uhci_remove_ctrl() */
3246 1.223 bouyer
3247 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
3248 1.223 bouyer sizeof(sqh->qh.qh_elink),
3249 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3250 1.124 augustss if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) {
3251 1.124 augustss sqh->qh.qh_elink = htole32(UHCI_PTR_T);
3252 1.223 bouyer usb_syncmem(&sqh->dma,
3253 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
3254 1.223 bouyer sizeof(sqh->qh.qh_elink),
3255 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3256 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
3257 1.124 augustss }
3258 1.124 augustss
3259 1.92 augustss pqh = uhci_find_prev_qh(vf->hqh, sqh);
3260 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
3261 1.223 bouyer sizeof(sqh->qh.qh_hlink),
3262 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3263 1.42 augustss pqh->hlink = sqh->hlink;
3264 1.42 augustss pqh->qh.qh_hlink = sqh->qh.qh_hlink;
3265 1.223 bouyer usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
3266 1.223 bouyer sizeof(pqh->qh.qh_hlink),
3267 1.223 bouyer BUS_DMASYNC_PREWRITE);
3268 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
3269 1.1 augustss if (vf->eqh == sqh)
3270 1.1 augustss vf->eqh = pqh;
3271 1.1 augustss vf->bandwidth--;
3272 1.1 augustss }
3273 1.1 augustss
3274 1.1 augustss usbd_status
3275 1.119 augustss uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival)
3276 1.1 augustss {
3277 1.1 augustss uhci_soft_qh_t *sqh;
3278 1.248 mrg int i, npoll;
3279 1.1 augustss u_int bestbw, bw, bestoffs, offs;
3280 1.1 augustss
3281 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3282 1.264.4.21 skrll DPRINTFN(2, "pipe=%p", upipe, 0, 0, 0);
3283 1.1 augustss if (ival == 0) {
3284 1.173 gson printf("uhci_device_setintr: 0 interval\n");
3285 1.264.4.13 skrll return USBD_INVAL;
3286 1.1 augustss }
3287 1.1 augustss
3288 1.1 augustss if (ival > UHCI_VFRAMELIST_COUNT)
3289 1.1 augustss ival = UHCI_VFRAMELIST_COUNT;
3290 1.1 augustss npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival;
3291 1.264.4.27 skrll DPRINTF("ival=%d npoll=%d", ival, npoll, 0, 0);
3292 1.1 augustss
3293 1.1 augustss upipe->u.intr.npoll = npoll;
3294 1.152 augustss upipe->u.intr.qhs =
3295 1.248 mrg kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP);
3296 1.248 mrg if (upipe->u.intr.qhs == NULL)
3297 1.248 mrg return USBD_NOMEM;
3298 1.1 augustss
3299 1.152 augustss /*
3300 1.1 augustss * Figure out which offset in the schedule that has most
3301 1.1 augustss * bandwidth left over.
3302 1.1 augustss */
3303 1.1 augustss #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1))
3304 1.1 augustss for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) {
3305 1.1 augustss for (bw = i = 0; i < npoll; i++)
3306 1.1 augustss bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth;
3307 1.1 augustss if (bw < bestbw) {
3308 1.1 augustss bestbw = bw;
3309 1.1 augustss bestoffs = offs;
3310 1.1 augustss }
3311 1.1 augustss }
3312 1.264.4.27 skrll DPRINTF("bw=%d offs=%d", bestbw, bestoffs, 0, 0);
3313 1.248 mrg mutex_enter(&sc->sc_lock);
3314 1.1 augustss for(i = 0; i < npoll; i++) {
3315 1.1 augustss upipe->u.intr.qhs[i] = sqh = uhci_alloc_sqh(sc);
3316 1.121 augustss sqh->elink = NULL;
3317 1.88 tsutsui sqh->qh.qh_elink = htole32(UHCI_PTR_T);
3318 1.223 bouyer usb_syncmem(&sqh->dma,
3319 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
3320 1.223 bouyer sizeof(sqh->qh.qh_elink),
3321 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3322 1.1 augustss sqh->pos = MOD(i * ival + bestoffs);
3323 1.1 augustss }
3324 1.1 augustss #undef MOD
3325 1.1 augustss
3326 1.1 augustss /* Enter QHs into the controller data structures. */
3327 1.1 augustss for(i = 0; i < npoll; i++)
3328 1.92 augustss uhci_add_intr(sc, upipe->u.intr.qhs[i]);
3329 1.248 mrg mutex_exit(&sc->sc_lock);
3330 1.1 augustss
3331 1.264.4.21 skrll DPRINTFN(5, "returns %p", upipe, 0, 0, 0);
3332 1.264.4.21 skrll
3333 1.264.4.13 skrll return USBD_NORMAL_COMPLETION;
3334 1.1 augustss }
3335 1.1 augustss
3336 1.1 augustss /* Open a new pipe. */
3337 1.1 augustss usbd_status
3338 1.264.4.25 skrll uhci_open(struct usbd_pipe *pipe)
3339 1.1 augustss {
3340 1.264.4.7 skrll uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv;
3341 1.264.4.12 skrll struct usbd_bus *bus = pipe->up_dev->ud_bus;
3342 1.1 augustss struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;
3343 1.264.4.7 skrll usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc;
3344 1.248 mrg usbd_status err = USBD_NOMEM;
3345 1.79 augustss int ival;
3346 1.1 augustss
3347 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3348 1.264.4.27 skrll DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)",
3349 1.264.4.21 skrll pipe, pipe->up_dev->ud_addr, ed->bEndpointAddress, bus->ub_rhaddr);
3350 1.92 augustss
3351 1.248 mrg if (sc->sc_dying)
3352 1.248 mrg return USBD_IOERROR;
3353 1.248 mrg
3354 1.92 augustss upipe->aborting = 0;
3355 1.236 drochner /* toggle state needed for bulk endpoints */
3356 1.264.4.7 skrll upipe->nexttoggle = pipe->up_endpoint->ue_toggle;
3357 1.92 augustss
3358 1.264.4.12 skrll if (pipe->up_dev->ud_addr == bus->ub_rhaddr) {
3359 1.1 augustss switch (ed->bEndpointAddress) {
3360 1.1 augustss case USB_CONTROL_ENDPOINT:
3361 1.264.4.12 skrll pipe->up_methods = &roothub_ctrl_methods;
3362 1.1 augustss break;
3363 1.264.4.12 skrll case UE_DIR_IN | USBROOTHUB_INTR_ENDPT:
3364 1.264.4.7 skrll pipe->up_methods = &uhci_root_intr_methods;
3365 1.1 augustss break;
3366 1.1 augustss default:
3367 1.264.4.13 skrll return USBD_INVAL;
3368 1.1 augustss }
3369 1.1 augustss } else {
3370 1.1 augustss switch (ed->bmAttributes & UE_XFERTYPE) {
3371 1.1 augustss case UE_CONTROL:
3372 1.264.4.7 skrll pipe->up_methods = &uhci_device_ctrl_methods;
3373 1.1 augustss upipe->u.ctl.sqh = uhci_alloc_sqh(sc);
3374 1.63 augustss if (upipe->u.ctl.sqh == NULL)
3375 1.5 augustss goto bad;
3376 1.1 augustss upipe->u.ctl.setup = uhci_alloc_std(sc);
3377 1.63 augustss if (upipe->u.ctl.setup == NULL) {
3378 1.5 augustss uhci_free_sqh(sc, upipe->u.ctl.sqh);
3379 1.5 augustss goto bad;
3380 1.5 augustss }
3381 1.1 augustss upipe->u.ctl.stat = uhci_alloc_std(sc);
3382 1.63 augustss if (upipe->u.ctl.stat == NULL) {
3383 1.5 augustss uhci_free_sqh(sc, upipe->u.ctl.sqh);
3384 1.5 augustss uhci_free_std(sc, upipe->u.ctl.setup);
3385 1.5 augustss goto bad;
3386 1.5 augustss }
3387 1.152 augustss err = usb_allocmem(&sc->sc_bus,
3388 1.152 augustss sizeof(usb_device_request_t),
3389 1.63 augustss 0, &upipe->u.ctl.reqdma);
3390 1.63 augustss if (err) {
3391 1.5 augustss uhci_free_sqh(sc, upipe->u.ctl.sqh);
3392 1.5 augustss uhci_free_std(sc, upipe->u.ctl.setup);
3393 1.5 augustss uhci_free_std(sc, upipe->u.ctl.stat);
3394 1.5 augustss goto bad;
3395 1.5 augustss }
3396 1.1 augustss break;
3397 1.1 augustss case UE_INTERRUPT:
3398 1.264.4.7 skrll pipe->up_methods = &uhci_device_intr_methods;
3399 1.264.4.7 skrll ival = pipe->up_interval;
3400 1.79 augustss if (ival == USBD_DEFAULT_INTERVAL)
3401 1.79 augustss ival = ed->bInterval;
3402 1.264.4.13 skrll return uhci_device_setintr(sc, upipe, ival);
3403 1.1 augustss case UE_ISOCHRONOUS:
3404 1.264.4.7 skrll pipe->up_methods = &uhci_device_isoc_methods;
3405 1.264.4.13 skrll return uhci_setup_isoc(pipe);
3406 1.1 augustss case UE_BULK:
3407 1.264.4.7 skrll pipe->up_methods = &uhci_device_bulk_methods;
3408 1.1 augustss upipe->u.bulk.sqh = uhci_alloc_sqh(sc);
3409 1.63 augustss if (upipe->u.bulk.sqh == NULL)
3410 1.5 augustss goto bad;
3411 1.1 augustss break;
3412 1.1 augustss }
3413 1.1 augustss }
3414 1.264.4.13 skrll return USBD_NORMAL_COMPLETION;
3415 1.5 augustss
3416 1.5 augustss bad:
3417 1.248 mrg return USBD_NOMEM;
3418 1.1 augustss }
3419 1.1 augustss
3420 1.1 augustss /*
3421 1.1 augustss * Data structures and routines to emulate the root hub.
3422 1.1 augustss */
3423 1.1 augustss /*
3424 1.166 dsainty * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also
3425 1.166 dsainty * enables the port, and also states that SET_FEATURE(PORT_ENABLE)
3426 1.166 dsainty * should not be used by the USB subsystem. As we cannot issue a
3427 1.166 dsainty * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port
3428 1.166 dsainty * will be enabled as part of the reset.
3429 1.166 dsainty *
3430 1.166 dsainty * On the VT83C572, the port cannot be successfully enabled until the
3431 1.166 dsainty * outstanding "port enable change" and "connection status change"
3432 1.166 dsainty * events have been reset.
3433 1.166 dsainty */
3434 1.166 dsainty Static usbd_status
3435 1.166 dsainty uhci_portreset(uhci_softc_t *sc, int index)
3436 1.166 dsainty {
3437 1.166 dsainty int lim, port, x;
3438 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3439 1.166 dsainty
3440 1.166 dsainty if (index == 1)
3441 1.166 dsainty port = UHCI_PORTSC1;
3442 1.166 dsainty else if (index == 2)
3443 1.166 dsainty port = UHCI_PORTSC2;
3444 1.166 dsainty else
3445 1.264.4.13 skrll return USBD_IOERROR;
3446 1.166 dsainty
3447 1.166 dsainty x = URWMASK(UREAD2(sc, port));
3448 1.166 dsainty UWRITE2(sc, port, x | UHCI_PORTSC_PR);
3449 1.166 dsainty
3450 1.166 dsainty usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY);
3451 1.166 dsainty
3452 1.264.4.27 skrll DPRINTF("uhci port %d reset, status0 = 0x%04x", index,
3453 1.264.4.21 skrll UREAD2(sc, port), 0, 0);
3454 1.166 dsainty
3455 1.166 dsainty x = URWMASK(UREAD2(sc, port));
3456 1.222 drochner UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP));
3457 1.166 dsainty
3458 1.166 dsainty delay(100);
3459 1.166 dsainty
3460 1.264.4.27 skrll DPRINTF("uhci port %d reset, status1 = 0x%04x", index,
3461 1.264.4.21 skrll UREAD2(sc, port), 0, 0);
3462 1.166 dsainty
3463 1.166 dsainty x = URWMASK(UREAD2(sc, port));
3464 1.166 dsainty UWRITE2(sc, port, x | UHCI_PORTSC_PE);
3465 1.166 dsainty
3466 1.166 dsainty for (lim = 10; --lim > 0;) {
3467 1.166 dsainty usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY);
3468 1.166 dsainty
3469 1.166 dsainty x = UREAD2(sc, port);
3470 1.264.4.27 skrll DPRINTF("uhci port %d iteration %u, status = 0x%04x", index,
3471 1.264.4.21 skrll lim, x, 0);
3472 1.166 dsainty
3473 1.166 dsainty if (!(x & UHCI_PORTSC_CCS)) {
3474 1.166 dsainty /*
3475 1.166 dsainty * No device is connected (or was disconnected
3476 1.166 dsainty * during reset). Consider the port reset.
3477 1.166 dsainty * The delay must be long enough to ensure on
3478 1.166 dsainty * the initial iteration that the device
3479 1.166 dsainty * connection will have been registered. 50ms
3480 1.166 dsainty * appears to be sufficient, but 20ms is not.
3481 1.166 dsainty */
3482 1.264.4.21 skrll DPRINTFN(3, "uhci port %d loop %u, device detached",
3483 1.264.4.21 skrll index, lim, 0, 0);
3484 1.166 dsainty break;
3485 1.166 dsainty }
3486 1.166 dsainty
3487 1.166 dsainty if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) {
3488 1.166 dsainty /*
3489 1.166 dsainty * Port enabled changed and/or connection
3490 1.166 dsainty * status changed were set. Reset either or
3491 1.166 dsainty * both raised flags (by writing a 1 to that
3492 1.166 dsainty * bit), and wait again for state to settle.
3493 1.166 dsainty */
3494 1.166 dsainty UWRITE2(sc, port, URWMASK(x) |
3495 1.166 dsainty (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)));
3496 1.166 dsainty continue;
3497 1.166 dsainty }
3498 1.166 dsainty
3499 1.166 dsainty if (x & UHCI_PORTSC_PE)
3500 1.166 dsainty /* Port is enabled */
3501 1.166 dsainty break;
3502 1.166 dsainty
3503 1.166 dsainty UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE);
3504 1.166 dsainty }
3505 1.166 dsainty
3506 1.264.4.21 skrll DPRINTFN(3, "uhci port %d reset, status2 = 0x%04x", index,
3507 1.264.4.21 skrll UREAD2(sc, port), 0, 0);
3508 1.166 dsainty
3509 1.166 dsainty if (lim <= 0) {
3510 1.264.4.27 skrll DPRINTF("uhci port %d reset timed out", index,
3511 1.264.4.21 skrll 0, 0, 0);
3512 1.264.4.13 skrll return USBD_TIMEOUT;
3513 1.166 dsainty }
3514 1.184 perry
3515 1.166 dsainty sc->sc_isreset = 1;
3516 1.264.4.13 skrll return USBD_NORMAL_COMPLETION;
3517 1.166 dsainty }
3518 1.166 dsainty
3519 1.264.4.12 skrll Static int
3520 1.264.4.12 skrll uhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req,
3521 1.264.4.12 skrll void *buf, int buflen)
3522 1.1 augustss {
3523 1.264.4.12 skrll uhci_softc_t *sc = bus->ub_hcpriv;
3524 1.1 augustss int port, x;
3525 1.264.4.12 skrll int status, change, totlen = 0;
3526 1.264.4.12 skrll uint16_t len, value, index;
3527 1.1 augustss usb_port_status_t ps;
3528 1.63 augustss usbd_status err;
3529 1.1 augustss
3530 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3531 1.264.4.21 skrll
3532 1.82 augustss if (sc->sc_dying)
3533 1.264.4.12 skrll return -1;
3534 1.1 augustss
3535 1.264.4.27 skrll DPRINTF("type=0x%02x request=%02x", req->bmRequestType,
3536 1.264.4.21 skrll req->bRequest, 0, 0);
3537 1.1 augustss
3538 1.1 augustss len = UGETW(req->wLength);
3539 1.1 augustss value = UGETW(req->wValue);
3540 1.1 augustss index = UGETW(req->wIndex);
3541 1.49 augustss
3542 1.1 augustss #define C(x,y) ((x) | ((y) << 8))
3543 1.264.4.12 skrll switch (C(req->bRequest, req->bmRequestType)) {
3544 1.1 augustss case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3545 1.264.4.27 skrll DPRINTF("wValue=0x%04x", value, 0, 0, 0);
3546 1.195 christos if (len == 0)
3547 1.195 christos break;
3548 1.264.4.12 skrll switch (value) {
3549 1.264.4.12 skrll case C(0, UDESC_DEVICE): {
3550 1.264.4.12 skrll usb_device_descriptor_t devd;
3551 1.264.4.12 skrll
3552 1.264.4.12 skrll totlen = min(buflen, sizeof(devd));
3553 1.264.4.12 skrll memcpy(&devd, buf, totlen);
3554 1.264.4.12 skrll USETW(devd.idVendor, sc->sc_id_vendor);
3555 1.264.4.12 skrll memcpy(buf, &devd, totlen);
3556 1.1 augustss break;
3557 1.264.4.12 skrll }
3558 1.264.4.12 skrll case C(1, UDESC_STRING):
3559 1.213 drochner #define sd ((usb_string_descriptor_t *)buf)
3560 1.264.4.12 skrll /* Vendor */
3561 1.264.4.12 skrll totlen = usb_makestrdesc(sd, len, sc->sc_vendor);
3562 1.264.4.12 skrll break;
3563 1.264.4.12 skrll case C(2, UDESC_STRING):
3564 1.264.4.12 skrll /* Product */
3565 1.264.4.12 skrll totlen = usb_makestrdesc(sd, len, "UHCI root hub");
3566 1.1 augustss break;
3567 1.264.4.12 skrll #undef sd
3568 1.1 augustss default:
3569 1.264.4.12 skrll /* default from usbroothub */
3570 1.264.4.12 skrll return buflen;
3571 1.1 augustss }
3572 1.1 augustss break;
3573 1.264.4.12 skrll
3574 1.1 augustss /* Hub requests */
3575 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3576 1.1 augustss break;
3577 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3578 1.264.4.27 skrll DPRINTF("UR_CLEAR_PORT_FEATURE port=%d feature=%d", index,
3579 1.264.4.21 skrll value, 0, 0);
3580 1.1 augustss if (index == 1)
3581 1.1 augustss port = UHCI_PORTSC1;
3582 1.1 augustss else if (index == 2)
3583 1.1 augustss port = UHCI_PORTSC2;
3584 1.1 augustss else {
3585 1.264.4.12 skrll return -1;
3586 1.1 augustss }
3587 1.1 augustss switch(value) {
3588 1.1 augustss case UHF_PORT_ENABLE:
3589 1.137 augustss x = URWMASK(UREAD2(sc, port));
3590 1.1 augustss UWRITE2(sc, port, x & ~UHCI_PORTSC_PE);
3591 1.1 augustss break;
3592 1.1 augustss case UHF_PORT_SUSPEND:
3593 1.137 augustss x = URWMASK(UREAD2(sc, port));
3594 1.222 drochner if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */
3595 1.222 drochner break;
3596 1.222 drochner UWRITE2(sc, port, x | UHCI_PORTSC_RD);
3597 1.222 drochner /* see USB2 spec ch. 7.1.7.7 */
3598 1.222 drochner usb_delay_ms(&sc->sc_bus, 20);
3599 1.1 augustss UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP);
3600 1.222 drochner /* 10ms resume delay must be provided by caller */
3601 1.1 augustss break;
3602 1.1 augustss case UHF_PORT_RESET:
3603 1.137 augustss x = URWMASK(UREAD2(sc, port));
3604 1.1 augustss UWRITE2(sc, port, x & ~UHCI_PORTSC_PR);
3605 1.1 augustss break;
3606 1.1 augustss case UHF_C_PORT_CONNECTION:
3607 1.137 augustss x = URWMASK(UREAD2(sc, port));
3608 1.1 augustss UWRITE2(sc, port, x | UHCI_PORTSC_CSC);
3609 1.1 augustss break;
3610 1.1 augustss case UHF_C_PORT_ENABLE:
3611 1.137 augustss x = URWMASK(UREAD2(sc, port));
3612 1.1 augustss UWRITE2(sc, port, x | UHCI_PORTSC_POEDC);
3613 1.1 augustss break;
3614 1.1 augustss case UHF_C_PORT_OVER_CURRENT:
3615 1.137 augustss x = URWMASK(UREAD2(sc, port));
3616 1.1 augustss UWRITE2(sc, port, x | UHCI_PORTSC_OCIC);
3617 1.1 augustss break;
3618 1.1 augustss case UHF_C_PORT_RESET:
3619 1.1 augustss sc->sc_isreset = 0;
3620 1.264.4.16 skrll break;
3621 1.1 augustss case UHF_PORT_CONNECTION:
3622 1.1 augustss case UHF_PORT_OVER_CURRENT:
3623 1.1 augustss case UHF_PORT_POWER:
3624 1.1 augustss case UHF_PORT_LOW_SPEED:
3625 1.1 augustss case UHF_C_PORT_SUSPEND:
3626 1.1 augustss default:
3627 1.264.4.12 skrll return -1;
3628 1.1 augustss }
3629 1.1 augustss break;
3630 1.1 augustss case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER):
3631 1.1 augustss if (index == 1)
3632 1.1 augustss port = UHCI_PORTSC1;
3633 1.1 augustss else if (index == 2)
3634 1.1 augustss port = UHCI_PORTSC2;
3635 1.1 augustss else {
3636 1.264.4.12 skrll return -1;
3637 1.1 augustss }
3638 1.1 augustss if (len > 0) {
3639 1.264.4.1 skrll *(uint8_t *)buf =
3640 1.1 augustss (UREAD2(sc, port) & UHCI_PORTSC_LS) >>
3641 1.1 augustss UHCI_PORTSC_LS_SHIFT;
3642 1.1 augustss totlen = 1;
3643 1.1 augustss }
3644 1.1 augustss break;
3645 1.1 augustss case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3646 1.195 christos if (len == 0)
3647 1.195 christos break;
3648 1.177 toshii if ((value & 0xff) != 0) {
3649 1.264.4.12 skrll return -1;
3650 1.1 augustss }
3651 1.264.4.12 skrll usb_hub_descriptor_t hubd;
3652 1.264.4.12 skrll
3653 1.264.4.12 skrll totlen = min(buflen, sizeof(hubd));
3654 1.264.4.12 skrll memcpy(&hubd, buf, totlen);
3655 1.264.4.12 skrll hubd.bNbrPorts = 2;
3656 1.264.4.12 skrll memcpy(buf, &hubd, totlen);
3657 1.1 augustss break;
3658 1.1 augustss case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3659 1.1 augustss if (len != 4) {
3660 1.264.4.12 skrll return -1;
3661 1.1 augustss }
3662 1.1 augustss memset(buf, 0, len);
3663 1.1 augustss totlen = len;
3664 1.1 augustss break;
3665 1.1 augustss case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3666 1.1 augustss if (index == 1)
3667 1.1 augustss port = UHCI_PORTSC1;
3668 1.1 augustss else if (index == 2)
3669 1.1 augustss port = UHCI_PORTSC2;
3670 1.1 augustss else {
3671 1.264.4.12 skrll return -1;
3672 1.1 augustss }
3673 1.1 augustss if (len != 4) {
3674 1.264.4.12 skrll return -1;
3675 1.1 augustss }
3676 1.1 augustss x = UREAD2(sc, port);
3677 1.1 augustss status = change = 0;
3678 1.142 augustss if (x & UHCI_PORTSC_CCS)
3679 1.1 augustss status |= UPS_CURRENT_CONNECT_STATUS;
3680 1.152 augustss if (x & UHCI_PORTSC_CSC)
3681 1.1 augustss change |= UPS_C_CONNECT_STATUS;
3682 1.152 augustss if (x & UHCI_PORTSC_PE)
3683 1.1 augustss status |= UPS_PORT_ENABLED;
3684 1.152 augustss if (x & UHCI_PORTSC_POEDC)
3685 1.1 augustss change |= UPS_C_PORT_ENABLED;
3686 1.152 augustss if (x & UHCI_PORTSC_OCI)
3687 1.1 augustss status |= UPS_OVERCURRENT_INDICATOR;
3688 1.152 augustss if (x & UHCI_PORTSC_OCIC)
3689 1.1 augustss change |= UPS_C_OVERCURRENT_INDICATOR;
3690 1.152 augustss if (x & UHCI_PORTSC_SUSP)
3691 1.1 augustss status |= UPS_SUSPEND;
3692 1.152 augustss if (x & UHCI_PORTSC_LSDA)
3693 1.1 augustss status |= UPS_LOW_SPEED;
3694 1.1 augustss status |= UPS_PORT_POWER;
3695 1.1 augustss if (sc->sc_isreset)
3696 1.1 augustss change |= UPS_C_PORT_RESET;
3697 1.1 augustss USETW(ps.wPortStatus, status);
3698 1.1 augustss USETW(ps.wPortChange, change);
3699 1.264.4.12 skrll totlen = min(len, sizeof(ps));
3700 1.264.4.12 skrll memcpy(buf, &ps, totlen);
3701 1.1 augustss break;
3702 1.1 augustss case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3703 1.264.4.12 skrll return -1;
3704 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3705 1.1 augustss break;
3706 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3707 1.1 augustss if (index == 1)
3708 1.1 augustss port = UHCI_PORTSC1;
3709 1.1 augustss else if (index == 2)
3710 1.1 augustss port = UHCI_PORTSC2;
3711 1.1 augustss else {
3712 1.264.4.12 skrll return -1;
3713 1.1 augustss }
3714 1.1 augustss switch(value) {
3715 1.1 augustss case UHF_PORT_ENABLE:
3716 1.137 augustss x = URWMASK(UREAD2(sc, port));
3717 1.1 augustss UWRITE2(sc, port, x | UHCI_PORTSC_PE);
3718 1.1 augustss break;
3719 1.1 augustss case UHF_PORT_SUSPEND:
3720 1.137 augustss x = URWMASK(UREAD2(sc, port));
3721 1.1 augustss UWRITE2(sc, port, x | UHCI_PORTSC_SUSP);
3722 1.1 augustss break;
3723 1.1 augustss case UHF_PORT_RESET:
3724 1.166 dsainty err = uhci_portreset(sc, index);
3725 1.264.4.12 skrll if (err != USBD_NORMAL_COMPLETION)
3726 1.264.4.12 skrll return -1;
3727 1.264.4.12 skrll return 0;
3728 1.111 augustss case UHF_PORT_POWER:
3729 1.111 augustss /* Pretend we turned on power */
3730 1.264.4.12 skrll return 0;
3731 1.1 augustss case UHF_C_PORT_CONNECTION:
3732 1.1 augustss case UHF_C_PORT_ENABLE:
3733 1.1 augustss case UHF_C_PORT_OVER_CURRENT:
3734 1.1 augustss case UHF_PORT_CONNECTION:
3735 1.1 augustss case UHF_PORT_OVER_CURRENT:
3736 1.1 augustss case UHF_PORT_LOW_SPEED:
3737 1.1 augustss case UHF_C_PORT_SUSPEND:
3738 1.1 augustss case UHF_C_PORT_RESET:
3739 1.1 augustss default:
3740 1.264.4.12 skrll return -1;
3741 1.1 augustss }
3742 1.1 augustss break;
3743 1.1 augustss default:
3744 1.264.4.12 skrll /* default from usbroothub */
3745 1.264.4.27 skrll DPRINTF("returning %d (usbroothub default)",
3746 1.264.4.21 skrll buflen, 0, 0, 0);
3747 1.264.4.12 skrll return buflen;
3748 1.1 augustss }
3749 1.1 augustss
3750 1.264.4.27 skrll DPRINTF("returning %d", totlen, 0, 0, 0);
3751 1.264.4.21 skrll
3752 1.264.4.12 skrll return totlen;
3753 1.1 augustss }
3754 1.1 augustss
3755 1.1 augustss /* Abort a root interrupt request. */
3756 1.1 augustss void
3757 1.264.4.25 skrll uhci_root_intr_abort(struct usbd_xfer *xfer)
3758 1.1 augustss {
3759 1.264.4.7 skrll uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
3760 1.30 augustss
3761 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
3762 1.264.4.7 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
3763 1.248 mrg
3764 1.234 dyoung callout_stop(&sc->sc_poll_handle);
3765 1.96 augustss sc->sc_intr_xfer = NULL;
3766 1.58 augustss
3767 1.264.4.7 skrll xfer->ux_status = USBD_CANCELLED;
3768 1.96 augustss #ifdef DIAGNOSTIC
3769 1.96 augustss UXFER(xfer)->iinfo.isdone = 1;
3770 1.96 augustss #endif
3771 1.63 augustss usb_transfer_complete(xfer);
3772 1.1 augustss }
3773 1.1 augustss
3774 1.16 augustss usbd_status
3775 1.264.4.25 skrll uhci_root_intr_transfer(struct usbd_xfer *xfer)
3776 1.16 augustss {
3777 1.264.4.7 skrll uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
3778 1.63 augustss usbd_status err;
3779 1.16 augustss
3780 1.52 augustss /* Insert last in queue. */
3781 1.248 mrg mutex_enter(&sc->sc_lock);
3782 1.63 augustss err = usb_insert_transfer(xfer);
3783 1.248 mrg mutex_exit(&sc->sc_lock);
3784 1.63 augustss if (err)
3785 1.264.4.13 skrll return err;
3786 1.52 augustss
3787 1.186 skrll /*
3788 1.186 skrll * Pipe isn't running (otherwise err would be USBD_INPROG),
3789 1.67 augustss * start first
3790 1.67 augustss */
3791 1.264.4.13 skrll return uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
3792 1.16 augustss }
3793 1.16 augustss
3794 1.1 augustss /* Start a transfer on the root interrupt pipe */
3795 1.1 augustss usbd_status
3796 1.264.4.25 skrll uhci_root_intr_start(struct usbd_xfer *xfer)
3797 1.1 augustss {
3798 1.264.4.25 skrll struct usbd_pipe *pipe = xfer->ux_pipe;
3799 1.264.4.7 skrll uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv;
3800 1.174 drochner unsigned int ival;
3801 1.1 augustss
3802 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3803 1.264.4.27 skrll DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length,
3804 1.264.4.21 skrll xfer->ux_flags, 0);
3805 1.82 augustss
3806 1.82 augustss if (sc->sc_dying)
3807 1.264.4.13 skrll return USBD_IOERROR;
3808 1.1 augustss
3809 1.174 drochner /* XXX temporary variable needed to avoid gcc3 warning */
3810 1.264.4.7 skrll ival = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval;
3811 1.174 drochner sc->sc_ival = mstohz(ival);
3812 1.234 dyoung callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer);
3813 1.96 augustss sc->sc_intr_xfer = xfer;
3814 1.264.4.13 skrll return USBD_IN_PROGRESS;
3815 1.1 augustss }
3816 1.1 augustss
3817 1.1 augustss /* Close the root interrupt pipe. */
3818 1.1 augustss void
3819 1.264.4.25 skrll uhci_root_intr_close(struct usbd_pipe *pipe)
3820 1.1 augustss {
3821 1.264.4.7 skrll uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv;
3822 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3823 1.30 augustss
3824 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
3825 1.248 mrg
3826 1.234 dyoung callout_stop(&sc->sc_poll_handle);
3827 1.96 augustss sc->sc_intr_xfer = NULL;
3828 1.1 augustss }
3829