uhci.c revision 1.264.4.5 1 1.264.4.5 skrll /* $NetBSD: uhci.c,v 1.264.4.5 2014/12/01 12:38:39 skrll Exp $ */
2 1.1 augustss
3 1.1 augustss /*
4 1.248 mrg * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc.
5 1.1 augustss * All rights reserved.
6 1.1 augustss *
7 1.11 augustss * This code is derived from software contributed to The NetBSD Foundation
8 1.113 augustss * by Lennart Augustsson (lennart (at) augustsson.net) at
9 1.248 mrg * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca)
10 1.248 mrg * and Matthew R. Green (mrg (at) eterna.com.au).
11 1.1 augustss *
12 1.1 augustss * Redistribution and use in source and binary forms, with or without
13 1.1 augustss * modification, are permitted provided that the following conditions
14 1.1 augustss * are met:
15 1.1 augustss * 1. Redistributions of source code must retain the above copyright
16 1.1 augustss * notice, this list of conditions and the following disclaimer.
17 1.1 augustss * 2. Redistributions in binary form must reproduce the above copyright
18 1.1 augustss * notice, this list of conditions and the following disclaimer in the
19 1.1 augustss * documentation and/or other materials provided with the distribution.
20 1.1 augustss *
21 1.1 augustss * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22 1.1 augustss * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 1.1 augustss * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 1.1 augustss * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25 1.1 augustss * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 1.1 augustss * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 1.1 augustss * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 1.1 augustss * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 1.1 augustss * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 1.1 augustss * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 1.1 augustss * POSSIBILITY OF SUCH DAMAGE.
32 1.1 augustss */
33 1.1 augustss
34 1.1 augustss /*
35 1.1 augustss * USB Universal Host Controller driver.
36 1.28 augustss * Handles e.g. PIIX3 and PIIX4.
37 1.1 augustss *
38 1.229 uebayasi * UHCI spec: http://www.intel.com/technology/usb/spec.htm
39 1.229 uebayasi * USB spec: http://www.usb.org/developers/docs/
40 1.71 augustss * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf
41 1.71 augustss * ftp://download.intel.com/design/intarch/datashts/29056201.pdf
42 1.1 augustss */
43 1.143 lukem
44 1.143 lukem #include <sys/cdefs.h>
45 1.264.4.5 skrll __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.264.4.5 2014/12/01 12:38:39 skrll Exp $");
46 1.1 augustss
47 1.1 augustss #include <sys/param.h>
48 1.1 augustss #include <sys/systm.h>
49 1.1 augustss #include <sys/kernel.h>
50 1.248 mrg #include <sys/kmem.h>
51 1.1 augustss #include <sys/device.h>
52 1.67 augustss #include <sys/select.h>
53 1.183 fvdl #include <sys/extent.h>
54 1.1 augustss #include <sys/proc.h>
55 1.1 augustss #include <sys/queue.h>
56 1.211 ad #include <sys/bus.h>
57 1.247 mrg #include <sys/cpu.h>
58 1.1 augustss
59 1.39 augustss #include <machine/endian.h>
60 1.7 augustss
61 1.1 augustss #include <dev/usb/usb.h>
62 1.1 augustss #include <dev/usb/usbdi.h>
63 1.1 augustss #include <dev/usb/usbdivar.h>
64 1.7 augustss #include <dev/usb/usb_mem.h>
65 1.1 augustss #include <dev/usb/usb_quirks.h>
66 1.1 augustss
67 1.1 augustss #include <dev/usb/uhcireg.h>
68 1.1 augustss #include <dev/usb/uhcivar.h>
69 1.213 drochner #include <dev/usb/usbroothub_subr.h>
70 1.1 augustss
71 1.125 augustss /* Use bandwidth reclamation for control transfers. Some devices choke on it. */
72 1.125 augustss /*#define UHCI_CTL_LOOP */
73 1.125 augustss
74 1.13 augustss
75 1.37 augustss
76 1.67 augustss #ifdef UHCI_DEBUG
77 1.92 augustss uhci_softc_t *thesc;
78 1.59 augustss #define DPRINTF(x) if (uhcidebug) printf x
79 1.59 augustss #define DPRINTFN(n,x) if (uhcidebug>(n)) printf x
80 1.67 augustss int uhcidebug = 0;
81 1.125 augustss int uhcinoloop = 0;
82 1.59 augustss #else
83 1.59 augustss #define DPRINTF(x)
84 1.59 augustss #define DPRINTFN(n,x)
85 1.59 augustss #endif
86 1.59 augustss
87 1.39 augustss /*
88 1.39 augustss * The UHCI controller is little endian, so on big endian machines
89 1.181 drochner * the data stored in memory needs to be swapped.
90 1.39 augustss */
91 1.39 augustss
92 1.1 augustss struct uhci_pipe {
93 1.1 augustss struct usbd_pipe pipe;
94 1.32 augustss int nexttoggle;
95 1.92 augustss
96 1.92 augustss u_char aborting;
97 1.92 augustss usbd_xfer_handle abortstart, abortend;
98 1.92 augustss
99 1.1 augustss /* Info needed for different pipe kinds. */
100 1.1 augustss union {
101 1.1 augustss /* Control pipe */
102 1.1 augustss struct {
103 1.1 augustss uhci_soft_qh_t *sqh;
104 1.7 augustss usb_dma_t reqdma;
105 1.16 augustss uhci_soft_td_t *setup, *stat;
106 1.1 augustss u_int length;
107 1.1 augustss } ctl;
108 1.1 augustss /* Interrupt pipe */
109 1.1 augustss struct {
110 1.1 augustss int npoll;
111 1.187 skrll int isread;
112 1.1 augustss uhci_soft_qh_t **qhs;
113 1.1 augustss } intr;
114 1.1 augustss /* Bulk pipe */
115 1.1 augustss struct {
116 1.1 augustss uhci_soft_qh_t *sqh;
117 1.1 augustss u_int length;
118 1.1 augustss int isread;
119 1.1 augustss } bulk;
120 1.16 augustss /* Iso pipe */
121 1.16 augustss struct iso {
122 1.16 augustss uhci_soft_td_t **stds;
123 1.48 augustss int next, inuse;
124 1.16 augustss } iso;
125 1.1 augustss } u;
126 1.1 augustss };
127 1.1 augustss
128 1.142 augustss Static void uhci_globalreset(uhci_softc_t *);
129 1.166 dsainty Static usbd_status uhci_portreset(uhci_softc_t*, int);
130 1.142 augustss Static void uhci_reset(uhci_softc_t *);
131 1.249 drochner Static usbd_status uhci_run(uhci_softc_t *, int run, int locked);
132 1.123 augustss Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *);
133 1.119 augustss Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *);
134 1.123 augustss Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *);
135 1.119 augustss Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *);
136 1.16 augustss #if 0
137 1.119 augustss Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *,
138 1.119 augustss uhci_intr_info_t *);
139 1.119 augustss Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *);
140 1.16 augustss #endif
141 1.1 augustss
142 1.152 augustss Static void uhci_free_std_chain(uhci_softc_t *,
143 1.119 augustss uhci_soft_td_t *, uhci_soft_td_t *);
144 1.119 augustss Static usbd_status uhci_alloc_std_chain(struct uhci_pipe *,
145 1.264.4.1 skrll uhci_softc_t *, int, int, uint16_t, usb_dma_t *,
146 1.119 augustss uhci_soft_td_t **, uhci_soft_td_t **);
147 1.119 augustss Static void uhci_poll_hub(void *);
148 1.119 augustss Static void uhci_waitintr(uhci_softc_t *, usbd_xfer_handle);
149 1.119 augustss Static void uhci_check_intr(uhci_softc_t *, uhci_intr_info_t *);
150 1.119 augustss Static void uhci_idone(uhci_intr_info_t *);
151 1.119 augustss
152 1.119 augustss Static void uhci_abort_xfer(usbd_xfer_handle, usbd_status status);
153 1.119 augustss
154 1.119 augustss Static void uhci_timeout(void *);
155 1.153 augustss Static void uhci_timeout_task(void *);
156 1.123 augustss Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *);
157 1.123 augustss Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *);
158 1.119 augustss Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *);
159 1.123 augustss Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *);
160 1.123 augustss Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *);
161 1.119 augustss Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *);
162 1.123 augustss Static void uhci_add_loop(uhci_softc_t *sc);
163 1.123 augustss Static void uhci_rem_loop(uhci_softc_t *sc);
164 1.119 augustss
165 1.119 augustss Static usbd_status uhci_setup_isoc(usbd_pipe_handle pipe);
166 1.119 augustss Static void uhci_device_isoc_enter(usbd_xfer_handle);
167 1.119 augustss
168 1.264.4.1 skrll Static usbd_status uhci_allocm(struct usbd_bus *, usb_dma_t *, uint32_t);
169 1.119 augustss Static void uhci_freem(struct usbd_bus *, usb_dma_t *);
170 1.119 augustss
171 1.119 augustss Static usbd_xfer_handle uhci_allocx(struct usbd_bus *);
172 1.119 augustss Static void uhci_freex(struct usbd_bus *, usbd_xfer_handle);
173 1.248 mrg Static void uhci_get_lock(struct usbd_bus *, kmutex_t **);
174 1.119 augustss
175 1.119 augustss Static usbd_status uhci_device_ctrl_transfer(usbd_xfer_handle);
176 1.119 augustss Static usbd_status uhci_device_ctrl_start(usbd_xfer_handle);
177 1.119 augustss Static void uhci_device_ctrl_abort(usbd_xfer_handle);
178 1.119 augustss Static void uhci_device_ctrl_close(usbd_pipe_handle);
179 1.119 augustss Static void uhci_device_ctrl_done(usbd_xfer_handle);
180 1.119 augustss
181 1.119 augustss Static usbd_status uhci_device_intr_transfer(usbd_xfer_handle);
182 1.119 augustss Static usbd_status uhci_device_intr_start(usbd_xfer_handle);
183 1.119 augustss Static void uhci_device_intr_abort(usbd_xfer_handle);
184 1.119 augustss Static void uhci_device_intr_close(usbd_pipe_handle);
185 1.119 augustss Static void uhci_device_intr_done(usbd_xfer_handle);
186 1.119 augustss
187 1.119 augustss Static usbd_status uhci_device_bulk_transfer(usbd_xfer_handle);
188 1.119 augustss Static usbd_status uhci_device_bulk_start(usbd_xfer_handle);
189 1.119 augustss Static void uhci_device_bulk_abort(usbd_xfer_handle);
190 1.119 augustss Static void uhci_device_bulk_close(usbd_pipe_handle);
191 1.119 augustss Static void uhci_device_bulk_done(usbd_xfer_handle);
192 1.119 augustss
193 1.119 augustss Static usbd_status uhci_device_isoc_transfer(usbd_xfer_handle);
194 1.119 augustss Static usbd_status uhci_device_isoc_start(usbd_xfer_handle);
195 1.119 augustss Static void uhci_device_isoc_abort(usbd_xfer_handle);
196 1.119 augustss Static void uhci_device_isoc_close(usbd_pipe_handle);
197 1.119 augustss Static void uhci_device_isoc_done(usbd_xfer_handle);
198 1.119 augustss
199 1.119 augustss Static usbd_status uhci_root_ctrl_transfer(usbd_xfer_handle);
200 1.119 augustss Static usbd_status uhci_root_ctrl_start(usbd_xfer_handle);
201 1.119 augustss Static void uhci_root_ctrl_abort(usbd_xfer_handle);
202 1.119 augustss Static void uhci_root_ctrl_close(usbd_pipe_handle);
203 1.119 augustss Static void uhci_root_ctrl_done(usbd_xfer_handle);
204 1.119 augustss
205 1.119 augustss Static usbd_status uhci_root_intr_transfer(usbd_xfer_handle);
206 1.119 augustss Static usbd_status uhci_root_intr_start(usbd_xfer_handle);
207 1.119 augustss Static void uhci_root_intr_abort(usbd_xfer_handle);
208 1.119 augustss Static void uhci_root_intr_close(usbd_pipe_handle);
209 1.119 augustss Static void uhci_root_intr_done(usbd_xfer_handle);
210 1.119 augustss
211 1.119 augustss Static usbd_status uhci_open(usbd_pipe_handle);
212 1.119 augustss Static void uhci_poll(struct usbd_bus *);
213 1.133 augustss Static void uhci_softintr(void *);
214 1.119 augustss
215 1.119 augustss Static usbd_status uhci_device_request(usbd_xfer_handle xfer);
216 1.119 augustss
217 1.119 augustss Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *);
218 1.158 augustss Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *);
219 1.152 augustss Static usbd_status uhci_device_setintr(uhci_softc_t *sc,
220 1.119 augustss struct uhci_pipe *pipe, int ival);
221 1.119 augustss
222 1.119 augustss Static void uhci_device_clear_toggle(usbd_pipe_handle pipe);
223 1.119 augustss Static void uhci_noop(usbd_pipe_handle pipe);
224 1.119 augustss
225 1.240 jakllsch static inline uhci_soft_qh_t *uhci_find_prev_qh(uhci_soft_qh_t *,
226 1.119 augustss uhci_soft_qh_t *);
227 1.119 augustss
228 1.119 augustss #ifdef UHCI_DEBUG
229 1.119 augustss Static void uhci_dump_all(uhci_softc_t *);
230 1.119 augustss Static void uhci_dumpregs(uhci_softc_t *);
231 1.119 augustss Static void uhci_dump_qhs(uhci_soft_qh_t *);
232 1.119 augustss Static void uhci_dump_qh(uhci_soft_qh_t *);
233 1.119 augustss Static void uhci_dump_tds(uhci_soft_td_t *);
234 1.119 augustss Static void uhci_dump_td(uhci_soft_td_t *);
235 1.119 augustss Static void uhci_dump_ii(uhci_intr_info_t *ii);
236 1.119 augustss void uhci_dump(void);
237 1.1 augustss #endif
238 1.1 augustss
239 1.112 augustss #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \
240 1.112 augustss BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
241 1.112 augustss #define UWRITE1(sc, r, x) \
242 1.165 dsainty do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \
243 1.165 dsainty } while (/*CONSTCOND*/0)
244 1.112 augustss #define UWRITE2(sc, r, x) \
245 1.165 dsainty do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \
246 1.165 dsainty } while (/*CONSTCOND*/0)
247 1.112 augustss #define UWRITE4(sc, r, x) \
248 1.165 dsainty do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \
249 1.165 dsainty } while (/*CONSTCOND*/0)
250 1.196 mrg static __inline uint8_t
251 1.196 mrg UREAD1(uhci_softc_t *sc, bus_size_t r)
252 1.196 mrg {
253 1.196 mrg
254 1.196 mrg UBARR(sc);
255 1.196 mrg return bus_space_read_1(sc->iot, sc->ioh, r);
256 1.196 mrg }
257 1.196 mrg
258 1.196 mrg static __inline uint16_t
259 1.196 mrg UREAD2(uhci_softc_t *sc, bus_size_t r)
260 1.196 mrg {
261 1.196 mrg
262 1.196 mrg UBARR(sc);
263 1.196 mrg return bus_space_read_2(sc->iot, sc->ioh, r);
264 1.196 mrg }
265 1.196 mrg
266 1.260 joerg #ifdef UHCI_DEBUG
267 1.196 mrg static __inline uint32_t
268 1.196 mrg UREAD4(uhci_softc_t *sc, bus_size_t r)
269 1.196 mrg {
270 1.196 mrg
271 1.196 mrg UBARR(sc);
272 1.196 mrg return bus_space_read_4(sc->iot, sc->ioh, r);
273 1.196 mrg }
274 1.260 joerg #endif
275 1.1 augustss
276 1.1 augustss #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd)
277 1.1 augustss #define UHCISTS(sc) UREAD2(sc, UHCI_STS)
278 1.1 augustss
279 1.142 augustss #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */
280 1.1 augustss
281 1.1 augustss #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK)
282 1.1 augustss
283 1.1 augustss #define UHCI_INTR_ENDPT 1
284 1.1 augustss
285 1.208 drochner const struct usbd_bus_methods uhci_bus_methods = {
286 1.264.4.5 skrll .ubm_open = uhci_open,
287 1.264.4.5 skrll .ubm_softint = uhci_softintr,
288 1.264.4.5 skrll .ubm_dopoll = uhci_poll,
289 1.264.4.5 skrll .ubm_allocm = uhci_allocm,
290 1.264.4.5 skrll .ubm_freem = uhci_freem,
291 1.264.4.5 skrll .ubm_allocx = uhci_allocx,
292 1.264.4.5 skrll .ubm_freex = uhci_freex,
293 1.264.4.5 skrll .ubm_getlock = uhci_get_lock,
294 1.264.4.5 skrll .ubm_newdev = NULL,
295 1.48 augustss };
296 1.48 augustss
297 1.208 drochner const struct usbd_pipe_methods uhci_root_ctrl_methods = {
298 1.264.4.5 skrll .upm_transfer = uhci_root_ctrl_transfer,
299 1.264.4.5 skrll .upm_start = uhci_root_ctrl_start,
300 1.264.4.5 skrll .upm_abort = uhci_root_ctrl_abort,
301 1.264.4.5 skrll .upm_close = uhci_root_ctrl_close,
302 1.264.4.5 skrll .upm_cleartoggle = uhci_noop,
303 1.264.4.5 skrll .upm_done = uhci_root_ctrl_done,
304 1.1 augustss };
305 1.1 augustss
306 1.208 drochner const struct usbd_pipe_methods uhci_root_intr_methods = {
307 1.264.4.5 skrll .upm_transfer = uhci_root_intr_transfer,
308 1.264.4.5 skrll .upm_start = uhci_root_intr_start,
309 1.264.4.5 skrll .upm_abort = uhci_root_intr_abort,
310 1.264.4.5 skrll .upm_close = uhci_root_intr_close,
311 1.264.4.5 skrll .upm_cleartoggle = uhci_noop,
312 1.264.4.5 skrll .upm_done = uhci_root_intr_done,
313 1.1 augustss };
314 1.1 augustss
315 1.208 drochner const struct usbd_pipe_methods uhci_device_ctrl_methods = {
316 1.264.4.5 skrll .upm_transfer = uhci_device_ctrl_transfer,
317 1.264.4.5 skrll .upm_start = uhci_device_ctrl_start,
318 1.264.4.5 skrll .upm_abort = uhci_device_ctrl_abort,
319 1.264.4.5 skrll .upm_close = uhci_device_ctrl_close,
320 1.264.4.5 skrll .upm_cleartoggle = uhci_noop,
321 1.264.4.5 skrll .upm_done = uhci_device_ctrl_done,
322 1.1 augustss };
323 1.1 augustss
324 1.208 drochner const struct usbd_pipe_methods uhci_device_intr_methods = {
325 1.264.4.5 skrll .upm_transfer = uhci_device_intr_transfer,
326 1.264.4.5 skrll .upm_start = uhci_device_intr_start,
327 1.264.4.5 skrll .upm_abort = uhci_device_intr_abort,
328 1.264.4.5 skrll .upm_close = uhci_device_intr_close,
329 1.264.4.5 skrll .upm_cleartoggle = uhci_device_clear_toggle,
330 1.264.4.5 skrll .upm_done = uhci_device_intr_done,
331 1.1 augustss };
332 1.1 augustss
333 1.208 drochner const struct usbd_pipe_methods uhci_device_bulk_methods = {
334 1.264.4.5 skrll .upm_transfer = uhci_device_bulk_transfer,
335 1.264.4.5 skrll .upm_start = uhci_device_bulk_start,
336 1.264.4.5 skrll .upm_abort = uhci_device_bulk_abort,
337 1.264.4.5 skrll .upm_close = uhci_device_bulk_close,
338 1.264.4.5 skrll .upm_cleartoggle = uhci_device_clear_toggle,
339 1.264.4.5 skrll .upm_done = uhci_device_bulk_done,
340 1.1 augustss };
341 1.1 augustss
342 1.208 drochner const struct usbd_pipe_methods uhci_device_isoc_methods = {
343 1.264.4.5 skrll .upm_transfer = uhci_device_isoc_transfer,
344 1.264.4.5 skrll .upm_start = uhci_device_isoc_start,
345 1.264.4.5 skrll .upm_abort = uhci_device_isoc_abort,
346 1.264.4.5 skrll .upm_close = uhci_device_isoc_close,
347 1.264.4.5 skrll .upm_cleartoggle = uhci_noop,
348 1.264.4.5 skrll .upm_done = uhci_device_isoc_done,
349 1.16 augustss };
350 1.16 augustss
351 1.92 augustss #define uhci_add_intr_info(sc, ii) \
352 1.169 augustss LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ii), list)
353 1.92 augustss #define uhci_del_intr_info(ii) \
354 1.169 augustss do { \
355 1.169 augustss LIST_REMOVE((ii), list); \
356 1.169 augustss (ii)->list.le_prev = NULL; \
357 1.169 augustss } while (0)
358 1.169 augustss #define uhci_active_intr_info(ii) ((ii)->list.le_prev != NULL)
359 1.92 augustss
360 1.240 jakllsch static inline uhci_soft_qh_t *
361 1.119 augustss uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh)
362 1.92 augustss {
363 1.92 augustss DPRINTFN(15,("uhci_find_prev_qh: pqh=%p sqh=%p\n", pqh, sqh));
364 1.92 augustss
365 1.92 augustss for (; pqh->hlink != sqh; pqh = pqh->hlink) {
366 1.152 augustss #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG)
367 1.223 bouyer usb_syncmem(&pqh->dma,
368 1.223 bouyer pqh->offs + offsetof(uhci_qh_t, qh_hlink),
369 1.223 bouyer sizeof(pqh->qh.qh_hlink),
370 1.223 bouyer BUS_DMASYNC_POSTWRITE);
371 1.92 augustss if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) {
372 1.102 augustss printf("uhci_find_prev_qh: QH not found\n");
373 1.92 augustss return (NULL);
374 1.92 augustss }
375 1.92 augustss #endif
376 1.92 augustss }
377 1.92 augustss return (pqh);
378 1.92 augustss }
379 1.92 augustss
380 1.1 augustss void
381 1.142 augustss uhci_globalreset(uhci_softc_t *sc)
382 1.1 augustss {
383 1.1 augustss UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */
384 1.20 augustss usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */
385 1.1 augustss UHCICMD(sc, 0); /* do nothing */
386 1.1 augustss }
387 1.1 augustss
388 1.1 augustss usbd_status
389 1.119 augustss uhci_init(uhci_softc_t *sc)
390 1.1 augustss {
391 1.63 augustss usbd_status err;
392 1.1 augustss int i, j;
393 1.123 augustss uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh;
394 1.1 augustss uhci_soft_td_t *std;
395 1.1 augustss
396 1.1 augustss DPRINTFN(1,("uhci_init: start\n"));
397 1.1 augustss
398 1.67 augustss #ifdef UHCI_DEBUG
399 1.92 augustss thesc = sc;
400 1.92 augustss
401 1.1 augustss if (uhcidebug > 2)
402 1.1 augustss uhci_dumpregs(sc);
403 1.1 augustss #endif
404 1.1 augustss
405 1.219 jmcneill sc->sc_suspend = PWR_RESUME;
406 1.219 jmcneill
407 1.1 augustss UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */
408 1.142 augustss uhci_globalreset(sc); /* reset the controller */
409 1.142 augustss uhci_reset(sc);
410 1.24 augustss
411 1.218 drochner usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag,
412 1.183 fvdl USB_MEM_RESERVE);
413 1.183 fvdl
414 1.1 augustss /* Allocate and initialize real frame array. */
415 1.152 augustss err = usb_allocmem(&sc->sc_bus,
416 1.63 augustss UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t),
417 1.63 augustss UHCI_FRAMELIST_ALIGN, &sc->sc_dma);
418 1.63 augustss if (err)
419 1.63 augustss return (err);
420 1.159 augustss sc->sc_pframes = KERNADDR(&sc->sc_dma, 0);
421 1.1 augustss UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */
422 1.160 augustss UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/
423 1.1 augustss
424 1.152 augustss /*
425 1.123 augustss * Allocate a TD, inactive, that hangs from the last QH.
426 1.123 augustss * This is to avoid a bug in the PIIX that makes it run berserk
427 1.123 augustss * otherwise.
428 1.123 augustss */
429 1.123 augustss std = uhci_alloc_std(sc);
430 1.123 augustss if (std == NULL)
431 1.123 augustss return (USBD_NOMEM);
432 1.123 augustss std->link.std = NULL;
433 1.123 augustss std->td.td_link = htole32(UHCI_PTR_T);
434 1.123 augustss std->td.td_status = htole32(0); /* inactive */
435 1.123 augustss std->td.td_token = htole32(0);
436 1.123 augustss std->td.td_buffer = htole32(0);
437 1.223 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
438 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
439 1.123 augustss
440 1.123 augustss /* Allocate the dummy QH marking the end and used for looping the QHs.*/
441 1.123 augustss lsqh = uhci_alloc_sqh(sc);
442 1.123 augustss if (lsqh == NULL)
443 1.123 augustss return (USBD_NOMEM);
444 1.123 augustss lsqh->hlink = NULL;
445 1.123 augustss lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */
446 1.123 augustss lsqh->elink = std;
447 1.123 augustss lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD);
448 1.123 augustss sc->sc_last_qh = lsqh;
449 1.223 bouyer usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh),
450 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
451 1.123 augustss
452 1.1 augustss /* Allocate the dummy QH where bulk traffic will be queued. */
453 1.1 augustss bsqh = uhci_alloc_sqh(sc);
454 1.63 augustss if (bsqh == NULL)
455 1.1 augustss return (USBD_NOMEM);
456 1.123 augustss bsqh->hlink = lsqh;
457 1.123 augustss bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH);
458 1.121 augustss bsqh->elink = NULL;
459 1.88 tsutsui bsqh->qh.qh_elink = htole32(UHCI_PTR_T);
460 1.1 augustss sc->sc_bulk_start = sc->sc_bulk_end = bsqh;
461 1.223 bouyer usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh),
462 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
463 1.1 augustss
464 1.123 augustss /* Allocate dummy QH where high speed control traffic will be queued. */
465 1.123 augustss chsqh = uhci_alloc_sqh(sc);
466 1.123 augustss if (chsqh == NULL)
467 1.123 augustss return (USBD_NOMEM);
468 1.123 augustss chsqh->hlink = bsqh;
469 1.123 augustss chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH);
470 1.123 augustss chsqh->elink = NULL;
471 1.123 augustss chsqh->qh.qh_elink = htole32(UHCI_PTR_T);
472 1.123 augustss sc->sc_hctl_start = sc->sc_hctl_end = chsqh;
473 1.223 bouyer usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh),
474 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
475 1.123 augustss
476 1.123 augustss /* Allocate dummy QH where control traffic will be queued. */
477 1.123 augustss clsqh = uhci_alloc_sqh(sc);
478 1.123 augustss if (clsqh == NULL)
479 1.1 augustss return (USBD_NOMEM);
480 1.220 bouyer clsqh->hlink = chsqh;
481 1.123 augustss clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH);
482 1.123 augustss clsqh->elink = NULL;
483 1.123 augustss clsqh->qh.qh_elink = htole32(UHCI_PTR_T);
484 1.123 augustss sc->sc_lctl_start = sc->sc_lctl_end = clsqh;
485 1.223 bouyer usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh),
486 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
487 1.1 augustss
488 1.152 augustss /*
489 1.1 augustss * Make all (virtual) frame list pointers point to the interrupt
490 1.1 augustss * queue heads and the interrupt queue heads at the control
491 1.1 augustss * queue head and point the physical frame list to the virtual.
492 1.1 augustss */
493 1.1 augustss for(i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
494 1.1 augustss std = uhci_alloc_std(sc);
495 1.1 augustss sqh = uhci_alloc_sqh(sc);
496 1.67 augustss if (std == NULL || sqh == NULL)
497 1.13 augustss return (USBD_NOMEM);
498 1.42 augustss std->link.sqh = sqh;
499 1.121 augustss std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH);
500 1.88 tsutsui std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */
501 1.88 tsutsui std->td.td_token = htole32(0);
502 1.88 tsutsui std->td.td_buffer = htole32(0);
503 1.223 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
504 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
505 1.123 augustss sqh->hlink = clsqh;
506 1.123 augustss sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH);
507 1.121 augustss sqh->elink = NULL;
508 1.88 tsutsui sqh->qh.qh_elink = htole32(UHCI_PTR_T);
509 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
510 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
511 1.1 augustss sc->sc_vframes[i].htd = std;
512 1.1 augustss sc->sc_vframes[i].etd = std;
513 1.1 augustss sc->sc_vframes[i].hqh = sqh;
514 1.1 augustss sc->sc_vframes[i].eqh = sqh;
515 1.152 augustss for (j = i;
516 1.152 augustss j < UHCI_FRAMELIST_COUNT;
517 1.1 augustss j += UHCI_VFRAMELIST_COUNT)
518 1.88 tsutsui sc->sc_pframes[j] = htole32(std->physaddr);
519 1.1 augustss }
520 1.223 bouyer usb_syncmem(&sc->sc_dma, 0,
521 1.223 bouyer UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t),
522 1.223 bouyer BUS_DMASYNC_PREWRITE);
523 1.223 bouyer
524 1.1 augustss
525 1.1 augustss LIST_INIT(&sc->sc_intrhead);
526 1.1 augustss
527 1.253 christos sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0,
528 1.253 christos "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL);
529 1.76 augustss
530 1.248 mrg callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE);
531 1.248 mrg
532 1.248 mrg mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
533 1.248 mrg mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED);
534 1.248 mrg cv_init(&sc->sc_softwake_cv, "uhciab");
535 1.96 augustss
536 1.1 augustss /* Set up the bus struct. */
537 1.48 augustss sc->sc_bus.methods = &uhci_bus_methods;
538 1.1 augustss sc->sc_bus.pipe_size = sizeof(struct uhci_pipe);
539 1.1 augustss
540 1.190 augustss UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */
541 1.190 augustss
542 1.1 augustss DPRINTFN(1,("uhci_init: enabling\n"));
543 1.225 bouyer
544 1.249 drochner err = uhci_run(sc, 1, 0); /* and here we go... */
545 1.152 augustss UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE |
546 1.1 augustss UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */
547 1.225 bouyer return err;
548 1.53 augustss }
549 1.53 augustss
550 1.53 augustss int
551 1.215 dyoung uhci_activate(device_t self, enum devact act)
552 1.53 augustss {
553 1.215 dyoung struct uhci_softc *sc = device_private(self);
554 1.53 augustss
555 1.53 augustss switch (act) {
556 1.53 augustss case DVACT_DEACTIVATE:
557 1.210 kiyohara sc->sc_dying = 1;
558 1.230 dyoung return 0;
559 1.230 dyoung default:
560 1.230 dyoung return EOPNOTSUPP;
561 1.53 augustss }
562 1.53 augustss }
563 1.53 augustss
564 1.215 dyoung void
565 1.215 dyoung uhci_childdet(device_t self, device_t child)
566 1.215 dyoung {
567 1.215 dyoung struct uhci_softc *sc = device_private(self);
568 1.215 dyoung
569 1.215 dyoung KASSERT(sc->sc_child == child);
570 1.215 dyoung sc->sc_child = NULL;
571 1.215 dyoung }
572 1.215 dyoung
573 1.53 augustss int
574 1.119 augustss uhci_detach(struct uhci_softc *sc, int flags)
575 1.53 augustss {
576 1.53 augustss int rv = 0;
577 1.53 augustss
578 1.53 augustss if (sc->sc_child != NULL)
579 1.53 augustss rv = config_detach(sc->sc_child, flags);
580 1.152 augustss
581 1.53 augustss if (rv != 0)
582 1.53 augustss return (rv);
583 1.53 augustss
584 1.226 ad callout_halt(&sc->sc_poll_handle, NULL);
585 1.226 ad callout_destroy(&sc->sc_poll_handle);
586 1.226 ad
587 1.248 mrg cv_destroy(&sc->sc_softwake_cv);
588 1.248 mrg
589 1.248 mrg mutex_destroy(&sc->sc_lock);
590 1.248 mrg mutex_destroy(&sc->sc_intr_lock);
591 1.248 mrg
592 1.254 christos pool_cache_destroy(sc->sc_xferpool);
593 1.254 christos
594 1.76 augustss /* XXX free other data structures XXX */
595 1.53 augustss
596 1.53 augustss return (rv);
597 1.1 augustss }
598 1.1 augustss
599 1.48 augustss usbd_status
600 1.264.4.1 skrll uhci_allocm(struct usbd_bus *bus, usb_dma_t *dma, uint32_t size)
601 1.48 augustss {
602 1.216 drochner struct uhci_softc *sc = bus->hci_private;
603 1.183 fvdl usbd_status status;
604 1.264.4.1 skrll uint32_t n;
605 1.102 augustss
606 1.152 augustss /*
607 1.102 augustss * XXX
608 1.102 augustss * Since we are allocating a buffer we can assume that we will
609 1.148 augustss * need TDs for it. Since we don't want to allocate those from
610 1.102 augustss * an interrupt context, we allocate them here and free them again.
611 1.102 augustss * This is no guarantee that we'll get the TDs next time...
612 1.102 augustss */
613 1.102 augustss n = size / 8;
614 1.102 augustss if (n > 16) {
615 1.264.4.1 skrll uint32_t i;
616 1.102 augustss uhci_soft_td_t **stds;
617 1.248 mrg
618 1.102 augustss DPRINTF(("uhci_allocm: get %d TDs\n", n));
619 1.248 mrg stds = kmem_alloc(sizeof(uhci_soft_td_t *) * n, KM_SLEEP);
620 1.248 mrg if (!stds)
621 1.248 mrg return USBD_NOMEM;
622 1.248 mrg for(i = 0; i < n; i++)
623 1.102 augustss stds[i] = uhci_alloc_std(sc);
624 1.248 mrg for(i = 0; i < n; i++)
625 1.102 augustss if (stds[i] != NULL)
626 1.102 augustss uhci_free_std(sc, stds[i]);
627 1.248 mrg kmem_free(stds, sizeof(uhci_soft_td_t *) * n);
628 1.102 augustss }
629 1.102 augustss
630 1.183 fvdl status = usb_allocmem(&sc->sc_bus, size, 0, dma);
631 1.183 fvdl if (status == USBD_NOMEM)
632 1.183 fvdl status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size);
633 1.183 fvdl return status;
634 1.48 augustss }
635 1.48 augustss
636 1.48 augustss void
637 1.119 augustss uhci_freem(struct usbd_bus *bus, usb_dma_t *dma)
638 1.48 augustss {
639 1.183 fvdl if (dma->block->flags & USB_DMA_RESERVE) {
640 1.183 fvdl usb_reserve_freem(&((struct uhci_softc *)bus)->sc_dma_reserve,
641 1.183 fvdl dma);
642 1.183 fvdl return;
643 1.183 fvdl }
644 1.63 augustss usb_freemem(&((struct uhci_softc *)bus)->sc_bus, dma);
645 1.76 augustss }
646 1.76 augustss
647 1.76 augustss usbd_xfer_handle
648 1.119 augustss uhci_allocx(struct usbd_bus *bus)
649 1.76 augustss {
650 1.216 drochner struct uhci_softc *sc = bus->hci_private;
651 1.76 augustss usbd_xfer_handle xfer;
652 1.76 augustss
653 1.253 christos xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT);
654 1.92 augustss if (xfer != NULL) {
655 1.253 christos memset(xfer, 0, sizeof(struct uhci_xfer));
656 1.254 christos UXFER(xfer)->iinfo.sc = sc;
657 1.92 augustss #ifdef DIAGNOSTIC
658 1.238 tsutsui UXFER(xfer)->iinfo.isdone = 1;
659 1.135 augustss xfer->busy_free = XFER_BUSY;
660 1.92 augustss #endif
661 1.92 augustss }
662 1.76 augustss return (xfer);
663 1.76 augustss }
664 1.76 augustss
665 1.76 augustss void
666 1.119 augustss uhci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer)
667 1.76 augustss {
668 1.216 drochner struct uhci_softc *sc = bus->hci_private;
669 1.76 augustss
670 1.93 augustss #ifdef DIAGNOSTIC
671 1.94 augustss if (xfer->busy_free != XFER_BUSY) {
672 1.94 augustss printf("uhci_freex: xfer=%p not busy, 0x%08x\n", xfer,
673 1.94 augustss xfer->busy_free);
674 1.93 augustss }
675 1.94 augustss xfer->busy_free = XFER_FREE;
676 1.238 tsutsui if (!UXFER(xfer)->iinfo.isdone) {
677 1.96 augustss printf("uhci_freex: !isdone\n");
678 1.105 augustss }
679 1.93 augustss #endif
680 1.253 christos pool_cache_put(sc->sc_xferpool, xfer);
681 1.48 augustss }
682 1.48 augustss
683 1.248 mrg Static void
684 1.248 mrg uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock)
685 1.248 mrg {
686 1.248 mrg struct uhci_softc *sc = bus->hci_private;
687 1.248 mrg
688 1.248 mrg *lock = &sc->sc_lock;
689 1.248 mrg }
690 1.248 mrg
691 1.248 mrg
692 1.72 augustss /*
693 1.212 jmcneill * Handle suspend/resume.
694 1.212 jmcneill *
695 1.212 jmcneill * We need to switch to polling mode here, because this routine is
696 1.212 jmcneill * called from an interrupt context. This is all right since we
697 1.212 jmcneill * are almost suspended anyway.
698 1.72 augustss */
699 1.212 jmcneill bool
700 1.232 dyoung uhci_resume(device_t dv, const pmf_qual_t *qual)
701 1.72 augustss {
702 1.212 jmcneill uhci_softc_t *sc = device_private(dv);
703 1.212 jmcneill int cmd;
704 1.72 augustss
705 1.248 mrg mutex_spin_enter(&sc->sc_intr_lock);
706 1.193 augustss
707 1.212 jmcneill cmd = UREAD2(sc, UHCI_CMD);
708 1.193 augustss sc->sc_bus.use_polling++;
709 1.214 smb UWRITE2(sc, UHCI_INTR, 0);
710 1.214 smb uhci_globalreset(sc);
711 1.214 smb uhci_reset(sc);
712 1.212 jmcneill if (cmd & UHCI_CMD_RS)
713 1.249 drochner uhci_run(sc, 0, 1);
714 1.212 jmcneill
715 1.212 jmcneill /* restore saved state */
716 1.212 jmcneill UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0));
717 1.212 jmcneill UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum);
718 1.212 jmcneill UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof);
719 1.212 jmcneill
720 1.212 jmcneill UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */
721 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock);
722 1.212 jmcneill UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */
723 1.212 jmcneill UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE |
724 1.212 jmcneill UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE);
725 1.214 smb UHCICMD(sc, UHCI_CMD_MAXP);
726 1.249 drochner uhci_run(sc, 1, 1); /* and start traffic again */
727 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock);
728 1.193 augustss sc->sc_bus.use_polling--;
729 1.212 jmcneill if (sc->sc_intr_xfer != NULL)
730 1.234 dyoung callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub,
731 1.212 jmcneill sc->sc_intr_xfer);
732 1.212 jmcneill #ifdef UHCI_DEBUG
733 1.212 jmcneill if (uhcidebug > 2)
734 1.212 jmcneill uhci_dumpregs(sc);
735 1.212 jmcneill #endif
736 1.212 jmcneill
737 1.219 jmcneill sc->sc_suspend = PWR_RESUME;
738 1.248 mrg mutex_spin_exit(&sc->sc_intr_lock);
739 1.212 jmcneill
740 1.212 jmcneill return true;
741 1.72 augustss }
742 1.72 augustss
743 1.212 jmcneill bool
744 1.232 dyoung uhci_suspend(device_t dv, const pmf_qual_t *qual)
745 1.30 augustss {
746 1.212 jmcneill uhci_softc_t *sc = device_private(dv);
747 1.30 augustss int cmd;
748 1.30 augustss
749 1.248 mrg mutex_spin_enter(&sc->sc_intr_lock);
750 1.212 jmcneill
751 1.30 augustss cmd = UREAD2(sc, UHCI_CMD);
752 1.30 augustss
753 1.212 jmcneill #ifdef UHCI_DEBUG
754 1.212 jmcneill if (uhcidebug > 2)
755 1.212 jmcneill uhci_dumpregs(sc);
756 1.212 jmcneill #endif
757 1.212 jmcneill if (sc->sc_intr_xfer != NULL)
758 1.234 dyoung callout_stop(&sc->sc_poll_handle);
759 1.219 jmcneill sc->sc_suspend = PWR_SUSPEND;
760 1.212 jmcneill sc->sc_bus.use_polling++;
761 1.219 jmcneill
762 1.249 drochner uhci_run(sc, 0, 1); /* stop the controller */
763 1.212 jmcneill cmd &= ~UHCI_CMD_RS;
764 1.212 jmcneill
765 1.212 jmcneill /* save some state if BIOS doesn't */
766 1.212 jmcneill sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM);
767 1.212 jmcneill sc->sc_saved_sof = UREAD1(sc, UHCI_SOF);
768 1.212 jmcneill
769 1.212 jmcneill UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */
770 1.30 augustss
771 1.212 jmcneill UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */
772 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock);
773 1.212 jmcneill sc->sc_bus.use_polling--;
774 1.86 augustss
775 1.248 mrg mutex_spin_exit(&sc->sc_intr_lock);
776 1.212 jmcneill
777 1.212 jmcneill return true;
778 1.30 augustss }
779 1.30 augustss
780 1.59 augustss #ifdef UHCI_DEBUG
781 1.101 augustss Static void
782 1.119 augustss uhci_dumpregs(uhci_softc_t *sc)
783 1.1 augustss {
784 1.48 augustss DPRINTFN(-1,("%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, "
785 1.48 augustss "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n",
786 1.216 drochner device_xname(sc->sc_dev),
787 1.48 augustss UREAD2(sc, UHCI_CMD),
788 1.48 augustss UREAD2(sc, UHCI_STS),
789 1.48 augustss UREAD2(sc, UHCI_INTR),
790 1.48 augustss UREAD2(sc, UHCI_FRNUM),
791 1.48 augustss UREAD4(sc, UHCI_FLBASEADDR),
792 1.48 augustss UREAD1(sc, UHCI_SOF),
793 1.48 augustss UREAD2(sc, UHCI_PORTSC1),
794 1.48 augustss UREAD2(sc, UHCI_PORTSC2)));
795 1.1 augustss }
796 1.1 augustss
797 1.1 augustss void
798 1.119 augustss uhci_dump_td(uhci_soft_td_t *p)
799 1.1 augustss {
800 1.122 tv char sbuf[128], sbuf2[128];
801 1.122 tv
802 1.250 christos
803 1.223 bouyer usb_syncmem(&p->dma, p->offs, sizeof(p->td),
804 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
805 1.48 augustss DPRINTFN(-1,("TD(%p) at %08lx = link=0x%08lx status=0x%08lx "
806 1.48 augustss "token=0x%08lx buffer=0x%08lx\n",
807 1.48 augustss p, (long)p->physaddr,
808 1.88 tsutsui (long)le32toh(p->td.td_link),
809 1.88 tsutsui (long)le32toh(p->td.td_status),
810 1.88 tsutsui (long)le32toh(p->td.td_token),
811 1.88 tsutsui (long)le32toh(p->td.td_buffer)));
812 1.122 tv
813 1.224 christos snprintb(sbuf, sizeof(sbuf), "\20\1T\2Q\3VF",
814 1.264.4.1 skrll (uint32_t)le32toh(p->td.td_link));
815 1.224 christos snprintb(sbuf2, sizeof(sbuf2),
816 1.224 christos "\20\22BITSTUFF\23CRCTO\24NAK\25BABBLE\26DBUFFER\27"
817 1.224 christos "STALLED\30ACTIVE\31IOC\32ISO\33LS\36SPD",
818 1.264.4.1 skrll (uint32_t)le32toh(p->td.td_status));
819 1.122 tv
820 1.122 tv DPRINTFN(-1,(" %s %s,errcnt=%d,actlen=%d pid=%02x,addr=%d,endpt=%d,"
821 1.122 tv "D=%d,maxlen=%d\n", sbuf, sbuf2,
822 1.88 tsutsui UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)),
823 1.88 tsutsui UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)),
824 1.88 tsutsui UHCI_TD_GET_PID(le32toh(p->td.td_token)),
825 1.88 tsutsui UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)),
826 1.88 tsutsui UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)),
827 1.88 tsutsui UHCI_TD_GET_DT(le32toh(p->td.td_token)),
828 1.88 tsutsui UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token))));
829 1.223 bouyer usb_syncmem(&p->dma, p->offs, sizeof(p->td),
830 1.223 bouyer BUS_DMASYNC_PREREAD);
831 1.1 augustss }
832 1.1 augustss
833 1.1 augustss void
834 1.119 augustss uhci_dump_qh(uhci_soft_qh_t *sqh)
835 1.1 augustss {
836 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
837 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
838 1.67 augustss DPRINTFN(-1,("QH(%p) at %08x: hlink=%08x elink=%08x\n", sqh,
839 1.88 tsutsui (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink),
840 1.88 tsutsui le32toh(sqh->qh.qh_elink)));
841 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD);
842 1.1 augustss }
843 1.1 augustss
844 1.13 augustss
845 1.110 augustss #if 1
846 1.1 augustss void
847 1.119 augustss uhci_dump(void)
848 1.1 augustss {
849 1.110 augustss uhci_dump_all(thesc);
850 1.110 augustss }
851 1.110 augustss #endif
852 1.1 augustss
853 1.110 augustss void
854 1.119 augustss uhci_dump_all(uhci_softc_t *sc)
855 1.110 augustss {
856 1.1 augustss uhci_dumpregs(sc);
857 1.110 augustss /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/
858 1.261 skrll uhci_dump_qhs(sc->sc_lctl_start);
859 1.1 augustss }
860 1.1 augustss
861 1.67 augustss
862 1.67 augustss void
863 1.119 augustss uhci_dump_qhs(uhci_soft_qh_t *sqh)
864 1.67 augustss {
865 1.67 augustss uhci_dump_qh(sqh);
866 1.67 augustss
867 1.67 augustss /* uhci_dump_qhs displays all the QHs and TDs from the given QH onwards
868 1.67 augustss * Traverses sideways first, then down.
869 1.67 augustss *
870 1.67 augustss * QH1
871 1.67 augustss * QH2
872 1.67 augustss * No QH
873 1.67 augustss * TD2.1
874 1.67 augustss * TD2.2
875 1.67 augustss * TD1.1
876 1.67 augustss * etc.
877 1.67 augustss *
878 1.67 augustss * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1.
879 1.67 augustss */
880 1.67 augustss
881 1.67 augustss
882 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
883 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
884 1.88 tsutsui if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T))
885 1.67 augustss uhci_dump_qhs(sqh->hlink);
886 1.67 augustss else
887 1.67 augustss DPRINTF(("No QH\n"));
888 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD);
889 1.67 augustss
890 1.88 tsutsui if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T))
891 1.67 augustss uhci_dump_tds(sqh->elink);
892 1.67 augustss else
893 1.67 augustss DPRINTF(("No TD\n"));
894 1.67 augustss }
895 1.67 augustss
896 1.1 augustss void
897 1.119 augustss uhci_dump_tds(uhci_soft_td_t *std)
898 1.1 augustss {
899 1.67 augustss uhci_soft_td_t *td;
900 1.223 bouyer int stop;
901 1.67 augustss
902 1.67 augustss for(td = std; td != NULL; td = td->link.std) {
903 1.67 augustss uhci_dump_td(td);
904 1.1 augustss
905 1.67 augustss /* Check whether the link pointer in this TD marks
906 1.67 augustss * the link pointer as end of queue. This avoids
907 1.67 augustss * printing the free list in case the queue/TD has
908 1.67 augustss * already been moved there (seatbelt).
909 1.67 augustss */
910 1.223 bouyer usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link),
911 1.223 bouyer sizeof(td->td.td_link),
912 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
913 1.223 bouyer stop = (le32toh(td->td.td_link) & UHCI_PTR_T ||
914 1.223 bouyer le32toh(td->td.td_link) == 0);
915 1.223 bouyer usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link),
916 1.223 bouyer sizeof(td->td.td_link), BUS_DMASYNC_PREREAD);
917 1.223 bouyer if (stop)
918 1.67 augustss break;
919 1.67 augustss }
920 1.1 augustss }
921 1.92 augustss
922 1.101 augustss Static void
923 1.119 augustss uhci_dump_ii(uhci_intr_info_t *ii)
924 1.92 augustss {
925 1.95 augustss usbd_pipe_handle pipe;
926 1.95 augustss usb_endpoint_descriptor_t *ed;
927 1.95 augustss usbd_device_handle dev;
928 1.152 augustss
929 1.98 augustss #ifdef DIAGNOSTIC
930 1.98 augustss #define DONE ii->isdone
931 1.98 augustss #else
932 1.98 augustss #define DONE 0
933 1.98 augustss #endif
934 1.264.4.2 skrll if (ii == NULL) {
935 1.264.4.2 skrll printf("ii NULL\n");
936 1.264.4.2 skrll return;
937 1.264.4.2 skrll }
938 1.264.4.2 skrll if (ii->xfer == NULL) {
939 1.95 augustss printf("ii %p: done=%d xfer=NULL\n",
940 1.98 augustss ii, DONE);
941 1.264.4.2 skrll return;
942 1.264.4.2 skrll }
943 1.264.4.2 skrll pipe = ii->xfer->pipe;
944 1.264.4.2 skrll if (pipe == NULL) {
945 1.95 augustss printf("ii %p: done=%d xfer=%p pipe=NULL\n",
946 1.264.4.2 skrll ii, DONE, ii->xfer);
947 1.264.4.2 skrll return;
948 1.139 augustss }
949 1.264.4.2 skrll if (pipe->endpoint == NULL) {
950 1.139 augustss printf("ii %p: done=%d xfer=%p pipe=%p pipe->endpoint=NULL\n",
951 1.139 augustss ii, DONE, ii->xfer, pipe);
952 1.264.4.2 skrll return;
953 1.139 augustss }
954 1.264.4.2 skrll if (pipe->device == NULL) {
955 1.139 augustss printf("ii %p: done=%d xfer=%p pipe=%p pipe->device=NULL\n",
956 1.139 augustss ii, DONE, ii->xfer, pipe);
957 1.264.4.2 skrll return;
958 1.95 augustss }
959 1.264.4.2 skrll ed = pipe->endpoint->edesc;
960 1.264.4.2 skrll dev = pipe->device;
961 1.152 augustss printf("ii %p: done=%d xfer=%p dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n",
962 1.152 augustss ii, DONE, ii->xfer, dev,
963 1.95 augustss UGETW(dev->ddesc.idVendor),
964 1.92 augustss UGETW(dev->ddesc.idProduct),
965 1.92 augustss dev->address, pipe,
966 1.92 augustss ed->bEndpointAddress, ed->bmAttributes);
967 1.98 augustss #undef DONE
968 1.92 augustss }
969 1.92 augustss
970 1.120 augustss void uhci_dump_iis(struct uhci_softc *sc);
971 1.92 augustss void
972 1.119 augustss uhci_dump_iis(struct uhci_softc *sc)
973 1.92 augustss {
974 1.92 augustss uhci_intr_info_t *ii;
975 1.92 augustss
976 1.92 augustss printf("intr_info list:\n");
977 1.92 augustss for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = LIST_NEXT(ii, list))
978 1.92 augustss uhci_dump_ii(ii);
979 1.92 augustss }
980 1.92 augustss
981 1.120 augustss void iidump(void);
982 1.119 augustss void iidump(void) { uhci_dump_iis(thesc); }
983 1.92 augustss
984 1.1 augustss #endif
985 1.1 augustss
986 1.1 augustss /*
987 1.1 augustss * This routine is executed periodically and simulates interrupts
988 1.1 augustss * from the root controller interrupt pipe for port status change.
989 1.1 augustss */
990 1.1 augustss void
991 1.119 augustss uhci_poll_hub(void *addr)
992 1.1 augustss {
993 1.63 augustss usbd_xfer_handle xfer = addr;
994 1.63 augustss usbd_pipe_handle pipe = xfer->pipe;
995 1.227 martin uhci_softc_t *sc;
996 1.1 augustss u_char *p;
997 1.1 augustss
998 1.96 augustss DPRINTFN(20, ("uhci_poll_hub\n"));
999 1.1 augustss
1000 1.228 martin if (__predict_false(pipe->device == NULL || pipe->device->bus == NULL))
1001 1.228 martin return; /* device has detached */
1002 1.227 martin sc = pipe->device->bus->hci_private;
1003 1.234 dyoung callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer);
1004 1.41 augustss
1005 1.159 augustss p = KERNADDR(&xfer->dmabuf, 0);
1006 1.1 augustss p[0] = 0;
1007 1.1 augustss if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC))
1008 1.1 augustss p[0] |= 1<<1;
1009 1.1 augustss if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC))
1010 1.1 augustss p[0] |= 1<<2;
1011 1.41 augustss if (p[0] == 0)
1012 1.41 augustss /* No change, try again in a while */
1013 1.41 augustss return;
1014 1.41 augustss
1015 1.63 augustss xfer->actlen = 1;
1016 1.63 augustss xfer->status = USBD_NORMAL_COMPLETION;
1017 1.248 mrg mutex_enter(&sc->sc_lock);
1018 1.63 augustss usb_transfer_complete(xfer);
1019 1.248 mrg mutex_exit(&sc->sc_lock);
1020 1.41 augustss }
1021 1.41 augustss
1022 1.41 augustss void
1023 1.205 christos uhci_root_intr_done(usbd_xfer_handle xfer)
1024 1.84 augustss {
1025 1.84 augustss }
1026 1.84 augustss
1027 1.84 augustss void
1028 1.205 christos uhci_root_ctrl_done(usbd_xfer_handle xfer)
1029 1.41 augustss {
1030 1.1 augustss }
1031 1.1 augustss
1032 1.123 augustss /*
1033 1.123 augustss * Let the last QH loop back to the high speed control transfer QH.
1034 1.123 augustss * This is what intel calls "bandwidth reclamation" and improves
1035 1.123 augustss * USB performance a lot for some devices.
1036 1.123 augustss * If we are already looping, just count it.
1037 1.123 augustss */
1038 1.1 augustss void
1039 1.123 augustss uhci_add_loop(uhci_softc_t *sc) {
1040 1.125 augustss #ifdef UHCI_DEBUG
1041 1.125 augustss if (uhcinoloop)
1042 1.125 augustss return;
1043 1.125 augustss #endif
1044 1.123 augustss if (++sc->sc_loops == 1) {
1045 1.125 augustss DPRINTFN(5,("uhci_start_loop: add\n"));
1046 1.123 augustss /* Note, we don't loop back the soft pointer. */
1047 1.152 augustss sc->sc_last_qh->qh.qh_hlink =
1048 1.123 augustss htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH);
1049 1.223 bouyer usb_syncmem(&sc->sc_last_qh->dma,
1050 1.223 bouyer sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink),
1051 1.223 bouyer sizeof(sc->sc_last_qh->qh.qh_hlink),
1052 1.223 bouyer BUS_DMASYNC_PREWRITE);
1053 1.123 augustss }
1054 1.123 augustss }
1055 1.123 augustss
1056 1.123 augustss void
1057 1.123 augustss uhci_rem_loop(uhci_softc_t *sc) {
1058 1.125 augustss #ifdef UHCI_DEBUG
1059 1.125 augustss if (uhcinoloop)
1060 1.125 augustss return;
1061 1.125 augustss #endif
1062 1.123 augustss if (--sc->sc_loops == 0) {
1063 1.123 augustss DPRINTFN(5,("uhci_end_loop: remove\n"));
1064 1.123 augustss sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T);
1065 1.223 bouyer usb_syncmem(&sc->sc_last_qh->dma,
1066 1.223 bouyer sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink),
1067 1.223 bouyer sizeof(sc->sc_last_qh->qh.qh_hlink),
1068 1.223 bouyer BUS_DMASYNC_PREWRITE);
1069 1.123 augustss }
1070 1.123 augustss }
1071 1.123 augustss
1072 1.248 mrg /* Add high speed control QH, called with lock held. */
1073 1.123 augustss void
1074 1.123 augustss uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1075 1.1 augustss {
1076 1.42 augustss uhci_soft_qh_t *eqh;
1077 1.1 augustss
1078 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
1079 1.248 mrg
1080 1.1 augustss DPRINTFN(10, ("uhci_add_ctrl: sqh=%p\n", sqh));
1081 1.123 augustss eqh = sc->sc_hctl_end;
1082 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1083 1.223 bouyer sizeof(eqh->qh.qh_hlink),
1084 1.223 bouyer BUS_DMASYNC_POSTWRITE);
1085 1.42 augustss sqh->hlink = eqh->hlink;
1086 1.42 augustss sqh->qh.qh_hlink = eqh->qh.qh_hlink;
1087 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1088 1.223 bouyer BUS_DMASYNC_PREWRITE);
1089 1.42 augustss eqh->hlink = sqh;
1090 1.121 augustss eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
1091 1.123 augustss sc->sc_hctl_end = sqh;
1092 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1093 1.223 bouyer sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
1094 1.125 augustss #ifdef UHCI_CTL_LOOP
1095 1.123 augustss uhci_add_loop(sc);
1096 1.125 augustss #endif
1097 1.1 augustss }
1098 1.1 augustss
1099 1.248 mrg /* Remove high speed control QH, called with lock held. */
1100 1.1 augustss void
1101 1.123 augustss uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1102 1.1 augustss {
1103 1.1 augustss uhci_soft_qh_t *pqh;
1104 1.256 tsutsui uint32_t elink;
1105 1.1 augustss
1106 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
1107 1.248 mrg
1108 1.123 augustss DPRINTFN(10, ("uhci_remove_hs_ctrl: sqh=%p\n", sqh));
1109 1.125 augustss #ifdef UHCI_CTL_LOOP
1110 1.123 augustss uhci_rem_loop(sc);
1111 1.125 augustss #endif
1112 1.124 augustss /*
1113 1.124 augustss * The T bit should be set in the elink of the QH so that the HC
1114 1.124 augustss * doesn't follow the pointer. This condition may fail if the
1115 1.124 augustss * the transferred packet was short so that the QH still points
1116 1.124 augustss * at the last used TD.
1117 1.124 augustss * In this case we set the T bit and wait a little for the HC
1118 1.124 augustss * to stop looking at the TD.
1119 1.223 bouyer * Note that if the TD chain is large enough, the controller
1120 1.223 bouyer * may still be looking at the chain at the end of this function.
1121 1.223 bouyer * uhci_free_std_chain() will make sure the controller stops
1122 1.223 bouyer * looking at it quickly, but until then we should not change
1123 1.223 bouyer * sqh->hlink.
1124 1.124 augustss */
1125 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
1126 1.223 bouyer sizeof(sqh->qh.qh_elink),
1127 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1128 1.256 tsutsui elink = le32toh(sqh->qh.qh_elink);
1129 1.256 tsutsui usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
1130 1.256 tsutsui sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD);
1131 1.256 tsutsui if (!(elink & UHCI_PTR_T)) {
1132 1.124 augustss sqh->qh.qh_elink = htole32(UHCI_PTR_T);
1133 1.223 bouyer usb_syncmem(&sqh->dma,
1134 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
1135 1.223 bouyer sizeof(sqh->qh.qh_elink),
1136 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1137 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1138 1.124 augustss }
1139 1.124 augustss
1140 1.123 augustss pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh);
1141 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
1142 1.223 bouyer sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
1143 1.152 augustss pqh->hlink = sqh->hlink;
1144 1.42 augustss pqh->qh.qh_hlink = sqh->qh.qh_hlink;
1145 1.223 bouyer usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
1146 1.223 bouyer sizeof(pqh->qh.qh_hlink),
1147 1.223 bouyer BUS_DMASYNC_PREWRITE);
1148 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1149 1.123 augustss if (sc->sc_hctl_end == sqh)
1150 1.123 augustss sc->sc_hctl_end = pqh;
1151 1.123 augustss }
1152 1.123 augustss
1153 1.248 mrg /* Add low speed control QH, called with lock held. */
1154 1.123 augustss void
1155 1.123 augustss uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1156 1.123 augustss {
1157 1.123 augustss uhci_soft_qh_t *eqh;
1158 1.123 augustss
1159 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
1160 1.248 mrg
1161 1.123 augustss DPRINTFN(10, ("uhci_add_ls_ctrl: sqh=%p\n", sqh));
1162 1.123 augustss eqh = sc->sc_lctl_end;
1163 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1164 1.223 bouyer sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
1165 1.152 augustss sqh->hlink = eqh->hlink;
1166 1.123 augustss sqh->qh.qh_hlink = eqh->qh.qh_hlink;
1167 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1168 1.223 bouyer BUS_DMASYNC_PREWRITE);
1169 1.152 augustss eqh->hlink = sqh;
1170 1.123 augustss eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
1171 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1172 1.223 bouyer sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
1173 1.123 augustss sc->sc_lctl_end = sqh;
1174 1.123 augustss }
1175 1.123 augustss
1176 1.248 mrg /* Remove low speed control QH, called with lock held. */
1177 1.123 augustss void
1178 1.123 augustss uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1179 1.123 augustss {
1180 1.123 augustss uhci_soft_qh_t *pqh;
1181 1.256 tsutsui uint32_t elink;
1182 1.123 augustss
1183 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
1184 1.248 mrg
1185 1.123 augustss DPRINTFN(10, ("uhci_remove_ls_ctrl: sqh=%p\n", sqh));
1186 1.124 augustss /* See comment in uhci_remove_hs_ctrl() */
1187 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
1188 1.223 bouyer sizeof(sqh->qh.qh_elink),
1189 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1190 1.256 tsutsui elink = le32toh(sqh->qh.qh_elink);
1191 1.256 tsutsui usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
1192 1.256 tsutsui sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD);
1193 1.256 tsutsui if (!(elink & UHCI_PTR_T)) {
1194 1.124 augustss sqh->qh.qh_elink = htole32(UHCI_PTR_T);
1195 1.223 bouyer usb_syncmem(&sqh->dma,
1196 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
1197 1.223 bouyer sizeof(sqh->qh.qh_elink),
1198 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1199 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1200 1.124 augustss }
1201 1.123 augustss pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh);
1202 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
1203 1.223 bouyer sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
1204 1.152 augustss pqh->hlink = sqh->hlink;
1205 1.123 augustss pqh->qh.qh_hlink = sqh->qh.qh_hlink;
1206 1.223 bouyer usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
1207 1.223 bouyer sizeof(pqh->qh.qh_hlink),
1208 1.223 bouyer BUS_DMASYNC_PREWRITE);
1209 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1210 1.123 augustss if (sc->sc_lctl_end == sqh)
1211 1.123 augustss sc->sc_lctl_end = pqh;
1212 1.1 augustss }
1213 1.1 augustss
1214 1.248 mrg /* Add bulk QH, called with lock held. */
1215 1.1 augustss void
1216 1.119 augustss uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1217 1.1 augustss {
1218 1.42 augustss uhci_soft_qh_t *eqh;
1219 1.1 augustss
1220 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
1221 1.248 mrg
1222 1.1 augustss DPRINTFN(10, ("uhci_add_bulk: sqh=%p\n", sqh));
1223 1.42 augustss eqh = sc->sc_bulk_end;
1224 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1225 1.223 bouyer sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
1226 1.152 augustss sqh->hlink = eqh->hlink;
1227 1.42 augustss sqh->qh.qh_hlink = eqh->qh.qh_hlink;
1228 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1229 1.223 bouyer BUS_DMASYNC_PREWRITE);
1230 1.152 augustss eqh->hlink = sqh;
1231 1.121 augustss eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
1232 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1233 1.223 bouyer sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
1234 1.1 augustss sc->sc_bulk_end = sqh;
1235 1.123 augustss uhci_add_loop(sc);
1236 1.1 augustss }
1237 1.1 augustss
1238 1.248 mrg /* Remove bulk QH, called with lock held. */
1239 1.1 augustss void
1240 1.119 augustss uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1241 1.1 augustss {
1242 1.1 augustss uhci_soft_qh_t *pqh;
1243 1.1 augustss
1244 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
1245 1.248 mrg
1246 1.1 augustss DPRINTFN(10, ("uhci_remove_bulk: sqh=%p\n", sqh));
1247 1.123 augustss uhci_rem_loop(sc);
1248 1.124 augustss /* See comment in uhci_remove_hs_ctrl() */
1249 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
1250 1.223 bouyer sizeof(sqh->qh.qh_elink),
1251 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1252 1.124 augustss if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) {
1253 1.124 augustss sqh->qh.qh_elink = htole32(UHCI_PTR_T);
1254 1.223 bouyer usb_syncmem(&sqh->dma,
1255 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
1256 1.223 bouyer sizeof(sqh->qh.qh_elink),
1257 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1258 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1259 1.124 augustss }
1260 1.92 augustss pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh);
1261 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
1262 1.223 bouyer sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
1263 1.42 augustss pqh->hlink = sqh->hlink;
1264 1.42 augustss pqh->qh.qh_hlink = sqh->qh.qh_hlink;
1265 1.223 bouyer usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
1266 1.223 bouyer sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
1267 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1268 1.1 augustss if (sc->sc_bulk_end == sqh)
1269 1.1 augustss sc->sc_bulk_end = pqh;
1270 1.1 augustss }
1271 1.1 augustss
1272 1.141 augustss Static int uhci_intr1(uhci_softc_t *);
1273 1.141 augustss
1274 1.1 augustss int
1275 1.119 augustss uhci_intr(void *arg)
1276 1.1 augustss {
1277 1.44 augustss uhci_softc_t *sc = arg;
1278 1.248 mrg int ret = 0;
1279 1.248 mrg
1280 1.248 mrg mutex_spin_enter(&sc->sc_intr_lock);
1281 1.146 augustss
1282 1.216 drochner if (sc->sc_dying || !device_has_power(sc->sc_dev))
1283 1.248 mrg goto done;
1284 1.141 augustss
1285 1.225 bouyer if (sc->sc_bus.use_polling || UREAD2(sc, UHCI_INTR) == 0) {
1286 1.141 augustss #ifdef DIAGNOSTIC
1287 1.179 mycroft DPRINTFN(16, ("uhci_intr: ignored interrupt while polling\n"));
1288 1.141 augustss #endif
1289 1.248 mrg goto done;
1290 1.141 augustss }
1291 1.179 mycroft
1292 1.248 mrg ret = uhci_intr1(sc);
1293 1.248 mrg
1294 1.248 mrg done:
1295 1.248 mrg mutex_spin_exit(&sc->sc_intr_lock);
1296 1.248 mrg return ret;
1297 1.141 augustss }
1298 1.141 augustss
1299 1.141 augustss int
1300 1.141 augustss uhci_intr1(uhci_softc_t *sc)
1301 1.141 augustss {
1302 1.44 augustss int status;
1303 1.44 augustss int ack;
1304 1.1 augustss
1305 1.67 augustss #ifdef UHCI_DEBUG
1306 1.44 augustss if (uhcidebug > 15) {
1307 1.216 drochner DPRINTF(("%s: uhci_intr1\n", device_xname(sc->sc_dev)));
1308 1.1 augustss uhci_dumpregs(sc);
1309 1.1 augustss }
1310 1.1 augustss #endif
1311 1.117 augustss
1312 1.248 mrg KASSERT(mutex_owned(&sc->sc_intr_lock));
1313 1.248 mrg
1314 1.153 augustss status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS;
1315 1.127 soren if (status == 0) /* The interrupt was not for us. */
1316 1.127 soren return (0);
1317 1.127 soren
1318 1.117 augustss if (sc->sc_suspend != PWR_RESUME) {
1319 1.201 jmcneill #ifdef DIAGNOSTIC
1320 1.117 augustss printf("%s: interrupt while not operating ignored\n",
1321 1.216 drochner device_xname(sc->sc_dev));
1322 1.201 jmcneill #endif
1323 1.134 augustss UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */
1324 1.117 augustss return (0);
1325 1.117 augustss }
1326 1.44 augustss
1327 1.44 augustss ack = 0;
1328 1.44 augustss if (status & UHCI_STS_USBINT)
1329 1.44 augustss ack |= UHCI_STS_USBINT;
1330 1.44 augustss if (status & UHCI_STS_USBEI)
1331 1.44 augustss ack |= UHCI_STS_USBEI;
1332 1.1 augustss if (status & UHCI_STS_RD) {
1333 1.44 augustss ack |= UHCI_STS_RD;
1334 1.118 augustss #ifdef UHCI_DEBUG
1335 1.216 drochner printf("%s: resume detect\n", device_xname(sc->sc_dev));
1336 1.118 augustss #endif
1337 1.1 augustss }
1338 1.1 augustss if (status & UHCI_STS_HSE) {
1339 1.44 augustss ack |= UHCI_STS_HSE;
1340 1.216 drochner printf("%s: host system error\n", device_xname(sc->sc_dev));
1341 1.1 augustss }
1342 1.1 augustss if (status & UHCI_STS_HCPE) {
1343 1.44 augustss ack |= UHCI_STS_HCPE;
1344 1.152 augustss printf("%s: host controller process error\n",
1345 1.216 drochner device_xname(sc->sc_dev));
1346 1.44 augustss }
1347 1.233 msaitoh
1348 1.233 msaitoh /* When HCHalted=1 and Run/Stop=0 , it is normal */
1349 1.233 msaitoh if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) {
1350 1.44 augustss /* no acknowledge needed */
1351 1.136 augustss if (!sc->sc_dying) {
1352 1.152 augustss printf("%s: host controller halted\n",
1353 1.216 drochner device_xname(sc->sc_dev));
1354 1.110 augustss #ifdef UHCI_DEBUG
1355 1.136 augustss uhci_dump_all(sc);
1356 1.110 augustss #endif
1357 1.136 augustss }
1358 1.136 augustss sc->sc_dying = 1;
1359 1.1 augustss }
1360 1.44 augustss
1361 1.132 augustss if (!ack)
1362 1.132 augustss return (0); /* nothing to acknowledge */
1363 1.132 augustss UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */
1364 1.1 augustss
1365 1.85 augustss usb_schedsoftintr(&sc->sc_bus);
1366 1.85 augustss
1367 1.216 drochner DPRINTFN(15, ("%s: uhci_intr: exit\n", device_xname(sc->sc_dev)));
1368 1.85 augustss
1369 1.85 augustss return (1);
1370 1.85 augustss }
1371 1.85 augustss
1372 1.85 augustss void
1373 1.133 augustss uhci_softintr(void *v)
1374 1.85 augustss {
1375 1.216 drochner struct usbd_bus *bus = v;
1376 1.216 drochner uhci_softc_t *sc = bus->hci_private;
1377 1.178 martin uhci_intr_info_t *ii, *nextii;
1378 1.85 augustss
1379 1.248 mrg KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock));
1380 1.248 mrg
1381 1.247 mrg DPRINTFN(10,("%s: uhci_softintr\n", device_xname(sc->sc_dev)));
1382 1.50 augustss
1383 1.1 augustss /*
1384 1.1 augustss * Interrupts on UHCI really suck. When the host controller
1385 1.1 augustss * interrupts because a transfer is completed there is no
1386 1.1 augustss * way of knowing which transfer it was. You can scan down
1387 1.1 augustss * the TDs and QHs of the previous frame to limit the search,
1388 1.1 augustss * but that assumes that the interrupt was not delayed by more
1389 1.1 augustss * than 1 ms, which may not always be true (e.g. after debug
1390 1.1 augustss * output on a slow console).
1391 1.1 augustss * We scan all interrupt descriptors to see if any have
1392 1.1 augustss * completed.
1393 1.1 augustss */
1394 1.178 martin for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = nextii) {
1395 1.178 martin nextii = LIST_NEXT(ii, list);
1396 1.1 augustss uhci_check_intr(sc, ii);
1397 1.178 martin }
1398 1.1 augustss
1399 1.153 augustss if (sc->sc_softwake) {
1400 1.153 augustss sc->sc_softwake = 0;
1401 1.248 mrg cv_broadcast(&sc->sc_softwake_cv);
1402 1.153 augustss }
1403 1.1 augustss }
1404 1.1 augustss
1405 1.1 augustss /* Check for an interrupt. */
1406 1.1 augustss void
1407 1.205 christos uhci_check_intr(uhci_softc_t *sc, uhci_intr_info_t *ii)
1408 1.1 augustss {
1409 1.1 augustss uhci_soft_td_t *std, *lstd;
1410 1.264.4.1 skrll uint32_t status;
1411 1.1 augustss
1412 1.1 augustss DPRINTFN(15, ("uhci_check_intr: ii=%p\n", ii));
1413 1.1 augustss #ifdef DIAGNOSTIC
1414 1.63 augustss if (ii == NULL) {
1415 1.1 augustss printf("uhci_check_intr: no ii? %p\n", ii);
1416 1.1 augustss return;
1417 1.1 augustss }
1418 1.1 augustss #endif
1419 1.155 augustss if (ii->xfer->status == USBD_CANCELLED ||
1420 1.155 augustss ii->xfer->status == USBD_TIMEOUT) {
1421 1.155 augustss DPRINTF(("uhci_check_intr: aborted xfer=%p\n", ii->xfer));
1422 1.155 augustss return;
1423 1.155 augustss }
1424 1.155 augustss
1425 1.63 augustss if (ii->stdstart == NULL)
1426 1.1 augustss return;
1427 1.1 augustss lstd = ii->stdend;
1428 1.1 augustss #ifdef DIAGNOSTIC
1429 1.63 augustss if (lstd == NULL) {
1430 1.1 augustss printf("uhci_check_intr: std==0\n");
1431 1.1 augustss return;
1432 1.1 augustss }
1433 1.1 augustss #endif
1434 1.223 bouyer usb_syncmem(&lstd->dma,
1435 1.223 bouyer lstd->offs + offsetof(uhci_td_t, td_status),
1436 1.223 bouyer sizeof(lstd->td.td_status),
1437 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1438 1.256 tsutsui status = le32toh(lstd->td.td_status);
1439 1.256 tsutsui usb_syncmem(&lstd->dma,
1440 1.256 tsutsui lstd->offs + offsetof(uhci_td_t, td_status),
1441 1.256 tsutsui sizeof(lstd->td.td_status),
1442 1.256 tsutsui BUS_DMASYNC_PREREAD);
1443 1.258 skrll
1444 1.258 skrll /* If the last TD is not marked active we can complete */
1445 1.258 skrll if (!(status & UHCI_TD_ACTIVE)) {
1446 1.258 skrll done:
1447 1.258 skrll DPRINTFN(12, ("uhci_check_intr: ii=%p done\n", ii));
1448 1.258 skrll callout_stop(&ii->xfer->timeout_handle);
1449 1.258 skrll uhci_idone(ii);
1450 1.258 skrll return;
1451 1.258 skrll }
1452 1.258 skrll
1453 1.258 skrll /*
1454 1.258 skrll * If the last TD is still active we need to check whether there
1455 1.258 skrll * is an error somewhere in the middle, or whether there was a
1456 1.258 skrll * short packet (SPD and not ACTIVE).
1457 1.258 skrll */
1458 1.258 skrll DPRINTFN(12, ("uhci_check_intr: active ii=%p\n", ii));
1459 1.258 skrll for (std = ii->stdstart; std != lstd; std = std->link.std) {
1460 1.258 skrll usb_syncmem(&std->dma,
1461 1.258 skrll std->offs + offsetof(uhci_td_t, td_status),
1462 1.258 skrll sizeof(std->td.td_status),
1463 1.258 skrll BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1464 1.258 skrll status = le32toh(std->td.td_status);
1465 1.258 skrll usb_syncmem(&std->dma,
1466 1.258 skrll std->offs + offsetof(uhci_td_t, td_status),
1467 1.258 skrll sizeof(std->td.td_status), BUS_DMASYNC_PREREAD);
1468 1.258 skrll
1469 1.258 skrll /* If there's an active TD the xfer isn't done. */
1470 1.258 skrll if (status & UHCI_TD_ACTIVE) {
1471 1.258 skrll DPRINTFN(12, ("%s: ii=%p std=%p still active\n",
1472 1.258 skrll __func__, ii, std));
1473 1.258 skrll return;
1474 1.258 skrll }
1475 1.258 skrll
1476 1.258 skrll /* Any kind of error makes the xfer done. */
1477 1.258 skrll if (status & UHCI_TD_STALLED)
1478 1.258 skrll goto done;
1479 1.258 skrll
1480 1.258 skrll /*
1481 1.258 skrll * If the data phase of a control transfer is short, we need
1482 1.258 skrll * to complete the status stage
1483 1.258 skrll */
1484 1.258 skrll usbd_xfer_handle xfer = ii->xfer;
1485 1.258 skrll usb_endpoint_descriptor_t *ed = xfer->pipe->endpoint->edesc;
1486 1.258 skrll uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
1487 1.258 skrll
1488 1.258 skrll if ((status & UHCI_TD_SPD) && xfertype == UE_CONTROL) {
1489 1.258 skrll struct uhci_pipe *upipe =
1490 1.258 skrll (struct uhci_pipe *)xfer->pipe;
1491 1.258 skrll uhci_soft_qh_t *sqh = upipe->u.ctl.sqh;
1492 1.258 skrll uhci_soft_td_t *stat = upipe->u.ctl.stat;
1493 1.258 skrll
1494 1.258 skrll DPRINTFN(12, ("%s: ii=%p std=%p control status"
1495 1.258 skrll "phase needs completion\n", __func__, ii,
1496 1.258 skrll ii->stdstart));
1497 1.258 skrll
1498 1.258 skrll sqh->qh.qh_elink =
1499 1.258 skrll htole32(stat->physaddr | UHCI_PTR_TD);
1500 1.258 skrll usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1501 1.258 skrll BUS_DMASYNC_PREWRITE);
1502 1.258 skrll break;
1503 1.258 skrll }
1504 1.258 skrll
1505 1.258 skrll /* We want short packets, and it is short: it's done */
1506 1.258 skrll usb_syncmem(&std->dma,
1507 1.258 skrll std->offs + offsetof(uhci_td_t, td_token),
1508 1.258 skrll sizeof(std->td.td_token),
1509 1.258 skrll BUS_DMASYNC_POSTWRITE);
1510 1.258 skrll
1511 1.258 skrll if ((status & UHCI_TD_SPD) &&
1512 1.258 skrll UHCI_TD_GET_ACTLEN(status) <
1513 1.258 skrll UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) {
1514 1.258 skrll goto done;
1515 1.18 augustss }
1516 1.1 augustss }
1517 1.1 augustss }
1518 1.1 augustss
1519 1.248 mrg /* Called with USB lock held. */
1520 1.1 augustss void
1521 1.119 augustss uhci_idone(uhci_intr_info_t *ii)
1522 1.1 augustss {
1523 1.63 augustss usbd_xfer_handle xfer = ii->xfer;
1524 1.63 augustss struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe;
1525 1.248 mrg #ifdef DIAGNOSTIC
1526 1.248 mrg uhci_softc_t *sc = upipe->pipe.device->bus->hci_private;
1527 1.248 mrg #endif
1528 1.1 augustss uhci_soft_td_t *std;
1529 1.264.4.1 skrll uint32_t status = 0, nstatus;
1530 1.26 augustss int actlen;
1531 1.1 augustss
1532 1.259 skrll KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock));
1533 1.248 mrg
1534 1.140 augustss DPRINTFN(12, ("uhci_idone: ii=%p\n", ii));
1535 1.7 augustss #ifdef DIAGNOSTIC
1536 1.7 augustss {
1537 1.248 mrg /* XXX SMP? */
1538 1.7 augustss int s = splhigh();
1539 1.7 augustss if (ii->isdone) {
1540 1.26 augustss splx(s);
1541 1.92 augustss #ifdef UHCI_DEBUG
1542 1.92 augustss printf("uhci_idone: ii is done!\n ");
1543 1.92 augustss uhci_dump_ii(ii);
1544 1.92 augustss #else
1545 1.36 augustss printf("uhci_idone: ii=%p is done!\n", ii);
1546 1.92 augustss #endif
1547 1.7 augustss return;
1548 1.7 augustss }
1549 1.7 augustss ii->isdone = 1;
1550 1.7 augustss splx(s);
1551 1.7 augustss }
1552 1.7 augustss #endif
1553 1.48 augustss
1554 1.63 augustss if (xfer->nframes != 0) {
1555 1.48 augustss /* Isoc transfer, do things differently. */
1556 1.48 augustss uhci_soft_td_t **stds = upipe->u.iso.stds;
1557 1.126 augustss int i, n, nframes, len;
1558 1.48 augustss
1559 1.48 augustss DPRINTFN(5,("uhci_idone: ii=%p isoc ready\n", ii));
1560 1.48 augustss
1561 1.63 augustss nframes = xfer->nframes;
1562 1.48 augustss actlen = 0;
1563 1.92 augustss n = UXFER(xfer)->curframe;
1564 1.48 augustss for (i = 0; i < nframes; i++) {
1565 1.48 augustss std = stds[n];
1566 1.59 augustss #ifdef UHCI_DEBUG
1567 1.48 augustss if (uhcidebug > 5) {
1568 1.48 augustss DPRINTFN(-1,("uhci_idone: isoc TD %d\n", i));
1569 1.48 augustss uhci_dump_td(std);
1570 1.48 augustss }
1571 1.48 augustss #endif
1572 1.48 augustss if (++n >= UHCI_VFRAMELIST_COUNT)
1573 1.48 augustss n = 0;
1574 1.223 bouyer usb_syncmem(&std->dma,
1575 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
1576 1.223 bouyer sizeof(std->td.td_status),
1577 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1578 1.88 tsutsui status = le32toh(std->td.td_status);
1579 1.126 augustss len = UHCI_TD_GET_ACTLEN(status);
1580 1.126 augustss xfer->frlengths[i] = len;
1581 1.126 augustss actlen += len;
1582 1.48 augustss }
1583 1.48 augustss upipe->u.iso.inuse -= nframes;
1584 1.63 augustss xfer->actlen = actlen;
1585 1.63 augustss xfer->status = USBD_NORMAL_COMPLETION;
1586 1.140 augustss goto end;
1587 1.48 augustss }
1588 1.48 augustss
1589 1.59 augustss #ifdef UHCI_DEBUG
1590 1.65 augustss DPRINTFN(10, ("uhci_idone: ii=%p, xfer=%p, pipe=%p ready\n",
1591 1.65 augustss ii, xfer, upipe));
1592 1.48 augustss if (uhcidebug > 10)
1593 1.48 augustss uhci_dump_tds(ii->stdstart);
1594 1.48 augustss #endif
1595 1.48 augustss
1596 1.26 augustss /* The transfer is done, compute actual length and status. */
1597 1.26 augustss actlen = 0;
1598 1.63 augustss for (std = ii->stdstart; std != NULL; std = std->link.std) {
1599 1.223 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
1600 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1601 1.88 tsutsui nstatus = le32toh(std->td.td_status);
1602 1.64 augustss if (nstatus & UHCI_TD_ACTIVE)
1603 1.26 augustss break;
1604 1.67 augustss
1605 1.64 augustss status = nstatus;
1606 1.88 tsutsui if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) !=
1607 1.88 tsutsui UHCI_TD_PID_SETUP)
1608 1.26 augustss actlen += UHCI_TD_GET_ACTLEN(status);
1609 1.176 mycroft else {
1610 1.176 mycroft /*
1611 1.176 mycroft * UHCI will report CRCTO in addition to a STALL or NAK
1612 1.176 mycroft * for a SETUP transaction. See section 3.2.2, "TD
1613 1.176 mycroft * CONTROL AND STATUS".
1614 1.176 mycroft */
1615 1.176 mycroft if (status & (UHCI_TD_STALLED | UHCI_TD_NAK))
1616 1.176 mycroft status &= ~UHCI_TD_CRCTO;
1617 1.176 mycroft }
1618 1.1 augustss }
1619 1.38 augustss /* If there are left over TDs we need to update the toggle. */
1620 1.63 augustss if (std != NULL)
1621 1.88 tsutsui upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token));
1622 1.38 augustss
1623 1.1 augustss status &= UHCI_TD_ERROR;
1624 1.152 augustss DPRINTFN(10, ("uhci_idone: actlen=%d, status=0x%x\n",
1625 1.26 augustss actlen, status));
1626 1.63 augustss xfer->actlen = actlen;
1627 1.1 augustss if (status != 0) {
1628 1.122 tv #ifdef UHCI_DEBUG
1629 1.122 tv char sbuf[128];
1630 1.122 tv
1631 1.224 christos snprintb(sbuf, sizeof(sbuf),
1632 1.224 christos "\20\22BITSTUFF\23CRCTO\24NAK\25"
1633 1.264.4.1 skrll "BABBLE\26DBUFFER\27STALLED\30ACTIVE",(uint32_t)status);
1634 1.122 tv
1635 1.75 augustss DPRINTFN((status == UHCI_TD_STALLED)*10,
1636 1.36 augustss ("uhci_idone: error, addr=%d, endpt=0x%02x, "
1637 1.122 tv "status 0x%s\n",
1638 1.63 augustss xfer->pipe->device->address,
1639 1.63 augustss xfer->pipe->endpoint->edesc->bEndpointAddress,
1640 1.122 tv sbuf));
1641 1.122 tv #endif
1642 1.122 tv
1643 1.1 augustss if (status == UHCI_TD_STALLED)
1644 1.63 augustss xfer->status = USBD_STALLED;
1645 1.1 augustss else
1646 1.63 augustss xfer->status = USBD_IOERROR; /* more info XXX */
1647 1.1 augustss } else {
1648 1.63 augustss xfer->status = USBD_NORMAL_COMPLETION;
1649 1.1 augustss }
1650 1.140 augustss
1651 1.140 augustss end:
1652 1.63 augustss usb_transfer_complete(xfer);
1653 1.259 skrll KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock));
1654 1.140 augustss DPRINTFN(12, ("uhci_idone: ii=%p done\n", ii));
1655 1.1 augustss }
1656 1.1 augustss
1657 1.13 augustss /*
1658 1.13 augustss * Called when a request does not complete.
1659 1.13 augustss */
1660 1.1 augustss void
1661 1.119 augustss uhci_timeout(void *addr)
1662 1.1 augustss {
1663 1.1 augustss uhci_intr_info_t *ii = addr;
1664 1.153 augustss struct uhci_xfer *uxfer = UXFER(ii->xfer);
1665 1.153 augustss struct uhci_pipe *upipe = (struct uhci_pipe *)uxfer->xfer.pipe;
1666 1.216 drochner uhci_softc_t *sc = upipe->pipe.device->bus->hci_private;
1667 1.153 augustss
1668 1.153 augustss DPRINTF(("uhci_timeout: uxfer=%p\n", uxfer));
1669 1.153 augustss
1670 1.153 augustss if (sc->sc_dying) {
1671 1.248 mrg mutex_enter(&sc->sc_lock);
1672 1.153 augustss uhci_abort_xfer(&uxfer->xfer, USBD_TIMEOUT);
1673 1.248 mrg mutex_exit(&sc->sc_lock);
1674 1.153 augustss return;
1675 1.153 augustss }
1676 1.1 augustss
1677 1.153 augustss /* Execute the abort in a process context. */
1678 1.252 jmcneill usb_init_task(&uxfer->abort_task, uhci_timeout_task, ii->xfer,
1679 1.252 jmcneill USB_TASKQ_MPSAFE);
1680 1.204 joerg usb_add_task(uxfer->xfer.pipe->device, &uxfer->abort_task,
1681 1.204 joerg USB_TASKQ_HC);
1682 1.153 augustss }
1683 1.51 augustss
1684 1.153 augustss void
1685 1.153 augustss uhci_timeout_task(void *addr)
1686 1.153 augustss {
1687 1.153 augustss usbd_xfer_handle xfer = addr;
1688 1.248 mrg uhci_softc_t *sc = xfer->pipe->device->bus->hci_private;
1689 1.153 augustss
1690 1.153 augustss DPRINTF(("uhci_timeout_task: xfer=%p\n", xfer));
1691 1.67 augustss
1692 1.248 mrg mutex_enter(&sc->sc_lock);
1693 1.153 augustss uhci_abort_xfer(xfer, USBD_TIMEOUT);
1694 1.248 mrg mutex_exit(&sc->sc_lock);
1695 1.1 augustss }
1696 1.1 augustss
1697 1.1 augustss /*
1698 1.1 augustss * Wait here until controller claims to have an interrupt.
1699 1.1 augustss * Then call uhci_intr and return. Use timeout to avoid waiting
1700 1.1 augustss * too long.
1701 1.13 augustss * Only used during boot when interrupts are not enabled yet.
1702 1.1 augustss */
1703 1.1 augustss void
1704 1.119 augustss uhci_waitintr(uhci_softc_t *sc, usbd_xfer_handle xfer)
1705 1.1 augustss {
1706 1.63 augustss int timo = xfer->timeout;
1707 1.13 augustss uhci_intr_info_t *ii;
1708 1.13 augustss
1709 1.248 mrg mutex_enter(&sc->sc_lock);
1710 1.248 mrg
1711 1.26 augustss DPRINTFN(10,("uhci_waitintr: timeout = %dms\n", timo));
1712 1.1 augustss
1713 1.63 augustss xfer->status = USBD_IN_PROGRESS;
1714 1.26 augustss for (; timo >= 0; timo--) {
1715 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_lock);
1716 1.26 augustss DPRINTFN(20,("uhci_waitintr: 0x%04x\n", UREAD2(sc, UHCI_STS)));
1717 1.1 augustss if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) {
1718 1.248 mrg mutex_spin_enter(&sc->sc_intr_lock);
1719 1.141 augustss uhci_intr1(sc);
1720 1.248 mrg mutex_spin_exit(&sc->sc_intr_lock);
1721 1.63 augustss if (xfer->status != USBD_IN_PROGRESS)
1722 1.248 mrg goto done;
1723 1.1 augustss }
1724 1.1 augustss }
1725 1.13 augustss
1726 1.13 augustss /* Timeout */
1727 1.13 augustss DPRINTF(("uhci_waitintr: timeout\n"));
1728 1.13 augustss for (ii = LIST_FIRST(&sc->sc_intrhead);
1729 1.152 augustss ii != NULL && ii->xfer != xfer;
1730 1.13 augustss ii = LIST_NEXT(ii, list))
1731 1.13 augustss ;
1732 1.41 augustss #ifdef DIAGNOSTIC
1733 1.63 augustss if (ii == NULL)
1734 1.163 provos panic("uhci_waitintr: lost intr_info");
1735 1.41 augustss #endif
1736 1.41 augustss uhci_idone(ii);
1737 1.248 mrg
1738 1.248 mrg done:
1739 1.248 mrg mutex_exit(&sc->sc_lock);
1740 1.1 augustss }
1741 1.1 augustss
1742 1.8 augustss void
1743 1.119 augustss uhci_poll(struct usbd_bus *bus)
1744 1.8 augustss {
1745 1.216 drochner uhci_softc_t *sc = bus->hci_private;
1746 1.8 augustss
1747 1.248 mrg if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) {
1748 1.248 mrg mutex_spin_enter(&sc->sc_intr_lock);
1749 1.141 augustss uhci_intr1(sc);
1750 1.248 mrg mutex_spin_exit(&sc->sc_intr_lock);
1751 1.248 mrg }
1752 1.8 augustss }
1753 1.8 augustss
1754 1.1 augustss void
1755 1.119 augustss uhci_reset(uhci_softc_t *sc)
1756 1.1 augustss {
1757 1.1 augustss int n;
1758 1.1 augustss
1759 1.1 augustss UHCICMD(sc, UHCI_CMD_HCRESET);
1760 1.1 augustss /* The reset bit goes low when the controller is done. */
1761 1.152 augustss for (n = 0; n < UHCI_RESET_TIMEOUT &&
1762 1.1 augustss (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++)
1763 1.92 augustss usb_delay_ms(&sc->sc_bus, 1);
1764 1.1 augustss if (n >= UHCI_RESET_TIMEOUT)
1765 1.152 augustss printf("%s: controller did not reset\n",
1766 1.216 drochner device_xname(sc->sc_dev));
1767 1.1 augustss }
1768 1.1 augustss
1769 1.16 augustss usbd_status
1770 1.249 drochner uhci_run(uhci_softc_t *sc, int run, int locked)
1771 1.1 augustss {
1772 1.248 mrg int n, running;
1773 1.264.4.1 skrll uint16_t cmd;
1774 1.1 augustss
1775 1.1 augustss run = run != 0;
1776 1.249 drochner if (!locked)
1777 1.249 drochner mutex_spin_enter(&sc->sc_intr_lock);
1778 1.30 augustss DPRINTF(("uhci_run: setting run=%d\n", run));
1779 1.71 augustss cmd = UREAD2(sc, UHCI_CMD);
1780 1.71 augustss if (run)
1781 1.71 augustss cmd |= UHCI_CMD_RS;
1782 1.71 augustss else
1783 1.71 augustss cmd &= ~UHCI_CMD_RS;
1784 1.71 augustss UHCICMD(sc, cmd);
1785 1.13 augustss for(n = 0; n < 10; n++) {
1786 1.1 augustss running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH);
1787 1.1 augustss /* return when we've entered the state we want */
1788 1.1 augustss if (run == running) {
1789 1.249 drochner if (!locked)
1790 1.249 drochner mutex_spin_exit(&sc->sc_intr_lock);
1791 1.30 augustss DPRINTF(("uhci_run: done cmd=0x%x sts=0x%x\n",
1792 1.30 augustss UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS)));
1793 1.16 augustss return (USBD_NORMAL_COMPLETION);
1794 1.1 augustss }
1795 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock);
1796 1.1 augustss }
1797 1.249 drochner if (!locked)
1798 1.249 drochner mutex_spin_exit(&sc->sc_intr_lock);
1799 1.216 drochner printf("%s: cannot %s\n", device_xname(sc->sc_dev),
1800 1.14 augustss run ? "start" : "stop");
1801 1.16 augustss return (USBD_IOERROR);
1802 1.1 augustss }
1803 1.1 augustss
1804 1.1 augustss /*
1805 1.1 augustss * Memory management routines.
1806 1.1 augustss * uhci_alloc_std allocates TDs
1807 1.1 augustss * uhci_alloc_sqh allocates QHs
1808 1.7 augustss * These two routines do their own free list management,
1809 1.1 augustss * partly for speed, partly because allocating DMAable memory
1810 1.1 augustss * has page size granularaity so much memory would be wasted if
1811 1.16 augustss * only one TD/QH (32 bytes) was placed in each allocated chunk.
1812 1.1 augustss */
1813 1.1 augustss
1814 1.1 augustss uhci_soft_td_t *
1815 1.119 augustss uhci_alloc_std(uhci_softc_t *sc)
1816 1.1 augustss {
1817 1.1 augustss uhci_soft_td_t *std;
1818 1.63 augustss usbd_status err;
1819 1.42 augustss int i, offs;
1820 1.7 augustss usb_dma_t dma;
1821 1.1 augustss
1822 1.63 augustss if (sc->sc_freetds == NULL) {
1823 1.1 augustss DPRINTFN(2,("uhci_alloc_std: allocating chunk\n"));
1824 1.63 augustss err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK,
1825 1.63 augustss UHCI_TD_ALIGN, &dma);
1826 1.63 augustss if (err)
1827 1.16 augustss return (0);
1828 1.248 mrg for (i = 0; i < UHCI_STD_CHUNK; i++) {
1829 1.42 augustss offs = i * UHCI_STD_SIZE;
1830 1.159 augustss std = KERNADDR(&dma, offs);
1831 1.160 augustss std->physaddr = DMAADDR(&dma, offs);
1832 1.223 bouyer std->dma = dma;
1833 1.223 bouyer std->offs = offs;
1834 1.42 augustss std->link.std = sc->sc_freetds;
1835 1.1 augustss sc->sc_freetds = std;
1836 1.1 augustss }
1837 1.1 augustss }
1838 1.1 augustss std = sc->sc_freetds;
1839 1.42 augustss sc->sc_freetds = std->link.std;
1840 1.42 augustss memset(&std->td, 0, sizeof(uhci_td_t));
1841 1.1 augustss return std;
1842 1.1 augustss }
1843 1.1 augustss
1844 1.1 augustss void
1845 1.119 augustss uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std)
1846 1.1 augustss {
1847 1.7 augustss #ifdef DIAGNOSTIC
1848 1.7 augustss #define TD_IS_FREE 0x12345678
1849 1.88 tsutsui if (le32toh(std->td.td_token) == TD_IS_FREE) {
1850 1.7 augustss printf("uhci_free_std: freeing free TD %p\n", std);
1851 1.7 augustss return;
1852 1.7 augustss }
1853 1.88 tsutsui std->td.td_token = htole32(TD_IS_FREE);
1854 1.7 augustss #endif
1855 1.42 augustss std->link.std = sc->sc_freetds;
1856 1.1 augustss sc->sc_freetds = std;
1857 1.1 augustss }
1858 1.1 augustss
1859 1.1 augustss uhci_soft_qh_t *
1860 1.119 augustss uhci_alloc_sqh(uhci_softc_t *sc)
1861 1.1 augustss {
1862 1.1 augustss uhci_soft_qh_t *sqh;
1863 1.63 augustss usbd_status err;
1864 1.1 augustss int i, offs;
1865 1.7 augustss usb_dma_t dma;
1866 1.1 augustss
1867 1.63 augustss if (sc->sc_freeqhs == NULL) {
1868 1.1 augustss DPRINTFN(2, ("uhci_alloc_sqh: allocating chunk\n"));
1869 1.63 augustss err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK,
1870 1.63 augustss UHCI_QH_ALIGN, &dma);
1871 1.63 augustss if (err)
1872 1.63 augustss return (0);
1873 1.43 augustss for(i = 0; i < UHCI_SQH_CHUNK; i++) {
1874 1.42 augustss offs = i * UHCI_SQH_SIZE;
1875 1.159 augustss sqh = KERNADDR(&dma, offs);
1876 1.160 augustss sqh->physaddr = DMAADDR(&dma, offs);
1877 1.223 bouyer sqh->dma = dma;
1878 1.223 bouyer sqh->offs = offs;
1879 1.42 augustss sqh->hlink = sc->sc_freeqhs;
1880 1.1 augustss sc->sc_freeqhs = sqh;
1881 1.1 augustss }
1882 1.1 augustss }
1883 1.1 augustss sqh = sc->sc_freeqhs;
1884 1.42 augustss sc->sc_freeqhs = sqh->hlink;
1885 1.42 augustss memset(&sqh->qh, 0, sizeof(uhci_qh_t));
1886 1.16 augustss return (sqh);
1887 1.1 augustss }
1888 1.1 augustss
1889 1.1 augustss void
1890 1.119 augustss uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1891 1.1 augustss {
1892 1.42 augustss sqh->hlink = sc->sc_freeqhs;
1893 1.1 augustss sc->sc_freeqhs = sqh;
1894 1.1 augustss }
1895 1.1 augustss
1896 1.1 augustss void
1897 1.119 augustss uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std,
1898 1.119 augustss uhci_soft_td_t *stdend)
1899 1.1 augustss {
1900 1.1 augustss uhci_soft_td_t *p;
1901 1.256 tsutsui uint32_t td_link;
1902 1.1 augustss
1903 1.223 bouyer /*
1904 1.223 bouyer * to avoid race condition with the controller which may be looking
1905 1.223 bouyer * at this chain, we need to first invalidate all links, and
1906 1.223 bouyer * then wait for the controller to move to another queue
1907 1.223 bouyer */
1908 1.223 bouyer for (p = std; p != stdend; p = p->link.std) {
1909 1.223 bouyer usb_syncmem(&p->dma,
1910 1.223 bouyer p->offs + offsetof(uhci_td_t, td_link),
1911 1.223 bouyer sizeof(p->td.td_link),
1912 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1913 1.256 tsutsui td_link = le32toh(p->td.td_link);
1914 1.256 tsutsui usb_syncmem(&p->dma,
1915 1.256 tsutsui p->offs + offsetof(uhci_td_t, td_link),
1916 1.256 tsutsui sizeof(p->td.td_link),
1917 1.256 tsutsui BUS_DMASYNC_PREREAD);
1918 1.256 tsutsui if ((td_link & UHCI_PTR_T) == 0) {
1919 1.255 tsutsui p->td.td_link = htole32(UHCI_PTR_T);
1920 1.223 bouyer usb_syncmem(&p->dma,
1921 1.223 bouyer p->offs + offsetof(uhci_td_t, td_link),
1922 1.223 bouyer sizeof(p->td.td_link),
1923 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1924 1.223 bouyer }
1925 1.223 bouyer }
1926 1.223 bouyer delay(UHCI_QH_REMOVE_DELAY);
1927 1.223 bouyer
1928 1.1 augustss for (; std != stdend; std = p) {
1929 1.42 augustss p = std->link.std;
1930 1.1 augustss uhci_free_std(sc, std);
1931 1.1 augustss }
1932 1.1 augustss }
1933 1.1 augustss
1934 1.1 augustss usbd_status
1935 1.119 augustss uhci_alloc_std_chain(struct uhci_pipe *upipe, uhci_softc_t *sc, int len,
1936 1.264.4.1 skrll int rd, uint16_t flags, usb_dma_t *dma,
1937 1.119 augustss uhci_soft_td_t **sp, uhci_soft_td_t **ep)
1938 1.1 augustss {
1939 1.1 augustss uhci_soft_td_t *p, *lastp;
1940 1.1 augustss uhci_physaddr_t lastlink;
1941 1.1 augustss int i, ntd, l, tog, maxp;
1942 1.264.4.1 skrll uint32_t status;
1943 1.1 augustss int addr = upipe->pipe.device->address;
1944 1.1 augustss int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress;
1945 1.1 augustss
1946 1.144 augustss DPRINTFN(8, ("uhci_alloc_std_chain: addr=%d endpt=%d len=%d speed=%d "
1947 1.152 augustss "flags=0x%x\n", addr, UE_GET_ADDR(endpt), len,
1948 1.144 augustss upipe->pipe.device->speed, flags));
1949 1.248 mrg
1950 1.257 skrll KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock));
1951 1.248 mrg
1952 1.4 augustss maxp = UGETW(upipe->pipe.endpoint->edesc->wMaxPacketSize);
1953 1.1 augustss if (maxp == 0) {
1954 1.1 augustss printf("uhci_alloc_std_chain: maxp=0\n");
1955 1.1 augustss return (USBD_INVAL);
1956 1.1 augustss }
1957 1.1 augustss ntd = (len + maxp - 1) / maxp;
1958 1.73 augustss if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0)
1959 1.73 augustss ntd++;
1960 1.39 augustss DPRINTFN(10, ("uhci_alloc_std_chain: maxp=%d ntd=%d\n", maxp, ntd));
1961 1.73 augustss if (ntd == 0) {
1962 1.73 augustss *sp = *ep = 0;
1963 1.73 augustss DPRINTFN(-1,("uhci_alloc_std_chain: ntd=0\n"));
1964 1.73 augustss return (USBD_NORMAL_COMPLETION);
1965 1.73 augustss }
1966 1.38 augustss tog = upipe->nexttoggle;
1967 1.1 augustss if (ntd % 2 == 0)
1968 1.1 augustss tog ^= 1;
1969 1.32 augustss upipe->nexttoggle = tog ^ 1;
1970 1.121 augustss lastp = NULL;
1971 1.1 augustss lastlink = UHCI_PTR_T;
1972 1.1 augustss ntd--;
1973 1.33 augustss status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE);
1974 1.144 augustss if (upipe->pipe.device->speed == USB_SPEED_LOW)
1975 1.18 augustss status |= UHCI_TD_LS;
1976 1.73 augustss if (flags & USBD_SHORT_XFER_OK)
1977 1.18 augustss status |= UHCI_TD_SPD;
1978 1.223 bouyer usb_syncmem(dma, 0, len,
1979 1.223 bouyer rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
1980 1.1 augustss for (i = ntd; i >= 0; i--) {
1981 1.1 augustss p = uhci_alloc_std(sc);
1982 1.63 augustss if (p == NULL) {
1983 1.202 christos KASSERT(lastp != NULL);
1984 1.149 augustss uhci_free_std_chain(sc, lastp, NULL);
1985 1.1 augustss return (USBD_NOMEM);
1986 1.1 augustss }
1987 1.42 augustss p->link.std = lastp;
1988 1.121 augustss p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD);
1989 1.1 augustss lastp = p;
1990 1.1 augustss lastlink = p->physaddr;
1991 1.88 tsutsui p->td.td_status = htole32(status);
1992 1.1 augustss if (i == ntd) {
1993 1.1 augustss /* last TD */
1994 1.1 augustss l = len % maxp;
1995 1.73 augustss if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER))
1996 1.73 augustss l = maxp;
1997 1.1 augustss *ep = p;
1998 1.1 augustss } else
1999 1.1 augustss l = maxp;
2000 1.152 augustss p->td.td_token =
2001 1.88 tsutsui htole32(rd ? UHCI_TD_IN (l, endpt, addr, tog) :
2002 1.88 tsutsui UHCI_TD_OUT(l, endpt, addr, tog));
2003 1.160 augustss p->td.td_buffer = htole32(DMAADDR(dma, i * maxp));
2004 1.223 bouyer usb_syncmem(&p->dma, p->offs, sizeof(p->td),
2005 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2006 1.1 augustss tog ^= 1;
2007 1.1 augustss }
2008 1.1 augustss *sp = lastp;
2009 1.152 augustss DPRINTFN(10, ("uhci_alloc_std_chain: nexttog=%d\n",
2010 1.38 augustss upipe->nexttoggle));
2011 1.1 augustss return (USBD_NORMAL_COMPLETION);
2012 1.1 augustss }
2013 1.1 augustss
2014 1.38 augustss void
2015 1.119 augustss uhci_device_clear_toggle(usbd_pipe_handle pipe)
2016 1.38 augustss {
2017 1.38 augustss struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;
2018 1.38 augustss upipe->nexttoggle = 0;
2019 1.38 augustss }
2020 1.38 augustss
2021 1.38 augustss void
2022 1.205 christos uhci_noop(usbd_pipe_handle pipe)
2023 1.38 augustss {
2024 1.38 augustss }
2025 1.38 augustss
2026 1.1 augustss usbd_status
2027 1.119 augustss uhci_device_bulk_transfer(usbd_xfer_handle xfer)
2028 1.1 augustss {
2029 1.248 mrg uhci_softc_t *sc = xfer->pipe->device->bus->hci_private;
2030 1.63 augustss usbd_status err;
2031 1.16 augustss
2032 1.52 augustss /* Insert last in queue. */
2033 1.248 mrg mutex_enter(&sc->sc_lock);
2034 1.63 augustss err = usb_insert_transfer(xfer);
2035 1.248 mrg mutex_exit(&sc->sc_lock);
2036 1.63 augustss if (err)
2037 1.63 augustss return (err);
2038 1.52 augustss
2039 1.152 augustss /*
2040 1.92 augustss * Pipe isn't running (otherwise err would be USBD_INPROG),
2041 1.92 augustss * so start it first.
2042 1.67 augustss */
2043 1.63 augustss return (uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
2044 1.16 augustss }
2045 1.16 augustss
2046 1.16 augustss usbd_status
2047 1.119 augustss uhci_device_bulk_start(usbd_xfer_handle xfer)
2048 1.16 augustss {
2049 1.63 augustss struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe;
2050 1.1 augustss usbd_device_handle dev = upipe->pipe.device;
2051 1.216 drochner uhci_softc_t *sc = dev->bus->hci_private;
2052 1.92 augustss uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
2053 1.55 augustss uhci_soft_td_t *data, *dataend;
2054 1.1 augustss uhci_soft_qh_t *sqh;
2055 1.63 augustss usbd_status err;
2056 1.45 augustss int len, isread, endpt;
2057 1.1 augustss
2058 1.169 augustss DPRINTFN(3, ("uhci_device_bulk_start: xfer=%p len=%d flags=%d ii=%p\n",
2059 1.169 augustss xfer, xfer->length, xfer->flags, ii));
2060 1.1 augustss
2061 1.82 augustss if (sc->sc_dying)
2062 1.82 augustss return (USBD_IOERROR);
2063 1.82 augustss
2064 1.48 augustss #ifdef DIAGNOSTIC
2065 1.63 augustss if (xfer->rqflags & URQ_REQUEST)
2066 1.163 provos panic("uhci_device_bulk_transfer: a request");
2067 1.48 augustss #endif
2068 1.1 augustss
2069 1.248 mrg mutex_enter(&sc->sc_lock);
2070 1.248 mrg
2071 1.63 augustss len = xfer->length;
2072 1.102 augustss endpt = upipe->pipe.endpoint->edesc->bEndpointAddress;
2073 1.45 augustss isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2074 1.1 augustss sqh = upipe->u.bulk.sqh;
2075 1.1 augustss
2076 1.1 augustss upipe->u.bulk.isread = isread;
2077 1.1 augustss upipe->u.bulk.length = len;
2078 1.1 augustss
2079 1.73 augustss err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->flags,
2080 1.73 augustss &xfer->dmabuf, &data, &dataend);
2081 1.248 mrg if (err) {
2082 1.248 mrg mutex_exit(&sc->sc_lock);
2083 1.63 augustss return (err);
2084 1.248 mrg }
2085 1.88 tsutsui dataend->td.td_status |= htole32(UHCI_TD_IOC);
2086 1.223 bouyer usb_syncmem(&dataend->dma,
2087 1.223 bouyer dataend->offs + offsetof(uhci_td_t, td_status),
2088 1.223 bouyer sizeof(dataend->td.td_status),
2089 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2090 1.223 bouyer
2091 1.1 augustss
2092 1.59 augustss #ifdef UHCI_DEBUG
2093 1.33 augustss if (uhcidebug > 8) {
2094 1.55 augustss DPRINTF(("uhci_device_bulk_transfer: data(1)\n"));
2095 1.55 augustss uhci_dump_tds(data);
2096 1.1 augustss }
2097 1.1 augustss #endif
2098 1.1 augustss
2099 1.1 augustss /* Set up interrupt info. */
2100 1.63 augustss ii->xfer = xfer;
2101 1.55 augustss ii->stdstart = data;
2102 1.55 augustss ii->stdend = dataend;
2103 1.7 augustss #ifdef DIAGNOSTIC
2104 1.70 augustss if (!ii->isdone) {
2105 1.70 augustss printf("uhci_device_bulk_transfer: not done, ii=%p\n", ii);
2106 1.70 augustss }
2107 1.7 augustss ii->isdone = 0;
2108 1.7 augustss #endif
2109 1.1 augustss
2110 1.55 augustss sqh->elink = data;
2111 1.121 augustss sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD);
2112 1.223 bouyer /* uhci_add_bulk() will do usb_syncmem(sqh) */
2113 1.1 augustss
2114 1.1 augustss uhci_add_bulk(sc, sqh);
2115 1.92 augustss uhci_add_intr_info(sc, ii);
2116 1.1 augustss
2117 1.63 augustss if (xfer->timeout && !sc->sc_bus.use_polling) {
2118 1.234 dyoung callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout),
2119 1.91 augustss uhci_timeout, ii);
2120 1.13 augustss }
2121 1.92 augustss xfer->status = USBD_IN_PROGRESS;
2122 1.1 augustss
2123 1.59 augustss #ifdef UHCI_DEBUG
2124 1.1 augustss if (uhcidebug > 10) {
2125 1.55 augustss DPRINTF(("uhci_device_bulk_transfer: data(2)\n"));
2126 1.55 augustss uhci_dump_tds(data);
2127 1.1 augustss }
2128 1.1 augustss #endif
2129 1.1 augustss
2130 1.26 augustss if (sc->sc_bus.use_polling)
2131 1.63 augustss uhci_waitintr(sc, xfer);
2132 1.26 augustss
2133 1.248 mrg mutex_exit(&sc->sc_lock);
2134 1.1 augustss return (USBD_IN_PROGRESS);
2135 1.1 augustss }
2136 1.1 augustss
2137 1.1 augustss /* Abort a device bulk request. */
2138 1.1 augustss void
2139 1.119 augustss uhci_device_bulk_abort(usbd_xfer_handle xfer)
2140 1.1 augustss {
2141 1.248 mrg #ifdef DIAGNOSTIC
2142 1.248 mrg uhci_softc_t *sc = xfer->pipe->device->bus->hci_private;
2143 1.248 mrg #endif
2144 1.248 mrg
2145 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2146 1.248 mrg
2147 1.33 augustss DPRINTF(("uhci_device_bulk_abort:\n"));
2148 1.66 augustss uhci_abort_xfer(xfer, USBD_CANCELLED);
2149 1.33 augustss }
2150 1.33 augustss
2151 1.92 augustss /*
2152 1.154 augustss * Abort a device request.
2153 1.154 augustss * If this routine is called at splusb() it guarantees that the request
2154 1.154 augustss * will be removed from the hardware scheduling and that the callback
2155 1.154 augustss * for it will be called with USBD_CANCELLED status.
2156 1.154 augustss * It's impossible to guarantee that the requested transfer will not
2157 1.154 augustss * have happened since the hardware runs concurrently.
2158 1.154 augustss * If the transaction has already happened we rely on the ordinary
2159 1.154 augustss * interrupt processing to process it.
2160 1.248 mrg * XXX This is most probably wrong.
2161 1.248 mrg * XXXMRG this doesn't make sense anymore.
2162 1.92 augustss */
2163 1.33 augustss void
2164 1.119 augustss uhci_abort_xfer(usbd_xfer_handle xfer, usbd_status status)
2165 1.33 augustss {
2166 1.92 augustss uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
2167 1.153 augustss struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe;
2168 1.216 drochner uhci_softc_t *sc = upipe->pipe.device->bus->hci_private;
2169 1.33 augustss uhci_soft_td_t *std;
2170 1.188 augustss int wake;
2171 1.65 augustss
2172 1.106 augustss DPRINTFN(1,("uhci_abort_xfer: xfer=%p, status=%d\n", xfer, status));
2173 1.33 augustss
2174 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2175 1.264.4.3 skrll ASSERT_SLEEPABLE();
2176 1.248 mrg
2177 1.153 augustss if (sc->sc_dying) {
2178 1.153 augustss /* If we're dying, just do the software part. */
2179 1.153 augustss xfer->status = status; /* make software ignore it */
2180 1.234 dyoung callout_stop(&xfer->timeout_handle);
2181 1.153 augustss usb_transfer_complete(xfer);
2182 1.194 christos return;
2183 1.92 augustss }
2184 1.92 augustss
2185 1.153 augustss /*
2186 1.188 augustss * If an abort is already in progress then just wait for it to
2187 1.188 augustss * complete and return.
2188 1.188 augustss */
2189 1.188 augustss if (xfer->hcflags & UXFER_ABORTING) {
2190 1.188 augustss DPRINTFN(2, ("uhci_abort_xfer: already aborting\n"));
2191 1.188 augustss #ifdef DIAGNOSTIC
2192 1.188 augustss if (status == USBD_TIMEOUT)
2193 1.188 augustss printf("uhci_abort_xfer: TIMEOUT while aborting\n");
2194 1.188 augustss #endif
2195 1.188 augustss /* Override the status which might be USBD_TIMEOUT. */
2196 1.188 augustss xfer->status = status;
2197 1.188 augustss DPRINTFN(2, ("uhci_abort_xfer: waiting for abort to finish\n"));
2198 1.188 augustss xfer->hcflags |= UXFER_ABORTWAIT;
2199 1.188 augustss while (xfer->hcflags & UXFER_ABORTING)
2200 1.248 mrg cv_wait(&xfer->hccv, &sc->sc_lock);
2201 1.248 mrg goto done;
2202 1.188 augustss }
2203 1.188 augustss xfer->hcflags |= UXFER_ABORTING;
2204 1.188 augustss
2205 1.188 augustss /*
2206 1.153 augustss * Step 1: Make interrupt routine and hardware ignore xfer.
2207 1.153 augustss */
2208 1.153 augustss xfer->status = status; /* make software ignore it */
2209 1.234 dyoung callout_stop(&xfer->timeout_handle);
2210 1.153 augustss DPRINTFN(1,("uhci_abort_xfer: stop ii=%p\n", ii));
2211 1.223 bouyer for (std = ii->stdstart; std != NULL; std = std->link.std) {
2212 1.223 bouyer usb_syncmem(&std->dma,
2213 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
2214 1.223 bouyer sizeof(std->td.td_status),
2215 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2216 1.92 augustss std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC));
2217 1.223 bouyer usb_syncmem(&std->dma,
2218 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
2219 1.223 bouyer sizeof(std->td.td_status),
2220 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2221 1.223 bouyer }
2222 1.92 augustss
2223 1.162 augustss /*
2224 1.153 augustss * Step 2: Wait until we know hardware has finished any possible
2225 1.153 augustss * use of the xfer. Also make sure the soft interrupt routine
2226 1.153 augustss * has run.
2227 1.153 augustss */
2228 1.248 mrg /* Hardware finishes in 1ms */
2229 1.248 mrg usb_delay_ms_locked(upipe->pipe.device->bus, 2, &sc->sc_lock);
2230 1.153 augustss sc->sc_softwake = 1;
2231 1.153 augustss usb_schedsoftintr(&sc->sc_bus);
2232 1.248 mrg DPRINTFN(1,("uhci_abort_xfer: cv_wait\n"));
2233 1.248 mrg cv_wait(&sc->sc_softwake_cv, &sc->sc_lock);
2234 1.162 augustss
2235 1.153 augustss /*
2236 1.153 augustss * Step 3: Execute callback.
2237 1.153 augustss */
2238 1.154 augustss DPRINTFN(1,("uhci_abort_xfer: callback\n"));
2239 1.100 augustss #ifdef DIAGNOSTIC
2240 1.106 augustss ii->isdone = 1;
2241 1.100 augustss #endif
2242 1.188 augustss wake = xfer->hcflags & UXFER_ABORTWAIT;
2243 1.188 augustss xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT);
2244 1.106 augustss usb_transfer_complete(xfer);
2245 1.188 augustss if (wake)
2246 1.248 mrg cv_broadcast(&xfer->hccv);
2247 1.248 mrg done:
2248 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2249 1.1 augustss }
2250 1.1 augustss
2251 1.1 augustss /* Close a device bulk pipe. */
2252 1.1 augustss void
2253 1.119 augustss uhci_device_bulk_close(usbd_pipe_handle pipe)
2254 1.1 augustss {
2255 1.1 augustss struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;
2256 1.1 augustss usbd_device_handle dev = upipe->pipe.device;
2257 1.216 drochner uhci_softc_t *sc = dev->bus->hci_private;
2258 1.1 augustss
2259 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2260 1.248 mrg
2261 1.1 augustss uhci_free_sqh(sc, upipe->u.bulk.sqh);
2262 1.236 drochner
2263 1.236 drochner pipe->endpoint->datatoggle = upipe->nexttoggle;
2264 1.1 augustss }
2265 1.1 augustss
2266 1.1 augustss usbd_status
2267 1.119 augustss uhci_device_ctrl_transfer(usbd_xfer_handle xfer)
2268 1.1 augustss {
2269 1.248 mrg uhci_softc_t *sc = xfer->pipe->device->bus->hci_private;
2270 1.63 augustss usbd_status err;
2271 1.16 augustss
2272 1.52 augustss /* Insert last in queue. */
2273 1.248 mrg mutex_enter(&sc->sc_lock);
2274 1.63 augustss err = usb_insert_transfer(xfer);
2275 1.248 mrg mutex_exit(&sc->sc_lock);
2276 1.63 augustss if (err)
2277 1.63 augustss return (err);
2278 1.52 augustss
2279 1.152 augustss /*
2280 1.92 augustss * Pipe isn't running (otherwise err would be USBD_INPROG),
2281 1.92 augustss * so start it first.
2282 1.67 augustss */
2283 1.63 augustss return (uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
2284 1.16 augustss }
2285 1.16 augustss
2286 1.16 augustss usbd_status
2287 1.119 augustss uhci_device_ctrl_start(usbd_xfer_handle xfer)
2288 1.16 augustss {
2289 1.216 drochner uhci_softc_t *sc = xfer->pipe->device->bus->hci_private;
2290 1.63 augustss usbd_status err;
2291 1.1 augustss
2292 1.82 augustss if (sc->sc_dying)
2293 1.82 augustss return (USBD_IOERROR);
2294 1.82 augustss
2295 1.48 augustss #ifdef DIAGNOSTIC
2296 1.63 augustss if (!(xfer->rqflags & URQ_REQUEST))
2297 1.163 provos panic("uhci_device_ctrl_transfer: not a request");
2298 1.48 augustss #endif
2299 1.1 augustss
2300 1.248 mrg mutex_enter(&sc->sc_lock);
2301 1.63 augustss err = uhci_device_request(xfer);
2302 1.248 mrg mutex_exit(&sc->sc_lock);
2303 1.63 augustss if (err)
2304 1.63 augustss return (err);
2305 1.1 augustss
2306 1.9 augustss if (sc->sc_bus.use_polling)
2307 1.63 augustss uhci_waitintr(sc, xfer);
2308 1.1 augustss return (USBD_IN_PROGRESS);
2309 1.1 augustss }
2310 1.1 augustss
2311 1.1 augustss usbd_status
2312 1.119 augustss uhci_device_intr_transfer(usbd_xfer_handle xfer)
2313 1.1 augustss {
2314 1.248 mrg uhci_softc_t *sc = xfer->pipe->device->bus->hci_private;
2315 1.63 augustss usbd_status err;
2316 1.16 augustss
2317 1.52 augustss /* Insert last in queue. */
2318 1.248 mrg mutex_enter(&sc->sc_lock);
2319 1.63 augustss err = usb_insert_transfer(xfer);
2320 1.248 mrg mutex_exit(&sc->sc_lock);
2321 1.63 augustss if (err)
2322 1.63 augustss return (err);
2323 1.52 augustss
2324 1.152 augustss /*
2325 1.92 augustss * Pipe isn't running (otherwise err would be USBD_INPROG),
2326 1.92 augustss * so start it first.
2327 1.67 augustss */
2328 1.63 augustss return (uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
2329 1.16 augustss }
2330 1.16 augustss
2331 1.16 augustss usbd_status
2332 1.119 augustss uhci_device_intr_start(usbd_xfer_handle xfer)
2333 1.16 augustss {
2334 1.63 augustss struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe;
2335 1.1 augustss usbd_device_handle dev = upipe->pipe.device;
2336 1.216 drochner uhci_softc_t *sc = dev->bus->hci_private;
2337 1.92 augustss uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
2338 1.55 augustss uhci_soft_td_t *data, *dataend;
2339 1.1 augustss uhci_soft_qh_t *sqh;
2340 1.63 augustss usbd_status err;
2341 1.187 skrll int isread, endpt;
2342 1.248 mrg int i;
2343 1.1 augustss
2344 1.82 augustss if (sc->sc_dying)
2345 1.82 augustss return (USBD_IOERROR);
2346 1.82 augustss
2347 1.63 augustss DPRINTFN(3,("uhci_device_intr_transfer: xfer=%p len=%d flags=%d\n",
2348 1.63 augustss xfer, xfer->length, xfer->flags));
2349 1.1 augustss
2350 1.48 augustss #ifdef DIAGNOSTIC
2351 1.63 augustss if (xfer->rqflags & URQ_REQUEST)
2352 1.163 provos panic("uhci_device_intr_transfer: a request");
2353 1.48 augustss #endif
2354 1.1 augustss
2355 1.248 mrg mutex_enter(&sc->sc_lock);
2356 1.248 mrg
2357 1.187 skrll endpt = upipe->pipe.endpoint->edesc->bEndpointAddress;
2358 1.187 skrll isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2359 1.187 skrll
2360 1.187 skrll upipe->u.intr.isread = isread;
2361 1.187 skrll
2362 1.187 skrll err = uhci_alloc_std_chain(upipe, sc, xfer->length, isread,
2363 1.187 skrll xfer->flags, &xfer->dmabuf, &data,
2364 1.187 skrll &dataend);
2365 1.248 mrg if (err) {
2366 1.248 mrg mutex_exit(&sc->sc_lock);
2367 1.63 augustss return (err);
2368 1.248 mrg }
2369 1.248 mrg
2370 1.88 tsutsui dataend->td.td_status |= htole32(UHCI_TD_IOC);
2371 1.223 bouyer usb_syncmem(&dataend->dma,
2372 1.223 bouyer dataend->offs + offsetof(uhci_td_t, td_status),
2373 1.223 bouyer sizeof(dataend->td.td_status),
2374 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2375 1.1 augustss
2376 1.59 augustss #ifdef UHCI_DEBUG
2377 1.1 augustss if (uhcidebug > 10) {
2378 1.55 augustss DPRINTF(("uhci_device_intr_transfer: data(1)\n"));
2379 1.55 augustss uhci_dump_tds(data);
2380 1.1 augustss uhci_dump_qh(upipe->u.intr.qhs[0]);
2381 1.1 augustss }
2382 1.1 augustss #endif
2383 1.1 augustss
2384 1.1 augustss /* Set up interrupt info. */
2385 1.63 augustss ii->xfer = xfer;
2386 1.55 augustss ii->stdstart = data;
2387 1.55 augustss ii->stdend = dataend;
2388 1.7 augustss #ifdef DIAGNOSTIC
2389 1.70 augustss if (!ii->isdone) {
2390 1.70 augustss printf("uhci_device_intr_transfer: not done, ii=%p\n", ii);
2391 1.70 augustss }
2392 1.7 augustss ii->isdone = 0;
2393 1.7 augustss #endif
2394 1.1 augustss
2395 1.152 augustss DPRINTFN(10,("uhci_device_intr_transfer: qhs[0]=%p\n",
2396 1.12 augustss upipe->u.intr.qhs[0]));
2397 1.1 augustss for (i = 0; i < upipe->u.intr.npoll; i++) {
2398 1.1 augustss sqh = upipe->u.intr.qhs[i];
2399 1.55 augustss sqh->elink = data;
2400 1.121 augustss sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD);
2401 1.223 bouyer usb_syncmem(&sqh->dma,
2402 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
2403 1.223 bouyer sizeof(sqh->qh.qh_elink),
2404 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2405 1.1 augustss }
2406 1.92 augustss uhci_add_intr_info(sc, ii);
2407 1.92 augustss xfer->status = USBD_IN_PROGRESS;
2408 1.248 mrg mutex_exit(&sc->sc_lock);
2409 1.1 augustss
2410 1.59 augustss #ifdef UHCI_DEBUG
2411 1.1 augustss if (uhcidebug > 10) {
2412 1.55 augustss DPRINTF(("uhci_device_intr_transfer: data(2)\n"));
2413 1.55 augustss uhci_dump_tds(data);
2414 1.1 augustss uhci_dump_qh(upipe->u.intr.qhs[0]);
2415 1.1 augustss }
2416 1.1 augustss #endif
2417 1.1 augustss
2418 1.1 augustss return (USBD_IN_PROGRESS);
2419 1.1 augustss }
2420 1.1 augustss
2421 1.1 augustss /* Abort a device control request. */
2422 1.1 augustss void
2423 1.119 augustss uhci_device_ctrl_abort(usbd_xfer_handle xfer)
2424 1.1 augustss {
2425 1.248 mrg #ifdef DIAGNOSTIC
2426 1.248 mrg uhci_softc_t *sc = xfer->pipe->device->bus->hci_private;
2427 1.248 mrg #endif
2428 1.248 mrg
2429 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2430 1.248 mrg
2431 1.33 augustss DPRINTF(("uhci_device_ctrl_abort:\n"));
2432 1.66 augustss uhci_abort_xfer(xfer, USBD_CANCELLED);
2433 1.1 augustss }
2434 1.1 augustss
2435 1.1 augustss /* Close a device control pipe. */
2436 1.1 augustss void
2437 1.205 christos uhci_device_ctrl_close(usbd_pipe_handle pipe)
2438 1.1 augustss {
2439 1.1 augustss }
2440 1.1 augustss
2441 1.1 augustss /* Abort a device interrupt request. */
2442 1.1 augustss void
2443 1.119 augustss uhci_device_intr_abort(usbd_xfer_handle xfer)
2444 1.1 augustss {
2445 1.248 mrg #ifdef DIAGNOSTIC
2446 1.248 mrg uhci_softc_t *sc = xfer->pipe->device->bus->hci_private;
2447 1.248 mrg #endif
2448 1.248 mrg
2449 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2450 1.264 skrll KASSERT(xfer->pipe->intrxfer == xfer);
2451 1.248 mrg
2452 1.63 augustss DPRINTFN(1,("uhci_device_intr_abort: xfer=%p\n", xfer));
2453 1.264 skrll
2454 1.66 augustss uhci_abort_xfer(xfer, USBD_CANCELLED);
2455 1.1 augustss }
2456 1.1 augustss
2457 1.1 augustss /* Close a device interrupt pipe. */
2458 1.1 augustss void
2459 1.119 augustss uhci_device_intr_close(usbd_pipe_handle pipe)
2460 1.1 augustss {
2461 1.1 augustss struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;
2462 1.216 drochner uhci_softc_t *sc = pipe->device->bus->hci_private;
2463 1.92 augustss int i, npoll;
2464 1.248 mrg
2465 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2466 1.1 augustss
2467 1.1 augustss /* Unlink descriptors from controller data structures. */
2468 1.1 augustss npoll = upipe->u.intr.npoll;
2469 1.1 augustss for (i = 0; i < npoll; i++)
2470 1.92 augustss uhci_remove_intr(sc, upipe->u.intr.qhs[i]);
2471 1.1 augustss
2472 1.152 augustss /*
2473 1.1 augustss * We now have to wait for any activity on the physical
2474 1.1 augustss * descriptors to stop.
2475 1.1 augustss */
2476 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock);
2477 1.1 augustss
2478 1.1 augustss for(i = 0; i < npoll; i++)
2479 1.1 augustss uhci_free_sqh(sc, upipe->u.intr.qhs[i]);
2480 1.248 mrg kmem_free(upipe->u.intr.qhs, npoll * sizeof(uhci_soft_qh_t *));
2481 1.1 augustss
2482 1.1 augustss /* XXX free other resources */
2483 1.1 augustss }
2484 1.1 augustss
2485 1.1 augustss usbd_status
2486 1.119 augustss uhci_device_request(usbd_xfer_handle xfer)
2487 1.1 augustss {
2488 1.63 augustss struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe;
2489 1.63 augustss usb_device_request_t *req = &xfer->request;
2490 1.1 augustss usbd_device_handle dev = upipe->pipe.device;
2491 1.216 drochner uhci_softc_t *sc = dev->bus->hci_private;
2492 1.1 augustss int addr = dev->address;
2493 1.1 augustss int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress;
2494 1.92 augustss uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
2495 1.55 augustss uhci_soft_td_t *setup, *data, *stat, *next, *dataend;
2496 1.1 augustss uhci_soft_qh_t *sqh;
2497 1.1 augustss int len;
2498 1.264.4.1 skrll uint32_t ls;
2499 1.63 augustss usbd_status err;
2500 1.1 augustss int isread;
2501 1.248 mrg
2502 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2503 1.1 augustss
2504 1.13 augustss DPRINTFN(3,("uhci_device_control type=0x%02x, request=0x%02x, "
2505 1.12 augustss "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n",
2506 1.1 augustss req->bmRequestType, req->bRequest, UGETW(req->wValue),
2507 1.1 augustss UGETW(req->wIndex), UGETW(req->wLength),
2508 1.1 augustss addr, endpt));
2509 1.1 augustss
2510 1.144 augustss ls = dev->speed == USB_SPEED_LOW ? UHCI_TD_LS : 0;
2511 1.1 augustss isread = req->bmRequestType & UT_READ;
2512 1.1 augustss len = UGETW(req->wLength);
2513 1.1 augustss
2514 1.1 augustss setup = upipe->u.ctl.setup;
2515 1.1 augustss stat = upipe->u.ctl.stat;
2516 1.1 augustss sqh = upipe->u.ctl.sqh;
2517 1.1 augustss
2518 1.1 augustss /* Set up data transaction */
2519 1.1 augustss if (len != 0) {
2520 1.38 augustss upipe->nexttoggle = 1;
2521 1.73 augustss err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->flags,
2522 1.73 augustss &xfer->dmabuf, &data, &dataend);
2523 1.63 augustss if (err)
2524 1.63 augustss return (err);
2525 1.55 augustss next = data;
2526 1.55 augustss dataend->link.std = stat;
2527 1.258 skrll dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD);
2528 1.223 bouyer usb_syncmem(&dataend->dma,
2529 1.223 bouyer dataend->offs + offsetof(uhci_td_t, td_link),
2530 1.223 bouyer sizeof(dataend->td.td_link),
2531 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2532 1.1 augustss } else {
2533 1.1 augustss next = stat;
2534 1.1 augustss }
2535 1.1 augustss upipe->u.ctl.length = len;
2536 1.1 augustss
2537 1.159 augustss memcpy(KERNADDR(&upipe->u.ctl.reqdma, 0), req, sizeof *req);
2538 1.223 bouyer usb_syncmem(&upipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE);
2539 1.1 augustss
2540 1.42 augustss setup->link.std = next;
2541 1.258 skrll setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD);
2542 1.88 tsutsui setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls |
2543 1.88 tsutsui UHCI_TD_ACTIVE);
2544 1.88 tsutsui setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof *req, endpt, addr));
2545 1.160 augustss setup->td.td_buffer = htole32(DMAADDR(&upipe->u.ctl.reqdma, 0));
2546 1.223 bouyer usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td),
2547 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2548 1.42 augustss
2549 1.92 augustss stat->link.std = NULL;
2550 1.88 tsutsui stat->td.td_link = htole32(UHCI_PTR_T);
2551 1.152 augustss stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls |
2552 1.39 augustss UHCI_TD_ACTIVE | UHCI_TD_IOC);
2553 1.152 augustss stat->td.td_token =
2554 1.88 tsutsui htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) :
2555 1.264.4.2 skrll UHCI_TD_IN (0, endpt, addr, 1));
2556 1.88 tsutsui stat->td.td_buffer = htole32(0);
2557 1.223 bouyer usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td),
2558 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2559 1.1 augustss
2560 1.59 augustss #ifdef UHCI_DEBUG
2561 1.67 augustss if (uhcidebug > 10) {
2562 1.47 augustss DPRINTF(("uhci_device_request: before transfer\n"));
2563 1.41 augustss uhci_dump_tds(setup);
2564 1.1 augustss }
2565 1.1 augustss #endif
2566 1.1 augustss
2567 1.1 augustss /* Set up interrupt info. */
2568 1.63 augustss ii->xfer = xfer;
2569 1.1 augustss ii->stdstart = setup;
2570 1.1 augustss ii->stdend = stat;
2571 1.7 augustss #ifdef DIAGNOSTIC
2572 1.70 augustss if (!ii->isdone) {
2573 1.70 augustss printf("uhci_device_request: not done, ii=%p\n", ii);
2574 1.70 augustss }
2575 1.7 augustss ii->isdone = 0;
2576 1.7 augustss #endif
2577 1.1 augustss
2578 1.42 augustss sqh->elink = setup;
2579 1.121 augustss sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD);
2580 1.223 bouyer /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */
2581 1.1 augustss
2582 1.144 augustss if (dev->speed == USB_SPEED_LOW)
2583 1.123 augustss uhci_add_ls_ctrl(sc, sqh);
2584 1.123 augustss else
2585 1.123 augustss uhci_add_hs_ctrl(sc, sqh);
2586 1.92 augustss uhci_add_intr_info(sc, ii);
2587 1.59 augustss #ifdef UHCI_DEBUG
2588 1.1 augustss if (uhcidebug > 12) {
2589 1.1 augustss uhci_soft_td_t *std;
2590 1.1 augustss uhci_soft_qh_t *xqh;
2591 1.13 augustss uhci_soft_qh_t *sxqh;
2592 1.13 augustss int maxqh = 0;
2593 1.1 augustss uhci_physaddr_t link;
2594 1.47 augustss DPRINTF(("uhci_enter_ctl_q: follow from [0]\n"));
2595 1.1 augustss for (std = sc->sc_vframes[0].htd, link = 0;
2596 1.121 augustss (link & UHCI_PTR_QH) == 0;
2597 1.42 augustss std = std->link.std) {
2598 1.88 tsutsui link = le32toh(std->td.td_link);
2599 1.1 augustss uhci_dump_td(std);
2600 1.1 augustss }
2601 1.67 augustss sxqh = (uhci_soft_qh_t *)std;
2602 1.67 augustss uhci_dump_qh(sxqh);
2603 1.67 augustss for (xqh = sxqh;
2604 1.63 augustss xqh != NULL;
2605 1.152 augustss xqh = (maxqh++ == 5 || xqh->hlink == sxqh ||
2606 1.264.4.2 skrll xqh->hlink == xqh ? NULL : xqh->hlink)) {
2607 1.1 augustss uhci_dump_qh(xqh);
2608 1.13 augustss }
2609 1.47 augustss DPRINTF(("Enqueued QH:\n"));
2610 1.1 augustss uhci_dump_qh(sqh);
2611 1.42 augustss uhci_dump_tds(sqh->elink);
2612 1.1 augustss }
2613 1.1 augustss #endif
2614 1.63 augustss if (xfer->timeout && !sc->sc_bus.use_polling) {
2615 1.234 dyoung callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout),
2616 1.91 augustss uhci_timeout, ii);
2617 1.13 augustss }
2618 1.92 augustss xfer->status = USBD_IN_PROGRESS;
2619 1.1 augustss
2620 1.1 augustss return (USBD_NORMAL_COMPLETION);
2621 1.1 augustss }
2622 1.1 augustss
2623 1.16 augustss usbd_status
2624 1.119 augustss uhci_device_isoc_transfer(usbd_xfer_handle xfer)
2625 1.16 augustss {
2626 1.248 mrg uhci_softc_t *sc = xfer->pipe->device->bus->hci_private;
2627 1.63 augustss usbd_status err;
2628 1.48 augustss
2629 1.63 augustss DPRINTFN(5,("uhci_device_isoc_transfer: xfer=%p\n", xfer));
2630 1.48 augustss
2631 1.48 augustss /* Put it on our queue, */
2632 1.248 mrg mutex_enter(&sc->sc_lock);
2633 1.63 augustss err = usb_insert_transfer(xfer);
2634 1.248 mrg mutex_exit(&sc->sc_lock);
2635 1.48 augustss
2636 1.48 augustss /* bail out on error, */
2637 1.63 augustss if (err && err != USBD_IN_PROGRESS)
2638 1.63 augustss return (err);
2639 1.48 augustss
2640 1.48 augustss /* XXX should check inuse here */
2641 1.48 augustss
2642 1.48 augustss /* insert into schedule, */
2643 1.63 augustss uhci_device_isoc_enter(xfer);
2644 1.48 augustss
2645 1.102 augustss /* and start if the pipe wasn't running */
2646 1.67 augustss if (!err)
2647 1.63 augustss uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue));
2648 1.48 augustss
2649 1.63 augustss return (err);
2650 1.48 augustss }
2651 1.48 augustss
2652 1.48 augustss void
2653 1.119 augustss uhci_device_isoc_enter(usbd_xfer_handle xfer)
2654 1.48 augustss {
2655 1.63 augustss struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe;
2656 1.16 augustss usbd_device_handle dev = upipe->pipe.device;
2657 1.216 drochner uhci_softc_t *sc = dev->bus->hci_private;
2658 1.48 augustss struct iso *iso = &upipe->u.iso;
2659 1.152 augustss uhci_soft_td_t *std;
2660 1.264.4.1 skrll uint32_t buf, len, status, offs;
2661 1.248 mrg int i, next, nframes;
2662 1.223 bouyer int rd = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN;
2663 1.48 augustss
2664 1.63 augustss DPRINTFN(5,("uhci_device_isoc_enter: used=%d next=%d xfer=%p "
2665 1.48 augustss "nframes=%d\n",
2666 1.63 augustss iso->inuse, iso->next, xfer, xfer->nframes));
2667 1.48 augustss
2668 1.82 augustss if (sc->sc_dying)
2669 1.82 augustss return;
2670 1.82 augustss
2671 1.63 augustss if (xfer->status == USBD_IN_PROGRESS) {
2672 1.48 augustss /* This request has already been entered into the frame list */
2673 1.96 augustss printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer);
2674 1.68 augustss /* XXX */
2675 1.48 augustss }
2676 1.48 augustss
2677 1.48 augustss #ifdef DIAGNOSTIC
2678 1.48 augustss if (iso->inuse >= UHCI_VFRAMELIST_COUNT)
2679 1.48 augustss printf("uhci_device_isoc_enter: overflow!\n");
2680 1.19 augustss #endif
2681 1.16 augustss
2682 1.48 augustss next = iso->next;
2683 1.48 augustss if (next == -1) {
2684 1.48 augustss /* Not in use yet, schedule it a few frames ahead. */
2685 1.48 augustss next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT;
2686 1.48 augustss DPRINTFN(2,("uhci_device_isoc_enter: start next=%d\n", next));
2687 1.48 augustss }
2688 1.48 augustss
2689 1.63 augustss xfer->status = USBD_IN_PROGRESS;
2690 1.92 augustss UXFER(xfer)->curframe = next;
2691 1.48 augustss
2692 1.160 augustss buf = DMAADDR(&xfer->dmabuf, 0);
2693 1.223 bouyer offs = 0;
2694 1.88 tsutsui status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) |
2695 1.88 tsutsui UHCI_TD_ACTIVE |
2696 1.88 tsutsui UHCI_TD_IOS);
2697 1.63 augustss nframes = xfer->nframes;
2698 1.248 mrg mutex_enter(&sc->sc_lock);
2699 1.48 augustss for (i = 0; i < nframes; i++) {
2700 1.48 augustss std = iso->stds[next];
2701 1.48 augustss if (++next >= UHCI_VFRAMELIST_COUNT)
2702 1.48 augustss next = 0;
2703 1.63 augustss len = xfer->frlengths[i];
2704 1.88 tsutsui std->td.td_buffer = htole32(buf);
2705 1.250 christos usb_syncmem(&xfer->dmabuf, offs, len,
2706 1.223 bouyer rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
2707 1.48 augustss if (i == nframes - 1)
2708 1.88 tsutsui status |= UHCI_TD_IOC;
2709 1.88 tsutsui std->td.td_status = htole32(status);
2710 1.88 tsutsui std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK);
2711 1.88 tsutsui std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len));
2712 1.223 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
2713 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2714 1.59 augustss #ifdef UHCI_DEBUG
2715 1.48 augustss if (uhcidebug > 5) {
2716 1.48 augustss DPRINTFN(5,("uhci_device_isoc_enter: TD %d\n", i));
2717 1.48 augustss uhci_dump_td(std);
2718 1.48 augustss }
2719 1.48 augustss #endif
2720 1.48 augustss buf += len;
2721 1.223 bouyer offs += len;
2722 1.48 augustss }
2723 1.48 augustss iso->next = next;
2724 1.63 augustss iso->inuse += xfer->nframes;
2725 1.16 augustss
2726 1.248 mrg mutex_exit(&sc->sc_lock);
2727 1.16 augustss }
2728 1.16 augustss
2729 1.16 augustss usbd_status
2730 1.119 augustss uhci_device_isoc_start(usbd_xfer_handle xfer)
2731 1.16 augustss {
2732 1.63 augustss struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe;
2733 1.216 drochner uhci_softc_t *sc = upipe->pipe.device->bus->hci_private;
2734 1.92 augustss uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
2735 1.48 augustss uhci_soft_td_t *end;
2736 1.248 mrg int i;
2737 1.48 augustss
2738 1.96 augustss DPRINTFN(5,("uhci_device_isoc_start: xfer=%p\n", xfer));
2739 1.96 augustss
2740 1.248 mrg mutex_enter(&sc->sc_lock);
2741 1.248 mrg
2742 1.248 mrg if (sc->sc_dying) {
2743 1.248 mrg mutex_exit(&sc->sc_lock);
2744 1.82 augustss return (USBD_IOERROR);
2745 1.248 mrg }
2746 1.82 augustss
2747 1.48 augustss #ifdef DIAGNOSTIC
2748 1.63 augustss if (xfer->status != USBD_IN_PROGRESS)
2749 1.63 augustss printf("uhci_device_isoc_start: not in progress %p\n", xfer);
2750 1.48 augustss #endif
2751 1.48 augustss
2752 1.48 augustss /* Find the last TD */
2753 1.92 augustss i = UXFER(xfer)->curframe + xfer->nframes;
2754 1.48 augustss if (i >= UHCI_VFRAMELIST_COUNT)
2755 1.48 augustss i -= UHCI_VFRAMELIST_COUNT;
2756 1.48 augustss end = upipe->u.iso.stds[i];
2757 1.48 augustss
2758 1.96 augustss #ifdef DIAGNOSTIC
2759 1.96 augustss if (end == NULL) {
2760 1.96 augustss printf("uhci_device_isoc_start: end == NULL\n");
2761 1.96 augustss return (USBD_INVAL);
2762 1.96 augustss }
2763 1.96 augustss #endif
2764 1.96 augustss
2765 1.48 augustss /* Set up interrupt info. */
2766 1.63 augustss ii->xfer = xfer;
2767 1.48 augustss ii->stdstart = end;
2768 1.48 augustss ii->stdend = end;
2769 1.48 augustss #ifdef DIAGNOSTIC
2770 1.102 augustss if (!ii->isdone)
2771 1.70 augustss printf("uhci_device_isoc_start: not done, ii=%p\n", ii);
2772 1.48 augustss ii->isdone = 0;
2773 1.48 augustss #endif
2774 1.92 augustss uhci_add_intr_info(sc, ii);
2775 1.152 augustss
2776 1.248 mrg mutex_exit(&sc->sc_lock);
2777 1.48 augustss
2778 1.48 augustss return (USBD_IN_PROGRESS);
2779 1.16 augustss }
2780 1.16 augustss
2781 1.16 augustss void
2782 1.119 augustss uhci_device_isoc_abort(usbd_xfer_handle xfer)
2783 1.16 augustss {
2784 1.248 mrg #ifdef DIAGNOSTIC
2785 1.248 mrg uhci_softc_t *sc = xfer->pipe->device->bus->hci_private;
2786 1.248 mrg #endif
2787 1.63 augustss struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe;
2788 1.48 augustss uhci_soft_td_t **stds = upipe->u.iso.stds;
2789 1.48 augustss uhci_soft_td_t *std;
2790 1.248 mrg int i, n, nframes, maxlen, len;
2791 1.92 augustss
2792 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2793 1.92 augustss
2794 1.92 augustss /* Transfer is already done. */
2795 1.152 augustss if (xfer->status != USBD_NOT_STARTED &&
2796 1.92 augustss xfer->status != USBD_IN_PROGRESS) {
2797 1.92 augustss return;
2798 1.92 augustss }
2799 1.48 augustss
2800 1.92 augustss /* Give xfer the requested abort code. */
2801 1.63 augustss xfer->status = USBD_CANCELLED;
2802 1.48 augustss
2803 1.48 augustss /* make hardware ignore it, */
2804 1.63 augustss nframes = xfer->nframes;
2805 1.92 augustss n = UXFER(xfer)->curframe;
2806 1.92 augustss maxlen = 0;
2807 1.48 augustss for (i = 0; i < nframes; i++) {
2808 1.48 augustss std = stds[n];
2809 1.223 bouyer usb_syncmem(&std->dma,
2810 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
2811 1.223 bouyer sizeof(std->td.td_status),
2812 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2813 1.88 tsutsui std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC));
2814 1.223 bouyer usb_syncmem(&std->dma,
2815 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
2816 1.223 bouyer sizeof(std->td.td_status),
2817 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2818 1.223 bouyer usb_syncmem(&std->dma,
2819 1.223 bouyer std->offs + offsetof(uhci_td_t, td_token),
2820 1.223 bouyer sizeof(std->td.td_token),
2821 1.223 bouyer BUS_DMASYNC_POSTWRITE);
2822 1.130 tsutsui len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token));
2823 1.92 augustss if (len > maxlen)
2824 1.92 augustss maxlen = len;
2825 1.48 augustss if (++n >= UHCI_VFRAMELIST_COUNT)
2826 1.48 augustss n = 0;
2827 1.48 augustss }
2828 1.48 augustss
2829 1.92 augustss /* and wait until we are sure the hardware has finished. */
2830 1.92 augustss delay(maxlen);
2831 1.92 augustss
2832 1.96 augustss #ifdef DIAGNOSTIC
2833 1.96 augustss UXFER(xfer)->iinfo.isdone = 1;
2834 1.96 augustss #endif
2835 1.92 augustss /* Run callback and remove from interrupt list. */
2836 1.92 augustss usb_transfer_complete(xfer);
2837 1.48 augustss
2838 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2839 1.16 augustss }
2840 1.16 augustss
2841 1.16 augustss void
2842 1.119 augustss uhci_device_isoc_close(usbd_pipe_handle pipe)
2843 1.16 augustss {
2844 1.16 augustss struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;
2845 1.16 augustss usbd_device_handle dev = upipe->pipe.device;
2846 1.216 drochner uhci_softc_t *sc = dev->bus->hci_private;
2847 1.48 augustss uhci_soft_td_t *std, *vstd;
2848 1.16 augustss struct iso *iso;
2849 1.248 mrg int i;
2850 1.248 mrg
2851 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2852 1.16 augustss
2853 1.16 augustss /*
2854 1.16 augustss * Make sure all TDs are marked as inactive.
2855 1.16 augustss * Wait for completion.
2856 1.16 augustss * Unschedule.
2857 1.16 augustss * Deallocate.
2858 1.16 augustss */
2859 1.16 augustss iso = &upipe->u.iso;
2860 1.16 augustss
2861 1.223 bouyer for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
2862 1.223 bouyer std = iso->stds[i];
2863 1.223 bouyer usb_syncmem(&std->dma,
2864 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
2865 1.223 bouyer sizeof(std->td.td_status),
2866 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2867 1.223 bouyer std->td.td_status &= htole32(~UHCI_TD_ACTIVE);
2868 1.223 bouyer usb_syncmem(&std->dma,
2869 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
2870 1.223 bouyer sizeof(std->td.td_status),
2871 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2872 1.223 bouyer }
2873 1.248 mrg /* wait for completion */
2874 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock);
2875 1.16 augustss
2876 1.16 augustss for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
2877 1.16 augustss std = iso->stds[i];
2878 1.48 augustss for (vstd = sc->sc_vframes[i].htd;
2879 1.67 augustss vstd != NULL && vstd->link.std != std;
2880 1.42 augustss vstd = vstd->link.std)
2881 1.16 augustss ;
2882 1.67 augustss if (vstd == NULL) {
2883 1.16 augustss /*panic*/
2884 1.16 augustss printf("uhci_device_isoc_close: %p not found\n", std);
2885 1.248 mrg mutex_exit(&sc->sc_lock);
2886 1.16 augustss return;
2887 1.16 augustss }
2888 1.42 augustss vstd->link = std->link;
2889 1.223 bouyer usb_syncmem(&std->dma,
2890 1.223 bouyer std->offs + offsetof(uhci_td_t, td_link),
2891 1.223 bouyer sizeof(std->td.td_link),
2892 1.223 bouyer BUS_DMASYNC_POSTWRITE);
2893 1.42 augustss vstd->td.td_link = std->td.td_link;
2894 1.223 bouyer usb_syncmem(&vstd->dma,
2895 1.223 bouyer vstd->offs + offsetof(uhci_td_t, td_link),
2896 1.223 bouyer sizeof(vstd->td.td_link),
2897 1.223 bouyer BUS_DMASYNC_PREWRITE);
2898 1.16 augustss uhci_free_std(sc, std);
2899 1.16 augustss }
2900 1.16 augustss
2901 1.248 mrg kmem_free(iso->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *));
2902 1.16 augustss }
2903 1.16 augustss
2904 1.16 augustss usbd_status
2905 1.119 augustss uhci_setup_isoc(usbd_pipe_handle pipe)
2906 1.16 augustss {
2907 1.16 augustss struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;
2908 1.16 augustss usbd_device_handle dev = upipe->pipe.device;
2909 1.216 drochner uhci_softc_t *sc = dev->bus->hci_private;
2910 1.16 augustss int addr = upipe->pipe.device->address;
2911 1.16 augustss int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress;
2912 1.45 augustss int rd = UE_GET_DIR(endpt) == UE_DIR_IN;
2913 1.48 augustss uhci_soft_td_t *std, *vstd;
2914 1.264.4.1 skrll uint32_t token;
2915 1.16 augustss struct iso *iso;
2916 1.248 mrg int i;
2917 1.16 augustss
2918 1.16 augustss iso = &upipe->u.iso;
2919 1.248 mrg iso->stds = kmem_alloc(UHCI_VFRAMELIST_COUNT *
2920 1.248 mrg sizeof (uhci_soft_td_t *),
2921 1.248 mrg KM_SLEEP);
2922 1.248 mrg if (iso->stds == NULL)
2923 1.248 mrg return USBD_NOMEM;
2924 1.16 augustss
2925 1.88 tsutsui token = rd ? UHCI_TD_IN (0, endpt, addr, 0) :
2926 1.88 tsutsui UHCI_TD_OUT(0, endpt, addr, 0);
2927 1.16 augustss
2928 1.248 mrg mutex_enter(&sc->sc_lock);
2929 1.248 mrg
2930 1.48 augustss /* Allocate the TDs and mark as inactive; */
2931 1.16 augustss for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
2932 1.48 augustss std = uhci_alloc_std(sc);
2933 1.48 augustss if (std == 0)
2934 1.48 augustss goto bad;
2935 1.88 tsutsui std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */
2936 1.88 tsutsui std->td.td_token = htole32(token);
2937 1.223 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
2938 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2939 1.48 augustss iso->stds[i] = std;
2940 1.16 augustss }
2941 1.16 augustss
2942 1.48 augustss /* Insert TDs into schedule. */
2943 1.16 augustss for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
2944 1.16 augustss std = iso->stds[i];
2945 1.48 augustss vstd = sc->sc_vframes[i].htd;
2946 1.223 bouyer usb_syncmem(&vstd->dma,
2947 1.223 bouyer vstd->offs + offsetof(uhci_td_t, td_link),
2948 1.223 bouyer sizeof(vstd->td.td_link),
2949 1.223 bouyer BUS_DMASYNC_POSTWRITE);
2950 1.42 augustss std->link = vstd->link;
2951 1.42 augustss std->td.td_link = vstd->td.td_link;
2952 1.223 bouyer usb_syncmem(&std->dma,
2953 1.223 bouyer std->offs + offsetof(uhci_td_t, td_link),
2954 1.223 bouyer sizeof(std->td.td_link),
2955 1.223 bouyer BUS_DMASYNC_PREWRITE);
2956 1.42 augustss vstd->link.std = std;
2957 1.121 augustss vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD);
2958 1.223 bouyer usb_syncmem(&vstd->dma,
2959 1.223 bouyer vstd->offs + offsetof(uhci_td_t, td_link),
2960 1.223 bouyer sizeof(vstd->td.td_link),
2961 1.223 bouyer BUS_DMASYNC_PREWRITE);
2962 1.16 augustss }
2963 1.248 mrg mutex_exit(&sc->sc_lock);
2964 1.16 augustss
2965 1.48 augustss iso->next = -1;
2966 1.48 augustss iso->inuse = 0;
2967 1.48 augustss
2968 1.16 augustss return (USBD_NORMAL_COMPLETION);
2969 1.16 augustss
2970 1.48 augustss bad:
2971 1.16 augustss while (--i >= 0)
2972 1.16 augustss uhci_free_std(sc, iso->stds[i]);
2973 1.248 mrg mutex_exit(&sc->sc_lock);
2974 1.248 mrg kmem_free(iso->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *));
2975 1.16 augustss return (USBD_NOMEM);
2976 1.16 augustss }
2977 1.16 augustss
2978 1.16 augustss void
2979 1.119 augustss uhci_device_isoc_done(usbd_xfer_handle xfer)
2980 1.16 augustss {
2981 1.92 augustss uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
2982 1.223 bouyer struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe;
2983 1.223 bouyer int i, offs;
2984 1.223 bouyer int rd = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN;
2985 1.223 bouyer
2986 1.48 augustss
2987 1.197 gdamore DPRINTFN(4, ("uhci_isoc_done: length=%d, busy_free=0x%08x\n",
2988 1.197 gdamore xfer->actlen, xfer->busy_free));
2989 1.93 augustss
2990 1.96 augustss if (ii->xfer != xfer)
2991 1.96 augustss /* Not on interrupt list, ignore it. */
2992 1.170 augustss return;
2993 1.170 augustss
2994 1.170 augustss if (!uhci_active_intr_info(ii))
2995 1.96 augustss return;
2996 1.96 augustss
2997 1.93 augustss #ifdef DIAGNOSTIC
2998 1.264.4.2 skrll if (ii->stdend == NULL) {
2999 1.264.4.2 skrll printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer);
3000 1.93 augustss #ifdef UHCI_DEBUG
3001 1.93 augustss uhci_dump_ii(ii);
3002 1.93 augustss #endif
3003 1.93 augustss return;
3004 1.93 augustss }
3005 1.93 augustss #endif
3006 1.48 augustss
3007 1.48 augustss /* Turn off the interrupt since it is active even if the TD is not. */
3008 1.223 bouyer usb_syncmem(&ii->stdend->dma,
3009 1.223 bouyer ii->stdend->offs + offsetof(uhci_td_t, td_status),
3010 1.223 bouyer sizeof(ii->stdend->td.td_status),
3011 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3012 1.88 tsutsui ii->stdend->td.td_status &= htole32(~UHCI_TD_IOC);
3013 1.223 bouyer usb_syncmem(&ii->stdend->dma,
3014 1.223 bouyer ii->stdend->offs + offsetof(uhci_td_t, td_status),
3015 1.223 bouyer sizeof(ii->stdend->td.td_status),
3016 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3017 1.48 augustss
3018 1.92 augustss uhci_del_intr_info(ii); /* remove from active list */
3019 1.223 bouyer
3020 1.223 bouyer offs = 0;
3021 1.223 bouyer for (i = 0; i < xfer->nframes; i++) {
3022 1.223 bouyer usb_syncmem(&xfer->dmabuf, offs, xfer->frlengths[i],
3023 1.223 bouyer rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
3024 1.223 bouyer offs += xfer->frlengths[i];
3025 1.223 bouyer }
3026 1.16 augustss }
3027 1.16 augustss
3028 1.1 augustss void
3029 1.119 augustss uhci_device_intr_done(usbd_xfer_handle xfer)
3030 1.1 augustss {
3031 1.92 augustss uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
3032 1.1 augustss uhci_softc_t *sc = ii->sc;
3033 1.63 augustss struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe;
3034 1.1 augustss uhci_soft_qh_t *sqh;
3035 1.223 bouyer int i, npoll, isread;
3036 1.1 augustss
3037 1.173 gson DPRINTFN(5, ("uhci_device_intr_done: length=%d\n", xfer->actlen));
3038 1.1 augustss
3039 1.257 skrll KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock));
3040 1.248 mrg
3041 1.1 augustss npoll = upipe->u.intr.npoll;
3042 1.1 augustss for(i = 0; i < npoll; i++) {
3043 1.1 augustss sqh = upipe->u.intr.qhs[i];
3044 1.121 augustss sqh->elink = NULL;
3045 1.88 tsutsui sqh->qh.qh_elink = htole32(UHCI_PTR_T);
3046 1.223 bouyer usb_syncmem(&sqh->dma,
3047 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
3048 1.223 bouyer sizeof(sqh->qh.qh_elink),
3049 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3050 1.1 augustss }
3051 1.149 augustss uhci_free_std_chain(sc, ii->stdstart, NULL);
3052 1.1 augustss
3053 1.223 bouyer isread = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN;
3054 1.250 christos usb_syncmem(&xfer->dmabuf, 0, xfer->length,
3055 1.223 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
3056 1.223 bouyer
3057 1.1 augustss /* XXX Wasteful. */
3058 1.63 augustss if (xfer->pipe->repeat) {
3059 1.55 augustss uhci_soft_td_t *data, *dataend;
3060 1.1 augustss
3061 1.92 augustss DPRINTFN(5,("uhci_device_intr_done: requeing\n"));
3062 1.92 augustss
3063 1.1 augustss /* This alloc cannot fail since we freed the chain above. */
3064 1.221 jmcneill uhci_alloc_std_chain(upipe, sc, xfer->length,
3065 1.221 jmcneill upipe->u.intr.isread, xfer->flags,
3066 1.63 augustss &xfer->dmabuf, &data, &dataend);
3067 1.88 tsutsui dataend->td.td_status |= htole32(UHCI_TD_IOC);
3068 1.223 bouyer usb_syncmem(&dataend->dma,
3069 1.223 bouyer dataend->offs + offsetof(uhci_td_t, td_status),
3070 1.223 bouyer sizeof(dataend->td.td_status),
3071 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3072 1.1 augustss
3073 1.59 augustss #ifdef UHCI_DEBUG
3074 1.1 augustss if (uhcidebug > 10) {
3075 1.55 augustss DPRINTF(("uhci_device_intr_done: data(1)\n"));
3076 1.55 augustss uhci_dump_tds(data);
3077 1.1 augustss uhci_dump_qh(upipe->u.intr.qhs[0]);
3078 1.1 augustss }
3079 1.1 augustss #endif
3080 1.1 augustss
3081 1.55 augustss ii->stdstart = data;
3082 1.55 augustss ii->stdend = dataend;
3083 1.7 augustss #ifdef DIAGNOSTIC
3084 1.70 augustss if (!ii->isdone) {
3085 1.70 augustss printf("uhci_device_intr_done: not done, ii=%p\n", ii);
3086 1.70 augustss }
3087 1.7 augustss ii->isdone = 0;
3088 1.7 augustss #endif
3089 1.1 augustss for (i = 0; i < npoll; i++) {
3090 1.1 augustss sqh = upipe->u.intr.qhs[i];
3091 1.55 augustss sqh->elink = data;
3092 1.121 augustss sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD);
3093 1.223 bouyer usb_syncmem(&sqh->dma,
3094 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
3095 1.223 bouyer sizeof(sqh->qh.qh_elink),
3096 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3097 1.1 augustss }
3098 1.92 augustss xfer->status = USBD_IN_PROGRESS;
3099 1.92 augustss /* The ii is already on the examined list, just leave it. */
3100 1.1 augustss } else {
3101 1.92 augustss DPRINTFN(5,("uhci_device_intr_done: removing\n"));
3102 1.169 augustss if (uhci_active_intr_info(ii))
3103 1.169 augustss uhci_del_intr_info(ii);
3104 1.1 augustss }
3105 1.1 augustss }
3106 1.1 augustss
3107 1.1 augustss /* Deallocate request data structures */
3108 1.1 augustss void
3109 1.119 augustss uhci_device_ctrl_done(usbd_xfer_handle xfer)
3110 1.1 augustss {
3111 1.92 augustss uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
3112 1.1 augustss uhci_softc_t *sc = ii->sc;
3113 1.63 augustss struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe;
3114 1.223 bouyer int len = UGETW(xfer->request.wLength);
3115 1.223 bouyer int isread = (xfer->request.bmRequestType & UT_READ);
3116 1.1 augustss
3117 1.263 skrll KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock));
3118 1.248 mrg
3119 1.7 augustss #ifdef DIAGNOSTIC
3120 1.63 augustss if (!(xfer->rqflags & URQ_REQUEST))
3121 1.173 gson panic("uhci_device_ctrl_done: not a request");
3122 1.7 augustss #endif
3123 1.1 augustss
3124 1.169 augustss if (!uhci_active_intr_info(ii))
3125 1.169 augustss return;
3126 1.169 augustss
3127 1.92 augustss uhci_del_intr_info(ii); /* remove from active list */
3128 1.1 augustss
3129 1.144 augustss if (upipe->pipe.device->speed == USB_SPEED_LOW)
3130 1.123 augustss uhci_remove_ls_ctrl(sc, upipe->u.ctl.sqh);
3131 1.123 augustss else
3132 1.123 augustss uhci_remove_hs_ctrl(sc, upipe->u.ctl.sqh);
3133 1.1 augustss
3134 1.49 augustss if (upipe->u.ctl.length != 0)
3135 1.42 augustss uhci_free_std_chain(sc, ii->stdstart->link.std, ii->stdend);
3136 1.49 augustss
3137 1.223 bouyer if (len) {
3138 1.250 christos usb_syncmem(&xfer->dmabuf, 0, len,
3139 1.223 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
3140 1.223 bouyer }
3141 1.223 bouyer usb_syncmem(&upipe->u.ctl.reqdma, 0,
3142 1.223 bouyer sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE);
3143 1.223 bouyer
3144 1.173 gson DPRINTFN(5, ("uhci_device_ctrl_done: length=%d\n", xfer->actlen));
3145 1.1 augustss }
3146 1.1 augustss
3147 1.1 augustss /* Deallocate request data structures */
3148 1.1 augustss void
3149 1.119 augustss uhci_device_bulk_done(usbd_xfer_handle xfer)
3150 1.1 augustss {
3151 1.92 augustss uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
3152 1.1 augustss uhci_softc_t *sc = ii->sc;
3153 1.63 augustss struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe;
3154 1.169 augustss
3155 1.173 gson DPRINTFN(5,("uhci_device_bulk_done: xfer=%p ii=%p sc=%p upipe=%p\n",
3156 1.169 augustss xfer, ii, sc, upipe));
3157 1.169 augustss
3158 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
3159 1.248 mrg
3160 1.169 augustss if (!uhci_active_intr_info(ii))
3161 1.169 augustss return;
3162 1.1 augustss
3163 1.92 augustss uhci_del_intr_info(ii); /* remove from active list */
3164 1.1 augustss
3165 1.1 augustss uhci_remove_bulk(sc, upipe->u.bulk.sqh);
3166 1.32 augustss
3167 1.149 augustss uhci_free_std_chain(sc, ii->stdstart, NULL);
3168 1.32 augustss
3169 1.173 gson DPRINTFN(5, ("uhci_device_bulk_done: length=%d\n", xfer->actlen));
3170 1.1 augustss }
3171 1.1 augustss
3172 1.1 augustss /* Add interrupt QH, called with vflock. */
3173 1.1 augustss void
3174 1.119 augustss uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
3175 1.1 augustss {
3176 1.92 augustss struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos];
3177 1.42 augustss uhci_soft_qh_t *eqh;
3178 1.1 augustss
3179 1.92 augustss DPRINTFN(4, ("uhci_add_intr: n=%d sqh=%p\n", sqh->pos, sqh));
3180 1.92 augustss
3181 1.42 augustss eqh = vf->eqh;
3182 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
3183 1.223 bouyer sizeof(eqh->qh.qh_hlink),
3184 1.223 bouyer BUS_DMASYNC_POSTWRITE);
3185 1.42 augustss sqh->hlink = eqh->hlink;
3186 1.42 augustss sqh->qh.qh_hlink = eqh->qh.qh_hlink;
3187 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
3188 1.223 bouyer sizeof(sqh->qh.qh_hlink),
3189 1.223 bouyer BUS_DMASYNC_PREWRITE);
3190 1.42 augustss eqh->hlink = sqh;
3191 1.121 augustss eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
3192 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
3193 1.223 bouyer sizeof(eqh->qh.qh_hlink),
3194 1.223 bouyer BUS_DMASYNC_PREWRITE);
3195 1.1 augustss vf->eqh = sqh;
3196 1.1 augustss vf->bandwidth++;
3197 1.1 augustss }
3198 1.1 augustss
3199 1.119 augustss /* Remove interrupt QH. */
3200 1.1 augustss void
3201 1.119 augustss uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
3202 1.1 augustss {
3203 1.92 augustss struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos];
3204 1.1 augustss uhci_soft_qh_t *pqh;
3205 1.1 augustss
3206 1.92 augustss DPRINTFN(4, ("uhci_remove_intr: n=%d sqh=%p\n", sqh->pos, sqh));
3207 1.1 augustss
3208 1.124 augustss /* See comment in uhci_remove_ctrl() */
3209 1.223 bouyer
3210 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
3211 1.223 bouyer sizeof(sqh->qh.qh_elink),
3212 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3213 1.124 augustss if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) {
3214 1.124 augustss sqh->qh.qh_elink = htole32(UHCI_PTR_T);
3215 1.223 bouyer usb_syncmem(&sqh->dma,
3216 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
3217 1.223 bouyer sizeof(sqh->qh.qh_elink),
3218 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3219 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
3220 1.124 augustss }
3221 1.124 augustss
3222 1.92 augustss pqh = uhci_find_prev_qh(vf->hqh, sqh);
3223 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
3224 1.223 bouyer sizeof(sqh->qh.qh_hlink),
3225 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3226 1.42 augustss pqh->hlink = sqh->hlink;
3227 1.42 augustss pqh->qh.qh_hlink = sqh->qh.qh_hlink;
3228 1.223 bouyer usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
3229 1.223 bouyer sizeof(pqh->qh.qh_hlink),
3230 1.223 bouyer BUS_DMASYNC_PREWRITE);
3231 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
3232 1.1 augustss if (vf->eqh == sqh)
3233 1.1 augustss vf->eqh = pqh;
3234 1.1 augustss vf->bandwidth--;
3235 1.1 augustss }
3236 1.1 augustss
3237 1.1 augustss usbd_status
3238 1.119 augustss uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival)
3239 1.1 augustss {
3240 1.1 augustss uhci_soft_qh_t *sqh;
3241 1.248 mrg int i, npoll;
3242 1.1 augustss u_int bestbw, bw, bestoffs, offs;
3243 1.1 augustss
3244 1.173 gson DPRINTFN(2, ("uhci_device_setintr: pipe=%p\n", upipe));
3245 1.1 augustss if (ival == 0) {
3246 1.173 gson printf("uhci_device_setintr: 0 interval\n");
3247 1.1 augustss return (USBD_INVAL);
3248 1.1 augustss }
3249 1.1 augustss
3250 1.1 augustss if (ival > UHCI_VFRAMELIST_COUNT)
3251 1.1 augustss ival = UHCI_VFRAMELIST_COUNT;
3252 1.1 augustss npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival;
3253 1.173 gson DPRINTFN(2, ("uhci_device_setintr: ival=%d npoll=%d\n", ival, npoll));
3254 1.1 augustss
3255 1.1 augustss upipe->u.intr.npoll = npoll;
3256 1.152 augustss upipe->u.intr.qhs =
3257 1.248 mrg kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP);
3258 1.248 mrg if (upipe->u.intr.qhs == NULL)
3259 1.248 mrg return USBD_NOMEM;
3260 1.1 augustss
3261 1.152 augustss /*
3262 1.1 augustss * Figure out which offset in the schedule that has most
3263 1.1 augustss * bandwidth left over.
3264 1.1 augustss */
3265 1.1 augustss #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1))
3266 1.1 augustss for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) {
3267 1.1 augustss for (bw = i = 0; i < npoll; i++)
3268 1.1 augustss bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth;
3269 1.1 augustss if (bw < bestbw) {
3270 1.1 augustss bestbw = bw;
3271 1.1 augustss bestoffs = offs;
3272 1.1 augustss }
3273 1.1 augustss }
3274 1.173 gson DPRINTFN(1, ("uhci_device_setintr: bw=%d offs=%d\n", bestbw, bestoffs));
3275 1.1 augustss
3276 1.248 mrg mutex_enter(&sc->sc_lock);
3277 1.1 augustss for(i = 0; i < npoll; i++) {
3278 1.1 augustss upipe->u.intr.qhs[i] = sqh = uhci_alloc_sqh(sc);
3279 1.121 augustss sqh->elink = NULL;
3280 1.88 tsutsui sqh->qh.qh_elink = htole32(UHCI_PTR_T);
3281 1.223 bouyer usb_syncmem(&sqh->dma,
3282 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
3283 1.223 bouyer sizeof(sqh->qh.qh_elink),
3284 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3285 1.1 augustss sqh->pos = MOD(i * ival + bestoffs);
3286 1.1 augustss }
3287 1.1 augustss #undef MOD
3288 1.1 augustss
3289 1.1 augustss /* Enter QHs into the controller data structures. */
3290 1.1 augustss for(i = 0; i < npoll; i++)
3291 1.92 augustss uhci_add_intr(sc, upipe->u.intr.qhs[i]);
3292 1.248 mrg mutex_exit(&sc->sc_lock);
3293 1.1 augustss
3294 1.173 gson DPRINTFN(5, ("uhci_device_setintr: returns %p\n", upipe));
3295 1.1 augustss return (USBD_NORMAL_COMPLETION);
3296 1.1 augustss }
3297 1.1 augustss
3298 1.1 augustss /* Open a new pipe. */
3299 1.1 augustss usbd_status
3300 1.119 augustss uhci_open(usbd_pipe_handle pipe)
3301 1.1 augustss {
3302 1.216 drochner uhci_softc_t *sc = pipe->device->bus->hci_private;
3303 1.1 augustss struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;
3304 1.1 augustss usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc;
3305 1.248 mrg usbd_status err = USBD_NOMEM;
3306 1.79 augustss int ival;
3307 1.1 augustss
3308 1.1 augustss DPRINTFN(1, ("uhci_open: pipe=%p, addr=%d, endpt=%d (%d)\n",
3309 1.152 augustss pipe, pipe->device->address,
3310 1.1 augustss ed->bEndpointAddress, sc->sc_addr));
3311 1.92 augustss
3312 1.248 mrg if (sc->sc_dying)
3313 1.248 mrg return USBD_IOERROR;
3314 1.248 mrg
3315 1.92 augustss upipe->aborting = 0;
3316 1.236 drochner /* toggle state needed for bulk endpoints */
3317 1.236 drochner upipe->nexttoggle = pipe->endpoint->datatoggle;
3318 1.92 augustss
3319 1.1 augustss if (pipe->device->address == sc->sc_addr) {
3320 1.1 augustss switch (ed->bEndpointAddress) {
3321 1.1 augustss case USB_CONTROL_ENDPOINT:
3322 1.1 augustss pipe->methods = &uhci_root_ctrl_methods;
3323 1.1 augustss break;
3324 1.45 augustss case UE_DIR_IN | UHCI_INTR_ENDPT:
3325 1.1 augustss pipe->methods = &uhci_root_intr_methods;
3326 1.1 augustss break;
3327 1.1 augustss default:
3328 1.1 augustss return (USBD_INVAL);
3329 1.1 augustss }
3330 1.1 augustss } else {
3331 1.1 augustss switch (ed->bmAttributes & UE_XFERTYPE) {
3332 1.1 augustss case UE_CONTROL:
3333 1.1 augustss pipe->methods = &uhci_device_ctrl_methods;
3334 1.1 augustss upipe->u.ctl.sqh = uhci_alloc_sqh(sc);
3335 1.63 augustss if (upipe->u.ctl.sqh == NULL)
3336 1.5 augustss goto bad;
3337 1.1 augustss upipe->u.ctl.setup = uhci_alloc_std(sc);
3338 1.63 augustss if (upipe->u.ctl.setup == NULL) {
3339 1.5 augustss uhci_free_sqh(sc, upipe->u.ctl.sqh);
3340 1.5 augustss goto bad;
3341 1.5 augustss }
3342 1.1 augustss upipe->u.ctl.stat = uhci_alloc_std(sc);
3343 1.63 augustss if (upipe->u.ctl.stat == NULL) {
3344 1.5 augustss uhci_free_sqh(sc, upipe->u.ctl.sqh);
3345 1.5 augustss uhci_free_std(sc, upipe->u.ctl.setup);
3346 1.5 augustss goto bad;
3347 1.5 augustss }
3348 1.152 augustss err = usb_allocmem(&sc->sc_bus,
3349 1.152 augustss sizeof(usb_device_request_t),
3350 1.63 augustss 0, &upipe->u.ctl.reqdma);
3351 1.63 augustss if (err) {
3352 1.5 augustss uhci_free_sqh(sc, upipe->u.ctl.sqh);
3353 1.5 augustss uhci_free_std(sc, upipe->u.ctl.setup);
3354 1.5 augustss uhci_free_std(sc, upipe->u.ctl.stat);
3355 1.5 augustss goto bad;
3356 1.5 augustss }
3357 1.1 augustss break;
3358 1.1 augustss case UE_INTERRUPT:
3359 1.1 augustss pipe->methods = &uhci_device_intr_methods;
3360 1.79 augustss ival = pipe->interval;
3361 1.79 augustss if (ival == USBD_DEFAULT_INTERVAL)
3362 1.79 augustss ival = ed->bInterval;
3363 1.80 augustss return (uhci_device_setintr(sc, upipe, ival));
3364 1.1 augustss case UE_ISOCHRONOUS:
3365 1.16 augustss pipe->methods = &uhci_device_isoc_methods;
3366 1.48 augustss return (uhci_setup_isoc(pipe));
3367 1.1 augustss case UE_BULK:
3368 1.1 augustss pipe->methods = &uhci_device_bulk_methods;
3369 1.1 augustss upipe->u.bulk.sqh = uhci_alloc_sqh(sc);
3370 1.63 augustss if (upipe->u.bulk.sqh == NULL)
3371 1.5 augustss goto bad;
3372 1.1 augustss break;
3373 1.1 augustss }
3374 1.1 augustss }
3375 1.1 augustss return (USBD_NORMAL_COMPLETION);
3376 1.5 augustss
3377 1.5 augustss bad:
3378 1.248 mrg return USBD_NOMEM;
3379 1.1 augustss }
3380 1.1 augustss
3381 1.1 augustss /*
3382 1.1 augustss * Data structures and routines to emulate the root hub.
3383 1.1 augustss */
3384 1.1 augustss usb_device_descriptor_t uhci_devd = {
3385 1.1 augustss USB_DEVICE_DESCRIPTOR_SIZE,
3386 1.1 augustss UDESC_DEVICE, /* type */
3387 1.1 augustss {0x00, 0x01}, /* USB version */
3388 1.87 augustss UDCLASS_HUB, /* class */
3389 1.87 augustss UDSUBCLASS_HUB, /* subclass */
3390 1.144 augustss UDPROTO_FSHUB, /* protocol */
3391 1.1 augustss 64, /* max packet */
3392 1.1 augustss {0},{0},{0x00,0x01}, /* device id */
3393 1.1 augustss 1,2,0, /* string indicies */
3394 1.1 augustss 1 /* # of configurations */
3395 1.1 augustss };
3396 1.1 augustss
3397 1.208 drochner const usb_config_descriptor_t uhci_confd = {
3398 1.1 augustss USB_CONFIG_DESCRIPTOR_SIZE,
3399 1.1 augustss UDESC_CONFIG,
3400 1.1 augustss {USB_CONFIG_DESCRIPTOR_SIZE +
3401 1.1 augustss USB_INTERFACE_DESCRIPTOR_SIZE +
3402 1.1 augustss USB_ENDPOINT_DESCRIPTOR_SIZE},
3403 1.1 augustss 1,
3404 1.1 augustss 1,
3405 1.1 augustss 0,
3406 1.206 drochner UC_ATTR_MBO | UC_SELF_POWERED,
3407 1.1 augustss 0 /* max power */
3408 1.1 augustss };
3409 1.1 augustss
3410 1.208 drochner const usb_interface_descriptor_t uhci_ifcd = {
3411 1.1 augustss USB_INTERFACE_DESCRIPTOR_SIZE,
3412 1.1 augustss UDESC_INTERFACE,
3413 1.1 augustss 0,
3414 1.1 augustss 0,
3415 1.1 augustss 1,
3416 1.87 augustss UICLASS_HUB,
3417 1.87 augustss UISUBCLASS_HUB,
3418 1.144 augustss UIPROTO_FSHUB,
3419 1.1 augustss 0
3420 1.1 augustss };
3421 1.1 augustss
3422 1.208 drochner const usb_endpoint_descriptor_t uhci_endpd = {
3423 1.1 augustss USB_ENDPOINT_DESCRIPTOR_SIZE,
3424 1.1 augustss UDESC_ENDPOINT,
3425 1.45 augustss UE_DIR_IN | UHCI_INTR_ENDPT,
3426 1.1 augustss UE_INTERRUPT,
3427 1.1 augustss {8},
3428 1.1 augustss 255
3429 1.1 augustss };
3430 1.1 augustss
3431 1.208 drochner const usb_hub_descriptor_t uhci_hubd_piix = {
3432 1.1 augustss USB_HUB_DESCRIPTOR_SIZE,
3433 1.1 augustss UDESC_HUB,
3434 1.1 augustss 2,
3435 1.1 augustss { UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0 },
3436 1.1 augustss 50, /* power on to power good */
3437 1.1 augustss 0,
3438 1.1 augustss { 0x00 }, /* both ports are removable */
3439 1.199 christos { 0 },
3440 1.1 augustss };
3441 1.1 augustss
3442 1.1 augustss /*
3443 1.166 dsainty * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also
3444 1.166 dsainty * enables the port, and also states that SET_FEATURE(PORT_ENABLE)
3445 1.166 dsainty * should not be used by the USB subsystem. As we cannot issue a
3446 1.166 dsainty * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port
3447 1.166 dsainty * will be enabled as part of the reset.
3448 1.166 dsainty *
3449 1.166 dsainty * On the VT83C572, the port cannot be successfully enabled until the
3450 1.166 dsainty * outstanding "port enable change" and "connection status change"
3451 1.166 dsainty * events have been reset.
3452 1.166 dsainty */
3453 1.166 dsainty Static usbd_status
3454 1.166 dsainty uhci_portreset(uhci_softc_t *sc, int index)
3455 1.166 dsainty {
3456 1.166 dsainty int lim, port, x;
3457 1.166 dsainty
3458 1.166 dsainty if (index == 1)
3459 1.166 dsainty port = UHCI_PORTSC1;
3460 1.166 dsainty else if (index == 2)
3461 1.166 dsainty port = UHCI_PORTSC2;
3462 1.166 dsainty else
3463 1.166 dsainty return (USBD_IOERROR);
3464 1.166 dsainty
3465 1.166 dsainty x = URWMASK(UREAD2(sc, port));
3466 1.166 dsainty UWRITE2(sc, port, x | UHCI_PORTSC_PR);
3467 1.166 dsainty
3468 1.166 dsainty usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY);
3469 1.166 dsainty
3470 1.166 dsainty DPRINTFN(3,("uhci port %d reset, status0 = 0x%04x\n",
3471 1.166 dsainty index, UREAD2(sc, port)));
3472 1.166 dsainty
3473 1.166 dsainty x = URWMASK(UREAD2(sc, port));
3474 1.222 drochner UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP));
3475 1.166 dsainty
3476 1.166 dsainty delay(100);
3477 1.166 dsainty
3478 1.166 dsainty DPRINTFN(3,("uhci port %d reset, status1 = 0x%04x\n",
3479 1.166 dsainty index, UREAD2(sc, port)));
3480 1.166 dsainty
3481 1.166 dsainty x = URWMASK(UREAD2(sc, port));
3482 1.166 dsainty UWRITE2(sc, port, x | UHCI_PORTSC_PE);
3483 1.166 dsainty
3484 1.166 dsainty for (lim = 10; --lim > 0;) {
3485 1.166 dsainty usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY);
3486 1.166 dsainty
3487 1.166 dsainty x = UREAD2(sc, port);
3488 1.166 dsainty
3489 1.166 dsainty DPRINTFN(3,("uhci port %d iteration %u, status = 0x%04x\n",
3490 1.166 dsainty index, lim, x));
3491 1.166 dsainty
3492 1.166 dsainty if (!(x & UHCI_PORTSC_CCS)) {
3493 1.166 dsainty /*
3494 1.166 dsainty * No device is connected (or was disconnected
3495 1.166 dsainty * during reset). Consider the port reset.
3496 1.166 dsainty * The delay must be long enough to ensure on
3497 1.166 dsainty * the initial iteration that the device
3498 1.166 dsainty * connection will have been registered. 50ms
3499 1.166 dsainty * appears to be sufficient, but 20ms is not.
3500 1.166 dsainty */
3501 1.166 dsainty DPRINTFN(3,("uhci port %d loop %u, device detached\n",
3502 1.166 dsainty index, lim));
3503 1.166 dsainty break;
3504 1.166 dsainty }
3505 1.166 dsainty
3506 1.166 dsainty if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) {
3507 1.166 dsainty /*
3508 1.166 dsainty * Port enabled changed and/or connection
3509 1.166 dsainty * status changed were set. Reset either or
3510 1.166 dsainty * both raised flags (by writing a 1 to that
3511 1.166 dsainty * bit), and wait again for state to settle.
3512 1.166 dsainty */
3513 1.166 dsainty UWRITE2(sc, port, URWMASK(x) |
3514 1.166 dsainty (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)));
3515 1.166 dsainty continue;
3516 1.166 dsainty }
3517 1.166 dsainty
3518 1.166 dsainty if (x & UHCI_PORTSC_PE)
3519 1.166 dsainty /* Port is enabled */
3520 1.166 dsainty break;
3521 1.166 dsainty
3522 1.166 dsainty UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE);
3523 1.166 dsainty }
3524 1.166 dsainty
3525 1.166 dsainty DPRINTFN(3,("uhci port %d reset, status2 = 0x%04x\n",
3526 1.166 dsainty index, UREAD2(sc, port)));
3527 1.166 dsainty
3528 1.166 dsainty if (lim <= 0) {
3529 1.166 dsainty DPRINTFN(1,("uhci port %d reset timed out\n", index));
3530 1.166 dsainty return (USBD_TIMEOUT);
3531 1.166 dsainty }
3532 1.184 perry
3533 1.166 dsainty sc->sc_isreset = 1;
3534 1.166 dsainty return (USBD_NORMAL_COMPLETION);
3535 1.166 dsainty }
3536 1.166 dsainty
3537 1.166 dsainty /*
3538 1.1 augustss * Simulate a hardware hub by handling all the necessary requests.
3539 1.1 augustss */
3540 1.1 augustss usbd_status
3541 1.119 augustss uhci_root_ctrl_transfer(usbd_xfer_handle xfer)
3542 1.1 augustss {
3543 1.248 mrg uhci_softc_t *sc = xfer->pipe->device->bus->hci_private;
3544 1.63 augustss usbd_status err;
3545 1.16 augustss
3546 1.52 augustss /* Insert last in queue. */
3547 1.248 mrg mutex_enter(&sc->sc_lock);
3548 1.63 augustss err = usb_insert_transfer(xfer);
3549 1.248 mrg mutex_exit(&sc->sc_lock);
3550 1.63 augustss if (err)
3551 1.63 augustss return (err);
3552 1.52 augustss
3553 1.152 augustss /*
3554 1.94 augustss * Pipe isn't running (otherwise err would be USBD_INPROG),
3555 1.94 augustss * so start it first.
3556 1.67 augustss */
3557 1.63 augustss return (uhci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
3558 1.16 augustss }
3559 1.16 augustss
3560 1.16 augustss usbd_status
3561 1.119 augustss uhci_root_ctrl_start(usbd_xfer_handle xfer)
3562 1.16 augustss {
3563 1.216 drochner uhci_softc_t *sc = xfer->pipe->device->bus->hci_private;
3564 1.1 augustss usb_device_request_t *req;
3565 1.59 augustss void *buf = NULL;
3566 1.1 augustss int port, x;
3567 1.248 mrg int len, value, index, status, change, l, totlen = 0;
3568 1.1 augustss usb_port_status_t ps;
3569 1.63 augustss usbd_status err;
3570 1.1 augustss
3571 1.82 augustss if (sc->sc_dying)
3572 1.82 augustss return (USBD_IOERROR);
3573 1.82 augustss
3574 1.48 augustss #ifdef DIAGNOSTIC
3575 1.63 augustss if (!(xfer->rqflags & URQ_REQUEST))
3576 1.248 mrg panic("uhci_root_ctrl_start: not a request");
3577 1.48 augustss #endif
3578 1.63 augustss req = &xfer->request;
3579 1.1 augustss
3580 1.152 augustss DPRINTFN(2,("uhci_root_ctrl_control type=0x%02x request=%02x\n",
3581 1.1 augustss req->bmRequestType, req->bRequest));
3582 1.1 augustss
3583 1.1 augustss len = UGETW(req->wLength);
3584 1.1 augustss value = UGETW(req->wValue);
3585 1.1 augustss index = UGETW(req->wIndex);
3586 1.49 augustss
3587 1.49 augustss if (len != 0)
3588 1.159 augustss buf = KERNADDR(&xfer->dmabuf, 0);
3589 1.49 augustss
3590 1.1 augustss #define C(x,y) ((x) | ((y) << 8))
3591 1.1 augustss switch(C(req->bRequest, req->bmRequestType)) {
3592 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3593 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3594 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3595 1.152 augustss /*
3596 1.13 augustss * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3597 1.1 augustss * for the integrated root hub.
3598 1.1 augustss */
3599 1.1 augustss break;
3600 1.1 augustss case C(UR_GET_CONFIG, UT_READ_DEVICE):
3601 1.1 augustss if (len > 0) {
3602 1.264.4.1 skrll *(uint8_t *)buf = sc->sc_conf;
3603 1.1 augustss totlen = 1;
3604 1.1 augustss }
3605 1.1 augustss break;
3606 1.1 augustss case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3607 1.1 augustss DPRINTFN(2,("uhci_root_ctrl_control wValue=0x%04x\n", value));
3608 1.195 christos if (len == 0)
3609 1.195 christos break;
3610 1.1 augustss switch(value >> 8) {
3611 1.1 augustss case UDESC_DEVICE:
3612 1.1 augustss if ((value & 0xff) != 0) {
3613 1.63 augustss err = USBD_IOERROR;
3614 1.1 augustss goto ret;
3615 1.1 augustss }
3616 1.1 augustss totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE);
3617 1.27 augustss USETW(uhci_devd.idVendor, sc->sc_id_vendor);
3618 1.1 augustss memcpy(buf, &uhci_devd, l);
3619 1.1 augustss break;
3620 1.1 augustss case UDESC_CONFIG:
3621 1.1 augustss if ((value & 0xff) != 0) {
3622 1.63 augustss err = USBD_IOERROR;
3623 1.1 augustss goto ret;
3624 1.1 augustss }
3625 1.1 augustss totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE);
3626 1.1 augustss memcpy(buf, &uhci_confd, l);
3627 1.1 augustss buf = (char *)buf + l;
3628 1.1 augustss len -= l;
3629 1.1 augustss l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE);
3630 1.1 augustss totlen += l;
3631 1.1 augustss memcpy(buf, &uhci_ifcd, l);
3632 1.1 augustss buf = (char *)buf + l;
3633 1.1 augustss len -= l;
3634 1.1 augustss l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE);
3635 1.1 augustss totlen += l;
3636 1.1 augustss memcpy(buf, &uhci_endpd, l);
3637 1.1 augustss break;
3638 1.1 augustss case UDESC_STRING:
3639 1.213 drochner #define sd ((usb_string_descriptor_t *)buf)
3640 1.1 augustss switch (value & 0xff) {
3641 1.182 augustss case 0: /* Language table */
3642 1.213 drochner totlen = usb_makelangtbl(sd, len);
3643 1.182 augustss break;
3644 1.1 augustss case 1: /* Vendor */
3645 1.213 drochner totlen = usb_makestrdesc(sd, len,
3646 1.213 drochner sc->sc_vendor);
3647 1.1 augustss break;
3648 1.1 augustss case 2: /* Product */
3649 1.213 drochner totlen = usb_makestrdesc(sd, len,
3650 1.213 drochner "UHCI root hub");
3651 1.1 augustss break;
3652 1.1 augustss }
3653 1.213 drochner #undef sd
3654 1.1 augustss break;
3655 1.1 augustss default:
3656 1.63 augustss err = USBD_IOERROR;
3657 1.1 augustss goto ret;
3658 1.1 augustss }
3659 1.1 augustss break;
3660 1.1 augustss case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3661 1.1 augustss if (len > 0) {
3662 1.264.4.1 skrll *(uint8_t *)buf = 0;
3663 1.1 augustss totlen = 1;
3664 1.1 augustss }
3665 1.1 augustss break;
3666 1.1 augustss case C(UR_GET_STATUS, UT_READ_DEVICE):
3667 1.1 augustss if (len > 1) {
3668 1.1 augustss USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED);
3669 1.1 augustss totlen = 2;
3670 1.1 augustss }
3671 1.1 augustss break;
3672 1.1 augustss case C(UR_GET_STATUS, UT_READ_INTERFACE):
3673 1.1 augustss case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3674 1.1 augustss if (len > 1) {
3675 1.1 augustss USETW(((usb_status_t *)buf)->wStatus, 0);
3676 1.1 augustss totlen = 2;
3677 1.1 augustss }
3678 1.1 augustss break;
3679 1.1 augustss case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3680 1.1 augustss if (value >= USB_MAX_DEVICES) {
3681 1.63 augustss err = USBD_IOERROR;
3682 1.1 augustss goto ret;
3683 1.1 augustss }
3684 1.1 augustss sc->sc_addr = value;
3685 1.1 augustss break;
3686 1.1 augustss case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3687 1.1 augustss if (value != 0 && value != 1) {
3688 1.63 augustss err = USBD_IOERROR;
3689 1.1 augustss goto ret;
3690 1.1 augustss }
3691 1.1 augustss sc->sc_conf = value;
3692 1.1 augustss break;
3693 1.1 augustss case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3694 1.1 augustss break;
3695 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3696 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3697 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3698 1.63 augustss err = USBD_IOERROR;
3699 1.1 augustss goto ret;
3700 1.1 augustss case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3701 1.1 augustss break;
3702 1.1 augustss case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3703 1.1 augustss break;
3704 1.1 augustss /* Hub requests */
3705 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3706 1.1 augustss break;
3707 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3708 1.12 augustss DPRINTFN(3, ("uhci_root_ctrl_control: UR_CLEAR_PORT_FEATURE "
3709 1.12 augustss "port=%d feature=%d\n",
3710 1.1 augustss index, value));
3711 1.1 augustss if (index == 1)
3712 1.1 augustss port = UHCI_PORTSC1;
3713 1.1 augustss else if (index == 2)
3714 1.1 augustss port = UHCI_PORTSC2;
3715 1.1 augustss else {
3716 1.63 augustss err = USBD_IOERROR;
3717 1.1 augustss goto ret;
3718 1.1 augustss }
3719 1.1 augustss switch(value) {
3720 1.1 augustss case UHF_PORT_ENABLE:
3721 1.137 augustss x = URWMASK(UREAD2(sc, port));
3722 1.1 augustss UWRITE2(sc, port, x & ~UHCI_PORTSC_PE);
3723 1.1 augustss break;
3724 1.1 augustss case UHF_PORT_SUSPEND:
3725 1.137 augustss x = URWMASK(UREAD2(sc, port));
3726 1.222 drochner if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */
3727 1.222 drochner break;
3728 1.222 drochner UWRITE2(sc, port, x | UHCI_PORTSC_RD);
3729 1.222 drochner /* see USB2 spec ch. 7.1.7.7 */
3730 1.222 drochner usb_delay_ms(&sc->sc_bus, 20);
3731 1.1 augustss UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP);
3732 1.222 drochner /* 10ms resume delay must be provided by caller */
3733 1.1 augustss break;
3734 1.1 augustss case UHF_PORT_RESET:
3735 1.137 augustss x = URWMASK(UREAD2(sc, port));
3736 1.1 augustss UWRITE2(sc, port, x & ~UHCI_PORTSC_PR);
3737 1.1 augustss break;
3738 1.1 augustss case UHF_C_PORT_CONNECTION:
3739 1.137 augustss x = URWMASK(UREAD2(sc, port));
3740 1.1 augustss UWRITE2(sc, port, x | UHCI_PORTSC_CSC);
3741 1.1 augustss break;
3742 1.1 augustss case UHF_C_PORT_ENABLE:
3743 1.137 augustss x = URWMASK(UREAD2(sc, port));
3744 1.1 augustss UWRITE2(sc, port, x | UHCI_PORTSC_POEDC);
3745 1.1 augustss break;
3746 1.1 augustss case UHF_C_PORT_OVER_CURRENT:
3747 1.137 augustss x = URWMASK(UREAD2(sc, port));
3748 1.1 augustss UWRITE2(sc, port, x | UHCI_PORTSC_OCIC);
3749 1.1 augustss break;
3750 1.1 augustss case UHF_C_PORT_RESET:
3751 1.1 augustss sc->sc_isreset = 0;
3752 1.63 augustss err = USBD_NORMAL_COMPLETION;
3753 1.1 augustss goto ret;
3754 1.1 augustss case UHF_PORT_CONNECTION:
3755 1.1 augustss case UHF_PORT_OVER_CURRENT:
3756 1.1 augustss case UHF_PORT_POWER:
3757 1.1 augustss case UHF_PORT_LOW_SPEED:
3758 1.1 augustss case UHF_C_PORT_SUSPEND:
3759 1.1 augustss default:
3760 1.63 augustss err = USBD_IOERROR;
3761 1.1 augustss goto ret;
3762 1.1 augustss }
3763 1.1 augustss break;
3764 1.1 augustss case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER):
3765 1.1 augustss if (index == 1)
3766 1.1 augustss port = UHCI_PORTSC1;
3767 1.1 augustss else if (index == 2)
3768 1.1 augustss port = UHCI_PORTSC2;
3769 1.1 augustss else {
3770 1.63 augustss err = USBD_IOERROR;
3771 1.1 augustss goto ret;
3772 1.1 augustss }
3773 1.1 augustss if (len > 0) {
3774 1.264.4.1 skrll *(uint8_t *)buf =
3775 1.1 augustss (UREAD2(sc, port) & UHCI_PORTSC_LS) >>
3776 1.1 augustss UHCI_PORTSC_LS_SHIFT;
3777 1.1 augustss totlen = 1;
3778 1.1 augustss }
3779 1.1 augustss break;
3780 1.1 augustss case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3781 1.195 christos if (len == 0)
3782 1.195 christos break;
3783 1.177 toshii if ((value & 0xff) != 0) {
3784 1.63 augustss err = USBD_IOERROR;
3785 1.1 augustss goto ret;
3786 1.1 augustss }
3787 1.1 augustss l = min(len, USB_HUB_DESCRIPTOR_SIZE);
3788 1.1 augustss totlen = l;
3789 1.1 augustss memcpy(buf, &uhci_hubd_piix, l);
3790 1.1 augustss break;
3791 1.1 augustss case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3792 1.1 augustss if (len != 4) {
3793 1.63 augustss err = USBD_IOERROR;
3794 1.1 augustss goto ret;
3795 1.1 augustss }
3796 1.1 augustss memset(buf, 0, len);
3797 1.1 augustss totlen = len;
3798 1.1 augustss break;
3799 1.1 augustss case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3800 1.1 augustss if (index == 1)
3801 1.1 augustss port = UHCI_PORTSC1;
3802 1.1 augustss else if (index == 2)
3803 1.1 augustss port = UHCI_PORTSC2;
3804 1.1 augustss else {
3805 1.63 augustss err = USBD_IOERROR;
3806 1.1 augustss goto ret;
3807 1.1 augustss }
3808 1.1 augustss if (len != 4) {
3809 1.63 augustss err = USBD_IOERROR;
3810 1.1 augustss goto ret;
3811 1.1 augustss }
3812 1.1 augustss x = UREAD2(sc, port);
3813 1.1 augustss status = change = 0;
3814 1.142 augustss if (x & UHCI_PORTSC_CCS)
3815 1.1 augustss status |= UPS_CURRENT_CONNECT_STATUS;
3816 1.152 augustss if (x & UHCI_PORTSC_CSC)
3817 1.1 augustss change |= UPS_C_CONNECT_STATUS;
3818 1.152 augustss if (x & UHCI_PORTSC_PE)
3819 1.1 augustss status |= UPS_PORT_ENABLED;
3820 1.152 augustss if (x & UHCI_PORTSC_POEDC)
3821 1.1 augustss change |= UPS_C_PORT_ENABLED;
3822 1.152 augustss if (x & UHCI_PORTSC_OCI)
3823 1.1 augustss status |= UPS_OVERCURRENT_INDICATOR;
3824 1.152 augustss if (x & UHCI_PORTSC_OCIC)
3825 1.1 augustss change |= UPS_C_OVERCURRENT_INDICATOR;
3826 1.152 augustss if (x & UHCI_PORTSC_SUSP)
3827 1.1 augustss status |= UPS_SUSPEND;
3828 1.152 augustss if (x & UHCI_PORTSC_LSDA)
3829 1.1 augustss status |= UPS_LOW_SPEED;
3830 1.1 augustss status |= UPS_PORT_POWER;
3831 1.1 augustss if (sc->sc_isreset)
3832 1.1 augustss change |= UPS_C_PORT_RESET;
3833 1.1 augustss USETW(ps.wPortStatus, status);
3834 1.1 augustss USETW(ps.wPortChange, change);
3835 1.1 augustss l = min(len, sizeof ps);
3836 1.1 augustss memcpy(buf, &ps, l);
3837 1.1 augustss totlen = l;
3838 1.1 augustss break;
3839 1.1 augustss case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3840 1.63 augustss err = USBD_IOERROR;
3841 1.1 augustss goto ret;
3842 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3843 1.1 augustss break;
3844 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3845 1.1 augustss if (index == 1)
3846 1.1 augustss port = UHCI_PORTSC1;
3847 1.1 augustss else if (index == 2)
3848 1.1 augustss port = UHCI_PORTSC2;
3849 1.1 augustss else {
3850 1.63 augustss err = USBD_IOERROR;
3851 1.1 augustss goto ret;
3852 1.1 augustss }
3853 1.1 augustss switch(value) {
3854 1.1 augustss case UHF_PORT_ENABLE:
3855 1.137 augustss x = URWMASK(UREAD2(sc, port));
3856 1.1 augustss UWRITE2(sc, port, x | UHCI_PORTSC_PE);
3857 1.1 augustss break;
3858 1.1 augustss case UHF_PORT_SUSPEND:
3859 1.137 augustss x = URWMASK(UREAD2(sc, port));
3860 1.1 augustss UWRITE2(sc, port, x | UHCI_PORTSC_SUSP);
3861 1.1 augustss break;
3862 1.1 augustss case UHF_PORT_RESET:
3863 1.166 dsainty err = uhci_portreset(sc, index);
3864 1.166 dsainty goto ret;
3865 1.111 augustss case UHF_PORT_POWER:
3866 1.111 augustss /* Pretend we turned on power */
3867 1.115 mycroft err = USBD_NORMAL_COMPLETION;
3868 1.111 augustss goto ret;
3869 1.1 augustss case UHF_C_PORT_CONNECTION:
3870 1.1 augustss case UHF_C_PORT_ENABLE:
3871 1.1 augustss case UHF_C_PORT_OVER_CURRENT:
3872 1.1 augustss case UHF_PORT_CONNECTION:
3873 1.1 augustss case UHF_PORT_OVER_CURRENT:
3874 1.1 augustss case UHF_PORT_LOW_SPEED:
3875 1.1 augustss case UHF_C_PORT_SUSPEND:
3876 1.1 augustss case UHF_C_PORT_RESET:
3877 1.1 augustss default:
3878 1.63 augustss err = USBD_IOERROR;
3879 1.1 augustss goto ret;
3880 1.1 augustss }
3881 1.1 augustss break;
3882 1.1 augustss default:
3883 1.63 augustss err = USBD_IOERROR;
3884 1.1 augustss goto ret;
3885 1.1 augustss }
3886 1.63 augustss xfer->actlen = totlen;
3887 1.63 augustss err = USBD_NORMAL_COMPLETION;
3888 1.1 augustss ret:
3889 1.63 augustss xfer->status = err;
3890 1.248 mrg mutex_enter(&sc->sc_lock);
3891 1.63 augustss usb_transfer_complete(xfer);
3892 1.248 mrg mutex_exit(&sc->sc_lock);
3893 1.1 augustss return (USBD_IN_PROGRESS);
3894 1.1 augustss }
3895 1.1 augustss
3896 1.1 augustss /* Abort a root control request. */
3897 1.1 augustss void
3898 1.205 christos uhci_root_ctrl_abort(usbd_xfer_handle xfer)
3899 1.1 augustss {
3900 1.70 augustss /* Nothing to do, all transfers are synchronous. */
3901 1.1 augustss }
3902 1.1 augustss
3903 1.1 augustss /* Close the root pipe. */
3904 1.1 augustss void
3905 1.205 christos uhci_root_ctrl_close(usbd_pipe_handle pipe)
3906 1.1 augustss {
3907 1.1 augustss DPRINTF(("uhci_root_ctrl_close\n"));
3908 1.1 augustss }
3909 1.1 augustss
3910 1.1 augustss /* Abort a root interrupt request. */
3911 1.1 augustss void
3912 1.119 augustss uhci_root_intr_abort(usbd_xfer_handle xfer)
3913 1.1 augustss {
3914 1.216 drochner uhci_softc_t *sc = xfer->pipe->device->bus->hci_private;
3915 1.30 augustss
3916 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
3917 1.264 skrll KASSERT(xfer->pipe->intrxfer == xfer);
3918 1.248 mrg
3919 1.234 dyoung callout_stop(&sc->sc_poll_handle);
3920 1.96 augustss sc->sc_intr_xfer = NULL;
3921 1.58 augustss
3922 1.63 augustss xfer->status = USBD_CANCELLED;
3923 1.96 augustss #ifdef DIAGNOSTIC
3924 1.96 augustss UXFER(xfer)->iinfo.isdone = 1;
3925 1.96 augustss #endif
3926 1.63 augustss usb_transfer_complete(xfer);
3927 1.1 augustss }
3928 1.1 augustss
3929 1.16 augustss usbd_status
3930 1.119 augustss uhci_root_intr_transfer(usbd_xfer_handle xfer)
3931 1.16 augustss {
3932 1.248 mrg uhci_softc_t *sc = xfer->pipe->device->bus->hci_private;
3933 1.63 augustss usbd_status err;
3934 1.16 augustss
3935 1.52 augustss /* Insert last in queue. */
3936 1.248 mrg mutex_enter(&sc->sc_lock);
3937 1.63 augustss err = usb_insert_transfer(xfer);
3938 1.248 mrg mutex_exit(&sc->sc_lock);
3939 1.63 augustss if (err)
3940 1.63 augustss return (err);
3941 1.52 augustss
3942 1.186 skrll /*
3943 1.186 skrll * Pipe isn't running (otherwise err would be USBD_INPROG),
3944 1.67 augustss * start first
3945 1.67 augustss */
3946 1.63 augustss return (uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
3947 1.16 augustss }
3948 1.16 augustss
3949 1.1 augustss /* Start a transfer on the root interrupt pipe */
3950 1.1 augustss usbd_status
3951 1.119 augustss uhci_root_intr_start(usbd_xfer_handle xfer)
3952 1.1 augustss {
3953 1.63 augustss usbd_pipe_handle pipe = xfer->pipe;
3954 1.216 drochner uhci_softc_t *sc = pipe->device->bus->hci_private;
3955 1.174 drochner unsigned int ival;
3956 1.1 augustss
3957 1.173 gson DPRINTFN(3, ("uhci_root_intr_start: xfer=%p len=%d flags=%d\n",
3958 1.63 augustss xfer, xfer->length, xfer->flags));
3959 1.82 augustss
3960 1.82 augustss if (sc->sc_dying)
3961 1.82 augustss return (USBD_IOERROR);
3962 1.1 augustss
3963 1.174 drochner /* XXX temporary variable needed to avoid gcc3 warning */
3964 1.174 drochner ival = xfer->pipe->endpoint->edesc->bInterval;
3965 1.174 drochner sc->sc_ival = mstohz(ival);
3966 1.234 dyoung callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer);
3967 1.96 augustss sc->sc_intr_xfer = xfer;
3968 1.1 augustss return (USBD_IN_PROGRESS);
3969 1.1 augustss }
3970 1.1 augustss
3971 1.1 augustss /* Close the root interrupt pipe. */
3972 1.1 augustss void
3973 1.119 augustss uhci_root_intr_close(usbd_pipe_handle pipe)
3974 1.1 augustss {
3975 1.216 drochner uhci_softc_t *sc = pipe->device->bus->hci_private;
3976 1.30 augustss
3977 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
3978 1.248 mrg
3979 1.234 dyoung callout_stop(&sc->sc_poll_handle);
3980 1.96 augustss sc->sc_intr_xfer = NULL;
3981 1.1 augustss DPRINTF(("uhci_root_intr_close\n"));
3982 1.1 augustss }
3983