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uhci.c revision 1.264.4.54
      1  1.264.4.54     skrll /*	$NetBSD: uhci.c,v 1.264.4.54 2015/11/09 08:35:23 skrll Exp $	*/
      2         1.1  augustss 
      3         1.1  augustss /*
      4       1.248       mrg  * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc.
      5         1.1  augustss  * All rights reserved.
      6         1.1  augustss  *
      7        1.11  augustss  * This code is derived from software contributed to The NetBSD Foundation
      8       1.113  augustss  * by Lennart Augustsson (lennart (at) augustsson.net) at
      9       1.248       mrg  * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca)
     10       1.248       mrg  * and Matthew R. Green (mrg (at) eterna.com.au).
     11         1.1  augustss  *
     12         1.1  augustss  * Redistribution and use in source and binary forms, with or without
     13         1.1  augustss  * modification, are permitted provided that the following conditions
     14         1.1  augustss  * are met:
     15         1.1  augustss  * 1. Redistributions of source code must retain the above copyright
     16         1.1  augustss  *    notice, this list of conditions and the following disclaimer.
     17         1.1  augustss  * 2. Redistributions in binary form must reproduce the above copyright
     18         1.1  augustss  *    notice, this list of conditions and the following disclaimer in the
     19         1.1  augustss  *    documentation and/or other materials provided with the distribution.
     20         1.1  augustss  *
     21         1.1  augustss  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     22         1.1  augustss  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     23         1.1  augustss  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     24         1.1  augustss  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     25         1.1  augustss  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     26         1.1  augustss  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     27         1.1  augustss  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     28         1.1  augustss  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     29         1.1  augustss  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     30         1.1  augustss  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     31         1.1  augustss  * POSSIBILITY OF SUCH DAMAGE.
     32         1.1  augustss  */
     33         1.1  augustss 
     34         1.1  augustss /*
     35         1.1  augustss  * USB Universal Host Controller driver.
     36        1.28  augustss  * Handles e.g. PIIX3 and PIIX4.
     37         1.1  augustss  *
     38       1.229  uebayasi  * UHCI spec: http://www.intel.com/technology/usb/spec.htm
     39       1.229  uebayasi  * USB spec: http://www.usb.org/developers/docs/
     40        1.71  augustss  * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf
     41        1.71  augustss  *             ftp://download.intel.com/design/intarch/datashts/29056201.pdf
     42         1.1  augustss  */
     43       1.143     lukem 
     44       1.143     lukem #include <sys/cdefs.h>
     45  1.264.4.54     skrll __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.264.4.54 2015/11/09 08:35:23 skrll Exp $");
     46  1.264.4.30     skrll 
     47  1.264.4.30     skrll #include "opt_usb.h"
     48         1.1  augustss 
     49         1.1  augustss #include <sys/param.h>
     50  1.264.4.20     skrll 
     51  1.264.4.20     skrll #include <sys/bus.h>
     52  1.264.4.20     skrll #include <sys/cpu.h>
     53  1.264.4.20     skrll #include <sys/device.h>
     54         1.1  augustss #include <sys/kernel.h>
     55       1.248       mrg #include <sys/kmem.h>
     56  1.264.4.20     skrll #include <sys/mutex.h>
     57         1.1  augustss #include <sys/proc.h>
     58         1.1  augustss #include <sys/queue.h>
     59  1.264.4.20     skrll #include <sys/select.h>
     60  1.264.4.20     skrll #include <sys/sysctl.h>
     61  1.264.4.20     skrll #include <sys/systm.h>
     62         1.1  augustss 
     63        1.39  augustss #include <machine/endian.h>
     64         1.7  augustss 
     65         1.1  augustss #include <dev/usb/usb.h>
     66         1.1  augustss #include <dev/usb/usbdi.h>
     67         1.1  augustss #include <dev/usb/usbdivar.h>
     68         1.7  augustss #include <dev/usb/usb_mem.h>
     69         1.1  augustss 
     70         1.1  augustss #include <dev/usb/uhcireg.h>
     71         1.1  augustss #include <dev/usb/uhcivar.h>
     72  1.264.4.11     skrll #include <dev/usb/usbroothub.h>
     73  1.264.4.21     skrll #include <dev/usb/usbhist.h>
     74         1.1  augustss 
     75       1.125  augustss /* Use bandwidth reclamation for control transfers. Some devices choke on it. */
     76       1.125  augustss /*#define UHCI_CTL_LOOP */
     77       1.125  augustss 
     78        1.67  augustss #ifdef UHCI_DEBUG
     79        1.92  augustss uhci_softc_t *thesc;
     80       1.125  augustss int uhcinoloop = 0;
     81        1.59  augustss #endif
     82        1.59  augustss 
     83  1.264.4.21     skrll #ifdef USB_DEBUG
     84  1.264.4.21     skrll #ifndef UHCI_DEBUG
     85  1.264.4.21     skrll #define uhcidebug 0
     86  1.264.4.21     skrll #else
     87  1.264.4.21     skrll static int uhcidebug = 0;
     88  1.264.4.21     skrll 
     89  1.264.4.21     skrll SYSCTL_SETUP(sysctl_hw_uhci_setup, "sysctl hw.uhci setup")
     90  1.264.4.21     skrll {
     91  1.264.4.21     skrll 	int err;
     92  1.264.4.21     skrll 	const struct sysctlnode *rnode;
     93  1.264.4.21     skrll 	const struct sysctlnode *cnode;
     94  1.264.4.21     skrll 
     95  1.264.4.21     skrll 	err = sysctl_createv(clog, 0, NULL, &rnode,
     96  1.264.4.21     skrll 	    CTLFLAG_PERMANENT, CTLTYPE_NODE, "uhci",
     97  1.264.4.21     skrll 	    SYSCTL_DESCR("uhci global controls"),
     98  1.264.4.21     skrll 	    NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
     99  1.264.4.21     skrll 
    100  1.264.4.21     skrll 	if (err)
    101  1.264.4.21     skrll 		goto fail;
    102  1.264.4.21     skrll 
    103  1.264.4.21     skrll 	/* control debugging printfs */
    104  1.264.4.21     skrll 	err = sysctl_createv(clog, 0, &rnode, &cnode,
    105  1.264.4.21     skrll 	    CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
    106  1.264.4.21     skrll 	    "debug", SYSCTL_DESCR("Enable debugging output"),
    107  1.264.4.21     skrll 	    NULL, 0, &uhcidebug, sizeof(uhcidebug), CTL_CREATE, CTL_EOL);
    108  1.264.4.21     skrll 	if (err)
    109  1.264.4.21     skrll 		goto fail;
    110  1.264.4.21     skrll 
    111  1.264.4.21     skrll 	return;
    112  1.264.4.21     skrll fail:
    113  1.264.4.21     skrll 	aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err);
    114  1.264.4.21     skrll }
    115  1.264.4.21     skrll 
    116  1.264.4.21     skrll #endif /* UHCI_DEBUG */
    117  1.264.4.21     skrll #endif /* USB_DEBUG */
    118  1.264.4.21     skrll 
    119  1.264.4.27     skrll #define	DPRINTF(FMT,A,B,C,D)	USBHIST_LOGN(uhcidebug,1,FMT,A,B,C,D)
    120  1.264.4.21     skrll #define	DPRINTFN(N,FMT,A,B,C,D)	USBHIST_LOGN(uhcidebug,N,FMT,A,B,C,D)
    121  1.264.4.21     skrll #define	UHCIHIST_FUNC()		USBHIST_FUNC()
    122  1.264.4.21     skrll #define	UHCIHIST_CALLED(name)	USBHIST_CALLED(uhcidebug)
    123  1.264.4.21     skrll 
    124        1.39  augustss /*
    125        1.39  augustss  * The UHCI controller is little endian, so on big endian machines
    126       1.181  drochner  * the data stored in memory needs to be swapped.
    127        1.39  augustss  */
    128        1.39  augustss 
    129         1.1  augustss struct uhci_pipe {
    130         1.1  augustss 	struct usbd_pipe pipe;
    131        1.32  augustss 	int nexttoggle;
    132        1.92  augustss 
    133        1.92  augustss 	u_char aborting;
    134  1.264.4.25     skrll 	struct usbd_xfer *abortstart, abortend;
    135        1.92  augustss 
    136         1.1  augustss 	/* Info needed for different pipe kinds. */
    137         1.1  augustss 	union {
    138         1.1  augustss 		/* Control pipe */
    139         1.1  augustss 		struct {
    140         1.1  augustss 			uhci_soft_qh_t *sqh;
    141         1.7  augustss 			usb_dma_t reqdma;
    142        1.16  augustss 			uhci_soft_td_t *setup, *stat;
    143         1.1  augustss 			u_int length;
    144  1.264.4.33     skrll 		} ctrl;
    145         1.1  augustss 		/* Interrupt pipe */
    146         1.1  augustss 		struct {
    147         1.1  augustss 			int npoll;
    148       1.187     skrll 			int isread;
    149         1.1  augustss 			uhci_soft_qh_t **qhs;
    150         1.1  augustss 		} intr;
    151         1.1  augustss 		/* Bulk pipe */
    152         1.1  augustss 		struct {
    153         1.1  augustss 			uhci_soft_qh_t *sqh;
    154         1.1  augustss 			u_int length;
    155         1.1  augustss 			int isread;
    156         1.1  augustss 		} bulk;
    157  1.264.4.33     skrll 		/* Isochronous pipe */
    158  1.264.4.33     skrll 		struct isoc {
    159        1.16  augustss 			uhci_soft_td_t **stds;
    160        1.48  augustss 			int next, inuse;
    161  1.264.4.33     skrll 		} isoc;
    162  1.264.4.33     skrll 	};
    163         1.1  augustss };
    164         1.1  augustss 
    165       1.142  augustss Static void		uhci_globalreset(uhci_softc_t *);
    166       1.166   dsainty Static usbd_status	uhci_portreset(uhci_softc_t*, int);
    167       1.142  augustss Static void		uhci_reset(uhci_softc_t *);
    168  1.264.4.15     skrll Static usbd_status	uhci_run(uhci_softc_t *, int, int);
    169       1.123  augustss Static uhci_soft_td_t  *uhci_alloc_std(uhci_softc_t *);
    170       1.119  augustss Static void		uhci_free_std(uhci_softc_t *, uhci_soft_td_t *);
    171       1.123  augustss Static uhci_soft_qh_t  *uhci_alloc_sqh(uhci_softc_t *);
    172       1.119  augustss Static void		uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *);
    173        1.16  augustss #if 0
    174       1.119  augustss Static void		uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *,
    175  1.264.4.48     skrll 			    uhci_intr_info_t *);
    176       1.119  augustss Static void		uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *);
    177        1.16  augustss #endif
    178         1.1  augustss 
    179       1.152  augustss Static void		uhci_free_std_chain(uhci_softc_t *,
    180  1.264.4.48     skrll 			    uhci_soft_td_t *, uhci_soft_td_t *);
    181       1.119  augustss Static usbd_status	uhci_alloc_std_chain(struct uhci_pipe *,
    182   1.264.4.1     skrll 			    uhci_softc_t *, int, int, uint16_t, usb_dma_t *,
    183       1.119  augustss 			    uhci_soft_td_t **, uhci_soft_td_t **);
    184       1.119  augustss Static void		uhci_poll_hub(void *);
    185  1.264.4.25     skrll Static void		uhci_waitintr(uhci_softc_t *, struct usbd_xfer *);
    186  1.264.4.39     skrll Static void		uhci_check_intr(uhci_softc_t *, struct uhci_xfer *);
    187  1.264.4.39     skrll Static void		uhci_idone(struct uhci_xfer *);
    188       1.119  augustss 
    189  1.264.4.25     skrll Static void		uhci_abort_xfer(struct usbd_xfer *, usbd_status);
    190       1.119  augustss 
    191       1.119  augustss Static void		uhci_timeout(void *);
    192       1.153  augustss Static void		uhci_timeout_task(void *);
    193       1.123  augustss Static void		uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *);
    194       1.123  augustss Static void		uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *);
    195       1.119  augustss Static void		uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *);
    196       1.123  augustss Static void		uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *);
    197       1.123  augustss Static void		uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *);
    198       1.119  augustss Static void		uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *);
    199  1.264.4.15     skrll Static void		uhci_add_loop(uhci_softc_t *);
    200  1.264.4.15     skrll Static void		uhci_rem_loop(uhci_softc_t *);
    201       1.119  augustss 
    202  1.264.4.25     skrll Static usbd_status	uhci_setup_isoc(struct usbd_pipe *);
    203  1.264.4.25     skrll Static void		uhci_device_isoc_enter(struct usbd_xfer *);
    204       1.119  augustss 
    205  1.264.4.36     skrll Static struct usbd_xfer *
    206  1.264.4.36     skrll 			uhci_allocx(struct usbd_bus *, unsigned int);
    207  1.264.4.25     skrll Static void		uhci_freex(struct usbd_bus *, struct usbd_xfer *);
    208       1.248       mrg Static void		uhci_get_lock(struct usbd_bus *, kmutex_t **);
    209  1.264.4.13     skrll Static int		uhci_roothub_ctrl(struct usbd_bus *,
    210  1.264.4.42     skrll 			    usb_device_request_t *, void *, int);
    211       1.119  augustss 
    212  1.264.4.25     skrll Static usbd_status	uhci_device_ctrl_transfer(struct usbd_xfer *);
    213  1.264.4.25     skrll Static usbd_status	uhci_device_ctrl_start(struct usbd_xfer *);
    214  1.264.4.25     skrll Static void		uhci_device_ctrl_abort(struct usbd_xfer *);
    215  1.264.4.25     skrll Static void		uhci_device_ctrl_close(struct usbd_pipe *);
    216  1.264.4.25     skrll Static void		uhci_device_ctrl_done(struct usbd_xfer *);
    217  1.264.4.25     skrll 
    218  1.264.4.25     skrll Static usbd_status	uhci_device_intr_transfer(struct usbd_xfer *);
    219  1.264.4.25     skrll Static usbd_status	uhci_device_intr_start(struct usbd_xfer *);
    220  1.264.4.25     skrll Static void		uhci_device_intr_abort(struct usbd_xfer *);
    221  1.264.4.25     skrll Static void		uhci_device_intr_close(struct usbd_pipe *);
    222  1.264.4.25     skrll Static void		uhci_device_intr_done(struct usbd_xfer *);
    223  1.264.4.25     skrll 
    224  1.264.4.25     skrll Static usbd_status	uhci_device_bulk_transfer(struct usbd_xfer *);
    225  1.264.4.25     skrll Static usbd_status	uhci_device_bulk_start(struct usbd_xfer *);
    226  1.264.4.25     skrll Static void		uhci_device_bulk_abort(struct usbd_xfer *);
    227  1.264.4.25     skrll Static void		uhci_device_bulk_close(struct usbd_pipe *);
    228  1.264.4.25     skrll Static void		uhci_device_bulk_done(struct usbd_xfer *);
    229  1.264.4.25     skrll 
    230  1.264.4.25     skrll Static usbd_status	uhci_device_isoc_transfer(struct usbd_xfer *);
    231  1.264.4.25     skrll Static usbd_status	uhci_device_isoc_start(struct usbd_xfer *);
    232  1.264.4.25     skrll Static void		uhci_device_isoc_abort(struct usbd_xfer *);
    233  1.264.4.25     skrll Static void		uhci_device_isoc_close(struct usbd_pipe *);
    234  1.264.4.25     skrll Static void		uhci_device_isoc_done(struct usbd_xfer *);
    235  1.264.4.25     skrll 
    236  1.264.4.25     skrll Static usbd_status	uhci_root_intr_transfer(struct usbd_xfer *);
    237  1.264.4.25     skrll Static usbd_status	uhci_root_intr_start(struct usbd_xfer *);
    238  1.264.4.25     skrll Static void		uhci_root_intr_abort(struct usbd_xfer *);
    239  1.264.4.25     skrll Static void		uhci_root_intr_close(struct usbd_pipe *);
    240  1.264.4.25     skrll Static void		uhci_root_intr_done(struct usbd_xfer *);
    241       1.119  augustss 
    242  1.264.4.25     skrll Static usbd_status	uhci_open(struct usbd_pipe *);
    243       1.119  augustss Static void		uhci_poll(struct usbd_bus *);
    244       1.133  augustss Static void		uhci_softintr(void *);
    245       1.119  augustss 
    246  1.264.4.25     skrll Static usbd_status	uhci_device_request(struct usbd_xfer *);
    247       1.119  augustss 
    248       1.119  augustss Static void		uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *);
    249       1.158  augustss Static void		uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *);
    250  1.264.4.15     skrll Static usbd_status	uhci_device_setintr(uhci_softc_t *,
    251  1.264.4.15     skrll 			    struct uhci_pipe *, int);
    252       1.119  augustss 
    253  1.264.4.25     skrll Static void		uhci_device_clear_toggle(struct usbd_pipe *);
    254  1.264.4.25     skrll Static void		uhci_noop(struct usbd_pipe *);
    255       1.119  augustss 
    256  1.264.4.42     skrll static inline uhci_soft_qh_t *
    257  1.264.4.42     skrll 			uhci_find_prev_qh(uhci_soft_qh_t *, uhci_soft_qh_t *);
    258       1.119  augustss 
    259       1.119  augustss #ifdef UHCI_DEBUG
    260       1.119  augustss Static void		uhci_dump_all(uhci_softc_t *);
    261       1.119  augustss Static void		uhci_dumpregs(uhci_softc_t *);
    262       1.119  augustss Static void		uhci_dump_qhs(uhci_soft_qh_t *);
    263       1.119  augustss Static void		uhci_dump_qh(uhci_soft_qh_t *);
    264       1.119  augustss Static void		uhci_dump_tds(uhci_soft_td_t *);
    265       1.119  augustss Static void		uhci_dump_td(uhci_soft_td_t *);
    266  1.264.4.40     skrll Static void		uhci_dump_ii(struct uhci_xfer *);
    267       1.119  augustss void			uhci_dump(void);
    268         1.1  augustss #endif
    269         1.1  augustss 
    270       1.112  augustss #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \
    271       1.112  augustss 			BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
    272       1.112  augustss #define UWRITE1(sc, r, x) \
    273       1.165   dsainty  do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \
    274       1.165   dsainty  } while (/*CONSTCOND*/0)
    275       1.112  augustss #define UWRITE2(sc, r, x) \
    276       1.165   dsainty  do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \
    277       1.165   dsainty  } while (/*CONSTCOND*/0)
    278       1.112  augustss #define UWRITE4(sc, r, x) \
    279       1.165   dsainty  do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \
    280       1.165   dsainty  } while (/*CONSTCOND*/0)
    281  1.264.4.42     skrll 
    282       1.196       mrg static __inline uint8_t
    283       1.196       mrg UREAD1(uhci_softc_t *sc, bus_size_t r)
    284       1.196       mrg {
    285       1.196       mrg 
    286       1.196       mrg 	UBARR(sc);
    287       1.196       mrg 	return bus_space_read_1(sc->iot, sc->ioh, r);
    288       1.196       mrg }
    289       1.196       mrg 
    290       1.196       mrg static __inline uint16_t
    291       1.196       mrg UREAD2(uhci_softc_t *sc, bus_size_t r)
    292       1.196       mrg {
    293       1.196       mrg 
    294       1.196       mrg 	UBARR(sc);
    295       1.196       mrg 	return bus_space_read_2(sc->iot, sc->ioh, r);
    296       1.196       mrg }
    297       1.196       mrg 
    298       1.260     joerg #ifdef UHCI_DEBUG
    299       1.196       mrg static __inline uint32_t
    300       1.196       mrg UREAD4(uhci_softc_t *sc, bus_size_t r)
    301       1.196       mrg {
    302       1.196       mrg 
    303       1.196       mrg 	UBARR(sc);
    304       1.196       mrg 	return bus_space_read_4(sc->iot, sc->ioh, r);
    305       1.196       mrg }
    306       1.260     joerg #endif
    307         1.1  augustss 
    308         1.1  augustss #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd)
    309         1.1  augustss #define UHCISTS(sc) UREAD2(sc, UHCI_STS)
    310         1.1  augustss 
    311       1.142  augustss #define UHCI_RESET_TIMEOUT 100	/* ms, reset timeout */
    312         1.1  augustss 
    313         1.1  augustss #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK)
    314         1.1  augustss 
    315       1.208  drochner const struct usbd_bus_methods uhci_bus_methods = {
    316   1.264.4.5     skrll 	.ubm_open =	uhci_open,
    317   1.264.4.5     skrll 	.ubm_softint =	uhci_softintr,
    318   1.264.4.5     skrll 	.ubm_dopoll =	uhci_poll,
    319   1.264.4.5     skrll 	.ubm_allocx =	uhci_allocx,
    320   1.264.4.5     skrll 	.ubm_freex =	uhci_freex,
    321   1.264.4.5     skrll 	.ubm_getlock =	uhci_get_lock,
    322  1.264.4.12     skrll 	.ubm_rhctrl =	uhci_roothub_ctrl,
    323         1.1  augustss };
    324         1.1  augustss 
    325       1.208  drochner const struct usbd_pipe_methods uhci_root_intr_methods = {
    326   1.264.4.5     skrll 	.upm_transfer =	uhci_root_intr_transfer,
    327   1.264.4.5     skrll 	.upm_start =	uhci_root_intr_start,
    328   1.264.4.5     skrll 	.upm_abort =	uhci_root_intr_abort,
    329   1.264.4.5     skrll 	.upm_close =	uhci_root_intr_close,
    330   1.264.4.5     skrll 	.upm_cleartoggle =	uhci_noop,
    331   1.264.4.5     skrll 	.upm_done =	uhci_root_intr_done,
    332         1.1  augustss };
    333         1.1  augustss 
    334       1.208  drochner const struct usbd_pipe_methods uhci_device_ctrl_methods = {
    335   1.264.4.5     skrll 	.upm_transfer =	uhci_device_ctrl_transfer,
    336   1.264.4.5     skrll 	.upm_start =	uhci_device_ctrl_start,
    337   1.264.4.5     skrll 	.upm_abort =	uhci_device_ctrl_abort,
    338   1.264.4.5     skrll 	.upm_close =	uhci_device_ctrl_close,
    339   1.264.4.5     skrll 	.upm_cleartoggle =	uhci_noop,
    340   1.264.4.5     skrll 	.upm_done =	uhci_device_ctrl_done,
    341         1.1  augustss };
    342         1.1  augustss 
    343       1.208  drochner const struct usbd_pipe_methods uhci_device_intr_methods = {
    344   1.264.4.5     skrll 	.upm_transfer =	uhci_device_intr_transfer,
    345   1.264.4.5     skrll 	.upm_start =	uhci_device_intr_start,
    346   1.264.4.5     skrll 	.upm_abort =	uhci_device_intr_abort,
    347   1.264.4.5     skrll 	.upm_close =	uhci_device_intr_close,
    348   1.264.4.5     skrll 	.upm_cleartoggle =	uhci_device_clear_toggle,
    349   1.264.4.5     skrll 	.upm_done =	uhci_device_intr_done,
    350         1.1  augustss };
    351         1.1  augustss 
    352       1.208  drochner const struct usbd_pipe_methods uhci_device_bulk_methods = {
    353   1.264.4.5     skrll 	.upm_transfer =	uhci_device_bulk_transfer,
    354   1.264.4.5     skrll 	.upm_start =	uhci_device_bulk_start,
    355   1.264.4.5     skrll 	.upm_abort =	uhci_device_bulk_abort,
    356   1.264.4.5     skrll 	.upm_close =	uhci_device_bulk_close,
    357   1.264.4.5     skrll 	.upm_cleartoggle =	uhci_device_clear_toggle,
    358   1.264.4.5     skrll 	.upm_done =	uhci_device_bulk_done,
    359         1.1  augustss };
    360         1.1  augustss 
    361       1.208  drochner const struct usbd_pipe_methods uhci_device_isoc_methods = {
    362   1.264.4.5     skrll 	.upm_transfer =	uhci_device_isoc_transfer,
    363   1.264.4.5     skrll 	.upm_start =	uhci_device_isoc_start,
    364   1.264.4.5     skrll 	.upm_abort =	uhci_device_isoc_abort,
    365   1.264.4.5     skrll 	.upm_close =	uhci_device_isoc_close,
    366   1.264.4.5     skrll 	.upm_cleartoggle =	uhci_noop,
    367   1.264.4.5     skrll 	.upm_done =	uhci_device_isoc_done,
    368        1.16  augustss };
    369        1.16  augustss 
    370  1.264.4.39     skrll #define uhci_add_intr_info(sc, ux) \
    371  1.264.4.41     skrll 	TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ux), ux_list)
    372  1.264.4.39     skrll #define uhci_del_intr_info(sc, ux) \
    373       1.169  augustss 	do { \
    374  1.264.4.41     skrll 		TAILQ_REMOVE(&(sc)->sc_intrhead, (ux), ux_list); \
    375  1.264.4.41     skrll 		(ux)->ux_list.tqe_prev = NULL; \
    376       1.169  augustss 	} while (0)
    377  1.264.4.41     skrll #define uhci_active_intr_info(ux) ((ux)->ux_list.tqe_prev != NULL)
    378        1.92  augustss 
    379       1.240  jakllsch static inline uhci_soft_qh_t *
    380       1.119  augustss uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh)
    381        1.92  augustss {
    382  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
    383  1.264.4.21     skrll 	DPRINTFN(15, "pqh=%p sqh=%p", pqh, sqh, 0, 0);
    384        1.92  augustss 
    385        1.92  augustss 	for (; pqh->hlink != sqh; pqh = pqh->hlink) {
    386       1.152  augustss #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG)
    387       1.223    bouyer 		usb_syncmem(&pqh->dma,
    388       1.223    bouyer 		    pqh->offs + offsetof(uhci_qh_t, qh_hlink),
    389       1.223    bouyer 		    sizeof(pqh->qh.qh_hlink),
    390       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE);
    391        1.92  augustss 		if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) {
    392       1.102  augustss 			printf("uhci_find_prev_qh: QH not found\n");
    393  1.264.4.13     skrll 			return NULL;
    394        1.92  augustss 		}
    395        1.92  augustss #endif
    396        1.92  augustss 	}
    397  1.264.4.13     skrll 	return pqh;
    398        1.92  augustss }
    399        1.92  augustss 
    400         1.1  augustss void
    401       1.142  augustss uhci_globalreset(uhci_softc_t *sc)
    402         1.1  augustss {
    403         1.1  augustss 	UHCICMD(sc, UHCI_CMD_GRESET);	/* global reset */
    404        1.20  augustss 	usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */
    405         1.1  augustss 	UHCICMD(sc, 0);			/* do nothing */
    406         1.1  augustss }
    407         1.1  augustss 
    408  1.264.4.14     skrll int
    409       1.119  augustss uhci_init(uhci_softc_t *sc)
    410         1.1  augustss {
    411        1.63  augustss 	usbd_status err;
    412         1.1  augustss 	int i, j;
    413       1.123  augustss 	uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh;
    414         1.1  augustss 	uhci_soft_td_t *std;
    415         1.1  augustss 
    416  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
    417         1.1  augustss 
    418        1.67  augustss #ifdef UHCI_DEBUG
    419        1.92  augustss 	thesc = sc;
    420        1.92  augustss 
    421  1.264.4.43     skrll 	if (uhcidebug >= 2)
    422         1.1  augustss 		uhci_dumpregs(sc);
    423         1.1  augustss #endif
    424         1.1  augustss 
    425       1.219  jmcneill 	sc->sc_suspend = PWR_RESUME;
    426       1.219  jmcneill 
    427         1.1  augustss 	UWRITE2(sc, UHCI_INTR, 0);		/* disable interrupts */
    428       1.142  augustss 	uhci_globalreset(sc);			/* reset the controller */
    429       1.142  augustss 	uhci_reset(sc);
    430        1.24  augustss 
    431         1.1  augustss 	/* Allocate and initialize real frame array. */
    432       1.152  augustss 	err = usb_allocmem(&sc->sc_bus,
    433  1.264.4.49     skrll 	    UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t),
    434  1.264.4.49     skrll 	    UHCI_FRAMELIST_ALIGN, &sc->sc_dma);
    435        1.63  augustss 	if (err)
    436  1.264.4.13     skrll 		return err;
    437       1.159  augustss 	sc->sc_pframes = KERNADDR(&sc->sc_dma, 0);
    438         1.1  augustss 	UWRITE2(sc, UHCI_FRNUM, 0);		/* set frame number to 0 */
    439       1.160  augustss 	UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/
    440         1.1  augustss 
    441       1.152  augustss 	/*
    442       1.123  augustss 	 * Allocate a TD, inactive, that hangs from the last QH.
    443       1.123  augustss 	 * This is to avoid a bug in the PIIX that makes it run berserk
    444       1.123  augustss 	 * otherwise.
    445       1.123  augustss 	 */
    446       1.123  augustss 	std = uhci_alloc_std(sc);
    447       1.123  augustss 	if (std == NULL)
    448  1.264.4.14     skrll 		return ENOMEM;
    449       1.123  augustss 	std->link.std = NULL;
    450       1.123  augustss 	std->td.td_link = htole32(UHCI_PTR_T);
    451       1.123  augustss 	std->td.td_status = htole32(0); /* inactive */
    452       1.123  augustss 	std->td.td_token = htole32(0);
    453       1.123  augustss 	std->td.td_buffer = htole32(0);
    454       1.223    bouyer 	usb_syncmem(&std->dma, std->offs, sizeof(std->td),
    455       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
    456       1.123  augustss 
    457       1.123  augustss 	/* Allocate the dummy QH marking the end and used for looping the QHs.*/
    458       1.123  augustss 	lsqh = uhci_alloc_sqh(sc);
    459       1.123  augustss 	if (lsqh == NULL)
    460  1.264.4.14     skrll 		return ENOMEM;
    461       1.123  augustss 	lsqh->hlink = NULL;
    462       1.123  augustss 	lsqh->qh.qh_hlink = htole32(UHCI_PTR_T);	/* end of QH chain */
    463       1.123  augustss 	lsqh->elink = std;
    464       1.123  augustss 	lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD);
    465       1.123  augustss 	sc->sc_last_qh = lsqh;
    466       1.223    bouyer 	usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh),
    467       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
    468       1.123  augustss 
    469         1.1  augustss 	/* Allocate the dummy QH where bulk traffic will be queued. */
    470         1.1  augustss 	bsqh = uhci_alloc_sqh(sc);
    471        1.63  augustss 	if (bsqh == NULL)
    472  1.264.4.14     skrll 		return ENOMEM;
    473       1.123  augustss 	bsqh->hlink = lsqh;
    474       1.123  augustss 	bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH);
    475       1.121  augustss 	bsqh->elink = NULL;
    476        1.88   tsutsui 	bsqh->qh.qh_elink = htole32(UHCI_PTR_T);
    477         1.1  augustss 	sc->sc_bulk_start = sc->sc_bulk_end = bsqh;
    478       1.223    bouyer 	usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh),
    479       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
    480         1.1  augustss 
    481       1.123  augustss 	/* Allocate dummy QH where high speed control traffic will be queued. */
    482       1.123  augustss 	chsqh = uhci_alloc_sqh(sc);
    483       1.123  augustss 	if (chsqh == NULL)
    484  1.264.4.14     skrll 		return ENOMEM;
    485       1.123  augustss 	chsqh->hlink = bsqh;
    486       1.123  augustss 	chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH);
    487       1.123  augustss 	chsqh->elink = NULL;
    488       1.123  augustss 	chsqh->qh.qh_elink = htole32(UHCI_PTR_T);
    489       1.123  augustss 	sc->sc_hctl_start = sc->sc_hctl_end = chsqh;
    490       1.223    bouyer 	usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh),
    491       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
    492       1.123  augustss 
    493       1.123  augustss 	/* Allocate dummy QH where control traffic will be queued. */
    494       1.123  augustss 	clsqh = uhci_alloc_sqh(sc);
    495       1.123  augustss 	if (clsqh == NULL)
    496  1.264.4.14     skrll 		return ENOMEM;
    497       1.220    bouyer 	clsqh->hlink = chsqh;
    498       1.123  augustss 	clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH);
    499       1.123  augustss 	clsqh->elink = NULL;
    500       1.123  augustss 	clsqh->qh.qh_elink = htole32(UHCI_PTR_T);
    501       1.123  augustss 	sc->sc_lctl_start = sc->sc_lctl_end = clsqh;
    502       1.223    bouyer 	usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh),
    503       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
    504         1.1  augustss 
    505       1.152  augustss 	/*
    506         1.1  augustss 	 * Make all (virtual) frame list pointers point to the interrupt
    507         1.1  augustss 	 * queue heads and the interrupt queue heads at the control
    508         1.1  augustss 	 * queue head and point the physical frame list to the virtual.
    509         1.1  augustss 	 */
    510  1.264.4.24     skrll 	for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
    511         1.1  augustss 		std = uhci_alloc_std(sc);
    512         1.1  augustss 		sqh = uhci_alloc_sqh(sc);
    513        1.67  augustss 		if (std == NULL || sqh == NULL)
    514  1.264.4.13     skrll 			return USBD_NOMEM;
    515        1.42  augustss 		std->link.sqh = sqh;
    516       1.121  augustss 		std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH);
    517        1.88   tsutsui 		std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */
    518        1.88   tsutsui 		std->td.td_token = htole32(0);
    519        1.88   tsutsui 		std->td.td_buffer = htole32(0);
    520       1.223    bouyer 		usb_syncmem(&std->dma, std->offs, sizeof(std->td),
    521       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
    522       1.123  augustss 		sqh->hlink = clsqh;
    523       1.123  augustss 		sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH);
    524       1.121  augustss 		sqh->elink = NULL;
    525        1.88   tsutsui 		sqh->qh.qh_elink = htole32(UHCI_PTR_T);
    526       1.223    bouyer 		usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
    527       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
    528         1.1  augustss 		sc->sc_vframes[i].htd = std;
    529         1.1  augustss 		sc->sc_vframes[i].etd = std;
    530         1.1  augustss 		sc->sc_vframes[i].hqh = sqh;
    531         1.1  augustss 		sc->sc_vframes[i].eqh = sqh;
    532       1.152  augustss 		for (j = i;
    533       1.152  augustss 		     j < UHCI_FRAMELIST_COUNT;
    534         1.1  augustss 		     j += UHCI_VFRAMELIST_COUNT)
    535        1.88   tsutsui 			sc->sc_pframes[j] = htole32(std->physaddr);
    536         1.1  augustss 	}
    537       1.223    bouyer 	usb_syncmem(&sc->sc_dma, 0,
    538       1.223    bouyer 	    UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t),
    539       1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
    540       1.223    bouyer 
    541         1.1  augustss 
    542  1.264.4.39     skrll 	TAILQ_INIT(&sc->sc_intrhead);
    543         1.1  augustss 
    544       1.253  christos 	sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0,
    545       1.253  christos 	    "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL);
    546        1.76  augustss 
    547       1.248       mrg 	callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE);
    548       1.248       mrg 
    549       1.248       mrg 	mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
    550  1.264.4.34     skrll 	mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB);
    551       1.248       mrg 	cv_init(&sc->sc_softwake_cv, "uhciab");
    552        1.96  augustss 
    553         1.1  augustss 	/* Set up the bus struct. */
    554   1.264.4.7     skrll 	sc->sc_bus.ub_methods = &uhci_bus_methods;
    555   1.264.4.7     skrll 	sc->sc_bus.ub_pipesize = sizeof(struct uhci_pipe);
    556   1.264.4.7     skrll 	sc->sc_bus.ub_usedma = true;
    557         1.1  augustss 
    558       1.190  augustss 	UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */
    559       1.190  augustss 
    560  1.264.4.27     skrll 	DPRINTF("Enabling...", 0, 0, 0, 0);
    561       1.225    bouyer 
    562  1.264.4.24     skrll 	err = uhci_run(sc, 1, 0);		/* and here we go... */
    563       1.152  augustss 	UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE |
    564         1.1  augustss 		UHCI_INTR_IOCE | UHCI_INTR_SPIE);	/* enable interrupts */
    565       1.225    bouyer 	return err;
    566        1.53  augustss }
    567        1.53  augustss 
    568        1.53  augustss int
    569       1.215    dyoung uhci_activate(device_t self, enum devact act)
    570        1.53  augustss {
    571       1.215    dyoung 	struct uhci_softc *sc = device_private(self);
    572        1.53  augustss 
    573        1.53  augustss 	switch (act) {
    574        1.53  augustss 	case DVACT_DEACTIVATE:
    575       1.210  kiyohara 		sc->sc_dying = 1;
    576       1.230    dyoung 		return 0;
    577       1.230    dyoung 	default:
    578       1.230    dyoung 		return EOPNOTSUPP;
    579        1.53  augustss 	}
    580        1.53  augustss }
    581        1.53  augustss 
    582       1.215    dyoung void
    583       1.215    dyoung uhci_childdet(device_t self, device_t child)
    584       1.215    dyoung {
    585       1.215    dyoung 	struct uhci_softc *sc = device_private(self);
    586       1.215    dyoung 
    587       1.215    dyoung 	KASSERT(sc->sc_child == child);
    588       1.215    dyoung 	sc->sc_child = NULL;
    589       1.215    dyoung }
    590       1.215    dyoung 
    591        1.53  augustss int
    592       1.119  augustss uhci_detach(struct uhci_softc *sc, int flags)
    593        1.53  augustss {
    594        1.53  augustss 	int rv = 0;
    595        1.53  augustss 
    596        1.53  augustss 	if (sc->sc_child != NULL)
    597        1.53  augustss 		rv = config_detach(sc->sc_child, flags);
    598       1.152  augustss 
    599        1.53  augustss 	if (rv != 0)
    600  1.264.4.13     skrll 		return rv;
    601        1.53  augustss 
    602       1.226        ad 	callout_halt(&sc->sc_poll_handle, NULL);
    603       1.226        ad 	callout_destroy(&sc->sc_poll_handle);
    604       1.226        ad 
    605       1.248       mrg 	cv_destroy(&sc->sc_softwake_cv);
    606       1.248       mrg 
    607       1.248       mrg 	mutex_destroy(&sc->sc_lock);
    608       1.248       mrg 	mutex_destroy(&sc->sc_intr_lock);
    609       1.248       mrg 
    610       1.254  christos 	pool_cache_destroy(sc->sc_xferpool);
    611       1.254  christos 
    612        1.76  augustss 	/* XXX free other data structures XXX */
    613        1.53  augustss 
    614  1.264.4.13     skrll 	return rv;
    615         1.1  augustss }
    616         1.1  augustss 
    617  1.264.4.25     skrll struct usbd_xfer *
    618  1.264.4.36     skrll uhci_allocx(struct usbd_bus *bus, unsigned int nframes)
    619        1.76  augustss {
    620  1.264.4.37     skrll 	struct uhci_softc *sc = UHCI_BUS2SC(bus);
    621  1.264.4.25     skrll 	struct usbd_xfer *xfer;
    622        1.76  augustss 
    623       1.253  christos 	xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT);
    624        1.92  augustss 	if (xfer != NULL) {
    625       1.253  christos 		memset(xfer, 0, sizeof(struct uhci_xfer));
    626  1.264.4.31     skrll 
    627        1.92  augustss #ifdef DIAGNOSTIC
    628  1.264.4.40     skrll 		struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
    629  1.264.4.41     skrll 		uxfer->ux_isdone = true;
    630   1.264.4.7     skrll 		xfer->ux_state = XFER_BUSY;
    631        1.92  augustss #endif
    632        1.92  augustss 	}
    633  1.264.4.13     skrll 	return xfer;
    634        1.76  augustss }
    635        1.76  augustss 
    636        1.76  augustss void
    637  1.264.4.25     skrll uhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer)
    638        1.76  augustss {
    639  1.264.4.37     skrll 	struct uhci_softc *sc = UHCI_BUS2SC(bus);
    640  1.264.4.37     skrll 	struct uhci_xfer *uxfer __diagused = UHCI_XFER2UXFER(xfer);
    641        1.76  augustss 
    642  1.264.4.31     skrll 	KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer,
    643  1.264.4.31     skrll 	    xfer->ux_state);
    644  1.264.4.41     skrll 	KASSERTMSG(uxfer->ux_isdone, "xfer %p not done\n", xfer);
    645        1.93  augustss #ifdef DIAGNOSTIC
    646   1.264.4.7     skrll 	xfer->ux_state = XFER_FREE;
    647        1.93  augustss #endif
    648       1.253  christos 	pool_cache_put(sc->sc_xferpool, xfer);
    649        1.48  augustss }
    650        1.48  augustss 
    651       1.248       mrg Static void
    652       1.248       mrg uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock)
    653       1.248       mrg {
    654  1.264.4.37     skrll 	struct uhci_softc *sc = UHCI_BUS2SC(bus);
    655       1.248       mrg 
    656       1.248       mrg 	*lock = &sc->sc_lock;
    657       1.248       mrg }
    658       1.248       mrg 
    659       1.248       mrg 
    660        1.72  augustss /*
    661       1.212  jmcneill  * Handle suspend/resume.
    662       1.212  jmcneill  *
    663       1.212  jmcneill  * We need to switch to polling mode here, because this routine is
    664       1.212  jmcneill  * called from an interrupt context.  This is all right since we
    665       1.212  jmcneill  * are almost suspended anyway.
    666        1.72  augustss  */
    667       1.212  jmcneill bool
    668       1.232    dyoung uhci_resume(device_t dv, const pmf_qual_t *qual)
    669        1.72  augustss {
    670       1.212  jmcneill 	uhci_softc_t *sc = device_private(dv);
    671       1.212  jmcneill 	int cmd;
    672        1.72  augustss 
    673       1.248       mrg 	mutex_spin_enter(&sc->sc_intr_lock);
    674       1.193  augustss 
    675       1.212  jmcneill 	cmd = UREAD2(sc, UHCI_CMD);
    676   1.264.4.7     skrll 	sc->sc_bus.ub_usepolling++;
    677       1.214       smb 	UWRITE2(sc, UHCI_INTR, 0);
    678       1.214       smb 	uhci_globalreset(sc);
    679       1.214       smb 	uhci_reset(sc);
    680       1.212  jmcneill 	if (cmd & UHCI_CMD_RS)
    681       1.249  drochner 		uhci_run(sc, 0, 1);
    682       1.212  jmcneill 
    683       1.212  jmcneill 	/* restore saved state */
    684       1.212  jmcneill 	UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0));
    685       1.212  jmcneill 	UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum);
    686       1.212  jmcneill 	UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof);
    687       1.212  jmcneill 
    688       1.212  jmcneill 	UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */
    689       1.248       mrg 	usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock);
    690       1.212  jmcneill 	UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */
    691       1.212  jmcneill 	UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE |
    692       1.212  jmcneill 	    UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE);
    693       1.214       smb 	UHCICMD(sc, UHCI_CMD_MAXP);
    694       1.249  drochner 	uhci_run(sc, 1, 1); /* and start traffic again */
    695       1.248       mrg 	usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock);
    696   1.264.4.7     skrll 	sc->sc_bus.ub_usepolling--;
    697       1.212  jmcneill 	if (sc->sc_intr_xfer != NULL)
    698       1.234    dyoung 		callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub,
    699       1.212  jmcneill 		    sc->sc_intr_xfer);
    700       1.212  jmcneill #ifdef UHCI_DEBUG
    701  1.264.4.43     skrll 	if (uhcidebug >= 2)
    702       1.212  jmcneill 		uhci_dumpregs(sc);
    703       1.212  jmcneill #endif
    704       1.212  jmcneill 
    705       1.219  jmcneill 	sc->sc_suspend = PWR_RESUME;
    706       1.248       mrg 	mutex_spin_exit(&sc->sc_intr_lock);
    707       1.212  jmcneill 
    708       1.212  jmcneill 	return true;
    709        1.72  augustss }
    710        1.72  augustss 
    711       1.212  jmcneill bool
    712       1.232    dyoung uhci_suspend(device_t dv, const pmf_qual_t *qual)
    713        1.30  augustss {
    714       1.212  jmcneill 	uhci_softc_t *sc = device_private(dv);
    715        1.30  augustss 	int cmd;
    716        1.30  augustss 
    717       1.248       mrg 	mutex_spin_enter(&sc->sc_intr_lock);
    718       1.212  jmcneill 
    719        1.30  augustss 	cmd = UREAD2(sc, UHCI_CMD);
    720        1.30  augustss 
    721       1.212  jmcneill #ifdef UHCI_DEBUG
    722  1.264.4.43     skrll 	if (uhcidebug >= 2)
    723       1.212  jmcneill 		uhci_dumpregs(sc);
    724       1.212  jmcneill #endif
    725       1.212  jmcneill 	if (sc->sc_intr_xfer != NULL)
    726       1.234    dyoung 		callout_stop(&sc->sc_poll_handle);
    727       1.219  jmcneill 	sc->sc_suspend = PWR_SUSPEND;
    728   1.264.4.7     skrll 	sc->sc_bus.ub_usepolling++;
    729       1.219  jmcneill 
    730       1.249  drochner 	uhci_run(sc, 0, 1); /* stop the controller */
    731       1.212  jmcneill 	cmd &= ~UHCI_CMD_RS;
    732       1.212  jmcneill 
    733       1.212  jmcneill 	/* save some state if BIOS doesn't */
    734       1.212  jmcneill 	sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM);
    735       1.212  jmcneill 	sc->sc_saved_sof = UREAD1(sc, UHCI_SOF);
    736       1.212  jmcneill 
    737       1.212  jmcneill 	UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */
    738        1.30  augustss 
    739       1.212  jmcneill 	UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */
    740       1.248       mrg 	usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock);
    741   1.264.4.7     skrll 	sc->sc_bus.ub_usepolling--;
    742        1.86  augustss 
    743       1.248       mrg 	mutex_spin_exit(&sc->sc_intr_lock);
    744       1.212  jmcneill 
    745       1.212  jmcneill 	return true;
    746        1.30  augustss }
    747        1.30  augustss 
    748        1.59  augustss #ifdef UHCI_DEBUG
    749       1.101  augustss Static void
    750       1.119  augustss uhci_dumpregs(uhci_softc_t *sc)
    751         1.1  augustss {
    752  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
    753  1.264.4.27     skrll 	DPRINTF("cmd =%04x  sts    =%04x  intr   =%04x  frnum =%04x",
    754  1.264.4.21     skrll 	    UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS),
    755  1.264.4.21     skrll 	    UREAD2(sc, UHCI_INTR), UREAD2(sc, UHCI_FRNUM));
    756  1.264.4.27     skrll 	DPRINTF("sof =%04x  portsc1=%04x  portsc2=%04x  flbase=%08x",
    757  1.264.4.21     skrll 	    UREAD1(sc, UHCI_SOF), UREAD2(sc, UHCI_PORTSC1),
    758  1.264.4.21     skrll 	    UREAD2(sc, UHCI_PORTSC2), UREAD4(sc, UHCI_FLBASEADDR));
    759         1.1  augustss }
    760         1.1  augustss 
    761         1.1  augustss void
    762       1.119  augustss uhci_dump_td(uhci_soft_td_t *p)
    763         1.1  augustss {
    764  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
    765       1.250  christos 
    766       1.223    bouyer 	usb_syncmem(&p->dma, p->offs, sizeof(p->td),
    767       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
    768  1.264.4.21     skrll 
    769  1.264.4.44     skrll 	DPRINTF("TD(%p) at 0x%08x", p, p->physaddr, 0, 0);
    770  1.264.4.27     skrll  	DPRINTF("   link=0x%08x status=0x%08x "
    771  1.264.4.21     skrll 	    "token=0x%08x buffer=0x%08x",
    772  1.264.4.21     skrll 	     le32toh(p->td.td_link),
    773  1.264.4.21     skrll 	     le32toh(p->td.td_status),
    774  1.264.4.21     skrll 	     le32toh(p->td.td_token),
    775  1.264.4.21     skrll 	     le32toh(p->td.td_buffer));
    776  1.264.4.21     skrll 
    777  1.264.4.27     skrll 	DPRINTF("bitstuff=%d crcto   =%d nak     =%d babble  =%d",
    778  1.264.4.21     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_BITSTUFF),
    779  1.264.4.21     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_CRCTO),
    780  1.264.4.21     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_NAK),
    781  1.264.4.21     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_BABBLE));
    782  1.264.4.27     skrll 	DPRINTF("dbuffer =%d stalled =%d active  =%d ioc     =%d",
    783  1.264.4.21     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_DBUFFER),
    784  1.264.4.21     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_STALLED),
    785  1.264.4.21     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_ACTIVE),
    786  1.264.4.21     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_IOC));
    787  1.264.4.27     skrll 	DPRINTF("ios     =%d ls      =%d spd     =%d",
    788  1.264.4.21     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_IOS),
    789  1.264.4.21     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_LS),
    790  1.264.4.21     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_SPD), 0);
    791  1.264.4.27     skrll 	DPRINTF("errcnt  =%d actlen  =%d pid=%02x",
    792  1.264.4.21     skrll 	    UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)),
    793  1.264.4.21     skrll 	    UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)),
    794  1.264.4.21     skrll 	    UHCI_TD_GET_PID(le32toh(p->td.td_token)), 0);
    795  1.264.4.27     skrll 	DPRINTF("addr=%d  endpt=%d  D=%d  maxlen=%d,",
    796  1.264.4.21     skrll 	    UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)),
    797  1.264.4.21     skrll 	    UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)),
    798  1.264.4.21     skrll 	    UHCI_TD_GET_DT(le32toh(p->td.td_token)),
    799  1.264.4.21     skrll 	    UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token)));
    800         1.1  augustss }
    801         1.1  augustss 
    802         1.1  augustss void
    803       1.119  augustss uhci_dump_qh(uhci_soft_qh_t *sqh)
    804         1.1  augustss {
    805  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
    806  1.264.4.21     skrll 
    807       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
    808       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
    809  1.264.4.21     skrll 
    810  1.264.4.44     skrll 	DPRINTF("QH(%p) at 0x%08x: hlink=%08x elink=%08x", sqh,
    811        1.88   tsutsui 	    (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink),
    812  1.264.4.21     skrll 	    le32toh(sqh->qh.qh_elink));
    813  1.264.4.21     skrll 
    814       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD);
    815         1.1  augustss }
    816         1.1  augustss 
    817        1.13  augustss 
    818       1.110  augustss #if 1
    819         1.1  augustss void
    820       1.119  augustss uhci_dump(void)
    821         1.1  augustss {
    822       1.110  augustss 	uhci_dump_all(thesc);
    823       1.110  augustss }
    824       1.110  augustss #endif
    825         1.1  augustss 
    826       1.110  augustss void
    827       1.119  augustss uhci_dump_all(uhci_softc_t *sc)
    828       1.110  augustss {
    829         1.1  augustss 	uhci_dumpregs(sc);
    830       1.110  augustss 	/*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/
    831       1.261     skrll 	uhci_dump_qhs(sc->sc_lctl_start);
    832         1.1  augustss }
    833         1.1  augustss 
    834        1.67  augustss 
    835        1.67  augustss void
    836       1.119  augustss uhci_dump_qhs(uhci_soft_qh_t *sqh)
    837        1.67  augustss {
    838  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
    839  1.264.4.21     skrll 
    840        1.67  augustss 	uhci_dump_qh(sqh);
    841        1.67  augustss 
    842  1.264.4.18     skrll 	/*
    843  1.264.4.18     skrll 	 * uhci_dump_qhs displays all the QHs and TDs from the given QH onwards
    844        1.67  augustss 	 * Traverses sideways first, then down.
    845        1.67  augustss 	 *
    846        1.67  augustss 	 * QH1
    847        1.67  augustss 	 * QH2
    848        1.67  augustss 	 * No QH
    849        1.67  augustss 	 * TD2.1
    850        1.67  augustss 	 * TD2.2
    851        1.67  augustss 	 * TD1.1
    852        1.67  augustss 	 * etc.
    853        1.67  augustss 	 *
    854        1.67  augustss 	 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1.
    855        1.67  augustss 	 */
    856        1.67  augustss 
    857       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
    858       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
    859        1.88   tsutsui 	if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T))
    860        1.67  augustss 		uhci_dump_qhs(sqh->hlink);
    861        1.67  augustss 	else
    862  1.264.4.27     skrll 		DPRINTF("No QH", 0, 0, 0, 0);
    863       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD);
    864        1.67  augustss 
    865        1.88   tsutsui 	if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T))
    866        1.67  augustss 		uhci_dump_tds(sqh->elink);
    867        1.67  augustss 	else
    868  1.264.4.27     skrll 		DPRINTF("No QH", 0, 0, 0, 0);
    869        1.67  augustss }
    870        1.67  augustss 
    871         1.1  augustss void
    872       1.119  augustss uhci_dump_tds(uhci_soft_td_t *std)
    873         1.1  augustss {
    874        1.67  augustss 	uhci_soft_td_t *td;
    875       1.223    bouyer 	int stop;
    876        1.67  augustss 
    877  1.264.4.24     skrll 	for (td = std; td != NULL; td = td->link.std) {
    878        1.67  augustss 		uhci_dump_td(td);
    879         1.1  augustss 
    880  1.264.4.18     skrll 		/*
    881  1.264.4.18     skrll 		 * Check whether the link pointer in this TD marks
    882        1.67  augustss 		 * the link pointer as end of queue. This avoids
    883        1.67  augustss 		 * printing the free list in case the queue/TD has
    884        1.67  augustss 		 * already been moved there (seatbelt).
    885        1.67  augustss 		 */
    886       1.223    bouyer 		usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link),
    887       1.223    bouyer 		    sizeof(td->td.td_link),
    888       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
    889       1.223    bouyer 		stop = (le32toh(td->td.td_link) & UHCI_PTR_T ||
    890       1.223    bouyer 			le32toh(td->td.td_link) == 0);
    891       1.223    bouyer 		usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link),
    892       1.223    bouyer 		    sizeof(td->td.td_link), BUS_DMASYNC_PREREAD);
    893       1.223    bouyer 		if (stop)
    894        1.67  augustss 			break;
    895        1.67  augustss 	}
    896         1.1  augustss }
    897        1.92  augustss 
    898       1.101  augustss Static void
    899  1.264.4.40     skrll uhci_dump_ii(struct uhci_xfer *ux)
    900        1.92  augustss {
    901  1.264.4.25     skrll 	struct usbd_pipe *pipe;
    902        1.95  augustss 	usb_endpoint_descriptor_t *ed;
    903  1.264.4.25     skrll 	struct usbd_device *dev;
    904       1.152  augustss 
    905  1.264.4.39     skrll 	if (ux == NULL) {
    906  1.264.4.39     skrll 		printf("ux NULL\n");
    907   1.264.4.2     skrll 		return;
    908   1.264.4.2     skrll 	}
    909  1.264.4.41     skrll 	pipe = ux->ux_xfer.ux_pipe;
    910   1.264.4.2     skrll 	if (pipe == NULL) {
    911  1.264.4.41     skrll 		printf("ux %p: done=%d pipe=NULL\n", ux, ux->ux_isdone);
    912   1.264.4.2     skrll 		return;
    913       1.139  augustss 	}
    914   1.264.4.7     skrll 	if (pipe->up_endpoint == NULL) {
    915  1.264.4.40     skrll 		printf("ux %p: done=%d pipe=%p pipe->up_endpoint=NULL\n",
    916  1.264.4.41     skrll 		       ux, ux->ux_isdone, pipe);
    917   1.264.4.2     skrll 		return;
    918       1.139  augustss 	}
    919   1.264.4.7     skrll 	if (pipe->up_dev == NULL) {
    920  1.264.4.40     skrll 		printf("ux %p: done=%d pipe=%p pipe->up_dev=NULL\n",
    921  1.264.4.41     skrll 		       ux, ux->ux_isdone, pipe);
    922   1.264.4.2     skrll 		return;
    923        1.95  augustss 	}
    924   1.264.4.7     skrll 	ed = pipe->up_endpoint->ue_edesc;
    925   1.264.4.7     skrll 	dev = pipe->up_dev;
    926  1.264.4.40     skrll 	printf("ux %p: done=%d dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n",
    927  1.264.4.41     skrll 	       ux, ux->ux_isdone, dev,
    928   1.264.4.7     skrll 	       UGETW(dev->ud_ddesc.idVendor),
    929   1.264.4.7     skrll 	       UGETW(dev->ud_ddesc.idProduct),
    930   1.264.4.7     skrll 	       dev->ud_addr, pipe,
    931        1.92  augustss 	       ed->bEndpointAddress, ed->bmAttributes);
    932        1.92  augustss }
    933        1.92  augustss 
    934       1.120  augustss void uhci_dump_iis(struct uhci_softc *sc);
    935        1.92  augustss void
    936       1.119  augustss uhci_dump_iis(struct uhci_softc *sc)
    937        1.92  augustss {
    938  1.264.4.40     skrll 	struct uhci_xfer *ux;
    939        1.92  augustss 
    940  1.264.4.39     skrll 	printf("interrupt list:\n");
    941  1.264.4.41     skrll 	for (ux = TAILQ_FIRST(&sc->sc_intrhead); ux; ux = TAILQ_NEXT(ux, ux_list))
    942  1.264.4.39     skrll 		uhci_dump_ii(ux);
    943        1.92  augustss }
    944        1.92  augustss 
    945       1.120  augustss void iidump(void);
    946       1.119  augustss void iidump(void) { uhci_dump_iis(thesc); }
    947        1.92  augustss 
    948         1.1  augustss #endif
    949         1.1  augustss 
    950         1.1  augustss /*
    951         1.1  augustss  * This routine is executed periodically and simulates interrupts
    952         1.1  augustss  * from the root controller interrupt pipe for port status change.
    953         1.1  augustss  */
    954         1.1  augustss void
    955       1.119  augustss uhci_poll_hub(void *addr)
    956         1.1  augustss {
    957  1.264.4.25     skrll 	struct usbd_xfer *xfer = addr;
    958  1.264.4.25     skrll 	struct usbd_pipe *pipe = xfer->ux_pipe;
    959       1.227    martin 	uhci_softc_t *sc;
    960         1.1  augustss 	u_char *p;
    961         1.1  augustss 
    962  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
    963         1.1  augustss 
    964   1.264.4.7     skrll 	if (__predict_false(pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL))
    965       1.228    martin 		return;	/* device has detached */
    966  1.264.4.37     skrll 	sc = UHCI_PIPE2SC(pipe);
    967       1.234    dyoung 	callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer);
    968        1.41  augustss 
    969   1.264.4.7     skrll 	p = xfer->ux_buf;
    970         1.1  augustss 	p[0] = 0;
    971         1.1  augustss 	if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC))
    972         1.1  augustss 		p[0] |= 1<<1;
    973         1.1  augustss 	if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC))
    974         1.1  augustss 		p[0] |= 1<<2;
    975        1.41  augustss 	if (p[0] == 0)
    976        1.41  augustss 		/* No change, try again in a while */
    977        1.41  augustss 		return;
    978        1.41  augustss 
    979   1.264.4.7     skrll 	xfer->ux_actlen = 1;
    980   1.264.4.7     skrll 	xfer->ux_status = USBD_NORMAL_COMPLETION;
    981       1.248       mrg 	mutex_enter(&sc->sc_lock);
    982        1.63  augustss 	usb_transfer_complete(xfer);
    983       1.248       mrg 	mutex_exit(&sc->sc_lock);
    984        1.41  augustss }
    985        1.41  augustss 
    986        1.41  augustss void
    987  1.264.4.25     skrll uhci_root_intr_done(struct usbd_xfer *xfer)
    988        1.84  augustss {
    989        1.84  augustss }
    990        1.84  augustss 
    991       1.123  augustss /*
    992       1.123  augustss  * Let the last QH loop back to the high speed control transfer QH.
    993       1.123  augustss  * This is what intel calls "bandwidth reclamation" and improves
    994       1.123  augustss  * USB performance a lot for some devices.
    995       1.123  augustss  * If we are already looping, just count it.
    996       1.123  augustss  */
    997         1.1  augustss void
    998  1.264.4.17     skrll uhci_add_loop(uhci_softc_t *sc)
    999  1.264.4.17     skrll {
   1000  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1001  1.264.4.25     skrll 
   1002       1.125  augustss #ifdef UHCI_DEBUG
   1003       1.125  augustss 	if (uhcinoloop)
   1004       1.125  augustss 		return;
   1005       1.125  augustss #endif
   1006       1.123  augustss 	if (++sc->sc_loops == 1) {
   1007  1.264.4.21     skrll 		DPRINTFN(5, "add loop", 0, 0, 0, 0);
   1008       1.123  augustss 		/* Note, we don't loop back the soft pointer. */
   1009       1.152  augustss 		sc->sc_last_qh->qh.qh_hlink =
   1010       1.123  augustss 		    htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH);
   1011       1.223    bouyer 		usb_syncmem(&sc->sc_last_qh->dma,
   1012       1.223    bouyer 		    sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink),
   1013       1.223    bouyer 		    sizeof(sc->sc_last_qh->qh.qh_hlink),
   1014       1.223    bouyer 		    BUS_DMASYNC_PREWRITE);
   1015       1.123  augustss 	}
   1016       1.123  augustss }
   1017       1.123  augustss 
   1018       1.123  augustss void
   1019  1.264.4.17     skrll uhci_rem_loop(uhci_softc_t *sc)
   1020  1.264.4.17     skrll {
   1021  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1022  1.264.4.21     skrll 
   1023       1.125  augustss #ifdef UHCI_DEBUG
   1024       1.125  augustss 	if (uhcinoloop)
   1025       1.125  augustss 		return;
   1026       1.125  augustss #endif
   1027       1.123  augustss 	if (--sc->sc_loops == 0) {
   1028  1.264.4.21     skrll 		DPRINTFN(5, "remove loop", 0, 0, 0, 0);
   1029       1.123  augustss 		sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T);
   1030       1.223    bouyer 		usb_syncmem(&sc->sc_last_qh->dma,
   1031       1.223    bouyer 		    sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink),
   1032       1.223    bouyer 		    sizeof(sc->sc_last_qh->qh.qh_hlink),
   1033       1.223    bouyer 		    BUS_DMASYNC_PREWRITE);
   1034       1.123  augustss 	}
   1035       1.123  augustss }
   1036       1.123  augustss 
   1037       1.248       mrg /* Add high speed control QH, called with lock held. */
   1038       1.123  augustss void
   1039       1.123  augustss uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   1040         1.1  augustss {
   1041        1.42  augustss 	uhci_soft_qh_t *eqh;
   1042         1.1  augustss 
   1043  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1044  1.264.4.21     skrll 
   1045       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   1046       1.248       mrg 
   1047  1.264.4.21     skrll 	DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
   1048       1.123  augustss 	eqh = sc->sc_hctl_end;
   1049       1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1050       1.223    bouyer 	    sizeof(eqh->qh.qh_hlink),
   1051       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE);
   1052        1.42  augustss 	sqh->hlink       = eqh->hlink;
   1053        1.42  augustss 	sqh->qh.qh_hlink = eqh->qh.qh_hlink;
   1054       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
   1055       1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   1056        1.42  augustss 	eqh->hlink       = sqh;
   1057       1.121  augustss 	eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
   1058       1.123  augustss 	sc->sc_hctl_end = sqh;
   1059       1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1060       1.223    bouyer 	    sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
   1061       1.125  augustss #ifdef UHCI_CTL_LOOP
   1062       1.123  augustss 	uhci_add_loop(sc);
   1063       1.125  augustss #endif
   1064         1.1  augustss }
   1065         1.1  augustss 
   1066       1.248       mrg /* Remove high speed control QH, called with lock held. */
   1067         1.1  augustss void
   1068       1.123  augustss uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   1069         1.1  augustss {
   1070         1.1  augustss 	uhci_soft_qh_t *pqh;
   1071       1.256   tsutsui 	uint32_t elink;
   1072         1.1  augustss 
   1073       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   1074       1.248       mrg 
   1075  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1076  1.264.4.21     skrll 	DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
   1077       1.125  augustss #ifdef UHCI_CTL_LOOP
   1078       1.123  augustss 	uhci_rem_loop(sc);
   1079       1.125  augustss #endif
   1080       1.124  augustss 	/*
   1081       1.124  augustss 	 * The T bit should be set in the elink of the QH so that the HC
   1082       1.124  augustss 	 * doesn't follow the pointer.  This condition may fail if the
   1083       1.124  augustss 	 * the transferred packet was short so that the QH still points
   1084       1.124  augustss 	 * at the last used TD.
   1085       1.124  augustss 	 * In this case we set the T bit and wait a little for the HC
   1086       1.124  augustss 	 * to stop looking at the TD.
   1087       1.223    bouyer 	 * Note that if the TD chain is large enough, the controller
   1088       1.223    bouyer 	 * may still be looking at the chain at the end of this function.
   1089       1.223    bouyer 	 * uhci_free_std_chain() will make sure the controller stops
   1090       1.223    bouyer 	 * looking at it quickly, but until then we should not change
   1091       1.223    bouyer 	 * sqh->hlink.
   1092       1.124  augustss 	 */
   1093       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1094       1.223    bouyer 	    sizeof(sqh->qh.qh_elink),
   1095       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1096       1.256   tsutsui 	elink = le32toh(sqh->qh.qh_elink);
   1097       1.256   tsutsui 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1098       1.256   tsutsui 	    sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD);
   1099       1.256   tsutsui 	if (!(elink & UHCI_PTR_T)) {
   1100       1.124  augustss 		sqh->qh.qh_elink = htole32(UHCI_PTR_T);
   1101       1.223    bouyer 		usb_syncmem(&sqh->dma,
   1102       1.223    bouyer 		    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1103       1.223    bouyer 		    sizeof(sqh->qh.qh_elink),
   1104       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   1105       1.124  augustss 		delay(UHCI_QH_REMOVE_DELAY);
   1106       1.124  augustss 	}
   1107       1.124  augustss 
   1108       1.123  augustss 	pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh);
   1109       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1110       1.223    bouyer 	    sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
   1111       1.152  augustss 	pqh->hlink = sqh->hlink;
   1112        1.42  augustss 	pqh->qh.qh_hlink = sqh->qh.qh_hlink;
   1113       1.223    bouyer 	usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1114       1.223    bouyer 	    sizeof(pqh->qh.qh_hlink),
   1115       1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   1116       1.124  augustss 	delay(UHCI_QH_REMOVE_DELAY);
   1117       1.123  augustss 	if (sc->sc_hctl_end == sqh)
   1118       1.123  augustss 		sc->sc_hctl_end = pqh;
   1119       1.123  augustss }
   1120       1.123  augustss 
   1121       1.248       mrg /* Add low speed control QH, called with lock held. */
   1122       1.123  augustss void
   1123       1.123  augustss uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   1124       1.123  augustss {
   1125       1.123  augustss 	uhci_soft_qh_t *eqh;
   1126       1.123  augustss 
   1127       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   1128       1.248       mrg 
   1129  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1130  1.264.4.21     skrll 	DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
   1131  1.264.4.21     skrll 
   1132       1.123  augustss 	eqh = sc->sc_lctl_end;
   1133       1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1134       1.223    bouyer 	    sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
   1135       1.152  augustss 	sqh->hlink = eqh->hlink;
   1136       1.123  augustss 	sqh->qh.qh_hlink = eqh->qh.qh_hlink;
   1137       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
   1138       1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   1139       1.152  augustss 	eqh->hlink = sqh;
   1140       1.123  augustss 	eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
   1141       1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1142       1.223    bouyer 	    sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
   1143       1.123  augustss 	sc->sc_lctl_end = sqh;
   1144       1.123  augustss }
   1145       1.123  augustss 
   1146       1.248       mrg /* Remove low speed control QH, called with lock held. */
   1147       1.123  augustss void
   1148       1.123  augustss uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   1149       1.123  augustss {
   1150       1.123  augustss 	uhci_soft_qh_t *pqh;
   1151       1.256   tsutsui 	uint32_t elink;
   1152       1.123  augustss 
   1153       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   1154       1.248       mrg 
   1155  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1156  1.264.4.21     skrll 	DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
   1157  1.264.4.21     skrll 
   1158       1.124  augustss 	/* See comment in uhci_remove_hs_ctrl() */
   1159       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1160       1.223    bouyer 	    sizeof(sqh->qh.qh_elink),
   1161       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1162       1.256   tsutsui 	elink = le32toh(sqh->qh.qh_elink);
   1163       1.256   tsutsui 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1164       1.256   tsutsui 	    sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD);
   1165       1.256   tsutsui 	if (!(elink & UHCI_PTR_T)) {
   1166       1.124  augustss 		sqh->qh.qh_elink = htole32(UHCI_PTR_T);
   1167       1.223    bouyer 		usb_syncmem(&sqh->dma,
   1168       1.223    bouyer 		    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1169       1.223    bouyer 		    sizeof(sqh->qh.qh_elink),
   1170       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   1171       1.124  augustss 		delay(UHCI_QH_REMOVE_DELAY);
   1172       1.124  augustss 	}
   1173       1.123  augustss 	pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh);
   1174       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1175       1.223    bouyer 	    sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
   1176       1.152  augustss 	pqh->hlink = sqh->hlink;
   1177       1.123  augustss 	pqh->qh.qh_hlink = sqh->qh.qh_hlink;
   1178       1.223    bouyer 	usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1179       1.223    bouyer 	    sizeof(pqh->qh.qh_hlink),
   1180       1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   1181       1.124  augustss 	delay(UHCI_QH_REMOVE_DELAY);
   1182       1.123  augustss 	if (sc->sc_lctl_end == sqh)
   1183       1.123  augustss 		sc->sc_lctl_end = pqh;
   1184         1.1  augustss }
   1185         1.1  augustss 
   1186       1.248       mrg /* Add bulk QH, called with lock held. */
   1187         1.1  augustss void
   1188       1.119  augustss uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   1189         1.1  augustss {
   1190        1.42  augustss 	uhci_soft_qh_t *eqh;
   1191         1.1  augustss 
   1192       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   1193       1.248       mrg 
   1194  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1195  1.264.4.21     skrll 	DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
   1196  1.264.4.21     skrll 
   1197        1.42  augustss 	eqh = sc->sc_bulk_end;
   1198       1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1199       1.223    bouyer 	    sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
   1200       1.152  augustss 	sqh->hlink = eqh->hlink;
   1201        1.42  augustss 	sqh->qh.qh_hlink = eqh->qh.qh_hlink;
   1202       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
   1203       1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   1204       1.152  augustss 	eqh->hlink = sqh;
   1205       1.121  augustss 	eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
   1206       1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1207       1.223    bouyer 	    sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
   1208         1.1  augustss 	sc->sc_bulk_end = sqh;
   1209       1.123  augustss 	uhci_add_loop(sc);
   1210         1.1  augustss }
   1211         1.1  augustss 
   1212       1.248       mrg /* Remove bulk QH, called with lock held. */
   1213         1.1  augustss void
   1214       1.119  augustss uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   1215         1.1  augustss {
   1216         1.1  augustss 	uhci_soft_qh_t *pqh;
   1217         1.1  augustss 
   1218       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   1219       1.248       mrg 
   1220  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1221  1.264.4.21     skrll 	DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
   1222  1.264.4.21     skrll 
   1223       1.123  augustss 	uhci_rem_loop(sc);
   1224       1.124  augustss 	/* See comment in uhci_remove_hs_ctrl() */
   1225       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1226       1.223    bouyer 	    sizeof(sqh->qh.qh_elink),
   1227       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1228       1.124  augustss 	if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) {
   1229       1.124  augustss 		sqh->qh.qh_elink = htole32(UHCI_PTR_T);
   1230       1.223    bouyer 		usb_syncmem(&sqh->dma,
   1231       1.223    bouyer 		    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1232       1.223    bouyer 		    sizeof(sqh->qh.qh_elink),
   1233       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   1234       1.124  augustss 		delay(UHCI_QH_REMOVE_DELAY);
   1235       1.124  augustss 	}
   1236        1.92  augustss 	pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh);
   1237       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1238       1.223    bouyer 	    sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
   1239        1.42  augustss 	pqh->hlink       = sqh->hlink;
   1240        1.42  augustss 	pqh->qh.qh_hlink = sqh->qh.qh_hlink;
   1241       1.223    bouyer 	usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1242       1.223    bouyer 	    sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
   1243       1.124  augustss 	delay(UHCI_QH_REMOVE_DELAY);
   1244         1.1  augustss 	if (sc->sc_bulk_end == sqh)
   1245         1.1  augustss 		sc->sc_bulk_end = pqh;
   1246         1.1  augustss }
   1247         1.1  augustss 
   1248       1.141  augustss Static int uhci_intr1(uhci_softc_t *);
   1249       1.141  augustss 
   1250         1.1  augustss int
   1251       1.119  augustss uhci_intr(void *arg)
   1252         1.1  augustss {
   1253        1.44  augustss 	uhci_softc_t *sc = arg;
   1254       1.248       mrg 	int ret = 0;
   1255       1.248       mrg 
   1256  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1257  1.264.4.21     skrll 
   1258       1.248       mrg 	mutex_spin_enter(&sc->sc_intr_lock);
   1259       1.146  augustss 
   1260       1.216  drochner 	if (sc->sc_dying || !device_has_power(sc->sc_dev))
   1261       1.248       mrg 		goto done;
   1262       1.141  augustss 
   1263   1.264.4.7     skrll 	if (sc->sc_bus.ub_usepolling || UREAD2(sc, UHCI_INTR) == 0) {
   1264  1.264.4.21     skrll 		DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0);
   1265       1.248       mrg 		goto done;
   1266       1.141  augustss 	}
   1267       1.179   mycroft 
   1268       1.248       mrg 	ret = uhci_intr1(sc);
   1269       1.248       mrg 
   1270       1.248       mrg  done:
   1271       1.248       mrg 	mutex_spin_exit(&sc->sc_intr_lock);
   1272       1.248       mrg 	return ret;
   1273       1.141  augustss }
   1274       1.141  augustss 
   1275       1.141  augustss int
   1276       1.141  augustss uhci_intr1(uhci_softc_t *sc)
   1277       1.141  augustss {
   1278        1.44  augustss 	int status;
   1279        1.44  augustss 	int ack;
   1280         1.1  augustss 
   1281  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1282  1.264.4.21     skrll 
   1283        1.67  augustss #ifdef UHCI_DEBUG
   1284  1.264.4.46     skrll 	if (uhcidebug >= 15) {
   1285  1.264.4.27     skrll 		DPRINTF("sc %p", sc, 0, 0, 0);
   1286         1.1  augustss 		uhci_dumpregs(sc);
   1287         1.1  augustss 	}
   1288         1.1  augustss #endif
   1289       1.117  augustss 
   1290       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_intr_lock));
   1291       1.248       mrg 
   1292       1.153  augustss 	status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS;
   1293       1.127     soren 	if (status == 0)	/* The interrupt was not for us. */
   1294  1.264.4.13     skrll 		return 0;
   1295       1.127     soren 
   1296       1.117  augustss 	if (sc->sc_suspend != PWR_RESUME) {
   1297       1.201  jmcneill #ifdef DIAGNOSTIC
   1298       1.117  augustss 		printf("%s: interrupt while not operating ignored\n",
   1299       1.216  drochner 		       device_xname(sc->sc_dev));
   1300       1.201  jmcneill #endif
   1301       1.134  augustss 		UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */
   1302  1.264.4.13     skrll 		return 0;
   1303       1.117  augustss 	}
   1304        1.44  augustss 
   1305        1.44  augustss 	ack = 0;
   1306        1.44  augustss 	if (status & UHCI_STS_USBINT)
   1307        1.44  augustss 		ack |= UHCI_STS_USBINT;
   1308        1.44  augustss 	if (status & UHCI_STS_USBEI)
   1309        1.44  augustss 		ack |= UHCI_STS_USBEI;
   1310         1.1  augustss 	if (status & UHCI_STS_RD) {
   1311        1.44  augustss 		ack |= UHCI_STS_RD;
   1312       1.118  augustss #ifdef UHCI_DEBUG
   1313       1.216  drochner 		printf("%s: resume detect\n", device_xname(sc->sc_dev));
   1314       1.118  augustss #endif
   1315         1.1  augustss 	}
   1316         1.1  augustss 	if (status & UHCI_STS_HSE) {
   1317        1.44  augustss 		ack |= UHCI_STS_HSE;
   1318       1.216  drochner 		printf("%s: host system error\n", device_xname(sc->sc_dev));
   1319         1.1  augustss 	}
   1320         1.1  augustss 	if (status & UHCI_STS_HCPE) {
   1321        1.44  augustss 		ack |= UHCI_STS_HCPE;
   1322       1.152  augustss 		printf("%s: host controller process error\n",
   1323       1.216  drochner 		       device_xname(sc->sc_dev));
   1324        1.44  augustss 	}
   1325       1.233   msaitoh 
   1326       1.233   msaitoh 	/* When HCHalted=1 and Run/Stop=0 , it is normal */
   1327       1.233   msaitoh 	if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) {
   1328        1.44  augustss 		/* no acknowledge needed */
   1329       1.136  augustss 		if (!sc->sc_dying) {
   1330       1.152  augustss 			printf("%s: host controller halted\n",
   1331       1.216  drochner 			    device_xname(sc->sc_dev));
   1332       1.110  augustss #ifdef UHCI_DEBUG
   1333       1.136  augustss 			uhci_dump_all(sc);
   1334       1.110  augustss #endif
   1335       1.136  augustss 		}
   1336       1.136  augustss 		sc->sc_dying = 1;
   1337         1.1  augustss 	}
   1338        1.44  augustss 
   1339       1.132  augustss 	if (!ack)
   1340  1.264.4.13     skrll 		return 0;	/* nothing to acknowledge */
   1341       1.132  augustss 	UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */
   1342         1.1  augustss 
   1343        1.85  augustss 	usb_schedsoftintr(&sc->sc_bus);
   1344        1.85  augustss 
   1345  1.264.4.21     skrll 	DPRINTFN(15, "sc %p done", sc, 0, 0, 0);
   1346        1.85  augustss 
   1347  1.264.4.13     skrll 	return 1;
   1348        1.85  augustss }
   1349        1.85  augustss 
   1350        1.85  augustss void
   1351       1.133  augustss uhci_softintr(void *v)
   1352        1.85  augustss {
   1353       1.216  drochner 	struct usbd_bus *bus = v;
   1354  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_BUS2SC(bus);
   1355  1.264.4.39     skrll 	struct uhci_xfer *ux, *nextux;
   1356        1.85  augustss 
   1357  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1358  1.264.4.27     skrll 	DPRINTF("sc %p", sc, 0, 0, 0);
   1359       1.248       mrg 
   1360  1.264.4.21     skrll 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
   1361        1.50  augustss 
   1362         1.1  augustss 	/*
   1363         1.1  augustss 	 * Interrupts on UHCI really suck.  When the host controller
   1364         1.1  augustss 	 * interrupts because a transfer is completed there is no
   1365         1.1  augustss 	 * way of knowing which transfer it was.  You can scan down
   1366         1.1  augustss 	 * the TDs and QHs of the previous frame to limit the search,
   1367         1.1  augustss 	 * but that assumes that the interrupt was not delayed by more
   1368         1.1  augustss 	 * than 1 ms, which may not always be true (e.g. after debug
   1369         1.1  augustss 	 * output on a slow console).
   1370         1.1  augustss 	 * We scan all interrupt descriptors to see if any have
   1371         1.1  augustss 	 * completed.
   1372         1.1  augustss 	 */
   1373  1.264.4.39     skrll 	for (ux = TAILQ_FIRST(&sc->sc_intrhead); ux; ux = nextux) {
   1374  1.264.4.41     skrll 		nextux = TAILQ_NEXT(ux, ux_list);
   1375  1.264.4.39     skrll 		uhci_check_intr(sc, ux);
   1376       1.178    martin 	}
   1377         1.1  augustss 
   1378       1.153  augustss 	if (sc->sc_softwake) {
   1379       1.153  augustss 		sc->sc_softwake = 0;
   1380       1.248       mrg 		cv_broadcast(&sc->sc_softwake_cv);
   1381       1.153  augustss 	}
   1382         1.1  augustss }
   1383         1.1  augustss 
   1384         1.1  augustss /* Check for an interrupt. */
   1385         1.1  augustss void
   1386  1.264.4.39     skrll uhci_check_intr(uhci_softc_t *sc, struct uhci_xfer *ux)
   1387         1.1  augustss {
   1388         1.1  augustss 	uhci_soft_td_t *std, *lstd;
   1389   1.264.4.1     skrll 	uint32_t status;
   1390         1.1  augustss 
   1391  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1392  1.264.4.39     skrll 	DPRINTFN(15, "ux %p", ux, 0, 0, 0);
   1393  1.264.4.31     skrll 
   1394  1.264.4.39     skrll 	KASSERT(ux != NULL);
   1395  1.264.4.31     skrll 
   1396  1.264.4.41     skrll 	struct usbd_xfer *xfer = &ux->ux_xfer;
   1397  1.264.4.39     skrll 	if (xfer->ux_status == USBD_CANCELLED ||
   1398  1.264.4.39     skrll 	    xfer->ux_status == USBD_TIMEOUT) {
   1399  1.264.4.39     skrll 		DPRINTF("aborted xfer %p", xfer, 0, 0, 0);
   1400       1.155  augustss 		return;
   1401       1.155  augustss 	}
   1402       1.155  augustss 
   1403  1.264.4.41     skrll 	if (ux->ux_stdstart == NULL)
   1404         1.1  augustss 		return;
   1405  1.264.4.41     skrll 	lstd = ux->ux_stdend;
   1406  1.264.4.31     skrll 
   1407  1.264.4.31     skrll 	KASSERT(lstd != NULL);
   1408  1.264.4.31     skrll 
   1409       1.223    bouyer 	usb_syncmem(&lstd->dma,
   1410       1.223    bouyer 	    lstd->offs + offsetof(uhci_td_t, td_status),
   1411       1.223    bouyer 	    sizeof(lstd->td.td_status),
   1412       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1413       1.256   tsutsui 	status = le32toh(lstd->td.td_status);
   1414       1.256   tsutsui 	usb_syncmem(&lstd->dma,
   1415       1.256   tsutsui 	    lstd->offs + offsetof(uhci_td_t, td_status),
   1416       1.256   tsutsui 	    sizeof(lstd->td.td_status),
   1417       1.256   tsutsui 	    BUS_DMASYNC_PREREAD);
   1418       1.258     skrll 
   1419       1.258     skrll 	/* If the last TD is not marked active we can complete */
   1420       1.258     skrll 	if (!(status & UHCI_TD_ACTIVE)) {
   1421       1.258     skrll  done:
   1422  1.264.4.39     skrll 		DPRINTFN(12, "ux=%p done", ux, 0, 0, 0);
   1423  1.264.4.21     skrll 
   1424  1.264.4.39     skrll 		callout_stop(&xfer->ux_callout);
   1425  1.264.4.39     skrll 		uhci_idone(ux);
   1426       1.258     skrll 		return;
   1427       1.258     skrll 	}
   1428       1.258     skrll 
   1429       1.258     skrll 	/*
   1430       1.258     skrll 	 * If the last TD is still active we need to check whether there
   1431       1.258     skrll 	 * is an error somewhere in the middle, or whether there was a
   1432       1.258     skrll 	 * short packet (SPD and not ACTIVE).
   1433       1.258     skrll 	 */
   1434  1.264.4.39     skrll 	DPRINTFN(12, "active ux=%p", ux, 0, 0, 0);
   1435  1.264.4.41     skrll 	for (std = ux->ux_stdstart; std != lstd; std = std->link.std) {
   1436       1.258     skrll 		usb_syncmem(&std->dma,
   1437       1.258     skrll 		    std->offs + offsetof(uhci_td_t, td_status),
   1438       1.258     skrll 		    sizeof(std->td.td_status),
   1439       1.258     skrll 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1440       1.258     skrll 		status = le32toh(std->td.td_status);
   1441       1.258     skrll 		usb_syncmem(&std->dma,
   1442       1.258     skrll 		    std->offs + offsetof(uhci_td_t, td_status),
   1443       1.258     skrll 		    sizeof(std->td.td_status), BUS_DMASYNC_PREREAD);
   1444       1.258     skrll 
   1445       1.258     skrll 		/* If there's an active TD the xfer isn't done. */
   1446       1.258     skrll 		if (status & UHCI_TD_ACTIVE) {
   1447  1.264.4.39     skrll 			DPRINTFN(12, "ux=%p std=%p still active",
   1448  1.264.4.39     skrll 			    ux, std, 0, 0);
   1449       1.258     skrll 			return;
   1450       1.258     skrll 		}
   1451       1.258     skrll 
   1452       1.258     skrll 		/* Any kind of error makes the xfer done. */
   1453       1.258     skrll 		if (status & UHCI_TD_STALLED)
   1454       1.258     skrll 			goto done;
   1455       1.258     skrll 
   1456       1.258     skrll 		/*
   1457       1.258     skrll 		 * If the data phase of a control transfer is short, we need
   1458       1.258     skrll 		 * to complete the status stage
   1459       1.258     skrll 		 */
   1460   1.264.4.7     skrll 		usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc;
   1461       1.258     skrll 		uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes);
   1462       1.258     skrll 
   1463       1.258     skrll 		if ((status & UHCI_TD_SPD) && xfertype == UE_CONTROL) {
   1464       1.258     skrll 			struct uhci_pipe *upipe =
   1465  1.264.4.50     skrll 			    UHCI_PIPE2UPIPE(xfer->ux_pipe);
   1466  1.264.4.33     skrll 			uhci_soft_qh_t *sqh = upipe->ctrl.sqh;
   1467  1.264.4.33     skrll 			uhci_soft_td_t *stat = upipe->ctrl.stat;
   1468       1.258     skrll 
   1469  1.264.4.39     skrll 			DPRINTFN(12, "ux=%p std=%p control status"
   1470  1.264.4.41     skrll 			    "phase needs completion", ux, ux->ux_stdstart, 0, 0);
   1471       1.258     skrll 
   1472       1.258     skrll 			sqh->qh.qh_elink =
   1473       1.258     skrll 			    htole32(stat->physaddr | UHCI_PTR_TD);
   1474       1.258     skrll 			usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
   1475       1.258     skrll 			    BUS_DMASYNC_PREWRITE);
   1476       1.258     skrll 			break;
   1477       1.258     skrll 		}
   1478       1.258     skrll 
   1479       1.258     skrll 		/* We want short packets, and it is short: it's done */
   1480       1.258     skrll 		usb_syncmem(&std->dma,
   1481       1.258     skrll 		    std->offs + offsetof(uhci_td_t, td_token),
   1482       1.258     skrll 		    sizeof(std->td.td_token),
   1483       1.258     skrll 		    BUS_DMASYNC_POSTWRITE);
   1484       1.258     skrll 
   1485       1.258     skrll 		if ((status & UHCI_TD_SPD) &&
   1486       1.258     skrll 			UHCI_TD_GET_ACTLEN(status) <
   1487       1.258     skrll 			UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) {
   1488       1.258     skrll 			goto done;
   1489        1.18  augustss 		}
   1490         1.1  augustss 	}
   1491         1.1  augustss }
   1492         1.1  augustss 
   1493       1.248       mrg /* Called with USB lock held. */
   1494         1.1  augustss void
   1495  1.264.4.39     skrll uhci_idone(struct uhci_xfer *ux)
   1496         1.1  augustss {
   1497  1.264.4.41     skrll 	struct usbd_xfer *xfer = &ux->ux_xfer;
   1498  1.264.4.37     skrll 	uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer);
   1499  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   1500         1.1  augustss 	uhci_soft_td_t *std;
   1501   1.264.4.1     skrll 	uint32_t status = 0, nstatus;
   1502        1.26  augustss 	int actlen;
   1503         1.1  augustss 
   1504   1.264.4.7     skrll 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
   1505       1.248       mrg 
   1506  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1507  1.264.4.39     skrll 	DPRINTFN(12, "ux=%p", ux, 0, 0, 0);
   1508  1.264.4.21     skrll 
   1509         1.7  augustss #ifdef DIAGNOSTIC
   1510        1.92  augustss #ifdef UHCI_DEBUG
   1511  1.264.4.41     skrll 	if (ux->ux_isdone) {
   1512  1.264.4.31     skrll 		DPRINTF("--- dump start ---", 0, 0, 0, 0);
   1513  1.264.4.39     skrll 		uhci_dump_ii(ux);
   1514  1.264.4.31     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   1515         1.7  augustss 	}
   1516         1.7  augustss #endif
   1517  1.264.4.41     skrll 	KASSERT(!ux->ux_isdone);
   1518  1.264.4.41     skrll 	ux->ux_isdone = true;
   1519  1.264.4.31     skrll #endif
   1520        1.48  augustss 
   1521   1.264.4.7     skrll 	if (xfer->ux_nframes != 0) {
   1522        1.48  augustss 		/* Isoc transfer, do things differently. */
   1523  1.264.4.33     skrll 		uhci_soft_td_t **stds = upipe->isoc.stds;
   1524       1.126  augustss 		int i, n, nframes, len;
   1525        1.48  augustss 
   1526  1.264.4.39     skrll 		DPRINTFN(5, "ux=%p isoc ready", ux, 0, 0, 0);
   1527        1.48  augustss 
   1528   1.264.4.7     skrll 		nframes = xfer->ux_nframes;
   1529        1.48  augustss 		actlen = 0;
   1530  1.264.4.41     skrll 		n = UHCI_XFER2UXFER(xfer)->ux_curframe;
   1531        1.48  augustss 		for (i = 0; i < nframes; i++) {
   1532        1.48  augustss 			std = stds[n];
   1533        1.59  augustss #ifdef UHCI_DEBUG
   1534  1.264.4.43     skrll 			if (uhcidebug >= 5) {
   1535  1.264.4.27     skrll 				DPRINTF("isoc TD %d", i, 0, 0, 0);
   1536  1.264.4.53     skrll 				DPRINTF("--- dump start ---", 0, 0, 0, 0);
   1537        1.48  augustss 				uhci_dump_td(std);
   1538  1.264.4.53     skrll 				DPRINTF("--- dump end ---", 0, 0, 0, 0);
   1539        1.48  augustss 			}
   1540        1.48  augustss #endif
   1541        1.48  augustss 			if (++n >= UHCI_VFRAMELIST_COUNT)
   1542        1.48  augustss 				n = 0;
   1543       1.223    bouyer 			usb_syncmem(&std->dma,
   1544       1.223    bouyer 			    std->offs + offsetof(uhci_td_t, td_status),
   1545       1.223    bouyer 			    sizeof(std->td.td_status),
   1546       1.223    bouyer 			    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1547        1.88   tsutsui 			status = le32toh(std->td.td_status);
   1548       1.126  augustss 			len = UHCI_TD_GET_ACTLEN(status);
   1549   1.264.4.7     skrll 			xfer->ux_frlengths[i] = len;
   1550       1.126  augustss 			actlen += len;
   1551        1.48  augustss 		}
   1552  1.264.4.33     skrll 		upipe->isoc.inuse -= nframes;
   1553   1.264.4.7     skrll 		xfer->ux_actlen = actlen;
   1554   1.264.4.7     skrll 		xfer->ux_status = USBD_NORMAL_COMPLETION;
   1555       1.140  augustss 		goto end;
   1556        1.48  augustss 	}
   1557        1.48  augustss 
   1558        1.59  augustss #ifdef UHCI_DEBUG
   1559  1.264.4.47     skrll 	DPRINTFN(10, "ux=%p, xfer=%p, pipe=%p ready", ux, xfer, upipe, 0);
   1560  1.264.4.47     skrll 	if (uhcidebug >= 10) {
   1561  1.264.4.47     skrll 		DPRINTF("--- dump start ---", 0, 0, 0, 0);
   1562  1.264.4.41     skrll 		uhci_dump_tds(ux->ux_stdstart);
   1563  1.264.4.47     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   1564  1.264.4.47     skrll 	}
   1565        1.48  augustss #endif
   1566        1.48  augustss 
   1567        1.26  augustss 	/* The transfer is done, compute actual length and status. */
   1568        1.26  augustss 	actlen = 0;
   1569  1.264.4.41     skrll 	for (std = ux->ux_stdstart; std != NULL; std = std->link.std) {
   1570       1.223    bouyer 		usb_syncmem(&std->dma, std->offs, sizeof(std->td),
   1571       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1572        1.88   tsutsui 		nstatus = le32toh(std->td.td_status);
   1573        1.64  augustss 		if (nstatus & UHCI_TD_ACTIVE)
   1574        1.26  augustss 			break;
   1575        1.67  augustss 
   1576        1.64  augustss 		status = nstatus;
   1577        1.88   tsutsui 		if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) !=
   1578        1.88   tsutsui 			UHCI_TD_PID_SETUP)
   1579        1.26  augustss 			actlen += UHCI_TD_GET_ACTLEN(status);
   1580       1.176   mycroft 		else {
   1581       1.176   mycroft 			/*
   1582       1.176   mycroft 			 * UHCI will report CRCTO in addition to a STALL or NAK
   1583       1.176   mycroft 			 * for a SETUP transaction.  See section 3.2.2, "TD
   1584       1.176   mycroft 			 * CONTROL AND STATUS".
   1585       1.176   mycroft 			 */
   1586       1.176   mycroft 			if (status & (UHCI_TD_STALLED | UHCI_TD_NAK))
   1587       1.176   mycroft 				status &= ~UHCI_TD_CRCTO;
   1588       1.176   mycroft 		}
   1589         1.1  augustss 	}
   1590        1.38  augustss 	/* If there are left over TDs we need to update the toggle. */
   1591        1.63  augustss 	if (std != NULL)
   1592        1.88   tsutsui 		upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token));
   1593        1.38  augustss 
   1594         1.1  augustss 	status &= UHCI_TD_ERROR;
   1595  1.264.4.29     skrll 	DPRINTFN(10, "actlen=%d, status=0x%x", actlen, status, 0, 0);
   1596   1.264.4.7     skrll 	xfer->ux_actlen = actlen;
   1597         1.1  augustss 	if (status != 0) {
   1598       1.122        tv 
   1599  1.264.4.21     skrll 		DPRINTFN((status == UHCI_TD_STALLED) * 10,
   1600  1.264.4.21     skrll 		    "error, addr=%d, endpt=0x%02x",
   1601  1.264.4.21     skrll 		    xfer->ux_pipe->up_dev->ud_addr,
   1602  1.264.4.21     skrll 		    xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress,
   1603  1.264.4.21     skrll 		    0, 0);
   1604  1.264.4.21     skrll 		DPRINTFN((status == UHCI_TD_STALLED) * 10,
   1605  1.264.4.21     skrll 		    "bitstuff=%d crcto   =%d nak     =%d babble  =%d",
   1606  1.264.4.45     skrll 		    !!(status & UHCI_TD_BITSTUFF),
   1607  1.264.4.45     skrll 		    !!(status & UHCI_TD_CRCTO),
   1608  1.264.4.45     skrll 		    !!(status & UHCI_TD_NAK),
   1609  1.264.4.45     skrll 		    !!(status & UHCI_TD_BABBLE));
   1610  1.264.4.21     skrll 		DPRINTFN((status == UHCI_TD_STALLED) * 10,
   1611  1.264.4.21     skrll 		    "dbuffer =%d stalled =%d active  =%d",
   1612  1.264.4.45     skrll 		    !!(status & UHCI_TD_DBUFFER),
   1613  1.264.4.45     skrll 		    !!(status & UHCI_TD_STALLED),
   1614  1.264.4.45     skrll 		    !!(status & UHCI_TD_ACTIVE),
   1615  1.264.4.21     skrll 		    0);
   1616       1.122        tv 
   1617         1.1  augustss 		if (status == UHCI_TD_STALLED)
   1618   1.264.4.7     skrll 			xfer->ux_status = USBD_STALLED;
   1619         1.1  augustss 		else
   1620   1.264.4.7     skrll 			xfer->ux_status = USBD_IOERROR; /* more info XXX */
   1621         1.1  augustss 	} else {
   1622   1.264.4.7     skrll 		xfer->ux_status = USBD_NORMAL_COMPLETION;
   1623         1.1  augustss 	}
   1624       1.140  augustss 
   1625       1.140  augustss  end:
   1626        1.63  augustss 	usb_transfer_complete(xfer);
   1627   1.264.4.7     skrll 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
   1628  1.264.4.39     skrll 	DPRINTFN(12, "ux=%p done", ux, 0, 0, 0);
   1629         1.1  augustss }
   1630         1.1  augustss 
   1631        1.13  augustss /*
   1632        1.13  augustss  * Called when a request does not complete.
   1633        1.13  augustss  */
   1634         1.1  augustss void
   1635       1.119  augustss uhci_timeout(void *addr)
   1636         1.1  augustss {
   1637  1.264.4.39     skrll 	struct usbd_xfer *xfer = addr;
   1638  1.264.4.39     skrll 	struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
   1639  1.264.4.39     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   1640       1.153  augustss 
   1641  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1642  1.264.4.21     skrll 
   1643  1.264.4.27     skrll 	DPRINTF("uxfer %p", uxfer, 0, 0, 0);
   1644       1.153  augustss 
   1645       1.153  augustss 	if (sc->sc_dying) {
   1646       1.248       mrg 		mutex_enter(&sc->sc_lock);
   1647  1.264.4.39     skrll 		uhci_abort_xfer(xfer, USBD_TIMEOUT);
   1648       1.248       mrg 		mutex_exit(&sc->sc_lock);
   1649       1.153  augustss 		return;
   1650       1.153  augustss 	}
   1651         1.1  augustss 
   1652       1.153  augustss 	/* Execute the abort in a process context. */
   1653  1.264.4.41     skrll 	usb_init_task(&uxfer->ux_aborttask, uhci_timeout_task, xfer,
   1654       1.252  jmcneill 	    USB_TASKQ_MPSAFE);
   1655  1.264.4.41     skrll 	usb_add_task(uxfer->ux_xfer.ux_pipe->up_dev, &uxfer->ux_aborttask,
   1656       1.204     joerg 	    USB_TASKQ_HC);
   1657       1.153  augustss }
   1658        1.51  augustss 
   1659       1.153  augustss void
   1660       1.153  augustss uhci_timeout_task(void *addr)
   1661       1.153  augustss {
   1662  1.264.4.25     skrll 	struct usbd_xfer *xfer = addr;
   1663  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   1664       1.153  augustss 
   1665  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1666  1.264.4.21     skrll 
   1667  1.264.4.27     skrll 	DPRINTF("xfer=%p", xfer, 0, 0, 0);
   1668        1.67  augustss 
   1669       1.248       mrg 	mutex_enter(&sc->sc_lock);
   1670       1.153  augustss 	uhci_abort_xfer(xfer, USBD_TIMEOUT);
   1671       1.248       mrg 	mutex_exit(&sc->sc_lock);
   1672         1.1  augustss }
   1673         1.1  augustss 
   1674         1.1  augustss /*
   1675         1.1  augustss  * Wait here until controller claims to have an interrupt.
   1676         1.1  augustss  * Then call uhci_intr and return.  Use timeout to avoid waiting
   1677         1.1  augustss  * too long.
   1678        1.13  augustss  * Only used during boot when interrupts are not enabled yet.
   1679         1.1  augustss  */
   1680         1.1  augustss void
   1681  1.264.4.25     skrll uhci_waitintr(uhci_softc_t *sc, struct usbd_xfer *xfer)
   1682         1.1  augustss {
   1683   1.264.4.7     skrll 	int timo = xfer->ux_timeout;
   1684  1.264.4.39     skrll 	struct uhci_xfer *ux;
   1685        1.13  augustss 
   1686       1.248       mrg 	mutex_enter(&sc->sc_lock);
   1687       1.248       mrg 
   1688  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1689  1.264.4.21     skrll 	DPRINTFN(10, "timeout = %dms", timo, 0, 0, 0);
   1690         1.1  augustss 
   1691   1.264.4.7     skrll 	xfer->ux_status = USBD_IN_PROGRESS;
   1692        1.26  augustss 	for (; timo >= 0; timo--) {
   1693       1.248       mrg 		usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_lock);
   1694  1.264.4.21     skrll 		DPRINTFN(20, "0x%04x",
   1695  1.264.4.21     skrll 		    UREAD2(sc, UHCI_STS), 0, 0, 0);
   1696         1.1  augustss 		if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) {
   1697       1.248       mrg 			mutex_spin_enter(&sc->sc_intr_lock);
   1698       1.141  augustss 			uhci_intr1(sc);
   1699       1.248       mrg 			mutex_spin_exit(&sc->sc_intr_lock);
   1700   1.264.4.7     skrll 			if (xfer->ux_status != USBD_IN_PROGRESS)
   1701       1.248       mrg 				goto done;
   1702         1.1  augustss 		}
   1703         1.1  augustss 	}
   1704        1.13  augustss 
   1705        1.13  augustss 	/* Timeout */
   1706  1.264.4.27     skrll 	DPRINTF("timeout", 0, 0, 0, 0);
   1707  1.264.4.39     skrll 	for (ux = TAILQ_FIRST(&sc->sc_intrhead); ux != NULL;
   1708  1.264.4.41     skrll 	    ux = TAILQ_NEXT(ux, ux_list))
   1709  1.264.4.41     skrll 		if (&ux->ux_xfer == xfer)
   1710  1.264.4.39     skrll 			break;
   1711  1.264.4.31     skrll 
   1712  1.264.4.39     skrll 	KASSERT(ux != NULL);
   1713  1.264.4.31     skrll 
   1714  1.264.4.39     skrll 	uhci_idone(ux);
   1715       1.248       mrg 
   1716       1.248       mrg done:
   1717       1.248       mrg 	mutex_exit(&sc->sc_lock);
   1718         1.1  augustss }
   1719         1.1  augustss 
   1720         1.8  augustss void
   1721       1.119  augustss uhci_poll(struct usbd_bus *bus)
   1722         1.8  augustss {
   1723  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_BUS2SC(bus);
   1724         1.8  augustss 
   1725       1.248       mrg 	if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) {
   1726       1.248       mrg 		mutex_spin_enter(&sc->sc_intr_lock);
   1727       1.141  augustss 		uhci_intr1(sc);
   1728       1.248       mrg 		mutex_spin_exit(&sc->sc_intr_lock);
   1729       1.248       mrg 	}
   1730         1.8  augustss }
   1731         1.8  augustss 
   1732         1.1  augustss void
   1733       1.119  augustss uhci_reset(uhci_softc_t *sc)
   1734         1.1  augustss {
   1735         1.1  augustss 	int n;
   1736         1.1  augustss 
   1737         1.1  augustss 	UHCICMD(sc, UHCI_CMD_HCRESET);
   1738         1.1  augustss 	/* The reset bit goes low when the controller is done. */
   1739       1.152  augustss 	for (n = 0; n < UHCI_RESET_TIMEOUT &&
   1740         1.1  augustss 		    (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++)
   1741        1.92  augustss 		usb_delay_ms(&sc->sc_bus, 1);
   1742         1.1  augustss 	if (n >= UHCI_RESET_TIMEOUT)
   1743       1.152  augustss 		printf("%s: controller did not reset\n",
   1744       1.216  drochner 		       device_xname(sc->sc_dev));
   1745         1.1  augustss }
   1746         1.1  augustss 
   1747        1.16  augustss usbd_status
   1748       1.249  drochner uhci_run(uhci_softc_t *sc, int run, int locked)
   1749         1.1  augustss {
   1750       1.248       mrg 	int n, running;
   1751   1.264.4.1     skrll 	uint16_t cmd;
   1752         1.1  augustss 
   1753  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1754  1.264.4.21     skrll 
   1755         1.1  augustss 	run = run != 0;
   1756       1.249  drochner 	if (!locked)
   1757       1.249  drochner 		mutex_spin_enter(&sc->sc_intr_lock);
   1758  1.264.4.21     skrll 
   1759  1.264.4.27     skrll 	DPRINTF("setting run=%d", run, 0, 0, 0);
   1760        1.71  augustss 	cmd = UREAD2(sc, UHCI_CMD);
   1761        1.71  augustss 	if (run)
   1762        1.71  augustss 		cmd |= UHCI_CMD_RS;
   1763        1.71  augustss 	else
   1764        1.71  augustss 		cmd &= ~UHCI_CMD_RS;
   1765        1.71  augustss 	UHCICMD(sc, cmd);
   1766  1.264.4.54     skrll 	for (n = 0; n < 10; n++) {
   1767         1.1  augustss 		running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH);
   1768         1.1  augustss 		/* return when we've entered the state we want */
   1769         1.1  augustss 		if (run == running) {
   1770       1.249  drochner 			if (!locked)
   1771       1.249  drochner 				mutex_spin_exit(&sc->sc_intr_lock);
   1772  1.264.4.27     skrll 			DPRINTF("done cmd=0x%x sts=0x%x",
   1773  1.264.4.21     skrll 			    UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 0, 0);
   1774  1.264.4.13     skrll 			return USBD_NORMAL_COMPLETION;
   1775         1.1  augustss 		}
   1776       1.248       mrg 		usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock);
   1777         1.1  augustss 	}
   1778       1.249  drochner 	if (!locked)
   1779       1.249  drochner 		mutex_spin_exit(&sc->sc_intr_lock);
   1780       1.216  drochner 	printf("%s: cannot %s\n", device_xname(sc->sc_dev),
   1781        1.14  augustss 	       run ? "start" : "stop");
   1782  1.264.4.13     skrll 	return USBD_IOERROR;
   1783         1.1  augustss }
   1784         1.1  augustss 
   1785         1.1  augustss /*
   1786         1.1  augustss  * Memory management routines.
   1787         1.1  augustss  *  uhci_alloc_std allocates TDs
   1788         1.1  augustss  *  uhci_alloc_sqh allocates QHs
   1789         1.7  augustss  * These two routines do their own free list management,
   1790         1.1  augustss  * partly for speed, partly because allocating DMAable memory
   1791  1.264.4.28     skrll  * has page size granularity so much memory would be wasted if
   1792        1.16  augustss  * only one TD/QH (32 bytes) was placed in each allocated chunk.
   1793         1.1  augustss  */
   1794         1.1  augustss 
   1795         1.1  augustss uhci_soft_td_t *
   1796       1.119  augustss uhci_alloc_std(uhci_softc_t *sc)
   1797         1.1  augustss {
   1798         1.1  augustss 	uhci_soft_td_t *std;
   1799        1.63  augustss 	usbd_status err;
   1800        1.42  augustss 	int i, offs;
   1801         1.7  augustss 	usb_dma_t dma;
   1802         1.1  augustss 
   1803  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1804  1.264.4.21     skrll 
   1805        1.63  augustss 	if (sc->sc_freetds == NULL) {
   1806  1.264.4.21     skrll 		DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
   1807        1.63  augustss 		err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK,
   1808        1.63  augustss 			  UHCI_TD_ALIGN, &dma);
   1809        1.63  augustss 		if (err)
   1810  1.264.4.52     skrll 			return NULL;
   1811       1.248       mrg 		for (i = 0; i < UHCI_STD_CHUNK; i++) {
   1812        1.42  augustss 			offs = i * UHCI_STD_SIZE;
   1813       1.159  augustss 			std = KERNADDR(&dma, offs);
   1814       1.160  augustss 			std->physaddr = DMAADDR(&dma, offs);
   1815       1.223    bouyer 			std->dma = dma;
   1816       1.223    bouyer 			std->offs = offs;
   1817        1.42  augustss 			std->link.std = sc->sc_freetds;
   1818         1.1  augustss 			sc->sc_freetds = std;
   1819         1.1  augustss 		}
   1820         1.1  augustss 	}
   1821         1.1  augustss 	std = sc->sc_freetds;
   1822        1.42  augustss 	sc->sc_freetds = std->link.std;
   1823        1.42  augustss 	memset(&std->td, 0, sizeof(uhci_td_t));
   1824         1.1  augustss 	return std;
   1825         1.1  augustss }
   1826         1.1  augustss 
   1827         1.1  augustss void
   1828       1.119  augustss uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std)
   1829         1.1  augustss {
   1830         1.7  augustss #ifdef DIAGNOSTIC
   1831         1.7  augustss #define TD_IS_FREE 0x12345678
   1832        1.88   tsutsui 	if (le32toh(std->td.td_token) == TD_IS_FREE) {
   1833         1.7  augustss 		printf("uhci_free_std: freeing free TD %p\n", std);
   1834         1.7  augustss 		return;
   1835         1.7  augustss 	}
   1836        1.88   tsutsui 	std->td.td_token = htole32(TD_IS_FREE);
   1837         1.7  augustss #endif
   1838        1.42  augustss 	std->link.std = sc->sc_freetds;
   1839         1.1  augustss 	sc->sc_freetds = std;
   1840         1.1  augustss }
   1841         1.1  augustss 
   1842         1.1  augustss uhci_soft_qh_t *
   1843       1.119  augustss uhci_alloc_sqh(uhci_softc_t *sc)
   1844         1.1  augustss {
   1845         1.1  augustss 	uhci_soft_qh_t *sqh;
   1846        1.63  augustss 	usbd_status err;
   1847         1.1  augustss 	int i, offs;
   1848         1.7  augustss 	usb_dma_t dma;
   1849         1.1  augustss 
   1850  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1851  1.264.4.21     skrll 
   1852        1.63  augustss 	if (sc->sc_freeqhs == NULL) {
   1853  1.264.4.21     skrll 		DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
   1854        1.63  augustss 		err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK,
   1855        1.63  augustss 			  UHCI_QH_ALIGN, &dma);
   1856        1.63  augustss 		if (err)
   1857  1.264.4.52     skrll 			return NULL;
   1858  1.264.4.54     skrll 		for (i = 0; i < UHCI_SQH_CHUNK; i++) {
   1859        1.42  augustss 			offs = i * UHCI_SQH_SIZE;
   1860       1.159  augustss 			sqh = KERNADDR(&dma, offs);
   1861       1.160  augustss 			sqh->physaddr = DMAADDR(&dma, offs);
   1862       1.223    bouyer 			sqh->dma = dma;
   1863       1.223    bouyer 			sqh->offs = offs;
   1864        1.42  augustss 			sqh->hlink = sc->sc_freeqhs;
   1865         1.1  augustss 			sc->sc_freeqhs = sqh;
   1866         1.1  augustss 		}
   1867         1.1  augustss 	}
   1868         1.1  augustss 	sqh = sc->sc_freeqhs;
   1869        1.42  augustss 	sc->sc_freeqhs = sqh->hlink;
   1870        1.42  augustss 	memset(&sqh->qh, 0, sizeof(uhci_qh_t));
   1871  1.264.4.13     skrll 	return sqh;
   1872         1.1  augustss }
   1873         1.1  augustss 
   1874         1.1  augustss void
   1875       1.119  augustss uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   1876         1.1  augustss {
   1877        1.42  augustss 	sqh->hlink = sc->sc_freeqhs;
   1878         1.1  augustss 	sc->sc_freeqhs = sqh;
   1879         1.1  augustss }
   1880         1.1  augustss 
   1881         1.1  augustss void
   1882       1.119  augustss uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std,
   1883       1.119  augustss 		    uhci_soft_td_t *stdend)
   1884         1.1  augustss {
   1885         1.1  augustss 	uhci_soft_td_t *p;
   1886       1.256   tsutsui 	uint32_t td_link;
   1887         1.1  augustss 
   1888       1.223    bouyer 	/*
   1889       1.223    bouyer 	 * to avoid race condition with the controller which may be looking
   1890       1.223    bouyer 	 * at this chain, we need to first invalidate all links, and
   1891       1.223    bouyer 	 * then wait for the controller to move to another queue
   1892       1.223    bouyer 	 */
   1893       1.223    bouyer 	for (p = std; p != stdend; p = p->link.std) {
   1894       1.223    bouyer 		usb_syncmem(&p->dma,
   1895       1.223    bouyer 		    p->offs + offsetof(uhci_td_t, td_link),
   1896       1.223    bouyer 		    sizeof(p->td.td_link),
   1897       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1898       1.256   tsutsui 		td_link = le32toh(p->td.td_link);
   1899       1.256   tsutsui 		usb_syncmem(&p->dma,
   1900       1.256   tsutsui 		    p->offs + offsetof(uhci_td_t, td_link),
   1901       1.256   tsutsui 		    sizeof(p->td.td_link),
   1902       1.256   tsutsui 		    BUS_DMASYNC_PREREAD);
   1903       1.256   tsutsui 		if ((td_link & UHCI_PTR_T) == 0) {
   1904       1.255   tsutsui 			p->td.td_link = htole32(UHCI_PTR_T);
   1905       1.223    bouyer 			usb_syncmem(&p->dma,
   1906       1.223    bouyer 			    p->offs + offsetof(uhci_td_t, td_link),
   1907       1.223    bouyer 			    sizeof(p->td.td_link),
   1908       1.223    bouyer 			    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   1909       1.223    bouyer 		}
   1910       1.223    bouyer 	}
   1911       1.223    bouyer 	delay(UHCI_QH_REMOVE_DELAY);
   1912       1.223    bouyer 
   1913         1.1  augustss 	for (; std != stdend; std = p) {
   1914        1.42  augustss 		p = std->link.std;
   1915         1.1  augustss 		uhci_free_std(sc, std);
   1916         1.1  augustss 	}
   1917         1.1  augustss }
   1918         1.1  augustss 
   1919         1.1  augustss usbd_status
   1920       1.119  augustss uhci_alloc_std_chain(struct uhci_pipe *upipe, uhci_softc_t *sc, int len,
   1921   1.264.4.1     skrll 		     int rd, uint16_t flags, usb_dma_t *dma,
   1922       1.119  augustss 		     uhci_soft_td_t **sp, uhci_soft_td_t **ep)
   1923         1.1  augustss {
   1924         1.1  augustss 	uhci_soft_td_t *p, *lastp;
   1925         1.1  augustss 	uhci_physaddr_t lastlink;
   1926         1.1  augustss 	int i, ntd, l, tog, maxp;
   1927   1.264.4.1     skrll 	uint32_t status;
   1928   1.264.4.7     skrll 	int addr = upipe->pipe.up_dev->ud_addr;
   1929   1.264.4.7     skrll 	int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
   1930         1.1  augustss 
   1931  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1932  1.264.4.21     skrll 
   1933  1.264.4.21     skrll 	DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d",
   1934  1.264.4.21     skrll 	    addr, UE_GET_ADDR(endpt), len, upipe->pipe.up_dev->ud_speed);
   1935       1.248       mrg 
   1936   1.264.4.7     skrll 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
   1937       1.248       mrg 
   1938   1.264.4.7     skrll 	maxp = UGETW(upipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize);
   1939         1.1  augustss 	if (maxp == 0) {
   1940         1.1  augustss 		printf("uhci_alloc_std_chain: maxp=0\n");
   1941  1.264.4.13     skrll 		return USBD_INVAL;
   1942         1.1  augustss 	}
   1943         1.1  augustss 	ntd = (len + maxp - 1) / maxp;
   1944        1.73  augustss 	if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0)
   1945        1.73  augustss 		ntd++;
   1946  1.264.4.21     skrll 	DPRINTFN(10, "maxp=%d ntd=%d",
   1947  1.264.4.21     skrll 	    maxp, ntd, 0, 0);
   1948  1.264.4.21     skrll 
   1949        1.73  augustss 	if (ntd == 0) {
   1950  1.264.4.26     skrll 		*sp = *ep = NULL;
   1951  1.264.4.27     skrll 		DPRINTF("ntd=0", 0, 0, 0, 0);
   1952  1.264.4.13     skrll 		return USBD_NORMAL_COMPLETION;
   1953        1.73  augustss 	}
   1954        1.38  augustss 	tog = upipe->nexttoggle;
   1955         1.1  augustss 	if (ntd % 2 == 0)
   1956         1.1  augustss 		tog ^= 1;
   1957        1.32  augustss 	upipe->nexttoggle = tog ^ 1;
   1958       1.121  augustss 	lastp = NULL;
   1959         1.1  augustss 	lastlink = UHCI_PTR_T;
   1960         1.1  augustss 	ntd--;
   1961        1.33  augustss 	status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE);
   1962   1.264.4.7     skrll 	if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW)
   1963        1.18  augustss 		status |= UHCI_TD_LS;
   1964        1.73  augustss 	if (flags & USBD_SHORT_XFER_OK)
   1965        1.18  augustss 		status |= UHCI_TD_SPD;
   1966       1.223    bouyer 	usb_syncmem(dma, 0, len,
   1967       1.223    bouyer 	    rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
   1968         1.1  augustss 	for (i = ntd; i >= 0; i--) {
   1969         1.1  augustss 		p = uhci_alloc_std(sc);
   1970        1.63  augustss 		if (p == NULL) {
   1971       1.202  christos 			KASSERT(lastp != NULL);
   1972       1.149  augustss 			uhci_free_std_chain(sc, lastp, NULL);
   1973  1.264.4.13     skrll 			return USBD_NOMEM;
   1974         1.1  augustss 		}
   1975        1.42  augustss 		p->link.std = lastp;
   1976       1.121  augustss 		p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD);
   1977         1.1  augustss 		lastp = p;
   1978         1.1  augustss 		lastlink = p->physaddr;
   1979        1.88   tsutsui 		p->td.td_status = htole32(status);
   1980         1.1  augustss 		if (i == ntd) {
   1981         1.1  augustss 			/* last TD */
   1982         1.1  augustss 			l = len % maxp;
   1983        1.73  augustss 			if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER))
   1984        1.73  augustss 				l = maxp;
   1985         1.1  augustss 			*ep = p;
   1986         1.1  augustss 		} else
   1987         1.1  augustss 			l = maxp;
   1988       1.152  augustss 		p->td.td_token =
   1989        1.88   tsutsui 		    htole32(rd ? UHCI_TD_IN (l, endpt, addr, tog) :
   1990        1.88   tsutsui 				 UHCI_TD_OUT(l, endpt, addr, tog));
   1991       1.160  augustss 		p->td.td_buffer = htole32(DMAADDR(dma, i * maxp));
   1992       1.223    bouyer 		usb_syncmem(&p->dma, p->offs, sizeof(p->td),
   1993       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   1994         1.1  augustss 		tog ^= 1;
   1995         1.1  augustss 	}
   1996         1.1  augustss 	*sp = lastp;
   1997  1.264.4.21     skrll 	DPRINTFN(10, "nexttog=%d", upipe->nexttoggle,
   1998  1.264.4.21     skrll 	    0, 0, 0);
   1999  1.264.4.21     skrll 
   2000  1.264.4.13     skrll 	return USBD_NORMAL_COMPLETION;
   2001         1.1  augustss }
   2002         1.1  augustss 
   2003        1.38  augustss void
   2004  1.264.4.25     skrll uhci_device_clear_toggle(struct usbd_pipe *pipe)
   2005        1.38  augustss {
   2006  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
   2007        1.38  augustss 	upipe->nexttoggle = 0;
   2008        1.38  augustss }
   2009        1.38  augustss 
   2010        1.38  augustss void
   2011  1.264.4.25     skrll uhci_noop(struct usbd_pipe *pipe)
   2012        1.38  augustss {
   2013        1.38  augustss }
   2014        1.38  augustss 
   2015         1.1  augustss usbd_status
   2016  1.264.4.25     skrll uhci_device_bulk_transfer(struct usbd_xfer *xfer)
   2017         1.1  augustss {
   2018  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2019        1.63  augustss 	usbd_status err;
   2020        1.16  augustss 
   2021        1.52  augustss 	/* Insert last in queue. */
   2022       1.248       mrg 	mutex_enter(&sc->sc_lock);
   2023        1.63  augustss 	err = usb_insert_transfer(xfer);
   2024       1.248       mrg 	mutex_exit(&sc->sc_lock);
   2025        1.63  augustss 	if (err)
   2026  1.264.4.13     skrll 		return err;
   2027        1.52  augustss 
   2028       1.152  augustss 	/*
   2029        1.92  augustss 	 * Pipe isn't running (otherwise err would be USBD_INPROG),
   2030        1.92  augustss 	 * so start it first.
   2031        1.67  augustss 	 */
   2032  1.264.4.13     skrll 	return uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
   2033        1.16  augustss }
   2034        1.16  augustss 
   2035        1.16  augustss usbd_status
   2036  1.264.4.25     skrll uhci_device_bulk_start(struct usbd_xfer *xfer)
   2037        1.16  augustss {
   2038  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   2039  1.264.4.39     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   2040  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2041        1.55  augustss 	uhci_soft_td_t *data, *dataend;
   2042         1.1  augustss 	uhci_soft_qh_t *sqh;
   2043        1.63  augustss 	usbd_status err;
   2044        1.45  augustss 	int len, isread, endpt;
   2045         1.1  augustss 
   2046  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2047  1.264.4.39     skrll 	DPRINTFN(3, "xfer=%p len=%d flags=%d ux=%p",
   2048  1.264.4.39     skrll 	     xfer, xfer->ux_length, xfer->ux_flags, ux);
   2049         1.1  augustss 
   2050        1.82  augustss 	if (sc->sc_dying)
   2051  1.264.4.13     skrll 		return USBD_IOERROR;
   2052        1.82  augustss 
   2053  1.264.4.31     skrll 	KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
   2054         1.1  augustss 
   2055       1.248       mrg 	mutex_enter(&sc->sc_lock);
   2056       1.248       mrg 
   2057   1.264.4.7     skrll 	len = xfer->ux_length;
   2058   1.264.4.7     skrll 	endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
   2059        1.45  augustss 	isread = UE_GET_DIR(endpt) == UE_DIR_IN;
   2060  1.264.4.33     skrll 	sqh = upipe->bulk.sqh;
   2061         1.1  augustss 
   2062  1.264.4.33     skrll 	upipe->bulk.isread = isread;
   2063  1.264.4.33     skrll 	upipe->bulk.length = len;
   2064         1.1  augustss 
   2065   1.264.4.7     skrll 	err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->ux_flags,
   2066   1.264.4.7     skrll 				   &xfer->ux_dmabuf, &data, &dataend);
   2067       1.248       mrg 	if (err) {
   2068       1.248       mrg 		mutex_exit(&sc->sc_lock);
   2069  1.264.4.13     skrll 		return err;
   2070       1.248       mrg 	}
   2071        1.88   tsutsui 	dataend->td.td_status |= htole32(UHCI_TD_IOC);
   2072       1.223    bouyer 	usb_syncmem(&dataend->dma,
   2073       1.223    bouyer 	    dataend->offs + offsetof(uhci_td_t, td_status),
   2074       1.223    bouyer 	    sizeof(dataend->td.td_status),
   2075       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2076       1.223    bouyer 
   2077         1.1  augustss 
   2078        1.59  augustss #ifdef UHCI_DEBUG
   2079  1.264.4.43     skrll 	if (uhcidebug >= 8) {
   2080  1.264.4.47     skrll 		DPRINTF("--- dump start ---", 0, 0, 0, 0);
   2081  1.264.4.21     skrll 		DPRINTFN(8, "data(1)", 0, 0, 0, 0);
   2082        1.55  augustss 		uhci_dump_tds(data);
   2083  1.264.4.47     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   2084         1.1  augustss 	}
   2085         1.1  augustss #endif
   2086         1.1  augustss 
   2087         1.1  augustss 	/* Set up interrupt info. */
   2088  1.264.4.41     skrll 	ux->ux_stdstart = data;
   2089  1.264.4.41     skrll 	ux->ux_stdend = dataend;
   2090  1.264.4.31     skrll 
   2091  1.264.4.41     skrll 	KASSERT(ux->ux_isdone);
   2092         1.7  augustss #ifdef DIAGNOSTIC
   2093  1.264.4.41     skrll 	ux->ux_isdone = false;
   2094         1.7  augustss #endif
   2095         1.1  augustss 
   2096        1.55  augustss 	sqh->elink = data;
   2097       1.121  augustss 	sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD);
   2098       1.223    bouyer 	/* uhci_add_bulk() will do usb_syncmem(sqh) */
   2099         1.1  augustss 
   2100         1.1  augustss 	uhci_add_bulk(sc, sqh);
   2101  1.264.4.39     skrll 	uhci_add_intr_info(sc, ux);
   2102         1.1  augustss 
   2103   1.264.4.7     skrll 	if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
   2104   1.264.4.7     skrll 		callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
   2105  1.264.4.39     skrll 			    uhci_timeout, xfer);
   2106        1.13  augustss 	}
   2107   1.264.4.7     skrll 	xfer->ux_status = USBD_IN_PROGRESS;
   2108         1.1  augustss 
   2109        1.59  augustss #ifdef UHCI_DEBUG
   2110  1.264.4.43     skrll 	if (uhcidebug >= 10) {
   2111  1.264.4.47     skrll 		DPRINTF("--- dump start ---", 0, 0, 0, 0);
   2112  1.264.4.21     skrll 		DPRINTFN(10, "data(2)", 0, 0, 0, 0);
   2113        1.55  augustss 		uhci_dump_tds(data);
   2114  1.264.4.47     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   2115         1.1  augustss 	}
   2116         1.1  augustss #endif
   2117         1.1  augustss 
   2118   1.264.4.7     skrll 	if (sc->sc_bus.ub_usepolling)
   2119        1.63  augustss 		uhci_waitintr(sc, xfer);
   2120        1.26  augustss 
   2121       1.248       mrg 	mutex_exit(&sc->sc_lock);
   2122  1.264.4.13     skrll 	return USBD_IN_PROGRESS;
   2123         1.1  augustss }
   2124         1.1  augustss 
   2125         1.1  augustss /* Abort a device bulk request. */
   2126         1.1  augustss void
   2127  1.264.4.25     skrll uhci_device_bulk_abort(struct usbd_xfer *xfer)
   2128         1.1  augustss {
   2129  1.264.4.37     skrll 	uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer);
   2130       1.248       mrg 
   2131       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2132       1.248       mrg 
   2133  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2134  1.264.4.21     skrll 
   2135        1.66  augustss 	uhci_abort_xfer(xfer, USBD_CANCELLED);
   2136        1.33  augustss }
   2137        1.33  augustss 
   2138        1.92  augustss /*
   2139       1.154  augustss  * Abort a device request.
   2140       1.154  augustss  * If this routine is called at splusb() it guarantees that the request
   2141       1.154  augustss  * will be removed from the hardware scheduling and that the callback
   2142       1.154  augustss  * for it will be called with USBD_CANCELLED status.
   2143       1.154  augustss  * It's impossible to guarantee that the requested transfer will not
   2144       1.154  augustss  * have happened since the hardware runs concurrently.
   2145       1.154  augustss  * If the transaction has already happened we rely on the ordinary
   2146       1.154  augustss  * interrupt processing to process it.
   2147       1.248       mrg  * XXX This is most probably wrong.
   2148       1.248       mrg  * XXXMRG this doesn't make sense anymore.
   2149        1.92  augustss  */
   2150        1.33  augustss void
   2151  1.264.4.25     skrll uhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status)
   2152        1.33  augustss {
   2153  1.264.4.39     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   2154  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   2155  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2156        1.33  augustss 	uhci_soft_td_t *std;
   2157       1.188  augustss 	int wake;
   2158        1.65  augustss 
   2159  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2160  1.264.4.21     skrll 	DPRINTFN(1,"xfer=%p, status=%d", xfer, status, 0, 0);
   2161        1.33  augustss 
   2162       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2163   1.264.4.3     skrll 	ASSERT_SLEEPABLE();
   2164       1.248       mrg 
   2165       1.153  augustss 	if (sc->sc_dying) {
   2166       1.153  augustss 		/* If we're dying, just do the software part. */
   2167   1.264.4.7     skrll 		xfer->ux_status = status;	/* make software ignore it */
   2168   1.264.4.7     skrll 		callout_stop(&xfer->ux_callout);
   2169       1.153  augustss 		usb_transfer_complete(xfer);
   2170       1.194  christos 		return;
   2171        1.92  augustss 	}
   2172        1.92  augustss 
   2173       1.153  augustss 	/*
   2174       1.188  augustss 	 * If an abort is already in progress then just wait for it to
   2175       1.188  augustss 	 * complete and return.
   2176       1.188  augustss 	 */
   2177   1.264.4.7     skrll 	if (xfer->ux_hcflags & UXFER_ABORTING) {
   2178  1.264.4.21     skrll 		DPRINTFN(2, "already aborting", 0, 0, 0, 0);
   2179       1.188  augustss #ifdef DIAGNOSTIC
   2180       1.188  augustss 		if (status == USBD_TIMEOUT)
   2181       1.188  augustss 			printf("uhci_abort_xfer: TIMEOUT while aborting\n");
   2182       1.188  augustss #endif
   2183       1.188  augustss 		/* Override the status which might be USBD_TIMEOUT. */
   2184   1.264.4.7     skrll 		xfer->ux_status = status;
   2185  1.264.4.21     skrll 		DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0);
   2186   1.264.4.7     skrll 		xfer->ux_hcflags |= UXFER_ABORTWAIT;
   2187   1.264.4.7     skrll 		while (xfer->ux_hcflags & UXFER_ABORTING)
   2188   1.264.4.7     skrll 			cv_wait(&xfer->ux_hccv, &sc->sc_lock);
   2189       1.248       mrg 		goto done;
   2190       1.188  augustss 	}
   2191   1.264.4.7     skrll 	xfer->ux_hcflags |= UXFER_ABORTING;
   2192       1.188  augustss 
   2193       1.188  augustss 	/*
   2194       1.153  augustss 	 * Step 1: Make interrupt routine and hardware ignore xfer.
   2195       1.153  augustss 	 */
   2196   1.264.4.7     skrll 	xfer->ux_status = status;	/* make software ignore it */
   2197   1.264.4.7     skrll 	callout_stop(&xfer->ux_callout);
   2198  1.264.4.39     skrll 	DPRINTF("stop ux=%p", ux, 0, 0, 0);
   2199  1.264.4.41     skrll 	for (std = ux->ux_stdstart; std != NULL; std = std->link.std) {
   2200       1.223    bouyer 		usb_syncmem(&std->dma,
   2201       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_status),
   2202       1.223    bouyer 		    sizeof(std->td.td_status),
   2203       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   2204        1.92  augustss 		std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC));
   2205       1.223    bouyer 		usb_syncmem(&std->dma,
   2206       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_status),
   2207       1.223    bouyer 		    sizeof(std->td.td_status),
   2208       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2209       1.223    bouyer 	}
   2210        1.92  augustss 
   2211       1.162  augustss 	/*
   2212       1.153  augustss 	 * Step 2: Wait until we know hardware has finished any possible
   2213       1.153  augustss 	 * use of the xfer.  Also make sure the soft interrupt routine
   2214       1.153  augustss 	 * has run.
   2215       1.153  augustss 	 */
   2216       1.248       mrg 	/* Hardware finishes in 1ms */
   2217   1.264.4.7     skrll 	usb_delay_ms_locked(upipe->pipe.up_dev->ud_bus, 2, &sc->sc_lock);
   2218       1.153  augustss 	sc->sc_softwake = 1;
   2219       1.153  augustss 	usb_schedsoftintr(&sc->sc_bus);
   2220  1.264.4.27     skrll 	DPRINTF("cv_wait", 0, 0, 0, 0);
   2221       1.248       mrg 	cv_wait(&sc->sc_softwake_cv, &sc->sc_lock);
   2222       1.162  augustss 
   2223       1.153  augustss 	/*
   2224       1.153  augustss 	 * Step 3: Execute callback.
   2225       1.153  augustss 	 */
   2226  1.264.4.27     skrll 	DPRINTF("callback", 0, 0, 0, 0);
   2227       1.100  augustss #ifdef DIAGNOSTIC
   2228  1.264.4.41     skrll 	ux->ux_isdone = true;
   2229       1.100  augustss #endif
   2230   1.264.4.7     skrll 	wake = xfer->ux_hcflags & UXFER_ABORTWAIT;
   2231   1.264.4.7     skrll 	xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT);
   2232       1.106  augustss 	usb_transfer_complete(xfer);
   2233       1.188  augustss 	if (wake)
   2234   1.264.4.7     skrll 		cv_broadcast(&xfer->ux_hccv);
   2235       1.248       mrg done:
   2236       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2237         1.1  augustss }
   2238         1.1  augustss 
   2239         1.1  augustss /* Close a device bulk pipe. */
   2240         1.1  augustss void
   2241  1.264.4.25     skrll uhci_device_bulk_close(struct usbd_pipe *pipe)
   2242         1.1  augustss {
   2243  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
   2244  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
   2245         1.1  augustss 
   2246       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2247       1.248       mrg 
   2248  1.264.4.33     skrll 	uhci_free_sqh(sc, upipe->bulk.sqh);
   2249       1.236  drochner 
   2250   1.264.4.7     skrll 	pipe->up_endpoint->ue_toggle = upipe->nexttoggle;
   2251         1.1  augustss }
   2252         1.1  augustss 
   2253         1.1  augustss usbd_status
   2254  1.264.4.25     skrll uhci_device_ctrl_transfer(struct usbd_xfer *xfer)
   2255         1.1  augustss {
   2256  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2257        1.63  augustss 	usbd_status err;
   2258        1.16  augustss 
   2259        1.52  augustss 	/* Insert last in queue. */
   2260       1.248       mrg 	mutex_enter(&sc->sc_lock);
   2261        1.63  augustss 	err = usb_insert_transfer(xfer);
   2262       1.248       mrg 	mutex_exit(&sc->sc_lock);
   2263        1.63  augustss 	if (err)
   2264  1.264.4.13     skrll 		return err;
   2265        1.52  augustss 
   2266       1.152  augustss 	/*
   2267        1.92  augustss 	 * Pipe isn't running (otherwise err would be USBD_INPROG),
   2268        1.92  augustss 	 * so start it first.
   2269        1.67  augustss 	 */
   2270  1.264.4.13     skrll 	return uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
   2271        1.16  augustss }
   2272        1.16  augustss 
   2273        1.16  augustss usbd_status
   2274  1.264.4.25     skrll uhci_device_ctrl_start(struct usbd_xfer *xfer)
   2275        1.16  augustss {
   2276  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2277        1.63  augustss 	usbd_status err;
   2278         1.1  augustss 
   2279        1.82  augustss 	if (sc->sc_dying)
   2280  1.264.4.13     skrll 		return USBD_IOERROR;
   2281        1.82  augustss 
   2282  1.264.4.31     skrll 	KASSERT(xfer->ux_rqflags & URQ_REQUEST);
   2283         1.1  augustss 
   2284       1.248       mrg 	mutex_enter(&sc->sc_lock);
   2285        1.63  augustss 	err = uhci_device_request(xfer);
   2286       1.248       mrg 	mutex_exit(&sc->sc_lock);
   2287        1.63  augustss 	if (err)
   2288  1.264.4.13     skrll 		return err;
   2289         1.1  augustss 
   2290   1.264.4.7     skrll 	if (sc->sc_bus.ub_usepolling)
   2291        1.63  augustss 		uhci_waitintr(sc, xfer);
   2292  1.264.4.13     skrll 	return USBD_IN_PROGRESS;
   2293         1.1  augustss }
   2294         1.1  augustss 
   2295         1.1  augustss usbd_status
   2296  1.264.4.25     skrll uhci_device_intr_transfer(struct usbd_xfer *xfer)
   2297         1.1  augustss {
   2298  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2299        1.63  augustss 	usbd_status err;
   2300        1.16  augustss 
   2301        1.52  augustss 	/* Insert last in queue. */
   2302       1.248       mrg 	mutex_enter(&sc->sc_lock);
   2303        1.63  augustss 	err = usb_insert_transfer(xfer);
   2304       1.248       mrg 	mutex_exit(&sc->sc_lock);
   2305        1.63  augustss 	if (err)
   2306  1.264.4.13     skrll 		return err;
   2307        1.52  augustss 
   2308       1.152  augustss 	/*
   2309        1.92  augustss 	 * Pipe isn't running (otherwise err would be USBD_INPROG),
   2310        1.92  augustss 	 * so start it first.
   2311        1.67  augustss 	 */
   2312  1.264.4.13     skrll 	return uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
   2313        1.16  augustss }
   2314        1.16  augustss 
   2315        1.16  augustss usbd_status
   2316  1.264.4.25     skrll uhci_device_intr_start(struct usbd_xfer *xfer)
   2317        1.16  augustss {
   2318  1.264.4.39     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   2319  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   2320  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2321        1.55  augustss 	uhci_soft_td_t *data, *dataend;
   2322         1.1  augustss 	uhci_soft_qh_t *sqh;
   2323        1.63  augustss 	usbd_status err;
   2324       1.187     skrll 	int isread, endpt;
   2325       1.248       mrg 	int i;
   2326         1.1  augustss 
   2327        1.82  augustss 	if (sc->sc_dying)
   2328  1.264.4.13     skrll 		return USBD_IOERROR;
   2329        1.82  augustss 
   2330  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2331  1.264.4.21     skrll 
   2332  1.264.4.21     skrll 	DPRINTFN(3, "xfer=%p len=%d flags=%d",
   2333  1.264.4.21     skrll 	    xfer, xfer->ux_length, xfer->ux_flags, 0);
   2334         1.1  augustss 
   2335  1.264.4.31     skrll 	KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
   2336         1.1  augustss 
   2337       1.248       mrg 	mutex_enter(&sc->sc_lock);
   2338       1.248       mrg 
   2339   1.264.4.7     skrll 	endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
   2340       1.187     skrll 	isread = UE_GET_DIR(endpt) == UE_DIR_IN;
   2341       1.187     skrll 
   2342  1.264.4.33     skrll 	upipe->intr.isread = isread;
   2343       1.187     skrll 
   2344   1.264.4.7     skrll 	err = uhci_alloc_std_chain(upipe, sc, xfer->ux_length, isread,
   2345   1.264.4.7     skrll 				   xfer->ux_flags, &xfer->ux_dmabuf, &data,
   2346       1.187     skrll 				   &dataend);
   2347       1.248       mrg 	if (err) {
   2348       1.248       mrg 		mutex_exit(&sc->sc_lock);
   2349  1.264.4.13     skrll 		return err;
   2350       1.248       mrg 	}
   2351       1.248       mrg 
   2352        1.88   tsutsui 	dataend->td.td_status |= htole32(UHCI_TD_IOC);
   2353       1.223    bouyer 	usb_syncmem(&dataend->dma,
   2354       1.223    bouyer 	    dataend->offs + offsetof(uhci_td_t, td_status),
   2355       1.223    bouyer 	    sizeof(dataend->td.td_status),
   2356       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2357         1.1  augustss 
   2358        1.59  augustss #ifdef UHCI_DEBUG
   2359  1.264.4.43     skrll 	if (uhcidebug >= 10) {
   2360  1.264.4.47     skrll 		DPRINTF("--- dump start ---", 0, 0, 0, 0);
   2361        1.55  augustss 		uhci_dump_tds(data);
   2362  1.264.4.33     skrll 		uhci_dump_qh(upipe->intr.qhs[0]);
   2363  1.264.4.47     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   2364         1.1  augustss 	}
   2365         1.1  augustss #endif
   2366         1.1  augustss 
   2367         1.1  augustss 	/* Set up interrupt info. */
   2368  1.264.4.41     skrll 	ux->ux_stdstart = data;
   2369  1.264.4.41     skrll 	ux->ux_stdend = dataend;
   2370  1.264.4.41     skrll 	KASSERT(ux->ux_isdone);
   2371         1.7  augustss #ifdef DIAGNOSTIC
   2372  1.264.4.41     skrll 	ux->ux_isdone = false;
   2373         1.7  augustss #endif
   2374         1.1  augustss 
   2375  1.264.4.33     skrll 	DPRINTFN(10, "qhs[0]=%p", upipe->intr.qhs[0], 0, 0, 0);
   2376  1.264.4.33     skrll 	for (i = 0; i < upipe->intr.npoll; i++) {
   2377  1.264.4.33     skrll 		sqh = upipe->intr.qhs[i];
   2378        1.55  augustss 		sqh->elink = data;
   2379       1.121  augustss 		sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD);
   2380       1.223    bouyer 		usb_syncmem(&sqh->dma,
   2381       1.223    bouyer 		    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   2382       1.223    bouyer 		    sizeof(sqh->qh.qh_elink),
   2383       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2384         1.1  augustss 	}
   2385  1.264.4.39     skrll 	uhci_add_intr_info(sc, ux);
   2386   1.264.4.7     skrll 	xfer->ux_status = USBD_IN_PROGRESS;
   2387       1.248       mrg 	mutex_exit(&sc->sc_lock);
   2388         1.1  augustss 
   2389        1.59  augustss #ifdef UHCI_DEBUG
   2390  1.264.4.43     skrll 	if (uhcidebug >= 10) {
   2391  1.264.4.47     skrll 		DPRINTF("--- dump start ---", 0, 0, 0, 0);
   2392        1.55  augustss 		uhci_dump_tds(data);
   2393  1.264.4.33     skrll 		uhci_dump_qh(upipe->intr.qhs[0]);
   2394  1.264.4.47     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   2395         1.1  augustss 	}
   2396         1.1  augustss #endif
   2397         1.1  augustss 
   2398  1.264.4.13     skrll 	return USBD_IN_PROGRESS;
   2399         1.1  augustss }
   2400         1.1  augustss 
   2401         1.1  augustss /* Abort a device control request. */
   2402         1.1  augustss void
   2403  1.264.4.25     skrll uhci_device_ctrl_abort(struct usbd_xfer *xfer)
   2404         1.1  augustss {
   2405  1.264.4.37     skrll 	uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer);
   2406       1.248       mrg 
   2407       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2408       1.248       mrg 
   2409  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2410        1.66  augustss 	uhci_abort_xfer(xfer, USBD_CANCELLED);
   2411         1.1  augustss }
   2412         1.1  augustss 
   2413         1.1  augustss /* Close a device control pipe. */
   2414         1.1  augustss void
   2415  1.264.4.25     skrll uhci_device_ctrl_close(struct usbd_pipe *pipe)
   2416         1.1  augustss {
   2417         1.1  augustss }
   2418         1.1  augustss 
   2419         1.1  augustss /* Abort a device interrupt request. */
   2420         1.1  augustss void
   2421  1.264.4.25     skrll uhci_device_intr_abort(struct usbd_xfer *xfer)
   2422         1.1  augustss {
   2423  1.264.4.37     skrll 	uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer);
   2424       1.248       mrg 
   2425       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2426   1.264.4.7     skrll 	KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
   2427       1.248       mrg 
   2428  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2429  1.264.4.27     skrll 	DPRINTF("xfer=%p", xfer, 0, 0, 0);
   2430       1.264     skrll 
   2431        1.66  augustss 	uhci_abort_xfer(xfer, USBD_CANCELLED);
   2432         1.1  augustss }
   2433         1.1  augustss 
   2434         1.1  augustss /* Close a device interrupt pipe. */
   2435         1.1  augustss void
   2436  1.264.4.25     skrll uhci_device_intr_close(struct usbd_pipe *pipe)
   2437         1.1  augustss {
   2438  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
   2439  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
   2440        1.92  augustss 	int i, npoll;
   2441       1.248       mrg 
   2442       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2443         1.1  augustss 
   2444         1.1  augustss 	/* Unlink descriptors from controller data structures. */
   2445  1.264.4.33     skrll 	npoll = upipe->intr.npoll;
   2446         1.1  augustss 	for (i = 0; i < npoll; i++)
   2447  1.264.4.33     skrll 		uhci_remove_intr(sc, upipe->intr.qhs[i]);
   2448         1.1  augustss 
   2449       1.152  augustss 	/*
   2450         1.1  augustss 	 * We now have to wait for any activity on the physical
   2451         1.1  augustss 	 * descriptors to stop.
   2452         1.1  augustss 	 */
   2453       1.248       mrg 	usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock);
   2454         1.1  augustss 
   2455  1.264.4.54     skrll 	for (i = 0; i < npoll; i++)
   2456  1.264.4.33     skrll 		uhci_free_sqh(sc, upipe->intr.qhs[i]);
   2457  1.264.4.33     skrll 	kmem_free(upipe->intr.qhs, npoll * sizeof(uhci_soft_qh_t *));
   2458         1.1  augustss 
   2459         1.1  augustss 	/* XXX free other resources */
   2460         1.1  augustss }
   2461         1.1  augustss 
   2462         1.1  augustss usbd_status
   2463  1.264.4.25     skrll uhci_device_request(struct usbd_xfer *xfer)
   2464         1.1  augustss {
   2465  1.264.4.39     skrll 	struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
   2466  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   2467   1.264.4.7     skrll 	usb_device_request_t *req = &xfer->ux_request;
   2468  1.264.4.25     skrll 	struct usbd_device *dev = upipe->pipe.up_dev;
   2469  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2470   1.264.4.7     skrll 	int addr = dev->ud_addr;
   2471   1.264.4.7     skrll 	int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
   2472        1.55  augustss 	uhci_soft_td_t *setup, *data, *stat, *next, *dataend;
   2473         1.1  augustss 	uhci_soft_qh_t *sqh;
   2474         1.1  augustss 	int len;
   2475   1.264.4.1     skrll 	uint32_t ls;
   2476        1.63  augustss 	usbd_status err;
   2477         1.1  augustss 	int isread;
   2478       1.248       mrg 
   2479       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2480         1.1  augustss 
   2481  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2482  1.264.4.21     skrll 	DPRINTFN(3, "type=0x%02x, request=0x%02x, "
   2483  1.264.4.21     skrll 	    "wValue=0x%04x, wIndex=0x%04x",
   2484  1.264.4.21     skrll 	    req->bmRequestType, req->bRequest, UGETW(req->wValue),
   2485  1.264.4.21     skrll 	    UGETW(req->wIndex));
   2486  1.264.4.21     skrll 	DPRINTFN(3, "len=%d, addr=%d, endpt=%d",
   2487  1.264.4.21     skrll 	    UGETW(req->wLength), dev->ud_addr, endpt, 0);
   2488         1.1  augustss 
   2489   1.264.4.7     skrll 	ls = dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0;
   2490         1.1  augustss 	isread = req->bmRequestType & UT_READ;
   2491         1.1  augustss 	len = UGETW(req->wLength);
   2492         1.1  augustss 
   2493  1.264.4.33     skrll 	setup = upipe->ctrl.setup;
   2494  1.264.4.33     skrll 	stat = upipe->ctrl.stat;
   2495  1.264.4.33     skrll 	sqh = upipe->ctrl.sqh;
   2496         1.1  augustss 
   2497         1.1  augustss 	/* Set up data transaction */
   2498         1.1  augustss 	if (len != 0) {
   2499        1.38  augustss 		upipe->nexttoggle = 1;
   2500   1.264.4.7     skrll 		err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->ux_flags,
   2501   1.264.4.7     skrll 					   &xfer->ux_dmabuf, &data, &dataend);
   2502        1.63  augustss 		if (err)
   2503  1.264.4.13     skrll 			return err;
   2504        1.55  augustss 		next = data;
   2505        1.55  augustss 		dataend->link.std = stat;
   2506       1.258     skrll 		dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD);
   2507       1.223    bouyer 		usb_syncmem(&dataend->dma,
   2508       1.223    bouyer 		    dataend->offs + offsetof(uhci_td_t, td_link),
   2509       1.223    bouyer 		    sizeof(dataend->td.td_link),
   2510       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2511         1.1  augustss 	} else {
   2512         1.1  augustss 		next = stat;
   2513         1.1  augustss 	}
   2514  1.264.4.33     skrll 	upipe->ctrl.length = len;
   2515         1.1  augustss 
   2516  1.264.4.35     skrll 	memcpy(KERNADDR(&upipe->ctrl.reqdma, 0), req, sizeof(*req));
   2517  1.264.4.35     skrll 	usb_syncmem(&upipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE);
   2518         1.1  augustss 
   2519        1.42  augustss 	setup->link.std = next;
   2520       1.258     skrll 	setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD);
   2521        1.88   tsutsui 	setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls |
   2522        1.88   tsutsui 		UHCI_TD_ACTIVE);
   2523  1.264.4.35     skrll 	setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof(*req), endpt, addr));
   2524  1.264.4.33     skrll 	setup->td.td_buffer = htole32(DMAADDR(&upipe->ctrl.reqdma, 0));
   2525       1.223    bouyer 	usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td),
   2526       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2527        1.42  augustss 
   2528        1.92  augustss 	stat->link.std = NULL;
   2529        1.88   tsutsui 	stat->td.td_link = htole32(UHCI_PTR_T);
   2530       1.152  augustss 	stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls |
   2531        1.39  augustss 		UHCI_TD_ACTIVE | UHCI_TD_IOC);
   2532       1.152  augustss 	stat->td.td_token =
   2533        1.88   tsutsui 		htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) :
   2534   1.264.4.2     skrll 				 UHCI_TD_IN (0, endpt, addr, 1));
   2535        1.88   tsutsui 	stat->td.td_buffer = htole32(0);
   2536       1.223    bouyer 	usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td),
   2537       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2538         1.1  augustss 
   2539        1.59  augustss #ifdef UHCI_DEBUG
   2540  1.264.4.43     skrll 	if (uhcidebug >= 10) {
   2541  1.264.4.47     skrll 		DPRINTF("--- dump start ---", 0, 0, 0, 0);
   2542  1.264.4.47     skrll 		DPRINTF("before transfer", 0, 0, 0, 0);
   2543        1.41  augustss 		uhci_dump_tds(setup);
   2544  1.264.4.47     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   2545         1.1  augustss 	}
   2546         1.1  augustss #endif
   2547         1.1  augustss 
   2548         1.1  augustss 	/* Set up interrupt info. */
   2549  1.264.4.41     skrll 	uxfer->ux_stdstart = setup;
   2550  1.264.4.41     skrll 	uxfer->ux_stdend = stat;
   2551  1.264.4.41     skrll 	KASSERT(uxfer->ux_isdone);
   2552         1.7  augustss #ifdef DIAGNOSTIC
   2553  1.264.4.41     skrll 	uxfer->ux_isdone = false;
   2554         1.7  augustss #endif
   2555         1.1  augustss 
   2556        1.42  augustss 	sqh->elink = setup;
   2557       1.121  augustss 	sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD);
   2558       1.223    bouyer 	/* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */
   2559         1.1  augustss 
   2560   1.264.4.7     skrll 	if (dev->ud_speed == USB_SPEED_LOW)
   2561       1.123  augustss 		uhci_add_ls_ctrl(sc, sqh);
   2562       1.123  augustss 	else
   2563       1.123  augustss 		uhci_add_hs_ctrl(sc, sqh);
   2564  1.264.4.39     skrll 	uhci_add_intr_info(sc, uxfer);
   2565        1.59  augustss #ifdef UHCI_DEBUG
   2566  1.264.4.43     skrll 	if (uhcidebug >= 12) {
   2567         1.1  augustss 		uhci_soft_td_t *std;
   2568         1.1  augustss 		uhci_soft_qh_t *xqh;
   2569        1.13  augustss 		uhci_soft_qh_t *sxqh;
   2570        1.13  augustss 		int maxqh = 0;
   2571         1.1  augustss 		uhci_physaddr_t link;
   2572  1.264.4.47     skrll 
   2573  1.264.4.47     skrll 		DPRINTF("--- dump start ---", 0, 0, 0, 0);
   2574  1.264.4.21     skrll 		DPRINTFN(12, "follow from [0]", 0, 0, 0, 0);
   2575         1.1  augustss 		for (std = sc->sc_vframes[0].htd, link = 0;
   2576       1.121  augustss 		     (link & UHCI_PTR_QH) == 0;
   2577        1.42  augustss 		     std = std->link.std) {
   2578        1.88   tsutsui 			link = le32toh(std->td.td_link);
   2579         1.1  augustss 			uhci_dump_td(std);
   2580         1.1  augustss 		}
   2581        1.67  augustss 		sxqh = (uhci_soft_qh_t *)std;
   2582        1.67  augustss 		uhci_dump_qh(sxqh);
   2583        1.67  augustss 		for (xqh = sxqh;
   2584        1.63  augustss 		     xqh != NULL;
   2585       1.152  augustss 		     xqh = (maxqh++ == 5 || xqh->hlink == sxqh ||
   2586   1.264.4.2     skrll 			xqh->hlink == xqh ? NULL : xqh->hlink)) {
   2587         1.1  augustss 			uhci_dump_qh(xqh);
   2588        1.13  augustss 		}
   2589  1.264.4.21     skrll 		DPRINTFN(12, "Enqueued QH:", 0, 0, 0, 0);
   2590         1.1  augustss 		uhci_dump_qh(sqh);
   2591        1.42  augustss 		uhci_dump_tds(sqh->elink);
   2592  1.264.4.47     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   2593         1.1  augustss 	}
   2594         1.1  augustss #endif
   2595   1.264.4.7     skrll 	if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
   2596   1.264.4.7     skrll 		callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
   2597  1.264.4.39     skrll 			    uhci_timeout, xfer);
   2598        1.13  augustss 	}
   2599   1.264.4.7     skrll 	xfer->ux_status = USBD_IN_PROGRESS;
   2600         1.1  augustss 
   2601  1.264.4.13     skrll 	return USBD_NORMAL_COMPLETION;
   2602         1.1  augustss }
   2603         1.1  augustss 
   2604        1.16  augustss usbd_status
   2605  1.264.4.25     skrll uhci_device_isoc_transfer(struct usbd_xfer *xfer)
   2606        1.16  augustss {
   2607  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2608        1.63  augustss 	usbd_status err;
   2609        1.48  augustss 
   2610  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2611  1.264.4.21     skrll 	DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0);
   2612        1.48  augustss 
   2613        1.48  augustss 	/* Put it on our queue, */
   2614       1.248       mrg 	mutex_enter(&sc->sc_lock);
   2615        1.63  augustss 	err = usb_insert_transfer(xfer);
   2616       1.248       mrg 	mutex_exit(&sc->sc_lock);
   2617        1.48  augustss 
   2618        1.48  augustss 	/* bail out on error, */
   2619        1.63  augustss 	if (err && err != USBD_IN_PROGRESS)
   2620  1.264.4.13     skrll 		return err;
   2621        1.48  augustss 
   2622        1.48  augustss 	/* XXX should check inuse here */
   2623        1.48  augustss 
   2624        1.48  augustss 	/* insert into schedule, */
   2625        1.63  augustss 	uhci_device_isoc_enter(xfer);
   2626        1.48  augustss 
   2627       1.102  augustss 	/* and start if the pipe wasn't running */
   2628        1.67  augustss 	if (!err)
   2629   1.264.4.7     skrll 		uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
   2630        1.48  augustss 
   2631  1.264.4.13     skrll 	return err;
   2632        1.48  augustss }
   2633        1.48  augustss 
   2634        1.48  augustss void
   2635  1.264.4.25     skrll uhci_device_isoc_enter(struct usbd_xfer *xfer)
   2636        1.48  augustss {
   2637  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   2638  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2639  1.264.4.33     skrll 	struct isoc *isoc = &upipe->isoc;
   2640       1.152  augustss 	uhci_soft_td_t *std;
   2641   1.264.4.1     skrll 	uint32_t buf, len, status, offs;
   2642       1.248       mrg 	int i, next, nframes;
   2643   1.264.4.7     skrll 	int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN;
   2644        1.48  augustss 
   2645  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2646  1.264.4.21     skrll 	DPRINTFN(5, "used=%d next=%d xfer=%p nframes=%d",
   2647  1.264.4.33     skrll 	    isoc->inuse, isoc->next, xfer, xfer->ux_nframes);
   2648        1.48  augustss 
   2649        1.82  augustss 	if (sc->sc_dying)
   2650        1.82  augustss 		return;
   2651        1.82  augustss 
   2652   1.264.4.7     skrll 	if (xfer->ux_status == USBD_IN_PROGRESS) {
   2653        1.48  augustss 		/* This request has already been entered into the frame list */
   2654        1.96  augustss 		printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer);
   2655        1.68  augustss 		/* XXX */
   2656        1.48  augustss 	}
   2657        1.48  augustss 
   2658        1.48  augustss #ifdef DIAGNOSTIC
   2659  1.264.4.33     skrll 	if (isoc->inuse >= UHCI_VFRAMELIST_COUNT)
   2660        1.48  augustss 		printf("uhci_device_isoc_enter: overflow!\n");
   2661        1.19  augustss #endif
   2662        1.16  augustss 
   2663  1.264.4.33     skrll 	next = isoc->next;
   2664        1.48  augustss 	if (next == -1) {
   2665        1.48  augustss 		/* Not in use yet, schedule it a few frames ahead. */
   2666        1.48  augustss 		next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT;
   2667  1.264.4.21     skrll 		DPRINTFN(2, "start next=%d", next, 0, 0, 0);
   2668        1.48  augustss 	}
   2669        1.48  augustss 
   2670   1.264.4.7     skrll 	xfer->ux_status = USBD_IN_PROGRESS;
   2671  1.264.4.41     skrll 	UHCI_XFER2UXFER(xfer)->ux_curframe = next;
   2672        1.48  augustss 
   2673   1.264.4.7     skrll 	buf = DMAADDR(&xfer->ux_dmabuf, 0);
   2674       1.223    bouyer 	offs = 0;
   2675        1.88   tsutsui 	status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) |
   2676        1.88   tsutsui 				     UHCI_TD_ACTIVE |
   2677        1.88   tsutsui 				     UHCI_TD_IOS);
   2678   1.264.4.7     skrll 	nframes = xfer->ux_nframes;
   2679       1.248       mrg 	mutex_enter(&sc->sc_lock);
   2680        1.48  augustss 	for (i = 0; i < nframes; i++) {
   2681  1.264.4.33     skrll 		std = isoc->stds[next];
   2682        1.48  augustss 		if (++next >= UHCI_VFRAMELIST_COUNT)
   2683        1.48  augustss 			next = 0;
   2684   1.264.4.7     skrll 		len = xfer->ux_frlengths[i];
   2685        1.88   tsutsui 		std->td.td_buffer = htole32(buf);
   2686   1.264.4.7     skrll 		usb_syncmem(&xfer->ux_dmabuf, offs, len,
   2687       1.223    bouyer 		    rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
   2688        1.48  augustss 		if (i == nframes - 1)
   2689        1.88   tsutsui 			status |= UHCI_TD_IOC;
   2690        1.88   tsutsui 		std->td.td_status = htole32(status);
   2691        1.88   tsutsui 		std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK);
   2692        1.88   tsutsui 		std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len));
   2693       1.223    bouyer 		usb_syncmem(&std->dma, std->offs, sizeof(std->td),
   2694       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2695        1.59  augustss #ifdef UHCI_DEBUG
   2696  1.264.4.43     skrll 		if (uhcidebug >= 5) {
   2697  1.264.4.47     skrll 			DPRINTF("--- dump start ---", 0, 0, 0, 0);
   2698  1.264.4.27     skrll 			DPRINTF("TD %d", i, 0, 0, 0);
   2699        1.48  augustss 			uhci_dump_td(std);
   2700  1.264.4.47     skrll 			DPRINTF("--- dump end ---", 0, 0, 0, 0);
   2701        1.48  augustss 		}
   2702        1.48  augustss #endif
   2703        1.48  augustss 		buf += len;
   2704       1.223    bouyer 		offs += len;
   2705        1.48  augustss 	}
   2706  1.264.4.33     skrll 	isoc->next = next;
   2707  1.264.4.33     skrll 	isoc->inuse += xfer->ux_nframes;
   2708        1.16  augustss 
   2709       1.248       mrg 	mutex_exit(&sc->sc_lock);
   2710        1.16  augustss }
   2711        1.16  augustss 
   2712        1.16  augustss usbd_status
   2713  1.264.4.25     skrll uhci_device_isoc_start(struct usbd_xfer *xfer)
   2714        1.16  augustss {
   2715  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   2716  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2717  1.264.4.39     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   2718        1.48  augustss 	uhci_soft_td_t *end;
   2719       1.248       mrg 	int i;
   2720        1.48  augustss 
   2721  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2722  1.264.4.21     skrll 	DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0);
   2723        1.96  augustss 
   2724       1.248       mrg 	mutex_enter(&sc->sc_lock);
   2725       1.248       mrg 
   2726       1.248       mrg 	if (sc->sc_dying) {
   2727       1.248       mrg 		mutex_exit(&sc->sc_lock);
   2728  1.264.4.13     skrll 		return USBD_IOERROR;
   2729       1.248       mrg 	}
   2730        1.82  augustss 
   2731        1.48  augustss #ifdef DIAGNOSTIC
   2732   1.264.4.7     skrll 	if (xfer->ux_status != USBD_IN_PROGRESS)
   2733        1.63  augustss 		printf("uhci_device_isoc_start: not in progress %p\n", xfer);
   2734        1.48  augustss #endif
   2735        1.48  augustss 
   2736        1.48  augustss 	/* Find the last TD */
   2737  1.264.4.41     skrll 	i = UHCI_XFER2UXFER(xfer)->ux_curframe + xfer->ux_nframes;
   2738        1.48  augustss 	if (i >= UHCI_VFRAMELIST_COUNT)
   2739        1.48  augustss 		i -= UHCI_VFRAMELIST_COUNT;
   2740  1.264.4.33     skrll 	end = upipe->isoc.stds[i];
   2741        1.48  augustss 
   2742  1.264.4.31     skrll 	KASSERT(end != NULL);
   2743        1.96  augustss 
   2744        1.48  augustss 	/* Set up interrupt info. */
   2745  1.264.4.41     skrll 	ux->ux_stdstart = end;
   2746  1.264.4.41     skrll 	ux->ux_stdend = end;
   2747  1.264.4.31     skrll 
   2748  1.264.4.41     skrll 	KASSERT(ux->ux_isdone);
   2749        1.48  augustss #ifdef DIAGNOSTIC
   2750  1.264.4.41     skrll 	ux->ux_isdone = false;
   2751        1.48  augustss #endif
   2752  1.264.4.39     skrll 	uhci_add_intr_info(sc, ux);
   2753       1.152  augustss 
   2754       1.248       mrg 	mutex_exit(&sc->sc_lock);
   2755        1.48  augustss 
   2756  1.264.4.13     skrll 	return USBD_IN_PROGRESS;
   2757        1.16  augustss }
   2758        1.16  augustss 
   2759        1.16  augustss void
   2760  1.264.4.25     skrll uhci_device_isoc_abort(struct usbd_xfer *xfer)
   2761        1.16  augustss {
   2762  1.264.4.37     skrll 	uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer);
   2763  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   2764  1.264.4.33     skrll 	uhci_soft_td_t **stds = upipe->isoc.stds;
   2765        1.48  augustss 	uhci_soft_td_t *std;
   2766       1.248       mrg 	int i, n, nframes, maxlen, len;
   2767        1.92  augustss 
   2768       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2769        1.92  augustss 
   2770        1.92  augustss 	/* Transfer is already done. */
   2771   1.264.4.7     skrll 	if (xfer->ux_status != USBD_NOT_STARTED &&
   2772   1.264.4.7     skrll 	    xfer->ux_status != USBD_IN_PROGRESS) {
   2773        1.92  augustss 		return;
   2774        1.92  augustss 	}
   2775        1.48  augustss 
   2776        1.92  augustss 	/* Give xfer the requested abort code. */
   2777   1.264.4.7     skrll 	xfer->ux_status = USBD_CANCELLED;
   2778        1.48  augustss 
   2779        1.48  augustss 	/* make hardware ignore it, */
   2780   1.264.4.7     skrll 	nframes = xfer->ux_nframes;
   2781  1.264.4.41     skrll 	n = UHCI_XFER2UXFER(xfer)->ux_curframe;
   2782        1.92  augustss 	maxlen = 0;
   2783        1.48  augustss 	for (i = 0; i < nframes; i++) {
   2784        1.48  augustss 		std = stds[n];
   2785       1.223    bouyer 		usb_syncmem(&std->dma,
   2786       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_status),
   2787       1.223    bouyer 		    sizeof(std->td.td_status),
   2788       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   2789        1.88   tsutsui 		std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC));
   2790       1.223    bouyer 		usb_syncmem(&std->dma,
   2791       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_status),
   2792       1.223    bouyer 		    sizeof(std->td.td_status),
   2793       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2794       1.223    bouyer 		usb_syncmem(&std->dma,
   2795       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_token),
   2796       1.223    bouyer 		    sizeof(std->td.td_token),
   2797       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE);
   2798       1.130   tsutsui 		len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token));
   2799        1.92  augustss 		if (len > maxlen)
   2800        1.92  augustss 			maxlen = len;
   2801        1.48  augustss 		if (++n >= UHCI_VFRAMELIST_COUNT)
   2802        1.48  augustss 			n = 0;
   2803        1.48  augustss 	}
   2804        1.48  augustss 
   2805        1.92  augustss 	/* and wait until we are sure the hardware has finished. */
   2806        1.92  augustss 	delay(maxlen);
   2807        1.92  augustss 
   2808        1.96  augustss #ifdef DIAGNOSTIC
   2809  1.264.4.41     skrll 	UHCI_XFER2UXFER(xfer)->ux_isdone = true;
   2810        1.96  augustss #endif
   2811        1.92  augustss 	/* Run callback and remove from interrupt list. */
   2812        1.92  augustss 	usb_transfer_complete(xfer);
   2813        1.48  augustss 
   2814       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2815        1.16  augustss }
   2816        1.16  augustss 
   2817        1.16  augustss void
   2818  1.264.4.25     skrll uhci_device_isoc_close(struct usbd_pipe *pipe)
   2819        1.16  augustss {
   2820  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
   2821  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
   2822        1.48  augustss 	uhci_soft_td_t *std, *vstd;
   2823  1.264.4.33     skrll 	struct isoc *isoc;
   2824       1.248       mrg 	int i;
   2825       1.248       mrg 
   2826       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2827        1.16  augustss 
   2828        1.16  augustss 	/*
   2829        1.16  augustss 	 * Make sure all TDs are marked as inactive.
   2830        1.16  augustss 	 * Wait for completion.
   2831        1.16  augustss 	 * Unschedule.
   2832        1.16  augustss 	 * Deallocate.
   2833        1.16  augustss 	 */
   2834  1.264.4.33     skrll 	isoc = &upipe->isoc;
   2835        1.16  augustss 
   2836       1.223    bouyer 	for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
   2837  1.264.4.33     skrll 		std = isoc->stds[i];
   2838       1.223    bouyer 		usb_syncmem(&std->dma,
   2839       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_status),
   2840       1.223    bouyer 		    sizeof(std->td.td_status),
   2841       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   2842       1.223    bouyer 		std->td.td_status &= htole32(~UHCI_TD_ACTIVE);
   2843       1.223    bouyer 		usb_syncmem(&std->dma,
   2844       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_status),
   2845       1.223    bouyer 		    sizeof(std->td.td_status),
   2846       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2847       1.223    bouyer 	}
   2848       1.248       mrg 	/* wait for completion */
   2849       1.248       mrg 	usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock);
   2850        1.16  augustss 
   2851        1.16  augustss 	for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
   2852  1.264.4.33     skrll 		std = isoc->stds[i];
   2853        1.48  augustss 		for (vstd = sc->sc_vframes[i].htd;
   2854        1.67  augustss 		     vstd != NULL && vstd->link.std != std;
   2855        1.42  augustss 		     vstd = vstd->link.std)
   2856        1.16  augustss 			;
   2857        1.67  augustss 		if (vstd == NULL) {
   2858        1.16  augustss 			/*panic*/
   2859        1.16  augustss 			printf("uhci_device_isoc_close: %p not found\n", std);
   2860       1.248       mrg 			mutex_exit(&sc->sc_lock);
   2861        1.16  augustss 			return;
   2862        1.16  augustss 		}
   2863        1.42  augustss 		vstd->link = std->link;
   2864       1.223    bouyer 		usb_syncmem(&std->dma,
   2865       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_link),
   2866       1.223    bouyer 		    sizeof(std->td.td_link),
   2867       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE);
   2868        1.42  augustss 		vstd->td.td_link = std->td.td_link;
   2869       1.223    bouyer 		usb_syncmem(&vstd->dma,
   2870       1.223    bouyer 		    vstd->offs + offsetof(uhci_td_t, td_link),
   2871       1.223    bouyer 		    sizeof(vstd->td.td_link),
   2872       1.223    bouyer 		    BUS_DMASYNC_PREWRITE);
   2873        1.16  augustss 		uhci_free_std(sc, std);
   2874        1.16  augustss 	}
   2875        1.16  augustss 
   2876  1.264.4.35     skrll 	kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *));
   2877        1.16  augustss }
   2878        1.16  augustss 
   2879        1.16  augustss usbd_status
   2880  1.264.4.25     skrll uhci_setup_isoc(struct usbd_pipe *pipe)
   2881        1.16  augustss {
   2882  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
   2883  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
   2884   1.264.4.7     skrll 	int addr = upipe->pipe.up_dev->ud_addr;
   2885   1.264.4.7     skrll 	int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
   2886        1.45  augustss 	int rd = UE_GET_DIR(endpt) == UE_DIR_IN;
   2887        1.48  augustss 	uhci_soft_td_t *std, *vstd;
   2888   1.264.4.1     skrll 	uint32_t token;
   2889  1.264.4.33     skrll 	struct isoc *isoc;
   2890       1.248       mrg 	int i;
   2891        1.16  augustss 
   2892  1.264.4.33     skrll 	isoc = &upipe->isoc;
   2893  1.264.4.33     skrll 	isoc->stds = kmem_alloc(UHCI_VFRAMELIST_COUNT *
   2894  1.264.4.35     skrll 				 sizeof(uhci_soft_td_t *),
   2895       1.248       mrg 			       KM_SLEEP);
   2896  1.264.4.33     skrll 	if (isoc->stds == NULL)
   2897       1.248       mrg 		return USBD_NOMEM;
   2898        1.16  augustss 
   2899        1.88   tsutsui 	token = rd ? UHCI_TD_IN (0, endpt, addr, 0) :
   2900        1.88   tsutsui 		     UHCI_TD_OUT(0, endpt, addr, 0);
   2901        1.16  augustss 
   2902       1.248       mrg 	mutex_enter(&sc->sc_lock);
   2903       1.248       mrg 
   2904        1.48  augustss 	/* Allocate the TDs and mark as inactive; */
   2905        1.16  augustss 	for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
   2906        1.48  augustss 		std = uhci_alloc_std(sc);
   2907        1.48  augustss 		if (std == 0)
   2908        1.48  augustss 			goto bad;
   2909        1.88   tsutsui 		std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */
   2910        1.88   tsutsui 		std->td.td_token = htole32(token);
   2911       1.223    bouyer 		usb_syncmem(&std->dma, std->offs, sizeof(std->td),
   2912       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2913  1.264.4.33     skrll 		isoc->stds[i] = std;
   2914        1.16  augustss 	}
   2915        1.16  augustss 
   2916        1.48  augustss 	/* Insert TDs into schedule. */
   2917        1.16  augustss 	for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
   2918  1.264.4.33     skrll 		std = isoc->stds[i];
   2919        1.48  augustss 		vstd = sc->sc_vframes[i].htd;
   2920       1.223    bouyer 		usb_syncmem(&vstd->dma,
   2921       1.223    bouyer 		    vstd->offs + offsetof(uhci_td_t, td_link),
   2922       1.223    bouyer 		    sizeof(vstd->td.td_link),
   2923       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE);
   2924        1.42  augustss 		std->link = vstd->link;
   2925        1.42  augustss 		std->td.td_link = vstd->td.td_link;
   2926       1.223    bouyer 		usb_syncmem(&std->dma,
   2927       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_link),
   2928       1.223    bouyer 		    sizeof(std->td.td_link),
   2929       1.223    bouyer 		    BUS_DMASYNC_PREWRITE);
   2930        1.42  augustss 		vstd->link.std = std;
   2931       1.121  augustss 		vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD);
   2932       1.223    bouyer 		usb_syncmem(&vstd->dma,
   2933       1.223    bouyer 		    vstd->offs + offsetof(uhci_td_t, td_link),
   2934       1.223    bouyer 		    sizeof(vstd->td.td_link),
   2935       1.223    bouyer 		    BUS_DMASYNC_PREWRITE);
   2936        1.16  augustss 	}
   2937       1.248       mrg 	mutex_exit(&sc->sc_lock);
   2938        1.16  augustss 
   2939  1.264.4.33     skrll 	isoc->next = -1;
   2940  1.264.4.33     skrll 	isoc->inuse = 0;
   2941        1.48  augustss 
   2942  1.264.4.13     skrll 	return USBD_NORMAL_COMPLETION;
   2943        1.16  augustss 
   2944        1.48  augustss  bad:
   2945        1.16  augustss 	while (--i >= 0)
   2946  1.264.4.33     skrll 		uhci_free_std(sc, isoc->stds[i]);
   2947       1.248       mrg 	mutex_exit(&sc->sc_lock);
   2948  1.264.4.35     skrll 	kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *));
   2949  1.264.4.13     skrll 	return USBD_NOMEM;
   2950        1.16  augustss }
   2951        1.16  augustss 
   2952        1.16  augustss void
   2953  1.264.4.25     skrll uhci_device_isoc_done(struct usbd_xfer *xfer)
   2954        1.16  augustss {
   2955  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   2956  1.264.4.39     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   2957  1.264.4.39     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2958       1.223    bouyer 	int i, offs;
   2959   1.264.4.7     skrll 	int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN;
   2960       1.223    bouyer 
   2961        1.48  augustss 
   2962  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2963  1.264.4.21     skrll 	DPRINTFN(4, "length=%d, ux_state=0x%08x",
   2964  1.264.4.21     skrll 	    xfer->ux_actlen, xfer->ux_state, 0, 0);
   2965        1.93  augustss 
   2966  1.264.4.39     skrll 	if (!uhci_active_intr_info(ux))
   2967        1.96  augustss 		return;
   2968        1.96  augustss 
   2969        1.93  augustss #ifdef DIAGNOSTIC
   2970  1.264.4.41     skrll 	if (ux->ux_stdend == NULL) {
   2971   1.264.4.2     skrll 		printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer);
   2972        1.93  augustss #ifdef UHCI_DEBUG
   2973  1.264.4.47     skrll 		DPRINTF("--- dump start ---", 0, 0, 0, 0);
   2974  1.264.4.39     skrll 		uhci_dump_ii(ux);
   2975  1.264.4.47     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   2976        1.93  augustss #endif
   2977        1.93  augustss 		return;
   2978        1.93  augustss 	}
   2979        1.93  augustss #endif
   2980        1.48  augustss 
   2981        1.48  augustss 	/* Turn off the interrupt since it is active even if the TD is not. */
   2982  1.264.4.41     skrll 	usb_syncmem(&ux->ux_stdend->dma,
   2983  1.264.4.41     skrll 	    ux->ux_stdend->offs + offsetof(uhci_td_t, td_status),
   2984  1.264.4.41     skrll 	    sizeof(ux->ux_stdend->td.td_status),
   2985       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   2986  1.264.4.41     skrll 	ux->ux_stdend->td.td_status &= htole32(~UHCI_TD_IOC);
   2987  1.264.4.41     skrll 	usb_syncmem(&ux->ux_stdend->dma,
   2988  1.264.4.41     skrll 	    ux->ux_stdend->offs + offsetof(uhci_td_t, td_status),
   2989  1.264.4.41     skrll 	    sizeof(ux->ux_stdend->td.td_status),
   2990       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2991        1.48  augustss 
   2992  1.264.4.39     skrll 	uhci_del_intr_info(sc, ux);	/* remove from active list */
   2993       1.223    bouyer 
   2994       1.223    bouyer 	offs = 0;
   2995   1.264.4.7     skrll 	for (i = 0; i < xfer->ux_nframes; i++) {
   2996   1.264.4.7     skrll 		usb_syncmem(&xfer->ux_dmabuf, offs, xfer->ux_frlengths[i],
   2997       1.223    bouyer 		    rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
   2998   1.264.4.7     skrll 		offs += xfer->ux_frlengths[i];
   2999       1.223    bouyer 	}
   3000        1.16  augustss }
   3001        1.16  augustss 
   3002         1.1  augustss void
   3003  1.264.4.25     skrll uhci_device_intr_done(struct usbd_xfer *xfer)
   3004         1.1  augustss {
   3005  1.264.4.38     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   3006  1.264.4.39     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   3007  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   3008         1.1  augustss 	uhci_soft_qh_t *sqh;
   3009       1.223    bouyer 	int i, npoll, isread;
   3010         1.1  augustss 
   3011  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3012  1.264.4.21     skrll 	DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0);
   3013         1.1  augustss 
   3014   1.264.4.7     skrll 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
   3015       1.248       mrg 
   3016  1.264.4.33     skrll 	npoll = upipe->intr.npoll;
   3017  1.264.4.54     skrll 	for (i = 0; i < npoll; i++) {
   3018  1.264.4.33     skrll 		sqh = upipe->intr.qhs[i];
   3019       1.121  augustss 		sqh->elink = NULL;
   3020        1.88   tsutsui 		sqh->qh.qh_elink = htole32(UHCI_PTR_T);
   3021       1.223    bouyer 		usb_syncmem(&sqh->dma,
   3022       1.223    bouyer 		    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   3023       1.223    bouyer 		    sizeof(sqh->qh.qh_elink),
   3024       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   3025         1.1  augustss 	}
   3026  1.264.4.41     skrll 	uhci_free_std_chain(sc, ux->ux_stdstart, NULL);
   3027         1.1  augustss 
   3028   1.264.4.7     skrll 	isread = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN;
   3029   1.264.4.7     skrll 	usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
   3030       1.223    bouyer 	    isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
   3031       1.223    bouyer 
   3032         1.1  augustss 	/* XXX Wasteful. */
   3033   1.264.4.7     skrll 	if (xfer->ux_pipe->up_repeat) {
   3034        1.55  augustss 		uhci_soft_td_t *data, *dataend;
   3035         1.1  augustss 
   3036  1.264.4.21     skrll 		DPRINTFN(5, "re-queueing", 0, 0, 0, 0);
   3037        1.92  augustss 
   3038         1.1  augustss 		/* This alloc cannot fail since we freed the chain above. */
   3039   1.264.4.7     skrll 		uhci_alloc_std_chain(upipe, sc, xfer->ux_length,
   3040  1.264.4.33     skrll 				     upipe->intr.isread, xfer->ux_flags,
   3041   1.264.4.7     skrll 				     &xfer->ux_dmabuf, &data, &dataend);
   3042        1.88   tsutsui 		dataend->td.td_status |= htole32(UHCI_TD_IOC);
   3043       1.223    bouyer 		usb_syncmem(&dataend->dma,
   3044       1.223    bouyer 		    dataend->offs + offsetof(uhci_td_t, td_status),
   3045       1.223    bouyer 		    sizeof(dataend->td.td_status),
   3046       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   3047         1.1  augustss 
   3048        1.59  augustss #ifdef UHCI_DEBUG
   3049  1.264.4.43     skrll 		if (uhcidebug >= 10) {
   3050  1.264.4.47     skrll 			DPRINTF("--- dump start ---", 0, 0, 0, 0);
   3051        1.55  augustss 			uhci_dump_tds(data);
   3052  1.264.4.33     skrll 			uhci_dump_qh(upipe->intr.qhs[0]);
   3053  1.264.4.47     skrll 			DPRINTF("--- dump end ---", 0, 0, 0, 0);
   3054         1.1  augustss 		}
   3055         1.1  augustss #endif
   3056         1.1  augustss 
   3057  1.264.4.41     skrll 		ux->ux_stdstart = data;
   3058  1.264.4.41     skrll 		ux->ux_stdend = dataend;
   3059  1.264.4.41     skrll 		KASSERT(ux->ux_isdone);
   3060         1.7  augustss #ifdef DIAGNOSTIC
   3061  1.264.4.41     skrll 		ux->ux_isdone = false;
   3062         1.7  augustss #endif
   3063         1.1  augustss 		for (i = 0; i < npoll; i++) {
   3064  1.264.4.33     skrll 			sqh = upipe->intr.qhs[i];
   3065        1.55  augustss 			sqh->elink = data;
   3066       1.121  augustss 			sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD);
   3067       1.223    bouyer 			usb_syncmem(&sqh->dma,
   3068       1.223    bouyer 			    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   3069       1.223    bouyer 			    sizeof(sqh->qh.qh_elink),
   3070       1.223    bouyer 			    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   3071         1.1  augustss 		}
   3072   1.264.4.7     skrll 		xfer->ux_status = USBD_IN_PROGRESS;
   3073  1.264.4.39     skrll 		/* The ux is already on the examined list, just leave it. */
   3074         1.1  augustss 	} else {
   3075  1.264.4.21     skrll 		DPRINTFN(5, "removing", 0, 0, 0, 0);
   3076  1.264.4.39     skrll 		if (uhci_active_intr_info(ux))
   3077  1.264.4.39     skrll 			uhci_del_intr_info(sc, ux);
   3078         1.1  augustss 	}
   3079         1.1  augustss }
   3080         1.1  augustss 
   3081         1.1  augustss /* Deallocate request data structures */
   3082         1.1  augustss void
   3083  1.264.4.25     skrll uhci_device_ctrl_done(struct usbd_xfer *xfer)
   3084         1.1  augustss {
   3085  1.264.4.38     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   3086  1.264.4.39     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   3087  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   3088   1.264.4.7     skrll 	int len = UGETW(xfer->ux_request.wLength);
   3089   1.264.4.7     skrll 	int isread = (xfer->ux_request.bmRequestType & UT_READ);
   3090         1.1  augustss 
   3091   1.264.4.7     skrll 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
   3092       1.248       mrg 
   3093  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3094  1.264.4.31     skrll 
   3095  1.264.4.32     skrll 	KASSERT(xfer->ux_rqflags & URQ_REQUEST);
   3096         1.1  augustss 
   3097  1.264.4.39     skrll 	if (!uhci_active_intr_info(ux))
   3098       1.169  augustss 		return;
   3099       1.169  augustss 
   3100  1.264.4.39     skrll 	uhci_del_intr_info(sc, ux);	/* remove from active list */
   3101         1.1  augustss 
   3102   1.264.4.7     skrll 	if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW)
   3103  1.264.4.33     skrll 		uhci_remove_ls_ctrl(sc, upipe->ctrl.sqh);
   3104       1.123  augustss 	else
   3105  1.264.4.33     skrll 		uhci_remove_hs_ctrl(sc, upipe->ctrl.sqh);
   3106         1.1  augustss 
   3107  1.264.4.33     skrll 	if (upipe->ctrl.length != 0)
   3108  1.264.4.41     skrll 		uhci_free_std_chain(sc, ux->ux_stdstart->link.std, ux->ux_stdend);
   3109        1.49  augustss 
   3110       1.223    bouyer 	if (len) {
   3111   1.264.4.7     skrll 		usb_syncmem(&xfer->ux_dmabuf, 0, len,
   3112       1.223    bouyer 		    isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
   3113       1.223    bouyer 	}
   3114  1.264.4.33     skrll 	usb_syncmem(&upipe->ctrl.reqdma, 0,
   3115       1.223    bouyer 	    sizeof(usb_device_request_t),  BUS_DMASYNC_POSTWRITE);
   3116       1.223    bouyer 
   3117  1.264.4.27     skrll 	DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0);
   3118         1.1  augustss }
   3119         1.1  augustss 
   3120         1.1  augustss /* Deallocate request data structures */
   3121         1.1  augustss void
   3122  1.264.4.25     skrll uhci_device_bulk_done(struct usbd_xfer *xfer)
   3123         1.1  augustss {
   3124  1.264.4.39     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   3125  1.264.4.38     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   3126  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   3127  1.264.4.51     skrll 	usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc;
   3128  1.264.4.51     skrll 	int endpt = ed->bEndpointAddress;
   3129  1.264.4.51     skrll 	int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
   3130       1.169  augustss 
   3131  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3132  1.264.4.39     skrll 	DPRINTFN(5, "xfer=%p ux=%p sc=%p upipe=%p", xfer, ux, sc,
   3133  1.264.4.21     skrll 	    upipe);
   3134       1.169  augustss 
   3135       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   3136       1.248       mrg 
   3137  1.264.4.39     skrll 	if (!uhci_active_intr_info(ux))
   3138       1.169  augustss 		return;
   3139         1.1  augustss 
   3140  1.264.4.39     skrll 	uhci_del_intr_info(sc, ux);	/* remove from active list */
   3141         1.1  augustss 
   3142  1.264.4.33     skrll 	uhci_remove_bulk(sc, upipe->bulk.sqh);
   3143        1.32  augustss 
   3144  1.264.4.41     skrll 	uhci_free_std_chain(sc, ux->ux_stdstart, NULL);
   3145  1.264.4.51     skrll 	if (xfer->ux_length) {
   3146  1.264.4.51     skrll 		usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
   3147  1.264.4.51     skrll 		    isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
   3148  1.264.4.51     skrll 	}
   3149        1.32  augustss 
   3150  1.264.4.21     skrll 	DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0);
   3151         1.1  augustss }
   3152         1.1  augustss 
   3153         1.1  augustss /* Add interrupt QH, called with vflock. */
   3154         1.1  augustss void
   3155       1.119  augustss uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   3156         1.1  augustss {
   3157        1.92  augustss 	struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos];
   3158        1.42  augustss 	uhci_soft_qh_t *eqh;
   3159         1.1  augustss 
   3160  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3161  1.264.4.21     skrll 	DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0);
   3162        1.92  augustss 
   3163        1.42  augustss 	eqh = vf->eqh;
   3164       1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   3165       1.223    bouyer 	    sizeof(eqh->qh.qh_hlink),
   3166       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE);
   3167        1.42  augustss 	sqh->hlink       = eqh->hlink;
   3168        1.42  augustss 	sqh->qh.qh_hlink = eqh->qh.qh_hlink;
   3169       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
   3170       1.223    bouyer 	    sizeof(sqh->qh.qh_hlink),
   3171       1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   3172        1.42  augustss 	eqh->hlink       = sqh;
   3173       1.121  augustss 	eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
   3174       1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   3175       1.223    bouyer 	    sizeof(eqh->qh.qh_hlink),
   3176       1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   3177         1.1  augustss 	vf->eqh = sqh;
   3178         1.1  augustss 	vf->bandwidth++;
   3179         1.1  augustss }
   3180         1.1  augustss 
   3181       1.119  augustss /* Remove interrupt QH. */
   3182         1.1  augustss void
   3183       1.119  augustss uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   3184         1.1  augustss {
   3185        1.92  augustss 	struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos];
   3186         1.1  augustss 	uhci_soft_qh_t *pqh;
   3187         1.1  augustss 
   3188  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3189  1.264.4.21     skrll 	DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0);
   3190         1.1  augustss 
   3191       1.124  augustss 	/* See comment in uhci_remove_ctrl() */
   3192       1.223    bouyer 
   3193       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
   3194       1.223    bouyer 	    sizeof(sqh->qh.qh_elink),
   3195       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   3196       1.124  augustss 	if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) {
   3197       1.124  augustss 		sqh->qh.qh_elink = htole32(UHCI_PTR_T);
   3198       1.223    bouyer 		usb_syncmem(&sqh->dma,
   3199       1.223    bouyer 		    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   3200       1.223    bouyer 		    sizeof(sqh->qh.qh_elink),
   3201       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   3202       1.124  augustss 		delay(UHCI_QH_REMOVE_DELAY);
   3203       1.124  augustss 	}
   3204       1.124  augustss 
   3205        1.92  augustss 	pqh = uhci_find_prev_qh(vf->hqh, sqh);
   3206       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
   3207       1.223    bouyer 	    sizeof(sqh->qh.qh_hlink),
   3208       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   3209        1.42  augustss 	pqh->hlink       = sqh->hlink;
   3210        1.42  augustss 	pqh->qh.qh_hlink = sqh->qh.qh_hlink;
   3211       1.223    bouyer 	usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
   3212       1.223    bouyer 	    sizeof(pqh->qh.qh_hlink),
   3213       1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   3214       1.124  augustss 	delay(UHCI_QH_REMOVE_DELAY);
   3215         1.1  augustss 	if (vf->eqh == sqh)
   3216         1.1  augustss 		vf->eqh = pqh;
   3217         1.1  augustss 	vf->bandwidth--;
   3218         1.1  augustss }
   3219         1.1  augustss 
   3220         1.1  augustss usbd_status
   3221       1.119  augustss uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival)
   3222         1.1  augustss {
   3223         1.1  augustss 	uhci_soft_qh_t *sqh;
   3224       1.248       mrg 	int i, npoll;
   3225         1.1  augustss 	u_int bestbw, bw, bestoffs, offs;
   3226         1.1  augustss 
   3227  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3228  1.264.4.21     skrll 	DPRINTFN(2, "pipe=%p", upipe, 0, 0, 0);
   3229         1.1  augustss 	if (ival == 0) {
   3230       1.173      gson 		printf("uhci_device_setintr: 0 interval\n");
   3231  1.264.4.13     skrll 		return USBD_INVAL;
   3232         1.1  augustss 	}
   3233         1.1  augustss 
   3234         1.1  augustss 	if (ival > UHCI_VFRAMELIST_COUNT)
   3235         1.1  augustss 		ival = UHCI_VFRAMELIST_COUNT;
   3236         1.1  augustss 	npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival;
   3237  1.264.4.27     skrll 	DPRINTF("ival=%d npoll=%d", ival, npoll, 0, 0);
   3238         1.1  augustss 
   3239  1.264.4.33     skrll 	upipe->intr.npoll = npoll;
   3240  1.264.4.33     skrll 	upipe->intr.qhs =
   3241       1.248       mrg 		kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP);
   3242  1.264.4.33     skrll 	if (upipe->intr.qhs == NULL)
   3243       1.248       mrg 		return USBD_NOMEM;
   3244         1.1  augustss 
   3245       1.152  augustss 	/*
   3246         1.1  augustss 	 * Figure out which offset in the schedule that has most
   3247         1.1  augustss 	 * bandwidth left over.
   3248         1.1  augustss 	 */
   3249         1.1  augustss #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1))
   3250         1.1  augustss 	for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) {
   3251         1.1  augustss 		for (bw = i = 0; i < npoll; i++)
   3252         1.1  augustss 			bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth;
   3253         1.1  augustss 		if (bw < bestbw) {
   3254         1.1  augustss 			bestbw = bw;
   3255         1.1  augustss 			bestoffs = offs;
   3256         1.1  augustss 		}
   3257         1.1  augustss 	}
   3258  1.264.4.27     skrll 	DPRINTF("bw=%d offs=%d", bestbw, bestoffs, 0, 0);
   3259       1.248       mrg 	mutex_enter(&sc->sc_lock);
   3260  1.264.4.54     skrll 	for (i = 0; i < npoll; i++) {
   3261  1.264.4.33     skrll 		upipe->intr.qhs[i] = sqh = uhci_alloc_sqh(sc);
   3262       1.121  augustss 		sqh->elink = NULL;
   3263        1.88   tsutsui 		sqh->qh.qh_elink = htole32(UHCI_PTR_T);
   3264       1.223    bouyer 		usb_syncmem(&sqh->dma,
   3265       1.223    bouyer 		    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   3266       1.223    bouyer 		    sizeof(sqh->qh.qh_elink),
   3267       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   3268         1.1  augustss 		sqh->pos = MOD(i * ival + bestoffs);
   3269         1.1  augustss 	}
   3270         1.1  augustss #undef MOD
   3271         1.1  augustss 
   3272         1.1  augustss 	/* Enter QHs into the controller data structures. */
   3273  1.264.4.54     skrll 	for (i = 0; i < npoll; i++)
   3274  1.264.4.33     skrll 		uhci_add_intr(sc, upipe->intr.qhs[i]);
   3275       1.248       mrg 	mutex_exit(&sc->sc_lock);
   3276         1.1  augustss 
   3277  1.264.4.21     skrll 	DPRINTFN(5, "returns %p", upipe, 0, 0, 0);
   3278  1.264.4.21     skrll 
   3279  1.264.4.13     skrll 	return USBD_NORMAL_COMPLETION;
   3280         1.1  augustss }
   3281         1.1  augustss 
   3282         1.1  augustss /* Open a new pipe. */
   3283         1.1  augustss usbd_status
   3284  1.264.4.25     skrll uhci_open(struct usbd_pipe *pipe)
   3285         1.1  augustss {
   3286  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
   3287  1.264.4.12     skrll 	struct usbd_bus *bus = pipe->up_dev->ud_bus;
   3288  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
   3289   1.264.4.7     skrll 	usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc;
   3290       1.248       mrg 	usbd_status err = USBD_NOMEM;
   3291        1.79  augustss 	int ival;
   3292         1.1  augustss 
   3293  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3294  1.264.4.27     skrll 	DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)",
   3295  1.264.4.21     skrll 	    pipe, pipe->up_dev->ud_addr, ed->bEndpointAddress, bus->ub_rhaddr);
   3296        1.92  augustss 
   3297       1.248       mrg 	if (sc->sc_dying)
   3298       1.248       mrg 		return USBD_IOERROR;
   3299       1.248       mrg 
   3300        1.92  augustss 	upipe->aborting = 0;
   3301       1.236  drochner 	/* toggle state needed for bulk endpoints */
   3302   1.264.4.7     skrll 	upipe->nexttoggle = pipe->up_endpoint->ue_toggle;
   3303        1.92  augustss 
   3304  1.264.4.12     skrll 	if (pipe->up_dev->ud_addr == bus->ub_rhaddr) {
   3305         1.1  augustss 		switch (ed->bEndpointAddress) {
   3306         1.1  augustss 		case USB_CONTROL_ENDPOINT:
   3307  1.264.4.12     skrll 			pipe->up_methods = &roothub_ctrl_methods;
   3308         1.1  augustss 			break;
   3309  1.264.4.12     skrll 		case UE_DIR_IN | USBROOTHUB_INTR_ENDPT:
   3310   1.264.4.7     skrll 			pipe->up_methods = &uhci_root_intr_methods;
   3311         1.1  augustss 			break;
   3312         1.1  augustss 		default:
   3313  1.264.4.13     skrll 			return USBD_INVAL;
   3314         1.1  augustss 		}
   3315         1.1  augustss 	} else {
   3316         1.1  augustss 		switch (ed->bmAttributes & UE_XFERTYPE) {
   3317         1.1  augustss 		case UE_CONTROL:
   3318   1.264.4.7     skrll 			pipe->up_methods = &uhci_device_ctrl_methods;
   3319  1.264.4.33     skrll 			upipe->ctrl.sqh = uhci_alloc_sqh(sc);
   3320  1.264.4.33     skrll 			if (upipe->ctrl.sqh == NULL)
   3321         1.5  augustss 				goto bad;
   3322  1.264.4.33     skrll 			upipe->ctrl.setup = uhci_alloc_std(sc);
   3323  1.264.4.33     skrll 			if (upipe->ctrl.setup == NULL) {
   3324  1.264.4.33     skrll 				uhci_free_sqh(sc, upipe->ctrl.sqh);
   3325         1.5  augustss 				goto bad;
   3326         1.5  augustss 			}
   3327  1.264.4.33     skrll 			upipe->ctrl.stat = uhci_alloc_std(sc);
   3328  1.264.4.33     skrll 			if (upipe->ctrl.stat == NULL) {
   3329  1.264.4.33     skrll 				uhci_free_sqh(sc, upipe->ctrl.sqh);
   3330  1.264.4.33     skrll 				uhci_free_std(sc, upipe->ctrl.setup);
   3331         1.5  augustss 				goto bad;
   3332         1.5  augustss 			}
   3333       1.152  augustss 			err = usb_allocmem(&sc->sc_bus,
   3334       1.152  augustss 				  sizeof(usb_device_request_t),
   3335  1.264.4.33     skrll 				  0, &upipe->ctrl.reqdma);
   3336        1.63  augustss 			if (err) {
   3337  1.264.4.33     skrll 				uhci_free_sqh(sc, upipe->ctrl.sqh);
   3338  1.264.4.33     skrll 				uhci_free_std(sc, upipe->ctrl.setup);
   3339  1.264.4.33     skrll 				uhci_free_std(sc, upipe->ctrl.stat);
   3340         1.5  augustss 				goto bad;
   3341         1.5  augustss 			}
   3342         1.1  augustss 			break;
   3343         1.1  augustss 		case UE_INTERRUPT:
   3344   1.264.4.7     skrll 			pipe->up_methods = &uhci_device_intr_methods;
   3345   1.264.4.7     skrll 			ival = pipe->up_interval;
   3346        1.79  augustss 			if (ival == USBD_DEFAULT_INTERVAL)
   3347        1.79  augustss 				ival = ed->bInterval;
   3348  1.264.4.13     skrll 			return uhci_device_setintr(sc, upipe, ival);
   3349         1.1  augustss 		case UE_ISOCHRONOUS:
   3350   1.264.4.7     skrll 			pipe->up_methods = &uhci_device_isoc_methods;
   3351  1.264.4.13     skrll 			return uhci_setup_isoc(pipe);
   3352         1.1  augustss 		case UE_BULK:
   3353   1.264.4.7     skrll 			pipe->up_methods = &uhci_device_bulk_methods;
   3354  1.264.4.33     skrll 			upipe->bulk.sqh = uhci_alloc_sqh(sc);
   3355  1.264.4.33     skrll 			if (upipe->bulk.sqh == NULL)
   3356         1.5  augustss 				goto bad;
   3357         1.1  augustss 			break;
   3358         1.1  augustss 		}
   3359         1.1  augustss 	}
   3360  1.264.4.13     skrll 	return USBD_NORMAL_COMPLETION;
   3361         1.5  augustss 
   3362         1.5  augustss  bad:
   3363       1.248       mrg 	return USBD_NOMEM;
   3364         1.1  augustss }
   3365         1.1  augustss 
   3366         1.1  augustss /*
   3367         1.1  augustss  * Data structures and routines to emulate the root hub.
   3368         1.1  augustss  */
   3369         1.1  augustss /*
   3370       1.166   dsainty  * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also
   3371       1.166   dsainty  * enables the port, and also states that SET_FEATURE(PORT_ENABLE)
   3372       1.166   dsainty  * should not be used by the USB subsystem.  As we cannot issue a
   3373       1.166   dsainty  * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port
   3374       1.166   dsainty  * will be enabled as part of the reset.
   3375       1.166   dsainty  *
   3376       1.166   dsainty  * On the VT83C572, the port cannot be successfully enabled until the
   3377       1.166   dsainty  * outstanding "port enable change" and "connection status change"
   3378       1.166   dsainty  * events have been reset.
   3379       1.166   dsainty  */
   3380       1.166   dsainty Static usbd_status
   3381       1.166   dsainty uhci_portreset(uhci_softc_t *sc, int index)
   3382       1.166   dsainty {
   3383       1.166   dsainty 	int lim, port, x;
   3384  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3385       1.166   dsainty 
   3386       1.166   dsainty 	if (index == 1)
   3387       1.166   dsainty 		port = UHCI_PORTSC1;
   3388       1.166   dsainty 	else if (index == 2)
   3389       1.166   dsainty 		port = UHCI_PORTSC2;
   3390       1.166   dsainty 	else
   3391  1.264.4.13     skrll 		return USBD_IOERROR;
   3392       1.166   dsainty 
   3393       1.166   dsainty 	x = URWMASK(UREAD2(sc, port));
   3394       1.166   dsainty 	UWRITE2(sc, port, x | UHCI_PORTSC_PR);
   3395       1.166   dsainty 
   3396       1.166   dsainty 	usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY);
   3397       1.166   dsainty 
   3398  1.264.4.27     skrll 	DPRINTF("uhci port %d reset, status0 = 0x%04x", index,
   3399  1.264.4.21     skrll 	    UREAD2(sc, port), 0, 0);
   3400       1.166   dsainty 
   3401       1.166   dsainty 	x = URWMASK(UREAD2(sc, port));
   3402       1.222  drochner 	UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP));
   3403       1.166   dsainty 
   3404       1.166   dsainty 	delay(100);
   3405       1.166   dsainty 
   3406  1.264.4.27     skrll 	DPRINTF("uhci port %d reset, status1 = 0x%04x", index,
   3407  1.264.4.21     skrll 	    UREAD2(sc, port), 0, 0);
   3408       1.166   dsainty 
   3409       1.166   dsainty 	x = URWMASK(UREAD2(sc, port));
   3410       1.166   dsainty 	UWRITE2(sc, port, x  | UHCI_PORTSC_PE);
   3411       1.166   dsainty 
   3412       1.166   dsainty 	for (lim = 10; --lim > 0;) {
   3413       1.166   dsainty 		usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY);
   3414       1.166   dsainty 
   3415       1.166   dsainty 		x = UREAD2(sc, port);
   3416  1.264.4.27     skrll 		DPRINTF("uhci port %d iteration %u, status = 0x%04x", index,
   3417  1.264.4.21     skrll 		    lim, x, 0);
   3418       1.166   dsainty 
   3419       1.166   dsainty 		if (!(x & UHCI_PORTSC_CCS)) {
   3420       1.166   dsainty 			/*
   3421       1.166   dsainty 			 * No device is connected (or was disconnected
   3422       1.166   dsainty 			 * during reset).  Consider the port reset.
   3423       1.166   dsainty 			 * The delay must be long enough to ensure on
   3424       1.166   dsainty 			 * the initial iteration that the device
   3425       1.166   dsainty 			 * connection will have been registered.  50ms
   3426       1.166   dsainty 			 * appears to be sufficient, but 20ms is not.
   3427       1.166   dsainty 			 */
   3428  1.264.4.21     skrll 			DPRINTFN(3, "uhci port %d loop %u, device detached",
   3429  1.264.4.21     skrll 			    index, lim, 0, 0);
   3430       1.166   dsainty 			break;
   3431       1.166   dsainty 		}
   3432       1.166   dsainty 
   3433       1.166   dsainty 		if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) {
   3434       1.166   dsainty 			/*
   3435       1.166   dsainty 			 * Port enabled changed and/or connection
   3436       1.166   dsainty 			 * status changed were set.  Reset either or
   3437       1.166   dsainty 			 * both raised flags (by writing a 1 to that
   3438       1.166   dsainty 			 * bit), and wait again for state to settle.
   3439       1.166   dsainty 			 */
   3440       1.166   dsainty 			UWRITE2(sc, port, URWMASK(x) |
   3441       1.166   dsainty 				(x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)));
   3442       1.166   dsainty 			continue;
   3443       1.166   dsainty 		}
   3444       1.166   dsainty 
   3445       1.166   dsainty 		if (x & UHCI_PORTSC_PE)
   3446       1.166   dsainty 			/* Port is enabled */
   3447       1.166   dsainty 			break;
   3448       1.166   dsainty 
   3449       1.166   dsainty 		UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE);
   3450       1.166   dsainty 	}
   3451       1.166   dsainty 
   3452  1.264.4.21     skrll 	DPRINTFN(3, "uhci port %d reset, status2 = 0x%04x", index,
   3453  1.264.4.21     skrll 	    UREAD2(sc, port), 0, 0);
   3454       1.166   dsainty 
   3455       1.166   dsainty 	if (lim <= 0) {
   3456  1.264.4.27     skrll 		DPRINTF("uhci port %d reset timed out", index,
   3457  1.264.4.21     skrll 		    0, 0, 0);
   3458  1.264.4.13     skrll 		return USBD_TIMEOUT;
   3459       1.166   dsainty 	}
   3460       1.184     perry 
   3461       1.166   dsainty 	sc->sc_isreset = 1;
   3462  1.264.4.13     skrll 	return USBD_NORMAL_COMPLETION;
   3463       1.166   dsainty }
   3464       1.166   dsainty 
   3465  1.264.4.12     skrll Static int
   3466  1.264.4.12     skrll uhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req,
   3467  1.264.4.12     skrll     void *buf, int buflen)
   3468         1.1  augustss {
   3469  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_BUS2SC(bus);
   3470         1.1  augustss 	int port, x;
   3471  1.264.4.12     skrll 	int status, change, totlen = 0;
   3472  1.264.4.12     skrll 	uint16_t len, value, index;
   3473         1.1  augustss 	usb_port_status_t ps;
   3474        1.63  augustss 	usbd_status err;
   3475         1.1  augustss 
   3476  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3477  1.264.4.21     skrll 
   3478        1.82  augustss 	if (sc->sc_dying)
   3479  1.264.4.12     skrll 		return -1;
   3480         1.1  augustss 
   3481  1.264.4.27     skrll 	DPRINTF("type=0x%02x request=%02x", req->bmRequestType,
   3482  1.264.4.21     skrll 	    req->bRequest, 0, 0);
   3483         1.1  augustss 
   3484         1.1  augustss 	len = UGETW(req->wLength);
   3485         1.1  augustss 	value = UGETW(req->wValue);
   3486         1.1  augustss 	index = UGETW(req->wIndex);
   3487        1.49  augustss 
   3488         1.1  augustss #define C(x,y) ((x) | ((y) << 8))
   3489  1.264.4.12     skrll 	switch (C(req->bRequest, req->bmRequestType)) {
   3490         1.1  augustss 	case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
   3491  1.264.4.27     skrll 		DPRINTF("wValue=0x%04x", value, 0, 0, 0);
   3492       1.195  christos 		if (len == 0)
   3493       1.195  christos 			break;
   3494  1.264.4.12     skrll 		switch (value) {
   3495  1.264.4.12     skrll 		case C(0, UDESC_DEVICE): {
   3496  1.264.4.12     skrll 			usb_device_descriptor_t devd;
   3497  1.264.4.12     skrll 
   3498  1.264.4.12     skrll 			totlen = min(buflen, sizeof(devd));
   3499  1.264.4.12     skrll 			memcpy(&devd, buf, totlen);
   3500  1.264.4.12     skrll 			USETW(devd.idVendor, sc->sc_id_vendor);
   3501  1.264.4.12     skrll 			memcpy(buf, &devd, totlen);
   3502         1.1  augustss 			break;
   3503  1.264.4.12     skrll 		}
   3504  1.264.4.12     skrll 		case C(1, UDESC_STRING):
   3505       1.213  drochner #define sd ((usb_string_descriptor_t *)buf)
   3506  1.264.4.12     skrll 			/* Vendor */
   3507  1.264.4.12     skrll 			totlen = usb_makestrdesc(sd, len, sc->sc_vendor);
   3508  1.264.4.12     skrll 			break;
   3509  1.264.4.12     skrll 		case C(2, UDESC_STRING):
   3510  1.264.4.12     skrll 			/* Product */
   3511  1.264.4.12     skrll 			totlen = usb_makestrdesc(sd, len, "UHCI root hub");
   3512         1.1  augustss 			break;
   3513  1.264.4.12     skrll #undef sd
   3514         1.1  augustss 		default:
   3515  1.264.4.12     skrll 			/* default from usbroothub */
   3516  1.264.4.12     skrll 			return buflen;
   3517         1.1  augustss 		}
   3518         1.1  augustss 		break;
   3519  1.264.4.12     skrll 
   3520         1.1  augustss 	/* Hub requests */
   3521         1.1  augustss 	case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
   3522         1.1  augustss 		break;
   3523         1.1  augustss 	case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
   3524  1.264.4.27     skrll 		DPRINTF("UR_CLEAR_PORT_FEATURE port=%d feature=%d", index,
   3525  1.264.4.21     skrll 		    value, 0, 0);
   3526         1.1  augustss 		if (index == 1)
   3527         1.1  augustss 			port = UHCI_PORTSC1;
   3528         1.1  augustss 		else if (index == 2)
   3529         1.1  augustss 			port = UHCI_PORTSC2;
   3530         1.1  augustss 		else {
   3531  1.264.4.12     skrll 			return -1;
   3532         1.1  augustss 		}
   3533         1.1  augustss 		switch(value) {
   3534         1.1  augustss 		case UHF_PORT_ENABLE:
   3535       1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3536         1.1  augustss 			UWRITE2(sc, port, x & ~UHCI_PORTSC_PE);
   3537         1.1  augustss 			break;
   3538         1.1  augustss 		case UHF_PORT_SUSPEND:
   3539       1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3540       1.222  drochner 			if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */
   3541       1.222  drochner 				break;
   3542       1.222  drochner 			UWRITE2(sc, port, x | UHCI_PORTSC_RD);
   3543       1.222  drochner 			/* see USB2 spec ch. 7.1.7.7 */
   3544       1.222  drochner 			usb_delay_ms(&sc->sc_bus, 20);
   3545         1.1  augustss 			UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP);
   3546       1.222  drochner 			/* 10ms resume delay must be provided by caller */
   3547         1.1  augustss 			break;
   3548         1.1  augustss 		case UHF_PORT_RESET:
   3549       1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3550         1.1  augustss 			UWRITE2(sc, port, x & ~UHCI_PORTSC_PR);
   3551         1.1  augustss 			break;
   3552         1.1  augustss 		case UHF_C_PORT_CONNECTION:
   3553       1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3554         1.1  augustss 			UWRITE2(sc, port, x | UHCI_PORTSC_CSC);
   3555         1.1  augustss 			break;
   3556         1.1  augustss 		case UHF_C_PORT_ENABLE:
   3557       1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3558         1.1  augustss 			UWRITE2(sc, port, x | UHCI_PORTSC_POEDC);
   3559         1.1  augustss 			break;
   3560         1.1  augustss 		case UHF_C_PORT_OVER_CURRENT:
   3561       1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3562         1.1  augustss 			UWRITE2(sc, port, x | UHCI_PORTSC_OCIC);
   3563         1.1  augustss 			break;
   3564         1.1  augustss 		case UHF_C_PORT_RESET:
   3565         1.1  augustss 			sc->sc_isreset = 0;
   3566  1.264.4.16     skrll 			break;
   3567         1.1  augustss 		case UHF_PORT_CONNECTION:
   3568         1.1  augustss 		case UHF_PORT_OVER_CURRENT:
   3569         1.1  augustss 		case UHF_PORT_POWER:
   3570         1.1  augustss 		case UHF_PORT_LOW_SPEED:
   3571         1.1  augustss 		case UHF_C_PORT_SUSPEND:
   3572         1.1  augustss 		default:
   3573  1.264.4.12     skrll 			return -1;
   3574         1.1  augustss 		}
   3575         1.1  augustss 		break;
   3576         1.1  augustss 	case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER):
   3577         1.1  augustss 		if (index == 1)
   3578         1.1  augustss 			port = UHCI_PORTSC1;
   3579         1.1  augustss 		else if (index == 2)
   3580         1.1  augustss 			port = UHCI_PORTSC2;
   3581         1.1  augustss 		else {
   3582  1.264.4.12     skrll 			return -1;
   3583         1.1  augustss 		}
   3584         1.1  augustss 		if (len > 0) {
   3585   1.264.4.1     skrll 			*(uint8_t *)buf =
   3586         1.1  augustss 				(UREAD2(sc, port) & UHCI_PORTSC_LS) >>
   3587         1.1  augustss 				UHCI_PORTSC_LS_SHIFT;
   3588         1.1  augustss 			totlen = 1;
   3589         1.1  augustss 		}
   3590         1.1  augustss 		break;
   3591         1.1  augustss 	case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
   3592       1.195  christos 		if (len == 0)
   3593       1.195  christos 			break;
   3594       1.177    toshii 		if ((value & 0xff) != 0) {
   3595  1.264.4.12     skrll 			return -1;
   3596         1.1  augustss 		}
   3597  1.264.4.12     skrll 		usb_hub_descriptor_t hubd;
   3598  1.264.4.12     skrll 
   3599  1.264.4.12     skrll 		totlen = min(buflen, sizeof(hubd));
   3600  1.264.4.12     skrll 		memcpy(&hubd, buf, totlen);
   3601  1.264.4.12     skrll 		hubd.bNbrPorts = 2;
   3602  1.264.4.12     skrll 		memcpy(buf, &hubd, totlen);
   3603         1.1  augustss 		break;
   3604         1.1  augustss 	case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
   3605         1.1  augustss 		if (len != 4) {
   3606  1.264.4.12     skrll 			return -1;
   3607         1.1  augustss 		}
   3608         1.1  augustss 		memset(buf, 0, len);
   3609         1.1  augustss 		totlen = len;
   3610         1.1  augustss 		break;
   3611         1.1  augustss 	case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
   3612         1.1  augustss 		if (index == 1)
   3613         1.1  augustss 			port = UHCI_PORTSC1;
   3614         1.1  augustss 		else if (index == 2)
   3615         1.1  augustss 			port = UHCI_PORTSC2;
   3616         1.1  augustss 		else {
   3617  1.264.4.12     skrll 			return -1;
   3618         1.1  augustss 		}
   3619         1.1  augustss 		if (len != 4) {
   3620  1.264.4.12     skrll 			return -1;
   3621         1.1  augustss 		}
   3622         1.1  augustss 		x = UREAD2(sc, port);
   3623         1.1  augustss 		status = change = 0;
   3624       1.142  augustss 		if (x & UHCI_PORTSC_CCS)
   3625         1.1  augustss 			status |= UPS_CURRENT_CONNECT_STATUS;
   3626       1.152  augustss 		if (x & UHCI_PORTSC_CSC)
   3627         1.1  augustss 			change |= UPS_C_CONNECT_STATUS;
   3628       1.152  augustss 		if (x & UHCI_PORTSC_PE)
   3629         1.1  augustss 			status |= UPS_PORT_ENABLED;
   3630       1.152  augustss 		if (x & UHCI_PORTSC_POEDC)
   3631         1.1  augustss 			change |= UPS_C_PORT_ENABLED;
   3632       1.152  augustss 		if (x & UHCI_PORTSC_OCI)
   3633         1.1  augustss 			status |= UPS_OVERCURRENT_INDICATOR;
   3634       1.152  augustss 		if (x & UHCI_PORTSC_OCIC)
   3635         1.1  augustss 			change |= UPS_C_OVERCURRENT_INDICATOR;
   3636       1.152  augustss 		if (x & UHCI_PORTSC_SUSP)
   3637         1.1  augustss 			status |= UPS_SUSPEND;
   3638       1.152  augustss 		if (x & UHCI_PORTSC_LSDA)
   3639         1.1  augustss 			status |= UPS_LOW_SPEED;
   3640         1.1  augustss 		status |= UPS_PORT_POWER;
   3641         1.1  augustss 		if (sc->sc_isreset)
   3642         1.1  augustss 			change |= UPS_C_PORT_RESET;
   3643         1.1  augustss 		USETW(ps.wPortStatus, status);
   3644         1.1  augustss 		USETW(ps.wPortChange, change);
   3645  1.264.4.12     skrll 		totlen = min(len, sizeof(ps));
   3646  1.264.4.12     skrll 		memcpy(buf, &ps, totlen);
   3647         1.1  augustss 		break;
   3648         1.1  augustss 	case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
   3649  1.264.4.12     skrll 		return -1;
   3650         1.1  augustss 	case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
   3651         1.1  augustss 		break;
   3652         1.1  augustss 	case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
   3653         1.1  augustss 		if (index == 1)
   3654         1.1  augustss 			port = UHCI_PORTSC1;
   3655         1.1  augustss 		else if (index == 2)
   3656         1.1  augustss 			port = UHCI_PORTSC2;
   3657         1.1  augustss 		else {
   3658  1.264.4.12     skrll 			return -1;
   3659         1.1  augustss 		}
   3660         1.1  augustss 		switch(value) {
   3661         1.1  augustss 		case UHF_PORT_ENABLE:
   3662       1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3663         1.1  augustss 			UWRITE2(sc, port, x | UHCI_PORTSC_PE);
   3664         1.1  augustss 			break;
   3665         1.1  augustss 		case UHF_PORT_SUSPEND:
   3666       1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3667         1.1  augustss 			UWRITE2(sc, port, x | UHCI_PORTSC_SUSP);
   3668         1.1  augustss 			break;
   3669         1.1  augustss 		case UHF_PORT_RESET:
   3670       1.166   dsainty 			err = uhci_portreset(sc, index);
   3671  1.264.4.12     skrll 			if (err != USBD_NORMAL_COMPLETION)
   3672  1.264.4.12     skrll 				return -1;
   3673  1.264.4.12     skrll 			return 0;
   3674       1.111  augustss 		case UHF_PORT_POWER:
   3675       1.111  augustss 			/* Pretend we turned on power */
   3676  1.264.4.12     skrll 			return 0;
   3677         1.1  augustss 		case UHF_C_PORT_CONNECTION:
   3678         1.1  augustss 		case UHF_C_PORT_ENABLE:
   3679         1.1  augustss 		case UHF_C_PORT_OVER_CURRENT:
   3680         1.1  augustss 		case UHF_PORT_CONNECTION:
   3681         1.1  augustss 		case UHF_PORT_OVER_CURRENT:
   3682         1.1  augustss 		case UHF_PORT_LOW_SPEED:
   3683         1.1  augustss 		case UHF_C_PORT_SUSPEND:
   3684         1.1  augustss 		case UHF_C_PORT_RESET:
   3685         1.1  augustss 		default:
   3686  1.264.4.12     skrll 			return -1;
   3687         1.1  augustss 		}
   3688         1.1  augustss 		break;
   3689         1.1  augustss 	default:
   3690  1.264.4.12     skrll 		/* default from usbroothub */
   3691  1.264.4.27     skrll 		DPRINTF("returning %d (usbroothub default)",
   3692  1.264.4.21     skrll 		    buflen, 0, 0, 0);
   3693  1.264.4.12     skrll 		return buflen;
   3694         1.1  augustss 	}
   3695         1.1  augustss 
   3696  1.264.4.27     skrll 	DPRINTF("returning %d", totlen, 0, 0, 0);
   3697  1.264.4.21     skrll 
   3698  1.264.4.12     skrll 	return totlen;
   3699         1.1  augustss }
   3700         1.1  augustss 
   3701         1.1  augustss /* Abort a root interrupt request. */
   3702         1.1  augustss void
   3703  1.264.4.25     skrll uhci_root_intr_abort(struct usbd_xfer *xfer)
   3704         1.1  augustss {
   3705  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   3706        1.30  augustss 
   3707       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   3708   1.264.4.7     skrll 	KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
   3709       1.248       mrg 
   3710       1.234    dyoung 	callout_stop(&sc->sc_poll_handle);
   3711        1.96  augustss 	sc->sc_intr_xfer = NULL;
   3712        1.58  augustss 
   3713   1.264.4.7     skrll 	xfer->ux_status = USBD_CANCELLED;
   3714        1.96  augustss #ifdef DIAGNOSTIC
   3715  1.264.4.41     skrll 	UHCI_XFER2UXFER(xfer)->ux_isdone = true;
   3716        1.96  augustss #endif
   3717        1.63  augustss 	usb_transfer_complete(xfer);
   3718         1.1  augustss }
   3719         1.1  augustss 
   3720        1.16  augustss usbd_status
   3721  1.264.4.25     skrll uhci_root_intr_transfer(struct usbd_xfer *xfer)
   3722        1.16  augustss {
   3723  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   3724        1.63  augustss 	usbd_status err;
   3725        1.16  augustss 
   3726        1.52  augustss 	/* Insert last in queue. */
   3727       1.248       mrg 	mutex_enter(&sc->sc_lock);
   3728        1.63  augustss 	err = usb_insert_transfer(xfer);
   3729       1.248       mrg 	mutex_exit(&sc->sc_lock);
   3730        1.63  augustss 	if (err)
   3731  1.264.4.13     skrll 		return err;
   3732        1.52  augustss 
   3733       1.186     skrll 	/*
   3734       1.186     skrll 	 * Pipe isn't running (otherwise err would be USBD_INPROG),
   3735        1.67  augustss 	 * start first
   3736        1.67  augustss 	 */
   3737  1.264.4.13     skrll 	return uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
   3738        1.16  augustss }
   3739        1.16  augustss 
   3740         1.1  augustss /* Start a transfer on the root interrupt pipe */
   3741         1.1  augustss usbd_status
   3742  1.264.4.25     skrll uhci_root_intr_start(struct usbd_xfer *xfer)
   3743         1.1  augustss {
   3744  1.264.4.25     skrll 	struct usbd_pipe *pipe = xfer->ux_pipe;
   3745  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
   3746       1.174  drochner 	unsigned int ival;
   3747         1.1  augustss 
   3748  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3749  1.264.4.27     skrll 	DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length,
   3750  1.264.4.21     skrll 	    xfer->ux_flags, 0);
   3751        1.82  augustss 
   3752        1.82  augustss 	if (sc->sc_dying)
   3753  1.264.4.13     skrll 		return USBD_IOERROR;
   3754         1.1  augustss 
   3755       1.174  drochner 	/* XXX temporary variable needed to avoid gcc3 warning */
   3756   1.264.4.7     skrll 	ival = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval;
   3757       1.174  drochner 	sc->sc_ival = mstohz(ival);
   3758       1.234    dyoung 	callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer);
   3759        1.96  augustss 	sc->sc_intr_xfer = xfer;
   3760  1.264.4.13     skrll 	return USBD_IN_PROGRESS;
   3761         1.1  augustss }
   3762         1.1  augustss 
   3763         1.1  augustss /* Close the root interrupt pipe. */
   3764         1.1  augustss void
   3765  1.264.4.25     skrll uhci_root_intr_close(struct usbd_pipe *pipe)
   3766         1.1  augustss {
   3767  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
   3768  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3769        1.30  augustss 
   3770       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   3771       1.248       mrg 
   3772       1.234    dyoung 	callout_stop(&sc->sc_poll_handle);
   3773        1.96  augustss 	sc->sc_intr_xfer = NULL;
   3774         1.1  augustss }
   3775