uhci.c revision 1.264.4.56 1 1.264.4.56 skrll /* $NetBSD: uhci.c,v 1.264.4.56 2015/11/20 12:49:59 skrll Exp $ */
2 1.1 augustss
3 1.1 augustss /*
4 1.248 mrg * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc.
5 1.1 augustss * All rights reserved.
6 1.1 augustss *
7 1.11 augustss * This code is derived from software contributed to The NetBSD Foundation
8 1.113 augustss * by Lennart Augustsson (lennart (at) augustsson.net) at
9 1.248 mrg * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca)
10 1.248 mrg * and Matthew R. Green (mrg (at) eterna.com.au).
11 1.1 augustss *
12 1.1 augustss * Redistribution and use in source and binary forms, with or without
13 1.1 augustss * modification, are permitted provided that the following conditions
14 1.1 augustss * are met:
15 1.1 augustss * 1. Redistributions of source code must retain the above copyright
16 1.1 augustss * notice, this list of conditions and the following disclaimer.
17 1.1 augustss * 2. Redistributions in binary form must reproduce the above copyright
18 1.1 augustss * notice, this list of conditions and the following disclaimer in the
19 1.1 augustss * documentation and/or other materials provided with the distribution.
20 1.1 augustss *
21 1.1 augustss * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22 1.1 augustss * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 1.1 augustss * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 1.1 augustss * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25 1.1 augustss * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 1.1 augustss * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 1.1 augustss * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 1.1 augustss * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 1.1 augustss * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 1.1 augustss * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 1.1 augustss * POSSIBILITY OF SUCH DAMAGE.
32 1.1 augustss */
33 1.1 augustss
34 1.1 augustss /*
35 1.1 augustss * USB Universal Host Controller driver.
36 1.28 augustss * Handles e.g. PIIX3 and PIIX4.
37 1.1 augustss *
38 1.229 uebayasi * UHCI spec: http://www.intel.com/technology/usb/spec.htm
39 1.229 uebayasi * USB spec: http://www.usb.org/developers/docs/
40 1.71 augustss * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf
41 1.71 augustss * ftp://download.intel.com/design/intarch/datashts/29056201.pdf
42 1.1 augustss */
43 1.143 lukem
44 1.143 lukem #include <sys/cdefs.h>
45 1.264.4.56 skrll __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.264.4.56 2015/11/20 12:49:59 skrll Exp $");
46 1.264.4.30 skrll
47 1.264.4.30 skrll #include "opt_usb.h"
48 1.1 augustss
49 1.1 augustss #include <sys/param.h>
50 1.264.4.20 skrll
51 1.264.4.20 skrll #include <sys/bus.h>
52 1.264.4.20 skrll #include <sys/cpu.h>
53 1.264.4.20 skrll #include <sys/device.h>
54 1.1 augustss #include <sys/kernel.h>
55 1.248 mrg #include <sys/kmem.h>
56 1.264.4.20 skrll #include <sys/mutex.h>
57 1.1 augustss #include <sys/proc.h>
58 1.1 augustss #include <sys/queue.h>
59 1.264.4.20 skrll #include <sys/select.h>
60 1.264.4.20 skrll #include <sys/sysctl.h>
61 1.264.4.20 skrll #include <sys/systm.h>
62 1.1 augustss
63 1.39 augustss #include <machine/endian.h>
64 1.7 augustss
65 1.1 augustss #include <dev/usb/usb.h>
66 1.1 augustss #include <dev/usb/usbdi.h>
67 1.1 augustss #include <dev/usb/usbdivar.h>
68 1.7 augustss #include <dev/usb/usb_mem.h>
69 1.1 augustss
70 1.1 augustss #include <dev/usb/uhcireg.h>
71 1.1 augustss #include <dev/usb/uhcivar.h>
72 1.264.4.11 skrll #include <dev/usb/usbroothub.h>
73 1.264.4.21 skrll #include <dev/usb/usbhist.h>
74 1.1 augustss
75 1.125 augustss /* Use bandwidth reclamation for control transfers. Some devices choke on it. */
76 1.125 augustss /*#define UHCI_CTL_LOOP */
77 1.125 augustss
78 1.67 augustss #ifdef UHCI_DEBUG
79 1.92 augustss uhci_softc_t *thesc;
80 1.125 augustss int uhcinoloop = 0;
81 1.59 augustss #endif
82 1.59 augustss
83 1.264.4.21 skrll #ifdef USB_DEBUG
84 1.264.4.21 skrll #ifndef UHCI_DEBUG
85 1.264.4.21 skrll #define uhcidebug 0
86 1.264.4.21 skrll #else
87 1.264.4.21 skrll static int uhcidebug = 0;
88 1.264.4.21 skrll
89 1.264.4.21 skrll SYSCTL_SETUP(sysctl_hw_uhci_setup, "sysctl hw.uhci setup")
90 1.264.4.21 skrll {
91 1.264.4.21 skrll int err;
92 1.264.4.21 skrll const struct sysctlnode *rnode;
93 1.264.4.21 skrll const struct sysctlnode *cnode;
94 1.264.4.21 skrll
95 1.264.4.21 skrll err = sysctl_createv(clog, 0, NULL, &rnode,
96 1.264.4.21 skrll CTLFLAG_PERMANENT, CTLTYPE_NODE, "uhci",
97 1.264.4.21 skrll SYSCTL_DESCR("uhci global controls"),
98 1.264.4.21 skrll NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
99 1.264.4.21 skrll
100 1.264.4.21 skrll if (err)
101 1.264.4.21 skrll goto fail;
102 1.264.4.21 skrll
103 1.264.4.21 skrll /* control debugging printfs */
104 1.264.4.21 skrll err = sysctl_createv(clog, 0, &rnode, &cnode,
105 1.264.4.21 skrll CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
106 1.264.4.21 skrll "debug", SYSCTL_DESCR("Enable debugging output"),
107 1.264.4.21 skrll NULL, 0, &uhcidebug, sizeof(uhcidebug), CTL_CREATE, CTL_EOL);
108 1.264.4.21 skrll if (err)
109 1.264.4.21 skrll goto fail;
110 1.264.4.21 skrll
111 1.264.4.21 skrll return;
112 1.264.4.21 skrll fail:
113 1.264.4.21 skrll aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err);
114 1.264.4.21 skrll }
115 1.264.4.21 skrll
116 1.264.4.21 skrll #endif /* UHCI_DEBUG */
117 1.264.4.21 skrll #endif /* USB_DEBUG */
118 1.264.4.21 skrll
119 1.264.4.27 skrll #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,1,FMT,A,B,C,D)
120 1.264.4.21 skrll #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,N,FMT,A,B,C,D)
121 1.264.4.21 skrll #define UHCIHIST_FUNC() USBHIST_FUNC()
122 1.264.4.21 skrll #define UHCIHIST_CALLED(name) USBHIST_CALLED(uhcidebug)
123 1.264.4.21 skrll
124 1.39 augustss /*
125 1.39 augustss * The UHCI controller is little endian, so on big endian machines
126 1.181 drochner * the data stored in memory needs to be swapped.
127 1.39 augustss */
128 1.39 augustss
129 1.1 augustss struct uhci_pipe {
130 1.1 augustss struct usbd_pipe pipe;
131 1.32 augustss int nexttoggle;
132 1.92 augustss
133 1.92 augustss u_char aborting;
134 1.264.4.25 skrll struct usbd_xfer *abortstart, abortend;
135 1.92 augustss
136 1.1 augustss /* Info needed for different pipe kinds. */
137 1.1 augustss union {
138 1.1 augustss /* Control pipe */
139 1.1 augustss struct {
140 1.1 augustss uhci_soft_qh_t *sqh;
141 1.7 augustss usb_dma_t reqdma;
142 1.264.4.55 skrll uhci_soft_td_t *setup;
143 1.264.4.55 skrll uhci_soft_td_t *stat;
144 1.264.4.33 skrll } ctrl;
145 1.1 augustss /* Interrupt pipe */
146 1.1 augustss struct {
147 1.1 augustss int npoll;
148 1.1 augustss uhci_soft_qh_t **qhs;
149 1.1 augustss } intr;
150 1.1 augustss /* Bulk pipe */
151 1.1 augustss struct {
152 1.1 augustss uhci_soft_qh_t *sqh;
153 1.1 augustss } bulk;
154 1.264.4.33 skrll /* Isochronous pipe */
155 1.264.4.33 skrll struct isoc {
156 1.16 augustss uhci_soft_td_t **stds;
157 1.48 augustss int next, inuse;
158 1.264.4.33 skrll } isoc;
159 1.264.4.33 skrll };
160 1.1 augustss };
161 1.1 augustss
162 1.142 augustss Static void uhci_globalreset(uhci_softc_t *);
163 1.166 dsainty Static usbd_status uhci_portreset(uhci_softc_t*, int);
164 1.142 augustss Static void uhci_reset(uhci_softc_t *);
165 1.264.4.15 skrll Static usbd_status uhci_run(uhci_softc_t *, int, int);
166 1.123 augustss Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *);
167 1.119 augustss Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *);
168 1.264.4.55 skrll Static void uhci_free_std_locked(uhci_softc_t *, uhci_soft_td_t *);
169 1.123 augustss Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *);
170 1.119 augustss Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *);
171 1.16 augustss #if 0
172 1.119 augustss Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *,
173 1.264.4.48 skrll uhci_intr_info_t *);
174 1.119 augustss Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *);
175 1.16 augustss #endif
176 1.1 augustss
177 1.264.4.55 skrll Static void uhci_free_std_chain(uhci_softc_t *, uhci_soft_td_t *,
178 1.264.4.55 skrll uhci_soft_td_t *);
179 1.264.4.55 skrll Static usbd_status uhci_alloc_std_chain(uhci_softc_t *, struct usbd_xfer *,
180 1.264.4.55 skrll int, int, uhci_soft_td_t **, uhci_soft_td_t **);
181 1.264.4.55 skrll Static void uhci_free_stds(uhci_softc_t *, struct uhci_xfer *);
182 1.264.4.55 skrll
183 1.264.4.55 skrll Static void uhci_reset_std_chain(uhci_softc_t *, struct usbd_xfer *,
184 1.264.4.55 skrll int, int, int *, uhci_soft_td_t *, uhci_soft_td_t **);
185 1.264.4.55 skrll
186 1.119 augustss Static void uhci_poll_hub(void *);
187 1.264.4.25 skrll Static void uhci_waitintr(uhci_softc_t *, struct usbd_xfer *);
188 1.264.4.39 skrll Static void uhci_check_intr(uhci_softc_t *, struct uhci_xfer *);
189 1.264.4.39 skrll Static void uhci_idone(struct uhci_xfer *);
190 1.119 augustss
191 1.264.4.25 skrll Static void uhci_abort_xfer(struct usbd_xfer *, usbd_status);
192 1.119 augustss
193 1.119 augustss Static void uhci_timeout(void *);
194 1.153 augustss Static void uhci_timeout_task(void *);
195 1.123 augustss Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *);
196 1.123 augustss Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *);
197 1.119 augustss Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *);
198 1.123 augustss Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *);
199 1.123 augustss Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *);
200 1.119 augustss Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *);
201 1.264.4.15 skrll Static void uhci_add_loop(uhci_softc_t *);
202 1.264.4.15 skrll Static void uhci_rem_loop(uhci_softc_t *);
203 1.119 augustss
204 1.264.4.25 skrll Static usbd_status uhci_setup_isoc(struct usbd_pipe *);
205 1.264.4.25 skrll Static void uhci_device_isoc_enter(struct usbd_xfer *);
206 1.119 augustss
207 1.264.4.36 skrll Static struct usbd_xfer *
208 1.264.4.36 skrll uhci_allocx(struct usbd_bus *, unsigned int);
209 1.264.4.25 skrll Static void uhci_freex(struct usbd_bus *, struct usbd_xfer *);
210 1.248 mrg Static void uhci_get_lock(struct usbd_bus *, kmutex_t **);
211 1.264.4.13 skrll Static int uhci_roothub_ctrl(struct usbd_bus *,
212 1.264.4.42 skrll usb_device_request_t *, void *, int);
213 1.119 augustss
214 1.264.4.55 skrll Static int uhci_device_ctrl_init(struct usbd_xfer *);
215 1.264.4.55 skrll Static void uhci_device_ctrl_fini(struct usbd_xfer *);
216 1.264.4.25 skrll Static usbd_status uhci_device_ctrl_transfer(struct usbd_xfer *);
217 1.264.4.25 skrll Static usbd_status uhci_device_ctrl_start(struct usbd_xfer *);
218 1.264.4.25 skrll Static void uhci_device_ctrl_abort(struct usbd_xfer *);
219 1.264.4.25 skrll Static void uhci_device_ctrl_close(struct usbd_pipe *);
220 1.264.4.25 skrll Static void uhci_device_ctrl_done(struct usbd_xfer *);
221 1.264.4.25 skrll
222 1.264.4.55 skrll Static int uhci_device_intr_init(struct usbd_xfer *);
223 1.264.4.55 skrll Static void uhci_device_intr_fini(struct usbd_xfer *);
224 1.264.4.25 skrll Static usbd_status uhci_device_intr_transfer(struct usbd_xfer *);
225 1.264.4.25 skrll Static usbd_status uhci_device_intr_start(struct usbd_xfer *);
226 1.264.4.25 skrll Static void uhci_device_intr_abort(struct usbd_xfer *);
227 1.264.4.25 skrll Static void uhci_device_intr_close(struct usbd_pipe *);
228 1.264.4.25 skrll Static void uhci_device_intr_done(struct usbd_xfer *);
229 1.264.4.25 skrll
230 1.264.4.55 skrll Static int uhci_device_bulk_init(struct usbd_xfer *);
231 1.264.4.55 skrll Static void uhci_device_bulk_fini(struct usbd_xfer *);
232 1.264.4.25 skrll Static usbd_status uhci_device_bulk_transfer(struct usbd_xfer *);
233 1.264.4.25 skrll Static usbd_status uhci_device_bulk_start(struct usbd_xfer *);
234 1.264.4.25 skrll Static void uhci_device_bulk_abort(struct usbd_xfer *);
235 1.264.4.25 skrll Static void uhci_device_bulk_close(struct usbd_pipe *);
236 1.264.4.25 skrll Static void uhci_device_bulk_done(struct usbd_xfer *);
237 1.264.4.25 skrll
238 1.264.4.55 skrll Static int uhci_device_isoc_init(struct usbd_xfer *);
239 1.264.4.55 skrll Static void uhci_device_isoc_fini(struct usbd_xfer *);
240 1.264.4.25 skrll Static usbd_status uhci_device_isoc_transfer(struct usbd_xfer *);
241 1.264.4.25 skrll Static usbd_status uhci_device_isoc_start(struct usbd_xfer *);
242 1.264.4.25 skrll Static void uhci_device_isoc_abort(struct usbd_xfer *);
243 1.264.4.25 skrll Static void uhci_device_isoc_close(struct usbd_pipe *);
244 1.264.4.25 skrll Static void uhci_device_isoc_done(struct usbd_xfer *);
245 1.264.4.25 skrll
246 1.264.4.25 skrll Static usbd_status uhci_root_intr_transfer(struct usbd_xfer *);
247 1.264.4.25 skrll Static usbd_status uhci_root_intr_start(struct usbd_xfer *);
248 1.264.4.25 skrll Static void uhci_root_intr_abort(struct usbd_xfer *);
249 1.264.4.25 skrll Static void uhci_root_intr_close(struct usbd_pipe *);
250 1.264.4.25 skrll Static void uhci_root_intr_done(struct usbd_xfer *);
251 1.119 augustss
252 1.264.4.25 skrll Static usbd_status uhci_open(struct usbd_pipe *);
253 1.119 augustss Static void uhci_poll(struct usbd_bus *);
254 1.133 augustss Static void uhci_softintr(void *);
255 1.119 augustss
256 1.264.4.25 skrll Static usbd_status uhci_device_request(struct usbd_xfer *);
257 1.119 augustss
258 1.119 augustss Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *);
259 1.158 augustss Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *);
260 1.264.4.15 skrll Static usbd_status uhci_device_setintr(uhci_softc_t *,
261 1.264.4.15 skrll struct uhci_pipe *, int);
262 1.119 augustss
263 1.264.4.25 skrll Static void uhci_device_clear_toggle(struct usbd_pipe *);
264 1.264.4.25 skrll Static void uhci_noop(struct usbd_pipe *);
265 1.119 augustss
266 1.264.4.42 skrll static inline uhci_soft_qh_t *
267 1.264.4.42 skrll uhci_find_prev_qh(uhci_soft_qh_t *, uhci_soft_qh_t *);
268 1.119 augustss
269 1.119 augustss #ifdef UHCI_DEBUG
270 1.119 augustss Static void uhci_dump_all(uhci_softc_t *);
271 1.119 augustss Static void uhci_dumpregs(uhci_softc_t *);
272 1.119 augustss Static void uhci_dump_qhs(uhci_soft_qh_t *);
273 1.119 augustss Static void uhci_dump_qh(uhci_soft_qh_t *);
274 1.119 augustss Static void uhci_dump_tds(uhci_soft_td_t *);
275 1.119 augustss Static void uhci_dump_td(uhci_soft_td_t *);
276 1.264.4.40 skrll Static void uhci_dump_ii(struct uhci_xfer *);
277 1.119 augustss void uhci_dump(void);
278 1.1 augustss #endif
279 1.1 augustss
280 1.112 augustss #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \
281 1.112 augustss BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
282 1.112 augustss #define UWRITE1(sc, r, x) \
283 1.165 dsainty do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \
284 1.165 dsainty } while (/*CONSTCOND*/0)
285 1.112 augustss #define UWRITE2(sc, r, x) \
286 1.165 dsainty do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \
287 1.165 dsainty } while (/*CONSTCOND*/0)
288 1.112 augustss #define UWRITE4(sc, r, x) \
289 1.165 dsainty do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \
290 1.165 dsainty } while (/*CONSTCOND*/0)
291 1.264.4.42 skrll
292 1.196 mrg static __inline uint8_t
293 1.196 mrg UREAD1(uhci_softc_t *sc, bus_size_t r)
294 1.196 mrg {
295 1.196 mrg
296 1.196 mrg UBARR(sc);
297 1.196 mrg return bus_space_read_1(sc->iot, sc->ioh, r);
298 1.196 mrg }
299 1.196 mrg
300 1.196 mrg static __inline uint16_t
301 1.196 mrg UREAD2(uhci_softc_t *sc, bus_size_t r)
302 1.196 mrg {
303 1.196 mrg
304 1.196 mrg UBARR(sc);
305 1.196 mrg return bus_space_read_2(sc->iot, sc->ioh, r);
306 1.196 mrg }
307 1.196 mrg
308 1.260 joerg #ifdef UHCI_DEBUG
309 1.196 mrg static __inline uint32_t
310 1.196 mrg UREAD4(uhci_softc_t *sc, bus_size_t r)
311 1.196 mrg {
312 1.196 mrg
313 1.196 mrg UBARR(sc);
314 1.196 mrg return bus_space_read_4(sc->iot, sc->ioh, r);
315 1.196 mrg }
316 1.260 joerg #endif
317 1.1 augustss
318 1.1 augustss #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd)
319 1.1 augustss #define UHCISTS(sc) UREAD2(sc, UHCI_STS)
320 1.1 augustss
321 1.142 augustss #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */
322 1.1 augustss
323 1.1 augustss #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK)
324 1.1 augustss
325 1.208 drochner const struct usbd_bus_methods uhci_bus_methods = {
326 1.264.4.5 skrll .ubm_open = uhci_open,
327 1.264.4.5 skrll .ubm_softint = uhci_softintr,
328 1.264.4.5 skrll .ubm_dopoll = uhci_poll,
329 1.264.4.5 skrll .ubm_allocx = uhci_allocx,
330 1.264.4.5 skrll .ubm_freex = uhci_freex,
331 1.264.4.5 skrll .ubm_getlock = uhci_get_lock,
332 1.264.4.12 skrll .ubm_rhctrl = uhci_roothub_ctrl,
333 1.1 augustss };
334 1.1 augustss
335 1.208 drochner const struct usbd_pipe_methods uhci_root_intr_methods = {
336 1.264.4.5 skrll .upm_transfer = uhci_root_intr_transfer,
337 1.264.4.5 skrll .upm_start = uhci_root_intr_start,
338 1.264.4.5 skrll .upm_abort = uhci_root_intr_abort,
339 1.264.4.5 skrll .upm_close = uhci_root_intr_close,
340 1.264.4.5 skrll .upm_cleartoggle = uhci_noop,
341 1.264.4.5 skrll .upm_done = uhci_root_intr_done,
342 1.1 augustss };
343 1.1 augustss
344 1.208 drochner const struct usbd_pipe_methods uhci_device_ctrl_methods = {
345 1.264.4.55 skrll .upm_init = uhci_device_ctrl_init,
346 1.264.4.55 skrll .upm_fini = uhci_device_ctrl_fini,
347 1.264.4.5 skrll .upm_transfer = uhci_device_ctrl_transfer,
348 1.264.4.5 skrll .upm_start = uhci_device_ctrl_start,
349 1.264.4.5 skrll .upm_abort = uhci_device_ctrl_abort,
350 1.264.4.5 skrll .upm_close = uhci_device_ctrl_close,
351 1.264.4.5 skrll .upm_cleartoggle = uhci_noop,
352 1.264.4.5 skrll .upm_done = uhci_device_ctrl_done,
353 1.1 augustss };
354 1.1 augustss
355 1.208 drochner const struct usbd_pipe_methods uhci_device_intr_methods = {
356 1.264.4.55 skrll .upm_init = uhci_device_intr_init,
357 1.264.4.55 skrll .upm_fini = uhci_device_intr_fini,
358 1.264.4.5 skrll .upm_transfer = uhci_device_intr_transfer,
359 1.264.4.5 skrll .upm_start = uhci_device_intr_start,
360 1.264.4.5 skrll .upm_abort = uhci_device_intr_abort,
361 1.264.4.5 skrll .upm_close = uhci_device_intr_close,
362 1.264.4.5 skrll .upm_cleartoggle = uhci_device_clear_toggle,
363 1.264.4.5 skrll .upm_done = uhci_device_intr_done,
364 1.1 augustss };
365 1.1 augustss
366 1.208 drochner const struct usbd_pipe_methods uhci_device_bulk_methods = {
367 1.264.4.55 skrll .upm_init = uhci_device_bulk_init,
368 1.264.4.55 skrll .upm_fini = uhci_device_bulk_fini,
369 1.264.4.5 skrll .upm_transfer = uhci_device_bulk_transfer,
370 1.264.4.5 skrll .upm_start = uhci_device_bulk_start,
371 1.264.4.5 skrll .upm_abort = uhci_device_bulk_abort,
372 1.264.4.5 skrll .upm_close = uhci_device_bulk_close,
373 1.264.4.5 skrll .upm_cleartoggle = uhci_device_clear_toggle,
374 1.264.4.5 skrll .upm_done = uhci_device_bulk_done,
375 1.1 augustss };
376 1.1 augustss
377 1.208 drochner const struct usbd_pipe_methods uhci_device_isoc_methods = {
378 1.264.4.55 skrll .upm_init = uhci_device_isoc_init,
379 1.264.4.55 skrll .upm_fini = uhci_device_isoc_fini,
380 1.264.4.5 skrll .upm_transfer = uhci_device_isoc_transfer,
381 1.264.4.5 skrll .upm_start = uhci_device_isoc_start,
382 1.264.4.5 skrll .upm_abort = uhci_device_isoc_abort,
383 1.264.4.5 skrll .upm_close = uhci_device_isoc_close,
384 1.264.4.5 skrll .upm_cleartoggle = uhci_noop,
385 1.264.4.5 skrll .upm_done = uhci_device_isoc_done,
386 1.16 augustss };
387 1.16 augustss
388 1.264.4.56 skrll #define uhci_add_intr_list(sc, ux) \
389 1.264.4.41 skrll TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ux), ux_list)
390 1.264.4.56 skrll #define uhci_del_intr_list(sc, ux) \
391 1.169 augustss do { \
392 1.264.4.41 skrll TAILQ_REMOVE(&(sc)->sc_intrhead, (ux), ux_list); \
393 1.264.4.41 skrll (ux)->ux_list.tqe_prev = NULL; \
394 1.169 augustss } while (0)
395 1.264.4.56 skrll #define uhci_active_intr_list(ux) ((ux)->ux_list.tqe_prev != NULL)
396 1.92 augustss
397 1.240 jakllsch static inline uhci_soft_qh_t *
398 1.119 augustss uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh)
399 1.92 augustss {
400 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
401 1.264.4.21 skrll DPRINTFN(15, "pqh=%p sqh=%p", pqh, sqh, 0, 0);
402 1.92 augustss
403 1.92 augustss for (; pqh->hlink != sqh; pqh = pqh->hlink) {
404 1.152 augustss #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG)
405 1.223 bouyer usb_syncmem(&pqh->dma,
406 1.223 bouyer pqh->offs + offsetof(uhci_qh_t, qh_hlink),
407 1.223 bouyer sizeof(pqh->qh.qh_hlink),
408 1.223 bouyer BUS_DMASYNC_POSTWRITE);
409 1.92 augustss if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) {
410 1.102 augustss printf("uhci_find_prev_qh: QH not found\n");
411 1.264.4.13 skrll return NULL;
412 1.92 augustss }
413 1.92 augustss #endif
414 1.92 augustss }
415 1.264.4.13 skrll return pqh;
416 1.92 augustss }
417 1.92 augustss
418 1.1 augustss void
419 1.142 augustss uhci_globalreset(uhci_softc_t *sc)
420 1.1 augustss {
421 1.1 augustss UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */
422 1.20 augustss usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */
423 1.1 augustss UHCICMD(sc, 0); /* do nothing */
424 1.1 augustss }
425 1.1 augustss
426 1.264.4.14 skrll int
427 1.119 augustss uhci_init(uhci_softc_t *sc)
428 1.1 augustss {
429 1.63 augustss usbd_status err;
430 1.1 augustss int i, j;
431 1.123 augustss uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh;
432 1.1 augustss uhci_soft_td_t *std;
433 1.1 augustss
434 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
435 1.1 augustss
436 1.67 augustss #ifdef UHCI_DEBUG
437 1.92 augustss thesc = sc;
438 1.92 augustss
439 1.264.4.43 skrll if (uhcidebug >= 2)
440 1.1 augustss uhci_dumpregs(sc);
441 1.1 augustss #endif
442 1.1 augustss
443 1.219 jmcneill sc->sc_suspend = PWR_RESUME;
444 1.219 jmcneill
445 1.1 augustss UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */
446 1.142 augustss uhci_globalreset(sc); /* reset the controller */
447 1.142 augustss uhci_reset(sc);
448 1.24 augustss
449 1.1 augustss /* Allocate and initialize real frame array. */
450 1.152 augustss err = usb_allocmem(&sc->sc_bus,
451 1.264.4.49 skrll UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t),
452 1.264.4.49 skrll UHCI_FRAMELIST_ALIGN, &sc->sc_dma);
453 1.63 augustss if (err)
454 1.264.4.13 skrll return err;
455 1.159 augustss sc->sc_pframes = KERNADDR(&sc->sc_dma, 0);
456 1.1 augustss UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */
457 1.160 augustss UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/
458 1.1 augustss
459 1.264.4.55 skrll /* Initialise mutex early for uhci_alloc_* */
460 1.264.4.55 skrll mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
461 1.264.4.55 skrll mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB);
462 1.264.4.55 skrll
463 1.152 augustss /*
464 1.123 augustss * Allocate a TD, inactive, that hangs from the last QH.
465 1.123 augustss * This is to avoid a bug in the PIIX that makes it run berserk
466 1.123 augustss * otherwise.
467 1.123 augustss */
468 1.123 augustss std = uhci_alloc_std(sc);
469 1.123 augustss if (std == NULL)
470 1.264.4.14 skrll return ENOMEM;
471 1.123 augustss std->link.std = NULL;
472 1.123 augustss std->td.td_link = htole32(UHCI_PTR_T);
473 1.123 augustss std->td.td_status = htole32(0); /* inactive */
474 1.123 augustss std->td.td_token = htole32(0);
475 1.123 augustss std->td.td_buffer = htole32(0);
476 1.223 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
477 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
478 1.123 augustss
479 1.123 augustss /* Allocate the dummy QH marking the end and used for looping the QHs.*/
480 1.123 augustss lsqh = uhci_alloc_sqh(sc);
481 1.123 augustss if (lsqh == NULL)
482 1.264.4.55 skrll goto fail1;
483 1.123 augustss lsqh->hlink = NULL;
484 1.123 augustss lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */
485 1.123 augustss lsqh->elink = std;
486 1.123 augustss lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD);
487 1.123 augustss sc->sc_last_qh = lsqh;
488 1.223 bouyer usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh),
489 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
490 1.123 augustss
491 1.1 augustss /* Allocate the dummy QH where bulk traffic will be queued. */
492 1.1 augustss bsqh = uhci_alloc_sqh(sc);
493 1.63 augustss if (bsqh == NULL)
494 1.264.4.55 skrll goto fail2;
495 1.123 augustss bsqh->hlink = lsqh;
496 1.123 augustss bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH);
497 1.121 augustss bsqh->elink = NULL;
498 1.88 tsutsui bsqh->qh.qh_elink = htole32(UHCI_PTR_T);
499 1.1 augustss sc->sc_bulk_start = sc->sc_bulk_end = bsqh;
500 1.223 bouyer usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh),
501 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
502 1.1 augustss
503 1.123 augustss /* Allocate dummy QH where high speed control traffic will be queued. */
504 1.123 augustss chsqh = uhci_alloc_sqh(sc);
505 1.123 augustss if (chsqh == NULL)
506 1.264.4.55 skrll goto fail3;
507 1.123 augustss chsqh->hlink = bsqh;
508 1.123 augustss chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH);
509 1.123 augustss chsqh->elink = NULL;
510 1.123 augustss chsqh->qh.qh_elink = htole32(UHCI_PTR_T);
511 1.123 augustss sc->sc_hctl_start = sc->sc_hctl_end = chsqh;
512 1.223 bouyer usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh),
513 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
514 1.123 augustss
515 1.123 augustss /* Allocate dummy QH where control traffic will be queued. */
516 1.123 augustss clsqh = uhci_alloc_sqh(sc);
517 1.123 augustss if (clsqh == NULL)
518 1.264.4.55 skrll goto fail4;
519 1.220 bouyer clsqh->hlink = chsqh;
520 1.123 augustss clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH);
521 1.123 augustss clsqh->elink = NULL;
522 1.123 augustss clsqh->qh.qh_elink = htole32(UHCI_PTR_T);
523 1.123 augustss sc->sc_lctl_start = sc->sc_lctl_end = clsqh;
524 1.223 bouyer usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh),
525 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
526 1.1 augustss
527 1.152 augustss /*
528 1.1 augustss * Make all (virtual) frame list pointers point to the interrupt
529 1.1 augustss * queue heads and the interrupt queue heads at the control
530 1.1 augustss * queue head and point the physical frame list to the virtual.
531 1.1 augustss */
532 1.264.4.24 skrll for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
533 1.1 augustss std = uhci_alloc_std(sc);
534 1.1 augustss sqh = uhci_alloc_sqh(sc);
535 1.67 augustss if (std == NULL || sqh == NULL)
536 1.264.4.13 skrll return USBD_NOMEM;
537 1.42 augustss std->link.sqh = sqh;
538 1.121 augustss std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH);
539 1.88 tsutsui std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */
540 1.88 tsutsui std->td.td_token = htole32(0);
541 1.88 tsutsui std->td.td_buffer = htole32(0);
542 1.223 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
543 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
544 1.123 augustss sqh->hlink = clsqh;
545 1.123 augustss sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH);
546 1.121 augustss sqh->elink = NULL;
547 1.88 tsutsui sqh->qh.qh_elink = htole32(UHCI_PTR_T);
548 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
549 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
550 1.1 augustss sc->sc_vframes[i].htd = std;
551 1.1 augustss sc->sc_vframes[i].etd = std;
552 1.1 augustss sc->sc_vframes[i].hqh = sqh;
553 1.1 augustss sc->sc_vframes[i].eqh = sqh;
554 1.152 augustss for (j = i;
555 1.152 augustss j < UHCI_FRAMELIST_COUNT;
556 1.1 augustss j += UHCI_VFRAMELIST_COUNT)
557 1.88 tsutsui sc->sc_pframes[j] = htole32(std->physaddr);
558 1.1 augustss }
559 1.223 bouyer usb_syncmem(&sc->sc_dma, 0,
560 1.223 bouyer UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t),
561 1.223 bouyer BUS_DMASYNC_PREWRITE);
562 1.223 bouyer
563 1.1 augustss
564 1.264.4.39 skrll TAILQ_INIT(&sc->sc_intrhead);
565 1.1 augustss
566 1.253 christos sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0,
567 1.253 christos "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL);
568 1.76 augustss
569 1.248 mrg callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE);
570 1.248 mrg
571 1.248 mrg cv_init(&sc->sc_softwake_cv, "uhciab");
572 1.96 augustss
573 1.1 augustss /* Set up the bus struct. */
574 1.264.4.7 skrll sc->sc_bus.ub_methods = &uhci_bus_methods;
575 1.264.4.7 skrll sc->sc_bus.ub_pipesize = sizeof(struct uhci_pipe);
576 1.264.4.7 skrll sc->sc_bus.ub_usedma = true;
577 1.1 augustss
578 1.190 augustss UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */
579 1.190 augustss
580 1.264.4.27 skrll DPRINTF("Enabling...", 0, 0, 0, 0);
581 1.225 bouyer
582 1.264.4.24 skrll err = uhci_run(sc, 1, 0); /* and here we go... */
583 1.152 augustss UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE |
584 1.1 augustss UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */
585 1.225 bouyer return err;
586 1.264.4.55 skrll
587 1.264.4.55 skrll fail4:
588 1.264.4.55 skrll uhci_free_sqh(sc, chsqh);
589 1.264.4.55 skrll fail3:
590 1.264.4.55 skrll uhci_free_sqh(sc, lsqh);
591 1.264.4.55 skrll fail2:
592 1.264.4.55 skrll uhci_free_sqh(sc, lsqh);
593 1.264.4.55 skrll fail1:
594 1.264.4.55 skrll uhci_free_std(sc, std);
595 1.264.4.55 skrll
596 1.264.4.55 skrll return ENOMEM;
597 1.53 augustss }
598 1.53 augustss
599 1.53 augustss int
600 1.215 dyoung uhci_activate(device_t self, enum devact act)
601 1.53 augustss {
602 1.215 dyoung struct uhci_softc *sc = device_private(self);
603 1.53 augustss
604 1.53 augustss switch (act) {
605 1.53 augustss case DVACT_DEACTIVATE:
606 1.210 kiyohara sc->sc_dying = 1;
607 1.230 dyoung return 0;
608 1.230 dyoung default:
609 1.230 dyoung return EOPNOTSUPP;
610 1.53 augustss }
611 1.53 augustss }
612 1.53 augustss
613 1.215 dyoung void
614 1.215 dyoung uhci_childdet(device_t self, device_t child)
615 1.215 dyoung {
616 1.215 dyoung struct uhci_softc *sc = device_private(self);
617 1.215 dyoung
618 1.215 dyoung KASSERT(sc->sc_child == child);
619 1.215 dyoung sc->sc_child = NULL;
620 1.215 dyoung }
621 1.215 dyoung
622 1.53 augustss int
623 1.119 augustss uhci_detach(struct uhci_softc *sc, int flags)
624 1.53 augustss {
625 1.53 augustss int rv = 0;
626 1.53 augustss
627 1.53 augustss if (sc->sc_child != NULL)
628 1.53 augustss rv = config_detach(sc->sc_child, flags);
629 1.152 augustss
630 1.53 augustss if (rv != 0)
631 1.264.4.13 skrll return rv;
632 1.53 augustss
633 1.226 ad callout_halt(&sc->sc_poll_handle, NULL);
634 1.226 ad callout_destroy(&sc->sc_poll_handle);
635 1.226 ad
636 1.248 mrg cv_destroy(&sc->sc_softwake_cv);
637 1.248 mrg
638 1.248 mrg mutex_destroy(&sc->sc_lock);
639 1.248 mrg mutex_destroy(&sc->sc_intr_lock);
640 1.248 mrg
641 1.254 christos pool_cache_destroy(sc->sc_xferpool);
642 1.254 christos
643 1.76 augustss /* XXX free other data structures XXX */
644 1.53 augustss
645 1.264.4.13 skrll return rv;
646 1.1 augustss }
647 1.1 augustss
648 1.264.4.25 skrll struct usbd_xfer *
649 1.264.4.36 skrll uhci_allocx(struct usbd_bus *bus, unsigned int nframes)
650 1.76 augustss {
651 1.264.4.37 skrll struct uhci_softc *sc = UHCI_BUS2SC(bus);
652 1.264.4.25 skrll struct usbd_xfer *xfer;
653 1.76 augustss
654 1.253 christos xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT);
655 1.92 augustss if (xfer != NULL) {
656 1.253 christos memset(xfer, 0, sizeof(struct uhci_xfer));
657 1.264.4.31 skrll
658 1.92 augustss #ifdef DIAGNOSTIC
659 1.264.4.40 skrll struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
660 1.264.4.41 skrll uxfer->ux_isdone = true;
661 1.264.4.7 skrll xfer->ux_state = XFER_BUSY;
662 1.92 augustss #endif
663 1.92 augustss }
664 1.264.4.13 skrll return xfer;
665 1.76 augustss }
666 1.76 augustss
667 1.76 augustss void
668 1.264.4.25 skrll uhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer)
669 1.76 augustss {
670 1.264.4.37 skrll struct uhci_softc *sc = UHCI_BUS2SC(bus);
671 1.264.4.37 skrll struct uhci_xfer *uxfer __diagused = UHCI_XFER2UXFER(xfer);
672 1.76 augustss
673 1.264.4.31 skrll KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer,
674 1.264.4.31 skrll xfer->ux_state);
675 1.264.4.41 skrll KASSERTMSG(uxfer->ux_isdone, "xfer %p not done\n", xfer);
676 1.93 augustss #ifdef DIAGNOSTIC
677 1.264.4.7 skrll xfer->ux_state = XFER_FREE;
678 1.93 augustss #endif
679 1.253 christos pool_cache_put(sc->sc_xferpool, xfer);
680 1.48 augustss }
681 1.48 augustss
682 1.248 mrg Static void
683 1.248 mrg uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock)
684 1.248 mrg {
685 1.264.4.37 skrll struct uhci_softc *sc = UHCI_BUS2SC(bus);
686 1.248 mrg
687 1.248 mrg *lock = &sc->sc_lock;
688 1.248 mrg }
689 1.248 mrg
690 1.248 mrg
691 1.72 augustss /*
692 1.212 jmcneill * Handle suspend/resume.
693 1.212 jmcneill *
694 1.212 jmcneill * We need to switch to polling mode here, because this routine is
695 1.212 jmcneill * called from an interrupt context. This is all right since we
696 1.212 jmcneill * are almost suspended anyway.
697 1.72 augustss */
698 1.212 jmcneill bool
699 1.232 dyoung uhci_resume(device_t dv, const pmf_qual_t *qual)
700 1.72 augustss {
701 1.212 jmcneill uhci_softc_t *sc = device_private(dv);
702 1.212 jmcneill int cmd;
703 1.72 augustss
704 1.248 mrg mutex_spin_enter(&sc->sc_intr_lock);
705 1.193 augustss
706 1.212 jmcneill cmd = UREAD2(sc, UHCI_CMD);
707 1.264.4.7 skrll sc->sc_bus.ub_usepolling++;
708 1.214 smb UWRITE2(sc, UHCI_INTR, 0);
709 1.214 smb uhci_globalreset(sc);
710 1.214 smb uhci_reset(sc);
711 1.212 jmcneill if (cmd & UHCI_CMD_RS)
712 1.249 drochner uhci_run(sc, 0, 1);
713 1.212 jmcneill
714 1.212 jmcneill /* restore saved state */
715 1.212 jmcneill UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0));
716 1.212 jmcneill UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum);
717 1.212 jmcneill UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof);
718 1.212 jmcneill
719 1.212 jmcneill UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */
720 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock);
721 1.212 jmcneill UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */
722 1.212 jmcneill UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE |
723 1.212 jmcneill UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE);
724 1.214 smb UHCICMD(sc, UHCI_CMD_MAXP);
725 1.249 drochner uhci_run(sc, 1, 1); /* and start traffic again */
726 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock);
727 1.264.4.7 skrll sc->sc_bus.ub_usepolling--;
728 1.212 jmcneill if (sc->sc_intr_xfer != NULL)
729 1.234 dyoung callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub,
730 1.212 jmcneill sc->sc_intr_xfer);
731 1.212 jmcneill #ifdef UHCI_DEBUG
732 1.264.4.43 skrll if (uhcidebug >= 2)
733 1.212 jmcneill uhci_dumpregs(sc);
734 1.212 jmcneill #endif
735 1.212 jmcneill
736 1.219 jmcneill sc->sc_suspend = PWR_RESUME;
737 1.248 mrg mutex_spin_exit(&sc->sc_intr_lock);
738 1.212 jmcneill
739 1.212 jmcneill return true;
740 1.72 augustss }
741 1.72 augustss
742 1.212 jmcneill bool
743 1.232 dyoung uhci_suspend(device_t dv, const pmf_qual_t *qual)
744 1.30 augustss {
745 1.212 jmcneill uhci_softc_t *sc = device_private(dv);
746 1.30 augustss int cmd;
747 1.30 augustss
748 1.248 mrg mutex_spin_enter(&sc->sc_intr_lock);
749 1.212 jmcneill
750 1.30 augustss cmd = UREAD2(sc, UHCI_CMD);
751 1.30 augustss
752 1.212 jmcneill #ifdef UHCI_DEBUG
753 1.264.4.43 skrll if (uhcidebug >= 2)
754 1.212 jmcneill uhci_dumpregs(sc);
755 1.212 jmcneill #endif
756 1.212 jmcneill if (sc->sc_intr_xfer != NULL)
757 1.234 dyoung callout_stop(&sc->sc_poll_handle);
758 1.219 jmcneill sc->sc_suspend = PWR_SUSPEND;
759 1.264.4.7 skrll sc->sc_bus.ub_usepolling++;
760 1.219 jmcneill
761 1.249 drochner uhci_run(sc, 0, 1); /* stop the controller */
762 1.212 jmcneill cmd &= ~UHCI_CMD_RS;
763 1.212 jmcneill
764 1.212 jmcneill /* save some state if BIOS doesn't */
765 1.212 jmcneill sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM);
766 1.212 jmcneill sc->sc_saved_sof = UREAD1(sc, UHCI_SOF);
767 1.212 jmcneill
768 1.212 jmcneill UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */
769 1.30 augustss
770 1.212 jmcneill UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */
771 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock);
772 1.264.4.7 skrll sc->sc_bus.ub_usepolling--;
773 1.86 augustss
774 1.248 mrg mutex_spin_exit(&sc->sc_intr_lock);
775 1.212 jmcneill
776 1.212 jmcneill return true;
777 1.30 augustss }
778 1.30 augustss
779 1.59 augustss #ifdef UHCI_DEBUG
780 1.101 augustss Static void
781 1.119 augustss uhci_dumpregs(uhci_softc_t *sc)
782 1.1 augustss {
783 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
784 1.264.4.27 skrll DPRINTF("cmd =%04x sts =%04x intr =%04x frnum =%04x",
785 1.264.4.21 skrll UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS),
786 1.264.4.21 skrll UREAD2(sc, UHCI_INTR), UREAD2(sc, UHCI_FRNUM));
787 1.264.4.27 skrll DPRINTF("sof =%04x portsc1=%04x portsc2=%04x flbase=%08x",
788 1.264.4.21 skrll UREAD1(sc, UHCI_SOF), UREAD2(sc, UHCI_PORTSC1),
789 1.264.4.21 skrll UREAD2(sc, UHCI_PORTSC2), UREAD4(sc, UHCI_FLBASEADDR));
790 1.1 augustss }
791 1.1 augustss
792 1.1 augustss void
793 1.119 augustss uhci_dump_td(uhci_soft_td_t *p)
794 1.1 augustss {
795 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
796 1.250 christos
797 1.223 bouyer usb_syncmem(&p->dma, p->offs, sizeof(p->td),
798 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
799 1.264.4.21 skrll
800 1.264.4.44 skrll DPRINTF("TD(%p) at 0x%08x", p, p->physaddr, 0, 0);
801 1.264.4.27 skrll DPRINTF(" link=0x%08x status=0x%08x "
802 1.264.4.21 skrll "token=0x%08x buffer=0x%08x",
803 1.264.4.21 skrll le32toh(p->td.td_link),
804 1.264.4.21 skrll le32toh(p->td.td_status),
805 1.264.4.21 skrll le32toh(p->td.td_token),
806 1.264.4.21 skrll le32toh(p->td.td_buffer));
807 1.264.4.21 skrll
808 1.264.4.27 skrll DPRINTF("bitstuff=%d crcto =%d nak =%d babble =%d",
809 1.264.4.21 skrll !!(le32toh(p->td.td_status) & UHCI_TD_BITSTUFF),
810 1.264.4.21 skrll !!(le32toh(p->td.td_status) & UHCI_TD_CRCTO),
811 1.264.4.21 skrll !!(le32toh(p->td.td_status) & UHCI_TD_NAK),
812 1.264.4.21 skrll !!(le32toh(p->td.td_status) & UHCI_TD_BABBLE));
813 1.264.4.27 skrll DPRINTF("dbuffer =%d stalled =%d active =%d ioc =%d",
814 1.264.4.21 skrll !!(le32toh(p->td.td_status) & UHCI_TD_DBUFFER),
815 1.264.4.21 skrll !!(le32toh(p->td.td_status) & UHCI_TD_STALLED),
816 1.264.4.21 skrll !!(le32toh(p->td.td_status) & UHCI_TD_ACTIVE),
817 1.264.4.21 skrll !!(le32toh(p->td.td_status) & UHCI_TD_IOC));
818 1.264.4.27 skrll DPRINTF("ios =%d ls =%d spd =%d",
819 1.264.4.21 skrll !!(le32toh(p->td.td_status) & UHCI_TD_IOS),
820 1.264.4.21 skrll !!(le32toh(p->td.td_status) & UHCI_TD_LS),
821 1.264.4.21 skrll !!(le32toh(p->td.td_status) & UHCI_TD_SPD), 0);
822 1.264.4.27 skrll DPRINTF("errcnt =%d actlen =%d pid=%02x",
823 1.264.4.21 skrll UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)),
824 1.264.4.21 skrll UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)),
825 1.264.4.21 skrll UHCI_TD_GET_PID(le32toh(p->td.td_token)), 0);
826 1.264.4.27 skrll DPRINTF("addr=%d endpt=%d D=%d maxlen=%d,",
827 1.264.4.21 skrll UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)),
828 1.264.4.21 skrll UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)),
829 1.264.4.21 skrll UHCI_TD_GET_DT(le32toh(p->td.td_token)),
830 1.264.4.21 skrll UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token)));
831 1.1 augustss }
832 1.1 augustss
833 1.1 augustss void
834 1.119 augustss uhci_dump_qh(uhci_soft_qh_t *sqh)
835 1.1 augustss {
836 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
837 1.264.4.21 skrll
838 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
839 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
840 1.264.4.21 skrll
841 1.264.4.44 skrll DPRINTF("QH(%p) at 0x%08x: hlink=%08x elink=%08x", sqh,
842 1.88 tsutsui (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink),
843 1.264.4.21 skrll le32toh(sqh->qh.qh_elink));
844 1.264.4.21 skrll
845 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD);
846 1.1 augustss }
847 1.1 augustss
848 1.13 augustss
849 1.110 augustss #if 1
850 1.1 augustss void
851 1.119 augustss uhci_dump(void)
852 1.1 augustss {
853 1.110 augustss uhci_dump_all(thesc);
854 1.110 augustss }
855 1.110 augustss #endif
856 1.1 augustss
857 1.110 augustss void
858 1.119 augustss uhci_dump_all(uhci_softc_t *sc)
859 1.110 augustss {
860 1.1 augustss uhci_dumpregs(sc);
861 1.110 augustss /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/
862 1.261 skrll uhci_dump_qhs(sc->sc_lctl_start);
863 1.1 augustss }
864 1.1 augustss
865 1.67 augustss
866 1.67 augustss void
867 1.119 augustss uhci_dump_qhs(uhci_soft_qh_t *sqh)
868 1.67 augustss {
869 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
870 1.264.4.21 skrll
871 1.67 augustss uhci_dump_qh(sqh);
872 1.67 augustss
873 1.264.4.18 skrll /*
874 1.264.4.18 skrll * uhci_dump_qhs displays all the QHs and TDs from the given QH onwards
875 1.67 augustss * Traverses sideways first, then down.
876 1.67 augustss *
877 1.67 augustss * QH1
878 1.67 augustss * QH2
879 1.67 augustss * No QH
880 1.67 augustss * TD2.1
881 1.67 augustss * TD2.2
882 1.67 augustss * TD1.1
883 1.67 augustss * etc.
884 1.67 augustss *
885 1.67 augustss * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1.
886 1.67 augustss */
887 1.67 augustss
888 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
889 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
890 1.88 tsutsui if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T))
891 1.67 augustss uhci_dump_qhs(sqh->hlink);
892 1.67 augustss else
893 1.264.4.27 skrll DPRINTF("No QH", 0, 0, 0, 0);
894 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD);
895 1.67 augustss
896 1.88 tsutsui if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T))
897 1.67 augustss uhci_dump_tds(sqh->elink);
898 1.67 augustss else
899 1.264.4.27 skrll DPRINTF("No QH", 0, 0, 0, 0);
900 1.67 augustss }
901 1.67 augustss
902 1.1 augustss void
903 1.119 augustss uhci_dump_tds(uhci_soft_td_t *std)
904 1.1 augustss {
905 1.67 augustss uhci_soft_td_t *td;
906 1.223 bouyer int stop;
907 1.67 augustss
908 1.264.4.24 skrll for (td = std; td != NULL; td = td->link.std) {
909 1.67 augustss uhci_dump_td(td);
910 1.1 augustss
911 1.264.4.18 skrll /*
912 1.264.4.18 skrll * Check whether the link pointer in this TD marks
913 1.67 augustss * the link pointer as end of queue. This avoids
914 1.67 augustss * printing the free list in case the queue/TD has
915 1.67 augustss * already been moved there (seatbelt).
916 1.67 augustss */
917 1.223 bouyer usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link),
918 1.223 bouyer sizeof(td->td.td_link),
919 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
920 1.223 bouyer stop = (le32toh(td->td.td_link) & UHCI_PTR_T ||
921 1.223 bouyer le32toh(td->td.td_link) == 0);
922 1.223 bouyer usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link),
923 1.223 bouyer sizeof(td->td.td_link), BUS_DMASYNC_PREREAD);
924 1.223 bouyer if (stop)
925 1.67 augustss break;
926 1.67 augustss }
927 1.1 augustss }
928 1.92 augustss
929 1.101 augustss Static void
930 1.264.4.40 skrll uhci_dump_ii(struct uhci_xfer *ux)
931 1.92 augustss {
932 1.264.4.25 skrll struct usbd_pipe *pipe;
933 1.95 augustss usb_endpoint_descriptor_t *ed;
934 1.264.4.25 skrll struct usbd_device *dev;
935 1.152 augustss
936 1.264.4.39 skrll if (ux == NULL) {
937 1.264.4.39 skrll printf("ux NULL\n");
938 1.264.4.2 skrll return;
939 1.264.4.2 skrll }
940 1.264.4.41 skrll pipe = ux->ux_xfer.ux_pipe;
941 1.264.4.2 skrll if (pipe == NULL) {
942 1.264.4.41 skrll printf("ux %p: done=%d pipe=NULL\n", ux, ux->ux_isdone);
943 1.264.4.2 skrll return;
944 1.139 augustss }
945 1.264.4.7 skrll if (pipe->up_endpoint == NULL) {
946 1.264.4.40 skrll printf("ux %p: done=%d pipe=%p pipe->up_endpoint=NULL\n",
947 1.264.4.41 skrll ux, ux->ux_isdone, pipe);
948 1.264.4.2 skrll return;
949 1.139 augustss }
950 1.264.4.7 skrll if (pipe->up_dev == NULL) {
951 1.264.4.40 skrll printf("ux %p: done=%d pipe=%p pipe->up_dev=NULL\n",
952 1.264.4.41 skrll ux, ux->ux_isdone, pipe);
953 1.264.4.2 skrll return;
954 1.95 augustss }
955 1.264.4.7 skrll ed = pipe->up_endpoint->ue_edesc;
956 1.264.4.7 skrll dev = pipe->up_dev;
957 1.264.4.40 skrll printf("ux %p: done=%d dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n",
958 1.264.4.41 skrll ux, ux->ux_isdone, dev,
959 1.264.4.7 skrll UGETW(dev->ud_ddesc.idVendor),
960 1.264.4.7 skrll UGETW(dev->ud_ddesc.idProduct),
961 1.264.4.7 skrll dev->ud_addr, pipe,
962 1.92 augustss ed->bEndpointAddress, ed->bmAttributes);
963 1.92 augustss }
964 1.92 augustss
965 1.120 augustss void uhci_dump_iis(struct uhci_softc *sc);
966 1.92 augustss void
967 1.119 augustss uhci_dump_iis(struct uhci_softc *sc)
968 1.92 augustss {
969 1.264.4.40 skrll struct uhci_xfer *ux;
970 1.92 augustss
971 1.264.4.39 skrll printf("interrupt list:\n");
972 1.264.4.41 skrll for (ux = TAILQ_FIRST(&sc->sc_intrhead); ux; ux = TAILQ_NEXT(ux, ux_list))
973 1.264.4.39 skrll uhci_dump_ii(ux);
974 1.92 augustss }
975 1.92 augustss
976 1.120 augustss void iidump(void);
977 1.119 augustss void iidump(void) { uhci_dump_iis(thesc); }
978 1.92 augustss
979 1.1 augustss #endif
980 1.1 augustss
981 1.1 augustss /*
982 1.1 augustss * This routine is executed periodically and simulates interrupts
983 1.1 augustss * from the root controller interrupt pipe for port status change.
984 1.1 augustss */
985 1.1 augustss void
986 1.119 augustss uhci_poll_hub(void *addr)
987 1.1 augustss {
988 1.264.4.25 skrll struct usbd_xfer *xfer = addr;
989 1.264.4.25 skrll struct usbd_pipe *pipe = xfer->ux_pipe;
990 1.227 martin uhci_softc_t *sc;
991 1.1 augustss u_char *p;
992 1.1 augustss
993 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
994 1.1 augustss
995 1.264.4.7 skrll if (__predict_false(pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL))
996 1.228 martin return; /* device has detached */
997 1.264.4.37 skrll sc = UHCI_PIPE2SC(pipe);
998 1.234 dyoung callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer);
999 1.41 augustss
1000 1.264.4.7 skrll p = xfer->ux_buf;
1001 1.1 augustss p[0] = 0;
1002 1.1 augustss if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC))
1003 1.1 augustss p[0] |= 1<<1;
1004 1.1 augustss if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC))
1005 1.1 augustss p[0] |= 1<<2;
1006 1.41 augustss if (p[0] == 0)
1007 1.41 augustss /* No change, try again in a while */
1008 1.41 augustss return;
1009 1.41 augustss
1010 1.264.4.7 skrll xfer->ux_actlen = 1;
1011 1.264.4.7 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1012 1.248 mrg mutex_enter(&sc->sc_lock);
1013 1.63 augustss usb_transfer_complete(xfer);
1014 1.248 mrg mutex_exit(&sc->sc_lock);
1015 1.41 augustss }
1016 1.41 augustss
1017 1.41 augustss void
1018 1.264.4.25 skrll uhci_root_intr_done(struct usbd_xfer *xfer)
1019 1.84 augustss {
1020 1.84 augustss }
1021 1.84 augustss
1022 1.123 augustss /*
1023 1.123 augustss * Let the last QH loop back to the high speed control transfer QH.
1024 1.123 augustss * This is what intel calls "bandwidth reclamation" and improves
1025 1.123 augustss * USB performance a lot for some devices.
1026 1.123 augustss * If we are already looping, just count it.
1027 1.123 augustss */
1028 1.1 augustss void
1029 1.264.4.17 skrll uhci_add_loop(uhci_softc_t *sc)
1030 1.264.4.17 skrll {
1031 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1032 1.264.4.25 skrll
1033 1.125 augustss #ifdef UHCI_DEBUG
1034 1.125 augustss if (uhcinoloop)
1035 1.125 augustss return;
1036 1.125 augustss #endif
1037 1.123 augustss if (++sc->sc_loops == 1) {
1038 1.264.4.21 skrll DPRINTFN(5, "add loop", 0, 0, 0, 0);
1039 1.123 augustss /* Note, we don't loop back the soft pointer. */
1040 1.152 augustss sc->sc_last_qh->qh.qh_hlink =
1041 1.123 augustss htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH);
1042 1.223 bouyer usb_syncmem(&sc->sc_last_qh->dma,
1043 1.223 bouyer sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink),
1044 1.223 bouyer sizeof(sc->sc_last_qh->qh.qh_hlink),
1045 1.223 bouyer BUS_DMASYNC_PREWRITE);
1046 1.123 augustss }
1047 1.123 augustss }
1048 1.123 augustss
1049 1.123 augustss void
1050 1.264.4.17 skrll uhci_rem_loop(uhci_softc_t *sc)
1051 1.264.4.17 skrll {
1052 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1053 1.264.4.21 skrll
1054 1.125 augustss #ifdef UHCI_DEBUG
1055 1.125 augustss if (uhcinoloop)
1056 1.125 augustss return;
1057 1.125 augustss #endif
1058 1.123 augustss if (--sc->sc_loops == 0) {
1059 1.264.4.21 skrll DPRINTFN(5, "remove loop", 0, 0, 0, 0);
1060 1.123 augustss sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T);
1061 1.223 bouyer usb_syncmem(&sc->sc_last_qh->dma,
1062 1.223 bouyer sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink),
1063 1.223 bouyer sizeof(sc->sc_last_qh->qh.qh_hlink),
1064 1.223 bouyer BUS_DMASYNC_PREWRITE);
1065 1.123 augustss }
1066 1.123 augustss }
1067 1.123 augustss
1068 1.248 mrg /* Add high speed control QH, called with lock held. */
1069 1.123 augustss void
1070 1.123 augustss uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1071 1.1 augustss {
1072 1.42 augustss uhci_soft_qh_t *eqh;
1073 1.1 augustss
1074 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1075 1.264.4.21 skrll
1076 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
1077 1.248 mrg
1078 1.264.4.21 skrll DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
1079 1.123 augustss eqh = sc->sc_hctl_end;
1080 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1081 1.223 bouyer sizeof(eqh->qh.qh_hlink),
1082 1.223 bouyer BUS_DMASYNC_POSTWRITE);
1083 1.42 augustss sqh->hlink = eqh->hlink;
1084 1.42 augustss sqh->qh.qh_hlink = eqh->qh.qh_hlink;
1085 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1086 1.223 bouyer BUS_DMASYNC_PREWRITE);
1087 1.42 augustss eqh->hlink = sqh;
1088 1.121 augustss eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
1089 1.123 augustss sc->sc_hctl_end = sqh;
1090 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1091 1.223 bouyer sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
1092 1.125 augustss #ifdef UHCI_CTL_LOOP
1093 1.123 augustss uhci_add_loop(sc);
1094 1.125 augustss #endif
1095 1.1 augustss }
1096 1.1 augustss
1097 1.248 mrg /* Remove high speed control QH, called with lock held. */
1098 1.1 augustss void
1099 1.123 augustss uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1100 1.1 augustss {
1101 1.1 augustss uhci_soft_qh_t *pqh;
1102 1.256 tsutsui uint32_t elink;
1103 1.1 augustss
1104 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
1105 1.248 mrg
1106 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1107 1.264.4.21 skrll DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
1108 1.125 augustss #ifdef UHCI_CTL_LOOP
1109 1.123 augustss uhci_rem_loop(sc);
1110 1.125 augustss #endif
1111 1.124 augustss /*
1112 1.124 augustss * The T bit should be set in the elink of the QH so that the HC
1113 1.124 augustss * doesn't follow the pointer. This condition may fail if the
1114 1.124 augustss * the transferred packet was short so that the QH still points
1115 1.124 augustss * at the last used TD.
1116 1.124 augustss * In this case we set the T bit and wait a little for the HC
1117 1.124 augustss * to stop looking at the TD.
1118 1.223 bouyer * Note that if the TD chain is large enough, the controller
1119 1.223 bouyer * may still be looking at the chain at the end of this function.
1120 1.223 bouyer * uhci_free_std_chain() will make sure the controller stops
1121 1.223 bouyer * looking at it quickly, but until then we should not change
1122 1.223 bouyer * sqh->hlink.
1123 1.124 augustss */
1124 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
1125 1.223 bouyer sizeof(sqh->qh.qh_elink),
1126 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1127 1.256 tsutsui elink = le32toh(sqh->qh.qh_elink);
1128 1.256 tsutsui usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
1129 1.256 tsutsui sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD);
1130 1.256 tsutsui if (!(elink & UHCI_PTR_T)) {
1131 1.124 augustss sqh->qh.qh_elink = htole32(UHCI_PTR_T);
1132 1.223 bouyer usb_syncmem(&sqh->dma,
1133 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
1134 1.223 bouyer sizeof(sqh->qh.qh_elink),
1135 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1136 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1137 1.124 augustss }
1138 1.124 augustss
1139 1.123 augustss pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh);
1140 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
1141 1.223 bouyer sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
1142 1.152 augustss pqh->hlink = sqh->hlink;
1143 1.42 augustss pqh->qh.qh_hlink = sqh->qh.qh_hlink;
1144 1.223 bouyer usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
1145 1.223 bouyer sizeof(pqh->qh.qh_hlink),
1146 1.223 bouyer BUS_DMASYNC_PREWRITE);
1147 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1148 1.123 augustss if (sc->sc_hctl_end == sqh)
1149 1.123 augustss sc->sc_hctl_end = pqh;
1150 1.123 augustss }
1151 1.123 augustss
1152 1.248 mrg /* Add low speed control QH, called with lock held. */
1153 1.123 augustss void
1154 1.123 augustss uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1155 1.123 augustss {
1156 1.123 augustss uhci_soft_qh_t *eqh;
1157 1.123 augustss
1158 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
1159 1.248 mrg
1160 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1161 1.264.4.21 skrll DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
1162 1.264.4.21 skrll
1163 1.123 augustss eqh = sc->sc_lctl_end;
1164 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1165 1.223 bouyer sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
1166 1.152 augustss sqh->hlink = eqh->hlink;
1167 1.123 augustss sqh->qh.qh_hlink = eqh->qh.qh_hlink;
1168 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1169 1.223 bouyer BUS_DMASYNC_PREWRITE);
1170 1.152 augustss eqh->hlink = sqh;
1171 1.123 augustss eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
1172 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1173 1.223 bouyer sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
1174 1.123 augustss sc->sc_lctl_end = sqh;
1175 1.123 augustss }
1176 1.123 augustss
1177 1.248 mrg /* Remove low speed control QH, called with lock held. */
1178 1.123 augustss void
1179 1.123 augustss uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1180 1.123 augustss {
1181 1.123 augustss uhci_soft_qh_t *pqh;
1182 1.256 tsutsui uint32_t elink;
1183 1.123 augustss
1184 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
1185 1.248 mrg
1186 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1187 1.264.4.21 skrll DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
1188 1.264.4.21 skrll
1189 1.124 augustss /* See comment in uhci_remove_hs_ctrl() */
1190 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
1191 1.223 bouyer sizeof(sqh->qh.qh_elink),
1192 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1193 1.256 tsutsui elink = le32toh(sqh->qh.qh_elink);
1194 1.256 tsutsui usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
1195 1.256 tsutsui sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD);
1196 1.256 tsutsui if (!(elink & UHCI_PTR_T)) {
1197 1.124 augustss sqh->qh.qh_elink = htole32(UHCI_PTR_T);
1198 1.223 bouyer usb_syncmem(&sqh->dma,
1199 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
1200 1.223 bouyer sizeof(sqh->qh.qh_elink),
1201 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1202 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1203 1.124 augustss }
1204 1.123 augustss pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh);
1205 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
1206 1.223 bouyer sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
1207 1.152 augustss pqh->hlink = sqh->hlink;
1208 1.123 augustss pqh->qh.qh_hlink = sqh->qh.qh_hlink;
1209 1.223 bouyer usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
1210 1.223 bouyer sizeof(pqh->qh.qh_hlink),
1211 1.223 bouyer BUS_DMASYNC_PREWRITE);
1212 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1213 1.123 augustss if (sc->sc_lctl_end == sqh)
1214 1.123 augustss sc->sc_lctl_end = pqh;
1215 1.1 augustss }
1216 1.1 augustss
1217 1.248 mrg /* Add bulk QH, called with lock held. */
1218 1.1 augustss void
1219 1.119 augustss uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1220 1.1 augustss {
1221 1.42 augustss uhci_soft_qh_t *eqh;
1222 1.1 augustss
1223 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
1224 1.248 mrg
1225 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1226 1.264.4.21 skrll DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
1227 1.264.4.21 skrll
1228 1.42 augustss eqh = sc->sc_bulk_end;
1229 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1230 1.223 bouyer sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
1231 1.152 augustss sqh->hlink = eqh->hlink;
1232 1.42 augustss sqh->qh.qh_hlink = eqh->qh.qh_hlink;
1233 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1234 1.223 bouyer BUS_DMASYNC_PREWRITE);
1235 1.152 augustss eqh->hlink = sqh;
1236 1.121 augustss eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
1237 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1238 1.223 bouyer sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
1239 1.1 augustss sc->sc_bulk_end = sqh;
1240 1.123 augustss uhci_add_loop(sc);
1241 1.1 augustss }
1242 1.1 augustss
1243 1.248 mrg /* Remove bulk QH, called with lock held. */
1244 1.1 augustss void
1245 1.119 augustss uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1246 1.1 augustss {
1247 1.1 augustss uhci_soft_qh_t *pqh;
1248 1.1 augustss
1249 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
1250 1.248 mrg
1251 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1252 1.264.4.21 skrll DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
1253 1.264.4.21 skrll
1254 1.123 augustss uhci_rem_loop(sc);
1255 1.124 augustss /* See comment in uhci_remove_hs_ctrl() */
1256 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
1257 1.223 bouyer sizeof(sqh->qh.qh_elink),
1258 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1259 1.124 augustss if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) {
1260 1.124 augustss sqh->qh.qh_elink = htole32(UHCI_PTR_T);
1261 1.223 bouyer usb_syncmem(&sqh->dma,
1262 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
1263 1.223 bouyer sizeof(sqh->qh.qh_elink),
1264 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1265 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1266 1.124 augustss }
1267 1.92 augustss pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh);
1268 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
1269 1.223 bouyer sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
1270 1.42 augustss pqh->hlink = sqh->hlink;
1271 1.42 augustss pqh->qh.qh_hlink = sqh->qh.qh_hlink;
1272 1.223 bouyer usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
1273 1.223 bouyer sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
1274 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1275 1.1 augustss if (sc->sc_bulk_end == sqh)
1276 1.1 augustss sc->sc_bulk_end = pqh;
1277 1.1 augustss }
1278 1.1 augustss
1279 1.141 augustss Static int uhci_intr1(uhci_softc_t *);
1280 1.141 augustss
1281 1.1 augustss int
1282 1.119 augustss uhci_intr(void *arg)
1283 1.1 augustss {
1284 1.44 augustss uhci_softc_t *sc = arg;
1285 1.248 mrg int ret = 0;
1286 1.248 mrg
1287 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1288 1.264.4.21 skrll
1289 1.248 mrg mutex_spin_enter(&sc->sc_intr_lock);
1290 1.146 augustss
1291 1.216 drochner if (sc->sc_dying || !device_has_power(sc->sc_dev))
1292 1.248 mrg goto done;
1293 1.141 augustss
1294 1.264.4.7 skrll if (sc->sc_bus.ub_usepolling || UREAD2(sc, UHCI_INTR) == 0) {
1295 1.264.4.21 skrll DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0);
1296 1.248 mrg goto done;
1297 1.141 augustss }
1298 1.179 mycroft
1299 1.248 mrg ret = uhci_intr1(sc);
1300 1.248 mrg
1301 1.248 mrg done:
1302 1.248 mrg mutex_spin_exit(&sc->sc_intr_lock);
1303 1.248 mrg return ret;
1304 1.141 augustss }
1305 1.141 augustss
1306 1.141 augustss int
1307 1.141 augustss uhci_intr1(uhci_softc_t *sc)
1308 1.141 augustss {
1309 1.44 augustss int status;
1310 1.44 augustss int ack;
1311 1.1 augustss
1312 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1313 1.264.4.21 skrll
1314 1.67 augustss #ifdef UHCI_DEBUG
1315 1.264.4.46 skrll if (uhcidebug >= 15) {
1316 1.264.4.27 skrll DPRINTF("sc %p", sc, 0, 0, 0);
1317 1.1 augustss uhci_dumpregs(sc);
1318 1.1 augustss }
1319 1.1 augustss #endif
1320 1.117 augustss
1321 1.248 mrg KASSERT(mutex_owned(&sc->sc_intr_lock));
1322 1.248 mrg
1323 1.153 augustss status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS;
1324 1.127 soren if (status == 0) /* The interrupt was not for us. */
1325 1.264.4.13 skrll return 0;
1326 1.127 soren
1327 1.117 augustss if (sc->sc_suspend != PWR_RESUME) {
1328 1.201 jmcneill #ifdef DIAGNOSTIC
1329 1.117 augustss printf("%s: interrupt while not operating ignored\n",
1330 1.216 drochner device_xname(sc->sc_dev));
1331 1.201 jmcneill #endif
1332 1.134 augustss UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */
1333 1.264.4.13 skrll return 0;
1334 1.117 augustss }
1335 1.44 augustss
1336 1.44 augustss ack = 0;
1337 1.44 augustss if (status & UHCI_STS_USBINT)
1338 1.44 augustss ack |= UHCI_STS_USBINT;
1339 1.44 augustss if (status & UHCI_STS_USBEI)
1340 1.44 augustss ack |= UHCI_STS_USBEI;
1341 1.1 augustss if (status & UHCI_STS_RD) {
1342 1.44 augustss ack |= UHCI_STS_RD;
1343 1.118 augustss #ifdef UHCI_DEBUG
1344 1.216 drochner printf("%s: resume detect\n", device_xname(sc->sc_dev));
1345 1.118 augustss #endif
1346 1.1 augustss }
1347 1.1 augustss if (status & UHCI_STS_HSE) {
1348 1.44 augustss ack |= UHCI_STS_HSE;
1349 1.216 drochner printf("%s: host system error\n", device_xname(sc->sc_dev));
1350 1.1 augustss }
1351 1.1 augustss if (status & UHCI_STS_HCPE) {
1352 1.44 augustss ack |= UHCI_STS_HCPE;
1353 1.152 augustss printf("%s: host controller process error\n",
1354 1.216 drochner device_xname(sc->sc_dev));
1355 1.44 augustss }
1356 1.233 msaitoh
1357 1.233 msaitoh /* When HCHalted=1 and Run/Stop=0 , it is normal */
1358 1.233 msaitoh if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) {
1359 1.44 augustss /* no acknowledge needed */
1360 1.136 augustss if (!sc->sc_dying) {
1361 1.152 augustss printf("%s: host controller halted\n",
1362 1.216 drochner device_xname(sc->sc_dev));
1363 1.110 augustss #ifdef UHCI_DEBUG
1364 1.136 augustss uhci_dump_all(sc);
1365 1.110 augustss #endif
1366 1.136 augustss }
1367 1.136 augustss sc->sc_dying = 1;
1368 1.1 augustss }
1369 1.44 augustss
1370 1.132 augustss if (!ack)
1371 1.264.4.13 skrll return 0; /* nothing to acknowledge */
1372 1.132 augustss UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */
1373 1.1 augustss
1374 1.85 augustss usb_schedsoftintr(&sc->sc_bus);
1375 1.85 augustss
1376 1.264.4.21 skrll DPRINTFN(15, "sc %p done", sc, 0, 0, 0);
1377 1.85 augustss
1378 1.264.4.13 skrll return 1;
1379 1.85 augustss }
1380 1.85 augustss
1381 1.85 augustss void
1382 1.133 augustss uhci_softintr(void *v)
1383 1.85 augustss {
1384 1.216 drochner struct usbd_bus *bus = v;
1385 1.264.4.37 skrll uhci_softc_t *sc = UHCI_BUS2SC(bus);
1386 1.264.4.39 skrll struct uhci_xfer *ux, *nextux;
1387 1.85 augustss
1388 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1389 1.264.4.27 skrll DPRINTF("sc %p", sc, 0, 0, 0);
1390 1.248 mrg
1391 1.264.4.21 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1392 1.50 augustss
1393 1.1 augustss /*
1394 1.1 augustss * Interrupts on UHCI really suck. When the host controller
1395 1.1 augustss * interrupts because a transfer is completed there is no
1396 1.1 augustss * way of knowing which transfer it was. You can scan down
1397 1.1 augustss * the TDs and QHs of the previous frame to limit the search,
1398 1.1 augustss * but that assumes that the interrupt was not delayed by more
1399 1.1 augustss * than 1 ms, which may not always be true (e.g. after debug
1400 1.1 augustss * output on a slow console).
1401 1.1 augustss * We scan all interrupt descriptors to see if any have
1402 1.1 augustss * completed.
1403 1.1 augustss */
1404 1.264.4.39 skrll for (ux = TAILQ_FIRST(&sc->sc_intrhead); ux; ux = nextux) {
1405 1.264.4.41 skrll nextux = TAILQ_NEXT(ux, ux_list);
1406 1.264.4.39 skrll uhci_check_intr(sc, ux);
1407 1.178 martin }
1408 1.1 augustss
1409 1.153 augustss if (sc->sc_softwake) {
1410 1.153 augustss sc->sc_softwake = 0;
1411 1.248 mrg cv_broadcast(&sc->sc_softwake_cv);
1412 1.153 augustss }
1413 1.1 augustss }
1414 1.1 augustss
1415 1.1 augustss /* Check for an interrupt. */
1416 1.1 augustss void
1417 1.264.4.39 skrll uhci_check_intr(uhci_softc_t *sc, struct uhci_xfer *ux)
1418 1.1 augustss {
1419 1.264.4.55 skrll uhci_soft_td_t *std, *fstd = NULL, *lstd = NULL;
1420 1.264.4.1 skrll uint32_t status;
1421 1.1 augustss
1422 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1423 1.264.4.39 skrll DPRINTFN(15, "ux %p", ux, 0, 0, 0);
1424 1.264.4.31 skrll
1425 1.264.4.39 skrll KASSERT(ux != NULL);
1426 1.264.4.31 skrll
1427 1.264.4.41 skrll struct usbd_xfer *xfer = &ux->ux_xfer;
1428 1.264.4.39 skrll if (xfer->ux_status == USBD_CANCELLED ||
1429 1.264.4.39 skrll xfer->ux_status == USBD_TIMEOUT) {
1430 1.264.4.39 skrll DPRINTF("aborted xfer %p", xfer, 0, 0, 0);
1431 1.155 augustss return;
1432 1.155 augustss }
1433 1.155 augustss
1434 1.264.4.55 skrll switch (ux->ux_type) {
1435 1.264.4.55 skrll case UX_CTRL:
1436 1.264.4.55 skrll fstd = ux->ux_setup;
1437 1.264.4.55 skrll lstd = ux->ux_stat;
1438 1.264.4.55 skrll break;
1439 1.264.4.55 skrll case UX_BULK:
1440 1.264.4.55 skrll case UX_INTR:
1441 1.264.4.55 skrll case UX_ISOC:
1442 1.264.4.55 skrll fstd = ux->ux_stdstart;
1443 1.264.4.55 skrll lstd = ux->ux_stdend;
1444 1.264.4.55 skrll break;
1445 1.264.4.55 skrll default:
1446 1.264.4.55 skrll KASSERT(false);
1447 1.264.4.55 skrll break;
1448 1.264.4.55 skrll }
1449 1.264.4.55 skrll if (fstd == NULL)
1450 1.1 augustss return;
1451 1.264.4.31 skrll
1452 1.264.4.31 skrll KASSERT(lstd != NULL);
1453 1.264.4.31 skrll
1454 1.223 bouyer usb_syncmem(&lstd->dma,
1455 1.223 bouyer lstd->offs + offsetof(uhci_td_t, td_status),
1456 1.223 bouyer sizeof(lstd->td.td_status),
1457 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1458 1.256 tsutsui status = le32toh(lstd->td.td_status);
1459 1.256 tsutsui usb_syncmem(&lstd->dma,
1460 1.256 tsutsui lstd->offs + offsetof(uhci_td_t, td_status),
1461 1.256 tsutsui sizeof(lstd->td.td_status),
1462 1.256 tsutsui BUS_DMASYNC_PREREAD);
1463 1.258 skrll
1464 1.258 skrll /* If the last TD is not marked active we can complete */
1465 1.258 skrll if (!(status & UHCI_TD_ACTIVE)) {
1466 1.258 skrll done:
1467 1.264.4.39 skrll DPRINTFN(12, "ux=%p done", ux, 0, 0, 0);
1468 1.264.4.21 skrll
1469 1.264.4.39 skrll callout_stop(&xfer->ux_callout);
1470 1.264.4.39 skrll uhci_idone(ux);
1471 1.258 skrll return;
1472 1.258 skrll }
1473 1.258 skrll
1474 1.258 skrll /*
1475 1.258 skrll * If the last TD is still active we need to check whether there
1476 1.258 skrll * is an error somewhere in the middle, or whether there was a
1477 1.258 skrll * short packet (SPD and not ACTIVE).
1478 1.258 skrll */
1479 1.264.4.39 skrll DPRINTFN(12, "active ux=%p", ux, 0, 0, 0);
1480 1.264.4.55 skrll for (std = fstd; std != lstd; std = std->link.std) {
1481 1.258 skrll usb_syncmem(&std->dma,
1482 1.258 skrll std->offs + offsetof(uhci_td_t, td_status),
1483 1.258 skrll sizeof(std->td.td_status),
1484 1.258 skrll BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1485 1.258 skrll status = le32toh(std->td.td_status);
1486 1.258 skrll usb_syncmem(&std->dma,
1487 1.258 skrll std->offs + offsetof(uhci_td_t, td_status),
1488 1.258 skrll sizeof(std->td.td_status), BUS_DMASYNC_PREREAD);
1489 1.258 skrll
1490 1.258 skrll /* If there's an active TD the xfer isn't done. */
1491 1.258 skrll if (status & UHCI_TD_ACTIVE) {
1492 1.264.4.39 skrll DPRINTFN(12, "ux=%p std=%p still active",
1493 1.264.4.39 skrll ux, std, 0, 0);
1494 1.258 skrll return;
1495 1.258 skrll }
1496 1.258 skrll
1497 1.258 skrll /* Any kind of error makes the xfer done. */
1498 1.258 skrll if (status & UHCI_TD_STALLED)
1499 1.258 skrll goto done;
1500 1.258 skrll
1501 1.258 skrll /*
1502 1.258 skrll * If the data phase of a control transfer is short, we need
1503 1.258 skrll * to complete the status stage
1504 1.258 skrll */
1505 1.258 skrll
1506 1.264.4.55 skrll if ((status & UHCI_TD_SPD) && ux->ux_type == UX_CTRL) {
1507 1.258 skrll struct uhci_pipe *upipe =
1508 1.264.4.50 skrll UHCI_PIPE2UPIPE(xfer->ux_pipe);
1509 1.264.4.33 skrll uhci_soft_qh_t *sqh = upipe->ctrl.sqh;
1510 1.264.4.33 skrll uhci_soft_td_t *stat = upipe->ctrl.stat;
1511 1.258 skrll
1512 1.264.4.39 skrll DPRINTFN(12, "ux=%p std=%p control status"
1513 1.264.4.41 skrll "phase needs completion", ux, ux->ux_stdstart, 0, 0);
1514 1.258 skrll
1515 1.258 skrll sqh->qh.qh_elink =
1516 1.258 skrll htole32(stat->physaddr | UHCI_PTR_TD);
1517 1.258 skrll usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1518 1.258 skrll BUS_DMASYNC_PREWRITE);
1519 1.258 skrll break;
1520 1.258 skrll }
1521 1.258 skrll
1522 1.258 skrll /* We want short packets, and it is short: it's done */
1523 1.258 skrll usb_syncmem(&std->dma,
1524 1.258 skrll std->offs + offsetof(uhci_td_t, td_token),
1525 1.258 skrll sizeof(std->td.td_token),
1526 1.258 skrll BUS_DMASYNC_POSTWRITE);
1527 1.258 skrll
1528 1.258 skrll if ((status & UHCI_TD_SPD) &&
1529 1.258 skrll UHCI_TD_GET_ACTLEN(status) <
1530 1.258 skrll UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) {
1531 1.258 skrll goto done;
1532 1.18 augustss }
1533 1.1 augustss }
1534 1.1 augustss }
1535 1.1 augustss
1536 1.248 mrg /* Called with USB lock held. */
1537 1.1 augustss void
1538 1.264.4.39 skrll uhci_idone(struct uhci_xfer *ux)
1539 1.1 augustss {
1540 1.264.4.41 skrll struct usbd_xfer *xfer = &ux->ux_xfer;
1541 1.264.4.37 skrll uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer);
1542 1.264.4.50 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
1543 1.1 augustss uhci_soft_td_t *std;
1544 1.264.4.1 skrll uint32_t status = 0, nstatus;
1545 1.26 augustss int actlen;
1546 1.1 augustss
1547 1.264.4.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1548 1.248 mrg
1549 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1550 1.264.4.39 skrll DPRINTFN(12, "ux=%p", ux, 0, 0, 0);
1551 1.264.4.21 skrll
1552 1.7 augustss #ifdef DIAGNOSTIC
1553 1.92 augustss #ifdef UHCI_DEBUG
1554 1.264.4.41 skrll if (ux->ux_isdone) {
1555 1.264.4.31 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
1556 1.264.4.39 skrll uhci_dump_ii(ux);
1557 1.264.4.31 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
1558 1.7 augustss }
1559 1.7 augustss #endif
1560 1.264.4.41 skrll KASSERT(!ux->ux_isdone);
1561 1.264.4.41 skrll ux->ux_isdone = true;
1562 1.264.4.31 skrll #endif
1563 1.48 augustss
1564 1.264.4.7 skrll if (xfer->ux_nframes != 0) {
1565 1.48 augustss /* Isoc transfer, do things differently. */
1566 1.264.4.33 skrll uhci_soft_td_t **stds = upipe->isoc.stds;
1567 1.126 augustss int i, n, nframes, len;
1568 1.48 augustss
1569 1.264.4.39 skrll DPRINTFN(5, "ux=%p isoc ready", ux, 0, 0, 0);
1570 1.48 augustss
1571 1.264.4.7 skrll nframes = xfer->ux_nframes;
1572 1.48 augustss actlen = 0;
1573 1.264.4.41 skrll n = UHCI_XFER2UXFER(xfer)->ux_curframe;
1574 1.48 augustss for (i = 0; i < nframes; i++) {
1575 1.48 augustss std = stds[n];
1576 1.59 augustss #ifdef UHCI_DEBUG
1577 1.264.4.43 skrll if (uhcidebug >= 5) {
1578 1.264.4.27 skrll DPRINTF("isoc TD %d", i, 0, 0, 0);
1579 1.264.4.53 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
1580 1.48 augustss uhci_dump_td(std);
1581 1.264.4.53 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
1582 1.48 augustss }
1583 1.48 augustss #endif
1584 1.48 augustss if (++n >= UHCI_VFRAMELIST_COUNT)
1585 1.48 augustss n = 0;
1586 1.223 bouyer usb_syncmem(&std->dma,
1587 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
1588 1.223 bouyer sizeof(std->td.td_status),
1589 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1590 1.88 tsutsui status = le32toh(std->td.td_status);
1591 1.126 augustss len = UHCI_TD_GET_ACTLEN(status);
1592 1.264.4.7 skrll xfer->ux_frlengths[i] = len;
1593 1.126 augustss actlen += len;
1594 1.48 augustss }
1595 1.264.4.33 skrll upipe->isoc.inuse -= nframes;
1596 1.264.4.7 skrll xfer->ux_actlen = actlen;
1597 1.264.4.7 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1598 1.140 augustss goto end;
1599 1.48 augustss }
1600 1.48 augustss
1601 1.59 augustss #ifdef UHCI_DEBUG
1602 1.264.4.47 skrll DPRINTFN(10, "ux=%p, xfer=%p, pipe=%p ready", ux, xfer, upipe, 0);
1603 1.264.4.47 skrll if (uhcidebug >= 10) {
1604 1.264.4.47 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
1605 1.264.4.41 skrll uhci_dump_tds(ux->ux_stdstart);
1606 1.264.4.47 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
1607 1.264.4.47 skrll }
1608 1.48 augustss #endif
1609 1.48 augustss
1610 1.26 augustss /* The transfer is done, compute actual length and status. */
1611 1.26 augustss actlen = 0;
1612 1.264.4.41 skrll for (std = ux->ux_stdstart; std != NULL; std = std->link.std) {
1613 1.223 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
1614 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1615 1.88 tsutsui nstatus = le32toh(std->td.td_status);
1616 1.64 augustss if (nstatus & UHCI_TD_ACTIVE)
1617 1.26 augustss break;
1618 1.67 augustss
1619 1.64 augustss status = nstatus;
1620 1.88 tsutsui if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) !=
1621 1.88 tsutsui UHCI_TD_PID_SETUP)
1622 1.26 augustss actlen += UHCI_TD_GET_ACTLEN(status);
1623 1.176 mycroft else {
1624 1.176 mycroft /*
1625 1.176 mycroft * UHCI will report CRCTO in addition to a STALL or NAK
1626 1.176 mycroft * for a SETUP transaction. See section 3.2.2, "TD
1627 1.176 mycroft * CONTROL AND STATUS".
1628 1.176 mycroft */
1629 1.176 mycroft if (status & (UHCI_TD_STALLED | UHCI_TD_NAK))
1630 1.176 mycroft status &= ~UHCI_TD_CRCTO;
1631 1.176 mycroft }
1632 1.1 augustss }
1633 1.38 augustss /* If there are left over TDs we need to update the toggle. */
1634 1.63 augustss if (std != NULL)
1635 1.88 tsutsui upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token));
1636 1.38 augustss
1637 1.1 augustss status &= UHCI_TD_ERROR;
1638 1.264.4.29 skrll DPRINTFN(10, "actlen=%d, status=0x%x", actlen, status, 0, 0);
1639 1.264.4.7 skrll xfer->ux_actlen = actlen;
1640 1.1 augustss if (status != 0) {
1641 1.122 tv
1642 1.264.4.21 skrll DPRINTFN((status == UHCI_TD_STALLED) * 10,
1643 1.264.4.21 skrll "error, addr=%d, endpt=0x%02x",
1644 1.264.4.21 skrll xfer->ux_pipe->up_dev->ud_addr,
1645 1.264.4.21 skrll xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress,
1646 1.264.4.21 skrll 0, 0);
1647 1.264.4.21 skrll DPRINTFN((status == UHCI_TD_STALLED) * 10,
1648 1.264.4.21 skrll "bitstuff=%d crcto =%d nak =%d babble =%d",
1649 1.264.4.45 skrll !!(status & UHCI_TD_BITSTUFF),
1650 1.264.4.45 skrll !!(status & UHCI_TD_CRCTO),
1651 1.264.4.45 skrll !!(status & UHCI_TD_NAK),
1652 1.264.4.45 skrll !!(status & UHCI_TD_BABBLE));
1653 1.264.4.21 skrll DPRINTFN((status == UHCI_TD_STALLED) * 10,
1654 1.264.4.21 skrll "dbuffer =%d stalled =%d active =%d",
1655 1.264.4.45 skrll !!(status & UHCI_TD_DBUFFER),
1656 1.264.4.45 skrll !!(status & UHCI_TD_STALLED),
1657 1.264.4.45 skrll !!(status & UHCI_TD_ACTIVE),
1658 1.264.4.21 skrll 0);
1659 1.122 tv
1660 1.1 augustss if (status == UHCI_TD_STALLED)
1661 1.264.4.7 skrll xfer->ux_status = USBD_STALLED;
1662 1.1 augustss else
1663 1.264.4.7 skrll xfer->ux_status = USBD_IOERROR; /* more info XXX */
1664 1.1 augustss } else {
1665 1.264.4.7 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1666 1.1 augustss }
1667 1.140 augustss
1668 1.140 augustss end:
1669 1.63 augustss usb_transfer_complete(xfer);
1670 1.264.4.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1671 1.264.4.39 skrll DPRINTFN(12, "ux=%p done", ux, 0, 0, 0);
1672 1.1 augustss }
1673 1.1 augustss
1674 1.13 augustss /*
1675 1.13 augustss * Called when a request does not complete.
1676 1.13 augustss */
1677 1.1 augustss void
1678 1.119 augustss uhci_timeout(void *addr)
1679 1.1 augustss {
1680 1.264.4.39 skrll struct usbd_xfer *xfer = addr;
1681 1.264.4.39 skrll struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
1682 1.264.4.39 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
1683 1.153 augustss
1684 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1685 1.264.4.21 skrll
1686 1.264.4.27 skrll DPRINTF("uxfer %p", uxfer, 0, 0, 0);
1687 1.153 augustss
1688 1.153 augustss if (sc->sc_dying) {
1689 1.248 mrg mutex_enter(&sc->sc_lock);
1690 1.264.4.39 skrll uhci_abort_xfer(xfer, USBD_TIMEOUT);
1691 1.248 mrg mutex_exit(&sc->sc_lock);
1692 1.153 augustss return;
1693 1.153 augustss }
1694 1.1 augustss
1695 1.153 augustss /* Execute the abort in a process context. */
1696 1.264.4.41 skrll usb_init_task(&uxfer->ux_aborttask, uhci_timeout_task, xfer,
1697 1.252 jmcneill USB_TASKQ_MPSAFE);
1698 1.264.4.41 skrll usb_add_task(uxfer->ux_xfer.ux_pipe->up_dev, &uxfer->ux_aborttask,
1699 1.204 joerg USB_TASKQ_HC);
1700 1.153 augustss }
1701 1.51 augustss
1702 1.153 augustss void
1703 1.153 augustss uhci_timeout_task(void *addr)
1704 1.153 augustss {
1705 1.264.4.25 skrll struct usbd_xfer *xfer = addr;
1706 1.264.4.37 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
1707 1.153 augustss
1708 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1709 1.264.4.21 skrll
1710 1.264.4.27 skrll DPRINTF("xfer=%p", xfer, 0, 0, 0);
1711 1.67 augustss
1712 1.248 mrg mutex_enter(&sc->sc_lock);
1713 1.153 augustss uhci_abort_xfer(xfer, USBD_TIMEOUT);
1714 1.248 mrg mutex_exit(&sc->sc_lock);
1715 1.1 augustss }
1716 1.1 augustss
1717 1.1 augustss /*
1718 1.1 augustss * Wait here until controller claims to have an interrupt.
1719 1.1 augustss * Then call uhci_intr and return. Use timeout to avoid waiting
1720 1.1 augustss * too long.
1721 1.13 augustss * Only used during boot when interrupts are not enabled yet.
1722 1.1 augustss */
1723 1.1 augustss void
1724 1.264.4.25 skrll uhci_waitintr(uhci_softc_t *sc, struct usbd_xfer *xfer)
1725 1.1 augustss {
1726 1.264.4.7 skrll int timo = xfer->ux_timeout;
1727 1.264.4.39 skrll struct uhci_xfer *ux;
1728 1.13 augustss
1729 1.248 mrg mutex_enter(&sc->sc_lock);
1730 1.248 mrg
1731 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1732 1.264.4.21 skrll DPRINTFN(10, "timeout = %dms", timo, 0, 0, 0);
1733 1.1 augustss
1734 1.264.4.7 skrll xfer->ux_status = USBD_IN_PROGRESS;
1735 1.26 augustss for (; timo >= 0; timo--) {
1736 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_lock);
1737 1.264.4.21 skrll DPRINTFN(20, "0x%04x",
1738 1.264.4.21 skrll UREAD2(sc, UHCI_STS), 0, 0, 0);
1739 1.1 augustss if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) {
1740 1.248 mrg mutex_spin_enter(&sc->sc_intr_lock);
1741 1.141 augustss uhci_intr1(sc);
1742 1.248 mrg mutex_spin_exit(&sc->sc_intr_lock);
1743 1.264.4.7 skrll if (xfer->ux_status != USBD_IN_PROGRESS)
1744 1.248 mrg goto done;
1745 1.1 augustss }
1746 1.1 augustss }
1747 1.13 augustss
1748 1.13 augustss /* Timeout */
1749 1.264.4.27 skrll DPRINTF("timeout", 0, 0, 0, 0);
1750 1.264.4.39 skrll for (ux = TAILQ_FIRST(&sc->sc_intrhead); ux != NULL;
1751 1.264.4.41 skrll ux = TAILQ_NEXT(ux, ux_list))
1752 1.264.4.41 skrll if (&ux->ux_xfer == xfer)
1753 1.264.4.39 skrll break;
1754 1.264.4.31 skrll
1755 1.264.4.39 skrll KASSERT(ux != NULL);
1756 1.264.4.31 skrll
1757 1.264.4.39 skrll uhci_idone(ux);
1758 1.248 mrg
1759 1.248 mrg done:
1760 1.248 mrg mutex_exit(&sc->sc_lock);
1761 1.1 augustss }
1762 1.1 augustss
1763 1.8 augustss void
1764 1.119 augustss uhci_poll(struct usbd_bus *bus)
1765 1.8 augustss {
1766 1.264.4.37 skrll uhci_softc_t *sc = UHCI_BUS2SC(bus);
1767 1.8 augustss
1768 1.248 mrg if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) {
1769 1.248 mrg mutex_spin_enter(&sc->sc_intr_lock);
1770 1.141 augustss uhci_intr1(sc);
1771 1.248 mrg mutex_spin_exit(&sc->sc_intr_lock);
1772 1.248 mrg }
1773 1.8 augustss }
1774 1.8 augustss
1775 1.1 augustss void
1776 1.119 augustss uhci_reset(uhci_softc_t *sc)
1777 1.1 augustss {
1778 1.1 augustss int n;
1779 1.1 augustss
1780 1.1 augustss UHCICMD(sc, UHCI_CMD_HCRESET);
1781 1.1 augustss /* The reset bit goes low when the controller is done. */
1782 1.152 augustss for (n = 0; n < UHCI_RESET_TIMEOUT &&
1783 1.1 augustss (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++)
1784 1.92 augustss usb_delay_ms(&sc->sc_bus, 1);
1785 1.1 augustss if (n >= UHCI_RESET_TIMEOUT)
1786 1.152 augustss printf("%s: controller did not reset\n",
1787 1.216 drochner device_xname(sc->sc_dev));
1788 1.1 augustss }
1789 1.1 augustss
1790 1.16 augustss usbd_status
1791 1.249 drochner uhci_run(uhci_softc_t *sc, int run, int locked)
1792 1.1 augustss {
1793 1.248 mrg int n, running;
1794 1.264.4.1 skrll uint16_t cmd;
1795 1.1 augustss
1796 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1797 1.264.4.21 skrll
1798 1.1 augustss run = run != 0;
1799 1.249 drochner if (!locked)
1800 1.249 drochner mutex_spin_enter(&sc->sc_intr_lock);
1801 1.264.4.21 skrll
1802 1.264.4.27 skrll DPRINTF("setting run=%d", run, 0, 0, 0);
1803 1.71 augustss cmd = UREAD2(sc, UHCI_CMD);
1804 1.71 augustss if (run)
1805 1.71 augustss cmd |= UHCI_CMD_RS;
1806 1.71 augustss else
1807 1.71 augustss cmd &= ~UHCI_CMD_RS;
1808 1.71 augustss UHCICMD(sc, cmd);
1809 1.264.4.54 skrll for (n = 0; n < 10; n++) {
1810 1.1 augustss running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH);
1811 1.1 augustss /* return when we've entered the state we want */
1812 1.1 augustss if (run == running) {
1813 1.249 drochner if (!locked)
1814 1.249 drochner mutex_spin_exit(&sc->sc_intr_lock);
1815 1.264.4.27 skrll DPRINTF("done cmd=0x%x sts=0x%x",
1816 1.264.4.21 skrll UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 0, 0);
1817 1.264.4.13 skrll return USBD_NORMAL_COMPLETION;
1818 1.1 augustss }
1819 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock);
1820 1.1 augustss }
1821 1.249 drochner if (!locked)
1822 1.249 drochner mutex_spin_exit(&sc->sc_intr_lock);
1823 1.216 drochner printf("%s: cannot %s\n", device_xname(sc->sc_dev),
1824 1.14 augustss run ? "start" : "stop");
1825 1.264.4.13 skrll return USBD_IOERROR;
1826 1.1 augustss }
1827 1.1 augustss
1828 1.1 augustss /*
1829 1.1 augustss * Memory management routines.
1830 1.1 augustss * uhci_alloc_std allocates TDs
1831 1.1 augustss * uhci_alloc_sqh allocates QHs
1832 1.7 augustss * These two routines do their own free list management,
1833 1.1 augustss * partly for speed, partly because allocating DMAable memory
1834 1.264.4.28 skrll * has page size granularity so much memory would be wasted if
1835 1.16 augustss * only one TD/QH (32 bytes) was placed in each allocated chunk.
1836 1.1 augustss */
1837 1.1 augustss
1838 1.1 augustss uhci_soft_td_t *
1839 1.119 augustss uhci_alloc_std(uhci_softc_t *sc)
1840 1.1 augustss {
1841 1.1 augustss uhci_soft_td_t *std;
1842 1.63 augustss usbd_status err;
1843 1.42 augustss int i, offs;
1844 1.7 augustss usb_dma_t dma;
1845 1.1 augustss
1846 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1847 1.264.4.21 skrll
1848 1.264.4.55 skrll mutex_enter(&sc->sc_lock);
1849 1.63 augustss if (sc->sc_freetds == NULL) {
1850 1.264.4.21 skrll DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
1851 1.264.4.55 skrll mutex_exit(&sc->sc_lock);
1852 1.264.4.55 skrll
1853 1.63 augustss err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK,
1854 1.63 augustss UHCI_TD_ALIGN, &dma);
1855 1.63 augustss if (err)
1856 1.264.4.52 skrll return NULL;
1857 1.264.4.55 skrll
1858 1.264.4.55 skrll mutex_enter(&sc->sc_lock);
1859 1.248 mrg for (i = 0; i < UHCI_STD_CHUNK; i++) {
1860 1.42 augustss offs = i * UHCI_STD_SIZE;
1861 1.159 augustss std = KERNADDR(&dma, offs);
1862 1.160 augustss std->physaddr = DMAADDR(&dma, offs);
1863 1.223 bouyer std->dma = dma;
1864 1.223 bouyer std->offs = offs;
1865 1.42 augustss std->link.std = sc->sc_freetds;
1866 1.1 augustss sc->sc_freetds = std;
1867 1.1 augustss }
1868 1.1 augustss }
1869 1.1 augustss std = sc->sc_freetds;
1870 1.42 augustss sc->sc_freetds = std->link.std;
1871 1.264.4.55 skrll mutex_exit(&sc->sc_lock);
1872 1.264.4.55 skrll
1873 1.42 augustss memset(&std->td, 0, sizeof(uhci_td_t));
1874 1.264.4.55 skrll
1875 1.1 augustss return std;
1876 1.1 augustss }
1877 1.1 augustss
1878 1.264.4.55 skrll #define TD_IS_FREE 0x12345678
1879 1.264.4.55 skrll
1880 1.1 augustss void
1881 1.264.4.55 skrll uhci_free_std_locked(uhci_softc_t *sc, uhci_soft_td_t *std)
1882 1.1 augustss {
1883 1.264.4.55 skrll KASSERT(mutex_owned(&sc->sc_lock));
1884 1.264.4.55 skrll
1885 1.7 augustss #ifdef DIAGNOSTIC
1886 1.88 tsutsui if (le32toh(std->td.td_token) == TD_IS_FREE) {
1887 1.7 augustss printf("uhci_free_std: freeing free TD %p\n", std);
1888 1.7 augustss return;
1889 1.7 augustss }
1890 1.88 tsutsui std->td.td_token = htole32(TD_IS_FREE);
1891 1.7 augustss #endif
1892 1.264.4.55 skrll
1893 1.42 augustss std->link.std = sc->sc_freetds;
1894 1.1 augustss sc->sc_freetds = std;
1895 1.1 augustss }
1896 1.1 augustss
1897 1.264.4.55 skrll void
1898 1.264.4.55 skrll uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std)
1899 1.264.4.55 skrll {
1900 1.264.4.55 skrll mutex_enter(&sc->sc_lock);
1901 1.264.4.55 skrll uhci_free_std_locked(sc, std);
1902 1.264.4.55 skrll mutex_exit(&sc->sc_lock);
1903 1.264.4.55 skrll }
1904 1.264.4.55 skrll
1905 1.1 augustss uhci_soft_qh_t *
1906 1.119 augustss uhci_alloc_sqh(uhci_softc_t *sc)
1907 1.1 augustss {
1908 1.1 augustss uhci_soft_qh_t *sqh;
1909 1.63 augustss usbd_status err;
1910 1.1 augustss int i, offs;
1911 1.7 augustss usb_dma_t dma;
1912 1.1 augustss
1913 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1914 1.264.4.21 skrll
1915 1.264.4.55 skrll mutex_enter(&sc->sc_lock);
1916 1.63 augustss if (sc->sc_freeqhs == NULL) {
1917 1.264.4.21 skrll DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
1918 1.264.4.55 skrll mutex_exit(&sc->sc_lock);
1919 1.264.4.55 skrll
1920 1.63 augustss err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK,
1921 1.63 augustss UHCI_QH_ALIGN, &dma);
1922 1.63 augustss if (err)
1923 1.264.4.52 skrll return NULL;
1924 1.264.4.55 skrll
1925 1.264.4.55 skrll mutex_enter(&sc->sc_lock);
1926 1.264.4.54 skrll for (i = 0; i < UHCI_SQH_CHUNK; i++) {
1927 1.42 augustss offs = i * UHCI_SQH_SIZE;
1928 1.159 augustss sqh = KERNADDR(&dma, offs);
1929 1.160 augustss sqh->physaddr = DMAADDR(&dma, offs);
1930 1.223 bouyer sqh->dma = dma;
1931 1.223 bouyer sqh->offs = offs;
1932 1.42 augustss sqh->hlink = sc->sc_freeqhs;
1933 1.1 augustss sc->sc_freeqhs = sqh;
1934 1.1 augustss }
1935 1.1 augustss }
1936 1.1 augustss sqh = sc->sc_freeqhs;
1937 1.42 augustss sc->sc_freeqhs = sqh->hlink;
1938 1.264.4.55 skrll mutex_exit(&sc->sc_lock);
1939 1.264.4.55 skrll
1940 1.42 augustss memset(&sqh->qh, 0, sizeof(uhci_qh_t));
1941 1.264.4.55 skrll
1942 1.264.4.13 skrll return sqh;
1943 1.1 augustss }
1944 1.1 augustss
1945 1.1 augustss void
1946 1.119 augustss uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1947 1.1 augustss {
1948 1.264.4.55 skrll KASSERT(mutex_owned(&sc->sc_lock));
1949 1.264.4.55 skrll
1950 1.42 augustss sqh->hlink = sc->sc_freeqhs;
1951 1.1 augustss sc->sc_freeqhs = sqh;
1952 1.1 augustss }
1953 1.1 augustss
1954 1.1 augustss void
1955 1.119 augustss uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std,
1956 1.119 augustss uhci_soft_td_t *stdend)
1957 1.1 augustss {
1958 1.1 augustss uhci_soft_td_t *p;
1959 1.256 tsutsui uint32_t td_link;
1960 1.1 augustss
1961 1.223 bouyer /*
1962 1.223 bouyer * to avoid race condition with the controller which may be looking
1963 1.223 bouyer * at this chain, we need to first invalidate all links, and
1964 1.223 bouyer * then wait for the controller to move to another queue
1965 1.223 bouyer */
1966 1.223 bouyer for (p = std; p != stdend; p = p->link.std) {
1967 1.223 bouyer usb_syncmem(&p->dma,
1968 1.223 bouyer p->offs + offsetof(uhci_td_t, td_link),
1969 1.223 bouyer sizeof(p->td.td_link),
1970 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1971 1.256 tsutsui td_link = le32toh(p->td.td_link);
1972 1.256 tsutsui usb_syncmem(&p->dma,
1973 1.256 tsutsui p->offs + offsetof(uhci_td_t, td_link),
1974 1.256 tsutsui sizeof(p->td.td_link),
1975 1.256 tsutsui BUS_DMASYNC_PREREAD);
1976 1.256 tsutsui if ((td_link & UHCI_PTR_T) == 0) {
1977 1.255 tsutsui p->td.td_link = htole32(UHCI_PTR_T);
1978 1.223 bouyer usb_syncmem(&p->dma,
1979 1.223 bouyer p->offs + offsetof(uhci_td_t, td_link),
1980 1.223 bouyer sizeof(p->td.td_link),
1981 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1982 1.223 bouyer }
1983 1.223 bouyer }
1984 1.223 bouyer delay(UHCI_QH_REMOVE_DELAY);
1985 1.223 bouyer
1986 1.1 augustss for (; std != stdend; std = p) {
1987 1.42 augustss p = std->link.std;
1988 1.1 augustss uhci_free_std(sc, std);
1989 1.1 augustss }
1990 1.1 augustss }
1991 1.1 augustss
1992 1.1 augustss usbd_status
1993 1.264.4.55 skrll uhci_alloc_std_chain(uhci_softc_t *sc, struct usbd_xfer *xfer, int alen,
1994 1.264.4.55 skrll int rd, uhci_soft_td_t **sp, uhci_soft_td_t **ep)
1995 1.1 augustss {
1996 1.1 augustss uhci_soft_td_t *p, *lastp;
1997 1.1 augustss uhci_physaddr_t lastlink;
1998 1.264.4.55 skrll int i, l, maxp;
1999 1.264.4.55 skrll int len;
2000 1.264.4.1 skrll uint32_t status;
2001 1.264.4.55 skrll struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
2002 1.264.4.55 skrll int addr = xfer->ux_pipe->up_dev->ud_addr;
2003 1.264.4.55 skrll int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;
2004 1.264.4.55 skrll usb_dma_t *dma = &xfer->ux_dmabuf;
2005 1.264.4.55 skrll uint16_t flags = xfer->ux_flags;
2006 1.1 augustss
2007 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2008 1.264.4.21 skrll
2009 1.264.4.55 skrll DPRINTFN(8, "xfer=%p pipe=%p", xfer, xfer->ux_pipe, 0, 0);
2010 1.264.4.21 skrll DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d",
2011 1.264.4.55 skrll addr, UE_GET_ADDR(endpt), alen, xfer->ux_pipe->up_dev->ud_speed);
2012 1.248 mrg
2013 1.264.4.55 skrll ASSERT_SLEEPABLE();
2014 1.264.4.55 skrll KASSERT(sp);
2015 1.248 mrg
2016 1.264.4.55 skrll len = alen;
2017 1.264.4.55 skrll maxp = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize);
2018 1.1 augustss if (maxp == 0) {
2019 1.1 augustss printf("uhci_alloc_std_chain: maxp=0\n");
2020 1.264.4.13 skrll return USBD_INVAL;
2021 1.1 augustss }
2022 1.264.4.55 skrll size_t ntd = (len + maxp - 1) / maxp;
2023 1.73 augustss if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0)
2024 1.73 augustss ntd++;
2025 1.264.4.55 skrll DPRINTFN(10, "maxp=%d ntd=%d", maxp, ntd, 0, 0);
2026 1.264.4.21 skrll
2027 1.264.4.55 skrll uxfer->ux_stds = NULL;
2028 1.264.4.55 skrll uxfer->ux_nstd = ntd;
2029 1.73 augustss if (ntd == 0) {
2030 1.264.4.55 skrll *sp = NULL;
2031 1.264.4.55 skrll if (ep)
2032 1.264.4.55 skrll *ep = NULL;
2033 1.264.4.27 skrll DPRINTF("ntd=0", 0, 0, 0, 0);
2034 1.264.4.13 skrll return USBD_NORMAL_COMPLETION;
2035 1.73 augustss }
2036 1.264.4.55 skrll uxfer->ux_stds = kmem_alloc(sizeof(uhci_soft_td_t *) * ntd,
2037 1.264.4.55 skrll KM_SLEEP);
2038 1.264.4.55 skrll
2039 1.121 augustss lastp = NULL;
2040 1.1 augustss ntd--;
2041 1.33 augustss status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE);
2042 1.264.4.55 skrll if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_LOW)
2043 1.18 augustss status |= UHCI_TD_LS;
2044 1.73 augustss if (flags & USBD_SHORT_XFER_OK)
2045 1.18 augustss status |= UHCI_TD_SPD;
2046 1.1 augustss for (i = ntd; i >= 0; i--) {
2047 1.1 augustss p = uhci_alloc_std(sc);
2048 1.63 augustss if (p == NULL) {
2049 1.149 augustss uhci_free_std_chain(sc, lastp, NULL);
2050 1.264.4.13 skrll return USBD_NOMEM;
2051 1.1 augustss }
2052 1.264.4.55 skrll uxfer->ux_stds[i] = p;
2053 1.1 augustss if (i == ntd) {
2054 1.1 augustss /* last TD */
2055 1.1 augustss l = len % maxp;
2056 1.73 augustss if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER))
2057 1.73 augustss l = maxp;
2058 1.264.4.55 skrll if (ep)
2059 1.264.4.55 skrll *ep = p;
2060 1.264.4.55 skrll lastlink = UHCI_PTR_T;
2061 1.264.4.55 skrll } else {
2062 1.1 augustss l = maxp;
2063 1.264.4.55 skrll lastlink = p->physaddr;
2064 1.264.4.55 skrll }
2065 1.264.4.55 skrll p->link.std = lastp;
2066 1.264.4.55 skrll p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD);
2067 1.264.4.55 skrll p->td.td_status = htole32(status);
2068 1.264.4.55 skrll p->td.td_token = htole32(
2069 1.264.4.55 skrll (rd ? UHCI_TD_PID_IN : UHCI_TD_PID_OUT) |
2070 1.264.4.55 skrll UHCI_TD_SET_MAXLEN(l) |
2071 1.264.4.55 skrll UHCI_TD_SET_ENDPT(UE_GET_ADDR(endpt)) |
2072 1.264.4.55 skrll UHCI_TD_SET_DEVADDR(addr)
2073 1.264.4.55 skrll );
2074 1.160 augustss p->td.td_buffer = htole32(DMAADDR(dma, i * maxp));
2075 1.264.4.55 skrll DPRINTF("std %p link 0x%08x status 0x%08x token 0x%08x",
2076 1.264.4.55 skrll p, le32toh(p->td.td_link), le32toh(p->td.td_status),
2077 1.264.4.55 skrll le32toh(p->td.td_token));
2078 1.264.4.55 skrll
2079 1.264.4.55 skrll lastp = p;
2080 1.1 augustss }
2081 1.1 augustss *sp = lastp;
2082 1.264.4.21 skrll
2083 1.264.4.13 skrll return USBD_NORMAL_COMPLETION;
2084 1.1 augustss }
2085 1.1 augustss
2086 1.264.4.55 skrll Static void
2087 1.264.4.55 skrll uhci_free_stds(uhci_softc_t *sc, struct uhci_xfer *ux)
2088 1.264.4.55 skrll {
2089 1.264.4.55 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2090 1.264.4.55 skrll
2091 1.264.4.55 skrll DPRINTFN(8, "ux=%p", ux, 0, 0, 0);
2092 1.264.4.55 skrll
2093 1.264.4.55 skrll mutex_enter(&sc->sc_lock);
2094 1.264.4.55 skrll for (size_t i = 0; i < ux->ux_nstd; i++) {
2095 1.264.4.55 skrll uhci_soft_td_t *std = ux->ux_stds[i];
2096 1.264.4.55 skrll #ifdef DIAGNOSTIC
2097 1.264.4.55 skrll if (le32toh(std->td.td_token) == TD_IS_FREE) {
2098 1.264.4.55 skrll printf("uhci_free_std: freeing free TD %p\n", std);
2099 1.264.4.55 skrll return;
2100 1.264.4.55 skrll }
2101 1.264.4.55 skrll std->td.td_token = htole32(TD_IS_FREE);
2102 1.264.4.55 skrll #endif
2103 1.264.4.55 skrll ux->ux_stds[i]->link.std = sc->sc_freetds;
2104 1.264.4.55 skrll sc->sc_freetds = std;
2105 1.264.4.55 skrll }
2106 1.264.4.55 skrll mutex_exit(&sc->sc_lock);
2107 1.264.4.55 skrll }
2108 1.264.4.55 skrll
2109 1.264.4.55 skrll
2110 1.264.4.55 skrll Static void
2111 1.264.4.55 skrll uhci_reset_std_chain(uhci_softc_t *sc, struct usbd_xfer *xfer,
2112 1.264.4.55 skrll int length, int isread, int *toggle,
2113 1.264.4.55 skrll uhci_soft_td_t *fstd, uhci_soft_td_t **lstd)
2114 1.264.4.55 skrll {
2115 1.264.4.55 skrll struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
2116 1.264.4.55 skrll struct usbd_pipe *pipe = xfer->ux_pipe;
2117 1.264.4.55 skrll usb_dma_t *dma = &xfer->ux_dmabuf;
2118 1.264.4.55 skrll uint16_t flags = xfer->ux_flags;
2119 1.264.4.55 skrll uhci_soft_td_t *std, *prev;
2120 1.264.4.55 skrll int len = length;
2121 1.264.4.55 skrll int tog = *toggle;
2122 1.264.4.55 skrll int maxp;
2123 1.264.4.55 skrll uint32_t status;
2124 1.264.4.55 skrll size_t i;
2125 1.264.4.55 skrll
2126 1.264.4.55 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2127 1.264.4.55 skrll DPRINTFN(8, "xfer=%p len %d isread %d toggle %d", xfer,
2128 1.264.4.55 skrll len, isread, *toggle);
2129 1.264.4.55 skrll
2130 1.264.4.55 skrll KASSERT(len != 0 || (flags & USBD_FORCE_SHORT_XFER));
2131 1.264.4.55 skrll
2132 1.264.4.55 skrll maxp = UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize);
2133 1.264.4.55 skrll KASSERT(maxp != 0);
2134 1.264.4.55 skrll
2135 1.264.4.55 skrll status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE);
2136 1.264.4.55 skrll if (pipe->up_dev->ud_speed == USB_SPEED_LOW)
2137 1.264.4.55 skrll status |= UHCI_TD_LS;
2138 1.264.4.55 skrll if (flags & USBD_SHORT_XFER_OK)
2139 1.264.4.55 skrll status |= UHCI_TD_SPD;
2140 1.264.4.55 skrll usb_syncmem(dma, 0, len,
2141 1.264.4.55 skrll isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
2142 1.264.4.55 skrll
2143 1.264.4.55 skrll std = prev = NULL;
2144 1.264.4.55 skrll for (i = 0; i < uxfer->ux_nstd; i++, prev = std) {
2145 1.264.4.55 skrll int l = len;
2146 1.264.4.55 skrll std = uxfer->ux_stds[i];
2147 1.264.4.55 skrll if (l > maxp)
2148 1.264.4.55 skrll l = maxp;
2149 1.264.4.55 skrll if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER))
2150 1.264.4.55 skrll break;
2151 1.264.4.55 skrll
2152 1.264.4.55 skrll if (prev) {
2153 1.264.4.55 skrll prev->link.std = std;
2154 1.264.4.55 skrll prev->td.td_link = htole32(
2155 1.264.4.55 skrll std->physaddr | UHCI_PTR_VF | UHCI_PTR_TD
2156 1.264.4.55 skrll );
2157 1.264.4.55 skrll usb_syncmem(&prev->dma, prev->offs, sizeof(prev->td),
2158 1.264.4.55 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2159 1.264.4.55 skrll }
2160 1.264.4.55 skrll
2161 1.264.4.55 skrll int addr __diagused = xfer->ux_pipe->up_dev->ud_addr;
2162 1.264.4.55 skrll int endpt __diagused = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;
2163 1.264.4.55 skrll KASSERTMSG(UHCI_TD_GET_ENDPT(le32toh(std->td.td_token)) == UE_GET_ADDR(endpt),
2164 1.264.4.55 skrll "%" __PRIuBIT " vs %d (0x%08x) in %p",
2165 1.264.4.55 skrll UHCI_TD_GET_ENDPT(le32toh(std->td.td_token)),
2166 1.264.4.55 skrll UE_GET_ADDR(endpt), le32toh(std->td.td_token), std);
2167 1.264.4.55 skrll KASSERTMSG(UHCI_TD_GET_DEVADDR(le32toh(std->td.td_token)) == addr,
2168 1.264.4.55 skrll "%" __PRIuBIT " vs %d (0x%08x) in %p",
2169 1.264.4.55 skrll UHCI_TD_GET_DEVADDR(le32toh(std->td.td_token)), addr,
2170 1.264.4.55 skrll le32toh(std->td.td_token), std);
2171 1.264.4.55 skrll
2172 1.264.4.55 skrll usb_syncmem(&std->dma, std->offs, sizeof(std->td),
2173 1.264.4.55 skrll BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2174 1.264.4.55 skrll
2175 1.264.4.55 skrll std->td.td_status = htole32(status);
2176 1.264.4.55 skrll std->td.td_token &= ~htole32(
2177 1.264.4.55 skrll UHCI_TD_PID_MASK |
2178 1.264.4.55 skrll UHCI_TD_DT_MASK |
2179 1.264.4.55 skrll UHCI_TD_MAXLEN_MASK
2180 1.264.4.55 skrll );
2181 1.264.4.55 skrll std->td.td_token |= htole32(
2182 1.264.4.55 skrll UHCI_TD_SET_PID(isread ? UHCI_TD_PID_IN : UHCI_TD_PID_OUT) |
2183 1.264.4.55 skrll UHCI_TD_SET_DT(tog) |
2184 1.264.4.55 skrll UHCI_TD_SET_MAXLEN(l)
2185 1.264.4.55 skrll );
2186 1.264.4.55 skrll std->td.td_link &= ~htole32(UHCI_PTR_T);
2187 1.264.4.55 skrll
2188 1.264.4.55 skrll usb_syncmem(&std->dma, std->offs, sizeof(std->td),
2189 1.264.4.55 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2190 1.264.4.55 skrll tog ^= 1;
2191 1.264.4.55 skrll
2192 1.264.4.55 skrll len -= l;
2193 1.264.4.55 skrll if (len == 0)
2194 1.264.4.55 skrll break;
2195 1.264.4.55 skrll }
2196 1.264.4.55 skrll KASSERTMSG(len == 0, "xfer %p alen %d len %d mps %d ux_nqtd %zu i %zu",
2197 1.264.4.55 skrll xfer, length, len, maxp, uxfer->ux_nstd, i);
2198 1.264.4.55 skrll
2199 1.264.4.55 skrll if (i < uxfer->ux_nstd) {
2200 1.264.4.55 skrll /*
2201 1.264.4.55 skrll * The full allocation chain wasn't used, so we need to
2202 1.264.4.55 skrll * terminate it.
2203 1.264.4.55 skrll */
2204 1.264.4.55 skrll std->link.std = NULL;
2205 1.264.4.55 skrll std->td.td_link = htole32(UHCI_PTR_T);
2206 1.264.4.55 skrll usb_syncmem(&std->dma, std->offs, sizeof(std->td),
2207 1.264.4.55 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2208 1.264.4.55 skrll }
2209 1.264.4.55 skrll *lstd = std;
2210 1.264.4.55 skrll *toggle = tog;
2211 1.264.4.55 skrll }
2212 1.264.4.55 skrll
2213 1.38 augustss void
2214 1.264.4.25 skrll uhci_device_clear_toggle(struct usbd_pipe *pipe)
2215 1.38 augustss {
2216 1.264.4.50 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
2217 1.38 augustss upipe->nexttoggle = 0;
2218 1.38 augustss }
2219 1.38 augustss
2220 1.38 augustss void
2221 1.264.4.25 skrll uhci_noop(struct usbd_pipe *pipe)
2222 1.38 augustss {
2223 1.38 augustss }
2224 1.38 augustss
2225 1.264.4.55 skrll int
2226 1.264.4.55 skrll uhci_device_bulk_init(struct usbd_xfer *xfer)
2227 1.264.4.55 skrll {
2228 1.264.4.55 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2229 1.264.4.55 skrll struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
2230 1.264.4.55 skrll usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc;
2231 1.264.4.55 skrll int endpt = ed->bEndpointAddress;
2232 1.264.4.55 skrll int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2233 1.264.4.55 skrll int len = xfer->ux_bufsize;
2234 1.264.4.55 skrll int err = 0;
2235 1.264.4.55 skrll
2236 1.264.4.55 skrll
2237 1.264.4.55 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2238 1.264.4.55 skrll DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, len, xfer->ux_flags, 0);
2239 1.264.4.55 skrll
2240 1.264.4.55 skrll if (sc->sc_dying)
2241 1.264.4.55 skrll return USBD_IOERROR;
2242 1.264.4.55 skrll
2243 1.264.4.55 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
2244 1.264.4.55 skrll
2245 1.264.4.55 skrll uxfer->ux_type = UX_BULK;
2246 1.264.4.55 skrll err = uhci_alloc_std_chain(sc, xfer, len, isread, &uxfer->ux_stdstart,
2247 1.264.4.55 skrll &uxfer->ux_stdend);
2248 1.264.4.55 skrll if (err)
2249 1.264.4.55 skrll return err;
2250 1.264.4.55 skrll
2251 1.264.4.55 skrll #ifdef UHCI_DEBUG
2252 1.264.4.55 skrll if (uhcidebug >= 10) {
2253 1.264.4.55 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
2254 1.264.4.55 skrll uhci_dump_tds(uxfer->ux_stdstart);
2255 1.264.4.55 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
2256 1.264.4.55 skrll }
2257 1.264.4.55 skrll #endif
2258 1.264.4.55 skrll
2259 1.264.4.55 skrll return 0;
2260 1.264.4.55 skrll }
2261 1.264.4.55 skrll
2262 1.264.4.55 skrll Static void
2263 1.264.4.55 skrll uhci_device_bulk_fini(struct usbd_xfer *xfer)
2264 1.264.4.55 skrll {
2265 1.264.4.55 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2266 1.264.4.55 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
2267 1.264.4.55 skrll
2268 1.264.4.55 skrll KASSERT(ux->ux_type == UX_BULK);
2269 1.264.4.55 skrll
2270 1.264.4.55 skrll uhci_free_stds(sc, ux);
2271 1.264.4.55 skrll if (ux->ux_nstd)
2272 1.264.4.55 skrll kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd);
2273 1.264.4.55 skrll }
2274 1.264.4.55 skrll
2275 1.1 augustss usbd_status
2276 1.264.4.25 skrll uhci_device_bulk_transfer(struct usbd_xfer *xfer)
2277 1.1 augustss {
2278 1.264.4.37 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2279 1.63 augustss usbd_status err;
2280 1.16 augustss
2281 1.52 augustss /* Insert last in queue. */
2282 1.248 mrg mutex_enter(&sc->sc_lock);
2283 1.63 augustss err = usb_insert_transfer(xfer);
2284 1.248 mrg mutex_exit(&sc->sc_lock);
2285 1.63 augustss if (err)
2286 1.264.4.13 skrll return err;
2287 1.52 augustss
2288 1.152 augustss /*
2289 1.92 augustss * Pipe isn't running (otherwise err would be USBD_INPROG),
2290 1.92 augustss * so start it first.
2291 1.67 augustss */
2292 1.264.4.13 skrll return uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2293 1.16 augustss }
2294 1.16 augustss
2295 1.16 augustss usbd_status
2296 1.264.4.25 skrll uhci_device_bulk_start(struct usbd_xfer *xfer)
2297 1.16 augustss {
2298 1.264.4.50 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
2299 1.264.4.39 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
2300 1.264.4.37 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2301 1.55 augustss uhci_soft_td_t *data, *dataend;
2302 1.1 augustss uhci_soft_qh_t *sqh;
2303 1.264.4.55 skrll int len;
2304 1.264.4.55 skrll int endpt;
2305 1.264.4.55 skrll int isread;
2306 1.1 augustss
2307 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2308 1.264.4.55 skrll DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length,
2309 1.264.4.55 skrll xfer->ux_flags, 0);
2310 1.1 augustss
2311 1.82 augustss if (sc->sc_dying)
2312 1.264.4.13 skrll return USBD_IOERROR;
2313 1.82 augustss
2314 1.264.4.31 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
2315 1.264.4.55 skrll KASSERT(xfer->ux_length <= xfer->ux_bufsize);
2316 1.248 mrg
2317 1.264.4.7 skrll len = xfer->ux_length;
2318 1.264.4.7 skrll endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
2319 1.45 augustss isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2320 1.264.4.33 skrll sqh = upipe->bulk.sqh;
2321 1.1 augustss
2322 1.264.4.55 skrll /* Take lock here to protect nexttoggle */
2323 1.264.4.55 skrll mutex_enter(&sc->sc_lock);
2324 1.1 augustss
2325 1.264.4.55 skrll uhci_reset_std_chain(sc, xfer, len, isread, &upipe->nexttoggle,
2326 1.264.4.55 skrll ux->ux_stdstart, &dataend);
2327 1.264.4.55 skrll
2328 1.264.4.55 skrll data = ux->ux_stdstart;
2329 1.264.4.55 skrll ux->ux_stdend = dataend;
2330 1.88 tsutsui dataend->td.td_status |= htole32(UHCI_TD_IOC);
2331 1.223 bouyer usb_syncmem(&dataend->dma,
2332 1.223 bouyer dataend->offs + offsetof(uhci_td_t, td_status),
2333 1.223 bouyer sizeof(dataend->td.td_status),
2334 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2335 1.223 bouyer
2336 1.59 augustss #ifdef UHCI_DEBUG
2337 1.264.4.55 skrll if (uhcidebug >= 10) {
2338 1.264.4.47 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
2339 1.264.4.55 skrll DPRINTFN(10, "before transfer", 0, 0, 0, 0);
2340 1.264.4.55 skrll uhci_dump_tds(ux->ux_stdstart);
2341 1.264.4.47 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
2342 1.1 augustss }
2343 1.1 augustss #endif
2344 1.1 augustss
2345 1.264.4.41 skrll KASSERT(ux->ux_isdone);
2346 1.7 augustss #ifdef DIAGNOSTIC
2347 1.264.4.41 skrll ux->ux_isdone = false;
2348 1.7 augustss #endif
2349 1.1 augustss
2350 1.55 augustss sqh->elink = data;
2351 1.121 augustss sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD);
2352 1.223 bouyer /* uhci_add_bulk() will do usb_syncmem(sqh) */
2353 1.1 augustss
2354 1.1 augustss uhci_add_bulk(sc, sqh);
2355 1.264.4.56 skrll uhci_add_intr_list(sc, ux);
2356 1.1 augustss
2357 1.264.4.7 skrll if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
2358 1.264.4.7 skrll callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
2359 1.264.4.39 skrll uhci_timeout, xfer);
2360 1.13 augustss }
2361 1.264.4.7 skrll xfer->ux_status = USBD_IN_PROGRESS;
2362 1.264.4.55 skrll mutex_exit(&sc->sc_lock);
2363 1.1 augustss
2364 1.264.4.7 skrll if (sc->sc_bus.ub_usepolling)
2365 1.63 augustss uhci_waitintr(sc, xfer);
2366 1.26 augustss
2367 1.264.4.13 skrll return USBD_IN_PROGRESS;
2368 1.1 augustss }
2369 1.1 augustss
2370 1.1 augustss /* Abort a device bulk request. */
2371 1.1 augustss void
2372 1.264.4.25 skrll uhci_device_bulk_abort(struct usbd_xfer *xfer)
2373 1.1 augustss {
2374 1.264.4.37 skrll uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer);
2375 1.248 mrg
2376 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2377 1.248 mrg
2378 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2379 1.264.4.21 skrll
2380 1.66 augustss uhci_abort_xfer(xfer, USBD_CANCELLED);
2381 1.33 augustss }
2382 1.33 augustss
2383 1.92 augustss /*
2384 1.154 augustss * Abort a device request.
2385 1.154 augustss * If this routine is called at splusb() it guarantees that the request
2386 1.154 augustss * will be removed from the hardware scheduling and that the callback
2387 1.154 augustss * for it will be called with USBD_CANCELLED status.
2388 1.154 augustss * It's impossible to guarantee that the requested transfer will not
2389 1.154 augustss * have happened since the hardware runs concurrently.
2390 1.154 augustss * If the transaction has already happened we rely on the ordinary
2391 1.154 augustss * interrupt processing to process it.
2392 1.248 mrg * XXX This is most probably wrong.
2393 1.248 mrg * XXXMRG this doesn't make sense anymore.
2394 1.92 augustss */
2395 1.33 augustss void
2396 1.264.4.25 skrll uhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status)
2397 1.33 augustss {
2398 1.264.4.39 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
2399 1.264.4.50 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
2400 1.264.4.37 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2401 1.33 augustss uhci_soft_td_t *std;
2402 1.188 augustss int wake;
2403 1.65 augustss
2404 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2405 1.264.4.21 skrll DPRINTFN(1,"xfer=%p, status=%d", xfer, status, 0, 0);
2406 1.33 augustss
2407 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2408 1.264.4.3 skrll ASSERT_SLEEPABLE();
2409 1.248 mrg
2410 1.153 augustss if (sc->sc_dying) {
2411 1.153 augustss /* If we're dying, just do the software part. */
2412 1.264.4.7 skrll xfer->ux_status = status; /* make software ignore it */
2413 1.264.4.7 skrll callout_stop(&xfer->ux_callout);
2414 1.153 augustss usb_transfer_complete(xfer);
2415 1.194 christos return;
2416 1.92 augustss }
2417 1.92 augustss
2418 1.153 augustss /*
2419 1.188 augustss * If an abort is already in progress then just wait for it to
2420 1.188 augustss * complete and return.
2421 1.188 augustss */
2422 1.264.4.7 skrll if (xfer->ux_hcflags & UXFER_ABORTING) {
2423 1.264.4.21 skrll DPRINTFN(2, "already aborting", 0, 0, 0, 0);
2424 1.188 augustss #ifdef DIAGNOSTIC
2425 1.188 augustss if (status == USBD_TIMEOUT)
2426 1.188 augustss printf("uhci_abort_xfer: TIMEOUT while aborting\n");
2427 1.188 augustss #endif
2428 1.188 augustss /* Override the status which might be USBD_TIMEOUT. */
2429 1.264.4.7 skrll xfer->ux_status = status;
2430 1.264.4.21 skrll DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0);
2431 1.264.4.7 skrll xfer->ux_hcflags |= UXFER_ABORTWAIT;
2432 1.264.4.7 skrll while (xfer->ux_hcflags & UXFER_ABORTING)
2433 1.264.4.7 skrll cv_wait(&xfer->ux_hccv, &sc->sc_lock);
2434 1.248 mrg goto done;
2435 1.188 augustss }
2436 1.264.4.7 skrll xfer->ux_hcflags |= UXFER_ABORTING;
2437 1.188 augustss
2438 1.188 augustss /*
2439 1.153 augustss * Step 1: Make interrupt routine and hardware ignore xfer.
2440 1.153 augustss */
2441 1.264.4.7 skrll xfer->ux_status = status; /* make software ignore it */
2442 1.264.4.7 skrll callout_stop(&xfer->ux_callout);
2443 1.264.4.39 skrll DPRINTF("stop ux=%p", ux, 0, 0, 0);
2444 1.264.4.41 skrll for (std = ux->ux_stdstart; std != NULL; std = std->link.std) {
2445 1.223 bouyer usb_syncmem(&std->dma,
2446 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
2447 1.223 bouyer sizeof(std->td.td_status),
2448 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2449 1.92 augustss std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC));
2450 1.223 bouyer usb_syncmem(&std->dma,
2451 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
2452 1.223 bouyer sizeof(std->td.td_status),
2453 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2454 1.223 bouyer }
2455 1.92 augustss
2456 1.162 augustss /*
2457 1.153 augustss * Step 2: Wait until we know hardware has finished any possible
2458 1.153 augustss * use of the xfer. Also make sure the soft interrupt routine
2459 1.153 augustss * has run.
2460 1.153 augustss */
2461 1.248 mrg /* Hardware finishes in 1ms */
2462 1.264.4.7 skrll usb_delay_ms_locked(upipe->pipe.up_dev->ud_bus, 2, &sc->sc_lock);
2463 1.153 augustss sc->sc_softwake = 1;
2464 1.153 augustss usb_schedsoftintr(&sc->sc_bus);
2465 1.264.4.27 skrll DPRINTF("cv_wait", 0, 0, 0, 0);
2466 1.248 mrg cv_wait(&sc->sc_softwake_cv, &sc->sc_lock);
2467 1.162 augustss
2468 1.153 augustss /*
2469 1.153 augustss * Step 3: Execute callback.
2470 1.153 augustss */
2471 1.264.4.27 skrll DPRINTF("callback", 0, 0, 0, 0);
2472 1.100 augustss #ifdef DIAGNOSTIC
2473 1.264.4.41 skrll ux->ux_isdone = true;
2474 1.100 augustss #endif
2475 1.264.4.7 skrll wake = xfer->ux_hcflags & UXFER_ABORTWAIT;
2476 1.264.4.7 skrll xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT);
2477 1.106 augustss usb_transfer_complete(xfer);
2478 1.188 augustss if (wake)
2479 1.264.4.7 skrll cv_broadcast(&xfer->ux_hccv);
2480 1.248 mrg done:
2481 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2482 1.1 augustss }
2483 1.1 augustss
2484 1.1 augustss /* Close a device bulk pipe. */
2485 1.1 augustss void
2486 1.264.4.25 skrll uhci_device_bulk_close(struct usbd_pipe *pipe)
2487 1.1 augustss {
2488 1.264.4.50 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
2489 1.264.4.37 skrll uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
2490 1.1 augustss
2491 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2492 1.248 mrg
2493 1.264.4.33 skrll uhci_free_sqh(sc, upipe->bulk.sqh);
2494 1.236 drochner
2495 1.264.4.7 skrll pipe->up_endpoint->ue_toggle = upipe->nexttoggle;
2496 1.1 augustss }
2497 1.1 augustss
2498 1.264.4.55 skrll int
2499 1.264.4.55 skrll uhci_device_ctrl_init(struct usbd_xfer *xfer)
2500 1.1 augustss {
2501 1.264.4.55 skrll struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
2502 1.264.4.55 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
2503 1.264.4.55 skrll usb_device_request_t *req = &xfer->ux_request;
2504 1.264.4.55 skrll struct usbd_device *dev = upipe->pipe.up_dev;
2505 1.264.4.55 skrll uhci_softc_t *sc = dev->ud_bus->ub_hcpriv;
2506 1.264.4.55 skrll int addr = dev->ud_addr;
2507 1.264.4.55 skrll int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
2508 1.264.4.55 skrll uhci_soft_td_t *setup, *data, *stat, *next, *dataend;
2509 1.264.4.55 skrll int len;
2510 1.264.4.55 skrll uint32_t ls;
2511 1.63 augustss usbd_status err;
2512 1.264.4.55 skrll int isread;
2513 1.16 augustss
2514 1.264.4.55 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2515 1.264.4.55 skrll DPRINTFN(3, "len=%d, addr=%d, endpt=%d", xfer->ux_bufsize,
2516 1.264.4.55 skrll dev->ud_addr, endpt, 0);
2517 1.16 augustss
2518 1.264.4.55 skrll ls = dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0;
2519 1.264.4.55 skrll isread = req->bmRequestType & UT_READ;
2520 1.264.4.55 skrll len = xfer->ux_bufsize;
2521 1.1 augustss
2522 1.264.4.55 skrll uxfer->ux_type = UX_CTRL;
2523 1.264.4.55 skrll setup = upipe->ctrl.setup;
2524 1.264.4.55 skrll stat = upipe->ctrl.stat;
2525 1.82 augustss
2526 1.264.4.55 skrll /* Set up data transaction */
2527 1.264.4.55 skrll if (len != 0) {
2528 1.264.4.55 skrll err = uhci_alloc_std_chain(sc, xfer, len, isread, &data,
2529 1.264.4.55 skrll &dataend);
2530 1.264.4.55 skrll if (err)
2531 1.264.4.55 skrll return err;
2532 1.264.4.55 skrll next = data;
2533 1.264.4.55 skrll dataend->link.std = stat;
2534 1.264.4.55 skrll dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD);
2535 1.264.4.55 skrll } else {
2536 1.264.4.55 skrll next = stat;
2537 1.264.4.55 skrll }
2538 1.1 augustss
2539 1.264.4.55 skrll setup->link.std = next;
2540 1.264.4.55 skrll setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD);
2541 1.264.4.55 skrll setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls |
2542 1.264.4.55 skrll UHCI_TD_ACTIVE);
2543 1.264.4.55 skrll setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof(*req), endpt, addr));
2544 1.264.4.55 skrll setup->td.td_buffer = htole32(DMAADDR(&upipe->ctrl.reqdma, 0));
2545 1.1 augustss
2546 1.264.4.55 skrll stat->link.std = NULL;
2547 1.264.4.55 skrll stat->td.td_link = htole32(UHCI_PTR_T);
2548 1.264.4.55 skrll stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls |
2549 1.264.4.55 skrll UHCI_TD_ACTIVE | UHCI_TD_IOC);
2550 1.264.4.55 skrll stat->td.td_token =
2551 1.264.4.55 skrll htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) :
2552 1.264.4.55 skrll UHCI_TD_IN (0, endpt, addr, 1));
2553 1.264.4.55 skrll stat->td.td_buffer = htole32(0);
2554 1.264.4.55 skrll
2555 1.264.4.55 skrll DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0);
2556 1.264.4.55 skrll #ifdef UHCI_DEBUG
2557 1.264.4.55 skrll if (uhcidebug >= 10) {
2558 1.264.4.55 skrll DPRINTFN(10, "before transfer", 0, 0, 0, 0);
2559 1.264.4.55 skrll uhci_dump_tds(setup);
2560 1.264.4.55 skrll }
2561 1.264.4.55 skrll #endif
2562 1.264.4.55 skrll DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0);
2563 1.264.4.55 skrll
2564 1.264.4.55 skrll /* Set up interrupt info. */
2565 1.264.4.55 skrll uxfer->ux_setup = setup;
2566 1.264.4.55 skrll uxfer->ux_data = data;
2567 1.264.4.55 skrll uxfer->ux_stat = stat;
2568 1.264.4.55 skrll
2569 1.264.4.55 skrll return 0;
2570 1.264.4.55 skrll }
2571 1.264.4.55 skrll
2572 1.264.4.55 skrll Static void
2573 1.264.4.55 skrll uhci_device_ctrl_fini(struct usbd_xfer *xfer)
2574 1.264.4.55 skrll {
2575 1.264.4.55 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2576 1.264.4.55 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
2577 1.264.4.55 skrll
2578 1.264.4.55 skrll KASSERT(ux->ux_type == UX_CTRL);
2579 1.264.4.55 skrll
2580 1.264.4.55 skrll uhci_free_stds(sc, ux);
2581 1.264.4.55 skrll if (ux->ux_nstd)
2582 1.264.4.55 skrll kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd);
2583 1.264.4.55 skrll }
2584 1.264.4.55 skrll
2585 1.264.4.55 skrll usbd_status
2586 1.264.4.55 skrll uhci_device_ctrl_transfer(struct usbd_xfer *xfer)
2587 1.264.4.55 skrll {
2588 1.264.4.55 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2589 1.264.4.55 skrll usbd_status err;
2590 1.264.4.55 skrll
2591 1.264.4.55 skrll /* Insert last in queue. */
2592 1.264.4.55 skrll mutex_enter(&sc->sc_lock);
2593 1.264.4.55 skrll err = usb_insert_transfer(xfer);
2594 1.264.4.55 skrll mutex_exit(&sc->sc_lock);
2595 1.264.4.55 skrll if (err)
2596 1.264.4.55 skrll return err;
2597 1.264.4.55 skrll
2598 1.264.4.55 skrll /*
2599 1.264.4.55 skrll * Pipe isn't running (otherwise err would be USBD_INPROG),
2600 1.264.4.55 skrll * so start it first.
2601 1.264.4.55 skrll */
2602 1.264.4.55 skrll return uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2603 1.264.4.55 skrll }
2604 1.264.4.55 skrll
2605 1.264.4.55 skrll usbd_status
2606 1.264.4.55 skrll uhci_device_ctrl_start(struct usbd_xfer *xfer)
2607 1.264.4.55 skrll {
2608 1.264.4.55 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2609 1.264.4.55 skrll struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
2610 1.264.4.55 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
2611 1.264.4.55 skrll usb_device_request_t *req = &xfer->ux_request;
2612 1.264.4.55 skrll struct usbd_device *dev = upipe->pipe.up_dev;
2613 1.264.4.55 skrll int addr = dev->ud_addr;
2614 1.264.4.55 skrll int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
2615 1.264.4.55 skrll uhci_soft_td_t *setup, *stat, *next, *dataend;
2616 1.264.4.55 skrll uhci_soft_qh_t *sqh;
2617 1.264.4.55 skrll int len;
2618 1.264.4.55 skrll uint32_t ls;
2619 1.264.4.55 skrll int isread;
2620 1.264.4.55 skrll
2621 1.264.4.55 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2622 1.264.4.55 skrll
2623 1.264.4.55 skrll if (sc->sc_dying)
2624 1.264.4.55 skrll return USBD_IOERROR;
2625 1.264.4.55 skrll
2626 1.264.4.55 skrll KASSERT(xfer->ux_rqflags & URQ_REQUEST);
2627 1.264.4.55 skrll
2628 1.264.4.55 skrll DPRINTFN(3, "type=0x%02x, request=0x%02x, "
2629 1.264.4.55 skrll "wValue=0x%04x, wIndex=0x%04x",
2630 1.264.4.55 skrll req->bmRequestType, req->bRequest, UGETW(req->wValue),
2631 1.264.4.55 skrll UGETW(req->wIndex));
2632 1.264.4.55 skrll DPRINTFN(3, "len=%d, addr=%d, endpt=%d",
2633 1.264.4.55 skrll UGETW(req->wLength), dev->ud_addr, endpt, 0);
2634 1.264.4.55 skrll
2635 1.264.4.55 skrll ls = dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0;
2636 1.264.4.55 skrll isread = req->bmRequestType & UT_READ;
2637 1.264.4.55 skrll len = UGETW(req->wLength);
2638 1.264.4.55 skrll
2639 1.264.4.55 skrll setup = upipe->ctrl.setup;
2640 1.264.4.55 skrll stat = upipe->ctrl.stat;
2641 1.264.4.55 skrll sqh = upipe->ctrl.sqh;
2642 1.264.4.55 skrll
2643 1.264.4.55 skrll memcpy(KERNADDR(&upipe->ctrl.reqdma, 0), req, sizeof(*req));
2644 1.264.4.55 skrll usb_syncmem(&upipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE);
2645 1.264.4.55 skrll
2646 1.264.4.55 skrll mutex_enter(&sc->sc_lock);
2647 1.264.4.55 skrll
2648 1.264.4.55 skrll /* Set up data transaction */
2649 1.264.4.55 skrll if (len != 0) {
2650 1.264.4.55 skrll upipe->nexttoggle = 1;
2651 1.264.4.55 skrll next = uxfer->ux_data;
2652 1.264.4.55 skrll uhci_reset_std_chain(sc, xfer, len, isread,
2653 1.264.4.55 skrll &upipe->nexttoggle, next, &dataend);
2654 1.264.4.55 skrll dataend->link.std = stat;
2655 1.264.4.55 skrll dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD);
2656 1.264.4.55 skrll usb_syncmem(&dataend->dma,
2657 1.264.4.55 skrll dataend->offs + offsetof(uhci_td_t, td_link),
2658 1.264.4.55 skrll sizeof(dataend->td.td_link),
2659 1.264.4.55 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2660 1.264.4.55 skrll } else {
2661 1.264.4.55 skrll next = stat;
2662 1.264.4.55 skrll }
2663 1.264.4.55 skrll
2664 1.264.4.55 skrll setup->link.std = next;
2665 1.264.4.55 skrll setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD);
2666 1.264.4.55 skrll setup->td.td_status |= htole32(
2667 1.264.4.55 skrll UHCI_TD_SET_ERRCNT(3) |
2668 1.264.4.55 skrll ls |
2669 1.264.4.55 skrll UHCI_TD_ACTIVE
2670 1.264.4.55 skrll );
2671 1.264.4.55 skrll setup->td.td_token &= ~htole32(UHCI_TD_MAXLEN_MASK);
2672 1.264.4.55 skrll setup->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(sizeof(*req)));
2673 1.264.4.55 skrll usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td),
2674 1.264.4.55 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2675 1.264.4.55 skrll
2676 1.264.4.55 skrll stat->link.std = NULL;
2677 1.264.4.55 skrll stat->td.td_link = htole32(UHCI_PTR_T);
2678 1.264.4.55 skrll stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls |
2679 1.264.4.55 skrll UHCI_TD_ACTIVE | UHCI_TD_IOC);
2680 1.264.4.55 skrll stat->td.td_token =
2681 1.264.4.55 skrll htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) :
2682 1.264.4.55 skrll UHCI_TD_IN (0, endpt, addr, 1));
2683 1.264.4.55 skrll stat->td.td_buffer = htole32(0);
2684 1.264.4.55 skrll usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td),
2685 1.264.4.55 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2686 1.264.4.55 skrll
2687 1.264.4.55 skrll #ifdef UHCI_DEBUG
2688 1.264.4.55 skrll if (uhcidebug >= 10) {
2689 1.264.4.55 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
2690 1.264.4.55 skrll DPRINTF("before transfer", 0, 0, 0, 0);
2691 1.264.4.55 skrll uhci_dump_tds(setup);
2692 1.264.4.55 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
2693 1.264.4.55 skrll }
2694 1.264.4.55 skrll #endif
2695 1.264.4.55 skrll
2696 1.264.4.55 skrll /* Set up interrupt info. */
2697 1.264.4.55 skrll uxfer->ux_setup = setup;
2698 1.264.4.55 skrll uxfer->ux_stat = stat;
2699 1.264.4.55 skrll KASSERT(uxfer->ux_isdone);
2700 1.264.4.55 skrll #ifdef DIAGNOSTIC
2701 1.264.4.55 skrll uxfer->ux_isdone = false;
2702 1.264.4.55 skrll #endif
2703 1.264.4.55 skrll
2704 1.264.4.55 skrll sqh->elink = setup;
2705 1.264.4.55 skrll sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD);
2706 1.264.4.55 skrll /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */
2707 1.264.4.55 skrll
2708 1.264.4.55 skrll if (dev->ud_speed == USB_SPEED_LOW)
2709 1.264.4.55 skrll uhci_add_ls_ctrl(sc, sqh);
2710 1.264.4.55 skrll else
2711 1.264.4.55 skrll uhci_add_hs_ctrl(sc, sqh);
2712 1.264.4.56 skrll uhci_add_intr_list(sc, uxfer);
2713 1.264.4.55 skrll #ifdef UHCI_DEBUG
2714 1.264.4.55 skrll if (uhcidebug >= 12) {
2715 1.264.4.55 skrll uhci_soft_td_t *std;
2716 1.264.4.55 skrll uhci_soft_qh_t *xqh;
2717 1.264.4.55 skrll uhci_soft_qh_t *sxqh;
2718 1.264.4.55 skrll int maxqh = 0;
2719 1.264.4.55 skrll uhci_physaddr_t link;
2720 1.264.4.55 skrll DPRINTFN(12, "--- dump start ---", 0, 0, 0, 0);
2721 1.264.4.55 skrll DPRINTFN(12, "follow from [0]", 0, 0, 0, 0);
2722 1.264.4.55 skrll for (std = sc->sc_vframes[0].htd, link = 0;
2723 1.264.4.55 skrll (link & UHCI_PTR_QH) == 0;
2724 1.264.4.55 skrll std = std->link.std) {
2725 1.264.4.55 skrll link = le32toh(std->td.td_link);
2726 1.264.4.55 skrll uhci_dump_td(std);
2727 1.264.4.55 skrll }
2728 1.264.4.55 skrll sxqh = (uhci_soft_qh_t *)std;
2729 1.264.4.55 skrll uhci_dump_qh(sxqh);
2730 1.264.4.55 skrll for (xqh = sxqh;
2731 1.264.4.55 skrll xqh != NULL;
2732 1.264.4.55 skrll xqh = (maxqh++ == 5 || xqh->hlink == sxqh ||
2733 1.264.4.55 skrll xqh->hlink == xqh ? NULL : xqh->hlink)) {
2734 1.264.4.55 skrll uhci_dump_qh(xqh);
2735 1.264.4.55 skrll }
2736 1.264.4.55 skrll DPRINTFN(12, "Enqueued QH:", 0, 0, 0, 0);
2737 1.264.4.55 skrll uhci_dump_qh(sqh);
2738 1.264.4.55 skrll uhci_dump_tds(sqh->elink);
2739 1.264.4.55 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
2740 1.264.4.55 skrll }
2741 1.264.4.55 skrll #endif
2742 1.264.4.55 skrll if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
2743 1.264.4.55 skrll callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
2744 1.264.4.55 skrll uhci_timeout, xfer);
2745 1.264.4.55 skrll }
2746 1.264.4.55 skrll xfer->ux_status = USBD_IN_PROGRESS;
2747 1.264.4.55 skrll mutex_exit(&sc->sc_lock);
2748 1.264.4.55 skrll
2749 1.264.4.55 skrll if (sc->sc_bus.ub_usepolling)
2750 1.63 augustss uhci_waitintr(sc, xfer);
2751 1.264.4.55 skrll
2752 1.264.4.13 skrll return USBD_IN_PROGRESS;
2753 1.1 augustss }
2754 1.1 augustss
2755 1.264.4.55 skrll int
2756 1.264.4.55 skrll uhci_device_intr_init(struct usbd_xfer *xfer)
2757 1.264.4.55 skrll {
2758 1.264.4.55 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2759 1.264.4.55 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
2760 1.264.4.55 skrll usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc;
2761 1.264.4.55 skrll int endpt = ed->bEndpointAddress;
2762 1.264.4.55 skrll int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2763 1.264.4.55 skrll int len = xfer->ux_bufsize;
2764 1.264.4.55 skrll int err;
2765 1.264.4.55 skrll
2766 1.264.4.55 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2767 1.264.4.55 skrll
2768 1.264.4.55 skrll DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length,
2769 1.264.4.55 skrll xfer->ux_flags, 0);
2770 1.264.4.55 skrll
2771 1.264.4.55 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
2772 1.264.4.55 skrll KASSERT(len != 0);
2773 1.264.4.55 skrll
2774 1.264.4.55 skrll ux->ux_type = UX_INTR;
2775 1.264.4.55 skrll ux->ux_nstd = 0;
2776 1.264.4.55 skrll err = uhci_alloc_std_chain(sc, xfer, len, isread,
2777 1.264.4.55 skrll &ux->ux_stdstart, &ux->ux_stdend);
2778 1.264.4.55 skrll
2779 1.264.4.55 skrll return err;
2780 1.264.4.55 skrll }
2781 1.264.4.55 skrll
2782 1.264.4.55 skrll Static void
2783 1.264.4.55 skrll uhci_device_intr_fini(struct usbd_xfer *xfer)
2784 1.264.4.55 skrll {
2785 1.264.4.55 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2786 1.264.4.55 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
2787 1.264.4.55 skrll
2788 1.264.4.55 skrll KASSERT(ux->ux_type == UX_INTR);
2789 1.264.4.55 skrll
2790 1.264.4.55 skrll uhci_free_stds(sc, ux);
2791 1.264.4.55 skrll if (ux->ux_nstd)
2792 1.264.4.55 skrll kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd);
2793 1.264.4.55 skrll }
2794 1.264.4.55 skrll
2795 1.1 augustss usbd_status
2796 1.264.4.25 skrll uhci_device_intr_transfer(struct usbd_xfer *xfer)
2797 1.1 augustss {
2798 1.264.4.37 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2799 1.63 augustss usbd_status err;
2800 1.16 augustss
2801 1.52 augustss /* Insert last in queue. */
2802 1.248 mrg mutex_enter(&sc->sc_lock);
2803 1.63 augustss err = usb_insert_transfer(xfer);
2804 1.248 mrg mutex_exit(&sc->sc_lock);
2805 1.63 augustss if (err)
2806 1.264.4.13 skrll return err;
2807 1.52 augustss
2808 1.152 augustss /*
2809 1.92 augustss * Pipe isn't running (otherwise err would be USBD_INPROG),
2810 1.92 augustss * so start it first.
2811 1.67 augustss */
2812 1.264.4.13 skrll return uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2813 1.16 augustss }
2814 1.16 augustss
2815 1.16 augustss usbd_status
2816 1.264.4.25 skrll uhci_device_intr_start(struct usbd_xfer *xfer)
2817 1.16 augustss {
2818 1.264.4.39 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
2819 1.264.4.50 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
2820 1.264.4.37 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2821 1.55 augustss uhci_soft_td_t *data, *dataend;
2822 1.1 augustss uhci_soft_qh_t *sqh;
2823 1.187 skrll int isread, endpt;
2824 1.248 mrg int i;
2825 1.1 augustss
2826 1.82 augustss if (sc->sc_dying)
2827 1.264.4.13 skrll return USBD_IOERROR;
2828 1.82 augustss
2829 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2830 1.264.4.21 skrll
2831 1.264.4.55 skrll DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length,
2832 1.264.4.55 skrll xfer->ux_flags, 0);
2833 1.1 augustss
2834 1.264.4.31 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
2835 1.264.4.55 skrll KASSERT(xfer->ux_length <= xfer->ux_bufsize);
2836 1.248 mrg
2837 1.264.4.7 skrll endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
2838 1.187 skrll isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2839 1.187 skrll
2840 1.264.4.55 skrll data = ux->ux_stdstart;
2841 1.187 skrll
2842 1.264.4.55 skrll KASSERT(ux->ux_isdone);
2843 1.264.4.55 skrll #ifdef DIAGNOSTIC
2844 1.264.4.55 skrll ux->ux_isdone = false;
2845 1.264.4.55 skrll #endif
2846 1.264.4.55 skrll
2847 1.264.4.55 skrll /* Take lock to protect nexttoggle */
2848 1.264.4.55 skrll mutex_enter(&sc->sc_lock);
2849 1.264.4.55 skrll uhci_reset_std_chain(sc, xfer, xfer->ux_length, isread,
2850 1.264.4.55 skrll &upipe->nexttoggle, data, &dataend);
2851 1.248 mrg
2852 1.88 tsutsui dataend->td.td_status |= htole32(UHCI_TD_IOC);
2853 1.223 bouyer usb_syncmem(&dataend->dma,
2854 1.223 bouyer dataend->offs + offsetof(uhci_td_t, td_status),
2855 1.223 bouyer sizeof(dataend->td.td_status),
2856 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2857 1.264.4.55 skrll ux->ux_stdend = dataend;
2858 1.1 augustss
2859 1.59 augustss #ifdef UHCI_DEBUG
2860 1.264.4.43 skrll if (uhcidebug >= 10) {
2861 1.264.4.47 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
2862 1.55 augustss uhci_dump_tds(data);
2863 1.264.4.33 skrll uhci_dump_qh(upipe->intr.qhs[0]);
2864 1.264.4.47 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
2865 1.1 augustss }
2866 1.1 augustss #endif
2867 1.1 augustss
2868 1.264.4.33 skrll DPRINTFN(10, "qhs[0]=%p", upipe->intr.qhs[0], 0, 0, 0);
2869 1.264.4.33 skrll for (i = 0; i < upipe->intr.npoll; i++) {
2870 1.264.4.33 skrll sqh = upipe->intr.qhs[i];
2871 1.55 augustss sqh->elink = data;
2872 1.121 augustss sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD);
2873 1.223 bouyer usb_syncmem(&sqh->dma,
2874 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
2875 1.223 bouyer sizeof(sqh->qh.qh_elink),
2876 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2877 1.1 augustss }
2878 1.264.4.56 skrll uhci_add_intr_list(sc, ux);
2879 1.264.4.7 skrll xfer->ux_status = USBD_IN_PROGRESS;
2880 1.248 mrg mutex_exit(&sc->sc_lock);
2881 1.1 augustss
2882 1.59 augustss #ifdef UHCI_DEBUG
2883 1.264.4.43 skrll if (uhcidebug >= 10) {
2884 1.264.4.47 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
2885 1.55 augustss uhci_dump_tds(data);
2886 1.264.4.33 skrll uhci_dump_qh(upipe->intr.qhs[0]);
2887 1.264.4.47 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
2888 1.1 augustss }
2889 1.1 augustss #endif
2890 1.1 augustss
2891 1.264.4.13 skrll return USBD_IN_PROGRESS;
2892 1.1 augustss }
2893 1.1 augustss
2894 1.1 augustss /* Abort a device control request. */
2895 1.1 augustss void
2896 1.264.4.25 skrll uhci_device_ctrl_abort(struct usbd_xfer *xfer)
2897 1.1 augustss {
2898 1.264.4.37 skrll uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer);
2899 1.248 mrg
2900 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2901 1.248 mrg
2902 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2903 1.66 augustss uhci_abort_xfer(xfer, USBD_CANCELLED);
2904 1.1 augustss }
2905 1.1 augustss
2906 1.1 augustss /* Close a device control pipe. */
2907 1.1 augustss void
2908 1.264.4.25 skrll uhci_device_ctrl_close(struct usbd_pipe *pipe)
2909 1.1 augustss {
2910 1.264.4.55 skrll uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
2911 1.264.4.55 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
2912 1.264.4.55 skrll
2913 1.264.4.55 skrll uhci_free_sqh(sc, upipe->ctrl.sqh);
2914 1.264.4.55 skrll uhci_free_std_locked(sc, upipe->ctrl.setup);
2915 1.264.4.55 skrll uhci_free_std_locked(sc, upipe->ctrl.stat);
2916 1.264.4.55 skrll
2917 1.1 augustss }
2918 1.1 augustss
2919 1.1 augustss /* Abort a device interrupt request. */
2920 1.1 augustss void
2921 1.264.4.25 skrll uhci_device_intr_abort(struct usbd_xfer *xfer)
2922 1.1 augustss {
2923 1.264.4.37 skrll uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer);
2924 1.248 mrg
2925 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2926 1.264.4.7 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
2927 1.248 mrg
2928 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2929 1.264.4.27 skrll DPRINTF("xfer=%p", xfer, 0, 0, 0);
2930 1.264 skrll
2931 1.66 augustss uhci_abort_xfer(xfer, USBD_CANCELLED);
2932 1.1 augustss }
2933 1.1 augustss
2934 1.1 augustss /* Close a device interrupt pipe. */
2935 1.1 augustss void
2936 1.264.4.25 skrll uhci_device_intr_close(struct usbd_pipe *pipe)
2937 1.1 augustss {
2938 1.264.4.50 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
2939 1.264.4.37 skrll uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
2940 1.92 augustss int i, npoll;
2941 1.248 mrg
2942 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2943 1.1 augustss
2944 1.1 augustss /* Unlink descriptors from controller data structures. */
2945 1.264.4.33 skrll npoll = upipe->intr.npoll;
2946 1.1 augustss for (i = 0; i < npoll; i++)
2947 1.264.4.33 skrll uhci_remove_intr(sc, upipe->intr.qhs[i]);
2948 1.1 augustss
2949 1.152 augustss /*
2950 1.1 augustss * We now have to wait for any activity on the physical
2951 1.1 augustss * descriptors to stop.
2952 1.1 augustss */
2953 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock);
2954 1.1 augustss
2955 1.264.4.54 skrll for (i = 0; i < npoll; i++)
2956 1.264.4.33 skrll uhci_free_sqh(sc, upipe->intr.qhs[i]);
2957 1.264.4.33 skrll kmem_free(upipe->intr.qhs, npoll * sizeof(uhci_soft_qh_t *));
2958 1.1 augustss }
2959 1.1 augustss
2960 1.264.4.55 skrll int
2961 1.264.4.55 skrll uhci_device_isoc_init(struct usbd_xfer *xfer)
2962 1.1 augustss {
2963 1.264.4.55 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
2964 1.1 augustss
2965 1.264.4.55 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
2966 1.264.4.55 skrll KASSERT(xfer->ux_nframes != 0);
2967 1.264.4.55 skrll KASSERT(ux->ux_isdone);
2968 1.1 augustss
2969 1.264.4.55 skrll ux->ux_type = UX_ISOC;
2970 1.264.4.55 skrll return 0;
2971 1.264.4.55 skrll }
2972 1.264.4.47 skrll
2973 1.264.4.55 skrll Static void
2974 1.264.4.55 skrll uhci_device_isoc_fini(struct usbd_xfer *xfer)
2975 1.264.4.55 skrll {
2976 1.264.4.55 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
2977 1.1 augustss
2978 1.264.4.55 skrll KASSERT(ux->ux_type == UX_ISOC);
2979 1.1 augustss }
2980 1.1 augustss
2981 1.16 augustss usbd_status
2982 1.264.4.25 skrll uhci_device_isoc_transfer(struct usbd_xfer *xfer)
2983 1.16 augustss {
2984 1.264.4.37 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2985 1.63 augustss usbd_status err;
2986 1.48 augustss
2987 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2988 1.264.4.21 skrll DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0);
2989 1.48 augustss
2990 1.48 augustss /* Put it on our queue, */
2991 1.248 mrg mutex_enter(&sc->sc_lock);
2992 1.63 augustss err = usb_insert_transfer(xfer);
2993 1.248 mrg mutex_exit(&sc->sc_lock);
2994 1.48 augustss
2995 1.48 augustss /* bail out on error, */
2996 1.63 augustss if (err && err != USBD_IN_PROGRESS)
2997 1.264.4.13 skrll return err;
2998 1.48 augustss
2999 1.48 augustss /* XXX should check inuse here */
3000 1.48 augustss
3001 1.48 augustss /* insert into schedule, */
3002 1.63 augustss uhci_device_isoc_enter(xfer);
3003 1.48 augustss
3004 1.102 augustss /* and start if the pipe wasn't running */
3005 1.67 augustss if (!err)
3006 1.264.4.7 skrll uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
3007 1.48 augustss
3008 1.264.4.13 skrll return err;
3009 1.48 augustss }
3010 1.48 augustss
3011 1.48 augustss void
3012 1.264.4.25 skrll uhci_device_isoc_enter(struct usbd_xfer *xfer)
3013 1.48 augustss {
3014 1.264.4.37 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
3015 1.264.4.55 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
3016 1.264.4.33 skrll struct isoc *isoc = &upipe->isoc;
3017 1.152 augustss uhci_soft_td_t *std;
3018 1.264.4.1 skrll uint32_t buf, len, status, offs;
3019 1.248 mrg int i, next, nframes;
3020 1.264.4.7 skrll int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN;
3021 1.48 augustss
3022 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3023 1.264.4.21 skrll DPRINTFN(5, "used=%d next=%d xfer=%p nframes=%d",
3024 1.264.4.33 skrll isoc->inuse, isoc->next, xfer, xfer->ux_nframes);
3025 1.48 augustss
3026 1.82 augustss if (sc->sc_dying)
3027 1.82 augustss return;
3028 1.82 augustss
3029 1.264.4.7 skrll if (xfer->ux_status == USBD_IN_PROGRESS) {
3030 1.48 augustss /* This request has already been entered into the frame list */
3031 1.96 augustss printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer);
3032 1.68 augustss /* XXX */
3033 1.48 augustss }
3034 1.48 augustss
3035 1.48 augustss #ifdef DIAGNOSTIC
3036 1.264.4.33 skrll if (isoc->inuse >= UHCI_VFRAMELIST_COUNT)
3037 1.48 augustss printf("uhci_device_isoc_enter: overflow!\n");
3038 1.19 augustss #endif
3039 1.16 augustss
3040 1.264.4.33 skrll next = isoc->next;
3041 1.48 augustss if (next == -1) {
3042 1.48 augustss /* Not in use yet, schedule it a few frames ahead. */
3043 1.48 augustss next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT;
3044 1.264.4.21 skrll DPRINTFN(2, "start next=%d", next, 0, 0, 0);
3045 1.48 augustss }
3046 1.48 augustss
3047 1.264.4.7 skrll xfer->ux_status = USBD_IN_PROGRESS;
3048 1.264.4.41 skrll UHCI_XFER2UXFER(xfer)->ux_curframe = next;
3049 1.48 augustss
3050 1.264.4.7 skrll buf = DMAADDR(&xfer->ux_dmabuf, 0);
3051 1.223 bouyer offs = 0;
3052 1.88 tsutsui status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) |
3053 1.88 tsutsui UHCI_TD_ACTIVE |
3054 1.88 tsutsui UHCI_TD_IOS);
3055 1.264.4.7 skrll nframes = xfer->ux_nframes;
3056 1.248 mrg mutex_enter(&sc->sc_lock);
3057 1.48 augustss for (i = 0; i < nframes; i++) {
3058 1.264.4.33 skrll std = isoc->stds[next];
3059 1.48 augustss if (++next >= UHCI_VFRAMELIST_COUNT)
3060 1.48 augustss next = 0;
3061 1.264.4.7 skrll len = xfer->ux_frlengths[i];
3062 1.88 tsutsui std->td.td_buffer = htole32(buf);
3063 1.264.4.7 skrll usb_syncmem(&xfer->ux_dmabuf, offs, len,
3064 1.223 bouyer rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
3065 1.48 augustss if (i == nframes - 1)
3066 1.88 tsutsui status |= UHCI_TD_IOC;
3067 1.88 tsutsui std->td.td_status = htole32(status);
3068 1.88 tsutsui std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK);
3069 1.88 tsutsui std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len));
3070 1.223 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
3071 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3072 1.59 augustss #ifdef UHCI_DEBUG
3073 1.264.4.43 skrll if (uhcidebug >= 5) {
3074 1.264.4.47 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
3075 1.264.4.27 skrll DPRINTF("TD %d", i, 0, 0, 0);
3076 1.48 augustss uhci_dump_td(std);
3077 1.264.4.47 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
3078 1.48 augustss }
3079 1.48 augustss #endif
3080 1.48 augustss buf += len;
3081 1.223 bouyer offs += len;
3082 1.48 augustss }
3083 1.264.4.33 skrll isoc->next = next;
3084 1.264.4.33 skrll isoc->inuse += xfer->ux_nframes;
3085 1.16 augustss
3086 1.248 mrg mutex_exit(&sc->sc_lock);
3087 1.16 augustss }
3088 1.16 augustss
3089 1.16 augustss usbd_status
3090 1.264.4.25 skrll uhci_device_isoc_start(struct usbd_xfer *xfer)
3091 1.16 augustss {
3092 1.264.4.50 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
3093 1.264.4.37 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
3094 1.264.4.39 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
3095 1.48 augustss uhci_soft_td_t *end;
3096 1.248 mrg int i;
3097 1.48 augustss
3098 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3099 1.264.4.21 skrll DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0);
3100 1.96 augustss
3101 1.248 mrg mutex_enter(&sc->sc_lock);
3102 1.248 mrg
3103 1.248 mrg if (sc->sc_dying) {
3104 1.248 mrg mutex_exit(&sc->sc_lock);
3105 1.264.4.13 skrll return USBD_IOERROR;
3106 1.248 mrg }
3107 1.82 augustss
3108 1.48 augustss #ifdef DIAGNOSTIC
3109 1.264.4.7 skrll if (xfer->ux_status != USBD_IN_PROGRESS)
3110 1.63 augustss printf("uhci_device_isoc_start: not in progress %p\n", xfer);
3111 1.48 augustss #endif
3112 1.48 augustss
3113 1.48 augustss /* Find the last TD */
3114 1.264.4.41 skrll i = UHCI_XFER2UXFER(xfer)->ux_curframe + xfer->ux_nframes;
3115 1.48 augustss if (i >= UHCI_VFRAMELIST_COUNT)
3116 1.48 augustss i -= UHCI_VFRAMELIST_COUNT;
3117 1.264.4.33 skrll end = upipe->isoc.stds[i];
3118 1.48 augustss
3119 1.264.4.31 skrll KASSERT(end != NULL);
3120 1.96 augustss
3121 1.48 augustss /* Set up interrupt info. */
3122 1.264.4.41 skrll ux->ux_stdstart = end;
3123 1.264.4.41 skrll ux->ux_stdend = end;
3124 1.264.4.31 skrll
3125 1.264.4.41 skrll KASSERT(ux->ux_isdone);
3126 1.48 augustss #ifdef DIAGNOSTIC
3127 1.264.4.41 skrll ux->ux_isdone = false;
3128 1.48 augustss #endif
3129 1.264.4.56 skrll uhci_add_intr_list(sc, ux);
3130 1.152 augustss
3131 1.248 mrg mutex_exit(&sc->sc_lock);
3132 1.48 augustss
3133 1.264.4.13 skrll return USBD_IN_PROGRESS;
3134 1.16 augustss }
3135 1.16 augustss
3136 1.16 augustss void
3137 1.264.4.25 skrll uhci_device_isoc_abort(struct usbd_xfer *xfer)
3138 1.16 augustss {
3139 1.264.4.37 skrll uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer);
3140 1.264.4.50 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
3141 1.264.4.33 skrll uhci_soft_td_t **stds = upipe->isoc.stds;
3142 1.48 augustss uhci_soft_td_t *std;
3143 1.248 mrg int i, n, nframes, maxlen, len;
3144 1.92 augustss
3145 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
3146 1.92 augustss
3147 1.92 augustss /* Transfer is already done. */
3148 1.264.4.7 skrll if (xfer->ux_status != USBD_NOT_STARTED &&
3149 1.264.4.7 skrll xfer->ux_status != USBD_IN_PROGRESS) {
3150 1.92 augustss return;
3151 1.92 augustss }
3152 1.48 augustss
3153 1.92 augustss /* Give xfer the requested abort code. */
3154 1.264.4.7 skrll xfer->ux_status = USBD_CANCELLED;
3155 1.48 augustss
3156 1.48 augustss /* make hardware ignore it, */
3157 1.264.4.7 skrll nframes = xfer->ux_nframes;
3158 1.264.4.41 skrll n = UHCI_XFER2UXFER(xfer)->ux_curframe;
3159 1.92 augustss maxlen = 0;
3160 1.48 augustss for (i = 0; i < nframes; i++) {
3161 1.48 augustss std = stds[n];
3162 1.223 bouyer usb_syncmem(&std->dma,
3163 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
3164 1.223 bouyer sizeof(std->td.td_status),
3165 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3166 1.88 tsutsui std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC));
3167 1.223 bouyer usb_syncmem(&std->dma,
3168 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
3169 1.223 bouyer sizeof(std->td.td_status),
3170 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3171 1.223 bouyer usb_syncmem(&std->dma,
3172 1.223 bouyer std->offs + offsetof(uhci_td_t, td_token),
3173 1.223 bouyer sizeof(std->td.td_token),
3174 1.223 bouyer BUS_DMASYNC_POSTWRITE);
3175 1.130 tsutsui len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token));
3176 1.92 augustss if (len > maxlen)
3177 1.92 augustss maxlen = len;
3178 1.48 augustss if (++n >= UHCI_VFRAMELIST_COUNT)
3179 1.48 augustss n = 0;
3180 1.48 augustss }
3181 1.48 augustss
3182 1.92 augustss /* and wait until we are sure the hardware has finished. */
3183 1.92 augustss delay(maxlen);
3184 1.92 augustss
3185 1.96 augustss #ifdef DIAGNOSTIC
3186 1.264.4.41 skrll UHCI_XFER2UXFER(xfer)->ux_isdone = true;
3187 1.96 augustss #endif
3188 1.92 augustss /* Run callback and remove from interrupt list. */
3189 1.92 augustss usb_transfer_complete(xfer);
3190 1.48 augustss
3191 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
3192 1.16 augustss }
3193 1.16 augustss
3194 1.16 augustss void
3195 1.264.4.25 skrll uhci_device_isoc_close(struct usbd_pipe *pipe)
3196 1.16 augustss {
3197 1.264.4.50 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
3198 1.264.4.37 skrll uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
3199 1.48 augustss uhci_soft_td_t *std, *vstd;
3200 1.264.4.33 skrll struct isoc *isoc;
3201 1.248 mrg int i;
3202 1.248 mrg
3203 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
3204 1.16 augustss
3205 1.16 augustss /*
3206 1.16 augustss * Make sure all TDs are marked as inactive.
3207 1.16 augustss * Wait for completion.
3208 1.16 augustss * Unschedule.
3209 1.16 augustss * Deallocate.
3210 1.16 augustss */
3211 1.264.4.33 skrll isoc = &upipe->isoc;
3212 1.16 augustss
3213 1.223 bouyer for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
3214 1.264.4.33 skrll std = isoc->stds[i];
3215 1.223 bouyer usb_syncmem(&std->dma,
3216 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
3217 1.223 bouyer sizeof(std->td.td_status),
3218 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3219 1.223 bouyer std->td.td_status &= htole32(~UHCI_TD_ACTIVE);
3220 1.223 bouyer usb_syncmem(&std->dma,
3221 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
3222 1.223 bouyer sizeof(std->td.td_status),
3223 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3224 1.223 bouyer }
3225 1.248 mrg /* wait for completion */
3226 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock);
3227 1.16 augustss
3228 1.16 augustss for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
3229 1.264.4.33 skrll std = isoc->stds[i];
3230 1.48 augustss for (vstd = sc->sc_vframes[i].htd;
3231 1.67 augustss vstd != NULL && vstd->link.std != std;
3232 1.42 augustss vstd = vstd->link.std)
3233 1.16 augustss ;
3234 1.67 augustss if (vstd == NULL) {
3235 1.16 augustss /*panic*/
3236 1.16 augustss printf("uhci_device_isoc_close: %p not found\n", std);
3237 1.248 mrg mutex_exit(&sc->sc_lock);
3238 1.16 augustss return;
3239 1.16 augustss }
3240 1.42 augustss vstd->link = std->link;
3241 1.223 bouyer usb_syncmem(&std->dma,
3242 1.223 bouyer std->offs + offsetof(uhci_td_t, td_link),
3243 1.223 bouyer sizeof(std->td.td_link),
3244 1.223 bouyer BUS_DMASYNC_POSTWRITE);
3245 1.42 augustss vstd->td.td_link = std->td.td_link;
3246 1.223 bouyer usb_syncmem(&vstd->dma,
3247 1.223 bouyer vstd->offs + offsetof(uhci_td_t, td_link),
3248 1.223 bouyer sizeof(vstd->td.td_link),
3249 1.223 bouyer BUS_DMASYNC_PREWRITE);
3250 1.264.4.55 skrll uhci_free_std_locked(sc, std);
3251 1.16 augustss }
3252 1.16 augustss
3253 1.264.4.35 skrll kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *));
3254 1.16 augustss }
3255 1.16 augustss
3256 1.16 augustss usbd_status
3257 1.264.4.25 skrll uhci_setup_isoc(struct usbd_pipe *pipe)
3258 1.16 augustss {
3259 1.264.4.50 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
3260 1.264.4.37 skrll uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
3261 1.264.4.7 skrll int addr = upipe->pipe.up_dev->ud_addr;
3262 1.264.4.7 skrll int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
3263 1.45 augustss int rd = UE_GET_DIR(endpt) == UE_DIR_IN;
3264 1.48 augustss uhci_soft_td_t *std, *vstd;
3265 1.264.4.1 skrll uint32_t token;
3266 1.264.4.33 skrll struct isoc *isoc;
3267 1.248 mrg int i;
3268 1.16 augustss
3269 1.264.4.33 skrll isoc = &upipe->isoc;
3270 1.264.4.55 skrll
3271 1.264.4.55 skrll isoc->stds = kmem_alloc(
3272 1.264.4.55 skrll UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *), KM_SLEEP);
3273 1.264.4.33 skrll if (isoc->stds == NULL)
3274 1.248 mrg return USBD_NOMEM;
3275 1.16 augustss
3276 1.88 tsutsui token = rd ? UHCI_TD_IN (0, endpt, addr, 0) :
3277 1.88 tsutsui UHCI_TD_OUT(0, endpt, addr, 0);
3278 1.16 augustss
3279 1.48 augustss /* Allocate the TDs and mark as inactive; */
3280 1.16 augustss for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
3281 1.48 augustss std = uhci_alloc_std(sc);
3282 1.48 augustss if (std == 0)
3283 1.48 augustss goto bad;
3284 1.88 tsutsui std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */
3285 1.88 tsutsui std->td.td_token = htole32(token);
3286 1.223 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
3287 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3288 1.264.4.33 skrll isoc->stds[i] = std;
3289 1.16 augustss }
3290 1.16 augustss
3291 1.264.4.55 skrll mutex_enter(&sc->sc_lock);
3292 1.264.4.55 skrll
3293 1.48 augustss /* Insert TDs into schedule. */
3294 1.16 augustss for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
3295 1.264.4.33 skrll std = isoc->stds[i];
3296 1.48 augustss vstd = sc->sc_vframes[i].htd;
3297 1.223 bouyer usb_syncmem(&vstd->dma,
3298 1.223 bouyer vstd->offs + offsetof(uhci_td_t, td_link),
3299 1.223 bouyer sizeof(vstd->td.td_link),
3300 1.223 bouyer BUS_DMASYNC_POSTWRITE);
3301 1.42 augustss std->link = vstd->link;
3302 1.42 augustss std->td.td_link = vstd->td.td_link;
3303 1.223 bouyer usb_syncmem(&std->dma,
3304 1.223 bouyer std->offs + offsetof(uhci_td_t, td_link),
3305 1.223 bouyer sizeof(std->td.td_link),
3306 1.223 bouyer BUS_DMASYNC_PREWRITE);
3307 1.42 augustss vstd->link.std = std;
3308 1.121 augustss vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD);
3309 1.223 bouyer usb_syncmem(&vstd->dma,
3310 1.223 bouyer vstd->offs + offsetof(uhci_td_t, td_link),
3311 1.223 bouyer sizeof(vstd->td.td_link),
3312 1.223 bouyer BUS_DMASYNC_PREWRITE);
3313 1.16 augustss }
3314 1.248 mrg mutex_exit(&sc->sc_lock);
3315 1.16 augustss
3316 1.264.4.33 skrll isoc->next = -1;
3317 1.264.4.33 skrll isoc->inuse = 0;
3318 1.48 augustss
3319 1.264.4.13 skrll return USBD_NORMAL_COMPLETION;
3320 1.16 augustss
3321 1.48 augustss bad:
3322 1.16 augustss while (--i >= 0)
3323 1.264.4.33 skrll uhci_free_std(sc, isoc->stds[i]);
3324 1.264.4.35 skrll kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *));
3325 1.264.4.13 skrll return USBD_NOMEM;
3326 1.16 augustss }
3327 1.16 augustss
3328 1.16 augustss void
3329 1.264.4.25 skrll uhci_device_isoc_done(struct usbd_xfer *xfer)
3330 1.16 augustss {
3331 1.264.4.50 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
3332 1.264.4.39 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
3333 1.264.4.39 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
3334 1.223 bouyer int i, offs;
3335 1.264.4.7 skrll int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN;
3336 1.223 bouyer
3337 1.48 augustss
3338 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3339 1.264.4.21 skrll DPRINTFN(4, "length=%d, ux_state=0x%08x",
3340 1.264.4.21 skrll xfer->ux_actlen, xfer->ux_state, 0, 0);
3341 1.93 augustss
3342 1.264.4.56 skrll if (!uhci_active_intr_list(ux))
3343 1.96 augustss return;
3344 1.96 augustss
3345 1.93 augustss #ifdef DIAGNOSTIC
3346 1.264.4.41 skrll if (ux->ux_stdend == NULL) {
3347 1.264.4.2 skrll printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer);
3348 1.93 augustss #ifdef UHCI_DEBUG
3349 1.264.4.47 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
3350 1.264.4.39 skrll uhci_dump_ii(ux);
3351 1.264.4.47 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
3352 1.93 augustss #endif
3353 1.93 augustss return;
3354 1.93 augustss }
3355 1.93 augustss #endif
3356 1.48 augustss
3357 1.48 augustss /* Turn off the interrupt since it is active even if the TD is not. */
3358 1.264.4.41 skrll usb_syncmem(&ux->ux_stdend->dma,
3359 1.264.4.41 skrll ux->ux_stdend->offs + offsetof(uhci_td_t, td_status),
3360 1.264.4.41 skrll sizeof(ux->ux_stdend->td.td_status),
3361 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3362 1.264.4.41 skrll ux->ux_stdend->td.td_status &= htole32(~UHCI_TD_IOC);
3363 1.264.4.41 skrll usb_syncmem(&ux->ux_stdend->dma,
3364 1.264.4.41 skrll ux->ux_stdend->offs + offsetof(uhci_td_t, td_status),
3365 1.264.4.41 skrll sizeof(ux->ux_stdend->td.td_status),
3366 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3367 1.48 augustss
3368 1.264.4.56 skrll uhci_del_intr_list(sc, ux); /* remove from active list */
3369 1.223 bouyer
3370 1.223 bouyer offs = 0;
3371 1.264.4.7 skrll for (i = 0; i < xfer->ux_nframes; i++) {
3372 1.264.4.7 skrll usb_syncmem(&xfer->ux_dmabuf, offs, xfer->ux_frlengths[i],
3373 1.223 bouyer rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
3374 1.264.4.7 skrll offs += xfer->ux_frlengths[i];
3375 1.223 bouyer }
3376 1.16 augustss }
3377 1.16 augustss
3378 1.1 augustss void
3379 1.264.4.25 skrll uhci_device_intr_done(struct usbd_xfer *xfer)
3380 1.1 augustss {
3381 1.264.4.38 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
3382 1.264.4.39 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
3383 1.264.4.50 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
3384 1.1 augustss uhci_soft_qh_t *sqh;
3385 1.264.4.55 skrll int i, npoll;
3386 1.1 augustss
3387 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3388 1.264.4.21 skrll DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0);
3389 1.1 augustss
3390 1.264.4.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
3391 1.248 mrg
3392 1.264.4.33 skrll npoll = upipe->intr.npoll;
3393 1.264.4.54 skrll for (i = 0; i < npoll; i++) {
3394 1.264.4.33 skrll sqh = upipe->intr.qhs[i];
3395 1.121 augustss sqh->elink = NULL;
3396 1.88 tsutsui sqh->qh.qh_elink = htole32(UHCI_PTR_T);
3397 1.223 bouyer usb_syncmem(&sqh->dma,
3398 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
3399 1.223 bouyer sizeof(sqh->qh.qh_elink),
3400 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3401 1.1 augustss }
3402 1.1 augustss
3403 1.264.4.7 skrll if (xfer->ux_pipe->up_repeat) {
3404 1.55 augustss uhci_soft_td_t *data, *dataend;
3405 1.264.4.55 skrll int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
3406 1.264.4.55 skrll int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3407 1.1 augustss
3408 1.264.4.55 skrll KASSERT(ux->ux_isdone);
3409 1.264.4.55 skrll #ifdef DIAGNOSTIC
3410 1.264.4.55 skrll ux->ux_isdone = false;
3411 1.264.4.55 skrll #endif
3412 1.264.4.21 skrll DPRINTFN(5, "re-queueing", 0, 0, 0, 0);
3413 1.92 augustss
3414 1.264.4.55 skrll data = ux->ux_stdstart;
3415 1.264.4.55 skrll uhci_reset_std_chain(sc, xfer, xfer->ux_length, isread,
3416 1.264.4.55 skrll &upipe->nexttoggle, data, &dataend);
3417 1.88 tsutsui dataend->td.td_status |= htole32(UHCI_TD_IOC);
3418 1.223 bouyer usb_syncmem(&dataend->dma,
3419 1.223 bouyer dataend->offs + offsetof(uhci_td_t, td_status),
3420 1.223 bouyer sizeof(dataend->td.td_status),
3421 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3422 1.1 augustss
3423 1.59 augustss #ifdef UHCI_DEBUG
3424 1.264.4.43 skrll if (uhcidebug >= 10) {
3425 1.264.4.47 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
3426 1.55 augustss uhci_dump_tds(data);
3427 1.264.4.33 skrll uhci_dump_qh(upipe->intr.qhs[0]);
3428 1.264.4.47 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
3429 1.1 augustss }
3430 1.1 augustss #endif
3431 1.1 augustss
3432 1.264.4.41 skrll ux->ux_stdend = dataend;
3433 1.1 augustss for (i = 0; i < npoll; i++) {
3434 1.264.4.33 skrll sqh = upipe->intr.qhs[i];
3435 1.55 augustss sqh->elink = data;
3436 1.121 augustss sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD);
3437 1.223 bouyer usb_syncmem(&sqh->dma,
3438 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
3439 1.223 bouyer sizeof(sqh->qh.qh_elink),
3440 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3441 1.1 augustss }
3442 1.264.4.7 skrll xfer->ux_status = USBD_IN_PROGRESS;
3443 1.264.4.39 skrll /* The ux is already on the examined list, just leave it. */
3444 1.1 augustss } else {
3445 1.264.4.21 skrll DPRINTFN(5, "removing", 0, 0, 0, 0);
3446 1.264.4.56 skrll if (uhci_active_intr_list(ux))
3447 1.264.4.56 skrll uhci_del_intr_list(sc, ux);
3448 1.1 augustss }
3449 1.1 augustss }
3450 1.1 augustss
3451 1.1 augustss /* Deallocate request data structures */
3452 1.1 augustss void
3453 1.264.4.25 skrll uhci_device_ctrl_done(struct usbd_xfer *xfer)
3454 1.1 augustss {
3455 1.264.4.38 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
3456 1.264.4.39 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
3457 1.264.4.50 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
3458 1.264.4.7 skrll int len = UGETW(xfer->ux_request.wLength);
3459 1.264.4.7 skrll int isread = (xfer->ux_request.bmRequestType & UT_READ);
3460 1.1 augustss
3461 1.264.4.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
3462 1.248 mrg
3463 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3464 1.264.4.31 skrll
3465 1.264.4.32 skrll KASSERT(xfer->ux_rqflags & URQ_REQUEST);
3466 1.1 augustss
3467 1.264.4.56 skrll if (!uhci_active_intr_list(ux))
3468 1.169 augustss return;
3469 1.169 augustss
3470 1.264.4.56 skrll uhci_del_intr_list(sc, ux); /* remove from active list */
3471 1.1 augustss
3472 1.264.4.7 skrll if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW)
3473 1.264.4.33 skrll uhci_remove_ls_ctrl(sc, upipe->ctrl.sqh);
3474 1.123 augustss else
3475 1.264.4.33 skrll uhci_remove_hs_ctrl(sc, upipe->ctrl.sqh);
3476 1.1 augustss
3477 1.223 bouyer if (len) {
3478 1.264.4.7 skrll usb_syncmem(&xfer->ux_dmabuf, 0, len,
3479 1.223 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
3480 1.223 bouyer }
3481 1.264.4.33 skrll usb_syncmem(&upipe->ctrl.reqdma, 0,
3482 1.223 bouyer sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE);
3483 1.223 bouyer
3484 1.264.4.27 skrll DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0);
3485 1.1 augustss }
3486 1.1 augustss
3487 1.1 augustss /* Deallocate request data structures */
3488 1.1 augustss void
3489 1.264.4.25 skrll uhci_device_bulk_done(struct usbd_xfer *xfer)
3490 1.1 augustss {
3491 1.264.4.39 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
3492 1.264.4.38 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
3493 1.264.4.50 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
3494 1.264.4.51 skrll usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc;
3495 1.264.4.51 skrll int endpt = ed->bEndpointAddress;
3496 1.264.4.51 skrll int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3497 1.169 augustss
3498 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3499 1.264.4.39 skrll DPRINTFN(5, "xfer=%p ux=%p sc=%p upipe=%p", xfer, ux, sc,
3500 1.264.4.21 skrll upipe);
3501 1.169 augustss
3502 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
3503 1.248 mrg
3504 1.264.4.56 skrll if (!uhci_active_intr_list(ux))
3505 1.169 augustss return;
3506 1.1 augustss
3507 1.264.4.56 skrll uhci_del_intr_list(sc, ux); /* remove from active list */
3508 1.1 augustss
3509 1.264.4.33 skrll uhci_remove_bulk(sc, upipe->bulk.sqh);
3510 1.32 augustss
3511 1.264.4.51 skrll if (xfer->ux_length) {
3512 1.264.4.51 skrll usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
3513 1.264.4.51 skrll isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
3514 1.264.4.51 skrll }
3515 1.32 augustss
3516 1.264.4.21 skrll DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0);
3517 1.1 augustss }
3518 1.1 augustss
3519 1.1 augustss /* Add interrupt QH, called with vflock. */
3520 1.1 augustss void
3521 1.119 augustss uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
3522 1.1 augustss {
3523 1.92 augustss struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos];
3524 1.42 augustss uhci_soft_qh_t *eqh;
3525 1.1 augustss
3526 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3527 1.264.4.21 skrll DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0);
3528 1.92 augustss
3529 1.42 augustss eqh = vf->eqh;
3530 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
3531 1.223 bouyer sizeof(eqh->qh.qh_hlink),
3532 1.223 bouyer BUS_DMASYNC_POSTWRITE);
3533 1.42 augustss sqh->hlink = eqh->hlink;
3534 1.42 augustss sqh->qh.qh_hlink = eqh->qh.qh_hlink;
3535 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
3536 1.223 bouyer sizeof(sqh->qh.qh_hlink),
3537 1.223 bouyer BUS_DMASYNC_PREWRITE);
3538 1.42 augustss eqh->hlink = sqh;
3539 1.121 augustss eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
3540 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
3541 1.223 bouyer sizeof(eqh->qh.qh_hlink),
3542 1.223 bouyer BUS_DMASYNC_PREWRITE);
3543 1.1 augustss vf->eqh = sqh;
3544 1.1 augustss vf->bandwidth++;
3545 1.1 augustss }
3546 1.1 augustss
3547 1.119 augustss /* Remove interrupt QH. */
3548 1.1 augustss void
3549 1.119 augustss uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
3550 1.1 augustss {
3551 1.92 augustss struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos];
3552 1.1 augustss uhci_soft_qh_t *pqh;
3553 1.1 augustss
3554 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3555 1.264.4.21 skrll DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0);
3556 1.1 augustss
3557 1.124 augustss /* See comment in uhci_remove_ctrl() */
3558 1.223 bouyer
3559 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
3560 1.223 bouyer sizeof(sqh->qh.qh_elink),
3561 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3562 1.124 augustss if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) {
3563 1.124 augustss sqh->qh.qh_elink = htole32(UHCI_PTR_T);
3564 1.223 bouyer usb_syncmem(&sqh->dma,
3565 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
3566 1.223 bouyer sizeof(sqh->qh.qh_elink),
3567 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3568 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
3569 1.124 augustss }
3570 1.124 augustss
3571 1.92 augustss pqh = uhci_find_prev_qh(vf->hqh, sqh);
3572 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
3573 1.223 bouyer sizeof(sqh->qh.qh_hlink),
3574 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3575 1.42 augustss pqh->hlink = sqh->hlink;
3576 1.42 augustss pqh->qh.qh_hlink = sqh->qh.qh_hlink;
3577 1.223 bouyer usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
3578 1.223 bouyer sizeof(pqh->qh.qh_hlink),
3579 1.223 bouyer BUS_DMASYNC_PREWRITE);
3580 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
3581 1.1 augustss if (vf->eqh == sqh)
3582 1.1 augustss vf->eqh = pqh;
3583 1.1 augustss vf->bandwidth--;
3584 1.1 augustss }
3585 1.1 augustss
3586 1.1 augustss usbd_status
3587 1.119 augustss uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival)
3588 1.1 augustss {
3589 1.1 augustss uhci_soft_qh_t *sqh;
3590 1.248 mrg int i, npoll;
3591 1.1 augustss u_int bestbw, bw, bestoffs, offs;
3592 1.1 augustss
3593 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3594 1.264.4.21 skrll DPRINTFN(2, "pipe=%p", upipe, 0, 0, 0);
3595 1.1 augustss if (ival == 0) {
3596 1.173 gson printf("uhci_device_setintr: 0 interval\n");
3597 1.264.4.13 skrll return USBD_INVAL;
3598 1.1 augustss }
3599 1.1 augustss
3600 1.1 augustss if (ival > UHCI_VFRAMELIST_COUNT)
3601 1.1 augustss ival = UHCI_VFRAMELIST_COUNT;
3602 1.1 augustss npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival;
3603 1.264.4.27 skrll DPRINTF("ival=%d npoll=%d", ival, npoll, 0, 0);
3604 1.1 augustss
3605 1.264.4.33 skrll upipe->intr.npoll = npoll;
3606 1.264.4.33 skrll upipe->intr.qhs =
3607 1.248 mrg kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP);
3608 1.264.4.33 skrll if (upipe->intr.qhs == NULL)
3609 1.248 mrg return USBD_NOMEM;
3610 1.1 augustss
3611 1.152 augustss /*
3612 1.1 augustss * Figure out which offset in the schedule that has most
3613 1.1 augustss * bandwidth left over.
3614 1.1 augustss */
3615 1.1 augustss #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1))
3616 1.1 augustss for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) {
3617 1.1 augustss for (bw = i = 0; i < npoll; i++)
3618 1.1 augustss bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth;
3619 1.1 augustss if (bw < bestbw) {
3620 1.1 augustss bestbw = bw;
3621 1.1 augustss bestoffs = offs;
3622 1.1 augustss }
3623 1.1 augustss }
3624 1.264.4.27 skrll DPRINTF("bw=%d offs=%d", bestbw, bestoffs, 0, 0);
3625 1.264.4.54 skrll for (i = 0; i < npoll; i++) {
3626 1.264.4.33 skrll upipe->intr.qhs[i] = sqh = uhci_alloc_sqh(sc);
3627 1.121 augustss sqh->elink = NULL;
3628 1.88 tsutsui sqh->qh.qh_elink = htole32(UHCI_PTR_T);
3629 1.223 bouyer usb_syncmem(&sqh->dma,
3630 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
3631 1.223 bouyer sizeof(sqh->qh.qh_elink),
3632 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3633 1.1 augustss sqh->pos = MOD(i * ival + bestoffs);
3634 1.1 augustss }
3635 1.1 augustss #undef MOD
3636 1.1 augustss
3637 1.264.4.55 skrll mutex_enter(&sc->sc_lock);
3638 1.1 augustss /* Enter QHs into the controller data structures. */
3639 1.264.4.54 skrll for (i = 0; i < npoll; i++)
3640 1.264.4.33 skrll uhci_add_intr(sc, upipe->intr.qhs[i]);
3641 1.248 mrg mutex_exit(&sc->sc_lock);
3642 1.1 augustss
3643 1.264.4.21 skrll DPRINTFN(5, "returns %p", upipe, 0, 0, 0);
3644 1.264.4.21 skrll
3645 1.264.4.13 skrll return USBD_NORMAL_COMPLETION;
3646 1.1 augustss }
3647 1.1 augustss
3648 1.1 augustss /* Open a new pipe. */
3649 1.1 augustss usbd_status
3650 1.264.4.25 skrll uhci_open(struct usbd_pipe *pipe)
3651 1.1 augustss {
3652 1.264.4.37 skrll uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
3653 1.264.4.12 skrll struct usbd_bus *bus = pipe->up_dev->ud_bus;
3654 1.264.4.50 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
3655 1.264.4.7 skrll usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc;
3656 1.248 mrg usbd_status err = USBD_NOMEM;
3657 1.79 augustss int ival;
3658 1.1 augustss
3659 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3660 1.264.4.27 skrll DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)",
3661 1.264.4.21 skrll pipe, pipe->up_dev->ud_addr, ed->bEndpointAddress, bus->ub_rhaddr);
3662 1.92 augustss
3663 1.248 mrg if (sc->sc_dying)
3664 1.248 mrg return USBD_IOERROR;
3665 1.248 mrg
3666 1.92 augustss upipe->aborting = 0;
3667 1.236 drochner /* toggle state needed for bulk endpoints */
3668 1.264.4.7 skrll upipe->nexttoggle = pipe->up_endpoint->ue_toggle;
3669 1.92 augustss
3670 1.264.4.12 skrll if (pipe->up_dev->ud_addr == bus->ub_rhaddr) {
3671 1.1 augustss switch (ed->bEndpointAddress) {
3672 1.1 augustss case USB_CONTROL_ENDPOINT:
3673 1.264.4.12 skrll pipe->up_methods = &roothub_ctrl_methods;
3674 1.1 augustss break;
3675 1.264.4.12 skrll case UE_DIR_IN | USBROOTHUB_INTR_ENDPT:
3676 1.264.4.7 skrll pipe->up_methods = &uhci_root_intr_methods;
3677 1.1 augustss break;
3678 1.1 augustss default:
3679 1.264.4.13 skrll return USBD_INVAL;
3680 1.1 augustss }
3681 1.1 augustss } else {
3682 1.1 augustss switch (ed->bmAttributes & UE_XFERTYPE) {
3683 1.1 augustss case UE_CONTROL:
3684 1.264.4.7 skrll pipe->up_methods = &uhci_device_ctrl_methods;
3685 1.264.4.33 skrll upipe->ctrl.sqh = uhci_alloc_sqh(sc);
3686 1.264.4.33 skrll if (upipe->ctrl.sqh == NULL)
3687 1.5 augustss goto bad;
3688 1.264.4.33 skrll upipe->ctrl.setup = uhci_alloc_std(sc);
3689 1.264.4.33 skrll if (upipe->ctrl.setup == NULL) {
3690 1.264.4.33 skrll uhci_free_sqh(sc, upipe->ctrl.sqh);
3691 1.5 augustss goto bad;
3692 1.5 augustss }
3693 1.264.4.33 skrll upipe->ctrl.stat = uhci_alloc_std(sc);
3694 1.264.4.33 skrll if (upipe->ctrl.stat == NULL) {
3695 1.264.4.33 skrll uhci_free_sqh(sc, upipe->ctrl.sqh);
3696 1.264.4.33 skrll uhci_free_std(sc, upipe->ctrl.setup);
3697 1.5 augustss goto bad;
3698 1.5 augustss }
3699 1.152 augustss err = usb_allocmem(&sc->sc_bus,
3700 1.152 augustss sizeof(usb_device_request_t),
3701 1.264.4.33 skrll 0, &upipe->ctrl.reqdma);
3702 1.63 augustss if (err) {
3703 1.264.4.33 skrll uhci_free_sqh(sc, upipe->ctrl.sqh);
3704 1.264.4.33 skrll uhci_free_std(sc, upipe->ctrl.setup);
3705 1.264.4.33 skrll uhci_free_std(sc, upipe->ctrl.stat);
3706 1.5 augustss goto bad;
3707 1.5 augustss }
3708 1.1 augustss break;
3709 1.1 augustss case UE_INTERRUPT:
3710 1.264.4.7 skrll pipe->up_methods = &uhci_device_intr_methods;
3711 1.264.4.7 skrll ival = pipe->up_interval;
3712 1.79 augustss if (ival == USBD_DEFAULT_INTERVAL)
3713 1.79 augustss ival = ed->bInterval;
3714 1.264.4.13 skrll return uhci_device_setintr(sc, upipe, ival);
3715 1.1 augustss case UE_ISOCHRONOUS:
3716 1.264.4.7 skrll pipe->up_methods = &uhci_device_isoc_methods;
3717 1.264.4.13 skrll return uhci_setup_isoc(pipe);
3718 1.1 augustss case UE_BULK:
3719 1.264.4.7 skrll pipe->up_methods = &uhci_device_bulk_methods;
3720 1.264.4.33 skrll upipe->bulk.sqh = uhci_alloc_sqh(sc);
3721 1.264.4.33 skrll if (upipe->bulk.sqh == NULL)
3722 1.5 augustss goto bad;
3723 1.1 augustss break;
3724 1.1 augustss }
3725 1.1 augustss }
3726 1.264.4.13 skrll return USBD_NORMAL_COMPLETION;
3727 1.5 augustss
3728 1.5 augustss bad:
3729 1.248 mrg return USBD_NOMEM;
3730 1.1 augustss }
3731 1.1 augustss
3732 1.1 augustss /*
3733 1.1 augustss * Data structures and routines to emulate the root hub.
3734 1.1 augustss */
3735 1.1 augustss /*
3736 1.166 dsainty * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also
3737 1.166 dsainty * enables the port, and also states that SET_FEATURE(PORT_ENABLE)
3738 1.166 dsainty * should not be used by the USB subsystem. As we cannot issue a
3739 1.166 dsainty * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port
3740 1.166 dsainty * will be enabled as part of the reset.
3741 1.166 dsainty *
3742 1.166 dsainty * On the VT83C572, the port cannot be successfully enabled until the
3743 1.166 dsainty * outstanding "port enable change" and "connection status change"
3744 1.166 dsainty * events have been reset.
3745 1.166 dsainty */
3746 1.166 dsainty Static usbd_status
3747 1.166 dsainty uhci_portreset(uhci_softc_t *sc, int index)
3748 1.166 dsainty {
3749 1.166 dsainty int lim, port, x;
3750 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3751 1.166 dsainty
3752 1.166 dsainty if (index == 1)
3753 1.166 dsainty port = UHCI_PORTSC1;
3754 1.166 dsainty else if (index == 2)
3755 1.166 dsainty port = UHCI_PORTSC2;
3756 1.166 dsainty else
3757 1.264.4.13 skrll return USBD_IOERROR;
3758 1.166 dsainty
3759 1.166 dsainty x = URWMASK(UREAD2(sc, port));
3760 1.166 dsainty UWRITE2(sc, port, x | UHCI_PORTSC_PR);
3761 1.166 dsainty
3762 1.166 dsainty usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY);
3763 1.166 dsainty
3764 1.264.4.27 skrll DPRINTF("uhci port %d reset, status0 = 0x%04x", index,
3765 1.264.4.21 skrll UREAD2(sc, port), 0, 0);
3766 1.166 dsainty
3767 1.166 dsainty x = URWMASK(UREAD2(sc, port));
3768 1.222 drochner UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP));
3769 1.166 dsainty
3770 1.166 dsainty delay(100);
3771 1.166 dsainty
3772 1.264.4.27 skrll DPRINTF("uhci port %d reset, status1 = 0x%04x", index,
3773 1.264.4.21 skrll UREAD2(sc, port), 0, 0);
3774 1.166 dsainty
3775 1.166 dsainty x = URWMASK(UREAD2(sc, port));
3776 1.166 dsainty UWRITE2(sc, port, x | UHCI_PORTSC_PE);
3777 1.166 dsainty
3778 1.166 dsainty for (lim = 10; --lim > 0;) {
3779 1.166 dsainty usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY);
3780 1.166 dsainty
3781 1.166 dsainty x = UREAD2(sc, port);
3782 1.264.4.27 skrll DPRINTF("uhci port %d iteration %u, status = 0x%04x", index,
3783 1.264.4.21 skrll lim, x, 0);
3784 1.166 dsainty
3785 1.166 dsainty if (!(x & UHCI_PORTSC_CCS)) {
3786 1.166 dsainty /*
3787 1.166 dsainty * No device is connected (or was disconnected
3788 1.166 dsainty * during reset). Consider the port reset.
3789 1.166 dsainty * The delay must be long enough to ensure on
3790 1.166 dsainty * the initial iteration that the device
3791 1.166 dsainty * connection will have been registered. 50ms
3792 1.166 dsainty * appears to be sufficient, but 20ms is not.
3793 1.166 dsainty */
3794 1.264.4.21 skrll DPRINTFN(3, "uhci port %d loop %u, device detached",
3795 1.264.4.21 skrll index, lim, 0, 0);
3796 1.166 dsainty break;
3797 1.166 dsainty }
3798 1.166 dsainty
3799 1.166 dsainty if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) {
3800 1.166 dsainty /*
3801 1.166 dsainty * Port enabled changed and/or connection
3802 1.166 dsainty * status changed were set. Reset either or
3803 1.166 dsainty * both raised flags (by writing a 1 to that
3804 1.166 dsainty * bit), and wait again for state to settle.
3805 1.166 dsainty */
3806 1.166 dsainty UWRITE2(sc, port, URWMASK(x) |
3807 1.166 dsainty (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)));
3808 1.166 dsainty continue;
3809 1.166 dsainty }
3810 1.166 dsainty
3811 1.166 dsainty if (x & UHCI_PORTSC_PE)
3812 1.166 dsainty /* Port is enabled */
3813 1.166 dsainty break;
3814 1.166 dsainty
3815 1.166 dsainty UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE);
3816 1.166 dsainty }
3817 1.166 dsainty
3818 1.264.4.21 skrll DPRINTFN(3, "uhci port %d reset, status2 = 0x%04x", index,
3819 1.264.4.21 skrll UREAD2(sc, port), 0, 0);
3820 1.166 dsainty
3821 1.166 dsainty if (lim <= 0) {
3822 1.264.4.27 skrll DPRINTF("uhci port %d reset timed out", index,
3823 1.264.4.21 skrll 0, 0, 0);
3824 1.264.4.13 skrll return USBD_TIMEOUT;
3825 1.166 dsainty }
3826 1.184 perry
3827 1.166 dsainty sc->sc_isreset = 1;
3828 1.264.4.13 skrll return USBD_NORMAL_COMPLETION;
3829 1.166 dsainty }
3830 1.166 dsainty
3831 1.264.4.12 skrll Static int
3832 1.264.4.12 skrll uhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req,
3833 1.264.4.12 skrll void *buf, int buflen)
3834 1.1 augustss {
3835 1.264.4.37 skrll uhci_softc_t *sc = UHCI_BUS2SC(bus);
3836 1.1 augustss int port, x;
3837 1.264.4.12 skrll int status, change, totlen = 0;
3838 1.264.4.12 skrll uint16_t len, value, index;
3839 1.1 augustss usb_port_status_t ps;
3840 1.63 augustss usbd_status err;
3841 1.1 augustss
3842 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3843 1.264.4.21 skrll
3844 1.82 augustss if (sc->sc_dying)
3845 1.264.4.12 skrll return -1;
3846 1.1 augustss
3847 1.264.4.27 skrll DPRINTF("type=0x%02x request=%02x", req->bmRequestType,
3848 1.264.4.21 skrll req->bRequest, 0, 0);
3849 1.1 augustss
3850 1.1 augustss len = UGETW(req->wLength);
3851 1.1 augustss value = UGETW(req->wValue);
3852 1.1 augustss index = UGETW(req->wIndex);
3853 1.49 augustss
3854 1.1 augustss #define C(x,y) ((x) | ((y) << 8))
3855 1.264.4.12 skrll switch (C(req->bRequest, req->bmRequestType)) {
3856 1.1 augustss case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3857 1.264.4.27 skrll DPRINTF("wValue=0x%04x", value, 0, 0, 0);
3858 1.195 christos if (len == 0)
3859 1.195 christos break;
3860 1.264.4.12 skrll switch (value) {
3861 1.264.4.12 skrll case C(0, UDESC_DEVICE): {
3862 1.264.4.12 skrll usb_device_descriptor_t devd;
3863 1.264.4.12 skrll
3864 1.264.4.12 skrll totlen = min(buflen, sizeof(devd));
3865 1.264.4.12 skrll memcpy(&devd, buf, totlen);
3866 1.264.4.12 skrll USETW(devd.idVendor, sc->sc_id_vendor);
3867 1.264.4.12 skrll memcpy(buf, &devd, totlen);
3868 1.1 augustss break;
3869 1.264.4.12 skrll }
3870 1.264.4.12 skrll case C(1, UDESC_STRING):
3871 1.213 drochner #define sd ((usb_string_descriptor_t *)buf)
3872 1.264.4.12 skrll /* Vendor */
3873 1.264.4.12 skrll totlen = usb_makestrdesc(sd, len, sc->sc_vendor);
3874 1.264.4.12 skrll break;
3875 1.264.4.12 skrll case C(2, UDESC_STRING):
3876 1.264.4.12 skrll /* Product */
3877 1.264.4.12 skrll totlen = usb_makestrdesc(sd, len, "UHCI root hub");
3878 1.1 augustss break;
3879 1.264.4.12 skrll #undef sd
3880 1.1 augustss default:
3881 1.264.4.12 skrll /* default from usbroothub */
3882 1.264.4.12 skrll return buflen;
3883 1.1 augustss }
3884 1.1 augustss break;
3885 1.264.4.12 skrll
3886 1.1 augustss /* Hub requests */
3887 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3888 1.1 augustss break;
3889 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3890 1.264.4.27 skrll DPRINTF("UR_CLEAR_PORT_FEATURE port=%d feature=%d", index,
3891 1.264.4.21 skrll value, 0, 0);
3892 1.1 augustss if (index == 1)
3893 1.1 augustss port = UHCI_PORTSC1;
3894 1.1 augustss else if (index == 2)
3895 1.1 augustss port = UHCI_PORTSC2;
3896 1.1 augustss else {
3897 1.264.4.12 skrll return -1;
3898 1.1 augustss }
3899 1.1 augustss switch(value) {
3900 1.1 augustss case UHF_PORT_ENABLE:
3901 1.137 augustss x = URWMASK(UREAD2(sc, port));
3902 1.1 augustss UWRITE2(sc, port, x & ~UHCI_PORTSC_PE);
3903 1.1 augustss break;
3904 1.1 augustss case UHF_PORT_SUSPEND:
3905 1.137 augustss x = URWMASK(UREAD2(sc, port));
3906 1.222 drochner if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */
3907 1.222 drochner break;
3908 1.222 drochner UWRITE2(sc, port, x | UHCI_PORTSC_RD);
3909 1.222 drochner /* see USB2 spec ch. 7.1.7.7 */
3910 1.222 drochner usb_delay_ms(&sc->sc_bus, 20);
3911 1.1 augustss UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP);
3912 1.222 drochner /* 10ms resume delay must be provided by caller */
3913 1.1 augustss break;
3914 1.1 augustss case UHF_PORT_RESET:
3915 1.137 augustss x = URWMASK(UREAD2(sc, port));
3916 1.1 augustss UWRITE2(sc, port, x & ~UHCI_PORTSC_PR);
3917 1.1 augustss break;
3918 1.1 augustss case UHF_C_PORT_CONNECTION:
3919 1.137 augustss x = URWMASK(UREAD2(sc, port));
3920 1.1 augustss UWRITE2(sc, port, x | UHCI_PORTSC_CSC);
3921 1.1 augustss break;
3922 1.1 augustss case UHF_C_PORT_ENABLE:
3923 1.137 augustss x = URWMASK(UREAD2(sc, port));
3924 1.1 augustss UWRITE2(sc, port, x | UHCI_PORTSC_POEDC);
3925 1.1 augustss break;
3926 1.1 augustss case UHF_C_PORT_OVER_CURRENT:
3927 1.137 augustss x = URWMASK(UREAD2(sc, port));
3928 1.1 augustss UWRITE2(sc, port, x | UHCI_PORTSC_OCIC);
3929 1.1 augustss break;
3930 1.1 augustss case UHF_C_PORT_RESET:
3931 1.1 augustss sc->sc_isreset = 0;
3932 1.264.4.16 skrll break;
3933 1.1 augustss case UHF_PORT_CONNECTION:
3934 1.1 augustss case UHF_PORT_OVER_CURRENT:
3935 1.1 augustss case UHF_PORT_POWER:
3936 1.1 augustss case UHF_PORT_LOW_SPEED:
3937 1.1 augustss case UHF_C_PORT_SUSPEND:
3938 1.1 augustss default:
3939 1.264.4.12 skrll return -1;
3940 1.1 augustss }
3941 1.1 augustss break;
3942 1.1 augustss case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER):
3943 1.1 augustss if (index == 1)
3944 1.1 augustss port = UHCI_PORTSC1;
3945 1.1 augustss else if (index == 2)
3946 1.1 augustss port = UHCI_PORTSC2;
3947 1.1 augustss else {
3948 1.264.4.12 skrll return -1;
3949 1.1 augustss }
3950 1.1 augustss if (len > 0) {
3951 1.264.4.1 skrll *(uint8_t *)buf =
3952 1.1 augustss (UREAD2(sc, port) & UHCI_PORTSC_LS) >>
3953 1.1 augustss UHCI_PORTSC_LS_SHIFT;
3954 1.1 augustss totlen = 1;
3955 1.1 augustss }
3956 1.1 augustss break;
3957 1.1 augustss case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3958 1.195 christos if (len == 0)
3959 1.195 christos break;
3960 1.177 toshii if ((value & 0xff) != 0) {
3961 1.264.4.12 skrll return -1;
3962 1.1 augustss }
3963 1.264.4.12 skrll usb_hub_descriptor_t hubd;
3964 1.264.4.12 skrll
3965 1.264.4.12 skrll totlen = min(buflen, sizeof(hubd));
3966 1.264.4.12 skrll memcpy(&hubd, buf, totlen);
3967 1.264.4.12 skrll hubd.bNbrPorts = 2;
3968 1.264.4.12 skrll memcpy(buf, &hubd, totlen);
3969 1.1 augustss break;
3970 1.1 augustss case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3971 1.1 augustss if (len != 4) {
3972 1.264.4.12 skrll return -1;
3973 1.1 augustss }
3974 1.1 augustss memset(buf, 0, len);
3975 1.1 augustss totlen = len;
3976 1.1 augustss break;
3977 1.1 augustss case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3978 1.1 augustss if (index == 1)
3979 1.1 augustss port = UHCI_PORTSC1;
3980 1.1 augustss else if (index == 2)
3981 1.1 augustss port = UHCI_PORTSC2;
3982 1.1 augustss else {
3983 1.264.4.12 skrll return -1;
3984 1.1 augustss }
3985 1.1 augustss if (len != 4) {
3986 1.264.4.12 skrll return -1;
3987 1.1 augustss }
3988 1.1 augustss x = UREAD2(sc, port);
3989 1.1 augustss status = change = 0;
3990 1.142 augustss if (x & UHCI_PORTSC_CCS)
3991 1.1 augustss status |= UPS_CURRENT_CONNECT_STATUS;
3992 1.152 augustss if (x & UHCI_PORTSC_CSC)
3993 1.1 augustss change |= UPS_C_CONNECT_STATUS;
3994 1.152 augustss if (x & UHCI_PORTSC_PE)
3995 1.1 augustss status |= UPS_PORT_ENABLED;
3996 1.152 augustss if (x & UHCI_PORTSC_POEDC)
3997 1.1 augustss change |= UPS_C_PORT_ENABLED;
3998 1.152 augustss if (x & UHCI_PORTSC_OCI)
3999 1.1 augustss status |= UPS_OVERCURRENT_INDICATOR;
4000 1.152 augustss if (x & UHCI_PORTSC_OCIC)
4001 1.1 augustss change |= UPS_C_OVERCURRENT_INDICATOR;
4002 1.152 augustss if (x & UHCI_PORTSC_SUSP)
4003 1.1 augustss status |= UPS_SUSPEND;
4004 1.152 augustss if (x & UHCI_PORTSC_LSDA)
4005 1.1 augustss status |= UPS_LOW_SPEED;
4006 1.1 augustss status |= UPS_PORT_POWER;
4007 1.1 augustss if (sc->sc_isreset)
4008 1.1 augustss change |= UPS_C_PORT_RESET;
4009 1.1 augustss USETW(ps.wPortStatus, status);
4010 1.1 augustss USETW(ps.wPortChange, change);
4011 1.264.4.12 skrll totlen = min(len, sizeof(ps));
4012 1.264.4.12 skrll memcpy(buf, &ps, totlen);
4013 1.1 augustss break;
4014 1.1 augustss case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
4015 1.264.4.12 skrll return -1;
4016 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
4017 1.1 augustss break;
4018 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
4019 1.1 augustss if (index == 1)
4020 1.1 augustss port = UHCI_PORTSC1;
4021 1.1 augustss else if (index == 2)
4022 1.1 augustss port = UHCI_PORTSC2;
4023 1.1 augustss else {
4024 1.264.4.12 skrll return -1;
4025 1.1 augustss }
4026 1.1 augustss switch(value) {
4027 1.1 augustss case UHF_PORT_ENABLE:
4028 1.137 augustss x = URWMASK(UREAD2(sc, port));
4029 1.1 augustss UWRITE2(sc, port, x | UHCI_PORTSC_PE);
4030 1.1 augustss break;
4031 1.1 augustss case UHF_PORT_SUSPEND:
4032 1.137 augustss x = URWMASK(UREAD2(sc, port));
4033 1.1 augustss UWRITE2(sc, port, x | UHCI_PORTSC_SUSP);
4034 1.1 augustss break;
4035 1.1 augustss case UHF_PORT_RESET:
4036 1.166 dsainty err = uhci_portreset(sc, index);
4037 1.264.4.12 skrll if (err != USBD_NORMAL_COMPLETION)
4038 1.264.4.12 skrll return -1;
4039 1.264.4.12 skrll return 0;
4040 1.111 augustss case UHF_PORT_POWER:
4041 1.111 augustss /* Pretend we turned on power */
4042 1.264.4.12 skrll return 0;
4043 1.1 augustss case UHF_C_PORT_CONNECTION:
4044 1.1 augustss case UHF_C_PORT_ENABLE:
4045 1.1 augustss case UHF_C_PORT_OVER_CURRENT:
4046 1.1 augustss case UHF_PORT_CONNECTION:
4047 1.1 augustss case UHF_PORT_OVER_CURRENT:
4048 1.1 augustss case UHF_PORT_LOW_SPEED:
4049 1.1 augustss case UHF_C_PORT_SUSPEND:
4050 1.1 augustss case UHF_C_PORT_RESET:
4051 1.1 augustss default:
4052 1.264.4.12 skrll return -1;
4053 1.1 augustss }
4054 1.1 augustss break;
4055 1.1 augustss default:
4056 1.264.4.12 skrll /* default from usbroothub */
4057 1.264.4.27 skrll DPRINTF("returning %d (usbroothub default)",
4058 1.264.4.21 skrll buflen, 0, 0, 0);
4059 1.264.4.12 skrll return buflen;
4060 1.1 augustss }
4061 1.1 augustss
4062 1.264.4.27 skrll DPRINTF("returning %d", totlen, 0, 0, 0);
4063 1.264.4.21 skrll
4064 1.264.4.12 skrll return totlen;
4065 1.1 augustss }
4066 1.1 augustss
4067 1.1 augustss /* Abort a root interrupt request. */
4068 1.1 augustss void
4069 1.264.4.25 skrll uhci_root_intr_abort(struct usbd_xfer *xfer)
4070 1.1 augustss {
4071 1.264.4.37 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
4072 1.30 augustss
4073 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
4074 1.264.4.7 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
4075 1.248 mrg
4076 1.234 dyoung callout_stop(&sc->sc_poll_handle);
4077 1.96 augustss sc->sc_intr_xfer = NULL;
4078 1.58 augustss
4079 1.264.4.7 skrll xfer->ux_status = USBD_CANCELLED;
4080 1.96 augustss #ifdef DIAGNOSTIC
4081 1.264.4.41 skrll UHCI_XFER2UXFER(xfer)->ux_isdone = true;
4082 1.96 augustss #endif
4083 1.63 augustss usb_transfer_complete(xfer);
4084 1.1 augustss }
4085 1.1 augustss
4086 1.16 augustss usbd_status
4087 1.264.4.25 skrll uhci_root_intr_transfer(struct usbd_xfer *xfer)
4088 1.16 augustss {
4089 1.264.4.37 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
4090 1.63 augustss usbd_status err;
4091 1.16 augustss
4092 1.52 augustss /* Insert last in queue. */
4093 1.248 mrg mutex_enter(&sc->sc_lock);
4094 1.63 augustss err = usb_insert_transfer(xfer);
4095 1.248 mrg mutex_exit(&sc->sc_lock);
4096 1.63 augustss if (err)
4097 1.264.4.13 skrll return err;
4098 1.52 augustss
4099 1.186 skrll /*
4100 1.186 skrll * Pipe isn't running (otherwise err would be USBD_INPROG),
4101 1.67 augustss * start first
4102 1.67 augustss */
4103 1.264.4.13 skrll return uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
4104 1.16 augustss }
4105 1.16 augustss
4106 1.1 augustss /* Start a transfer on the root interrupt pipe */
4107 1.1 augustss usbd_status
4108 1.264.4.25 skrll uhci_root_intr_start(struct usbd_xfer *xfer)
4109 1.1 augustss {
4110 1.264.4.25 skrll struct usbd_pipe *pipe = xfer->ux_pipe;
4111 1.264.4.37 skrll uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
4112 1.174 drochner unsigned int ival;
4113 1.1 augustss
4114 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
4115 1.264.4.27 skrll DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length,
4116 1.264.4.21 skrll xfer->ux_flags, 0);
4117 1.82 augustss
4118 1.82 augustss if (sc->sc_dying)
4119 1.264.4.13 skrll return USBD_IOERROR;
4120 1.1 augustss
4121 1.174 drochner /* XXX temporary variable needed to avoid gcc3 warning */
4122 1.264.4.7 skrll ival = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval;
4123 1.174 drochner sc->sc_ival = mstohz(ival);
4124 1.234 dyoung callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer);
4125 1.96 augustss sc->sc_intr_xfer = xfer;
4126 1.264.4.13 skrll return USBD_IN_PROGRESS;
4127 1.1 augustss }
4128 1.1 augustss
4129 1.1 augustss /* Close the root interrupt pipe. */
4130 1.1 augustss void
4131 1.264.4.25 skrll uhci_root_intr_close(struct usbd_pipe *pipe)
4132 1.1 augustss {
4133 1.264.4.37 skrll uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
4134 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
4135 1.30 augustss
4136 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
4137 1.248 mrg
4138 1.234 dyoung callout_stop(&sc->sc_poll_handle);
4139 1.96 augustss sc->sc_intr_xfer = NULL;
4140 1.1 augustss }
4141