uhci.c revision 1.264.4.60 1 1.264.4.60 skrll /* $NetBSD: uhci.c,v 1.264.4.60 2016/02/16 07:30:46 skrll Exp $ */
2 1.1 augustss
3 1.1 augustss /*
4 1.248 mrg * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc.
5 1.1 augustss * All rights reserved.
6 1.1 augustss *
7 1.11 augustss * This code is derived from software contributed to The NetBSD Foundation
8 1.113 augustss * by Lennart Augustsson (lennart (at) augustsson.net) at
9 1.248 mrg * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca)
10 1.248 mrg * and Matthew R. Green (mrg (at) eterna.com.au).
11 1.1 augustss *
12 1.1 augustss * Redistribution and use in source and binary forms, with or without
13 1.1 augustss * modification, are permitted provided that the following conditions
14 1.1 augustss * are met:
15 1.1 augustss * 1. Redistributions of source code must retain the above copyright
16 1.1 augustss * notice, this list of conditions and the following disclaimer.
17 1.1 augustss * 2. Redistributions in binary form must reproduce the above copyright
18 1.1 augustss * notice, this list of conditions and the following disclaimer in the
19 1.1 augustss * documentation and/or other materials provided with the distribution.
20 1.1 augustss *
21 1.1 augustss * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22 1.1 augustss * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 1.1 augustss * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 1.1 augustss * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25 1.1 augustss * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 1.1 augustss * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 1.1 augustss * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 1.1 augustss * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 1.1 augustss * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 1.1 augustss * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 1.1 augustss * POSSIBILITY OF SUCH DAMAGE.
32 1.1 augustss */
33 1.1 augustss
34 1.1 augustss /*
35 1.1 augustss * USB Universal Host Controller driver.
36 1.28 augustss * Handles e.g. PIIX3 and PIIX4.
37 1.1 augustss *
38 1.229 uebayasi * UHCI spec: http://www.intel.com/technology/usb/spec.htm
39 1.229 uebayasi * USB spec: http://www.usb.org/developers/docs/
40 1.71 augustss * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf
41 1.71 augustss * ftp://download.intel.com/design/intarch/datashts/29056201.pdf
42 1.1 augustss */
43 1.143 lukem
44 1.143 lukem #include <sys/cdefs.h>
45 1.264.4.60 skrll __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.264.4.60 2016/02/16 07:30:46 skrll Exp $");
46 1.264.4.30 skrll
47 1.264.4.30 skrll #include "opt_usb.h"
48 1.1 augustss
49 1.1 augustss #include <sys/param.h>
50 1.264.4.20 skrll
51 1.264.4.20 skrll #include <sys/bus.h>
52 1.264.4.20 skrll #include <sys/cpu.h>
53 1.264.4.20 skrll #include <sys/device.h>
54 1.1 augustss #include <sys/kernel.h>
55 1.248 mrg #include <sys/kmem.h>
56 1.264.4.20 skrll #include <sys/mutex.h>
57 1.1 augustss #include <sys/proc.h>
58 1.1 augustss #include <sys/queue.h>
59 1.264.4.20 skrll #include <sys/select.h>
60 1.264.4.20 skrll #include <sys/sysctl.h>
61 1.264.4.20 skrll #include <sys/systm.h>
62 1.1 augustss
63 1.39 augustss #include <machine/endian.h>
64 1.7 augustss
65 1.1 augustss #include <dev/usb/usb.h>
66 1.1 augustss #include <dev/usb/usbdi.h>
67 1.1 augustss #include <dev/usb/usbdivar.h>
68 1.7 augustss #include <dev/usb/usb_mem.h>
69 1.1 augustss
70 1.1 augustss #include <dev/usb/uhcireg.h>
71 1.1 augustss #include <dev/usb/uhcivar.h>
72 1.264.4.11 skrll #include <dev/usb/usbroothub.h>
73 1.264.4.21 skrll #include <dev/usb/usbhist.h>
74 1.1 augustss
75 1.125 augustss /* Use bandwidth reclamation for control transfers. Some devices choke on it. */
76 1.125 augustss /*#define UHCI_CTL_LOOP */
77 1.125 augustss
78 1.67 augustss #ifdef UHCI_DEBUG
79 1.92 augustss uhci_softc_t *thesc;
80 1.125 augustss int uhcinoloop = 0;
81 1.59 augustss #endif
82 1.59 augustss
83 1.264.4.21 skrll #ifdef USB_DEBUG
84 1.264.4.21 skrll #ifndef UHCI_DEBUG
85 1.264.4.21 skrll #define uhcidebug 0
86 1.264.4.21 skrll #else
87 1.264.4.21 skrll static int uhcidebug = 0;
88 1.264.4.21 skrll
89 1.264.4.21 skrll SYSCTL_SETUP(sysctl_hw_uhci_setup, "sysctl hw.uhci setup")
90 1.264.4.21 skrll {
91 1.264.4.21 skrll int err;
92 1.264.4.21 skrll const struct sysctlnode *rnode;
93 1.264.4.21 skrll const struct sysctlnode *cnode;
94 1.264.4.21 skrll
95 1.264.4.21 skrll err = sysctl_createv(clog, 0, NULL, &rnode,
96 1.264.4.21 skrll CTLFLAG_PERMANENT, CTLTYPE_NODE, "uhci",
97 1.264.4.21 skrll SYSCTL_DESCR("uhci global controls"),
98 1.264.4.21 skrll NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
99 1.264.4.21 skrll
100 1.264.4.21 skrll if (err)
101 1.264.4.21 skrll goto fail;
102 1.264.4.21 skrll
103 1.264.4.21 skrll /* control debugging printfs */
104 1.264.4.21 skrll err = sysctl_createv(clog, 0, &rnode, &cnode,
105 1.264.4.21 skrll CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
106 1.264.4.21 skrll "debug", SYSCTL_DESCR("Enable debugging output"),
107 1.264.4.21 skrll NULL, 0, &uhcidebug, sizeof(uhcidebug), CTL_CREATE, CTL_EOL);
108 1.264.4.21 skrll if (err)
109 1.264.4.21 skrll goto fail;
110 1.264.4.21 skrll
111 1.264.4.21 skrll return;
112 1.264.4.21 skrll fail:
113 1.264.4.21 skrll aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err);
114 1.264.4.21 skrll }
115 1.264.4.21 skrll
116 1.264.4.21 skrll #endif /* UHCI_DEBUG */
117 1.264.4.21 skrll #endif /* USB_DEBUG */
118 1.264.4.21 skrll
119 1.264.4.27 skrll #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,1,FMT,A,B,C,D)
120 1.264.4.21 skrll #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,N,FMT,A,B,C,D)
121 1.264.4.21 skrll #define UHCIHIST_FUNC() USBHIST_FUNC()
122 1.264.4.21 skrll #define UHCIHIST_CALLED(name) USBHIST_CALLED(uhcidebug)
123 1.264.4.21 skrll
124 1.39 augustss /*
125 1.39 augustss * The UHCI controller is little endian, so on big endian machines
126 1.181 drochner * the data stored in memory needs to be swapped.
127 1.39 augustss */
128 1.39 augustss
129 1.1 augustss struct uhci_pipe {
130 1.1 augustss struct usbd_pipe pipe;
131 1.32 augustss int nexttoggle;
132 1.92 augustss
133 1.92 augustss u_char aborting;
134 1.264.4.25 skrll struct usbd_xfer *abortstart, abortend;
135 1.92 augustss
136 1.1 augustss /* Info needed for different pipe kinds. */
137 1.1 augustss union {
138 1.1 augustss /* Control pipe */
139 1.1 augustss struct {
140 1.1 augustss uhci_soft_qh_t *sqh;
141 1.7 augustss usb_dma_t reqdma;
142 1.264.4.55 skrll uhci_soft_td_t *setup;
143 1.264.4.55 skrll uhci_soft_td_t *stat;
144 1.264.4.33 skrll } ctrl;
145 1.1 augustss /* Interrupt pipe */
146 1.1 augustss struct {
147 1.1 augustss int npoll;
148 1.1 augustss uhci_soft_qh_t **qhs;
149 1.1 augustss } intr;
150 1.1 augustss /* Bulk pipe */
151 1.1 augustss struct {
152 1.1 augustss uhci_soft_qh_t *sqh;
153 1.1 augustss } bulk;
154 1.264.4.33 skrll /* Isochronous pipe */
155 1.264.4.33 skrll struct isoc {
156 1.16 augustss uhci_soft_td_t **stds;
157 1.48 augustss int next, inuse;
158 1.264.4.33 skrll } isoc;
159 1.264.4.33 skrll };
160 1.1 augustss };
161 1.1 augustss
162 1.142 augustss Static void uhci_globalreset(uhci_softc_t *);
163 1.166 dsainty Static usbd_status uhci_portreset(uhci_softc_t*, int);
164 1.142 augustss Static void uhci_reset(uhci_softc_t *);
165 1.264.4.15 skrll Static usbd_status uhci_run(uhci_softc_t *, int, int);
166 1.123 augustss Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *);
167 1.119 augustss Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *);
168 1.264.4.55 skrll Static void uhci_free_std_locked(uhci_softc_t *, uhci_soft_td_t *);
169 1.123 augustss Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *);
170 1.119 augustss Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *);
171 1.16 augustss #if 0
172 1.119 augustss Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *,
173 1.264.4.48 skrll uhci_intr_info_t *);
174 1.119 augustss Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *);
175 1.16 augustss #endif
176 1.1 augustss
177 1.264.4.55 skrll Static void uhci_free_std_chain(uhci_softc_t *, uhci_soft_td_t *,
178 1.264.4.55 skrll uhci_soft_td_t *);
179 1.264.4.55 skrll Static usbd_status uhci_alloc_std_chain(uhci_softc_t *, struct usbd_xfer *,
180 1.264.4.55 skrll int, int, uhci_soft_td_t **, uhci_soft_td_t **);
181 1.264.4.55 skrll Static void uhci_free_stds(uhci_softc_t *, struct uhci_xfer *);
182 1.264.4.55 skrll
183 1.264.4.55 skrll Static void uhci_reset_std_chain(uhci_softc_t *, struct usbd_xfer *,
184 1.264.4.58 skrll int, int, int *, uhci_soft_td_t **);
185 1.264.4.55 skrll
186 1.119 augustss Static void uhci_poll_hub(void *);
187 1.264.4.25 skrll Static void uhci_waitintr(uhci_softc_t *, struct usbd_xfer *);
188 1.264.4.39 skrll Static void uhci_check_intr(uhci_softc_t *, struct uhci_xfer *);
189 1.264.4.39 skrll Static void uhci_idone(struct uhci_xfer *);
190 1.119 augustss
191 1.264.4.25 skrll Static void uhci_abort_xfer(struct usbd_xfer *, usbd_status);
192 1.119 augustss
193 1.119 augustss Static void uhci_timeout(void *);
194 1.153 augustss Static void uhci_timeout_task(void *);
195 1.123 augustss Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *);
196 1.123 augustss Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *);
197 1.119 augustss Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *);
198 1.123 augustss Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *);
199 1.123 augustss Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *);
200 1.119 augustss Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *);
201 1.264.4.15 skrll Static void uhci_add_loop(uhci_softc_t *);
202 1.264.4.15 skrll Static void uhci_rem_loop(uhci_softc_t *);
203 1.119 augustss
204 1.264.4.25 skrll Static usbd_status uhci_setup_isoc(struct usbd_pipe *);
205 1.264.4.25 skrll Static void uhci_device_isoc_enter(struct usbd_xfer *);
206 1.119 augustss
207 1.264.4.36 skrll Static struct usbd_xfer *
208 1.264.4.36 skrll uhci_allocx(struct usbd_bus *, unsigned int);
209 1.264.4.25 skrll Static void uhci_freex(struct usbd_bus *, struct usbd_xfer *);
210 1.248 mrg Static void uhci_get_lock(struct usbd_bus *, kmutex_t **);
211 1.264.4.13 skrll Static int uhci_roothub_ctrl(struct usbd_bus *,
212 1.264.4.42 skrll usb_device_request_t *, void *, int);
213 1.119 augustss
214 1.264.4.55 skrll Static int uhci_device_ctrl_init(struct usbd_xfer *);
215 1.264.4.55 skrll Static void uhci_device_ctrl_fini(struct usbd_xfer *);
216 1.264.4.25 skrll Static usbd_status uhci_device_ctrl_transfer(struct usbd_xfer *);
217 1.264.4.25 skrll Static usbd_status uhci_device_ctrl_start(struct usbd_xfer *);
218 1.264.4.25 skrll Static void uhci_device_ctrl_abort(struct usbd_xfer *);
219 1.264.4.25 skrll Static void uhci_device_ctrl_close(struct usbd_pipe *);
220 1.264.4.25 skrll Static void uhci_device_ctrl_done(struct usbd_xfer *);
221 1.264.4.25 skrll
222 1.264.4.55 skrll Static int uhci_device_intr_init(struct usbd_xfer *);
223 1.264.4.55 skrll Static void uhci_device_intr_fini(struct usbd_xfer *);
224 1.264.4.25 skrll Static usbd_status uhci_device_intr_transfer(struct usbd_xfer *);
225 1.264.4.25 skrll Static usbd_status uhci_device_intr_start(struct usbd_xfer *);
226 1.264.4.25 skrll Static void uhci_device_intr_abort(struct usbd_xfer *);
227 1.264.4.25 skrll Static void uhci_device_intr_close(struct usbd_pipe *);
228 1.264.4.25 skrll Static void uhci_device_intr_done(struct usbd_xfer *);
229 1.264.4.25 skrll
230 1.264.4.55 skrll Static int uhci_device_bulk_init(struct usbd_xfer *);
231 1.264.4.55 skrll Static void uhci_device_bulk_fini(struct usbd_xfer *);
232 1.264.4.25 skrll Static usbd_status uhci_device_bulk_transfer(struct usbd_xfer *);
233 1.264.4.25 skrll Static usbd_status uhci_device_bulk_start(struct usbd_xfer *);
234 1.264.4.25 skrll Static void uhci_device_bulk_abort(struct usbd_xfer *);
235 1.264.4.25 skrll Static void uhci_device_bulk_close(struct usbd_pipe *);
236 1.264.4.25 skrll Static void uhci_device_bulk_done(struct usbd_xfer *);
237 1.264.4.25 skrll
238 1.264.4.55 skrll Static int uhci_device_isoc_init(struct usbd_xfer *);
239 1.264.4.55 skrll Static void uhci_device_isoc_fini(struct usbd_xfer *);
240 1.264.4.25 skrll Static usbd_status uhci_device_isoc_transfer(struct usbd_xfer *);
241 1.264.4.25 skrll Static usbd_status uhci_device_isoc_start(struct usbd_xfer *);
242 1.264.4.25 skrll Static void uhci_device_isoc_abort(struct usbd_xfer *);
243 1.264.4.25 skrll Static void uhci_device_isoc_close(struct usbd_pipe *);
244 1.264.4.25 skrll Static void uhci_device_isoc_done(struct usbd_xfer *);
245 1.264.4.25 skrll
246 1.264.4.25 skrll Static usbd_status uhci_root_intr_transfer(struct usbd_xfer *);
247 1.264.4.25 skrll Static usbd_status uhci_root_intr_start(struct usbd_xfer *);
248 1.264.4.25 skrll Static void uhci_root_intr_abort(struct usbd_xfer *);
249 1.264.4.25 skrll Static void uhci_root_intr_close(struct usbd_pipe *);
250 1.264.4.25 skrll Static void uhci_root_intr_done(struct usbd_xfer *);
251 1.119 augustss
252 1.264.4.25 skrll Static usbd_status uhci_open(struct usbd_pipe *);
253 1.119 augustss Static void uhci_poll(struct usbd_bus *);
254 1.133 augustss Static void uhci_softintr(void *);
255 1.119 augustss
256 1.119 augustss Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *);
257 1.158 augustss Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *);
258 1.264.4.15 skrll Static usbd_status uhci_device_setintr(uhci_softc_t *,
259 1.264.4.15 skrll struct uhci_pipe *, int);
260 1.119 augustss
261 1.264.4.25 skrll Static void uhci_device_clear_toggle(struct usbd_pipe *);
262 1.264.4.25 skrll Static void uhci_noop(struct usbd_pipe *);
263 1.119 augustss
264 1.264.4.42 skrll static inline uhci_soft_qh_t *
265 1.264.4.42 skrll uhci_find_prev_qh(uhci_soft_qh_t *, uhci_soft_qh_t *);
266 1.119 augustss
267 1.119 augustss #ifdef UHCI_DEBUG
268 1.119 augustss Static void uhci_dump_all(uhci_softc_t *);
269 1.119 augustss Static void uhci_dumpregs(uhci_softc_t *);
270 1.119 augustss Static void uhci_dump_qhs(uhci_soft_qh_t *);
271 1.119 augustss Static void uhci_dump_qh(uhci_soft_qh_t *);
272 1.119 augustss Static void uhci_dump_tds(uhci_soft_td_t *);
273 1.119 augustss Static void uhci_dump_td(uhci_soft_td_t *);
274 1.264.4.40 skrll Static void uhci_dump_ii(struct uhci_xfer *);
275 1.119 augustss void uhci_dump(void);
276 1.1 augustss #endif
277 1.1 augustss
278 1.112 augustss #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \
279 1.112 augustss BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
280 1.112 augustss #define UWRITE1(sc, r, x) \
281 1.165 dsainty do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \
282 1.165 dsainty } while (/*CONSTCOND*/0)
283 1.112 augustss #define UWRITE2(sc, r, x) \
284 1.165 dsainty do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \
285 1.165 dsainty } while (/*CONSTCOND*/0)
286 1.112 augustss #define UWRITE4(sc, r, x) \
287 1.165 dsainty do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \
288 1.165 dsainty } while (/*CONSTCOND*/0)
289 1.264.4.42 skrll
290 1.196 mrg static __inline uint8_t
291 1.196 mrg UREAD1(uhci_softc_t *sc, bus_size_t r)
292 1.196 mrg {
293 1.196 mrg
294 1.196 mrg UBARR(sc);
295 1.196 mrg return bus_space_read_1(sc->iot, sc->ioh, r);
296 1.196 mrg }
297 1.196 mrg
298 1.196 mrg static __inline uint16_t
299 1.196 mrg UREAD2(uhci_softc_t *sc, bus_size_t r)
300 1.196 mrg {
301 1.196 mrg
302 1.196 mrg UBARR(sc);
303 1.196 mrg return bus_space_read_2(sc->iot, sc->ioh, r);
304 1.196 mrg }
305 1.196 mrg
306 1.260 joerg #ifdef UHCI_DEBUG
307 1.196 mrg static __inline uint32_t
308 1.196 mrg UREAD4(uhci_softc_t *sc, bus_size_t r)
309 1.196 mrg {
310 1.196 mrg
311 1.196 mrg UBARR(sc);
312 1.196 mrg return bus_space_read_4(sc->iot, sc->ioh, r);
313 1.196 mrg }
314 1.260 joerg #endif
315 1.1 augustss
316 1.1 augustss #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd)
317 1.1 augustss #define UHCISTS(sc) UREAD2(sc, UHCI_STS)
318 1.1 augustss
319 1.142 augustss #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */
320 1.1 augustss
321 1.1 augustss #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK)
322 1.1 augustss
323 1.208 drochner const struct usbd_bus_methods uhci_bus_methods = {
324 1.264.4.5 skrll .ubm_open = uhci_open,
325 1.264.4.5 skrll .ubm_softint = uhci_softintr,
326 1.264.4.5 skrll .ubm_dopoll = uhci_poll,
327 1.264.4.5 skrll .ubm_allocx = uhci_allocx,
328 1.264.4.5 skrll .ubm_freex = uhci_freex,
329 1.264.4.5 skrll .ubm_getlock = uhci_get_lock,
330 1.264.4.12 skrll .ubm_rhctrl = uhci_roothub_ctrl,
331 1.1 augustss };
332 1.1 augustss
333 1.208 drochner const struct usbd_pipe_methods uhci_root_intr_methods = {
334 1.264.4.5 skrll .upm_transfer = uhci_root_intr_transfer,
335 1.264.4.5 skrll .upm_start = uhci_root_intr_start,
336 1.264.4.5 skrll .upm_abort = uhci_root_intr_abort,
337 1.264.4.5 skrll .upm_close = uhci_root_intr_close,
338 1.264.4.5 skrll .upm_cleartoggle = uhci_noop,
339 1.264.4.5 skrll .upm_done = uhci_root_intr_done,
340 1.1 augustss };
341 1.1 augustss
342 1.208 drochner const struct usbd_pipe_methods uhci_device_ctrl_methods = {
343 1.264.4.55 skrll .upm_init = uhci_device_ctrl_init,
344 1.264.4.55 skrll .upm_fini = uhci_device_ctrl_fini,
345 1.264.4.5 skrll .upm_transfer = uhci_device_ctrl_transfer,
346 1.264.4.5 skrll .upm_start = uhci_device_ctrl_start,
347 1.264.4.5 skrll .upm_abort = uhci_device_ctrl_abort,
348 1.264.4.5 skrll .upm_close = uhci_device_ctrl_close,
349 1.264.4.5 skrll .upm_cleartoggle = uhci_noop,
350 1.264.4.5 skrll .upm_done = uhci_device_ctrl_done,
351 1.1 augustss };
352 1.1 augustss
353 1.208 drochner const struct usbd_pipe_methods uhci_device_intr_methods = {
354 1.264.4.55 skrll .upm_init = uhci_device_intr_init,
355 1.264.4.55 skrll .upm_fini = uhci_device_intr_fini,
356 1.264.4.5 skrll .upm_transfer = uhci_device_intr_transfer,
357 1.264.4.5 skrll .upm_start = uhci_device_intr_start,
358 1.264.4.5 skrll .upm_abort = uhci_device_intr_abort,
359 1.264.4.5 skrll .upm_close = uhci_device_intr_close,
360 1.264.4.5 skrll .upm_cleartoggle = uhci_device_clear_toggle,
361 1.264.4.5 skrll .upm_done = uhci_device_intr_done,
362 1.1 augustss };
363 1.1 augustss
364 1.208 drochner const struct usbd_pipe_methods uhci_device_bulk_methods = {
365 1.264.4.55 skrll .upm_init = uhci_device_bulk_init,
366 1.264.4.55 skrll .upm_fini = uhci_device_bulk_fini,
367 1.264.4.5 skrll .upm_transfer = uhci_device_bulk_transfer,
368 1.264.4.5 skrll .upm_start = uhci_device_bulk_start,
369 1.264.4.5 skrll .upm_abort = uhci_device_bulk_abort,
370 1.264.4.5 skrll .upm_close = uhci_device_bulk_close,
371 1.264.4.5 skrll .upm_cleartoggle = uhci_device_clear_toggle,
372 1.264.4.5 skrll .upm_done = uhci_device_bulk_done,
373 1.1 augustss };
374 1.1 augustss
375 1.208 drochner const struct usbd_pipe_methods uhci_device_isoc_methods = {
376 1.264.4.55 skrll .upm_init = uhci_device_isoc_init,
377 1.264.4.55 skrll .upm_fini = uhci_device_isoc_fini,
378 1.264.4.5 skrll .upm_transfer = uhci_device_isoc_transfer,
379 1.264.4.5 skrll .upm_start = uhci_device_isoc_start,
380 1.264.4.5 skrll .upm_abort = uhci_device_isoc_abort,
381 1.264.4.5 skrll .upm_close = uhci_device_isoc_close,
382 1.264.4.5 skrll .upm_cleartoggle = uhci_noop,
383 1.264.4.5 skrll .upm_done = uhci_device_isoc_done,
384 1.16 augustss };
385 1.16 augustss
386 1.264.4.56 skrll #define uhci_add_intr_list(sc, ux) \
387 1.264.4.41 skrll TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ux), ux_list)
388 1.264.4.56 skrll #define uhci_del_intr_list(sc, ux) \
389 1.169 augustss do { \
390 1.264.4.41 skrll TAILQ_REMOVE(&(sc)->sc_intrhead, (ux), ux_list); \
391 1.264.4.41 skrll (ux)->ux_list.tqe_prev = NULL; \
392 1.169 augustss } while (0)
393 1.264.4.56 skrll #define uhci_active_intr_list(ux) ((ux)->ux_list.tqe_prev != NULL)
394 1.92 augustss
395 1.240 jakllsch static inline uhci_soft_qh_t *
396 1.119 augustss uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh)
397 1.92 augustss {
398 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
399 1.264.4.21 skrll DPRINTFN(15, "pqh=%p sqh=%p", pqh, sqh, 0, 0);
400 1.92 augustss
401 1.92 augustss for (; pqh->hlink != sqh; pqh = pqh->hlink) {
402 1.152 augustss #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG)
403 1.223 bouyer usb_syncmem(&pqh->dma,
404 1.223 bouyer pqh->offs + offsetof(uhci_qh_t, qh_hlink),
405 1.223 bouyer sizeof(pqh->qh.qh_hlink),
406 1.223 bouyer BUS_DMASYNC_POSTWRITE);
407 1.92 augustss if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) {
408 1.102 augustss printf("uhci_find_prev_qh: QH not found\n");
409 1.264.4.13 skrll return NULL;
410 1.92 augustss }
411 1.92 augustss #endif
412 1.92 augustss }
413 1.264.4.13 skrll return pqh;
414 1.92 augustss }
415 1.92 augustss
416 1.1 augustss void
417 1.142 augustss uhci_globalreset(uhci_softc_t *sc)
418 1.1 augustss {
419 1.1 augustss UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */
420 1.20 augustss usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */
421 1.1 augustss UHCICMD(sc, 0); /* do nothing */
422 1.1 augustss }
423 1.1 augustss
424 1.264.4.14 skrll int
425 1.119 augustss uhci_init(uhci_softc_t *sc)
426 1.1 augustss {
427 1.63 augustss usbd_status err;
428 1.1 augustss int i, j;
429 1.123 augustss uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh;
430 1.1 augustss uhci_soft_td_t *std;
431 1.1 augustss
432 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
433 1.1 augustss
434 1.67 augustss #ifdef UHCI_DEBUG
435 1.92 augustss thesc = sc;
436 1.92 augustss
437 1.264.4.43 skrll if (uhcidebug >= 2)
438 1.1 augustss uhci_dumpregs(sc);
439 1.1 augustss #endif
440 1.1 augustss
441 1.219 jmcneill sc->sc_suspend = PWR_RESUME;
442 1.219 jmcneill
443 1.1 augustss UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */
444 1.142 augustss uhci_globalreset(sc); /* reset the controller */
445 1.142 augustss uhci_reset(sc);
446 1.24 augustss
447 1.1 augustss /* Allocate and initialize real frame array. */
448 1.152 augustss err = usb_allocmem(&sc->sc_bus,
449 1.264.4.49 skrll UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t),
450 1.264.4.49 skrll UHCI_FRAMELIST_ALIGN, &sc->sc_dma);
451 1.63 augustss if (err)
452 1.264.4.13 skrll return err;
453 1.159 augustss sc->sc_pframes = KERNADDR(&sc->sc_dma, 0);
454 1.1 augustss UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */
455 1.160 augustss UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/
456 1.1 augustss
457 1.264.4.55 skrll /* Initialise mutex early for uhci_alloc_* */
458 1.264.4.55 skrll mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
459 1.264.4.55 skrll mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB);
460 1.264.4.55 skrll
461 1.152 augustss /*
462 1.123 augustss * Allocate a TD, inactive, that hangs from the last QH.
463 1.123 augustss * This is to avoid a bug in the PIIX that makes it run berserk
464 1.123 augustss * otherwise.
465 1.123 augustss */
466 1.123 augustss std = uhci_alloc_std(sc);
467 1.123 augustss if (std == NULL)
468 1.264.4.14 skrll return ENOMEM;
469 1.123 augustss std->link.std = NULL;
470 1.123 augustss std->td.td_link = htole32(UHCI_PTR_T);
471 1.123 augustss std->td.td_status = htole32(0); /* inactive */
472 1.123 augustss std->td.td_token = htole32(0);
473 1.123 augustss std->td.td_buffer = htole32(0);
474 1.223 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
475 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
476 1.123 augustss
477 1.123 augustss /* Allocate the dummy QH marking the end and used for looping the QHs.*/
478 1.123 augustss lsqh = uhci_alloc_sqh(sc);
479 1.123 augustss if (lsqh == NULL)
480 1.264.4.55 skrll goto fail1;
481 1.123 augustss lsqh->hlink = NULL;
482 1.123 augustss lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */
483 1.123 augustss lsqh->elink = std;
484 1.123 augustss lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD);
485 1.123 augustss sc->sc_last_qh = lsqh;
486 1.223 bouyer usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh),
487 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
488 1.123 augustss
489 1.1 augustss /* Allocate the dummy QH where bulk traffic will be queued. */
490 1.1 augustss bsqh = uhci_alloc_sqh(sc);
491 1.63 augustss if (bsqh == NULL)
492 1.264.4.55 skrll goto fail2;
493 1.123 augustss bsqh->hlink = lsqh;
494 1.123 augustss bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH);
495 1.121 augustss bsqh->elink = NULL;
496 1.88 tsutsui bsqh->qh.qh_elink = htole32(UHCI_PTR_T);
497 1.1 augustss sc->sc_bulk_start = sc->sc_bulk_end = bsqh;
498 1.223 bouyer usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh),
499 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
500 1.1 augustss
501 1.123 augustss /* Allocate dummy QH where high speed control traffic will be queued. */
502 1.123 augustss chsqh = uhci_alloc_sqh(sc);
503 1.123 augustss if (chsqh == NULL)
504 1.264.4.55 skrll goto fail3;
505 1.123 augustss chsqh->hlink = bsqh;
506 1.123 augustss chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH);
507 1.123 augustss chsqh->elink = NULL;
508 1.123 augustss chsqh->qh.qh_elink = htole32(UHCI_PTR_T);
509 1.123 augustss sc->sc_hctl_start = sc->sc_hctl_end = chsqh;
510 1.223 bouyer usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh),
511 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
512 1.123 augustss
513 1.123 augustss /* Allocate dummy QH where control traffic will be queued. */
514 1.123 augustss clsqh = uhci_alloc_sqh(sc);
515 1.123 augustss if (clsqh == NULL)
516 1.264.4.55 skrll goto fail4;
517 1.220 bouyer clsqh->hlink = chsqh;
518 1.123 augustss clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH);
519 1.123 augustss clsqh->elink = NULL;
520 1.123 augustss clsqh->qh.qh_elink = htole32(UHCI_PTR_T);
521 1.123 augustss sc->sc_lctl_start = sc->sc_lctl_end = clsqh;
522 1.223 bouyer usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh),
523 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
524 1.1 augustss
525 1.152 augustss /*
526 1.1 augustss * Make all (virtual) frame list pointers point to the interrupt
527 1.1 augustss * queue heads and the interrupt queue heads at the control
528 1.1 augustss * queue head and point the physical frame list to the virtual.
529 1.1 augustss */
530 1.264.4.24 skrll for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
531 1.1 augustss std = uhci_alloc_std(sc);
532 1.1 augustss sqh = uhci_alloc_sqh(sc);
533 1.67 augustss if (std == NULL || sqh == NULL)
534 1.264.4.13 skrll return USBD_NOMEM;
535 1.42 augustss std->link.sqh = sqh;
536 1.121 augustss std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH);
537 1.88 tsutsui std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */
538 1.88 tsutsui std->td.td_token = htole32(0);
539 1.88 tsutsui std->td.td_buffer = htole32(0);
540 1.223 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
541 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
542 1.123 augustss sqh->hlink = clsqh;
543 1.123 augustss sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH);
544 1.121 augustss sqh->elink = NULL;
545 1.88 tsutsui sqh->qh.qh_elink = htole32(UHCI_PTR_T);
546 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
547 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
548 1.1 augustss sc->sc_vframes[i].htd = std;
549 1.1 augustss sc->sc_vframes[i].etd = std;
550 1.1 augustss sc->sc_vframes[i].hqh = sqh;
551 1.1 augustss sc->sc_vframes[i].eqh = sqh;
552 1.152 augustss for (j = i;
553 1.152 augustss j < UHCI_FRAMELIST_COUNT;
554 1.1 augustss j += UHCI_VFRAMELIST_COUNT)
555 1.88 tsutsui sc->sc_pframes[j] = htole32(std->physaddr);
556 1.1 augustss }
557 1.223 bouyer usb_syncmem(&sc->sc_dma, 0,
558 1.223 bouyer UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t),
559 1.223 bouyer BUS_DMASYNC_PREWRITE);
560 1.223 bouyer
561 1.1 augustss
562 1.264.4.39 skrll TAILQ_INIT(&sc->sc_intrhead);
563 1.1 augustss
564 1.253 christos sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0,
565 1.253 christos "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL);
566 1.76 augustss
567 1.248 mrg callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE);
568 1.248 mrg
569 1.248 mrg cv_init(&sc->sc_softwake_cv, "uhciab");
570 1.96 augustss
571 1.1 augustss /* Set up the bus struct. */
572 1.264.4.7 skrll sc->sc_bus.ub_methods = &uhci_bus_methods;
573 1.264.4.7 skrll sc->sc_bus.ub_pipesize = sizeof(struct uhci_pipe);
574 1.264.4.7 skrll sc->sc_bus.ub_usedma = true;
575 1.1 augustss
576 1.190 augustss UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */
577 1.190 augustss
578 1.264.4.27 skrll DPRINTF("Enabling...", 0, 0, 0, 0);
579 1.225 bouyer
580 1.264.4.24 skrll err = uhci_run(sc, 1, 0); /* and here we go... */
581 1.152 augustss UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE |
582 1.1 augustss UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */
583 1.225 bouyer return err;
584 1.264.4.55 skrll
585 1.264.4.55 skrll fail4:
586 1.264.4.55 skrll uhci_free_sqh(sc, chsqh);
587 1.264.4.55 skrll fail3:
588 1.264.4.55 skrll uhci_free_sqh(sc, lsqh);
589 1.264.4.55 skrll fail2:
590 1.264.4.55 skrll uhci_free_sqh(sc, lsqh);
591 1.264.4.55 skrll fail1:
592 1.264.4.55 skrll uhci_free_std(sc, std);
593 1.264.4.55 skrll
594 1.264.4.55 skrll return ENOMEM;
595 1.53 augustss }
596 1.53 augustss
597 1.53 augustss int
598 1.215 dyoung uhci_activate(device_t self, enum devact act)
599 1.53 augustss {
600 1.215 dyoung struct uhci_softc *sc = device_private(self);
601 1.53 augustss
602 1.53 augustss switch (act) {
603 1.53 augustss case DVACT_DEACTIVATE:
604 1.210 kiyohara sc->sc_dying = 1;
605 1.230 dyoung return 0;
606 1.230 dyoung default:
607 1.230 dyoung return EOPNOTSUPP;
608 1.53 augustss }
609 1.53 augustss }
610 1.53 augustss
611 1.215 dyoung void
612 1.215 dyoung uhci_childdet(device_t self, device_t child)
613 1.215 dyoung {
614 1.215 dyoung struct uhci_softc *sc = device_private(self);
615 1.215 dyoung
616 1.215 dyoung KASSERT(sc->sc_child == child);
617 1.215 dyoung sc->sc_child = NULL;
618 1.215 dyoung }
619 1.215 dyoung
620 1.53 augustss int
621 1.119 augustss uhci_detach(struct uhci_softc *sc, int flags)
622 1.53 augustss {
623 1.53 augustss int rv = 0;
624 1.53 augustss
625 1.53 augustss if (sc->sc_child != NULL)
626 1.53 augustss rv = config_detach(sc->sc_child, flags);
627 1.152 augustss
628 1.53 augustss if (rv != 0)
629 1.264.4.13 skrll return rv;
630 1.53 augustss
631 1.226 ad callout_halt(&sc->sc_poll_handle, NULL);
632 1.226 ad callout_destroy(&sc->sc_poll_handle);
633 1.226 ad
634 1.248 mrg cv_destroy(&sc->sc_softwake_cv);
635 1.248 mrg
636 1.248 mrg mutex_destroy(&sc->sc_lock);
637 1.248 mrg mutex_destroy(&sc->sc_intr_lock);
638 1.248 mrg
639 1.254 christos pool_cache_destroy(sc->sc_xferpool);
640 1.254 christos
641 1.76 augustss /* XXX free other data structures XXX */
642 1.53 augustss
643 1.264.4.13 skrll return rv;
644 1.1 augustss }
645 1.1 augustss
646 1.264.4.25 skrll struct usbd_xfer *
647 1.264.4.36 skrll uhci_allocx(struct usbd_bus *bus, unsigned int nframes)
648 1.76 augustss {
649 1.264.4.37 skrll struct uhci_softc *sc = UHCI_BUS2SC(bus);
650 1.264.4.25 skrll struct usbd_xfer *xfer;
651 1.76 augustss
652 1.253 christos xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT);
653 1.92 augustss if (xfer != NULL) {
654 1.253 christos memset(xfer, 0, sizeof(struct uhci_xfer));
655 1.264.4.31 skrll
656 1.92 augustss #ifdef DIAGNOSTIC
657 1.264.4.40 skrll struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
658 1.264.4.41 skrll uxfer->ux_isdone = true;
659 1.264.4.7 skrll xfer->ux_state = XFER_BUSY;
660 1.92 augustss #endif
661 1.92 augustss }
662 1.264.4.13 skrll return xfer;
663 1.76 augustss }
664 1.76 augustss
665 1.76 augustss void
666 1.264.4.25 skrll uhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer)
667 1.76 augustss {
668 1.264.4.37 skrll struct uhci_softc *sc = UHCI_BUS2SC(bus);
669 1.264.4.37 skrll struct uhci_xfer *uxfer __diagused = UHCI_XFER2UXFER(xfer);
670 1.76 augustss
671 1.264.4.31 skrll KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer,
672 1.264.4.31 skrll xfer->ux_state);
673 1.264.4.41 skrll KASSERTMSG(uxfer->ux_isdone, "xfer %p not done\n", xfer);
674 1.93 augustss #ifdef DIAGNOSTIC
675 1.264.4.7 skrll xfer->ux_state = XFER_FREE;
676 1.93 augustss #endif
677 1.253 christos pool_cache_put(sc->sc_xferpool, xfer);
678 1.48 augustss }
679 1.48 augustss
680 1.248 mrg Static void
681 1.248 mrg uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock)
682 1.248 mrg {
683 1.264.4.37 skrll struct uhci_softc *sc = UHCI_BUS2SC(bus);
684 1.248 mrg
685 1.248 mrg *lock = &sc->sc_lock;
686 1.248 mrg }
687 1.248 mrg
688 1.248 mrg
689 1.72 augustss /*
690 1.212 jmcneill * Handle suspend/resume.
691 1.212 jmcneill *
692 1.212 jmcneill * We need to switch to polling mode here, because this routine is
693 1.212 jmcneill * called from an interrupt context. This is all right since we
694 1.212 jmcneill * are almost suspended anyway.
695 1.72 augustss */
696 1.212 jmcneill bool
697 1.232 dyoung uhci_resume(device_t dv, const pmf_qual_t *qual)
698 1.72 augustss {
699 1.212 jmcneill uhci_softc_t *sc = device_private(dv);
700 1.212 jmcneill int cmd;
701 1.72 augustss
702 1.248 mrg mutex_spin_enter(&sc->sc_intr_lock);
703 1.193 augustss
704 1.212 jmcneill cmd = UREAD2(sc, UHCI_CMD);
705 1.264.4.7 skrll sc->sc_bus.ub_usepolling++;
706 1.214 smb UWRITE2(sc, UHCI_INTR, 0);
707 1.214 smb uhci_globalreset(sc);
708 1.214 smb uhci_reset(sc);
709 1.212 jmcneill if (cmd & UHCI_CMD_RS)
710 1.249 drochner uhci_run(sc, 0, 1);
711 1.212 jmcneill
712 1.212 jmcneill /* restore saved state */
713 1.212 jmcneill UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0));
714 1.212 jmcneill UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum);
715 1.212 jmcneill UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof);
716 1.212 jmcneill
717 1.212 jmcneill UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */
718 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock);
719 1.212 jmcneill UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */
720 1.212 jmcneill UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE |
721 1.212 jmcneill UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE);
722 1.214 smb UHCICMD(sc, UHCI_CMD_MAXP);
723 1.249 drochner uhci_run(sc, 1, 1); /* and start traffic again */
724 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock);
725 1.264.4.7 skrll sc->sc_bus.ub_usepolling--;
726 1.212 jmcneill if (sc->sc_intr_xfer != NULL)
727 1.234 dyoung callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub,
728 1.212 jmcneill sc->sc_intr_xfer);
729 1.212 jmcneill #ifdef UHCI_DEBUG
730 1.264.4.43 skrll if (uhcidebug >= 2)
731 1.212 jmcneill uhci_dumpregs(sc);
732 1.212 jmcneill #endif
733 1.212 jmcneill
734 1.219 jmcneill sc->sc_suspend = PWR_RESUME;
735 1.248 mrg mutex_spin_exit(&sc->sc_intr_lock);
736 1.212 jmcneill
737 1.212 jmcneill return true;
738 1.72 augustss }
739 1.72 augustss
740 1.212 jmcneill bool
741 1.232 dyoung uhci_suspend(device_t dv, const pmf_qual_t *qual)
742 1.30 augustss {
743 1.212 jmcneill uhci_softc_t *sc = device_private(dv);
744 1.30 augustss int cmd;
745 1.30 augustss
746 1.248 mrg mutex_spin_enter(&sc->sc_intr_lock);
747 1.212 jmcneill
748 1.30 augustss cmd = UREAD2(sc, UHCI_CMD);
749 1.30 augustss
750 1.212 jmcneill #ifdef UHCI_DEBUG
751 1.264.4.43 skrll if (uhcidebug >= 2)
752 1.212 jmcneill uhci_dumpregs(sc);
753 1.212 jmcneill #endif
754 1.212 jmcneill if (sc->sc_intr_xfer != NULL)
755 1.234 dyoung callout_stop(&sc->sc_poll_handle);
756 1.219 jmcneill sc->sc_suspend = PWR_SUSPEND;
757 1.264.4.7 skrll sc->sc_bus.ub_usepolling++;
758 1.219 jmcneill
759 1.249 drochner uhci_run(sc, 0, 1); /* stop the controller */
760 1.212 jmcneill cmd &= ~UHCI_CMD_RS;
761 1.212 jmcneill
762 1.212 jmcneill /* save some state if BIOS doesn't */
763 1.212 jmcneill sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM);
764 1.212 jmcneill sc->sc_saved_sof = UREAD1(sc, UHCI_SOF);
765 1.212 jmcneill
766 1.212 jmcneill UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */
767 1.30 augustss
768 1.212 jmcneill UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */
769 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock);
770 1.264.4.7 skrll sc->sc_bus.ub_usepolling--;
771 1.86 augustss
772 1.248 mrg mutex_spin_exit(&sc->sc_intr_lock);
773 1.212 jmcneill
774 1.212 jmcneill return true;
775 1.30 augustss }
776 1.30 augustss
777 1.59 augustss #ifdef UHCI_DEBUG
778 1.101 augustss Static void
779 1.119 augustss uhci_dumpregs(uhci_softc_t *sc)
780 1.1 augustss {
781 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
782 1.264.4.27 skrll DPRINTF("cmd =%04x sts =%04x intr =%04x frnum =%04x",
783 1.264.4.21 skrll UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS),
784 1.264.4.21 skrll UREAD2(sc, UHCI_INTR), UREAD2(sc, UHCI_FRNUM));
785 1.264.4.27 skrll DPRINTF("sof =%04x portsc1=%04x portsc2=%04x flbase=%08x",
786 1.264.4.21 skrll UREAD1(sc, UHCI_SOF), UREAD2(sc, UHCI_PORTSC1),
787 1.264.4.21 skrll UREAD2(sc, UHCI_PORTSC2), UREAD4(sc, UHCI_FLBASEADDR));
788 1.1 augustss }
789 1.1 augustss
790 1.1 augustss void
791 1.119 augustss uhci_dump_td(uhci_soft_td_t *p)
792 1.1 augustss {
793 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
794 1.250 christos
795 1.223 bouyer usb_syncmem(&p->dma, p->offs, sizeof(p->td),
796 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
797 1.264.4.21 skrll
798 1.264.4.44 skrll DPRINTF("TD(%p) at 0x%08x", p, p->physaddr, 0, 0);
799 1.264.4.27 skrll DPRINTF(" link=0x%08x status=0x%08x "
800 1.264.4.21 skrll "token=0x%08x buffer=0x%08x",
801 1.264.4.21 skrll le32toh(p->td.td_link),
802 1.264.4.21 skrll le32toh(p->td.td_status),
803 1.264.4.21 skrll le32toh(p->td.td_token),
804 1.264.4.21 skrll le32toh(p->td.td_buffer));
805 1.264.4.21 skrll
806 1.264.4.27 skrll DPRINTF("bitstuff=%d crcto =%d nak =%d babble =%d",
807 1.264.4.21 skrll !!(le32toh(p->td.td_status) & UHCI_TD_BITSTUFF),
808 1.264.4.21 skrll !!(le32toh(p->td.td_status) & UHCI_TD_CRCTO),
809 1.264.4.21 skrll !!(le32toh(p->td.td_status) & UHCI_TD_NAK),
810 1.264.4.21 skrll !!(le32toh(p->td.td_status) & UHCI_TD_BABBLE));
811 1.264.4.27 skrll DPRINTF("dbuffer =%d stalled =%d active =%d ioc =%d",
812 1.264.4.21 skrll !!(le32toh(p->td.td_status) & UHCI_TD_DBUFFER),
813 1.264.4.21 skrll !!(le32toh(p->td.td_status) & UHCI_TD_STALLED),
814 1.264.4.21 skrll !!(le32toh(p->td.td_status) & UHCI_TD_ACTIVE),
815 1.264.4.21 skrll !!(le32toh(p->td.td_status) & UHCI_TD_IOC));
816 1.264.4.27 skrll DPRINTF("ios =%d ls =%d spd =%d",
817 1.264.4.21 skrll !!(le32toh(p->td.td_status) & UHCI_TD_IOS),
818 1.264.4.21 skrll !!(le32toh(p->td.td_status) & UHCI_TD_LS),
819 1.264.4.21 skrll !!(le32toh(p->td.td_status) & UHCI_TD_SPD), 0);
820 1.264.4.27 skrll DPRINTF("errcnt =%d actlen =%d pid=%02x",
821 1.264.4.21 skrll UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)),
822 1.264.4.21 skrll UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)),
823 1.264.4.21 skrll UHCI_TD_GET_PID(le32toh(p->td.td_token)), 0);
824 1.264.4.27 skrll DPRINTF("addr=%d endpt=%d D=%d maxlen=%d,",
825 1.264.4.21 skrll UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)),
826 1.264.4.21 skrll UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)),
827 1.264.4.21 skrll UHCI_TD_GET_DT(le32toh(p->td.td_token)),
828 1.264.4.21 skrll UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token)));
829 1.1 augustss }
830 1.1 augustss
831 1.1 augustss void
832 1.119 augustss uhci_dump_qh(uhci_soft_qh_t *sqh)
833 1.1 augustss {
834 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
835 1.264.4.21 skrll
836 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
837 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
838 1.264.4.21 skrll
839 1.264.4.44 skrll DPRINTF("QH(%p) at 0x%08x: hlink=%08x elink=%08x", sqh,
840 1.88 tsutsui (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink),
841 1.264.4.21 skrll le32toh(sqh->qh.qh_elink));
842 1.264.4.21 skrll
843 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD);
844 1.1 augustss }
845 1.1 augustss
846 1.13 augustss
847 1.110 augustss #if 1
848 1.1 augustss void
849 1.119 augustss uhci_dump(void)
850 1.1 augustss {
851 1.110 augustss uhci_dump_all(thesc);
852 1.110 augustss }
853 1.110 augustss #endif
854 1.1 augustss
855 1.110 augustss void
856 1.119 augustss uhci_dump_all(uhci_softc_t *sc)
857 1.110 augustss {
858 1.1 augustss uhci_dumpregs(sc);
859 1.110 augustss /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/
860 1.261 skrll uhci_dump_qhs(sc->sc_lctl_start);
861 1.1 augustss }
862 1.1 augustss
863 1.67 augustss
864 1.67 augustss void
865 1.119 augustss uhci_dump_qhs(uhci_soft_qh_t *sqh)
866 1.67 augustss {
867 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
868 1.264.4.21 skrll
869 1.67 augustss uhci_dump_qh(sqh);
870 1.67 augustss
871 1.264.4.18 skrll /*
872 1.264.4.18 skrll * uhci_dump_qhs displays all the QHs and TDs from the given QH onwards
873 1.67 augustss * Traverses sideways first, then down.
874 1.67 augustss *
875 1.67 augustss * QH1
876 1.67 augustss * QH2
877 1.67 augustss * No QH
878 1.67 augustss * TD2.1
879 1.67 augustss * TD2.2
880 1.67 augustss * TD1.1
881 1.67 augustss * etc.
882 1.67 augustss *
883 1.67 augustss * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1.
884 1.67 augustss */
885 1.67 augustss
886 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
887 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
888 1.88 tsutsui if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T))
889 1.67 augustss uhci_dump_qhs(sqh->hlink);
890 1.67 augustss else
891 1.264.4.27 skrll DPRINTF("No QH", 0, 0, 0, 0);
892 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD);
893 1.67 augustss
894 1.88 tsutsui if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T))
895 1.67 augustss uhci_dump_tds(sqh->elink);
896 1.67 augustss else
897 1.264.4.27 skrll DPRINTF("No QH", 0, 0, 0, 0);
898 1.67 augustss }
899 1.67 augustss
900 1.1 augustss void
901 1.119 augustss uhci_dump_tds(uhci_soft_td_t *std)
902 1.1 augustss {
903 1.67 augustss uhci_soft_td_t *td;
904 1.223 bouyer int stop;
905 1.67 augustss
906 1.264.4.24 skrll for (td = std; td != NULL; td = td->link.std) {
907 1.67 augustss uhci_dump_td(td);
908 1.1 augustss
909 1.264.4.18 skrll /*
910 1.264.4.18 skrll * Check whether the link pointer in this TD marks
911 1.67 augustss * the link pointer as end of queue. This avoids
912 1.67 augustss * printing the free list in case the queue/TD has
913 1.67 augustss * already been moved there (seatbelt).
914 1.67 augustss */
915 1.223 bouyer usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link),
916 1.223 bouyer sizeof(td->td.td_link),
917 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
918 1.223 bouyer stop = (le32toh(td->td.td_link) & UHCI_PTR_T ||
919 1.223 bouyer le32toh(td->td.td_link) == 0);
920 1.223 bouyer usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link),
921 1.223 bouyer sizeof(td->td.td_link), BUS_DMASYNC_PREREAD);
922 1.223 bouyer if (stop)
923 1.67 augustss break;
924 1.67 augustss }
925 1.1 augustss }
926 1.92 augustss
927 1.101 augustss Static void
928 1.264.4.40 skrll uhci_dump_ii(struct uhci_xfer *ux)
929 1.92 augustss {
930 1.264.4.25 skrll struct usbd_pipe *pipe;
931 1.95 augustss usb_endpoint_descriptor_t *ed;
932 1.264.4.25 skrll struct usbd_device *dev;
933 1.152 augustss
934 1.264.4.39 skrll if (ux == NULL) {
935 1.264.4.39 skrll printf("ux NULL\n");
936 1.264.4.2 skrll return;
937 1.264.4.2 skrll }
938 1.264.4.41 skrll pipe = ux->ux_xfer.ux_pipe;
939 1.264.4.2 skrll if (pipe == NULL) {
940 1.264.4.41 skrll printf("ux %p: done=%d pipe=NULL\n", ux, ux->ux_isdone);
941 1.264.4.2 skrll return;
942 1.139 augustss }
943 1.264.4.7 skrll if (pipe->up_endpoint == NULL) {
944 1.264.4.40 skrll printf("ux %p: done=%d pipe=%p pipe->up_endpoint=NULL\n",
945 1.264.4.41 skrll ux, ux->ux_isdone, pipe);
946 1.264.4.2 skrll return;
947 1.139 augustss }
948 1.264.4.7 skrll if (pipe->up_dev == NULL) {
949 1.264.4.40 skrll printf("ux %p: done=%d pipe=%p pipe->up_dev=NULL\n",
950 1.264.4.41 skrll ux, ux->ux_isdone, pipe);
951 1.264.4.2 skrll return;
952 1.95 augustss }
953 1.264.4.7 skrll ed = pipe->up_endpoint->ue_edesc;
954 1.264.4.7 skrll dev = pipe->up_dev;
955 1.264.4.40 skrll printf("ux %p: done=%d dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n",
956 1.264.4.41 skrll ux, ux->ux_isdone, dev,
957 1.264.4.7 skrll UGETW(dev->ud_ddesc.idVendor),
958 1.264.4.7 skrll UGETW(dev->ud_ddesc.idProduct),
959 1.264.4.7 skrll dev->ud_addr, pipe,
960 1.92 augustss ed->bEndpointAddress, ed->bmAttributes);
961 1.92 augustss }
962 1.92 augustss
963 1.120 augustss void uhci_dump_iis(struct uhci_softc *sc);
964 1.92 augustss void
965 1.119 augustss uhci_dump_iis(struct uhci_softc *sc)
966 1.92 augustss {
967 1.264.4.40 skrll struct uhci_xfer *ux;
968 1.92 augustss
969 1.264.4.39 skrll printf("interrupt list:\n");
970 1.264.4.60 skrll TAILQ_FOREACH(ux, &sc->sc_intrhead, ux_list)
971 1.264.4.39 skrll uhci_dump_ii(ux);
972 1.92 augustss }
973 1.92 augustss
974 1.120 augustss void iidump(void);
975 1.119 augustss void iidump(void) { uhci_dump_iis(thesc); }
976 1.92 augustss
977 1.1 augustss #endif
978 1.1 augustss
979 1.1 augustss /*
980 1.1 augustss * This routine is executed periodically and simulates interrupts
981 1.1 augustss * from the root controller interrupt pipe for port status change.
982 1.1 augustss */
983 1.1 augustss void
984 1.119 augustss uhci_poll_hub(void *addr)
985 1.1 augustss {
986 1.264.4.25 skrll struct usbd_xfer *xfer = addr;
987 1.264.4.25 skrll struct usbd_pipe *pipe = xfer->ux_pipe;
988 1.227 martin uhci_softc_t *sc;
989 1.1 augustss u_char *p;
990 1.1 augustss
991 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
992 1.1 augustss
993 1.264.4.7 skrll if (__predict_false(pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL))
994 1.228 martin return; /* device has detached */
995 1.264.4.37 skrll sc = UHCI_PIPE2SC(pipe);
996 1.234 dyoung callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer);
997 1.41 augustss
998 1.264.4.7 skrll p = xfer->ux_buf;
999 1.1 augustss p[0] = 0;
1000 1.1 augustss if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC))
1001 1.1 augustss p[0] |= 1<<1;
1002 1.1 augustss if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC))
1003 1.1 augustss p[0] |= 1<<2;
1004 1.41 augustss if (p[0] == 0)
1005 1.41 augustss /* No change, try again in a while */
1006 1.41 augustss return;
1007 1.41 augustss
1008 1.264.4.7 skrll xfer->ux_actlen = 1;
1009 1.264.4.7 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1010 1.248 mrg mutex_enter(&sc->sc_lock);
1011 1.63 augustss usb_transfer_complete(xfer);
1012 1.248 mrg mutex_exit(&sc->sc_lock);
1013 1.41 augustss }
1014 1.41 augustss
1015 1.41 augustss void
1016 1.264.4.25 skrll uhci_root_intr_done(struct usbd_xfer *xfer)
1017 1.84 augustss {
1018 1.84 augustss }
1019 1.84 augustss
1020 1.123 augustss /*
1021 1.123 augustss * Let the last QH loop back to the high speed control transfer QH.
1022 1.123 augustss * This is what intel calls "bandwidth reclamation" and improves
1023 1.123 augustss * USB performance a lot for some devices.
1024 1.123 augustss * If we are already looping, just count it.
1025 1.123 augustss */
1026 1.1 augustss void
1027 1.264.4.17 skrll uhci_add_loop(uhci_softc_t *sc)
1028 1.264.4.17 skrll {
1029 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1030 1.264.4.25 skrll
1031 1.125 augustss #ifdef UHCI_DEBUG
1032 1.125 augustss if (uhcinoloop)
1033 1.125 augustss return;
1034 1.125 augustss #endif
1035 1.123 augustss if (++sc->sc_loops == 1) {
1036 1.264.4.21 skrll DPRINTFN(5, "add loop", 0, 0, 0, 0);
1037 1.123 augustss /* Note, we don't loop back the soft pointer. */
1038 1.152 augustss sc->sc_last_qh->qh.qh_hlink =
1039 1.123 augustss htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH);
1040 1.223 bouyer usb_syncmem(&sc->sc_last_qh->dma,
1041 1.223 bouyer sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink),
1042 1.223 bouyer sizeof(sc->sc_last_qh->qh.qh_hlink),
1043 1.223 bouyer BUS_DMASYNC_PREWRITE);
1044 1.123 augustss }
1045 1.123 augustss }
1046 1.123 augustss
1047 1.123 augustss void
1048 1.264.4.17 skrll uhci_rem_loop(uhci_softc_t *sc)
1049 1.264.4.17 skrll {
1050 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1051 1.264.4.21 skrll
1052 1.125 augustss #ifdef UHCI_DEBUG
1053 1.125 augustss if (uhcinoloop)
1054 1.125 augustss return;
1055 1.125 augustss #endif
1056 1.123 augustss if (--sc->sc_loops == 0) {
1057 1.264.4.21 skrll DPRINTFN(5, "remove loop", 0, 0, 0, 0);
1058 1.123 augustss sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T);
1059 1.223 bouyer usb_syncmem(&sc->sc_last_qh->dma,
1060 1.223 bouyer sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink),
1061 1.223 bouyer sizeof(sc->sc_last_qh->qh.qh_hlink),
1062 1.223 bouyer BUS_DMASYNC_PREWRITE);
1063 1.123 augustss }
1064 1.123 augustss }
1065 1.123 augustss
1066 1.248 mrg /* Add high speed control QH, called with lock held. */
1067 1.123 augustss void
1068 1.123 augustss uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1069 1.1 augustss {
1070 1.42 augustss uhci_soft_qh_t *eqh;
1071 1.1 augustss
1072 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1073 1.264.4.21 skrll
1074 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
1075 1.248 mrg
1076 1.264.4.21 skrll DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
1077 1.123 augustss eqh = sc->sc_hctl_end;
1078 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1079 1.223 bouyer sizeof(eqh->qh.qh_hlink),
1080 1.223 bouyer BUS_DMASYNC_POSTWRITE);
1081 1.42 augustss sqh->hlink = eqh->hlink;
1082 1.42 augustss sqh->qh.qh_hlink = eqh->qh.qh_hlink;
1083 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1084 1.223 bouyer BUS_DMASYNC_PREWRITE);
1085 1.42 augustss eqh->hlink = sqh;
1086 1.121 augustss eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
1087 1.123 augustss sc->sc_hctl_end = sqh;
1088 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1089 1.223 bouyer sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
1090 1.125 augustss #ifdef UHCI_CTL_LOOP
1091 1.123 augustss uhci_add_loop(sc);
1092 1.125 augustss #endif
1093 1.1 augustss }
1094 1.1 augustss
1095 1.248 mrg /* Remove high speed control QH, called with lock held. */
1096 1.1 augustss void
1097 1.123 augustss uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1098 1.1 augustss {
1099 1.1 augustss uhci_soft_qh_t *pqh;
1100 1.256 tsutsui uint32_t elink;
1101 1.1 augustss
1102 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
1103 1.248 mrg
1104 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1105 1.264.4.21 skrll DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
1106 1.125 augustss #ifdef UHCI_CTL_LOOP
1107 1.123 augustss uhci_rem_loop(sc);
1108 1.125 augustss #endif
1109 1.124 augustss /*
1110 1.124 augustss * The T bit should be set in the elink of the QH so that the HC
1111 1.124 augustss * doesn't follow the pointer. This condition may fail if the
1112 1.124 augustss * the transferred packet was short so that the QH still points
1113 1.124 augustss * at the last used TD.
1114 1.124 augustss * In this case we set the T bit and wait a little for the HC
1115 1.124 augustss * to stop looking at the TD.
1116 1.223 bouyer * Note that if the TD chain is large enough, the controller
1117 1.223 bouyer * may still be looking at the chain at the end of this function.
1118 1.223 bouyer * uhci_free_std_chain() will make sure the controller stops
1119 1.223 bouyer * looking at it quickly, but until then we should not change
1120 1.223 bouyer * sqh->hlink.
1121 1.124 augustss */
1122 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
1123 1.223 bouyer sizeof(sqh->qh.qh_elink),
1124 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1125 1.256 tsutsui elink = le32toh(sqh->qh.qh_elink);
1126 1.256 tsutsui usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
1127 1.256 tsutsui sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD);
1128 1.256 tsutsui if (!(elink & UHCI_PTR_T)) {
1129 1.124 augustss sqh->qh.qh_elink = htole32(UHCI_PTR_T);
1130 1.223 bouyer usb_syncmem(&sqh->dma,
1131 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
1132 1.223 bouyer sizeof(sqh->qh.qh_elink),
1133 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1134 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1135 1.124 augustss }
1136 1.124 augustss
1137 1.123 augustss pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh);
1138 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
1139 1.223 bouyer sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
1140 1.152 augustss pqh->hlink = sqh->hlink;
1141 1.42 augustss pqh->qh.qh_hlink = sqh->qh.qh_hlink;
1142 1.223 bouyer usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
1143 1.223 bouyer sizeof(pqh->qh.qh_hlink),
1144 1.223 bouyer BUS_DMASYNC_PREWRITE);
1145 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1146 1.123 augustss if (sc->sc_hctl_end == sqh)
1147 1.123 augustss sc->sc_hctl_end = pqh;
1148 1.123 augustss }
1149 1.123 augustss
1150 1.248 mrg /* Add low speed control QH, called with lock held. */
1151 1.123 augustss void
1152 1.123 augustss uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1153 1.123 augustss {
1154 1.123 augustss uhci_soft_qh_t *eqh;
1155 1.123 augustss
1156 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
1157 1.248 mrg
1158 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1159 1.264.4.21 skrll DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
1160 1.264.4.21 skrll
1161 1.123 augustss eqh = sc->sc_lctl_end;
1162 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1163 1.223 bouyer sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
1164 1.152 augustss sqh->hlink = eqh->hlink;
1165 1.123 augustss sqh->qh.qh_hlink = eqh->qh.qh_hlink;
1166 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1167 1.223 bouyer BUS_DMASYNC_PREWRITE);
1168 1.152 augustss eqh->hlink = sqh;
1169 1.123 augustss eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
1170 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1171 1.223 bouyer sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
1172 1.123 augustss sc->sc_lctl_end = sqh;
1173 1.123 augustss }
1174 1.123 augustss
1175 1.248 mrg /* Remove low speed control QH, called with lock held. */
1176 1.123 augustss void
1177 1.123 augustss uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1178 1.123 augustss {
1179 1.123 augustss uhci_soft_qh_t *pqh;
1180 1.256 tsutsui uint32_t elink;
1181 1.123 augustss
1182 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
1183 1.248 mrg
1184 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1185 1.264.4.21 skrll DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
1186 1.264.4.21 skrll
1187 1.124 augustss /* See comment in uhci_remove_hs_ctrl() */
1188 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
1189 1.223 bouyer sizeof(sqh->qh.qh_elink),
1190 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1191 1.256 tsutsui elink = le32toh(sqh->qh.qh_elink);
1192 1.256 tsutsui usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
1193 1.256 tsutsui sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD);
1194 1.256 tsutsui if (!(elink & UHCI_PTR_T)) {
1195 1.124 augustss sqh->qh.qh_elink = htole32(UHCI_PTR_T);
1196 1.223 bouyer usb_syncmem(&sqh->dma,
1197 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
1198 1.223 bouyer sizeof(sqh->qh.qh_elink),
1199 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1200 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1201 1.124 augustss }
1202 1.123 augustss pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh);
1203 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
1204 1.223 bouyer sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
1205 1.152 augustss pqh->hlink = sqh->hlink;
1206 1.123 augustss pqh->qh.qh_hlink = sqh->qh.qh_hlink;
1207 1.223 bouyer usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
1208 1.223 bouyer sizeof(pqh->qh.qh_hlink),
1209 1.223 bouyer BUS_DMASYNC_PREWRITE);
1210 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1211 1.123 augustss if (sc->sc_lctl_end == sqh)
1212 1.123 augustss sc->sc_lctl_end = pqh;
1213 1.1 augustss }
1214 1.1 augustss
1215 1.248 mrg /* Add bulk QH, called with lock held. */
1216 1.1 augustss void
1217 1.119 augustss uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1218 1.1 augustss {
1219 1.42 augustss uhci_soft_qh_t *eqh;
1220 1.1 augustss
1221 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
1222 1.248 mrg
1223 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1224 1.264.4.21 skrll DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
1225 1.264.4.21 skrll
1226 1.42 augustss eqh = sc->sc_bulk_end;
1227 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1228 1.223 bouyer sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
1229 1.152 augustss sqh->hlink = eqh->hlink;
1230 1.42 augustss sqh->qh.qh_hlink = eqh->qh.qh_hlink;
1231 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1232 1.223 bouyer BUS_DMASYNC_PREWRITE);
1233 1.152 augustss eqh->hlink = sqh;
1234 1.121 augustss eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
1235 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1236 1.223 bouyer sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
1237 1.1 augustss sc->sc_bulk_end = sqh;
1238 1.123 augustss uhci_add_loop(sc);
1239 1.1 augustss }
1240 1.1 augustss
1241 1.248 mrg /* Remove bulk QH, called with lock held. */
1242 1.1 augustss void
1243 1.119 augustss uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1244 1.1 augustss {
1245 1.1 augustss uhci_soft_qh_t *pqh;
1246 1.1 augustss
1247 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
1248 1.248 mrg
1249 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1250 1.264.4.21 skrll DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
1251 1.264.4.21 skrll
1252 1.123 augustss uhci_rem_loop(sc);
1253 1.124 augustss /* See comment in uhci_remove_hs_ctrl() */
1254 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
1255 1.223 bouyer sizeof(sqh->qh.qh_elink),
1256 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1257 1.124 augustss if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) {
1258 1.124 augustss sqh->qh.qh_elink = htole32(UHCI_PTR_T);
1259 1.223 bouyer usb_syncmem(&sqh->dma,
1260 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
1261 1.223 bouyer sizeof(sqh->qh.qh_elink),
1262 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1263 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1264 1.124 augustss }
1265 1.92 augustss pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh);
1266 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
1267 1.223 bouyer sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
1268 1.42 augustss pqh->hlink = sqh->hlink;
1269 1.42 augustss pqh->qh.qh_hlink = sqh->qh.qh_hlink;
1270 1.223 bouyer usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
1271 1.223 bouyer sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
1272 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1273 1.1 augustss if (sc->sc_bulk_end == sqh)
1274 1.1 augustss sc->sc_bulk_end = pqh;
1275 1.1 augustss }
1276 1.1 augustss
1277 1.141 augustss Static int uhci_intr1(uhci_softc_t *);
1278 1.141 augustss
1279 1.1 augustss int
1280 1.119 augustss uhci_intr(void *arg)
1281 1.1 augustss {
1282 1.44 augustss uhci_softc_t *sc = arg;
1283 1.248 mrg int ret = 0;
1284 1.248 mrg
1285 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1286 1.264.4.21 skrll
1287 1.248 mrg mutex_spin_enter(&sc->sc_intr_lock);
1288 1.146 augustss
1289 1.216 drochner if (sc->sc_dying || !device_has_power(sc->sc_dev))
1290 1.248 mrg goto done;
1291 1.141 augustss
1292 1.264.4.7 skrll if (sc->sc_bus.ub_usepolling || UREAD2(sc, UHCI_INTR) == 0) {
1293 1.264.4.21 skrll DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0);
1294 1.248 mrg goto done;
1295 1.141 augustss }
1296 1.179 mycroft
1297 1.248 mrg ret = uhci_intr1(sc);
1298 1.248 mrg
1299 1.248 mrg done:
1300 1.248 mrg mutex_spin_exit(&sc->sc_intr_lock);
1301 1.248 mrg return ret;
1302 1.141 augustss }
1303 1.141 augustss
1304 1.141 augustss int
1305 1.141 augustss uhci_intr1(uhci_softc_t *sc)
1306 1.141 augustss {
1307 1.44 augustss int status;
1308 1.44 augustss int ack;
1309 1.1 augustss
1310 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1311 1.264.4.21 skrll
1312 1.67 augustss #ifdef UHCI_DEBUG
1313 1.264.4.46 skrll if (uhcidebug >= 15) {
1314 1.264.4.27 skrll DPRINTF("sc %p", sc, 0, 0, 0);
1315 1.1 augustss uhci_dumpregs(sc);
1316 1.1 augustss }
1317 1.1 augustss #endif
1318 1.117 augustss
1319 1.248 mrg KASSERT(mutex_owned(&sc->sc_intr_lock));
1320 1.248 mrg
1321 1.153 augustss status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS;
1322 1.264.4.59 skrll /* Check if the interrupt was for us. */
1323 1.264.4.59 skrll if (status == 0)
1324 1.264.4.13 skrll return 0;
1325 1.127 soren
1326 1.117 augustss if (sc->sc_suspend != PWR_RESUME) {
1327 1.201 jmcneill #ifdef DIAGNOSTIC
1328 1.117 augustss printf("%s: interrupt while not operating ignored\n",
1329 1.216 drochner device_xname(sc->sc_dev));
1330 1.201 jmcneill #endif
1331 1.134 augustss UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */
1332 1.264.4.13 skrll return 0;
1333 1.117 augustss }
1334 1.44 augustss
1335 1.44 augustss ack = 0;
1336 1.44 augustss if (status & UHCI_STS_USBINT)
1337 1.44 augustss ack |= UHCI_STS_USBINT;
1338 1.44 augustss if (status & UHCI_STS_USBEI)
1339 1.44 augustss ack |= UHCI_STS_USBEI;
1340 1.1 augustss if (status & UHCI_STS_RD) {
1341 1.44 augustss ack |= UHCI_STS_RD;
1342 1.118 augustss #ifdef UHCI_DEBUG
1343 1.216 drochner printf("%s: resume detect\n", device_xname(sc->sc_dev));
1344 1.118 augustss #endif
1345 1.1 augustss }
1346 1.1 augustss if (status & UHCI_STS_HSE) {
1347 1.44 augustss ack |= UHCI_STS_HSE;
1348 1.216 drochner printf("%s: host system error\n", device_xname(sc->sc_dev));
1349 1.1 augustss }
1350 1.1 augustss if (status & UHCI_STS_HCPE) {
1351 1.44 augustss ack |= UHCI_STS_HCPE;
1352 1.152 augustss printf("%s: host controller process error\n",
1353 1.216 drochner device_xname(sc->sc_dev));
1354 1.44 augustss }
1355 1.233 msaitoh
1356 1.233 msaitoh /* When HCHalted=1 and Run/Stop=0 , it is normal */
1357 1.233 msaitoh if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) {
1358 1.44 augustss /* no acknowledge needed */
1359 1.136 augustss if (!sc->sc_dying) {
1360 1.152 augustss printf("%s: host controller halted\n",
1361 1.216 drochner device_xname(sc->sc_dev));
1362 1.110 augustss #ifdef UHCI_DEBUG
1363 1.136 augustss uhci_dump_all(sc);
1364 1.110 augustss #endif
1365 1.136 augustss }
1366 1.136 augustss sc->sc_dying = 1;
1367 1.1 augustss }
1368 1.44 augustss
1369 1.132 augustss if (!ack)
1370 1.264.4.13 skrll return 0; /* nothing to acknowledge */
1371 1.132 augustss UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */
1372 1.1 augustss
1373 1.85 augustss usb_schedsoftintr(&sc->sc_bus);
1374 1.85 augustss
1375 1.264.4.21 skrll DPRINTFN(15, "sc %p done", sc, 0, 0, 0);
1376 1.85 augustss
1377 1.264.4.13 skrll return 1;
1378 1.85 augustss }
1379 1.85 augustss
1380 1.85 augustss void
1381 1.133 augustss uhci_softintr(void *v)
1382 1.85 augustss {
1383 1.216 drochner struct usbd_bus *bus = v;
1384 1.264.4.37 skrll uhci_softc_t *sc = UHCI_BUS2SC(bus);
1385 1.264.4.39 skrll struct uhci_xfer *ux, *nextux;
1386 1.85 augustss
1387 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1388 1.264.4.27 skrll DPRINTF("sc %p", sc, 0, 0, 0);
1389 1.248 mrg
1390 1.264.4.21 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1391 1.50 augustss
1392 1.1 augustss /*
1393 1.1 augustss * Interrupts on UHCI really suck. When the host controller
1394 1.1 augustss * interrupts because a transfer is completed there is no
1395 1.1 augustss * way of knowing which transfer it was. You can scan down
1396 1.1 augustss * the TDs and QHs of the previous frame to limit the search,
1397 1.1 augustss * but that assumes that the interrupt was not delayed by more
1398 1.1 augustss * than 1 ms, which may not always be true (e.g. after debug
1399 1.1 augustss * output on a slow console).
1400 1.1 augustss * We scan all interrupt descriptors to see if any have
1401 1.1 augustss * completed.
1402 1.1 augustss */
1403 1.264.4.39 skrll for (ux = TAILQ_FIRST(&sc->sc_intrhead); ux; ux = nextux) {
1404 1.264.4.41 skrll nextux = TAILQ_NEXT(ux, ux_list);
1405 1.264.4.39 skrll uhci_check_intr(sc, ux);
1406 1.178 martin }
1407 1.1 augustss
1408 1.153 augustss if (sc->sc_softwake) {
1409 1.153 augustss sc->sc_softwake = 0;
1410 1.248 mrg cv_broadcast(&sc->sc_softwake_cv);
1411 1.153 augustss }
1412 1.1 augustss }
1413 1.1 augustss
1414 1.1 augustss /* Check for an interrupt. */
1415 1.1 augustss void
1416 1.264.4.39 skrll uhci_check_intr(uhci_softc_t *sc, struct uhci_xfer *ux)
1417 1.1 augustss {
1418 1.264.4.55 skrll uhci_soft_td_t *std, *fstd = NULL, *lstd = NULL;
1419 1.264.4.1 skrll uint32_t status;
1420 1.1 augustss
1421 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1422 1.264.4.39 skrll DPRINTFN(15, "ux %p", ux, 0, 0, 0);
1423 1.264.4.31 skrll
1424 1.264.4.39 skrll KASSERT(ux != NULL);
1425 1.264.4.31 skrll
1426 1.264.4.41 skrll struct usbd_xfer *xfer = &ux->ux_xfer;
1427 1.264.4.39 skrll if (xfer->ux_status == USBD_CANCELLED ||
1428 1.264.4.39 skrll xfer->ux_status == USBD_TIMEOUT) {
1429 1.264.4.39 skrll DPRINTF("aborted xfer %p", xfer, 0, 0, 0);
1430 1.155 augustss return;
1431 1.155 augustss }
1432 1.155 augustss
1433 1.264.4.55 skrll switch (ux->ux_type) {
1434 1.264.4.55 skrll case UX_CTRL:
1435 1.264.4.55 skrll fstd = ux->ux_setup;
1436 1.264.4.55 skrll lstd = ux->ux_stat;
1437 1.264.4.55 skrll break;
1438 1.264.4.55 skrll case UX_BULK:
1439 1.264.4.55 skrll case UX_INTR:
1440 1.264.4.55 skrll case UX_ISOC:
1441 1.264.4.55 skrll fstd = ux->ux_stdstart;
1442 1.264.4.55 skrll lstd = ux->ux_stdend;
1443 1.264.4.55 skrll break;
1444 1.264.4.55 skrll default:
1445 1.264.4.55 skrll KASSERT(false);
1446 1.264.4.55 skrll break;
1447 1.264.4.55 skrll }
1448 1.264.4.55 skrll if (fstd == NULL)
1449 1.1 augustss return;
1450 1.264.4.31 skrll
1451 1.264.4.31 skrll KASSERT(lstd != NULL);
1452 1.264.4.31 skrll
1453 1.223 bouyer usb_syncmem(&lstd->dma,
1454 1.223 bouyer lstd->offs + offsetof(uhci_td_t, td_status),
1455 1.223 bouyer sizeof(lstd->td.td_status),
1456 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1457 1.256 tsutsui status = le32toh(lstd->td.td_status);
1458 1.256 tsutsui usb_syncmem(&lstd->dma,
1459 1.256 tsutsui lstd->offs + offsetof(uhci_td_t, td_status),
1460 1.256 tsutsui sizeof(lstd->td.td_status),
1461 1.256 tsutsui BUS_DMASYNC_PREREAD);
1462 1.258 skrll
1463 1.258 skrll /* If the last TD is not marked active we can complete */
1464 1.258 skrll if (!(status & UHCI_TD_ACTIVE)) {
1465 1.258 skrll done:
1466 1.264.4.39 skrll DPRINTFN(12, "ux=%p done", ux, 0, 0, 0);
1467 1.264.4.21 skrll
1468 1.264.4.39 skrll callout_stop(&xfer->ux_callout);
1469 1.264.4.39 skrll uhci_idone(ux);
1470 1.258 skrll return;
1471 1.258 skrll }
1472 1.258 skrll
1473 1.258 skrll /*
1474 1.258 skrll * If the last TD is still active we need to check whether there
1475 1.258 skrll * is an error somewhere in the middle, or whether there was a
1476 1.258 skrll * short packet (SPD and not ACTIVE).
1477 1.258 skrll */
1478 1.264.4.39 skrll DPRINTFN(12, "active ux=%p", ux, 0, 0, 0);
1479 1.264.4.55 skrll for (std = fstd; std != lstd; std = std->link.std) {
1480 1.258 skrll usb_syncmem(&std->dma,
1481 1.258 skrll std->offs + offsetof(uhci_td_t, td_status),
1482 1.258 skrll sizeof(std->td.td_status),
1483 1.258 skrll BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1484 1.258 skrll status = le32toh(std->td.td_status);
1485 1.258 skrll usb_syncmem(&std->dma,
1486 1.258 skrll std->offs + offsetof(uhci_td_t, td_status),
1487 1.258 skrll sizeof(std->td.td_status), BUS_DMASYNC_PREREAD);
1488 1.258 skrll
1489 1.258 skrll /* If there's an active TD the xfer isn't done. */
1490 1.258 skrll if (status & UHCI_TD_ACTIVE) {
1491 1.264.4.39 skrll DPRINTFN(12, "ux=%p std=%p still active",
1492 1.264.4.39 skrll ux, std, 0, 0);
1493 1.258 skrll return;
1494 1.258 skrll }
1495 1.258 skrll
1496 1.258 skrll /* Any kind of error makes the xfer done. */
1497 1.258 skrll if (status & UHCI_TD_STALLED)
1498 1.258 skrll goto done;
1499 1.258 skrll
1500 1.258 skrll /*
1501 1.258 skrll * If the data phase of a control transfer is short, we need
1502 1.258 skrll * to complete the status stage
1503 1.258 skrll */
1504 1.258 skrll
1505 1.264.4.55 skrll if ((status & UHCI_TD_SPD) && ux->ux_type == UX_CTRL) {
1506 1.258 skrll struct uhci_pipe *upipe =
1507 1.264.4.50 skrll UHCI_PIPE2UPIPE(xfer->ux_pipe);
1508 1.264.4.33 skrll uhci_soft_qh_t *sqh = upipe->ctrl.sqh;
1509 1.264.4.33 skrll uhci_soft_td_t *stat = upipe->ctrl.stat;
1510 1.258 skrll
1511 1.264.4.39 skrll DPRINTFN(12, "ux=%p std=%p control status"
1512 1.264.4.41 skrll "phase needs completion", ux, ux->ux_stdstart, 0, 0);
1513 1.258 skrll
1514 1.258 skrll sqh->qh.qh_elink =
1515 1.258 skrll htole32(stat->physaddr | UHCI_PTR_TD);
1516 1.258 skrll usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1517 1.258 skrll BUS_DMASYNC_PREWRITE);
1518 1.258 skrll break;
1519 1.258 skrll }
1520 1.258 skrll
1521 1.258 skrll /* We want short packets, and it is short: it's done */
1522 1.258 skrll usb_syncmem(&std->dma,
1523 1.258 skrll std->offs + offsetof(uhci_td_t, td_token),
1524 1.258 skrll sizeof(std->td.td_token),
1525 1.258 skrll BUS_DMASYNC_POSTWRITE);
1526 1.258 skrll
1527 1.258 skrll if ((status & UHCI_TD_SPD) &&
1528 1.258 skrll UHCI_TD_GET_ACTLEN(status) <
1529 1.258 skrll UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) {
1530 1.258 skrll goto done;
1531 1.18 augustss }
1532 1.1 augustss }
1533 1.1 augustss }
1534 1.1 augustss
1535 1.248 mrg /* Called with USB lock held. */
1536 1.1 augustss void
1537 1.264.4.39 skrll uhci_idone(struct uhci_xfer *ux)
1538 1.1 augustss {
1539 1.264.4.41 skrll struct usbd_xfer *xfer = &ux->ux_xfer;
1540 1.264.4.37 skrll uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer);
1541 1.264.4.50 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
1542 1.1 augustss uhci_soft_td_t *std;
1543 1.264.4.1 skrll uint32_t status = 0, nstatus;
1544 1.26 augustss int actlen;
1545 1.1 augustss
1546 1.264.4.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1547 1.248 mrg
1548 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1549 1.264.4.39 skrll DPRINTFN(12, "ux=%p", ux, 0, 0, 0);
1550 1.264.4.21 skrll
1551 1.7 augustss #ifdef DIAGNOSTIC
1552 1.92 augustss #ifdef UHCI_DEBUG
1553 1.264.4.41 skrll if (ux->ux_isdone) {
1554 1.264.4.31 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
1555 1.264.4.39 skrll uhci_dump_ii(ux);
1556 1.264.4.31 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
1557 1.7 augustss }
1558 1.7 augustss #endif
1559 1.264.4.41 skrll KASSERT(!ux->ux_isdone);
1560 1.264.4.41 skrll ux->ux_isdone = true;
1561 1.264.4.31 skrll #endif
1562 1.48 augustss
1563 1.264.4.7 skrll if (xfer->ux_nframes != 0) {
1564 1.48 augustss /* Isoc transfer, do things differently. */
1565 1.264.4.33 skrll uhci_soft_td_t **stds = upipe->isoc.stds;
1566 1.126 augustss int i, n, nframes, len;
1567 1.48 augustss
1568 1.264.4.39 skrll DPRINTFN(5, "ux=%p isoc ready", ux, 0, 0, 0);
1569 1.48 augustss
1570 1.264.4.7 skrll nframes = xfer->ux_nframes;
1571 1.48 augustss actlen = 0;
1572 1.264.4.41 skrll n = UHCI_XFER2UXFER(xfer)->ux_curframe;
1573 1.48 augustss for (i = 0; i < nframes; i++) {
1574 1.48 augustss std = stds[n];
1575 1.59 augustss #ifdef UHCI_DEBUG
1576 1.264.4.43 skrll if (uhcidebug >= 5) {
1577 1.264.4.27 skrll DPRINTF("isoc TD %d", i, 0, 0, 0);
1578 1.264.4.53 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
1579 1.48 augustss uhci_dump_td(std);
1580 1.264.4.53 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
1581 1.48 augustss }
1582 1.48 augustss #endif
1583 1.48 augustss if (++n >= UHCI_VFRAMELIST_COUNT)
1584 1.48 augustss n = 0;
1585 1.223 bouyer usb_syncmem(&std->dma,
1586 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
1587 1.223 bouyer sizeof(std->td.td_status),
1588 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1589 1.88 tsutsui status = le32toh(std->td.td_status);
1590 1.126 augustss len = UHCI_TD_GET_ACTLEN(status);
1591 1.264.4.7 skrll xfer->ux_frlengths[i] = len;
1592 1.126 augustss actlen += len;
1593 1.48 augustss }
1594 1.264.4.33 skrll upipe->isoc.inuse -= nframes;
1595 1.264.4.7 skrll xfer->ux_actlen = actlen;
1596 1.264.4.7 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1597 1.140 augustss goto end;
1598 1.48 augustss }
1599 1.48 augustss
1600 1.59 augustss #ifdef UHCI_DEBUG
1601 1.264.4.47 skrll DPRINTFN(10, "ux=%p, xfer=%p, pipe=%p ready", ux, xfer, upipe, 0);
1602 1.264.4.47 skrll if (uhcidebug >= 10) {
1603 1.264.4.47 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
1604 1.264.4.41 skrll uhci_dump_tds(ux->ux_stdstart);
1605 1.264.4.47 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
1606 1.264.4.47 skrll }
1607 1.48 augustss #endif
1608 1.48 augustss
1609 1.26 augustss /* The transfer is done, compute actual length and status. */
1610 1.26 augustss actlen = 0;
1611 1.264.4.41 skrll for (std = ux->ux_stdstart; std != NULL; std = std->link.std) {
1612 1.223 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
1613 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1614 1.88 tsutsui nstatus = le32toh(std->td.td_status);
1615 1.64 augustss if (nstatus & UHCI_TD_ACTIVE)
1616 1.26 augustss break;
1617 1.67 augustss
1618 1.64 augustss status = nstatus;
1619 1.88 tsutsui if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) !=
1620 1.88 tsutsui UHCI_TD_PID_SETUP)
1621 1.26 augustss actlen += UHCI_TD_GET_ACTLEN(status);
1622 1.176 mycroft else {
1623 1.176 mycroft /*
1624 1.176 mycroft * UHCI will report CRCTO in addition to a STALL or NAK
1625 1.176 mycroft * for a SETUP transaction. See section 3.2.2, "TD
1626 1.176 mycroft * CONTROL AND STATUS".
1627 1.176 mycroft */
1628 1.176 mycroft if (status & (UHCI_TD_STALLED | UHCI_TD_NAK))
1629 1.176 mycroft status &= ~UHCI_TD_CRCTO;
1630 1.176 mycroft }
1631 1.1 augustss }
1632 1.38 augustss /* If there are left over TDs we need to update the toggle. */
1633 1.63 augustss if (std != NULL)
1634 1.88 tsutsui upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token));
1635 1.38 augustss
1636 1.1 augustss status &= UHCI_TD_ERROR;
1637 1.264.4.29 skrll DPRINTFN(10, "actlen=%d, status=0x%x", actlen, status, 0, 0);
1638 1.264.4.7 skrll xfer->ux_actlen = actlen;
1639 1.1 augustss if (status != 0) {
1640 1.122 tv
1641 1.264.4.21 skrll DPRINTFN((status == UHCI_TD_STALLED) * 10,
1642 1.264.4.21 skrll "error, addr=%d, endpt=0x%02x",
1643 1.264.4.21 skrll xfer->ux_pipe->up_dev->ud_addr,
1644 1.264.4.21 skrll xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress,
1645 1.264.4.21 skrll 0, 0);
1646 1.264.4.21 skrll DPRINTFN((status == UHCI_TD_STALLED) * 10,
1647 1.264.4.21 skrll "bitstuff=%d crcto =%d nak =%d babble =%d",
1648 1.264.4.45 skrll !!(status & UHCI_TD_BITSTUFF),
1649 1.264.4.45 skrll !!(status & UHCI_TD_CRCTO),
1650 1.264.4.45 skrll !!(status & UHCI_TD_NAK),
1651 1.264.4.45 skrll !!(status & UHCI_TD_BABBLE));
1652 1.264.4.21 skrll DPRINTFN((status == UHCI_TD_STALLED) * 10,
1653 1.264.4.21 skrll "dbuffer =%d stalled =%d active =%d",
1654 1.264.4.45 skrll !!(status & UHCI_TD_DBUFFER),
1655 1.264.4.45 skrll !!(status & UHCI_TD_STALLED),
1656 1.264.4.45 skrll !!(status & UHCI_TD_ACTIVE),
1657 1.264.4.21 skrll 0);
1658 1.122 tv
1659 1.1 augustss if (status == UHCI_TD_STALLED)
1660 1.264.4.7 skrll xfer->ux_status = USBD_STALLED;
1661 1.1 augustss else
1662 1.264.4.7 skrll xfer->ux_status = USBD_IOERROR; /* more info XXX */
1663 1.1 augustss } else {
1664 1.264.4.7 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1665 1.1 augustss }
1666 1.140 augustss
1667 1.140 augustss end:
1668 1.63 augustss usb_transfer_complete(xfer);
1669 1.264.4.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1670 1.264.4.39 skrll DPRINTFN(12, "ux=%p done", ux, 0, 0, 0);
1671 1.1 augustss }
1672 1.1 augustss
1673 1.13 augustss /*
1674 1.13 augustss * Called when a request does not complete.
1675 1.13 augustss */
1676 1.1 augustss void
1677 1.119 augustss uhci_timeout(void *addr)
1678 1.1 augustss {
1679 1.264.4.39 skrll struct usbd_xfer *xfer = addr;
1680 1.264.4.39 skrll struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
1681 1.264.4.39 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
1682 1.153 augustss
1683 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1684 1.264.4.21 skrll
1685 1.264.4.27 skrll DPRINTF("uxfer %p", uxfer, 0, 0, 0);
1686 1.153 augustss
1687 1.153 augustss if (sc->sc_dying) {
1688 1.248 mrg mutex_enter(&sc->sc_lock);
1689 1.264.4.39 skrll uhci_abort_xfer(xfer, USBD_TIMEOUT);
1690 1.248 mrg mutex_exit(&sc->sc_lock);
1691 1.153 augustss return;
1692 1.153 augustss }
1693 1.1 augustss
1694 1.153 augustss /* Execute the abort in a process context. */
1695 1.264.4.41 skrll usb_init_task(&uxfer->ux_aborttask, uhci_timeout_task, xfer,
1696 1.252 jmcneill USB_TASKQ_MPSAFE);
1697 1.264.4.41 skrll usb_add_task(uxfer->ux_xfer.ux_pipe->up_dev, &uxfer->ux_aborttask,
1698 1.204 joerg USB_TASKQ_HC);
1699 1.153 augustss }
1700 1.51 augustss
1701 1.153 augustss void
1702 1.153 augustss uhci_timeout_task(void *addr)
1703 1.153 augustss {
1704 1.264.4.25 skrll struct usbd_xfer *xfer = addr;
1705 1.264.4.37 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
1706 1.153 augustss
1707 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1708 1.264.4.21 skrll
1709 1.264.4.27 skrll DPRINTF("xfer=%p", xfer, 0, 0, 0);
1710 1.67 augustss
1711 1.248 mrg mutex_enter(&sc->sc_lock);
1712 1.153 augustss uhci_abort_xfer(xfer, USBD_TIMEOUT);
1713 1.248 mrg mutex_exit(&sc->sc_lock);
1714 1.1 augustss }
1715 1.1 augustss
1716 1.1 augustss /*
1717 1.1 augustss * Wait here until controller claims to have an interrupt.
1718 1.1 augustss * Then call uhci_intr and return. Use timeout to avoid waiting
1719 1.1 augustss * too long.
1720 1.13 augustss * Only used during boot when interrupts are not enabled yet.
1721 1.1 augustss */
1722 1.1 augustss void
1723 1.264.4.25 skrll uhci_waitintr(uhci_softc_t *sc, struct usbd_xfer *xfer)
1724 1.1 augustss {
1725 1.264.4.7 skrll int timo = xfer->ux_timeout;
1726 1.264.4.39 skrll struct uhci_xfer *ux;
1727 1.13 augustss
1728 1.248 mrg mutex_enter(&sc->sc_lock);
1729 1.248 mrg
1730 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1731 1.264.4.21 skrll DPRINTFN(10, "timeout = %dms", timo, 0, 0, 0);
1732 1.1 augustss
1733 1.264.4.7 skrll xfer->ux_status = USBD_IN_PROGRESS;
1734 1.26 augustss for (; timo >= 0; timo--) {
1735 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_lock);
1736 1.264.4.21 skrll DPRINTFN(20, "0x%04x",
1737 1.264.4.21 skrll UREAD2(sc, UHCI_STS), 0, 0, 0);
1738 1.1 augustss if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) {
1739 1.248 mrg mutex_spin_enter(&sc->sc_intr_lock);
1740 1.141 augustss uhci_intr1(sc);
1741 1.248 mrg mutex_spin_exit(&sc->sc_intr_lock);
1742 1.264.4.7 skrll if (xfer->ux_status != USBD_IN_PROGRESS)
1743 1.248 mrg goto done;
1744 1.1 augustss }
1745 1.1 augustss }
1746 1.13 augustss
1747 1.13 augustss /* Timeout */
1748 1.264.4.27 skrll DPRINTF("timeout", 0, 0, 0, 0);
1749 1.264.4.60 skrll TAILQ_FOREACH(ux, &sc->sc_intrhead, ux_list)
1750 1.264.4.41 skrll if (&ux->ux_xfer == xfer)
1751 1.264.4.39 skrll break;
1752 1.264.4.31 skrll
1753 1.264.4.39 skrll KASSERT(ux != NULL);
1754 1.264.4.31 skrll
1755 1.264.4.39 skrll uhci_idone(ux);
1756 1.248 mrg
1757 1.248 mrg done:
1758 1.248 mrg mutex_exit(&sc->sc_lock);
1759 1.1 augustss }
1760 1.1 augustss
1761 1.8 augustss void
1762 1.119 augustss uhci_poll(struct usbd_bus *bus)
1763 1.8 augustss {
1764 1.264.4.37 skrll uhci_softc_t *sc = UHCI_BUS2SC(bus);
1765 1.8 augustss
1766 1.248 mrg if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) {
1767 1.248 mrg mutex_spin_enter(&sc->sc_intr_lock);
1768 1.141 augustss uhci_intr1(sc);
1769 1.248 mrg mutex_spin_exit(&sc->sc_intr_lock);
1770 1.248 mrg }
1771 1.8 augustss }
1772 1.8 augustss
1773 1.1 augustss void
1774 1.119 augustss uhci_reset(uhci_softc_t *sc)
1775 1.1 augustss {
1776 1.1 augustss int n;
1777 1.1 augustss
1778 1.1 augustss UHCICMD(sc, UHCI_CMD_HCRESET);
1779 1.1 augustss /* The reset bit goes low when the controller is done. */
1780 1.152 augustss for (n = 0; n < UHCI_RESET_TIMEOUT &&
1781 1.1 augustss (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++)
1782 1.92 augustss usb_delay_ms(&sc->sc_bus, 1);
1783 1.1 augustss if (n >= UHCI_RESET_TIMEOUT)
1784 1.152 augustss printf("%s: controller did not reset\n",
1785 1.216 drochner device_xname(sc->sc_dev));
1786 1.1 augustss }
1787 1.1 augustss
1788 1.16 augustss usbd_status
1789 1.249 drochner uhci_run(uhci_softc_t *sc, int run, int locked)
1790 1.1 augustss {
1791 1.248 mrg int n, running;
1792 1.264.4.1 skrll uint16_t cmd;
1793 1.1 augustss
1794 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1795 1.264.4.21 skrll
1796 1.1 augustss run = run != 0;
1797 1.249 drochner if (!locked)
1798 1.249 drochner mutex_spin_enter(&sc->sc_intr_lock);
1799 1.264.4.21 skrll
1800 1.264.4.27 skrll DPRINTF("setting run=%d", run, 0, 0, 0);
1801 1.71 augustss cmd = UREAD2(sc, UHCI_CMD);
1802 1.71 augustss if (run)
1803 1.71 augustss cmd |= UHCI_CMD_RS;
1804 1.71 augustss else
1805 1.71 augustss cmd &= ~UHCI_CMD_RS;
1806 1.71 augustss UHCICMD(sc, cmd);
1807 1.264.4.54 skrll for (n = 0; n < 10; n++) {
1808 1.1 augustss running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH);
1809 1.1 augustss /* return when we've entered the state we want */
1810 1.1 augustss if (run == running) {
1811 1.249 drochner if (!locked)
1812 1.249 drochner mutex_spin_exit(&sc->sc_intr_lock);
1813 1.264.4.27 skrll DPRINTF("done cmd=0x%x sts=0x%x",
1814 1.264.4.21 skrll UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 0, 0);
1815 1.264.4.13 skrll return USBD_NORMAL_COMPLETION;
1816 1.1 augustss }
1817 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock);
1818 1.1 augustss }
1819 1.249 drochner if (!locked)
1820 1.249 drochner mutex_spin_exit(&sc->sc_intr_lock);
1821 1.216 drochner printf("%s: cannot %s\n", device_xname(sc->sc_dev),
1822 1.14 augustss run ? "start" : "stop");
1823 1.264.4.13 skrll return USBD_IOERROR;
1824 1.1 augustss }
1825 1.1 augustss
1826 1.1 augustss /*
1827 1.1 augustss * Memory management routines.
1828 1.1 augustss * uhci_alloc_std allocates TDs
1829 1.1 augustss * uhci_alloc_sqh allocates QHs
1830 1.7 augustss * These two routines do their own free list management,
1831 1.1 augustss * partly for speed, partly because allocating DMAable memory
1832 1.264.4.28 skrll * has page size granularity so much memory would be wasted if
1833 1.16 augustss * only one TD/QH (32 bytes) was placed in each allocated chunk.
1834 1.1 augustss */
1835 1.1 augustss
1836 1.1 augustss uhci_soft_td_t *
1837 1.119 augustss uhci_alloc_std(uhci_softc_t *sc)
1838 1.1 augustss {
1839 1.1 augustss uhci_soft_td_t *std;
1840 1.63 augustss usbd_status err;
1841 1.42 augustss int i, offs;
1842 1.7 augustss usb_dma_t dma;
1843 1.1 augustss
1844 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1845 1.264.4.21 skrll
1846 1.264.4.55 skrll mutex_enter(&sc->sc_lock);
1847 1.63 augustss if (sc->sc_freetds == NULL) {
1848 1.264.4.21 skrll DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
1849 1.264.4.55 skrll mutex_exit(&sc->sc_lock);
1850 1.264.4.55 skrll
1851 1.63 augustss err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK,
1852 1.63 augustss UHCI_TD_ALIGN, &dma);
1853 1.63 augustss if (err)
1854 1.264.4.52 skrll return NULL;
1855 1.264.4.55 skrll
1856 1.264.4.55 skrll mutex_enter(&sc->sc_lock);
1857 1.248 mrg for (i = 0; i < UHCI_STD_CHUNK; i++) {
1858 1.42 augustss offs = i * UHCI_STD_SIZE;
1859 1.159 augustss std = KERNADDR(&dma, offs);
1860 1.160 augustss std->physaddr = DMAADDR(&dma, offs);
1861 1.223 bouyer std->dma = dma;
1862 1.223 bouyer std->offs = offs;
1863 1.42 augustss std->link.std = sc->sc_freetds;
1864 1.1 augustss sc->sc_freetds = std;
1865 1.1 augustss }
1866 1.1 augustss }
1867 1.1 augustss std = sc->sc_freetds;
1868 1.42 augustss sc->sc_freetds = std->link.std;
1869 1.264.4.55 skrll mutex_exit(&sc->sc_lock);
1870 1.264.4.55 skrll
1871 1.42 augustss memset(&std->td, 0, sizeof(uhci_td_t));
1872 1.264.4.55 skrll
1873 1.1 augustss return std;
1874 1.1 augustss }
1875 1.1 augustss
1876 1.264.4.55 skrll #define TD_IS_FREE 0x12345678
1877 1.264.4.55 skrll
1878 1.1 augustss void
1879 1.264.4.55 skrll uhci_free_std_locked(uhci_softc_t *sc, uhci_soft_td_t *std)
1880 1.1 augustss {
1881 1.264.4.55 skrll KASSERT(mutex_owned(&sc->sc_lock));
1882 1.264.4.55 skrll
1883 1.7 augustss #ifdef DIAGNOSTIC
1884 1.88 tsutsui if (le32toh(std->td.td_token) == TD_IS_FREE) {
1885 1.7 augustss printf("uhci_free_std: freeing free TD %p\n", std);
1886 1.7 augustss return;
1887 1.7 augustss }
1888 1.88 tsutsui std->td.td_token = htole32(TD_IS_FREE);
1889 1.7 augustss #endif
1890 1.264.4.55 skrll
1891 1.42 augustss std->link.std = sc->sc_freetds;
1892 1.1 augustss sc->sc_freetds = std;
1893 1.1 augustss }
1894 1.1 augustss
1895 1.264.4.55 skrll void
1896 1.264.4.55 skrll uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std)
1897 1.264.4.55 skrll {
1898 1.264.4.55 skrll mutex_enter(&sc->sc_lock);
1899 1.264.4.55 skrll uhci_free_std_locked(sc, std);
1900 1.264.4.55 skrll mutex_exit(&sc->sc_lock);
1901 1.264.4.55 skrll }
1902 1.264.4.55 skrll
1903 1.1 augustss uhci_soft_qh_t *
1904 1.119 augustss uhci_alloc_sqh(uhci_softc_t *sc)
1905 1.1 augustss {
1906 1.1 augustss uhci_soft_qh_t *sqh;
1907 1.63 augustss usbd_status err;
1908 1.1 augustss int i, offs;
1909 1.7 augustss usb_dma_t dma;
1910 1.1 augustss
1911 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1912 1.264.4.21 skrll
1913 1.264.4.55 skrll mutex_enter(&sc->sc_lock);
1914 1.63 augustss if (sc->sc_freeqhs == NULL) {
1915 1.264.4.21 skrll DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
1916 1.264.4.55 skrll mutex_exit(&sc->sc_lock);
1917 1.264.4.55 skrll
1918 1.63 augustss err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK,
1919 1.63 augustss UHCI_QH_ALIGN, &dma);
1920 1.63 augustss if (err)
1921 1.264.4.52 skrll return NULL;
1922 1.264.4.55 skrll
1923 1.264.4.55 skrll mutex_enter(&sc->sc_lock);
1924 1.264.4.54 skrll for (i = 0; i < UHCI_SQH_CHUNK; i++) {
1925 1.42 augustss offs = i * UHCI_SQH_SIZE;
1926 1.159 augustss sqh = KERNADDR(&dma, offs);
1927 1.160 augustss sqh->physaddr = DMAADDR(&dma, offs);
1928 1.223 bouyer sqh->dma = dma;
1929 1.223 bouyer sqh->offs = offs;
1930 1.42 augustss sqh->hlink = sc->sc_freeqhs;
1931 1.1 augustss sc->sc_freeqhs = sqh;
1932 1.1 augustss }
1933 1.1 augustss }
1934 1.1 augustss sqh = sc->sc_freeqhs;
1935 1.42 augustss sc->sc_freeqhs = sqh->hlink;
1936 1.264.4.55 skrll mutex_exit(&sc->sc_lock);
1937 1.264.4.55 skrll
1938 1.42 augustss memset(&sqh->qh, 0, sizeof(uhci_qh_t));
1939 1.264.4.55 skrll
1940 1.264.4.13 skrll return sqh;
1941 1.1 augustss }
1942 1.1 augustss
1943 1.1 augustss void
1944 1.119 augustss uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1945 1.1 augustss {
1946 1.264.4.55 skrll KASSERT(mutex_owned(&sc->sc_lock));
1947 1.264.4.55 skrll
1948 1.42 augustss sqh->hlink = sc->sc_freeqhs;
1949 1.1 augustss sc->sc_freeqhs = sqh;
1950 1.1 augustss }
1951 1.1 augustss
1952 1.1 augustss void
1953 1.119 augustss uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std,
1954 1.119 augustss uhci_soft_td_t *stdend)
1955 1.1 augustss {
1956 1.1 augustss uhci_soft_td_t *p;
1957 1.256 tsutsui uint32_t td_link;
1958 1.1 augustss
1959 1.223 bouyer /*
1960 1.223 bouyer * to avoid race condition with the controller which may be looking
1961 1.223 bouyer * at this chain, we need to first invalidate all links, and
1962 1.223 bouyer * then wait for the controller to move to another queue
1963 1.223 bouyer */
1964 1.223 bouyer for (p = std; p != stdend; p = p->link.std) {
1965 1.223 bouyer usb_syncmem(&p->dma,
1966 1.223 bouyer p->offs + offsetof(uhci_td_t, td_link),
1967 1.223 bouyer sizeof(p->td.td_link),
1968 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1969 1.256 tsutsui td_link = le32toh(p->td.td_link);
1970 1.256 tsutsui usb_syncmem(&p->dma,
1971 1.256 tsutsui p->offs + offsetof(uhci_td_t, td_link),
1972 1.256 tsutsui sizeof(p->td.td_link),
1973 1.256 tsutsui BUS_DMASYNC_PREREAD);
1974 1.256 tsutsui if ((td_link & UHCI_PTR_T) == 0) {
1975 1.255 tsutsui p->td.td_link = htole32(UHCI_PTR_T);
1976 1.223 bouyer usb_syncmem(&p->dma,
1977 1.223 bouyer p->offs + offsetof(uhci_td_t, td_link),
1978 1.223 bouyer sizeof(p->td.td_link),
1979 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1980 1.223 bouyer }
1981 1.223 bouyer }
1982 1.223 bouyer delay(UHCI_QH_REMOVE_DELAY);
1983 1.223 bouyer
1984 1.1 augustss for (; std != stdend; std = p) {
1985 1.42 augustss p = std->link.std;
1986 1.1 augustss uhci_free_std(sc, std);
1987 1.1 augustss }
1988 1.1 augustss }
1989 1.1 augustss
1990 1.1 augustss usbd_status
1991 1.264.4.55 skrll uhci_alloc_std_chain(uhci_softc_t *sc, struct usbd_xfer *xfer, int alen,
1992 1.264.4.55 skrll int rd, uhci_soft_td_t **sp, uhci_soft_td_t **ep)
1993 1.1 augustss {
1994 1.1 augustss uhci_soft_td_t *p, *lastp;
1995 1.1 augustss uhci_physaddr_t lastlink;
1996 1.264.4.55 skrll int i, l, maxp;
1997 1.264.4.55 skrll int len;
1998 1.264.4.1 skrll uint32_t status;
1999 1.264.4.55 skrll struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
2000 1.264.4.55 skrll int addr = xfer->ux_pipe->up_dev->ud_addr;
2001 1.264.4.55 skrll int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;
2002 1.264.4.55 skrll usb_dma_t *dma = &xfer->ux_dmabuf;
2003 1.264.4.55 skrll uint16_t flags = xfer->ux_flags;
2004 1.1 augustss
2005 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2006 1.264.4.21 skrll
2007 1.264.4.55 skrll DPRINTFN(8, "xfer=%p pipe=%p", xfer, xfer->ux_pipe, 0, 0);
2008 1.264.4.21 skrll DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d",
2009 1.264.4.55 skrll addr, UE_GET_ADDR(endpt), alen, xfer->ux_pipe->up_dev->ud_speed);
2010 1.248 mrg
2011 1.264.4.55 skrll ASSERT_SLEEPABLE();
2012 1.264.4.55 skrll KASSERT(sp);
2013 1.248 mrg
2014 1.264.4.55 skrll len = alen;
2015 1.264.4.55 skrll maxp = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize);
2016 1.1 augustss if (maxp == 0) {
2017 1.1 augustss printf("uhci_alloc_std_chain: maxp=0\n");
2018 1.264.4.13 skrll return USBD_INVAL;
2019 1.1 augustss }
2020 1.264.4.55 skrll size_t ntd = (len + maxp - 1) / maxp;
2021 1.73 augustss if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0)
2022 1.73 augustss ntd++;
2023 1.264.4.55 skrll DPRINTFN(10, "maxp=%d ntd=%d", maxp, ntd, 0, 0);
2024 1.264.4.21 skrll
2025 1.264.4.55 skrll uxfer->ux_stds = NULL;
2026 1.264.4.55 skrll uxfer->ux_nstd = ntd;
2027 1.73 augustss if (ntd == 0) {
2028 1.264.4.55 skrll *sp = NULL;
2029 1.264.4.55 skrll if (ep)
2030 1.264.4.55 skrll *ep = NULL;
2031 1.264.4.27 skrll DPRINTF("ntd=0", 0, 0, 0, 0);
2032 1.264.4.13 skrll return USBD_NORMAL_COMPLETION;
2033 1.73 augustss }
2034 1.264.4.55 skrll uxfer->ux_stds = kmem_alloc(sizeof(uhci_soft_td_t *) * ntd,
2035 1.264.4.55 skrll KM_SLEEP);
2036 1.264.4.55 skrll
2037 1.121 augustss lastp = NULL;
2038 1.1 augustss ntd--;
2039 1.33 augustss status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE);
2040 1.264.4.55 skrll if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_LOW)
2041 1.18 augustss status |= UHCI_TD_LS;
2042 1.73 augustss if (flags & USBD_SHORT_XFER_OK)
2043 1.18 augustss status |= UHCI_TD_SPD;
2044 1.1 augustss for (i = ntd; i >= 0; i--) {
2045 1.1 augustss p = uhci_alloc_std(sc);
2046 1.63 augustss if (p == NULL) {
2047 1.149 augustss uhci_free_std_chain(sc, lastp, NULL);
2048 1.264.4.13 skrll return USBD_NOMEM;
2049 1.1 augustss }
2050 1.264.4.55 skrll uxfer->ux_stds[i] = p;
2051 1.1 augustss if (i == ntd) {
2052 1.1 augustss /* last TD */
2053 1.1 augustss l = len % maxp;
2054 1.73 augustss if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER))
2055 1.73 augustss l = maxp;
2056 1.264.4.55 skrll if (ep)
2057 1.264.4.55 skrll *ep = p;
2058 1.264.4.55 skrll lastlink = UHCI_PTR_T;
2059 1.264.4.55 skrll } else {
2060 1.1 augustss l = maxp;
2061 1.264.4.55 skrll lastlink = p->physaddr;
2062 1.264.4.55 skrll }
2063 1.264.4.55 skrll p->link.std = lastp;
2064 1.264.4.55 skrll p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD);
2065 1.264.4.55 skrll p->td.td_status = htole32(status);
2066 1.264.4.55 skrll p->td.td_token = htole32(
2067 1.264.4.55 skrll (rd ? UHCI_TD_PID_IN : UHCI_TD_PID_OUT) |
2068 1.264.4.55 skrll UHCI_TD_SET_MAXLEN(l) |
2069 1.264.4.55 skrll UHCI_TD_SET_ENDPT(UE_GET_ADDR(endpt)) |
2070 1.264.4.55 skrll UHCI_TD_SET_DEVADDR(addr)
2071 1.264.4.55 skrll );
2072 1.160 augustss p->td.td_buffer = htole32(DMAADDR(dma, i * maxp));
2073 1.264.4.55 skrll DPRINTF("std %p link 0x%08x status 0x%08x token 0x%08x",
2074 1.264.4.55 skrll p, le32toh(p->td.td_link), le32toh(p->td.td_status),
2075 1.264.4.55 skrll le32toh(p->td.td_token));
2076 1.264.4.55 skrll
2077 1.264.4.55 skrll lastp = p;
2078 1.1 augustss }
2079 1.1 augustss *sp = lastp;
2080 1.264.4.21 skrll
2081 1.264.4.13 skrll return USBD_NORMAL_COMPLETION;
2082 1.1 augustss }
2083 1.1 augustss
2084 1.264.4.55 skrll Static void
2085 1.264.4.55 skrll uhci_free_stds(uhci_softc_t *sc, struct uhci_xfer *ux)
2086 1.264.4.55 skrll {
2087 1.264.4.55 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2088 1.264.4.55 skrll
2089 1.264.4.55 skrll DPRINTFN(8, "ux=%p", ux, 0, 0, 0);
2090 1.264.4.55 skrll
2091 1.264.4.55 skrll mutex_enter(&sc->sc_lock);
2092 1.264.4.55 skrll for (size_t i = 0; i < ux->ux_nstd; i++) {
2093 1.264.4.55 skrll uhci_soft_td_t *std = ux->ux_stds[i];
2094 1.264.4.55 skrll #ifdef DIAGNOSTIC
2095 1.264.4.55 skrll if (le32toh(std->td.td_token) == TD_IS_FREE) {
2096 1.264.4.55 skrll printf("uhci_free_std: freeing free TD %p\n", std);
2097 1.264.4.55 skrll return;
2098 1.264.4.55 skrll }
2099 1.264.4.55 skrll std->td.td_token = htole32(TD_IS_FREE);
2100 1.264.4.55 skrll #endif
2101 1.264.4.55 skrll ux->ux_stds[i]->link.std = sc->sc_freetds;
2102 1.264.4.55 skrll sc->sc_freetds = std;
2103 1.264.4.55 skrll }
2104 1.264.4.55 skrll mutex_exit(&sc->sc_lock);
2105 1.264.4.55 skrll }
2106 1.264.4.55 skrll
2107 1.264.4.55 skrll
2108 1.264.4.55 skrll Static void
2109 1.264.4.55 skrll uhci_reset_std_chain(uhci_softc_t *sc, struct usbd_xfer *xfer,
2110 1.264.4.58 skrll int length, int isread, int *toggle, uhci_soft_td_t **lstd)
2111 1.264.4.55 skrll {
2112 1.264.4.55 skrll struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
2113 1.264.4.55 skrll struct usbd_pipe *pipe = xfer->ux_pipe;
2114 1.264.4.55 skrll usb_dma_t *dma = &xfer->ux_dmabuf;
2115 1.264.4.55 skrll uint16_t flags = xfer->ux_flags;
2116 1.264.4.55 skrll uhci_soft_td_t *std, *prev;
2117 1.264.4.55 skrll int len = length;
2118 1.264.4.55 skrll int tog = *toggle;
2119 1.264.4.55 skrll int maxp;
2120 1.264.4.55 skrll uint32_t status;
2121 1.264.4.55 skrll size_t i;
2122 1.264.4.55 skrll
2123 1.264.4.55 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2124 1.264.4.55 skrll DPRINTFN(8, "xfer=%p len %d isread %d toggle %d", xfer,
2125 1.264.4.55 skrll len, isread, *toggle);
2126 1.264.4.55 skrll
2127 1.264.4.55 skrll KASSERT(len != 0 || (flags & USBD_FORCE_SHORT_XFER));
2128 1.264.4.55 skrll
2129 1.264.4.55 skrll maxp = UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize);
2130 1.264.4.55 skrll KASSERT(maxp != 0);
2131 1.264.4.55 skrll
2132 1.264.4.55 skrll status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE);
2133 1.264.4.55 skrll if (pipe->up_dev->ud_speed == USB_SPEED_LOW)
2134 1.264.4.55 skrll status |= UHCI_TD_LS;
2135 1.264.4.55 skrll if (flags & USBD_SHORT_XFER_OK)
2136 1.264.4.55 skrll status |= UHCI_TD_SPD;
2137 1.264.4.55 skrll usb_syncmem(dma, 0, len,
2138 1.264.4.55 skrll isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
2139 1.264.4.55 skrll
2140 1.264.4.55 skrll std = prev = NULL;
2141 1.264.4.55 skrll for (i = 0; i < uxfer->ux_nstd; i++, prev = std) {
2142 1.264.4.55 skrll int l = len;
2143 1.264.4.55 skrll std = uxfer->ux_stds[i];
2144 1.264.4.55 skrll if (l > maxp)
2145 1.264.4.55 skrll l = maxp;
2146 1.264.4.55 skrll if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER))
2147 1.264.4.55 skrll break;
2148 1.264.4.55 skrll
2149 1.264.4.55 skrll if (prev) {
2150 1.264.4.55 skrll prev->link.std = std;
2151 1.264.4.55 skrll prev->td.td_link = htole32(
2152 1.264.4.55 skrll std->physaddr | UHCI_PTR_VF | UHCI_PTR_TD
2153 1.264.4.55 skrll );
2154 1.264.4.55 skrll usb_syncmem(&prev->dma, prev->offs, sizeof(prev->td),
2155 1.264.4.55 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2156 1.264.4.55 skrll }
2157 1.264.4.55 skrll
2158 1.264.4.55 skrll int addr __diagused = xfer->ux_pipe->up_dev->ud_addr;
2159 1.264.4.55 skrll int endpt __diagused = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;
2160 1.264.4.55 skrll KASSERTMSG(UHCI_TD_GET_ENDPT(le32toh(std->td.td_token)) == UE_GET_ADDR(endpt),
2161 1.264.4.55 skrll "%" __PRIuBIT " vs %d (0x%08x) in %p",
2162 1.264.4.55 skrll UHCI_TD_GET_ENDPT(le32toh(std->td.td_token)),
2163 1.264.4.55 skrll UE_GET_ADDR(endpt), le32toh(std->td.td_token), std);
2164 1.264.4.55 skrll KASSERTMSG(UHCI_TD_GET_DEVADDR(le32toh(std->td.td_token)) == addr,
2165 1.264.4.55 skrll "%" __PRIuBIT " vs %d (0x%08x) in %p",
2166 1.264.4.55 skrll UHCI_TD_GET_DEVADDR(le32toh(std->td.td_token)), addr,
2167 1.264.4.55 skrll le32toh(std->td.td_token), std);
2168 1.264.4.55 skrll
2169 1.264.4.55 skrll usb_syncmem(&std->dma, std->offs, sizeof(std->td),
2170 1.264.4.55 skrll BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2171 1.264.4.55 skrll
2172 1.264.4.55 skrll std->td.td_status = htole32(status);
2173 1.264.4.55 skrll std->td.td_token &= ~htole32(
2174 1.264.4.55 skrll UHCI_TD_PID_MASK |
2175 1.264.4.55 skrll UHCI_TD_DT_MASK |
2176 1.264.4.55 skrll UHCI_TD_MAXLEN_MASK
2177 1.264.4.55 skrll );
2178 1.264.4.55 skrll std->td.td_token |= htole32(
2179 1.264.4.55 skrll UHCI_TD_SET_PID(isread ? UHCI_TD_PID_IN : UHCI_TD_PID_OUT) |
2180 1.264.4.55 skrll UHCI_TD_SET_DT(tog) |
2181 1.264.4.55 skrll UHCI_TD_SET_MAXLEN(l)
2182 1.264.4.55 skrll );
2183 1.264.4.55 skrll std->td.td_link &= ~htole32(UHCI_PTR_T);
2184 1.264.4.55 skrll
2185 1.264.4.55 skrll usb_syncmem(&std->dma, std->offs, sizeof(std->td),
2186 1.264.4.55 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2187 1.264.4.55 skrll tog ^= 1;
2188 1.264.4.55 skrll
2189 1.264.4.55 skrll len -= l;
2190 1.264.4.55 skrll if (len == 0)
2191 1.264.4.55 skrll break;
2192 1.264.4.55 skrll }
2193 1.264.4.55 skrll KASSERTMSG(len == 0, "xfer %p alen %d len %d mps %d ux_nqtd %zu i %zu",
2194 1.264.4.55 skrll xfer, length, len, maxp, uxfer->ux_nstd, i);
2195 1.264.4.55 skrll
2196 1.264.4.55 skrll if (i < uxfer->ux_nstd) {
2197 1.264.4.55 skrll /*
2198 1.264.4.55 skrll * The full allocation chain wasn't used, so we need to
2199 1.264.4.55 skrll * terminate it.
2200 1.264.4.55 skrll */
2201 1.264.4.55 skrll std->link.std = NULL;
2202 1.264.4.55 skrll std->td.td_link = htole32(UHCI_PTR_T);
2203 1.264.4.55 skrll usb_syncmem(&std->dma, std->offs, sizeof(std->td),
2204 1.264.4.55 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2205 1.264.4.55 skrll }
2206 1.264.4.55 skrll *lstd = std;
2207 1.264.4.55 skrll *toggle = tog;
2208 1.264.4.55 skrll }
2209 1.264.4.55 skrll
2210 1.38 augustss void
2211 1.264.4.25 skrll uhci_device_clear_toggle(struct usbd_pipe *pipe)
2212 1.38 augustss {
2213 1.264.4.50 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
2214 1.38 augustss upipe->nexttoggle = 0;
2215 1.38 augustss }
2216 1.38 augustss
2217 1.38 augustss void
2218 1.264.4.25 skrll uhci_noop(struct usbd_pipe *pipe)
2219 1.38 augustss {
2220 1.38 augustss }
2221 1.38 augustss
2222 1.264.4.55 skrll int
2223 1.264.4.55 skrll uhci_device_bulk_init(struct usbd_xfer *xfer)
2224 1.264.4.55 skrll {
2225 1.264.4.55 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2226 1.264.4.55 skrll struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
2227 1.264.4.55 skrll usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc;
2228 1.264.4.55 skrll int endpt = ed->bEndpointAddress;
2229 1.264.4.55 skrll int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2230 1.264.4.55 skrll int len = xfer->ux_bufsize;
2231 1.264.4.55 skrll int err = 0;
2232 1.264.4.55 skrll
2233 1.264.4.55 skrll
2234 1.264.4.55 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2235 1.264.4.55 skrll DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, len, xfer->ux_flags, 0);
2236 1.264.4.55 skrll
2237 1.264.4.55 skrll if (sc->sc_dying)
2238 1.264.4.55 skrll return USBD_IOERROR;
2239 1.264.4.55 skrll
2240 1.264.4.55 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
2241 1.264.4.55 skrll
2242 1.264.4.55 skrll uxfer->ux_type = UX_BULK;
2243 1.264.4.55 skrll err = uhci_alloc_std_chain(sc, xfer, len, isread, &uxfer->ux_stdstart,
2244 1.264.4.55 skrll &uxfer->ux_stdend);
2245 1.264.4.55 skrll if (err)
2246 1.264.4.55 skrll return err;
2247 1.264.4.55 skrll
2248 1.264.4.55 skrll #ifdef UHCI_DEBUG
2249 1.264.4.55 skrll if (uhcidebug >= 10) {
2250 1.264.4.55 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
2251 1.264.4.55 skrll uhci_dump_tds(uxfer->ux_stdstart);
2252 1.264.4.55 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
2253 1.264.4.55 skrll }
2254 1.264.4.55 skrll #endif
2255 1.264.4.55 skrll
2256 1.264.4.55 skrll return 0;
2257 1.264.4.55 skrll }
2258 1.264.4.55 skrll
2259 1.264.4.55 skrll Static void
2260 1.264.4.55 skrll uhci_device_bulk_fini(struct usbd_xfer *xfer)
2261 1.264.4.55 skrll {
2262 1.264.4.55 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2263 1.264.4.55 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
2264 1.264.4.55 skrll
2265 1.264.4.55 skrll KASSERT(ux->ux_type == UX_BULK);
2266 1.264.4.55 skrll
2267 1.264.4.55 skrll uhci_free_stds(sc, ux);
2268 1.264.4.55 skrll if (ux->ux_nstd)
2269 1.264.4.55 skrll kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd);
2270 1.264.4.55 skrll }
2271 1.264.4.55 skrll
2272 1.1 augustss usbd_status
2273 1.264.4.25 skrll uhci_device_bulk_transfer(struct usbd_xfer *xfer)
2274 1.1 augustss {
2275 1.264.4.37 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2276 1.63 augustss usbd_status err;
2277 1.16 augustss
2278 1.52 augustss /* Insert last in queue. */
2279 1.248 mrg mutex_enter(&sc->sc_lock);
2280 1.63 augustss err = usb_insert_transfer(xfer);
2281 1.248 mrg mutex_exit(&sc->sc_lock);
2282 1.63 augustss if (err)
2283 1.264.4.13 skrll return err;
2284 1.52 augustss
2285 1.152 augustss /*
2286 1.92 augustss * Pipe isn't running (otherwise err would be USBD_INPROG),
2287 1.92 augustss * so start it first.
2288 1.67 augustss */
2289 1.264.4.13 skrll return uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2290 1.16 augustss }
2291 1.16 augustss
2292 1.16 augustss usbd_status
2293 1.264.4.25 skrll uhci_device_bulk_start(struct usbd_xfer *xfer)
2294 1.16 augustss {
2295 1.264.4.50 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
2296 1.264.4.39 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
2297 1.264.4.37 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2298 1.55 augustss uhci_soft_td_t *data, *dataend;
2299 1.1 augustss uhci_soft_qh_t *sqh;
2300 1.264.4.55 skrll int len;
2301 1.264.4.55 skrll int endpt;
2302 1.264.4.55 skrll int isread;
2303 1.1 augustss
2304 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2305 1.264.4.55 skrll DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length,
2306 1.264.4.55 skrll xfer->ux_flags, 0);
2307 1.1 augustss
2308 1.82 augustss if (sc->sc_dying)
2309 1.264.4.13 skrll return USBD_IOERROR;
2310 1.82 augustss
2311 1.264.4.31 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
2312 1.264.4.55 skrll KASSERT(xfer->ux_length <= xfer->ux_bufsize);
2313 1.248 mrg
2314 1.264.4.7 skrll len = xfer->ux_length;
2315 1.264.4.7 skrll endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
2316 1.45 augustss isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2317 1.264.4.33 skrll sqh = upipe->bulk.sqh;
2318 1.1 augustss
2319 1.264.4.55 skrll /* Take lock here to protect nexttoggle */
2320 1.264.4.55 skrll mutex_enter(&sc->sc_lock);
2321 1.1 augustss
2322 1.264.4.55 skrll uhci_reset_std_chain(sc, xfer, len, isread, &upipe->nexttoggle,
2323 1.264.4.58 skrll &dataend);
2324 1.264.4.55 skrll
2325 1.264.4.55 skrll data = ux->ux_stdstart;
2326 1.264.4.55 skrll ux->ux_stdend = dataend;
2327 1.88 tsutsui dataend->td.td_status |= htole32(UHCI_TD_IOC);
2328 1.223 bouyer usb_syncmem(&dataend->dma,
2329 1.223 bouyer dataend->offs + offsetof(uhci_td_t, td_status),
2330 1.223 bouyer sizeof(dataend->td.td_status),
2331 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2332 1.223 bouyer
2333 1.59 augustss #ifdef UHCI_DEBUG
2334 1.264.4.55 skrll if (uhcidebug >= 10) {
2335 1.264.4.47 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
2336 1.264.4.55 skrll DPRINTFN(10, "before transfer", 0, 0, 0, 0);
2337 1.264.4.58 skrll uhci_dump_tds(data);
2338 1.264.4.47 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
2339 1.1 augustss }
2340 1.1 augustss #endif
2341 1.1 augustss
2342 1.264.4.41 skrll KASSERT(ux->ux_isdone);
2343 1.7 augustss #ifdef DIAGNOSTIC
2344 1.264.4.41 skrll ux->ux_isdone = false;
2345 1.7 augustss #endif
2346 1.1 augustss
2347 1.55 augustss sqh->elink = data;
2348 1.121 augustss sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD);
2349 1.223 bouyer /* uhci_add_bulk() will do usb_syncmem(sqh) */
2350 1.1 augustss
2351 1.1 augustss uhci_add_bulk(sc, sqh);
2352 1.264.4.56 skrll uhci_add_intr_list(sc, ux);
2353 1.1 augustss
2354 1.264.4.7 skrll if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
2355 1.264.4.7 skrll callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
2356 1.264.4.39 skrll uhci_timeout, xfer);
2357 1.13 augustss }
2358 1.264.4.7 skrll xfer->ux_status = USBD_IN_PROGRESS;
2359 1.264.4.55 skrll mutex_exit(&sc->sc_lock);
2360 1.1 augustss
2361 1.264.4.7 skrll if (sc->sc_bus.ub_usepolling)
2362 1.63 augustss uhci_waitintr(sc, xfer);
2363 1.26 augustss
2364 1.264.4.13 skrll return USBD_IN_PROGRESS;
2365 1.1 augustss }
2366 1.1 augustss
2367 1.1 augustss /* Abort a device bulk request. */
2368 1.1 augustss void
2369 1.264.4.25 skrll uhci_device_bulk_abort(struct usbd_xfer *xfer)
2370 1.1 augustss {
2371 1.264.4.37 skrll uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer);
2372 1.248 mrg
2373 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2374 1.248 mrg
2375 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2376 1.264.4.21 skrll
2377 1.66 augustss uhci_abort_xfer(xfer, USBD_CANCELLED);
2378 1.33 augustss }
2379 1.33 augustss
2380 1.92 augustss /*
2381 1.154 augustss * Abort a device request.
2382 1.154 augustss * If this routine is called at splusb() it guarantees that the request
2383 1.154 augustss * will be removed from the hardware scheduling and that the callback
2384 1.154 augustss * for it will be called with USBD_CANCELLED status.
2385 1.154 augustss * It's impossible to guarantee that the requested transfer will not
2386 1.154 augustss * have happened since the hardware runs concurrently.
2387 1.154 augustss * If the transaction has already happened we rely on the ordinary
2388 1.154 augustss * interrupt processing to process it.
2389 1.248 mrg * XXX This is most probably wrong.
2390 1.248 mrg * XXXMRG this doesn't make sense anymore.
2391 1.92 augustss */
2392 1.33 augustss void
2393 1.264.4.25 skrll uhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status)
2394 1.33 augustss {
2395 1.264.4.39 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
2396 1.264.4.50 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
2397 1.264.4.37 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2398 1.33 augustss uhci_soft_td_t *std;
2399 1.188 augustss int wake;
2400 1.65 augustss
2401 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2402 1.264.4.21 skrll DPRINTFN(1,"xfer=%p, status=%d", xfer, status, 0, 0);
2403 1.33 augustss
2404 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2405 1.264.4.3 skrll ASSERT_SLEEPABLE();
2406 1.248 mrg
2407 1.153 augustss if (sc->sc_dying) {
2408 1.153 augustss /* If we're dying, just do the software part. */
2409 1.264.4.7 skrll xfer->ux_status = status; /* make software ignore it */
2410 1.264.4.7 skrll callout_stop(&xfer->ux_callout);
2411 1.153 augustss usb_transfer_complete(xfer);
2412 1.194 christos return;
2413 1.92 augustss }
2414 1.92 augustss
2415 1.153 augustss /*
2416 1.188 augustss * If an abort is already in progress then just wait for it to
2417 1.188 augustss * complete and return.
2418 1.188 augustss */
2419 1.264.4.7 skrll if (xfer->ux_hcflags & UXFER_ABORTING) {
2420 1.264.4.21 skrll DPRINTFN(2, "already aborting", 0, 0, 0, 0);
2421 1.188 augustss #ifdef DIAGNOSTIC
2422 1.188 augustss if (status == USBD_TIMEOUT)
2423 1.188 augustss printf("uhci_abort_xfer: TIMEOUT while aborting\n");
2424 1.188 augustss #endif
2425 1.188 augustss /* Override the status which might be USBD_TIMEOUT. */
2426 1.264.4.7 skrll xfer->ux_status = status;
2427 1.264.4.21 skrll DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0);
2428 1.264.4.7 skrll xfer->ux_hcflags |= UXFER_ABORTWAIT;
2429 1.264.4.7 skrll while (xfer->ux_hcflags & UXFER_ABORTING)
2430 1.264.4.7 skrll cv_wait(&xfer->ux_hccv, &sc->sc_lock);
2431 1.248 mrg goto done;
2432 1.188 augustss }
2433 1.264.4.7 skrll xfer->ux_hcflags |= UXFER_ABORTING;
2434 1.188 augustss
2435 1.188 augustss /*
2436 1.153 augustss * Step 1: Make interrupt routine and hardware ignore xfer.
2437 1.153 augustss */
2438 1.264.4.7 skrll xfer->ux_status = status; /* make software ignore it */
2439 1.264.4.7 skrll callout_stop(&xfer->ux_callout);
2440 1.264.4.39 skrll DPRINTF("stop ux=%p", ux, 0, 0, 0);
2441 1.264.4.41 skrll for (std = ux->ux_stdstart; std != NULL; std = std->link.std) {
2442 1.223 bouyer usb_syncmem(&std->dma,
2443 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
2444 1.223 bouyer sizeof(std->td.td_status),
2445 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2446 1.92 augustss std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC));
2447 1.223 bouyer usb_syncmem(&std->dma,
2448 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
2449 1.223 bouyer sizeof(std->td.td_status),
2450 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2451 1.223 bouyer }
2452 1.92 augustss
2453 1.162 augustss /*
2454 1.153 augustss * Step 2: Wait until we know hardware has finished any possible
2455 1.153 augustss * use of the xfer. Also make sure the soft interrupt routine
2456 1.153 augustss * has run.
2457 1.153 augustss */
2458 1.248 mrg /* Hardware finishes in 1ms */
2459 1.264.4.7 skrll usb_delay_ms_locked(upipe->pipe.up_dev->ud_bus, 2, &sc->sc_lock);
2460 1.153 augustss sc->sc_softwake = 1;
2461 1.153 augustss usb_schedsoftintr(&sc->sc_bus);
2462 1.264.4.27 skrll DPRINTF("cv_wait", 0, 0, 0, 0);
2463 1.248 mrg cv_wait(&sc->sc_softwake_cv, &sc->sc_lock);
2464 1.162 augustss
2465 1.153 augustss /*
2466 1.153 augustss * Step 3: Execute callback.
2467 1.153 augustss */
2468 1.264.4.27 skrll DPRINTF("callback", 0, 0, 0, 0);
2469 1.100 augustss #ifdef DIAGNOSTIC
2470 1.264.4.41 skrll ux->ux_isdone = true;
2471 1.100 augustss #endif
2472 1.264.4.7 skrll wake = xfer->ux_hcflags & UXFER_ABORTWAIT;
2473 1.264.4.7 skrll xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT);
2474 1.106 augustss usb_transfer_complete(xfer);
2475 1.188 augustss if (wake)
2476 1.264.4.7 skrll cv_broadcast(&xfer->ux_hccv);
2477 1.248 mrg done:
2478 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2479 1.1 augustss }
2480 1.1 augustss
2481 1.1 augustss /* Close a device bulk pipe. */
2482 1.1 augustss void
2483 1.264.4.25 skrll uhci_device_bulk_close(struct usbd_pipe *pipe)
2484 1.1 augustss {
2485 1.264.4.50 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
2486 1.264.4.37 skrll uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
2487 1.1 augustss
2488 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2489 1.248 mrg
2490 1.264.4.33 skrll uhci_free_sqh(sc, upipe->bulk.sqh);
2491 1.236 drochner
2492 1.264.4.7 skrll pipe->up_endpoint->ue_toggle = upipe->nexttoggle;
2493 1.1 augustss }
2494 1.1 augustss
2495 1.264.4.55 skrll int
2496 1.264.4.55 skrll uhci_device_ctrl_init(struct usbd_xfer *xfer)
2497 1.1 augustss {
2498 1.264.4.55 skrll struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
2499 1.264.4.55 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
2500 1.264.4.55 skrll usb_device_request_t *req = &xfer->ux_request;
2501 1.264.4.55 skrll struct usbd_device *dev = upipe->pipe.up_dev;
2502 1.264.4.55 skrll uhci_softc_t *sc = dev->ud_bus->ub_hcpriv;
2503 1.264.4.55 skrll int addr = dev->ud_addr;
2504 1.264.4.55 skrll int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
2505 1.264.4.55 skrll uhci_soft_td_t *setup, *data, *stat, *next, *dataend;
2506 1.264.4.55 skrll int len;
2507 1.264.4.55 skrll uint32_t ls;
2508 1.63 augustss usbd_status err;
2509 1.264.4.55 skrll int isread;
2510 1.16 augustss
2511 1.264.4.55 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2512 1.264.4.55 skrll DPRINTFN(3, "len=%d, addr=%d, endpt=%d", xfer->ux_bufsize,
2513 1.264.4.55 skrll dev->ud_addr, endpt, 0);
2514 1.16 augustss
2515 1.264.4.55 skrll ls = dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0;
2516 1.264.4.55 skrll isread = req->bmRequestType & UT_READ;
2517 1.264.4.55 skrll len = xfer->ux_bufsize;
2518 1.1 augustss
2519 1.264.4.55 skrll uxfer->ux_type = UX_CTRL;
2520 1.264.4.55 skrll setup = upipe->ctrl.setup;
2521 1.264.4.55 skrll stat = upipe->ctrl.stat;
2522 1.82 augustss
2523 1.264.4.55 skrll /* Set up data transaction */
2524 1.264.4.55 skrll if (len != 0) {
2525 1.264.4.55 skrll err = uhci_alloc_std_chain(sc, xfer, len, isread, &data,
2526 1.264.4.55 skrll &dataend);
2527 1.264.4.55 skrll if (err)
2528 1.264.4.55 skrll return err;
2529 1.264.4.55 skrll next = data;
2530 1.264.4.55 skrll dataend->link.std = stat;
2531 1.264.4.55 skrll dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD);
2532 1.264.4.55 skrll } else {
2533 1.264.4.55 skrll next = stat;
2534 1.264.4.55 skrll }
2535 1.1 augustss
2536 1.264.4.55 skrll setup->link.std = next;
2537 1.264.4.55 skrll setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD);
2538 1.264.4.55 skrll setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls |
2539 1.264.4.55 skrll UHCI_TD_ACTIVE);
2540 1.264.4.55 skrll setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof(*req), endpt, addr));
2541 1.264.4.55 skrll setup->td.td_buffer = htole32(DMAADDR(&upipe->ctrl.reqdma, 0));
2542 1.1 augustss
2543 1.264.4.55 skrll stat->link.std = NULL;
2544 1.264.4.55 skrll stat->td.td_link = htole32(UHCI_PTR_T);
2545 1.264.4.55 skrll stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls |
2546 1.264.4.55 skrll UHCI_TD_ACTIVE | UHCI_TD_IOC);
2547 1.264.4.55 skrll stat->td.td_token =
2548 1.264.4.55 skrll htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) :
2549 1.264.4.55 skrll UHCI_TD_IN (0, endpt, addr, 1));
2550 1.264.4.55 skrll stat->td.td_buffer = htole32(0);
2551 1.264.4.55 skrll
2552 1.264.4.55 skrll DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0);
2553 1.264.4.55 skrll #ifdef UHCI_DEBUG
2554 1.264.4.55 skrll if (uhcidebug >= 10) {
2555 1.264.4.55 skrll DPRINTFN(10, "before transfer", 0, 0, 0, 0);
2556 1.264.4.55 skrll uhci_dump_tds(setup);
2557 1.264.4.55 skrll }
2558 1.264.4.55 skrll #endif
2559 1.264.4.55 skrll DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0);
2560 1.264.4.55 skrll
2561 1.264.4.55 skrll /* Set up interrupt info. */
2562 1.264.4.55 skrll uxfer->ux_setup = setup;
2563 1.264.4.55 skrll uxfer->ux_data = data;
2564 1.264.4.55 skrll uxfer->ux_stat = stat;
2565 1.264.4.55 skrll
2566 1.264.4.55 skrll return 0;
2567 1.264.4.55 skrll }
2568 1.264.4.55 skrll
2569 1.264.4.55 skrll Static void
2570 1.264.4.55 skrll uhci_device_ctrl_fini(struct usbd_xfer *xfer)
2571 1.264.4.55 skrll {
2572 1.264.4.55 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2573 1.264.4.55 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
2574 1.264.4.55 skrll
2575 1.264.4.55 skrll KASSERT(ux->ux_type == UX_CTRL);
2576 1.264.4.55 skrll
2577 1.264.4.55 skrll uhci_free_stds(sc, ux);
2578 1.264.4.55 skrll if (ux->ux_nstd)
2579 1.264.4.55 skrll kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd);
2580 1.264.4.55 skrll }
2581 1.264.4.55 skrll
2582 1.264.4.55 skrll usbd_status
2583 1.264.4.55 skrll uhci_device_ctrl_transfer(struct usbd_xfer *xfer)
2584 1.264.4.55 skrll {
2585 1.264.4.55 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2586 1.264.4.55 skrll usbd_status err;
2587 1.264.4.55 skrll
2588 1.264.4.55 skrll /* Insert last in queue. */
2589 1.264.4.55 skrll mutex_enter(&sc->sc_lock);
2590 1.264.4.55 skrll err = usb_insert_transfer(xfer);
2591 1.264.4.55 skrll mutex_exit(&sc->sc_lock);
2592 1.264.4.55 skrll if (err)
2593 1.264.4.55 skrll return err;
2594 1.264.4.55 skrll
2595 1.264.4.55 skrll /*
2596 1.264.4.55 skrll * Pipe isn't running (otherwise err would be USBD_INPROG),
2597 1.264.4.55 skrll * so start it first.
2598 1.264.4.55 skrll */
2599 1.264.4.55 skrll return uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2600 1.264.4.55 skrll }
2601 1.264.4.55 skrll
2602 1.264.4.55 skrll usbd_status
2603 1.264.4.55 skrll uhci_device_ctrl_start(struct usbd_xfer *xfer)
2604 1.264.4.55 skrll {
2605 1.264.4.55 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2606 1.264.4.55 skrll struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
2607 1.264.4.55 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
2608 1.264.4.55 skrll usb_device_request_t *req = &xfer->ux_request;
2609 1.264.4.55 skrll struct usbd_device *dev = upipe->pipe.up_dev;
2610 1.264.4.55 skrll int addr = dev->ud_addr;
2611 1.264.4.55 skrll int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
2612 1.264.4.55 skrll uhci_soft_td_t *setup, *stat, *next, *dataend;
2613 1.264.4.55 skrll uhci_soft_qh_t *sqh;
2614 1.264.4.55 skrll int len;
2615 1.264.4.55 skrll uint32_t ls;
2616 1.264.4.55 skrll int isread;
2617 1.264.4.55 skrll
2618 1.264.4.55 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2619 1.264.4.55 skrll
2620 1.264.4.55 skrll if (sc->sc_dying)
2621 1.264.4.55 skrll return USBD_IOERROR;
2622 1.264.4.55 skrll
2623 1.264.4.55 skrll KASSERT(xfer->ux_rqflags & URQ_REQUEST);
2624 1.264.4.55 skrll
2625 1.264.4.55 skrll DPRINTFN(3, "type=0x%02x, request=0x%02x, "
2626 1.264.4.55 skrll "wValue=0x%04x, wIndex=0x%04x",
2627 1.264.4.55 skrll req->bmRequestType, req->bRequest, UGETW(req->wValue),
2628 1.264.4.55 skrll UGETW(req->wIndex));
2629 1.264.4.55 skrll DPRINTFN(3, "len=%d, addr=%d, endpt=%d",
2630 1.264.4.55 skrll UGETW(req->wLength), dev->ud_addr, endpt, 0);
2631 1.264.4.55 skrll
2632 1.264.4.55 skrll ls = dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0;
2633 1.264.4.55 skrll isread = req->bmRequestType & UT_READ;
2634 1.264.4.55 skrll len = UGETW(req->wLength);
2635 1.264.4.55 skrll
2636 1.264.4.55 skrll setup = upipe->ctrl.setup;
2637 1.264.4.55 skrll stat = upipe->ctrl.stat;
2638 1.264.4.55 skrll sqh = upipe->ctrl.sqh;
2639 1.264.4.55 skrll
2640 1.264.4.55 skrll memcpy(KERNADDR(&upipe->ctrl.reqdma, 0), req, sizeof(*req));
2641 1.264.4.55 skrll usb_syncmem(&upipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE);
2642 1.264.4.55 skrll
2643 1.264.4.55 skrll mutex_enter(&sc->sc_lock);
2644 1.264.4.55 skrll
2645 1.264.4.55 skrll /* Set up data transaction */
2646 1.264.4.55 skrll if (len != 0) {
2647 1.264.4.55 skrll upipe->nexttoggle = 1;
2648 1.264.4.55 skrll next = uxfer->ux_data;
2649 1.264.4.55 skrll uhci_reset_std_chain(sc, xfer, len, isread,
2650 1.264.4.58 skrll &upipe->nexttoggle, &dataend);
2651 1.264.4.55 skrll dataend->link.std = stat;
2652 1.264.4.55 skrll dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD);
2653 1.264.4.55 skrll usb_syncmem(&dataend->dma,
2654 1.264.4.55 skrll dataend->offs + offsetof(uhci_td_t, td_link),
2655 1.264.4.55 skrll sizeof(dataend->td.td_link),
2656 1.264.4.55 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2657 1.264.4.55 skrll } else {
2658 1.264.4.55 skrll next = stat;
2659 1.264.4.55 skrll }
2660 1.264.4.55 skrll
2661 1.264.4.55 skrll setup->link.std = next;
2662 1.264.4.55 skrll setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD);
2663 1.264.4.55 skrll setup->td.td_status |= htole32(
2664 1.264.4.55 skrll UHCI_TD_SET_ERRCNT(3) |
2665 1.264.4.55 skrll ls |
2666 1.264.4.55 skrll UHCI_TD_ACTIVE
2667 1.264.4.55 skrll );
2668 1.264.4.55 skrll setup->td.td_token &= ~htole32(UHCI_TD_MAXLEN_MASK);
2669 1.264.4.55 skrll setup->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(sizeof(*req)));
2670 1.264.4.55 skrll usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td),
2671 1.264.4.55 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2672 1.264.4.55 skrll
2673 1.264.4.55 skrll stat->link.std = NULL;
2674 1.264.4.55 skrll stat->td.td_link = htole32(UHCI_PTR_T);
2675 1.264.4.55 skrll stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls |
2676 1.264.4.55 skrll UHCI_TD_ACTIVE | UHCI_TD_IOC);
2677 1.264.4.55 skrll stat->td.td_token =
2678 1.264.4.55 skrll htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) :
2679 1.264.4.55 skrll UHCI_TD_IN (0, endpt, addr, 1));
2680 1.264.4.55 skrll stat->td.td_buffer = htole32(0);
2681 1.264.4.55 skrll usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td),
2682 1.264.4.55 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2683 1.264.4.55 skrll
2684 1.264.4.55 skrll #ifdef UHCI_DEBUG
2685 1.264.4.55 skrll if (uhcidebug >= 10) {
2686 1.264.4.55 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
2687 1.264.4.55 skrll DPRINTF("before transfer", 0, 0, 0, 0);
2688 1.264.4.55 skrll uhci_dump_tds(setup);
2689 1.264.4.55 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
2690 1.264.4.55 skrll }
2691 1.264.4.55 skrll #endif
2692 1.264.4.55 skrll
2693 1.264.4.55 skrll /* Set up interrupt info. */
2694 1.264.4.55 skrll uxfer->ux_setup = setup;
2695 1.264.4.55 skrll uxfer->ux_stat = stat;
2696 1.264.4.55 skrll KASSERT(uxfer->ux_isdone);
2697 1.264.4.55 skrll #ifdef DIAGNOSTIC
2698 1.264.4.55 skrll uxfer->ux_isdone = false;
2699 1.264.4.55 skrll #endif
2700 1.264.4.55 skrll
2701 1.264.4.55 skrll sqh->elink = setup;
2702 1.264.4.55 skrll sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD);
2703 1.264.4.55 skrll /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */
2704 1.264.4.55 skrll
2705 1.264.4.55 skrll if (dev->ud_speed == USB_SPEED_LOW)
2706 1.264.4.55 skrll uhci_add_ls_ctrl(sc, sqh);
2707 1.264.4.55 skrll else
2708 1.264.4.55 skrll uhci_add_hs_ctrl(sc, sqh);
2709 1.264.4.56 skrll uhci_add_intr_list(sc, uxfer);
2710 1.264.4.55 skrll #ifdef UHCI_DEBUG
2711 1.264.4.55 skrll if (uhcidebug >= 12) {
2712 1.264.4.55 skrll uhci_soft_td_t *std;
2713 1.264.4.55 skrll uhci_soft_qh_t *xqh;
2714 1.264.4.55 skrll uhci_soft_qh_t *sxqh;
2715 1.264.4.55 skrll int maxqh = 0;
2716 1.264.4.55 skrll uhci_physaddr_t link;
2717 1.264.4.55 skrll DPRINTFN(12, "--- dump start ---", 0, 0, 0, 0);
2718 1.264.4.55 skrll DPRINTFN(12, "follow from [0]", 0, 0, 0, 0);
2719 1.264.4.55 skrll for (std = sc->sc_vframes[0].htd, link = 0;
2720 1.264.4.55 skrll (link & UHCI_PTR_QH) == 0;
2721 1.264.4.55 skrll std = std->link.std) {
2722 1.264.4.55 skrll link = le32toh(std->td.td_link);
2723 1.264.4.55 skrll uhci_dump_td(std);
2724 1.264.4.55 skrll }
2725 1.264.4.55 skrll sxqh = (uhci_soft_qh_t *)std;
2726 1.264.4.55 skrll uhci_dump_qh(sxqh);
2727 1.264.4.55 skrll for (xqh = sxqh;
2728 1.264.4.55 skrll xqh != NULL;
2729 1.264.4.55 skrll xqh = (maxqh++ == 5 || xqh->hlink == sxqh ||
2730 1.264.4.55 skrll xqh->hlink == xqh ? NULL : xqh->hlink)) {
2731 1.264.4.55 skrll uhci_dump_qh(xqh);
2732 1.264.4.55 skrll }
2733 1.264.4.55 skrll DPRINTFN(12, "Enqueued QH:", 0, 0, 0, 0);
2734 1.264.4.55 skrll uhci_dump_qh(sqh);
2735 1.264.4.55 skrll uhci_dump_tds(sqh->elink);
2736 1.264.4.55 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
2737 1.264.4.55 skrll }
2738 1.264.4.55 skrll #endif
2739 1.264.4.55 skrll if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
2740 1.264.4.55 skrll callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
2741 1.264.4.55 skrll uhci_timeout, xfer);
2742 1.264.4.55 skrll }
2743 1.264.4.55 skrll xfer->ux_status = USBD_IN_PROGRESS;
2744 1.264.4.55 skrll mutex_exit(&sc->sc_lock);
2745 1.264.4.55 skrll
2746 1.264.4.55 skrll if (sc->sc_bus.ub_usepolling)
2747 1.63 augustss uhci_waitintr(sc, xfer);
2748 1.264.4.55 skrll
2749 1.264.4.13 skrll return USBD_IN_PROGRESS;
2750 1.1 augustss }
2751 1.1 augustss
2752 1.264.4.55 skrll int
2753 1.264.4.55 skrll uhci_device_intr_init(struct usbd_xfer *xfer)
2754 1.264.4.55 skrll {
2755 1.264.4.55 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2756 1.264.4.55 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
2757 1.264.4.55 skrll usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc;
2758 1.264.4.55 skrll int endpt = ed->bEndpointAddress;
2759 1.264.4.55 skrll int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2760 1.264.4.55 skrll int len = xfer->ux_bufsize;
2761 1.264.4.55 skrll int err;
2762 1.264.4.55 skrll
2763 1.264.4.55 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2764 1.264.4.55 skrll
2765 1.264.4.55 skrll DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length,
2766 1.264.4.55 skrll xfer->ux_flags, 0);
2767 1.264.4.55 skrll
2768 1.264.4.55 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
2769 1.264.4.55 skrll KASSERT(len != 0);
2770 1.264.4.55 skrll
2771 1.264.4.55 skrll ux->ux_type = UX_INTR;
2772 1.264.4.55 skrll ux->ux_nstd = 0;
2773 1.264.4.55 skrll err = uhci_alloc_std_chain(sc, xfer, len, isread,
2774 1.264.4.55 skrll &ux->ux_stdstart, &ux->ux_stdend);
2775 1.264.4.55 skrll
2776 1.264.4.55 skrll return err;
2777 1.264.4.55 skrll }
2778 1.264.4.55 skrll
2779 1.264.4.55 skrll Static void
2780 1.264.4.55 skrll uhci_device_intr_fini(struct usbd_xfer *xfer)
2781 1.264.4.55 skrll {
2782 1.264.4.55 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2783 1.264.4.55 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
2784 1.264.4.55 skrll
2785 1.264.4.55 skrll KASSERT(ux->ux_type == UX_INTR);
2786 1.264.4.55 skrll
2787 1.264.4.55 skrll uhci_free_stds(sc, ux);
2788 1.264.4.55 skrll if (ux->ux_nstd)
2789 1.264.4.55 skrll kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd);
2790 1.264.4.55 skrll }
2791 1.264.4.55 skrll
2792 1.1 augustss usbd_status
2793 1.264.4.25 skrll uhci_device_intr_transfer(struct usbd_xfer *xfer)
2794 1.1 augustss {
2795 1.264.4.37 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2796 1.63 augustss usbd_status err;
2797 1.16 augustss
2798 1.52 augustss /* Insert last in queue. */
2799 1.248 mrg mutex_enter(&sc->sc_lock);
2800 1.63 augustss err = usb_insert_transfer(xfer);
2801 1.248 mrg mutex_exit(&sc->sc_lock);
2802 1.63 augustss if (err)
2803 1.264.4.13 skrll return err;
2804 1.52 augustss
2805 1.152 augustss /*
2806 1.92 augustss * Pipe isn't running (otherwise err would be USBD_INPROG),
2807 1.92 augustss * so start it first.
2808 1.67 augustss */
2809 1.264.4.13 skrll return uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2810 1.16 augustss }
2811 1.16 augustss
2812 1.16 augustss usbd_status
2813 1.264.4.25 skrll uhci_device_intr_start(struct usbd_xfer *xfer)
2814 1.16 augustss {
2815 1.264.4.39 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
2816 1.264.4.50 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
2817 1.264.4.37 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2818 1.55 augustss uhci_soft_td_t *data, *dataend;
2819 1.1 augustss uhci_soft_qh_t *sqh;
2820 1.187 skrll int isread, endpt;
2821 1.248 mrg int i;
2822 1.1 augustss
2823 1.82 augustss if (sc->sc_dying)
2824 1.264.4.13 skrll return USBD_IOERROR;
2825 1.82 augustss
2826 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2827 1.264.4.21 skrll
2828 1.264.4.55 skrll DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length,
2829 1.264.4.55 skrll xfer->ux_flags, 0);
2830 1.1 augustss
2831 1.264.4.31 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
2832 1.264.4.55 skrll KASSERT(xfer->ux_length <= xfer->ux_bufsize);
2833 1.248 mrg
2834 1.264.4.7 skrll endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
2835 1.187 skrll isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2836 1.187 skrll
2837 1.264.4.55 skrll data = ux->ux_stdstart;
2838 1.187 skrll
2839 1.264.4.55 skrll KASSERT(ux->ux_isdone);
2840 1.264.4.55 skrll #ifdef DIAGNOSTIC
2841 1.264.4.55 skrll ux->ux_isdone = false;
2842 1.264.4.55 skrll #endif
2843 1.264.4.55 skrll
2844 1.264.4.55 skrll /* Take lock to protect nexttoggle */
2845 1.264.4.55 skrll mutex_enter(&sc->sc_lock);
2846 1.264.4.55 skrll uhci_reset_std_chain(sc, xfer, xfer->ux_length, isread,
2847 1.264.4.58 skrll &upipe->nexttoggle, &dataend);
2848 1.248 mrg
2849 1.88 tsutsui dataend->td.td_status |= htole32(UHCI_TD_IOC);
2850 1.223 bouyer usb_syncmem(&dataend->dma,
2851 1.223 bouyer dataend->offs + offsetof(uhci_td_t, td_status),
2852 1.223 bouyer sizeof(dataend->td.td_status),
2853 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2854 1.264.4.55 skrll ux->ux_stdend = dataend;
2855 1.1 augustss
2856 1.59 augustss #ifdef UHCI_DEBUG
2857 1.264.4.43 skrll if (uhcidebug >= 10) {
2858 1.264.4.47 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
2859 1.55 augustss uhci_dump_tds(data);
2860 1.264.4.33 skrll uhci_dump_qh(upipe->intr.qhs[0]);
2861 1.264.4.47 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
2862 1.1 augustss }
2863 1.1 augustss #endif
2864 1.1 augustss
2865 1.264.4.33 skrll DPRINTFN(10, "qhs[0]=%p", upipe->intr.qhs[0], 0, 0, 0);
2866 1.264.4.33 skrll for (i = 0; i < upipe->intr.npoll; i++) {
2867 1.264.4.33 skrll sqh = upipe->intr.qhs[i];
2868 1.55 augustss sqh->elink = data;
2869 1.121 augustss sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD);
2870 1.223 bouyer usb_syncmem(&sqh->dma,
2871 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
2872 1.223 bouyer sizeof(sqh->qh.qh_elink),
2873 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2874 1.1 augustss }
2875 1.264.4.56 skrll uhci_add_intr_list(sc, ux);
2876 1.264.4.7 skrll xfer->ux_status = USBD_IN_PROGRESS;
2877 1.248 mrg mutex_exit(&sc->sc_lock);
2878 1.1 augustss
2879 1.59 augustss #ifdef UHCI_DEBUG
2880 1.264.4.43 skrll if (uhcidebug >= 10) {
2881 1.264.4.47 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
2882 1.55 augustss uhci_dump_tds(data);
2883 1.264.4.33 skrll uhci_dump_qh(upipe->intr.qhs[0]);
2884 1.264.4.47 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
2885 1.1 augustss }
2886 1.1 augustss #endif
2887 1.1 augustss
2888 1.264.4.13 skrll return USBD_IN_PROGRESS;
2889 1.1 augustss }
2890 1.1 augustss
2891 1.1 augustss /* Abort a device control request. */
2892 1.1 augustss void
2893 1.264.4.25 skrll uhci_device_ctrl_abort(struct usbd_xfer *xfer)
2894 1.1 augustss {
2895 1.264.4.37 skrll uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer);
2896 1.248 mrg
2897 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2898 1.248 mrg
2899 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2900 1.66 augustss uhci_abort_xfer(xfer, USBD_CANCELLED);
2901 1.1 augustss }
2902 1.1 augustss
2903 1.1 augustss /* Close a device control pipe. */
2904 1.1 augustss void
2905 1.264.4.25 skrll uhci_device_ctrl_close(struct usbd_pipe *pipe)
2906 1.1 augustss {
2907 1.264.4.55 skrll uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
2908 1.264.4.55 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
2909 1.264.4.55 skrll
2910 1.264.4.55 skrll uhci_free_sqh(sc, upipe->ctrl.sqh);
2911 1.264.4.55 skrll uhci_free_std_locked(sc, upipe->ctrl.setup);
2912 1.264.4.55 skrll uhci_free_std_locked(sc, upipe->ctrl.stat);
2913 1.264.4.55 skrll
2914 1.1 augustss }
2915 1.1 augustss
2916 1.1 augustss /* Abort a device interrupt request. */
2917 1.1 augustss void
2918 1.264.4.25 skrll uhci_device_intr_abort(struct usbd_xfer *xfer)
2919 1.1 augustss {
2920 1.264.4.37 skrll uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer);
2921 1.248 mrg
2922 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2923 1.264.4.7 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
2924 1.248 mrg
2925 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2926 1.264.4.27 skrll DPRINTF("xfer=%p", xfer, 0, 0, 0);
2927 1.264 skrll
2928 1.66 augustss uhci_abort_xfer(xfer, USBD_CANCELLED);
2929 1.1 augustss }
2930 1.1 augustss
2931 1.1 augustss /* Close a device interrupt pipe. */
2932 1.1 augustss void
2933 1.264.4.25 skrll uhci_device_intr_close(struct usbd_pipe *pipe)
2934 1.1 augustss {
2935 1.264.4.50 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
2936 1.264.4.37 skrll uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
2937 1.92 augustss int i, npoll;
2938 1.248 mrg
2939 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2940 1.1 augustss
2941 1.1 augustss /* Unlink descriptors from controller data structures. */
2942 1.264.4.33 skrll npoll = upipe->intr.npoll;
2943 1.1 augustss for (i = 0; i < npoll; i++)
2944 1.264.4.33 skrll uhci_remove_intr(sc, upipe->intr.qhs[i]);
2945 1.1 augustss
2946 1.152 augustss /*
2947 1.1 augustss * We now have to wait for any activity on the physical
2948 1.1 augustss * descriptors to stop.
2949 1.1 augustss */
2950 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock);
2951 1.1 augustss
2952 1.264.4.54 skrll for (i = 0; i < npoll; i++)
2953 1.264.4.33 skrll uhci_free_sqh(sc, upipe->intr.qhs[i]);
2954 1.264.4.33 skrll kmem_free(upipe->intr.qhs, npoll * sizeof(uhci_soft_qh_t *));
2955 1.1 augustss }
2956 1.1 augustss
2957 1.264.4.55 skrll int
2958 1.264.4.55 skrll uhci_device_isoc_init(struct usbd_xfer *xfer)
2959 1.1 augustss {
2960 1.264.4.55 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
2961 1.1 augustss
2962 1.264.4.55 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
2963 1.264.4.55 skrll KASSERT(xfer->ux_nframes != 0);
2964 1.264.4.55 skrll KASSERT(ux->ux_isdone);
2965 1.1 augustss
2966 1.264.4.55 skrll ux->ux_type = UX_ISOC;
2967 1.264.4.55 skrll return 0;
2968 1.264.4.55 skrll }
2969 1.264.4.47 skrll
2970 1.264.4.55 skrll Static void
2971 1.264.4.55 skrll uhci_device_isoc_fini(struct usbd_xfer *xfer)
2972 1.264.4.55 skrll {
2973 1.264.4.55 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
2974 1.1 augustss
2975 1.264.4.55 skrll KASSERT(ux->ux_type == UX_ISOC);
2976 1.1 augustss }
2977 1.1 augustss
2978 1.16 augustss usbd_status
2979 1.264.4.25 skrll uhci_device_isoc_transfer(struct usbd_xfer *xfer)
2980 1.16 augustss {
2981 1.264.4.37 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2982 1.63 augustss usbd_status err;
2983 1.48 augustss
2984 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2985 1.264.4.21 skrll DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0);
2986 1.48 augustss
2987 1.48 augustss /* Put it on our queue, */
2988 1.248 mrg mutex_enter(&sc->sc_lock);
2989 1.63 augustss err = usb_insert_transfer(xfer);
2990 1.248 mrg mutex_exit(&sc->sc_lock);
2991 1.48 augustss
2992 1.48 augustss /* bail out on error, */
2993 1.63 augustss if (err && err != USBD_IN_PROGRESS)
2994 1.264.4.13 skrll return err;
2995 1.48 augustss
2996 1.48 augustss /* XXX should check inuse here */
2997 1.48 augustss
2998 1.48 augustss /* insert into schedule, */
2999 1.63 augustss uhci_device_isoc_enter(xfer);
3000 1.48 augustss
3001 1.102 augustss /* and start if the pipe wasn't running */
3002 1.67 augustss if (!err)
3003 1.264.4.7 skrll uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
3004 1.48 augustss
3005 1.264.4.13 skrll return err;
3006 1.48 augustss }
3007 1.48 augustss
3008 1.48 augustss void
3009 1.264.4.25 skrll uhci_device_isoc_enter(struct usbd_xfer *xfer)
3010 1.48 augustss {
3011 1.264.4.37 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
3012 1.264.4.55 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
3013 1.264.4.33 skrll struct isoc *isoc = &upipe->isoc;
3014 1.152 augustss uhci_soft_td_t *std;
3015 1.264.4.1 skrll uint32_t buf, len, status, offs;
3016 1.248 mrg int i, next, nframes;
3017 1.264.4.7 skrll int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN;
3018 1.48 augustss
3019 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3020 1.264.4.21 skrll DPRINTFN(5, "used=%d next=%d xfer=%p nframes=%d",
3021 1.264.4.33 skrll isoc->inuse, isoc->next, xfer, xfer->ux_nframes);
3022 1.48 augustss
3023 1.82 augustss if (sc->sc_dying)
3024 1.82 augustss return;
3025 1.82 augustss
3026 1.264.4.7 skrll if (xfer->ux_status == USBD_IN_PROGRESS) {
3027 1.48 augustss /* This request has already been entered into the frame list */
3028 1.96 augustss printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer);
3029 1.68 augustss /* XXX */
3030 1.48 augustss }
3031 1.48 augustss
3032 1.48 augustss #ifdef DIAGNOSTIC
3033 1.264.4.33 skrll if (isoc->inuse >= UHCI_VFRAMELIST_COUNT)
3034 1.48 augustss printf("uhci_device_isoc_enter: overflow!\n");
3035 1.19 augustss #endif
3036 1.16 augustss
3037 1.264.4.33 skrll next = isoc->next;
3038 1.48 augustss if (next == -1) {
3039 1.48 augustss /* Not in use yet, schedule it a few frames ahead. */
3040 1.48 augustss next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT;
3041 1.264.4.21 skrll DPRINTFN(2, "start next=%d", next, 0, 0, 0);
3042 1.48 augustss }
3043 1.48 augustss
3044 1.264.4.7 skrll xfer->ux_status = USBD_IN_PROGRESS;
3045 1.264.4.41 skrll UHCI_XFER2UXFER(xfer)->ux_curframe = next;
3046 1.48 augustss
3047 1.264.4.7 skrll buf = DMAADDR(&xfer->ux_dmabuf, 0);
3048 1.223 bouyer offs = 0;
3049 1.88 tsutsui status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) |
3050 1.88 tsutsui UHCI_TD_ACTIVE |
3051 1.88 tsutsui UHCI_TD_IOS);
3052 1.264.4.7 skrll nframes = xfer->ux_nframes;
3053 1.248 mrg mutex_enter(&sc->sc_lock);
3054 1.48 augustss for (i = 0; i < nframes; i++) {
3055 1.264.4.33 skrll std = isoc->stds[next];
3056 1.48 augustss if (++next >= UHCI_VFRAMELIST_COUNT)
3057 1.48 augustss next = 0;
3058 1.264.4.7 skrll len = xfer->ux_frlengths[i];
3059 1.88 tsutsui std->td.td_buffer = htole32(buf);
3060 1.264.4.7 skrll usb_syncmem(&xfer->ux_dmabuf, offs, len,
3061 1.223 bouyer rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
3062 1.48 augustss if (i == nframes - 1)
3063 1.88 tsutsui status |= UHCI_TD_IOC;
3064 1.88 tsutsui std->td.td_status = htole32(status);
3065 1.88 tsutsui std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK);
3066 1.88 tsutsui std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len));
3067 1.223 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
3068 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3069 1.59 augustss #ifdef UHCI_DEBUG
3070 1.264.4.43 skrll if (uhcidebug >= 5) {
3071 1.264.4.47 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
3072 1.264.4.27 skrll DPRINTF("TD %d", i, 0, 0, 0);
3073 1.48 augustss uhci_dump_td(std);
3074 1.264.4.47 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
3075 1.48 augustss }
3076 1.48 augustss #endif
3077 1.48 augustss buf += len;
3078 1.223 bouyer offs += len;
3079 1.48 augustss }
3080 1.264.4.33 skrll isoc->next = next;
3081 1.264.4.33 skrll isoc->inuse += xfer->ux_nframes;
3082 1.16 augustss
3083 1.248 mrg mutex_exit(&sc->sc_lock);
3084 1.16 augustss }
3085 1.16 augustss
3086 1.16 augustss usbd_status
3087 1.264.4.25 skrll uhci_device_isoc_start(struct usbd_xfer *xfer)
3088 1.16 augustss {
3089 1.264.4.50 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
3090 1.264.4.37 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
3091 1.264.4.39 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
3092 1.48 augustss uhci_soft_td_t *end;
3093 1.248 mrg int i;
3094 1.48 augustss
3095 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3096 1.264.4.21 skrll DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0);
3097 1.96 augustss
3098 1.248 mrg mutex_enter(&sc->sc_lock);
3099 1.248 mrg
3100 1.248 mrg if (sc->sc_dying) {
3101 1.248 mrg mutex_exit(&sc->sc_lock);
3102 1.264.4.13 skrll return USBD_IOERROR;
3103 1.248 mrg }
3104 1.82 augustss
3105 1.48 augustss #ifdef DIAGNOSTIC
3106 1.264.4.7 skrll if (xfer->ux_status != USBD_IN_PROGRESS)
3107 1.63 augustss printf("uhci_device_isoc_start: not in progress %p\n", xfer);
3108 1.48 augustss #endif
3109 1.48 augustss
3110 1.48 augustss /* Find the last TD */
3111 1.264.4.41 skrll i = UHCI_XFER2UXFER(xfer)->ux_curframe + xfer->ux_nframes;
3112 1.48 augustss if (i >= UHCI_VFRAMELIST_COUNT)
3113 1.48 augustss i -= UHCI_VFRAMELIST_COUNT;
3114 1.264.4.33 skrll end = upipe->isoc.stds[i];
3115 1.48 augustss
3116 1.264.4.31 skrll KASSERT(end != NULL);
3117 1.96 augustss
3118 1.48 augustss /* Set up interrupt info. */
3119 1.264.4.41 skrll ux->ux_stdstart = end;
3120 1.264.4.41 skrll ux->ux_stdend = end;
3121 1.264.4.31 skrll
3122 1.264.4.41 skrll KASSERT(ux->ux_isdone);
3123 1.48 augustss #ifdef DIAGNOSTIC
3124 1.264.4.41 skrll ux->ux_isdone = false;
3125 1.48 augustss #endif
3126 1.264.4.56 skrll uhci_add_intr_list(sc, ux);
3127 1.152 augustss
3128 1.248 mrg mutex_exit(&sc->sc_lock);
3129 1.48 augustss
3130 1.264.4.13 skrll return USBD_IN_PROGRESS;
3131 1.16 augustss }
3132 1.16 augustss
3133 1.16 augustss void
3134 1.264.4.25 skrll uhci_device_isoc_abort(struct usbd_xfer *xfer)
3135 1.16 augustss {
3136 1.264.4.37 skrll uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer);
3137 1.264.4.50 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
3138 1.264.4.33 skrll uhci_soft_td_t **stds = upipe->isoc.stds;
3139 1.48 augustss uhci_soft_td_t *std;
3140 1.248 mrg int i, n, nframes, maxlen, len;
3141 1.92 augustss
3142 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
3143 1.92 augustss
3144 1.92 augustss /* Transfer is already done. */
3145 1.264.4.7 skrll if (xfer->ux_status != USBD_NOT_STARTED &&
3146 1.264.4.7 skrll xfer->ux_status != USBD_IN_PROGRESS) {
3147 1.92 augustss return;
3148 1.92 augustss }
3149 1.48 augustss
3150 1.92 augustss /* Give xfer the requested abort code. */
3151 1.264.4.7 skrll xfer->ux_status = USBD_CANCELLED;
3152 1.48 augustss
3153 1.48 augustss /* make hardware ignore it, */
3154 1.264.4.7 skrll nframes = xfer->ux_nframes;
3155 1.264.4.41 skrll n = UHCI_XFER2UXFER(xfer)->ux_curframe;
3156 1.92 augustss maxlen = 0;
3157 1.48 augustss for (i = 0; i < nframes; i++) {
3158 1.48 augustss std = stds[n];
3159 1.223 bouyer usb_syncmem(&std->dma,
3160 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
3161 1.223 bouyer sizeof(std->td.td_status),
3162 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3163 1.88 tsutsui std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC));
3164 1.223 bouyer usb_syncmem(&std->dma,
3165 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
3166 1.223 bouyer sizeof(std->td.td_status),
3167 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3168 1.223 bouyer usb_syncmem(&std->dma,
3169 1.223 bouyer std->offs + offsetof(uhci_td_t, td_token),
3170 1.223 bouyer sizeof(std->td.td_token),
3171 1.223 bouyer BUS_DMASYNC_POSTWRITE);
3172 1.130 tsutsui len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token));
3173 1.92 augustss if (len > maxlen)
3174 1.92 augustss maxlen = len;
3175 1.48 augustss if (++n >= UHCI_VFRAMELIST_COUNT)
3176 1.48 augustss n = 0;
3177 1.48 augustss }
3178 1.48 augustss
3179 1.92 augustss /* and wait until we are sure the hardware has finished. */
3180 1.92 augustss delay(maxlen);
3181 1.92 augustss
3182 1.96 augustss #ifdef DIAGNOSTIC
3183 1.264.4.41 skrll UHCI_XFER2UXFER(xfer)->ux_isdone = true;
3184 1.96 augustss #endif
3185 1.92 augustss /* Run callback and remove from interrupt list. */
3186 1.92 augustss usb_transfer_complete(xfer);
3187 1.48 augustss
3188 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
3189 1.16 augustss }
3190 1.16 augustss
3191 1.16 augustss void
3192 1.264.4.25 skrll uhci_device_isoc_close(struct usbd_pipe *pipe)
3193 1.16 augustss {
3194 1.264.4.50 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
3195 1.264.4.37 skrll uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
3196 1.48 augustss uhci_soft_td_t *std, *vstd;
3197 1.264.4.33 skrll struct isoc *isoc;
3198 1.248 mrg int i;
3199 1.248 mrg
3200 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
3201 1.16 augustss
3202 1.16 augustss /*
3203 1.16 augustss * Make sure all TDs are marked as inactive.
3204 1.16 augustss * Wait for completion.
3205 1.16 augustss * Unschedule.
3206 1.16 augustss * Deallocate.
3207 1.16 augustss */
3208 1.264.4.33 skrll isoc = &upipe->isoc;
3209 1.16 augustss
3210 1.223 bouyer for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
3211 1.264.4.33 skrll std = isoc->stds[i];
3212 1.223 bouyer usb_syncmem(&std->dma,
3213 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
3214 1.223 bouyer sizeof(std->td.td_status),
3215 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3216 1.223 bouyer std->td.td_status &= htole32(~UHCI_TD_ACTIVE);
3217 1.223 bouyer usb_syncmem(&std->dma,
3218 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
3219 1.223 bouyer sizeof(std->td.td_status),
3220 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3221 1.223 bouyer }
3222 1.248 mrg /* wait for completion */
3223 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock);
3224 1.16 augustss
3225 1.16 augustss for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
3226 1.264.4.33 skrll std = isoc->stds[i];
3227 1.48 augustss for (vstd = sc->sc_vframes[i].htd;
3228 1.67 augustss vstd != NULL && vstd->link.std != std;
3229 1.42 augustss vstd = vstd->link.std)
3230 1.16 augustss ;
3231 1.67 augustss if (vstd == NULL) {
3232 1.16 augustss /*panic*/
3233 1.16 augustss printf("uhci_device_isoc_close: %p not found\n", std);
3234 1.248 mrg mutex_exit(&sc->sc_lock);
3235 1.16 augustss return;
3236 1.16 augustss }
3237 1.42 augustss vstd->link = std->link;
3238 1.223 bouyer usb_syncmem(&std->dma,
3239 1.223 bouyer std->offs + offsetof(uhci_td_t, td_link),
3240 1.223 bouyer sizeof(std->td.td_link),
3241 1.223 bouyer BUS_DMASYNC_POSTWRITE);
3242 1.42 augustss vstd->td.td_link = std->td.td_link;
3243 1.223 bouyer usb_syncmem(&vstd->dma,
3244 1.223 bouyer vstd->offs + offsetof(uhci_td_t, td_link),
3245 1.223 bouyer sizeof(vstd->td.td_link),
3246 1.223 bouyer BUS_DMASYNC_PREWRITE);
3247 1.264.4.55 skrll uhci_free_std_locked(sc, std);
3248 1.16 augustss }
3249 1.16 augustss
3250 1.264.4.35 skrll kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *));
3251 1.16 augustss }
3252 1.16 augustss
3253 1.16 augustss usbd_status
3254 1.264.4.25 skrll uhci_setup_isoc(struct usbd_pipe *pipe)
3255 1.16 augustss {
3256 1.264.4.50 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
3257 1.264.4.37 skrll uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
3258 1.264.4.7 skrll int addr = upipe->pipe.up_dev->ud_addr;
3259 1.264.4.7 skrll int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
3260 1.45 augustss int rd = UE_GET_DIR(endpt) == UE_DIR_IN;
3261 1.48 augustss uhci_soft_td_t *std, *vstd;
3262 1.264.4.1 skrll uint32_t token;
3263 1.264.4.33 skrll struct isoc *isoc;
3264 1.248 mrg int i;
3265 1.16 augustss
3266 1.264.4.33 skrll isoc = &upipe->isoc;
3267 1.264.4.55 skrll
3268 1.264.4.55 skrll isoc->stds = kmem_alloc(
3269 1.264.4.55 skrll UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *), KM_SLEEP);
3270 1.264.4.33 skrll if (isoc->stds == NULL)
3271 1.248 mrg return USBD_NOMEM;
3272 1.16 augustss
3273 1.88 tsutsui token = rd ? UHCI_TD_IN (0, endpt, addr, 0) :
3274 1.88 tsutsui UHCI_TD_OUT(0, endpt, addr, 0);
3275 1.16 augustss
3276 1.48 augustss /* Allocate the TDs and mark as inactive; */
3277 1.16 augustss for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
3278 1.48 augustss std = uhci_alloc_std(sc);
3279 1.48 augustss if (std == 0)
3280 1.48 augustss goto bad;
3281 1.88 tsutsui std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */
3282 1.88 tsutsui std->td.td_token = htole32(token);
3283 1.223 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
3284 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3285 1.264.4.33 skrll isoc->stds[i] = std;
3286 1.16 augustss }
3287 1.16 augustss
3288 1.264.4.55 skrll mutex_enter(&sc->sc_lock);
3289 1.264.4.55 skrll
3290 1.48 augustss /* Insert TDs into schedule. */
3291 1.16 augustss for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
3292 1.264.4.33 skrll std = isoc->stds[i];
3293 1.48 augustss vstd = sc->sc_vframes[i].htd;
3294 1.223 bouyer usb_syncmem(&vstd->dma,
3295 1.223 bouyer vstd->offs + offsetof(uhci_td_t, td_link),
3296 1.223 bouyer sizeof(vstd->td.td_link),
3297 1.223 bouyer BUS_DMASYNC_POSTWRITE);
3298 1.42 augustss std->link = vstd->link;
3299 1.42 augustss std->td.td_link = vstd->td.td_link;
3300 1.223 bouyer usb_syncmem(&std->dma,
3301 1.223 bouyer std->offs + offsetof(uhci_td_t, td_link),
3302 1.223 bouyer sizeof(std->td.td_link),
3303 1.223 bouyer BUS_DMASYNC_PREWRITE);
3304 1.42 augustss vstd->link.std = std;
3305 1.121 augustss vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD);
3306 1.223 bouyer usb_syncmem(&vstd->dma,
3307 1.223 bouyer vstd->offs + offsetof(uhci_td_t, td_link),
3308 1.223 bouyer sizeof(vstd->td.td_link),
3309 1.223 bouyer BUS_DMASYNC_PREWRITE);
3310 1.16 augustss }
3311 1.248 mrg mutex_exit(&sc->sc_lock);
3312 1.16 augustss
3313 1.264.4.33 skrll isoc->next = -1;
3314 1.264.4.33 skrll isoc->inuse = 0;
3315 1.48 augustss
3316 1.264.4.13 skrll return USBD_NORMAL_COMPLETION;
3317 1.16 augustss
3318 1.48 augustss bad:
3319 1.16 augustss while (--i >= 0)
3320 1.264.4.33 skrll uhci_free_std(sc, isoc->stds[i]);
3321 1.264.4.35 skrll kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *));
3322 1.264.4.13 skrll return USBD_NOMEM;
3323 1.16 augustss }
3324 1.16 augustss
3325 1.16 augustss void
3326 1.264.4.25 skrll uhci_device_isoc_done(struct usbd_xfer *xfer)
3327 1.16 augustss {
3328 1.264.4.50 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
3329 1.264.4.39 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
3330 1.264.4.39 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
3331 1.223 bouyer int i, offs;
3332 1.264.4.7 skrll int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN;
3333 1.223 bouyer
3334 1.48 augustss
3335 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3336 1.264.4.21 skrll DPRINTFN(4, "length=%d, ux_state=0x%08x",
3337 1.264.4.21 skrll xfer->ux_actlen, xfer->ux_state, 0, 0);
3338 1.93 augustss
3339 1.264.4.56 skrll if (!uhci_active_intr_list(ux))
3340 1.96 augustss return;
3341 1.96 augustss
3342 1.93 augustss #ifdef DIAGNOSTIC
3343 1.264.4.41 skrll if (ux->ux_stdend == NULL) {
3344 1.264.4.2 skrll printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer);
3345 1.93 augustss #ifdef UHCI_DEBUG
3346 1.264.4.47 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
3347 1.264.4.39 skrll uhci_dump_ii(ux);
3348 1.264.4.47 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
3349 1.93 augustss #endif
3350 1.93 augustss return;
3351 1.93 augustss }
3352 1.93 augustss #endif
3353 1.48 augustss
3354 1.48 augustss /* Turn off the interrupt since it is active even if the TD is not. */
3355 1.264.4.41 skrll usb_syncmem(&ux->ux_stdend->dma,
3356 1.264.4.41 skrll ux->ux_stdend->offs + offsetof(uhci_td_t, td_status),
3357 1.264.4.41 skrll sizeof(ux->ux_stdend->td.td_status),
3358 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3359 1.264.4.41 skrll ux->ux_stdend->td.td_status &= htole32(~UHCI_TD_IOC);
3360 1.264.4.41 skrll usb_syncmem(&ux->ux_stdend->dma,
3361 1.264.4.41 skrll ux->ux_stdend->offs + offsetof(uhci_td_t, td_status),
3362 1.264.4.41 skrll sizeof(ux->ux_stdend->td.td_status),
3363 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3364 1.48 augustss
3365 1.264.4.56 skrll uhci_del_intr_list(sc, ux); /* remove from active list */
3366 1.223 bouyer
3367 1.223 bouyer offs = 0;
3368 1.264.4.7 skrll for (i = 0; i < xfer->ux_nframes; i++) {
3369 1.264.4.7 skrll usb_syncmem(&xfer->ux_dmabuf, offs, xfer->ux_frlengths[i],
3370 1.223 bouyer rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
3371 1.264.4.7 skrll offs += xfer->ux_frlengths[i];
3372 1.223 bouyer }
3373 1.16 augustss }
3374 1.16 augustss
3375 1.1 augustss void
3376 1.264.4.25 skrll uhci_device_intr_done(struct usbd_xfer *xfer)
3377 1.1 augustss {
3378 1.264.4.38 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
3379 1.264.4.39 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
3380 1.264.4.50 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
3381 1.1 augustss uhci_soft_qh_t *sqh;
3382 1.264.4.55 skrll int i, npoll;
3383 1.1 augustss
3384 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3385 1.264.4.21 skrll DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0);
3386 1.1 augustss
3387 1.264.4.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
3388 1.248 mrg
3389 1.264.4.33 skrll npoll = upipe->intr.npoll;
3390 1.264.4.54 skrll for (i = 0; i < npoll; i++) {
3391 1.264.4.33 skrll sqh = upipe->intr.qhs[i];
3392 1.121 augustss sqh->elink = NULL;
3393 1.88 tsutsui sqh->qh.qh_elink = htole32(UHCI_PTR_T);
3394 1.223 bouyer usb_syncmem(&sqh->dma,
3395 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
3396 1.223 bouyer sizeof(sqh->qh.qh_elink),
3397 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3398 1.1 augustss }
3399 1.1 augustss
3400 1.264.4.7 skrll if (xfer->ux_pipe->up_repeat) {
3401 1.55 augustss uhci_soft_td_t *data, *dataend;
3402 1.264.4.55 skrll int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
3403 1.264.4.55 skrll int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3404 1.1 augustss
3405 1.264.4.55 skrll KASSERT(ux->ux_isdone);
3406 1.264.4.55 skrll #ifdef DIAGNOSTIC
3407 1.264.4.55 skrll ux->ux_isdone = false;
3408 1.264.4.55 skrll #endif
3409 1.264.4.21 skrll DPRINTFN(5, "re-queueing", 0, 0, 0, 0);
3410 1.92 augustss
3411 1.264.4.55 skrll data = ux->ux_stdstart;
3412 1.264.4.55 skrll uhci_reset_std_chain(sc, xfer, xfer->ux_length, isread,
3413 1.264.4.58 skrll &upipe->nexttoggle, &dataend);
3414 1.88 tsutsui dataend->td.td_status |= htole32(UHCI_TD_IOC);
3415 1.223 bouyer usb_syncmem(&dataend->dma,
3416 1.223 bouyer dataend->offs + offsetof(uhci_td_t, td_status),
3417 1.223 bouyer sizeof(dataend->td.td_status),
3418 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3419 1.1 augustss
3420 1.59 augustss #ifdef UHCI_DEBUG
3421 1.264.4.43 skrll if (uhcidebug >= 10) {
3422 1.264.4.47 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
3423 1.55 augustss uhci_dump_tds(data);
3424 1.264.4.33 skrll uhci_dump_qh(upipe->intr.qhs[0]);
3425 1.264.4.47 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
3426 1.1 augustss }
3427 1.1 augustss #endif
3428 1.1 augustss
3429 1.264.4.41 skrll ux->ux_stdend = dataend;
3430 1.1 augustss for (i = 0; i < npoll; i++) {
3431 1.264.4.33 skrll sqh = upipe->intr.qhs[i];
3432 1.55 augustss sqh->elink = data;
3433 1.121 augustss sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD);
3434 1.223 bouyer usb_syncmem(&sqh->dma,
3435 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
3436 1.223 bouyer sizeof(sqh->qh.qh_elink),
3437 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3438 1.1 augustss }
3439 1.264.4.7 skrll xfer->ux_status = USBD_IN_PROGRESS;
3440 1.264.4.39 skrll /* The ux is already on the examined list, just leave it. */
3441 1.1 augustss } else {
3442 1.264.4.21 skrll DPRINTFN(5, "removing", 0, 0, 0, 0);
3443 1.264.4.56 skrll if (uhci_active_intr_list(ux))
3444 1.264.4.56 skrll uhci_del_intr_list(sc, ux);
3445 1.1 augustss }
3446 1.1 augustss }
3447 1.1 augustss
3448 1.1 augustss /* Deallocate request data structures */
3449 1.1 augustss void
3450 1.264.4.25 skrll uhci_device_ctrl_done(struct usbd_xfer *xfer)
3451 1.1 augustss {
3452 1.264.4.38 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
3453 1.264.4.39 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
3454 1.264.4.50 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
3455 1.264.4.7 skrll int len = UGETW(xfer->ux_request.wLength);
3456 1.264.4.7 skrll int isread = (xfer->ux_request.bmRequestType & UT_READ);
3457 1.1 augustss
3458 1.264.4.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
3459 1.248 mrg
3460 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3461 1.264.4.31 skrll
3462 1.264.4.32 skrll KASSERT(xfer->ux_rqflags & URQ_REQUEST);
3463 1.1 augustss
3464 1.264.4.56 skrll if (!uhci_active_intr_list(ux))
3465 1.169 augustss return;
3466 1.169 augustss
3467 1.264.4.56 skrll uhci_del_intr_list(sc, ux); /* remove from active list */
3468 1.1 augustss
3469 1.264.4.7 skrll if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW)
3470 1.264.4.33 skrll uhci_remove_ls_ctrl(sc, upipe->ctrl.sqh);
3471 1.123 augustss else
3472 1.264.4.33 skrll uhci_remove_hs_ctrl(sc, upipe->ctrl.sqh);
3473 1.1 augustss
3474 1.223 bouyer if (len) {
3475 1.264.4.7 skrll usb_syncmem(&xfer->ux_dmabuf, 0, len,
3476 1.223 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
3477 1.223 bouyer }
3478 1.264.4.33 skrll usb_syncmem(&upipe->ctrl.reqdma, 0,
3479 1.223 bouyer sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE);
3480 1.223 bouyer
3481 1.264.4.27 skrll DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0);
3482 1.1 augustss }
3483 1.1 augustss
3484 1.1 augustss /* Deallocate request data structures */
3485 1.1 augustss void
3486 1.264.4.25 skrll uhci_device_bulk_done(struct usbd_xfer *xfer)
3487 1.1 augustss {
3488 1.264.4.39 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
3489 1.264.4.38 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
3490 1.264.4.50 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
3491 1.264.4.51 skrll usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc;
3492 1.264.4.51 skrll int endpt = ed->bEndpointAddress;
3493 1.264.4.51 skrll int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3494 1.169 augustss
3495 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3496 1.264.4.39 skrll DPRINTFN(5, "xfer=%p ux=%p sc=%p upipe=%p", xfer, ux, sc,
3497 1.264.4.21 skrll upipe);
3498 1.169 augustss
3499 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
3500 1.248 mrg
3501 1.264.4.56 skrll if (!uhci_active_intr_list(ux))
3502 1.169 augustss return;
3503 1.1 augustss
3504 1.264.4.56 skrll uhci_del_intr_list(sc, ux); /* remove from active list */
3505 1.1 augustss
3506 1.264.4.33 skrll uhci_remove_bulk(sc, upipe->bulk.sqh);
3507 1.32 augustss
3508 1.264.4.51 skrll if (xfer->ux_length) {
3509 1.264.4.51 skrll usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
3510 1.264.4.51 skrll isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
3511 1.264.4.51 skrll }
3512 1.32 augustss
3513 1.264.4.21 skrll DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0);
3514 1.1 augustss }
3515 1.1 augustss
3516 1.1 augustss /* Add interrupt QH, called with vflock. */
3517 1.1 augustss void
3518 1.119 augustss uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
3519 1.1 augustss {
3520 1.92 augustss struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos];
3521 1.42 augustss uhci_soft_qh_t *eqh;
3522 1.1 augustss
3523 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3524 1.264.4.21 skrll DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0);
3525 1.92 augustss
3526 1.42 augustss eqh = vf->eqh;
3527 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
3528 1.223 bouyer sizeof(eqh->qh.qh_hlink),
3529 1.223 bouyer BUS_DMASYNC_POSTWRITE);
3530 1.42 augustss sqh->hlink = eqh->hlink;
3531 1.42 augustss sqh->qh.qh_hlink = eqh->qh.qh_hlink;
3532 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
3533 1.223 bouyer sizeof(sqh->qh.qh_hlink),
3534 1.223 bouyer BUS_DMASYNC_PREWRITE);
3535 1.42 augustss eqh->hlink = sqh;
3536 1.121 augustss eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
3537 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
3538 1.223 bouyer sizeof(eqh->qh.qh_hlink),
3539 1.223 bouyer BUS_DMASYNC_PREWRITE);
3540 1.1 augustss vf->eqh = sqh;
3541 1.1 augustss vf->bandwidth++;
3542 1.1 augustss }
3543 1.1 augustss
3544 1.119 augustss /* Remove interrupt QH. */
3545 1.1 augustss void
3546 1.119 augustss uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
3547 1.1 augustss {
3548 1.92 augustss struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos];
3549 1.1 augustss uhci_soft_qh_t *pqh;
3550 1.1 augustss
3551 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3552 1.264.4.21 skrll DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0);
3553 1.1 augustss
3554 1.124 augustss /* See comment in uhci_remove_ctrl() */
3555 1.223 bouyer
3556 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
3557 1.223 bouyer sizeof(sqh->qh.qh_elink),
3558 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3559 1.124 augustss if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) {
3560 1.124 augustss sqh->qh.qh_elink = htole32(UHCI_PTR_T);
3561 1.223 bouyer usb_syncmem(&sqh->dma,
3562 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
3563 1.223 bouyer sizeof(sqh->qh.qh_elink),
3564 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3565 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
3566 1.124 augustss }
3567 1.124 augustss
3568 1.92 augustss pqh = uhci_find_prev_qh(vf->hqh, sqh);
3569 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
3570 1.223 bouyer sizeof(sqh->qh.qh_hlink),
3571 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3572 1.42 augustss pqh->hlink = sqh->hlink;
3573 1.42 augustss pqh->qh.qh_hlink = sqh->qh.qh_hlink;
3574 1.223 bouyer usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
3575 1.223 bouyer sizeof(pqh->qh.qh_hlink),
3576 1.223 bouyer BUS_DMASYNC_PREWRITE);
3577 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
3578 1.1 augustss if (vf->eqh == sqh)
3579 1.1 augustss vf->eqh = pqh;
3580 1.1 augustss vf->bandwidth--;
3581 1.1 augustss }
3582 1.1 augustss
3583 1.1 augustss usbd_status
3584 1.119 augustss uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival)
3585 1.1 augustss {
3586 1.1 augustss uhci_soft_qh_t *sqh;
3587 1.248 mrg int i, npoll;
3588 1.1 augustss u_int bestbw, bw, bestoffs, offs;
3589 1.1 augustss
3590 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3591 1.264.4.21 skrll DPRINTFN(2, "pipe=%p", upipe, 0, 0, 0);
3592 1.1 augustss if (ival == 0) {
3593 1.173 gson printf("uhci_device_setintr: 0 interval\n");
3594 1.264.4.13 skrll return USBD_INVAL;
3595 1.1 augustss }
3596 1.1 augustss
3597 1.1 augustss if (ival > UHCI_VFRAMELIST_COUNT)
3598 1.1 augustss ival = UHCI_VFRAMELIST_COUNT;
3599 1.1 augustss npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival;
3600 1.264.4.27 skrll DPRINTF("ival=%d npoll=%d", ival, npoll, 0, 0);
3601 1.1 augustss
3602 1.264.4.33 skrll upipe->intr.npoll = npoll;
3603 1.264.4.33 skrll upipe->intr.qhs =
3604 1.248 mrg kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP);
3605 1.264.4.33 skrll if (upipe->intr.qhs == NULL)
3606 1.248 mrg return USBD_NOMEM;
3607 1.1 augustss
3608 1.152 augustss /*
3609 1.1 augustss * Figure out which offset in the schedule that has most
3610 1.1 augustss * bandwidth left over.
3611 1.1 augustss */
3612 1.1 augustss #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1))
3613 1.1 augustss for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) {
3614 1.1 augustss for (bw = i = 0; i < npoll; i++)
3615 1.1 augustss bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth;
3616 1.1 augustss if (bw < bestbw) {
3617 1.1 augustss bestbw = bw;
3618 1.1 augustss bestoffs = offs;
3619 1.1 augustss }
3620 1.1 augustss }
3621 1.264.4.27 skrll DPRINTF("bw=%d offs=%d", bestbw, bestoffs, 0, 0);
3622 1.264.4.54 skrll for (i = 0; i < npoll; i++) {
3623 1.264.4.33 skrll upipe->intr.qhs[i] = sqh = uhci_alloc_sqh(sc);
3624 1.121 augustss sqh->elink = NULL;
3625 1.88 tsutsui sqh->qh.qh_elink = htole32(UHCI_PTR_T);
3626 1.223 bouyer usb_syncmem(&sqh->dma,
3627 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
3628 1.223 bouyer sizeof(sqh->qh.qh_elink),
3629 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3630 1.1 augustss sqh->pos = MOD(i * ival + bestoffs);
3631 1.1 augustss }
3632 1.1 augustss #undef MOD
3633 1.1 augustss
3634 1.264.4.55 skrll mutex_enter(&sc->sc_lock);
3635 1.1 augustss /* Enter QHs into the controller data structures. */
3636 1.264.4.54 skrll for (i = 0; i < npoll; i++)
3637 1.264.4.33 skrll uhci_add_intr(sc, upipe->intr.qhs[i]);
3638 1.248 mrg mutex_exit(&sc->sc_lock);
3639 1.1 augustss
3640 1.264.4.21 skrll DPRINTFN(5, "returns %p", upipe, 0, 0, 0);
3641 1.264.4.21 skrll
3642 1.264.4.13 skrll return USBD_NORMAL_COMPLETION;
3643 1.1 augustss }
3644 1.1 augustss
3645 1.1 augustss /* Open a new pipe. */
3646 1.1 augustss usbd_status
3647 1.264.4.25 skrll uhci_open(struct usbd_pipe *pipe)
3648 1.1 augustss {
3649 1.264.4.37 skrll uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
3650 1.264.4.12 skrll struct usbd_bus *bus = pipe->up_dev->ud_bus;
3651 1.264.4.50 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
3652 1.264.4.7 skrll usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc;
3653 1.248 mrg usbd_status err = USBD_NOMEM;
3654 1.79 augustss int ival;
3655 1.1 augustss
3656 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3657 1.264.4.27 skrll DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)",
3658 1.264.4.21 skrll pipe, pipe->up_dev->ud_addr, ed->bEndpointAddress, bus->ub_rhaddr);
3659 1.92 augustss
3660 1.248 mrg if (sc->sc_dying)
3661 1.248 mrg return USBD_IOERROR;
3662 1.248 mrg
3663 1.92 augustss upipe->aborting = 0;
3664 1.236 drochner /* toggle state needed for bulk endpoints */
3665 1.264.4.7 skrll upipe->nexttoggle = pipe->up_endpoint->ue_toggle;
3666 1.92 augustss
3667 1.264.4.12 skrll if (pipe->up_dev->ud_addr == bus->ub_rhaddr) {
3668 1.1 augustss switch (ed->bEndpointAddress) {
3669 1.1 augustss case USB_CONTROL_ENDPOINT:
3670 1.264.4.12 skrll pipe->up_methods = &roothub_ctrl_methods;
3671 1.1 augustss break;
3672 1.264.4.12 skrll case UE_DIR_IN | USBROOTHUB_INTR_ENDPT:
3673 1.264.4.7 skrll pipe->up_methods = &uhci_root_intr_methods;
3674 1.1 augustss break;
3675 1.1 augustss default:
3676 1.264.4.13 skrll return USBD_INVAL;
3677 1.1 augustss }
3678 1.1 augustss } else {
3679 1.1 augustss switch (ed->bmAttributes & UE_XFERTYPE) {
3680 1.1 augustss case UE_CONTROL:
3681 1.264.4.7 skrll pipe->up_methods = &uhci_device_ctrl_methods;
3682 1.264.4.33 skrll upipe->ctrl.sqh = uhci_alloc_sqh(sc);
3683 1.264.4.33 skrll if (upipe->ctrl.sqh == NULL)
3684 1.5 augustss goto bad;
3685 1.264.4.33 skrll upipe->ctrl.setup = uhci_alloc_std(sc);
3686 1.264.4.33 skrll if (upipe->ctrl.setup == NULL) {
3687 1.264.4.33 skrll uhci_free_sqh(sc, upipe->ctrl.sqh);
3688 1.5 augustss goto bad;
3689 1.5 augustss }
3690 1.264.4.33 skrll upipe->ctrl.stat = uhci_alloc_std(sc);
3691 1.264.4.33 skrll if (upipe->ctrl.stat == NULL) {
3692 1.264.4.33 skrll uhci_free_sqh(sc, upipe->ctrl.sqh);
3693 1.264.4.33 skrll uhci_free_std(sc, upipe->ctrl.setup);
3694 1.5 augustss goto bad;
3695 1.5 augustss }
3696 1.152 augustss err = usb_allocmem(&sc->sc_bus,
3697 1.152 augustss sizeof(usb_device_request_t),
3698 1.264.4.33 skrll 0, &upipe->ctrl.reqdma);
3699 1.63 augustss if (err) {
3700 1.264.4.33 skrll uhci_free_sqh(sc, upipe->ctrl.sqh);
3701 1.264.4.33 skrll uhci_free_std(sc, upipe->ctrl.setup);
3702 1.264.4.33 skrll uhci_free_std(sc, upipe->ctrl.stat);
3703 1.5 augustss goto bad;
3704 1.5 augustss }
3705 1.1 augustss break;
3706 1.1 augustss case UE_INTERRUPT:
3707 1.264.4.7 skrll pipe->up_methods = &uhci_device_intr_methods;
3708 1.264.4.7 skrll ival = pipe->up_interval;
3709 1.79 augustss if (ival == USBD_DEFAULT_INTERVAL)
3710 1.79 augustss ival = ed->bInterval;
3711 1.264.4.13 skrll return uhci_device_setintr(sc, upipe, ival);
3712 1.1 augustss case UE_ISOCHRONOUS:
3713 1.264.4.7 skrll pipe->up_methods = &uhci_device_isoc_methods;
3714 1.264.4.13 skrll return uhci_setup_isoc(pipe);
3715 1.1 augustss case UE_BULK:
3716 1.264.4.7 skrll pipe->up_methods = &uhci_device_bulk_methods;
3717 1.264.4.33 skrll upipe->bulk.sqh = uhci_alloc_sqh(sc);
3718 1.264.4.33 skrll if (upipe->bulk.sqh == NULL)
3719 1.5 augustss goto bad;
3720 1.1 augustss break;
3721 1.1 augustss }
3722 1.1 augustss }
3723 1.264.4.13 skrll return USBD_NORMAL_COMPLETION;
3724 1.5 augustss
3725 1.5 augustss bad:
3726 1.248 mrg return USBD_NOMEM;
3727 1.1 augustss }
3728 1.1 augustss
3729 1.1 augustss /*
3730 1.1 augustss * Data structures and routines to emulate the root hub.
3731 1.1 augustss */
3732 1.1 augustss /*
3733 1.166 dsainty * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also
3734 1.166 dsainty * enables the port, and also states that SET_FEATURE(PORT_ENABLE)
3735 1.166 dsainty * should not be used by the USB subsystem. As we cannot issue a
3736 1.166 dsainty * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port
3737 1.166 dsainty * will be enabled as part of the reset.
3738 1.166 dsainty *
3739 1.166 dsainty * On the VT83C572, the port cannot be successfully enabled until the
3740 1.166 dsainty * outstanding "port enable change" and "connection status change"
3741 1.166 dsainty * events have been reset.
3742 1.166 dsainty */
3743 1.166 dsainty Static usbd_status
3744 1.166 dsainty uhci_portreset(uhci_softc_t *sc, int index)
3745 1.166 dsainty {
3746 1.166 dsainty int lim, port, x;
3747 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3748 1.166 dsainty
3749 1.166 dsainty if (index == 1)
3750 1.166 dsainty port = UHCI_PORTSC1;
3751 1.166 dsainty else if (index == 2)
3752 1.166 dsainty port = UHCI_PORTSC2;
3753 1.166 dsainty else
3754 1.264.4.13 skrll return USBD_IOERROR;
3755 1.166 dsainty
3756 1.166 dsainty x = URWMASK(UREAD2(sc, port));
3757 1.166 dsainty UWRITE2(sc, port, x | UHCI_PORTSC_PR);
3758 1.166 dsainty
3759 1.166 dsainty usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY);
3760 1.166 dsainty
3761 1.264.4.27 skrll DPRINTF("uhci port %d reset, status0 = 0x%04x", index,
3762 1.264.4.21 skrll UREAD2(sc, port), 0, 0);
3763 1.166 dsainty
3764 1.166 dsainty x = URWMASK(UREAD2(sc, port));
3765 1.222 drochner UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP));
3766 1.166 dsainty
3767 1.166 dsainty delay(100);
3768 1.166 dsainty
3769 1.264.4.27 skrll DPRINTF("uhci port %d reset, status1 = 0x%04x", index,
3770 1.264.4.21 skrll UREAD2(sc, port), 0, 0);
3771 1.166 dsainty
3772 1.166 dsainty x = URWMASK(UREAD2(sc, port));
3773 1.166 dsainty UWRITE2(sc, port, x | UHCI_PORTSC_PE);
3774 1.166 dsainty
3775 1.166 dsainty for (lim = 10; --lim > 0;) {
3776 1.166 dsainty usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY);
3777 1.166 dsainty
3778 1.166 dsainty x = UREAD2(sc, port);
3779 1.264.4.27 skrll DPRINTF("uhci port %d iteration %u, status = 0x%04x", index,
3780 1.264.4.21 skrll lim, x, 0);
3781 1.166 dsainty
3782 1.166 dsainty if (!(x & UHCI_PORTSC_CCS)) {
3783 1.166 dsainty /*
3784 1.166 dsainty * No device is connected (or was disconnected
3785 1.166 dsainty * during reset). Consider the port reset.
3786 1.166 dsainty * The delay must be long enough to ensure on
3787 1.166 dsainty * the initial iteration that the device
3788 1.166 dsainty * connection will have been registered. 50ms
3789 1.166 dsainty * appears to be sufficient, but 20ms is not.
3790 1.166 dsainty */
3791 1.264.4.21 skrll DPRINTFN(3, "uhci port %d loop %u, device detached",
3792 1.264.4.21 skrll index, lim, 0, 0);
3793 1.166 dsainty break;
3794 1.166 dsainty }
3795 1.166 dsainty
3796 1.166 dsainty if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) {
3797 1.166 dsainty /*
3798 1.166 dsainty * Port enabled changed and/or connection
3799 1.166 dsainty * status changed were set. Reset either or
3800 1.166 dsainty * both raised flags (by writing a 1 to that
3801 1.166 dsainty * bit), and wait again for state to settle.
3802 1.166 dsainty */
3803 1.166 dsainty UWRITE2(sc, port, URWMASK(x) |
3804 1.166 dsainty (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)));
3805 1.166 dsainty continue;
3806 1.166 dsainty }
3807 1.166 dsainty
3808 1.166 dsainty if (x & UHCI_PORTSC_PE)
3809 1.166 dsainty /* Port is enabled */
3810 1.166 dsainty break;
3811 1.166 dsainty
3812 1.166 dsainty UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE);
3813 1.166 dsainty }
3814 1.166 dsainty
3815 1.264.4.21 skrll DPRINTFN(3, "uhci port %d reset, status2 = 0x%04x", index,
3816 1.264.4.21 skrll UREAD2(sc, port), 0, 0);
3817 1.166 dsainty
3818 1.166 dsainty if (lim <= 0) {
3819 1.264.4.27 skrll DPRINTF("uhci port %d reset timed out", index,
3820 1.264.4.21 skrll 0, 0, 0);
3821 1.264.4.13 skrll return USBD_TIMEOUT;
3822 1.166 dsainty }
3823 1.184 perry
3824 1.166 dsainty sc->sc_isreset = 1;
3825 1.264.4.13 skrll return USBD_NORMAL_COMPLETION;
3826 1.166 dsainty }
3827 1.166 dsainty
3828 1.264.4.12 skrll Static int
3829 1.264.4.12 skrll uhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req,
3830 1.264.4.12 skrll void *buf, int buflen)
3831 1.1 augustss {
3832 1.264.4.37 skrll uhci_softc_t *sc = UHCI_BUS2SC(bus);
3833 1.1 augustss int port, x;
3834 1.264.4.12 skrll int status, change, totlen = 0;
3835 1.264.4.12 skrll uint16_t len, value, index;
3836 1.1 augustss usb_port_status_t ps;
3837 1.63 augustss usbd_status err;
3838 1.1 augustss
3839 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3840 1.264.4.21 skrll
3841 1.82 augustss if (sc->sc_dying)
3842 1.264.4.12 skrll return -1;
3843 1.1 augustss
3844 1.264.4.27 skrll DPRINTF("type=0x%02x request=%02x", req->bmRequestType,
3845 1.264.4.21 skrll req->bRequest, 0, 0);
3846 1.1 augustss
3847 1.1 augustss len = UGETW(req->wLength);
3848 1.1 augustss value = UGETW(req->wValue);
3849 1.1 augustss index = UGETW(req->wIndex);
3850 1.49 augustss
3851 1.1 augustss #define C(x,y) ((x) | ((y) << 8))
3852 1.264.4.12 skrll switch (C(req->bRequest, req->bmRequestType)) {
3853 1.1 augustss case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3854 1.264.4.27 skrll DPRINTF("wValue=0x%04x", value, 0, 0, 0);
3855 1.195 christos if (len == 0)
3856 1.195 christos break;
3857 1.264.4.12 skrll switch (value) {
3858 1.264.4.12 skrll case C(0, UDESC_DEVICE): {
3859 1.264.4.12 skrll usb_device_descriptor_t devd;
3860 1.264.4.12 skrll
3861 1.264.4.12 skrll totlen = min(buflen, sizeof(devd));
3862 1.264.4.12 skrll memcpy(&devd, buf, totlen);
3863 1.264.4.12 skrll USETW(devd.idVendor, sc->sc_id_vendor);
3864 1.264.4.12 skrll memcpy(buf, &devd, totlen);
3865 1.1 augustss break;
3866 1.264.4.12 skrll }
3867 1.264.4.12 skrll case C(1, UDESC_STRING):
3868 1.213 drochner #define sd ((usb_string_descriptor_t *)buf)
3869 1.264.4.12 skrll /* Vendor */
3870 1.264.4.12 skrll totlen = usb_makestrdesc(sd, len, sc->sc_vendor);
3871 1.264.4.12 skrll break;
3872 1.264.4.12 skrll case C(2, UDESC_STRING):
3873 1.264.4.12 skrll /* Product */
3874 1.264.4.12 skrll totlen = usb_makestrdesc(sd, len, "UHCI root hub");
3875 1.1 augustss break;
3876 1.264.4.12 skrll #undef sd
3877 1.1 augustss default:
3878 1.264.4.12 skrll /* default from usbroothub */
3879 1.264.4.12 skrll return buflen;
3880 1.1 augustss }
3881 1.1 augustss break;
3882 1.264.4.12 skrll
3883 1.1 augustss /* Hub requests */
3884 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3885 1.1 augustss break;
3886 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3887 1.264.4.27 skrll DPRINTF("UR_CLEAR_PORT_FEATURE port=%d feature=%d", index,
3888 1.264.4.21 skrll value, 0, 0);
3889 1.1 augustss if (index == 1)
3890 1.1 augustss port = UHCI_PORTSC1;
3891 1.1 augustss else if (index == 2)
3892 1.1 augustss port = UHCI_PORTSC2;
3893 1.1 augustss else {
3894 1.264.4.12 skrll return -1;
3895 1.1 augustss }
3896 1.1 augustss switch(value) {
3897 1.1 augustss case UHF_PORT_ENABLE:
3898 1.137 augustss x = URWMASK(UREAD2(sc, port));
3899 1.1 augustss UWRITE2(sc, port, x & ~UHCI_PORTSC_PE);
3900 1.1 augustss break;
3901 1.1 augustss case UHF_PORT_SUSPEND:
3902 1.137 augustss x = URWMASK(UREAD2(sc, port));
3903 1.222 drochner if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */
3904 1.222 drochner break;
3905 1.222 drochner UWRITE2(sc, port, x | UHCI_PORTSC_RD);
3906 1.222 drochner /* see USB2 spec ch. 7.1.7.7 */
3907 1.222 drochner usb_delay_ms(&sc->sc_bus, 20);
3908 1.1 augustss UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP);
3909 1.222 drochner /* 10ms resume delay must be provided by caller */
3910 1.1 augustss break;
3911 1.1 augustss case UHF_PORT_RESET:
3912 1.137 augustss x = URWMASK(UREAD2(sc, port));
3913 1.1 augustss UWRITE2(sc, port, x & ~UHCI_PORTSC_PR);
3914 1.1 augustss break;
3915 1.1 augustss case UHF_C_PORT_CONNECTION:
3916 1.137 augustss x = URWMASK(UREAD2(sc, port));
3917 1.1 augustss UWRITE2(sc, port, x | UHCI_PORTSC_CSC);
3918 1.1 augustss break;
3919 1.1 augustss case UHF_C_PORT_ENABLE:
3920 1.137 augustss x = URWMASK(UREAD2(sc, port));
3921 1.1 augustss UWRITE2(sc, port, x | UHCI_PORTSC_POEDC);
3922 1.1 augustss break;
3923 1.1 augustss case UHF_C_PORT_OVER_CURRENT:
3924 1.137 augustss x = URWMASK(UREAD2(sc, port));
3925 1.1 augustss UWRITE2(sc, port, x | UHCI_PORTSC_OCIC);
3926 1.1 augustss break;
3927 1.1 augustss case UHF_C_PORT_RESET:
3928 1.1 augustss sc->sc_isreset = 0;
3929 1.264.4.16 skrll break;
3930 1.1 augustss case UHF_PORT_CONNECTION:
3931 1.1 augustss case UHF_PORT_OVER_CURRENT:
3932 1.1 augustss case UHF_PORT_POWER:
3933 1.1 augustss case UHF_PORT_LOW_SPEED:
3934 1.1 augustss case UHF_C_PORT_SUSPEND:
3935 1.1 augustss default:
3936 1.264.4.12 skrll return -1;
3937 1.1 augustss }
3938 1.1 augustss break;
3939 1.1 augustss case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER):
3940 1.1 augustss if (index == 1)
3941 1.1 augustss port = UHCI_PORTSC1;
3942 1.1 augustss else if (index == 2)
3943 1.1 augustss port = UHCI_PORTSC2;
3944 1.1 augustss else {
3945 1.264.4.12 skrll return -1;
3946 1.1 augustss }
3947 1.1 augustss if (len > 0) {
3948 1.264.4.1 skrll *(uint8_t *)buf =
3949 1.1 augustss (UREAD2(sc, port) & UHCI_PORTSC_LS) >>
3950 1.1 augustss UHCI_PORTSC_LS_SHIFT;
3951 1.1 augustss totlen = 1;
3952 1.1 augustss }
3953 1.1 augustss break;
3954 1.1 augustss case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3955 1.195 christos if (len == 0)
3956 1.195 christos break;
3957 1.177 toshii if ((value & 0xff) != 0) {
3958 1.264.4.12 skrll return -1;
3959 1.1 augustss }
3960 1.264.4.12 skrll usb_hub_descriptor_t hubd;
3961 1.264.4.12 skrll
3962 1.264.4.12 skrll totlen = min(buflen, sizeof(hubd));
3963 1.264.4.12 skrll memcpy(&hubd, buf, totlen);
3964 1.264.4.12 skrll hubd.bNbrPorts = 2;
3965 1.264.4.12 skrll memcpy(buf, &hubd, totlen);
3966 1.1 augustss break;
3967 1.1 augustss case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3968 1.1 augustss if (len != 4) {
3969 1.264.4.12 skrll return -1;
3970 1.1 augustss }
3971 1.1 augustss memset(buf, 0, len);
3972 1.1 augustss totlen = len;
3973 1.1 augustss break;
3974 1.1 augustss case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3975 1.1 augustss if (index == 1)
3976 1.1 augustss port = UHCI_PORTSC1;
3977 1.1 augustss else if (index == 2)
3978 1.1 augustss port = UHCI_PORTSC2;
3979 1.1 augustss else {
3980 1.264.4.12 skrll return -1;
3981 1.1 augustss }
3982 1.1 augustss if (len != 4) {
3983 1.264.4.12 skrll return -1;
3984 1.1 augustss }
3985 1.1 augustss x = UREAD2(sc, port);
3986 1.1 augustss status = change = 0;
3987 1.142 augustss if (x & UHCI_PORTSC_CCS)
3988 1.1 augustss status |= UPS_CURRENT_CONNECT_STATUS;
3989 1.152 augustss if (x & UHCI_PORTSC_CSC)
3990 1.1 augustss change |= UPS_C_CONNECT_STATUS;
3991 1.152 augustss if (x & UHCI_PORTSC_PE)
3992 1.1 augustss status |= UPS_PORT_ENABLED;
3993 1.152 augustss if (x & UHCI_PORTSC_POEDC)
3994 1.1 augustss change |= UPS_C_PORT_ENABLED;
3995 1.152 augustss if (x & UHCI_PORTSC_OCI)
3996 1.1 augustss status |= UPS_OVERCURRENT_INDICATOR;
3997 1.152 augustss if (x & UHCI_PORTSC_OCIC)
3998 1.1 augustss change |= UPS_C_OVERCURRENT_INDICATOR;
3999 1.152 augustss if (x & UHCI_PORTSC_SUSP)
4000 1.1 augustss status |= UPS_SUSPEND;
4001 1.152 augustss if (x & UHCI_PORTSC_LSDA)
4002 1.1 augustss status |= UPS_LOW_SPEED;
4003 1.1 augustss status |= UPS_PORT_POWER;
4004 1.1 augustss if (sc->sc_isreset)
4005 1.1 augustss change |= UPS_C_PORT_RESET;
4006 1.1 augustss USETW(ps.wPortStatus, status);
4007 1.1 augustss USETW(ps.wPortChange, change);
4008 1.264.4.12 skrll totlen = min(len, sizeof(ps));
4009 1.264.4.12 skrll memcpy(buf, &ps, totlen);
4010 1.1 augustss break;
4011 1.1 augustss case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
4012 1.264.4.12 skrll return -1;
4013 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
4014 1.1 augustss break;
4015 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
4016 1.1 augustss if (index == 1)
4017 1.1 augustss port = UHCI_PORTSC1;
4018 1.1 augustss else if (index == 2)
4019 1.1 augustss port = UHCI_PORTSC2;
4020 1.1 augustss else {
4021 1.264.4.12 skrll return -1;
4022 1.1 augustss }
4023 1.1 augustss switch(value) {
4024 1.1 augustss case UHF_PORT_ENABLE:
4025 1.137 augustss x = URWMASK(UREAD2(sc, port));
4026 1.1 augustss UWRITE2(sc, port, x | UHCI_PORTSC_PE);
4027 1.1 augustss break;
4028 1.1 augustss case UHF_PORT_SUSPEND:
4029 1.137 augustss x = URWMASK(UREAD2(sc, port));
4030 1.1 augustss UWRITE2(sc, port, x | UHCI_PORTSC_SUSP);
4031 1.1 augustss break;
4032 1.1 augustss case UHF_PORT_RESET:
4033 1.166 dsainty err = uhci_portreset(sc, index);
4034 1.264.4.12 skrll if (err != USBD_NORMAL_COMPLETION)
4035 1.264.4.12 skrll return -1;
4036 1.264.4.12 skrll return 0;
4037 1.111 augustss case UHF_PORT_POWER:
4038 1.111 augustss /* Pretend we turned on power */
4039 1.264.4.12 skrll return 0;
4040 1.1 augustss case UHF_C_PORT_CONNECTION:
4041 1.1 augustss case UHF_C_PORT_ENABLE:
4042 1.1 augustss case UHF_C_PORT_OVER_CURRENT:
4043 1.1 augustss case UHF_PORT_CONNECTION:
4044 1.1 augustss case UHF_PORT_OVER_CURRENT:
4045 1.1 augustss case UHF_PORT_LOW_SPEED:
4046 1.1 augustss case UHF_C_PORT_SUSPEND:
4047 1.1 augustss case UHF_C_PORT_RESET:
4048 1.1 augustss default:
4049 1.264.4.12 skrll return -1;
4050 1.1 augustss }
4051 1.1 augustss break;
4052 1.1 augustss default:
4053 1.264.4.12 skrll /* default from usbroothub */
4054 1.264.4.27 skrll DPRINTF("returning %d (usbroothub default)",
4055 1.264.4.21 skrll buflen, 0, 0, 0);
4056 1.264.4.12 skrll return buflen;
4057 1.1 augustss }
4058 1.1 augustss
4059 1.264.4.27 skrll DPRINTF("returning %d", totlen, 0, 0, 0);
4060 1.264.4.21 skrll
4061 1.264.4.12 skrll return totlen;
4062 1.1 augustss }
4063 1.1 augustss
4064 1.1 augustss /* Abort a root interrupt request. */
4065 1.1 augustss void
4066 1.264.4.25 skrll uhci_root_intr_abort(struct usbd_xfer *xfer)
4067 1.1 augustss {
4068 1.264.4.37 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
4069 1.30 augustss
4070 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
4071 1.264.4.7 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
4072 1.248 mrg
4073 1.234 dyoung callout_stop(&sc->sc_poll_handle);
4074 1.96 augustss sc->sc_intr_xfer = NULL;
4075 1.58 augustss
4076 1.264.4.7 skrll xfer->ux_status = USBD_CANCELLED;
4077 1.96 augustss #ifdef DIAGNOSTIC
4078 1.264.4.41 skrll UHCI_XFER2UXFER(xfer)->ux_isdone = true;
4079 1.96 augustss #endif
4080 1.63 augustss usb_transfer_complete(xfer);
4081 1.1 augustss }
4082 1.1 augustss
4083 1.16 augustss usbd_status
4084 1.264.4.25 skrll uhci_root_intr_transfer(struct usbd_xfer *xfer)
4085 1.16 augustss {
4086 1.264.4.37 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
4087 1.63 augustss usbd_status err;
4088 1.16 augustss
4089 1.52 augustss /* Insert last in queue. */
4090 1.248 mrg mutex_enter(&sc->sc_lock);
4091 1.63 augustss err = usb_insert_transfer(xfer);
4092 1.248 mrg mutex_exit(&sc->sc_lock);
4093 1.63 augustss if (err)
4094 1.264.4.13 skrll return err;
4095 1.52 augustss
4096 1.186 skrll /*
4097 1.186 skrll * Pipe isn't running (otherwise err would be USBD_INPROG),
4098 1.67 augustss * start first
4099 1.67 augustss */
4100 1.264.4.13 skrll return uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
4101 1.16 augustss }
4102 1.16 augustss
4103 1.1 augustss /* Start a transfer on the root interrupt pipe */
4104 1.1 augustss usbd_status
4105 1.264.4.25 skrll uhci_root_intr_start(struct usbd_xfer *xfer)
4106 1.1 augustss {
4107 1.264.4.25 skrll struct usbd_pipe *pipe = xfer->ux_pipe;
4108 1.264.4.37 skrll uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
4109 1.174 drochner unsigned int ival;
4110 1.1 augustss
4111 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
4112 1.264.4.27 skrll DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length,
4113 1.264.4.21 skrll xfer->ux_flags, 0);
4114 1.82 augustss
4115 1.82 augustss if (sc->sc_dying)
4116 1.264.4.13 skrll return USBD_IOERROR;
4117 1.1 augustss
4118 1.174 drochner /* XXX temporary variable needed to avoid gcc3 warning */
4119 1.264.4.7 skrll ival = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval;
4120 1.174 drochner sc->sc_ival = mstohz(ival);
4121 1.234 dyoung callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer);
4122 1.96 augustss sc->sc_intr_xfer = xfer;
4123 1.264.4.13 skrll return USBD_IN_PROGRESS;
4124 1.1 augustss }
4125 1.1 augustss
4126 1.1 augustss /* Close the root interrupt pipe. */
4127 1.1 augustss void
4128 1.264.4.25 skrll uhci_root_intr_close(struct usbd_pipe *pipe)
4129 1.1 augustss {
4130 1.264.4.37 skrll uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
4131 1.264.4.21 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
4132 1.30 augustss
4133 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
4134 1.248 mrg
4135 1.234 dyoung callout_stop(&sc->sc_poll_handle);
4136 1.96 augustss sc->sc_intr_xfer = NULL;
4137 1.1 augustss }
4138