Home | History | Annotate | Line # | Download | only in usb
uhci.c revision 1.264.4.70
      1  1.264.4.70     skrll /*	$NetBSD: uhci.c,v 1.264.4.70 2016/04/04 07:43:12 skrll Exp $	*/
      2         1.1  augustss 
      3         1.1  augustss /*
      4       1.248       mrg  * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc.
      5         1.1  augustss  * All rights reserved.
      6         1.1  augustss  *
      7        1.11  augustss  * This code is derived from software contributed to The NetBSD Foundation
      8       1.113  augustss  * by Lennart Augustsson (lennart (at) augustsson.net) at
      9       1.248       mrg  * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca)
     10       1.248       mrg  * and Matthew R. Green (mrg (at) eterna.com.au).
     11         1.1  augustss  *
     12         1.1  augustss  * Redistribution and use in source and binary forms, with or without
     13         1.1  augustss  * modification, are permitted provided that the following conditions
     14         1.1  augustss  * are met:
     15         1.1  augustss  * 1. Redistributions of source code must retain the above copyright
     16         1.1  augustss  *    notice, this list of conditions and the following disclaimer.
     17         1.1  augustss  * 2. Redistributions in binary form must reproduce the above copyright
     18         1.1  augustss  *    notice, this list of conditions and the following disclaimer in the
     19         1.1  augustss  *    documentation and/or other materials provided with the distribution.
     20         1.1  augustss  *
     21         1.1  augustss  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     22         1.1  augustss  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     23         1.1  augustss  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     24         1.1  augustss  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     25         1.1  augustss  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     26         1.1  augustss  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     27         1.1  augustss  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     28         1.1  augustss  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     29         1.1  augustss  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     30         1.1  augustss  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     31         1.1  augustss  * POSSIBILITY OF SUCH DAMAGE.
     32         1.1  augustss  */
     33         1.1  augustss 
     34         1.1  augustss /*
     35         1.1  augustss  * USB Universal Host Controller driver.
     36        1.28  augustss  * Handles e.g. PIIX3 and PIIX4.
     37         1.1  augustss  *
     38       1.229  uebayasi  * UHCI spec: http://www.intel.com/technology/usb/spec.htm
     39       1.229  uebayasi  * USB spec: http://www.usb.org/developers/docs/
     40        1.71  augustss  * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf
     41        1.71  augustss  *             ftp://download.intel.com/design/intarch/datashts/29056201.pdf
     42         1.1  augustss  */
     43       1.143     lukem 
     44       1.143     lukem #include <sys/cdefs.h>
     45  1.264.4.70     skrll __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.264.4.70 2016/04/04 07:43:12 skrll Exp $");
     46  1.264.4.30     skrll 
     47  1.264.4.30     skrll #include "opt_usb.h"
     48         1.1  augustss 
     49         1.1  augustss #include <sys/param.h>
     50  1.264.4.20     skrll 
     51  1.264.4.20     skrll #include <sys/bus.h>
     52  1.264.4.20     skrll #include <sys/cpu.h>
     53  1.264.4.20     skrll #include <sys/device.h>
     54         1.1  augustss #include <sys/kernel.h>
     55       1.248       mrg #include <sys/kmem.h>
     56  1.264.4.20     skrll #include <sys/mutex.h>
     57         1.1  augustss #include <sys/proc.h>
     58         1.1  augustss #include <sys/queue.h>
     59  1.264.4.20     skrll #include <sys/select.h>
     60  1.264.4.20     skrll #include <sys/sysctl.h>
     61  1.264.4.20     skrll #include <sys/systm.h>
     62         1.1  augustss 
     63        1.39  augustss #include <machine/endian.h>
     64         1.7  augustss 
     65         1.1  augustss #include <dev/usb/usb.h>
     66         1.1  augustss #include <dev/usb/usbdi.h>
     67         1.1  augustss #include <dev/usb/usbdivar.h>
     68         1.7  augustss #include <dev/usb/usb_mem.h>
     69         1.1  augustss 
     70         1.1  augustss #include <dev/usb/uhcireg.h>
     71         1.1  augustss #include <dev/usb/uhcivar.h>
     72  1.264.4.11     skrll #include <dev/usb/usbroothub.h>
     73  1.264.4.21     skrll #include <dev/usb/usbhist.h>
     74         1.1  augustss 
     75       1.125  augustss /* Use bandwidth reclamation for control transfers. Some devices choke on it. */
     76       1.125  augustss /*#define UHCI_CTL_LOOP */
     77       1.125  augustss 
     78        1.67  augustss #ifdef UHCI_DEBUG
     79        1.92  augustss uhci_softc_t *thesc;
     80       1.125  augustss int uhcinoloop = 0;
     81        1.59  augustss #endif
     82        1.59  augustss 
     83  1.264.4.21     skrll #ifdef USB_DEBUG
     84  1.264.4.21     skrll #ifndef UHCI_DEBUG
     85  1.264.4.21     skrll #define uhcidebug 0
     86  1.264.4.21     skrll #else
     87  1.264.4.21     skrll static int uhcidebug = 0;
     88  1.264.4.21     skrll 
     89  1.264.4.21     skrll SYSCTL_SETUP(sysctl_hw_uhci_setup, "sysctl hw.uhci setup")
     90  1.264.4.21     skrll {
     91  1.264.4.21     skrll 	int err;
     92  1.264.4.21     skrll 	const struct sysctlnode *rnode;
     93  1.264.4.21     skrll 	const struct sysctlnode *cnode;
     94  1.264.4.21     skrll 
     95  1.264.4.21     skrll 	err = sysctl_createv(clog, 0, NULL, &rnode,
     96  1.264.4.21     skrll 	    CTLFLAG_PERMANENT, CTLTYPE_NODE, "uhci",
     97  1.264.4.21     skrll 	    SYSCTL_DESCR("uhci global controls"),
     98  1.264.4.21     skrll 	    NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
     99  1.264.4.21     skrll 
    100  1.264.4.21     skrll 	if (err)
    101  1.264.4.21     skrll 		goto fail;
    102  1.264.4.21     skrll 
    103  1.264.4.21     skrll 	/* control debugging printfs */
    104  1.264.4.21     skrll 	err = sysctl_createv(clog, 0, &rnode, &cnode,
    105  1.264.4.21     skrll 	    CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
    106  1.264.4.21     skrll 	    "debug", SYSCTL_DESCR("Enable debugging output"),
    107  1.264.4.21     skrll 	    NULL, 0, &uhcidebug, sizeof(uhcidebug), CTL_CREATE, CTL_EOL);
    108  1.264.4.21     skrll 	if (err)
    109  1.264.4.21     skrll 		goto fail;
    110  1.264.4.21     skrll 
    111  1.264.4.21     skrll 	return;
    112  1.264.4.21     skrll fail:
    113  1.264.4.21     skrll 	aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err);
    114  1.264.4.21     skrll }
    115  1.264.4.21     skrll 
    116  1.264.4.21     skrll #endif /* UHCI_DEBUG */
    117  1.264.4.21     skrll #endif /* USB_DEBUG */
    118  1.264.4.21     skrll 
    119  1.264.4.27     skrll #define	DPRINTF(FMT,A,B,C,D)	USBHIST_LOGN(uhcidebug,1,FMT,A,B,C,D)
    120  1.264.4.21     skrll #define	DPRINTFN(N,FMT,A,B,C,D)	USBHIST_LOGN(uhcidebug,N,FMT,A,B,C,D)
    121  1.264.4.21     skrll #define	UHCIHIST_FUNC()		USBHIST_FUNC()
    122  1.264.4.21     skrll #define	UHCIHIST_CALLED(name)	USBHIST_CALLED(uhcidebug)
    123  1.264.4.21     skrll 
    124        1.39  augustss /*
    125        1.39  augustss  * The UHCI controller is little endian, so on big endian machines
    126       1.181  drochner  * the data stored in memory needs to be swapped.
    127        1.39  augustss  */
    128        1.39  augustss 
    129         1.1  augustss struct uhci_pipe {
    130         1.1  augustss 	struct usbd_pipe pipe;
    131        1.32  augustss 	int nexttoggle;
    132        1.92  augustss 
    133        1.92  augustss 	u_char aborting;
    134  1.264.4.25     skrll 	struct usbd_xfer *abortstart, abortend;
    135        1.92  augustss 
    136         1.1  augustss 	/* Info needed for different pipe kinds. */
    137         1.1  augustss 	union {
    138         1.1  augustss 		/* Control pipe */
    139         1.1  augustss 		struct {
    140         1.1  augustss 			uhci_soft_qh_t *sqh;
    141         1.7  augustss 			usb_dma_t reqdma;
    142  1.264.4.55     skrll 			uhci_soft_td_t *setup;
    143  1.264.4.55     skrll 			uhci_soft_td_t *stat;
    144  1.264.4.33     skrll 		} ctrl;
    145         1.1  augustss 		/* Interrupt pipe */
    146         1.1  augustss 		struct {
    147         1.1  augustss 			int npoll;
    148         1.1  augustss 			uhci_soft_qh_t **qhs;
    149         1.1  augustss 		} intr;
    150         1.1  augustss 		/* Bulk pipe */
    151         1.1  augustss 		struct {
    152         1.1  augustss 			uhci_soft_qh_t *sqh;
    153         1.1  augustss 		} bulk;
    154  1.264.4.33     skrll 		/* Isochronous pipe */
    155  1.264.4.33     skrll 		struct isoc {
    156        1.16  augustss 			uhci_soft_td_t **stds;
    157        1.48  augustss 			int next, inuse;
    158  1.264.4.33     skrll 		} isoc;
    159  1.264.4.33     skrll 	};
    160         1.1  augustss };
    161         1.1  augustss 
    162  1.264.4.61     skrll typedef TAILQ_HEAD(ux_completeq, uhci_xfer) ux_completeq_t;
    163  1.264.4.61     skrll 
    164       1.142  augustss Static void		uhci_globalreset(uhci_softc_t *);
    165       1.166   dsainty Static usbd_status	uhci_portreset(uhci_softc_t*, int);
    166       1.142  augustss Static void		uhci_reset(uhci_softc_t *);
    167  1.264.4.15     skrll Static usbd_status	uhci_run(uhci_softc_t *, int, int);
    168       1.123  augustss Static uhci_soft_td_t  *uhci_alloc_std(uhci_softc_t *);
    169       1.119  augustss Static void		uhci_free_std(uhci_softc_t *, uhci_soft_td_t *);
    170  1.264.4.55     skrll Static void		uhci_free_std_locked(uhci_softc_t *, uhci_soft_td_t *);
    171       1.123  augustss Static uhci_soft_qh_t  *uhci_alloc_sqh(uhci_softc_t *);
    172       1.119  augustss Static void		uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *);
    173        1.16  augustss #if 0
    174       1.119  augustss Static void		uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *,
    175  1.264.4.48     skrll 			    uhci_intr_info_t *);
    176       1.119  augustss Static void		uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *);
    177        1.16  augustss #endif
    178         1.1  augustss 
    179  1.264.4.55     skrll Static void		uhci_free_std_chain(uhci_softc_t *, uhci_soft_td_t *,
    180  1.264.4.55     skrll 			    uhci_soft_td_t *);
    181  1.264.4.55     skrll Static usbd_status	uhci_alloc_std_chain(uhci_softc_t *, struct usbd_xfer *,
    182  1.264.4.70     skrll 			    int, int, uhci_soft_td_t **);
    183  1.264.4.55     skrll Static void		uhci_free_stds(uhci_softc_t *, struct uhci_xfer *);
    184  1.264.4.55     skrll 
    185  1.264.4.55     skrll Static void		uhci_reset_std_chain(uhci_softc_t *, struct usbd_xfer *,
    186  1.264.4.58     skrll 			    int, int, int *, uhci_soft_td_t **);
    187  1.264.4.55     skrll 
    188       1.119  augustss Static void		uhci_poll_hub(void *);
    189  1.264.4.25     skrll Static void		uhci_waitintr(uhci_softc_t *, struct usbd_xfer *);
    190  1.264.4.61     skrll Static void		uhci_check_intr(uhci_softc_t *, struct uhci_xfer *,
    191  1.264.4.61     skrll 			    ux_completeq_t *);
    192  1.264.4.61     skrll Static void		uhci_idone(struct uhci_xfer *, ux_completeq_t *);
    193       1.119  augustss 
    194  1.264.4.25     skrll Static void		uhci_abort_xfer(struct usbd_xfer *, usbd_status);
    195       1.119  augustss 
    196       1.119  augustss Static void		uhci_timeout(void *);
    197       1.153  augustss Static void		uhci_timeout_task(void *);
    198       1.123  augustss Static void		uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *);
    199       1.123  augustss Static void		uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *);
    200       1.119  augustss Static void		uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *);
    201       1.123  augustss Static void		uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *);
    202       1.123  augustss Static void		uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *);
    203       1.119  augustss Static void		uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *);
    204  1.264.4.15     skrll Static void		uhci_add_loop(uhci_softc_t *);
    205  1.264.4.15     skrll Static void		uhci_rem_loop(uhci_softc_t *);
    206       1.119  augustss 
    207  1.264.4.25     skrll Static usbd_status	uhci_setup_isoc(struct usbd_pipe *);
    208       1.119  augustss 
    209  1.264.4.36     skrll Static struct usbd_xfer *
    210  1.264.4.36     skrll 			uhci_allocx(struct usbd_bus *, unsigned int);
    211  1.264.4.25     skrll Static void		uhci_freex(struct usbd_bus *, struct usbd_xfer *);
    212       1.248       mrg Static void		uhci_get_lock(struct usbd_bus *, kmutex_t **);
    213  1.264.4.13     skrll Static int		uhci_roothub_ctrl(struct usbd_bus *,
    214  1.264.4.42     skrll 			    usb_device_request_t *, void *, int);
    215       1.119  augustss 
    216  1.264.4.55     skrll Static int		uhci_device_ctrl_init(struct usbd_xfer *);
    217  1.264.4.55     skrll Static void		uhci_device_ctrl_fini(struct usbd_xfer *);
    218  1.264.4.25     skrll Static usbd_status	uhci_device_ctrl_transfer(struct usbd_xfer *);
    219  1.264.4.25     skrll Static usbd_status	uhci_device_ctrl_start(struct usbd_xfer *);
    220  1.264.4.25     skrll Static void		uhci_device_ctrl_abort(struct usbd_xfer *);
    221  1.264.4.25     skrll Static void		uhci_device_ctrl_close(struct usbd_pipe *);
    222  1.264.4.25     skrll Static void		uhci_device_ctrl_done(struct usbd_xfer *);
    223  1.264.4.25     skrll 
    224  1.264.4.55     skrll Static int		uhci_device_intr_init(struct usbd_xfer *);
    225  1.264.4.55     skrll Static void		uhci_device_intr_fini(struct usbd_xfer *);
    226  1.264.4.25     skrll Static usbd_status	uhci_device_intr_transfer(struct usbd_xfer *);
    227  1.264.4.25     skrll Static usbd_status	uhci_device_intr_start(struct usbd_xfer *);
    228  1.264.4.25     skrll Static void		uhci_device_intr_abort(struct usbd_xfer *);
    229  1.264.4.25     skrll Static void		uhci_device_intr_close(struct usbd_pipe *);
    230  1.264.4.25     skrll Static void		uhci_device_intr_done(struct usbd_xfer *);
    231  1.264.4.25     skrll 
    232  1.264.4.55     skrll Static int		uhci_device_bulk_init(struct usbd_xfer *);
    233  1.264.4.55     skrll Static void		uhci_device_bulk_fini(struct usbd_xfer *);
    234  1.264.4.25     skrll Static usbd_status	uhci_device_bulk_transfer(struct usbd_xfer *);
    235  1.264.4.25     skrll Static usbd_status	uhci_device_bulk_start(struct usbd_xfer *);
    236  1.264.4.25     skrll Static void		uhci_device_bulk_abort(struct usbd_xfer *);
    237  1.264.4.25     skrll Static void		uhci_device_bulk_close(struct usbd_pipe *);
    238  1.264.4.25     skrll Static void		uhci_device_bulk_done(struct usbd_xfer *);
    239  1.264.4.25     skrll 
    240  1.264.4.55     skrll Static int		uhci_device_isoc_init(struct usbd_xfer *);
    241  1.264.4.55     skrll Static void		uhci_device_isoc_fini(struct usbd_xfer *);
    242  1.264.4.25     skrll Static usbd_status	uhci_device_isoc_transfer(struct usbd_xfer *);
    243  1.264.4.25     skrll Static usbd_status	uhci_device_isoc_start(struct usbd_xfer *);
    244  1.264.4.25     skrll Static void		uhci_device_isoc_abort(struct usbd_xfer *);
    245  1.264.4.25     skrll Static void		uhci_device_isoc_close(struct usbd_pipe *);
    246  1.264.4.25     skrll Static void		uhci_device_isoc_done(struct usbd_xfer *);
    247  1.264.4.25     skrll 
    248  1.264.4.25     skrll Static usbd_status	uhci_root_intr_transfer(struct usbd_xfer *);
    249  1.264.4.25     skrll Static usbd_status	uhci_root_intr_start(struct usbd_xfer *);
    250  1.264.4.25     skrll Static void		uhci_root_intr_abort(struct usbd_xfer *);
    251  1.264.4.25     skrll Static void		uhci_root_intr_close(struct usbd_pipe *);
    252  1.264.4.25     skrll Static void		uhci_root_intr_done(struct usbd_xfer *);
    253       1.119  augustss 
    254  1.264.4.25     skrll Static usbd_status	uhci_open(struct usbd_pipe *);
    255       1.119  augustss Static void		uhci_poll(struct usbd_bus *);
    256       1.133  augustss Static void		uhci_softintr(void *);
    257       1.119  augustss 
    258       1.119  augustss Static void		uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *);
    259       1.158  augustss Static void		uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *);
    260  1.264.4.15     skrll Static usbd_status	uhci_device_setintr(uhci_softc_t *,
    261  1.264.4.15     skrll 			    struct uhci_pipe *, int);
    262       1.119  augustss 
    263  1.264.4.25     skrll Static void		uhci_device_clear_toggle(struct usbd_pipe *);
    264  1.264.4.25     skrll Static void		uhci_noop(struct usbd_pipe *);
    265       1.119  augustss 
    266  1.264.4.42     skrll static inline uhci_soft_qh_t *
    267  1.264.4.42     skrll 			uhci_find_prev_qh(uhci_soft_qh_t *, uhci_soft_qh_t *);
    268       1.119  augustss 
    269       1.119  augustss #ifdef UHCI_DEBUG
    270       1.119  augustss Static void		uhci_dump_all(uhci_softc_t *);
    271       1.119  augustss Static void		uhci_dumpregs(uhci_softc_t *);
    272       1.119  augustss Static void		uhci_dump_qhs(uhci_soft_qh_t *);
    273       1.119  augustss Static void		uhci_dump_qh(uhci_soft_qh_t *);
    274       1.119  augustss Static void		uhci_dump_tds(uhci_soft_td_t *);
    275       1.119  augustss Static void		uhci_dump_td(uhci_soft_td_t *);
    276  1.264.4.40     skrll Static void		uhci_dump_ii(struct uhci_xfer *);
    277       1.119  augustss void			uhci_dump(void);
    278         1.1  augustss #endif
    279         1.1  augustss 
    280       1.112  augustss #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \
    281       1.112  augustss 			BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
    282       1.112  augustss #define UWRITE1(sc, r, x) \
    283       1.165   dsainty  do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \
    284       1.165   dsainty  } while (/*CONSTCOND*/0)
    285       1.112  augustss #define UWRITE2(sc, r, x) \
    286       1.165   dsainty  do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \
    287       1.165   dsainty  } while (/*CONSTCOND*/0)
    288       1.112  augustss #define UWRITE4(sc, r, x) \
    289       1.165   dsainty  do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \
    290       1.165   dsainty  } while (/*CONSTCOND*/0)
    291  1.264.4.42     skrll 
    292       1.196       mrg static __inline uint8_t
    293       1.196       mrg UREAD1(uhci_softc_t *sc, bus_size_t r)
    294       1.196       mrg {
    295       1.196       mrg 
    296       1.196       mrg 	UBARR(sc);
    297       1.196       mrg 	return bus_space_read_1(sc->iot, sc->ioh, r);
    298       1.196       mrg }
    299       1.196       mrg 
    300       1.196       mrg static __inline uint16_t
    301       1.196       mrg UREAD2(uhci_softc_t *sc, bus_size_t r)
    302       1.196       mrg {
    303       1.196       mrg 
    304       1.196       mrg 	UBARR(sc);
    305       1.196       mrg 	return bus_space_read_2(sc->iot, sc->ioh, r);
    306       1.196       mrg }
    307       1.196       mrg 
    308       1.260     joerg #ifdef UHCI_DEBUG
    309       1.196       mrg static __inline uint32_t
    310       1.196       mrg UREAD4(uhci_softc_t *sc, bus_size_t r)
    311       1.196       mrg {
    312       1.196       mrg 
    313       1.196       mrg 	UBARR(sc);
    314       1.196       mrg 	return bus_space_read_4(sc->iot, sc->ioh, r);
    315       1.196       mrg }
    316       1.260     joerg #endif
    317         1.1  augustss 
    318         1.1  augustss #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd)
    319         1.1  augustss #define UHCISTS(sc) UREAD2(sc, UHCI_STS)
    320         1.1  augustss 
    321       1.142  augustss #define UHCI_RESET_TIMEOUT 100	/* ms, reset timeout */
    322         1.1  augustss 
    323         1.1  augustss #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK)
    324         1.1  augustss 
    325       1.208  drochner const struct usbd_bus_methods uhci_bus_methods = {
    326   1.264.4.5     skrll 	.ubm_open =	uhci_open,
    327   1.264.4.5     skrll 	.ubm_softint =	uhci_softintr,
    328   1.264.4.5     skrll 	.ubm_dopoll =	uhci_poll,
    329   1.264.4.5     skrll 	.ubm_allocx =	uhci_allocx,
    330   1.264.4.5     skrll 	.ubm_freex =	uhci_freex,
    331   1.264.4.5     skrll 	.ubm_getlock =	uhci_get_lock,
    332  1.264.4.12     skrll 	.ubm_rhctrl =	uhci_roothub_ctrl,
    333         1.1  augustss };
    334         1.1  augustss 
    335       1.208  drochner const struct usbd_pipe_methods uhci_root_intr_methods = {
    336   1.264.4.5     skrll 	.upm_transfer =	uhci_root_intr_transfer,
    337   1.264.4.5     skrll 	.upm_start =	uhci_root_intr_start,
    338   1.264.4.5     skrll 	.upm_abort =	uhci_root_intr_abort,
    339   1.264.4.5     skrll 	.upm_close =	uhci_root_intr_close,
    340   1.264.4.5     skrll 	.upm_cleartoggle =	uhci_noop,
    341   1.264.4.5     skrll 	.upm_done =	uhci_root_intr_done,
    342         1.1  augustss };
    343         1.1  augustss 
    344       1.208  drochner const struct usbd_pipe_methods uhci_device_ctrl_methods = {
    345  1.264.4.55     skrll 	.upm_init =	uhci_device_ctrl_init,
    346  1.264.4.55     skrll 	.upm_fini =	uhci_device_ctrl_fini,
    347   1.264.4.5     skrll 	.upm_transfer =	uhci_device_ctrl_transfer,
    348   1.264.4.5     skrll 	.upm_start =	uhci_device_ctrl_start,
    349   1.264.4.5     skrll 	.upm_abort =	uhci_device_ctrl_abort,
    350   1.264.4.5     skrll 	.upm_close =	uhci_device_ctrl_close,
    351   1.264.4.5     skrll 	.upm_cleartoggle =	uhci_noop,
    352   1.264.4.5     skrll 	.upm_done =	uhci_device_ctrl_done,
    353         1.1  augustss };
    354         1.1  augustss 
    355       1.208  drochner const struct usbd_pipe_methods uhci_device_intr_methods = {
    356  1.264.4.55     skrll 	.upm_init =	uhci_device_intr_init,
    357  1.264.4.55     skrll 	.upm_fini =	uhci_device_intr_fini,
    358   1.264.4.5     skrll 	.upm_transfer =	uhci_device_intr_transfer,
    359   1.264.4.5     skrll 	.upm_start =	uhci_device_intr_start,
    360   1.264.4.5     skrll 	.upm_abort =	uhci_device_intr_abort,
    361   1.264.4.5     skrll 	.upm_close =	uhci_device_intr_close,
    362   1.264.4.5     skrll 	.upm_cleartoggle =	uhci_device_clear_toggle,
    363   1.264.4.5     skrll 	.upm_done =	uhci_device_intr_done,
    364         1.1  augustss };
    365         1.1  augustss 
    366       1.208  drochner const struct usbd_pipe_methods uhci_device_bulk_methods = {
    367  1.264.4.55     skrll 	.upm_init =	uhci_device_bulk_init,
    368  1.264.4.55     skrll 	.upm_fini =	uhci_device_bulk_fini,
    369   1.264.4.5     skrll 	.upm_transfer =	uhci_device_bulk_transfer,
    370   1.264.4.5     skrll 	.upm_start =	uhci_device_bulk_start,
    371   1.264.4.5     skrll 	.upm_abort =	uhci_device_bulk_abort,
    372   1.264.4.5     skrll 	.upm_close =	uhci_device_bulk_close,
    373   1.264.4.5     skrll 	.upm_cleartoggle =	uhci_device_clear_toggle,
    374   1.264.4.5     skrll 	.upm_done =	uhci_device_bulk_done,
    375         1.1  augustss };
    376         1.1  augustss 
    377       1.208  drochner const struct usbd_pipe_methods uhci_device_isoc_methods = {
    378  1.264.4.55     skrll 	.upm_init =	uhci_device_isoc_init,
    379  1.264.4.55     skrll 	.upm_fini =	uhci_device_isoc_fini,
    380   1.264.4.5     skrll 	.upm_transfer =	uhci_device_isoc_transfer,
    381   1.264.4.5     skrll 	.upm_abort =	uhci_device_isoc_abort,
    382   1.264.4.5     skrll 	.upm_close =	uhci_device_isoc_close,
    383   1.264.4.5     skrll 	.upm_cleartoggle =	uhci_noop,
    384   1.264.4.5     skrll 	.upm_done =	uhci_device_isoc_done,
    385        1.16  augustss };
    386        1.16  augustss 
    387  1.264.4.61     skrll static inline void
    388  1.264.4.61     skrll uhci_add_intr_list(uhci_softc_t *sc, struct uhci_xfer *ux)
    389  1.264.4.61     skrll {
    390  1.264.4.61     skrll 
    391  1.264.4.61     skrll 	TAILQ_INSERT_TAIL(&sc->sc_intrhead, ux, ux_list);
    392  1.264.4.61     skrll }
    393  1.264.4.61     skrll 
    394  1.264.4.61     skrll static inline void
    395  1.264.4.61     skrll uhci_del_intr_list(uhci_softc_t *sc, struct uhci_xfer *ux)
    396  1.264.4.61     skrll {
    397  1.264.4.61     skrll 
    398  1.264.4.61     skrll 	TAILQ_REMOVE(&sc->sc_intrhead, ux, ux_list);
    399  1.264.4.61     skrll }
    400        1.92  augustss 
    401       1.240  jakllsch static inline uhci_soft_qh_t *
    402       1.119  augustss uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh)
    403        1.92  augustss {
    404  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
    405  1.264.4.21     skrll 	DPRINTFN(15, "pqh=%p sqh=%p", pqh, sqh, 0, 0);
    406        1.92  augustss 
    407        1.92  augustss 	for (; pqh->hlink != sqh; pqh = pqh->hlink) {
    408       1.152  augustss #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG)
    409       1.223    bouyer 		usb_syncmem(&pqh->dma,
    410       1.223    bouyer 		    pqh->offs + offsetof(uhci_qh_t, qh_hlink),
    411       1.223    bouyer 		    sizeof(pqh->qh.qh_hlink),
    412       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE);
    413        1.92  augustss 		if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) {
    414  1.264.4.65     skrll 			printf("%s: QH not found\n", __func__);
    415  1.264.4.13     skrll 			return NULL;
    416        1.92  augustss 		}
    417        1.92  augustss #endif
    418        1.92  augustss 	}
    419  1.264.4.13     skrll 	return pqh;
    420        1.92  augustss }
    421        1.92  augustss 
    422         1.1  augustss void
    423       1.142  augustss uhci_globalreset(uhci_softc_t *sc)
    424         1.1  augustss {
    425         1.1  augustss 	UHCICMD(sc, UHCI_CMD_GRESET);	/* global reset */
    426        1.20  augustss 	usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */
    427         1.1  augustss 	UHCICMD(sc, 0);			/* do nothing */
    428         1.1  augustss }
    429         1.1  augustss 
    430  1.264.4.14     skrll int
    431       1.119  augustss uhci_init(uhci_softc_t *sc)
    432         1.1  augustss {
    433        1.63  augustss 	usbd_status err;
    434         1.1  augustss 	int i, j;
    435       1.123  augustss 	uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh;
    436         1.1  augustss 	uhci_soft_td_t *std;
    437         1.1  augustss 
    438  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
    439         1.1  augustss 
    440        1.67  augustss #ifdef UHCI_DEBUG
    441        1.92  augustss 	thesc = sc;
    442        1.92  augustss 
    443  1.264.4.43     skrll 	if (uhcidebug >= 2)
    444         1.1  augustss 		uhci_dumpregs(sc);
    445         1.1  augustss #endif
    446         1.1  augustss 
    447       1.219  jmcneill 	sc->sc_suspend = PWR_RESUME;
    448       1.219  jmcneill 
    449         1.1  augustss 	UWRITE2(sc, UHCI_INTR, 0);		/* disable interrupts */
    450       1.142  augustss 	uhci_globalreset(sc);			/* reset the controller */
    451       1.142  augustss 	uhci_reset(sc);
    452        1.24  augustss 
    453         1.1  augustss 	/* Allocate and initialize real frame array. */
    454       1.152  augustss 	err = usb_allocmem(&sc->sc_bus,
    455  1.264.4.49     skrll 	    UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t),
    456  1.264.4.49     skrll 	    UHCI_FRAMELIST_ALIGN, &sc->sc_dma);
    457        1.63  augustss 	if (err)
    458  1.264.4.13     skrll 		return err;
    459       1.159  augustss 	sc->sc_pframes = KERNADDR(&sc->sc_dma, 0);
    460         1.1  augustss 	UWRITE2(sc, UHCI_FRNUM, 0);		/* set frame number to 0 */
    461       1.160  augustss 	UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/
    462         1.1  augustss 
    463  1.264.4.55     skrll 	/* Initialise mutex early for uhci_alloc_* */
    464  1.264.4.55     skrll 	mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
    465  1.264.4.55     skrll 	mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB);
    466  1.264.4.55     skrll 
    467       1.152  augustss 	/*
    468       1.123  augustss 	 * Allocate a TD, inactive, that hangs from the last QH.
    469       1.123  augustss 	 * This is to avoid a bug in the PIIX that makes it run berserk
    470       1.123  augustss 	 * otherwise.
    471       1.123  augustss 	 */
    472       1.123  augustss 	std = uhci_alloc_std(sc);
    473       1.123  augustss 	if (std == NULL)
    474  1.264.4.14     skrll 		return ENOMEM;
    475       1.123  augustss 	std->link.std = NULL;
    476       1.123  augustss 	std->td.td_link = htole32(UHCI_PTR_T);
    477       1.123  augustss 	std->td.td_status = htole32(0); /* inactive */
    478       1.123  augustss 	std->td.td_token = htole32(0);
    479       1.123  augustss 	std->td.td_buffer = htole32(0);
    480       1.223    bouyer 	usb_syncmem(&std->dma, std->offs, sizeof(std->td),
    481       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
    482       1.123  augustss 
    483       1.123  augustss 	/* Allocate the dummy QH marking the end and used for looping the QHs.*/
    484       1.123  augustss 	lsqh = uhci_alloc_sqh(sc);
    485       1.123  augustss 	if (lsqh == NULL)
    486  1.264.4.55     skrll 		goto fail1;
    487       1.123  augustss 	lsqh->hlink = NULL;
    488       1.123  augustss 	lsqh->qh.qh_hlink = htole32(UHCI_PTR_T);	/* end of QH chain */
    489       1.123  augustss 	lsqh->elink = std;
    490       1.123  augustss 	lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD);
    491       1.123  augustss 	sc->sc_last_qh = lsqh;
    492       1.223    bouyer 	usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh),
    493       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
    494       1.123  augustss 
    495         1.1  augustss 	/* Allocate the dummy QH where bulk traffic will be queued. */
    496         1.1  augustss 	bsqh = uhci_alloc_sqh(sc);
    497        1.63  augustss 	if (bsqh == NULL)
    498  1.264.4.55     skrll 		goto fail2;
    499       1.123  augustss 	bsqh->hlink = lsqh;
    500       1.123  augustss 	bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH);
    501       1.121  augustss 	bsqh->elink = NULL;
    502        1.88   tsutsui 	bsqh->qh.qh_elink = htole32(UHCI_PTR_T);
    503         1.1  augustss 	sc->sc_bulk_start = sc->sc_bulk_end = bsqh;
    504       1.223    bouyer 	usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh),
    505       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
    506         1.1  augustss 
    507       1.123  augustss 	/* Allocate dummy QH where high speed control traffic will be queued. */
    508       1.123  augustss 	chsqh = uhci_alloc_sqh(sc);
    509       1.123  augustss 	if (chsqh == NULL)
    510  1.264.4.55     skrll 		goto fail3;
    511       1.123  augustss 	chsqh->hlink = bsqh;
    512       1.123  augustss 	chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH);
    513       1.123  augustss 	chsqh->elink = NULL;
    514       1.123  augustss 	chsqh->qh.qh_elink = htole32(UHCI_PTR_T);
    515       1.123  augustss 	sc->sc_hctl_start = sc->sc_hctl_end = chsqh;
    516       1.223    bouyer 	usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh),
    517       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
    518       1.123  augustss 
    519       1.123  augustss 	/* Allocate dummy QH where control traffic will be queued. */
    520       1.123  augustss 	clsqh = uhci_alloc_sqh(sc);
    521       1.123  augustss 	if (clsqh == NULL)
    522  1.264.4.55     skrll 		goto fail4;
    523       1.220    bouyer 	clsqh->hlink = chsqh;
    524       1.123  augustss 	clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH);
    525       1.123  augustss 	clsqh->elink = NULL;
    526       1.123  augustss 	clsqh->qh.qh_elink = htole32(UHCI_PTR_T);
    527       1.123  augustss 	sc->sc_lctl_start = sc->sc_lctl_end = clsqh;
    528       1.223    bouyer 	usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh),
    529       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
    530         1.1  augustss 
    531       1.152  augustss 	/*
    532         1.1  augustss 	 * Make all (virtual) frame list pointers point to the interrupt
    533         1.1  augustss 	 * queue heads and the interrupt queue heads at the control
    534         1.1  augustss 	 * queue head and point the physical frame list to the virtual.
    535         1.1  augustss 	 */
    536  1.264.4.24     skrll 	for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
    537         1.1  augustss 		std = uhci_alloc_std(sc);
    538         1.1  augustss 		sqh = uhci_alloc_sqh(sc);
    539        1.67  augustss 		if (std == NULL || sqh == NULL)
    540  1.264.4.13     skrll 			return USBD_NOMEM;
    541        1.42  augustss 		std->link.sqh = sqh;
    542       1.121  augustss 		std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH);
    543        1.88   tsutsui 		std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */
    544        1.88   tsutsui 		std->td.td_token = htole32(0);
    545        1.88   tsutsui 		std->td.td_buffer = htole32(0);
    546       1.223    bouyer 		usb_syncmem(&std->dma, std->offs, sizeof(std->td),
    547       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
    548       1.123  augustss 		sqh->hlink = clsqh;
    549       1.123  augustss 		sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH);
    550       1.121  augustss 		sqh->elink = NULL;
    551        1.88   tsutsui 		sqh->qh.qh_elink = htole32(UHCI_PTR_T);
    552       1.223    bouyer 		usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
    553       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
    554         1.1  augustss 		sc->sc_vframes[i].htd = std;
    555         1.1  augustss 		sc->sc_vframes[i].etd = std;
    556         1.1  augustss 		sc->sc_vframes[i].hqh = sqh;
    557         1.1  augustss 		sc->sc_vframes[i].eqh = sqh;
    558       1.152  augustss 		for (j = i;
    559       1.152  augustss 		     j < UHCI_FRAMELIST_COUNT;
    560         1.1  augustss 		     j += UHCI_VFRAMELIST_COUNT)
    561        1.88   tsutsui 			sc->sc_pframes[j] = htole32(std->physaddr);
    562         1.1  augustss 	}
    563       1.223    bouyer 	usb_syncmem(&sc->sc_dma, 0,
    564       1.223    bouyer 	    UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t),
    565       1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
    566       1.223    bouyer 
    567         1.1  augustss 
    568  1.264.4.39     skrll 	TAILQ_INIT(&sc->sc_intrhead);
    569         1.1  augustss 
    570       1.253  christos 	sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0,
    571       1.253  christos 	    "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL);
    572        1.76  augustss 
    573       1.248       mrg 	callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE);
    574       1.248       mrg 
    575       1.248       mrg 	cv_init(&sc->sc_softwake_cv, "uhciab");
    576        1.96  augustss 
    577         1.1  augustss 	/* Set up the bus struct. */
    578   1.264.4.7     skrll 	sc->sc_bus.ub_methods = &uhci_bus_methods;
    579   1.264.4.7     skrll 	sc->sc_bus.ub_pipesize = sizeof(struct uhci_pipe);
    580   1.264.4.7     skrll 	sc->sc_bus.ub_usedma = true;
    581         1.1  augustss 
    582       1.190  augustss 	UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */
    583       1.190  augustss 
    584  1.264.4.27     skrll 	DPRINTF("Enabling...", 0, 0, 0, 0);
    585       1.225    bouyer 
    586  1.264.4.24     skrll 	err = uhci_run(sc, 1, 0);		/* and here we go... */
    587       1.152  augustss 	UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE |
    588         1.1  augustss 		UHCI_INTR_IOCE | UHCI_INTR_SPIE);	/* enable interrupts */
    589       1.225    bouyer 	return err;
    590  1.264.4.55     skrll 
    591  1.264.4.55     skrll fail4:
    592  1.264.4.55     skrll 	uhci_free_sqh(sc, chsqh);
    593  1.264.4.55     skrll fail3:
    594  1.264.4.55     skrll 	uhci_free_sqh(sc, lsqh);
    595  1.264.4.55     skrll fail2:
    596  1.264.4.55     skrll 	uhci_free_sqh(sc, lsqh);
    597  1.264.4.55     skrll fail1:
    598  1.264.4.55     skrll 	uhci_free_std(sc, std);
    599  1.264.4.55     skrll 
    600  1.264.4.55     skrll 	return ENOMEM;
    601        1.53  augustss }
    602        1.53  augustss 
    603        1.53  augustss int
    604       1.215    dyoung uhci_activate(device_t self, enum devact act)
    605        1.53  augustss {
    606       1.215    dyoung 	struct uhci_softc *sc = device_private(self);
    607        1.53  augustss 
    608        1.53  augustss 	switch (act) {
    609        1.53  augustss 	case DVACT_DEACTIVATE:
    610       1.210  kiyohara 		sc->sc_dying = 1;
    611       1.230    dyoung 		return 0;
    612       1.230    dyoung 	default:
    613       1.230    dyoung 		return EOPNOTSUPP;
    614        1.53  augustss 	}
    615        1.53  augustss }
    616        1.53  augustss 
    617       1.215    dyoung void
    618       1.215    dyoung uhci_childdet(device_t self, device_t child)
    619       1.215    dyoung {
    620       1.215    dyoung 	struct uhci_softc *sc = device_private(self);
    621       1.215    dyoung 
    622       1.215    dyoung 	KASSERT(sc->sc_child == child);
    623       1.215    dyoung 	sc->sc_child = NULL;
    624       1.215    dyoung }
    625       1.215    dyoung 
    626        1.53  augustss int
    627       1.119  augustss uhci_detach(struct uhci_softc *sc, int flags)
    628        1.53  augustss {
    629        1.53  augustss 	int rv = 0;
    630        1.53  augustss 
    631        1.53  augustss 	if (sc->sc_child != NULL)
    632        1.53  augustss 		rv = config_detach(sc->sc_child, flags);
    633       1.152  augustss 
    634        1.53  augustss 	if (rv != 0)
    635  1.264.4.13     skrll 		return rv;
    636        1.53  augustss 
    637       1.226        ad 	callout_halt(&sc->sc_poll_handle, NULL);
    638       1.226        ad 	callout_destroy(&sc->sc_poll_handle);
    639       1.226        ad 
    640       1.248       mrg 	cv_destroy(&sc->sc_softwake_cv);
    641       1.248       mrg 
    642       1.248       mrg 	mutex_destroy(&sc->sc_lock);
    643       1.248       mrg 	mutex_destroy(&sc->sc_intr_lock);
    644       1.248       mrg 
    645       1.254  christos 	pool_cache_destroy(sc->sc_xferpool);
    646       1.254  christos 
    647        1.76  augustss 	/* XXX free other data structures XXX */
    648        1.53  augustss 
    649  1.264.4.13     skrll 	return rv;
    650         1.1  augustss }
    651         1.1  augustss 
    652  1.264.4.25     skrll struct usbd_xfer *
    653  1.264.4.36     skrll uhci_allocx(struct usbd_bus *bus, unsigned int nframes)
    654        1.76  augustss {
    655  1.264.4.37     skrll 	struct uhci_softc *sc = UHCI_BUS2SC(bus);
    656  1.264.4.25     skrll 	struct usbd_xfer *xfer;
    657        1.76  augustss 
    658       1.253  christos 	xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT);
    659        1.92  augustss 	if (xfer != NULL) {
    660       1.253  christos 		memset(xfer, 0, sizeof(struct uhci_xfer));
    661  1.264.4.31     skrll 
    662        1.92  augustss #ifdef DIAGNOSTIC
    663  1.264.4.40     skrll 		struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
    664  1.264.4.41     skrll 		uxfer->ux_isdone = true;
    665   1.264.4.7     skrll 		xfer->ux_state = XFER_BUSY;
    666        1.92  augustss #endif
    667        1.92  augustss 	}
    668  1.264.4.13     skrll 	return xfer;
    669        1.76  augustss }
    670        1.76  augustss 
    671        1.76  augustss void
    672  1.264.4.25     skrll uhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer)
    673        1.76  augustss {
    674  1.264.4.37     skrll 	struct uhci_softc *sc = UHCI_BUS2SC(bus);
    675  1.264.4.37     skrll 	struct uhci_xfer *uxfer __diagused = UHCI_XFER2UXFER(xfer);
    676        1.76  augustss 
    677  1.264.4.31     skrll 	KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer,
    678  1.264.4.31     skrll 	    xfer->ux_state);
    679  1.264.4.41     skrll 	KASSERTMSG(uxfer->ux_isdone, "xfer %p not done\n", xfer);
    680        1.93  augustss #ifdef DIAGNOSTIC
    681   1.264.4.7     skrll 	xfer->ux_state = XFER_FREE;
    682        1.93  augustss #endif
    683       1.253  christos 	pool_cache_put(sc->sc_xferpool, xfer);
    684        1.48  augustss }
    685        1.48  augustss 
    686       1.248       mrg Static void
    687       1.248       mrg uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock)
    688       1.248       mrg {
    689  1.264.4.37     skrll 	struct uhci_softc *sc = UHCI_BUS2SC(bus);
    690       1.248       mrg 
    691       1.248       mrg 	*lock = &sc->sc_lock;
    692       1.248       mrg }
    693       1.248       mrg 
    694       1.248       mrg 
    695        1.72  augustss /*
    696       1.212  jmcneill  * Handle suspend/resume.
    697       1.212  jmcneill  *
    698       1.212  jmcneill  * We need to switch to polling mode here, because this routine is
    699       1.212  jmcneill  * called from an interrupt context.  This is all right since we
    700       1.212  jmcneill  * are almost suspended anyway.
    701        1.72  augustss  */
    702       1.212  jmcneill bool
    703       1.232    dyoung uhci_resume(device_t dv, const pmf_qual_t *qual)
    704        1.72  augustss {
    705       1.212  jmcneill 	uhci_softc_t *sc = device_private(dv);
    706       1.212  jmcneill 	int cmd;
    707        1.72  augustss 
    708       1.248       mrg 	mutex_spin_enter(&sc->sc_intr_lock);
    709       1.193  augustss 
    710       1.212  jmcneill 	cmd = UREAD2(sc, UHCI_CMD);
    711   1.264.4.7     skrll 	sc->sc_bus.ub_usepolling++;
    712       1.214       smb 	UWRITE2(sc, UHCI_INTR, 0);
    713       1.214       smb 	uhci_globalreset(sc);
    714       1.214       smb 	uhci_reset(sc);
    715       1.212  jmcneill 	if (cmd & UHCI_CMD_RS)
    716       1.249  drochner 		uhci_run(sc, 0, 1);
    717       1.212  jmcneill 
    718       1.212  jmcneill 	/* restore saved state */
    719       1.212  jmcneill 	UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0));
    720       1.212  jmcneill 	UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum);
    721       1.212  jmcneill 	UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof);
    722       1.212  jmcneill 
    723       1.212  jmcneill 	UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */
    724       1.248       mrg 	usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock);
    725       1.212  jmcneill 	UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */
    726       1.212  jmcneill 	UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE |
    727       1.212  jmcneill 	    UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE);
    728       1.214       smb 	UHCICMD(sc, UHCI_CMD_MAXP);
    729       1.249  drochner 	uhci_run(sc, 1, 1); /* and start traffic again */
    730       1.248       mrg 	usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock);
    731   1.264.4.7     skrll 	sc->sc_bus.ub_usepolling--;
    732       1.212  jmcneill 	if (sc->sc_intr_xfer != NULL)
    733       1.234    dyoung 		callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub,
    734       1.212  jmcneill 		    sc->sc_intr_xfer);
    735       1.212  jmcneill #ifdef UHCI_DEBUG
    736  1.264.4.43     skrll 	if (uhcidebug >= 2)
    737       1.212  jmcneill 		uhci_dumpregs(sc);
    738       1.212  jmcneill #endif
    739       1.212  jmcneill 
    740       1.219  jmcneill 	sc->sc_suspend = PWR_RESUME;
    741       1.248       mrg 	mutex_spin_exit(&sc->sc_intr_lock);
    742       1.212  jmcneill 
    743       1.212  jmcneill 	return true;
    744        1.72  augustss }
    745        1.72  augustss 
    746       1.212  jmcneill bool
    747       1.232    dyoung uhci_suspend(device_t dv, const pmf_qual_t *qual)
    748        1.30  augustss {
    749       1.212  jmcneill 	uhci_softc_t *sc = device_private(dv);
    750        1.30  augustss 	int cmd;
    751        1.30  augustss 
    752       1.248       mrg 	mutex_spin_enter(&sc->sc_intr_lock);
    753       1.212  jmcneill 
    754        1.30  augustss 	cmd = UREAD2(sc, UHCI_CMD);
    755        1.30  augustss 
    756       1.212  jmcneill #ifdef UHCI_DEBUG
    757  1.264.4.43     skrll 	if (uhcidebug >= 2)
    758       1.212  jmcneill 		uhci_dumpregs(sc);
    759       1.212  jmcneill #endif
    760       1.212  jmcneill 	if (sc->sc_intr_xfer != NULL)
    761       1.234    dyoung 		callout_stop(&sc->sc_poll_handle);
    762       1.219  jmcneill 	sc->sc_suspend = PWR_SUSPEND;
    763   1.264.4.7     skrll 	sc->sc_bus.ub_usepolling++;
    764       1.219  jmcneill 
    765       1.249  drochner 	uhci_run(sc, 0, 1); /* stop the controller */
    766       1.212  jmcneill 	cmd &= ~UHCI_CMD_RS;
    767       1.212  jmcneill 
    768       1.212  jmcneill 	/* save some state if BIOS doesn't */
    769       1.212  jmcneill 	sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM);
    770       1.212  jmcneill 	sc->sc_saved_sof = UREAD1(sc, UHCI_SOF);
    771       1.212  jmcneill 
    772       1.212  jmcneill 	UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */
    773        1.30  augustss 
    774       1.212  jmcneill 	UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */
    775       1.248       mrg 	usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock);
    776   1.264.4.7     skrll 	sc->sc_bus.ub_usepolling--;
    777        1.86  augustss 
    778       1.248       mrg 	mutex_spin_exit(&sc->sc_intr_lock);
    779       1.212  jmcneill 
    780       1.212  jmcneill 	return true;
    781        1.30  augustss }
    782        1.30  augustss 
    783        1.59  augustss #ifdef UHCI_DEBUG
    784       1.101  augustss Static void
    785       1.119  augustss uhci_dumpregs(uhci_softc_t *sc)
    786         1.1  augustss {
    787  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
    788  1.264.4.27     skrll 	DPRINTF("cmd =%04x  sts    =%04x  intr   =%04x  frnum =%04x",
    789  1.264.4.21     skrll 	    UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS),
    790  1.264.4.21     skrll 	    UREAD2(sc, UHCI_INTR), UREAD2(sc, UHCI_FRNUM));
    791  1.264.4.27     skrll 	DPRINTF("sof =%04x  portsc1=%04x  portsc2=%04x  flbase=%08x",
    792  1.264.4.21     skrll 	    UREAD1(sc, UHCI_SOF), UREAD2(sc, UHCI_PORTSC1),
    793  1.264.4.21     skrll 	    UREAD2(sc, UHCI_PORTSC2), UREAD4(sc, UHCI_FLBASEADDR));
    794         1.1  augustss }
    795         1.1  augustss 
    796         1.1  augustss void
    797       1.119  augustss uhci_dump_td(uhci_soft_td_t *p)
    798         1.1  augustss {
    799  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
    800       1.250  christos 
    801       1.223    bouyer 	usb_syncmem(&p->dma, p->offs, sizeof(p->td),
    802       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
    803  1.264.4.21     skrll 
    804  1.264.4.44     skrll 	DPRINTF("TD(%p) at 0x%08x", p, p->physaddr, 0, 0);
    805  1.264.4.27     skrll  	DPRINTF("   link=0x%08x status=0x%08x "
    806  1.264.4.21     skrll 	    "token=0x%08x buffer=0x%08x",
    807  1.264.4.21     skrll 	     le32toh(p->td.td_link),
    808  1.264.4.21     skrll 	     le32toh(p->td.td_status),
    809  1.264.4.21     skrll 	     le32toh(p->td.td_token),
    810  1.264.4.21     skrll 	     le32toh(p->td.td_buffer));
    811  1.264.4.21     skrll 
    812  1.264.4.27     skrll 	DPRINTF("bitstuff=%d crcto   =%d nak     =%d babble  =%d",
    813  1.264.4.21     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_BITSTUFF),
    814  1.264.4.21     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_CRCTO),
    815  1.264.4.21     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_NAK),
    816  1.264.4.21     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_BABBLE));
    817  1.264.4.27     skrll 	DPRINTF("dbuffer =%d stalled =%d active  =%d ioc     =%d",
    818  1.264.4.21     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_DBUFFER),
    819  1.264.4.21     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_STALLED),
    820  1.264.4.21     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_ACTIVE),
    821  1.264.4.21     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_IOC));
    822  1.264.4.27     skrll 	DPRINTF("ios     =%d ls      =%d spd     =%d",
    823  1.264.4.21     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_IOS),
    824  1.264.4.21     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_LS),
    825  1.264.4.21     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_SPD), 0);
    826  1.264.4.27     skrll 	DPRINTF("errcnt  =%d actlen  =%d pid=%02x",
    827  1.264.4.21     skrll 	    UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)),
    828  1.264.4.21     skrll 	    UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)),
    829  1.264.4.21     skrll 	    UHCI_TD_GET_PID(le32toh(p->td.td_token)), 0);
    830  1.264.4.27     skrll 	DPRINTF("addr=%d  endpt=%d  D=%d  maxlen=%d,",
    831  1.264.4.21     skrll 	    UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)),
    832  1.264.4.21     skrll 	    UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)),
    833  1.264.4.21     skrll 	    UHCI_TD_GET_DT(le32toh(p->td.td_token)),
    834  1.264.4.21     skrll 	    UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token)));
    835         1.1  augustss }
    836         1.1  augustss 
    837         1.1  augustss void
    838       1.119  augustss uhci_dump_qh(uhci_soft_qh_t *sqh)
    839         1.1  augustss {
    840  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
    841  1.264.4.21     skrll 
    842       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
    843       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
    844  1.264.4.21     skrll 
    845  1.264.4.44     skrll 	DPRINTF("QH(%p) at 0x%08x: hlink=%08x elink=%08x", sqh,
    846        1.88   tsutsui 	    (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink),
    847  1.264.4.21     skrll 	    le32toh(sqh->qh.qh_elink));
    848  1.264.4.21     skrll 
    849       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD);
    850         1.1  augustss }
    851         1.1  augustss 
    852        1.13  augustss 
    853       1.110  augustss #if 1
    854         1.1  augustss void
    855       1.119  augustss uhci_dump(void)
    856         1.1  augustss {
    857       1.110  augustss 	uhci_dump_all(thesc);
    858       1.110  augustss }
    859       1.110  augustss #endif
    860         1.1  augustss 
    861       1.110  augustss void
    862       1.119  augustss uhci_dump_all(uhci_softc_t *sc)
    863       1.110  augustss {
    864         1.1  augustss 	uhci_dumpregs(sc);
    865       1.110  augustss 	/*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/
    866       1.261     skrll 	uhci_dump_qhs(sc->sc_lctl_start);
    867         1.1  augustss }
    868         1.1  augustss 
    869        1.67  augustss 
    870        1.67  augustss void
    871       1.119  augustss uhci_dump_qhs(uhci_soft_qh_t *sqh)
    872        1.67  augustss {
    873  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
    874  1.264.4.21     skrll 
    875        1.67  augustss 	uhci_dump_qh(sqh);
    876        1.67  augustss 
    877  1.264.4.18     skrll 	/*
    878  1.264.4.18     skrll 	 * uhci_dump_qhs displays all the QHs and TDs from the given QH onwards
    879        1.67  augustss 	 * Traverses sideways first, then down.
    880        1.67  augustss 	 *
    881        1.67  augustss 	 * QH1
    882        1.67  augustss 	 * QH2
    883        1.67  augustss 	 * No QH
    884        1.67  augustss 	 * TD2.1
    885        1.67  augustss 	 * TD2.2
    886        1.67  augustss 	 * TD1.1
    887        1.67  augustss 	 * etc.
    888        1.67  augustss 	 *
    889        1.67  augustss 	 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1.
    890        1.67  augustss 	 */
    891        1.67  augustss 
    892       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
    893       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
    894        1.88   tsutsui 	if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T))
    895        1.67  augustss 		uhci_dump_qhs(sqh->hlink);
    896        1.67  augustss 	else
    897  1.264.4.27     skrll 		DPRINTF("No QH", 0, 0, 0, 0);
    898       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD);
    899        1.67  augustss 
    900        1.88   tsutsui 	if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T))
    901        1.67  augustss 		uhci_dump_tds(sqh->elink);
    902        1.67  augustss 	else
    903  1.264.4.27     skrll 		DPRINTF("No QH", 0, 0, 0, 0);
    904        1.67  augustss }
    905        1.67  augustss 
    906         1.1  augustss void
    907       1.119  augustss uhci_dump_tds(uhci_soft_td_t *std)
    908         1.1  augustss {
    909        1.67  augustss 	uhci_soft_td_t *td;
    910       1.223    bouyer 	int stop;
    911        1.67  augustss 
    912  1.264.4.24     skrll 	for (td = std; td != NULL; td = td->link.std) {
    913        1.67  augustss 		uhci_dump_td(td);
    914         1.1  augustss 
    915  1.264.4.18     skrll 		/*
    916  1.264.4.18     skrll 		 * Check whether the link pointer in this TD marks
    917        1.67  augustss 		 * the link pointer as end of queue. This avoids
    918        1.67  augustss 		 * printing the free list in case the queue/TD has
    919        1.67  augustss 		 * already been moved there (seatbelt).
    920        1.67  augustss 		 */
    921       1.223    bouyer 		usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link),
    922       1.223    bouyer 		    sizeof(td->td.td_link),
    923       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
    924       1.223    bouyer 		stop = (le32toh(td->td.td_link) & UHCI_PTR_T ||
    925       1.223    bouyer 			le32toh(td->td.td_link) == 0);
    926       1.223    bouyer 		usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link),
    927       1.223    bouyer 		    sizeof(td->td.td_link), BUS_DMASYNC_PREREAD);
    928       1.223    bouyer 		if (stop)
    929        1.67  augustss 			break;
    930        1.67  augustss 	}
    931         1.1  augustss }
    932        1.92  augustss 
    933       1.101  augustss Static void
    934  1.264.4.40     skrll uhci_dump_ii(struct uhci_xfer *ux)
    935        1.92  augustss {
    936  1.264.4.25     skrll 	struct usbd_pipe *pipe;
    937        1.95  augustss 	usb_endpoint_descriptor_t *ed;
    938  1.264.4.25     skrll 	struct usbd_device *dev;
    939       1.152  augustss 
    940  1.264.4.39     skrll 	if (ux == NULL) {
    941  1.264.4.39     skrll 		printf("ux NULL\n");
    942   1.264.4.2     skrll 		return;
    943   1.264.4.2     skrll 	}
    944  1.264.4.41     skrll 	pipe = ux->ux_xfer.ux_pipe;
    945   1.264.4.2     skrll 	if (pipe == NULL) {
    946  1.264.4.41     skrll 		printf("ux %p: done=%d pipe=NULL\n", ux, ux->ux_isdone);
    947   1.264.4.2     skrll 		return;
    948       1.139  augustss 	}
    949   1.264.4.7     skrll 	if (pipe->up_endpoint == NULL) {
    950  1.264.4.40     skrll 		printf("ux %p: done=%d pipe=%p pipe->up_endpoint=NULL\n",
    951  1.264.4.41     skrll 		       ux, ux->ux_isdone, pipe);
    952   1.264.4.2     skrll 		return;
    953       1.139  augustss 	}
    954   1.264.4.7     skrll 	if (pipe->up_dev == NULL) {
    955  1.264.4.40     skrll 		printf("ux %p: done=%d pipe=%p pipe->up_dev=NULL\n",
    956  1.264.4.41     skrll 		       ux, ux->ux_isdone, pipe);
    957   1.264.4.2     skrll 		return;
    958        1.95  augustss 	}
    959   1.264.4.7     skrll 	ed = pipe->up_endpoint->ue_edesc;
    960   1.264.4.7     skrll 	dev = pipe->up_dev;
    961  1.264.4.40     skrll 	printf("ux %p: done=%d dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n",
    962  1.264.4.41     skrll 	       ux, ux->ux_isdone, dev,
    963   1.264.4.7     skrll 	       UGETW(dev->ud_ddesc.idVendor),
    964   1.264.4.7     skrll 	       UGETW(dev->ud_ddesc.idProduct),
    965   1.264.4.7     skrll 	       dev->ud_addr, pipe,
    966        1.92  augustss 	       ed->bEndpointAddress, ed->bmAttributes);
    967        1.92  augustss }
    968        1.92  augustss 
    969       1.120  augustss void uhci_dump_iis(struct uhci_softc *sc);
    970        1.92  augustss void
    971       1.119  augustss uhci_dump_iis(struct uhci_softc *sc)
    972        1.92  augustss {
    973  1.264.4.40     skrll 	struct uhci_xfer *ux;
    974        1.92  augustss 
    975  1.264.4.39     skrll 	printf("interrupt list:\n");
    976  1.264.4.60     skrll 	TAILQ_FOREACH(ux, &sc->sc_intrhead, ux_list)
    977  1.264.4.39     skrll 		uhci_dump_ii(ux);
    978        1.92  augustss }
    979        1.92  augustss 
    980       1.120  augustss void iidump(void);
    981       1.119  augustss void iidump(void) { uhci_dump_iis(thesc); }
    982        1.92  augustss 
    983         1.1  augustss #endif
    984         1.1  augustss 
    985         1.1  augustss /*
    986         1.1  augustss  * This routine is executed periodically and simulates interrupts
    987         1.1  augustss  * from the root controller interrupt pipe for port status change.
    988         1.1  augustss  */
    989         1.1  augustss void
    990       1.119  augustss uhci_poll_hub(void *addr)
    991         1.1  augustss {
    992  1.264.4.25     skrll 	struct usbd_xfer *xfer = addr;
    993  1.264.4.25     skrll 	struct usbd_pipe *pipe = xfer->ux_pipe;
    994       1.227    martin 	uhci_softc_t *sc;
    995         1.1  augustss 	u_char *p;
    996         1.1  augustss 
    997  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
    998         1.1  augustss 
    999   1.264.4.7     skrll 	if (__predict_false(pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL))
   1000       1.228    martin 		return;	/* device has detached */
   1001  1.264.4.37     skrll 	sc = UHCI_PIPE2SC(pipe);
   1002       1.234    dyoung 	callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer);
   1003        1.41  augustss 
   1004   1.264.4.7     skrll 	p = xfer->ux_buf;
   1005         1.1  augustss 	p[0] = 0;
   1006         1.1  augustss 	if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC))
   1007         1.1  augustss 		p[0] |= 1<<1;
   1008         1.1  augustss 	if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC))
   1009         1.1  augustss 		p[0] |= 1<<2;
   1010        1.41  augustss 	if (p[0] == 0)
   1011        1.41  augustss 		/* No change, try again in a while */
   1012        1.41  augustss 		return;
   1013        1.41  augustss 
   1014   1.264.4.7     skrll 	xfer->ux_actlen = 1;
   1015   1.264.4.7     skrll 	xfer->ux_status = USBD_NORMAL_COMPLETION;
   1016       1.248       mrg 	mutex_enter(&sc->sc_lock);
   1017        1.63  augustss 	usb_transfer_complete(xfer);
   1018       1.248       mrg 	mutex_exit(&sc->sc_lock);
   1019        1.41  augustss }
   1020        1.41  augustss 
   1021        1.41  augustss void
   1022  1.264.4.25     skrll uhci_root_intr_done(struct usbd_xfer *xfer)
   1023        1.84  augustss {
   1024        1.84  augustss }
   1025        1.84  augustss 
   1026       1.123  augustss /*
   1027       1.123  augustss  * Let the last QH loop back to the high speed control transfer QH.
   1028       1.123  augustss  * This is what intel calls "bandwidth reclamation" and improves
   1029       1.123  augustss  * USB performance a lot for some devices.
   1030       1.123  augustss  * If we are already looping, just count it.
   1031       1.123  augustss  */
   1032         1.1  augustss void
   1033  1.264.4.17     skrll uhci_add_loop(uhci_softc_t *sc)
   1034  1.264.4.17     skrll {
   1035  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1036  1.264.4.25     skrll 
   1037       1.125  augustss #ifdef UHCI_DEBUG
   1038       1.125  augustss 	if (uhcinoloop)
   1039       1.125  augustss 		return;
   1040       1.125  augustss #endif
   1041       1.123  augustss 	if (++sc->sc_loops == 1) {
   1042  1.264.4.21     skrll 		DPRINTFN(5, "add loop", 0, 0, 0, 0);
   1043       1.123  augustss 		/* Note, we don't loop back the soft pointer. */
   1044       1.152  augustss 		sc->sc_last_qh->qh.qh_hlink =
   1045       1.123  augustss 		    htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH);
   1046       1.223    bouyer 		usb_syncmem(&sc->sc_last_qh->dma,
   1047       1.223    bouyer 		    sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink),
   1048       1.223    bouyer 		    sizeof(sc->sc_last_qh->qh.qh_hlink),
   1049       1.223    bouyer 		    BUS_DMASYNC_PREWRITE);
   1050       1.123  augustss 	}
   1051       1.123  augustss }
   1052       1.123  augustss 
   1053       1.123  augustss void
   1054  1.264.4.17     skrll uhci_rem_loop(uhci_softc_t *sc)
   1055  1.264.4.17     skrll {
   1056  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1057  1.264.4.21     skrll 
   1058       1.125  augustss #ifdef UHCI_DEBUG
   1059       1.125  augustss 	if (uhcinoloop)
   1060       1.125  augustss 		return;
   1061       1.125  augustss #endif
   1062       1.123  augustss 	if (--sc->sc_loops == 0) {
   1063  1.264.4.21     skrll 		DPRINTFN(5, "remove loop", 0, 0, 0, 0);
   1064       1.123  augustss 		sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T);
   1065       1.223    bouyer 		usb_syncmem(&sc->sc_last_qh->dma,
   1066       1.223    bouyer 		    sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink),
   1067       1.223    bouyer 		    sizeof(sc->sc_last_qh->qh.qh_hlink),
   1068       1.223    bouyer 		    BUS_DMASYNC_PREWRITE);
   1069       1.123  augustss 	}
   1070       1.123  augustss }
   1071       1.123  augustss 
   1072       1.248       mrg /* Add high speed control QH, called with lock held. */
   1073       1.123  augustss void
   1074       1.123  augustss uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   1075         1.1  augustss {
   1076        1.42  augustss 	uhci_soft_qh_t *eqh;
   1077         1.1  augustss 
   1078  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1079  1.264.4.21     skrll 
   1080       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   1081       1.248       mrg 
   1082  1.264.4.21     skrll 	DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
   1083       1.123  augustss 	eqh = sc->sc_hctl_end;
   1084       1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1085       1.223    bouyer 	    sizeof(eqh->qh.qh_hlink),
   1086       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE);
   1087        1.42  augustss 	sqh->hlink       = eqh->hlink;
   1088        1.42  augustss 	sqh->qh.qh_hlink = eqh->qh.qh_hlink;
   1089       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
   1090       1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   1091        1.42  augustss 	eqh->hlink       = sqh;
   1092       1.121  augustss 	eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
   1093       1.123  augustss 	sc->sc_hctl_end = sqh;
   1094       1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1095       1.223    bouyer 	    sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
   1096       1.125  augustss #ifdef UHCI_CTL_LOOP
   1097       1.123  augustss 	uhci_add_loop(sc);
   1098       1.125  augustss #endif
   1099         1.1  augustss }
   1100         1.1  augustss 
   1101       1.248       mrg /* Remove high speed control QH, called with lock held. */
   1102         1.1  augustss void
   1103       1.123  augustss uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   1104         1.1  augustss {
   1105         1.1  augustss 	uhci_soft_qh_t *pqh;
   1106       1.256   tsutsui 	uint32_t elink;
   1107         1.1  augustss 
   1108       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   1109       1.248       mrg 
   1110  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1111  1.264.4.21     skrll 	DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
   1112       1.125  augustss #ifdef UHCI_CTL_LOOP
   1113       1.123  augustss 	uhci_rem_loop(sc);
   1114       1.125  augustss #endif
   1115       1.124  augustss 	/*
   1116       1.124  augustss 	 * The T bit should be set in the elink of the QH so that the HC
   1117       1.124  augustss 	 * doesn't follow the pointer.  This condition may fail if the
   1118       1.124  augustss 	 * the transferred packet was short so that the QH still points
   1119       1.124  augustss 	 * at the last used TD.
   1120       1.124  augustss 	 * In this case we set the T bit and wait a little for the HC
   1121       1.124  augustss 	 * to stop looking at the TD.
   1122       1.223    bouyer 	 * Note that if the TD chain is large enough, the controller
   1123       1.223    bouyer 	 * may still be looking at the chain at the end of this function.
   1124       1.223    bouyer 	 * uhci_free_std_chain() will make sure the controller stops
   1125       1.223    bouyer 	 * looking at it quickly, but until then we should not change
   1126       1.223    bouyer 	 * sqh->hlink.
   1127       1.124  augustss 	 */
   1128       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1129       1.223    bouyer 	    sizeof(sqh->qh.qh_elink),
   1130       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1131       1.256   tsutsui 	elink = le32toh(sqh->qh.qh_elink);
   1132       1.256   tsutsui 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1133       1.256   tsutsui 	    sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD);
   1134       1.256   tsutsui 	if (!(elink & UHCI_PTR_T)) {
   1135       1.124  augustss 		sqh->qh.qh_elink = htole32(UHCI_PTR_T);
   1136       1.223    bouyer 		usb_syncmem(&sqh->dma,
   1137       1.223    bouyer 		    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1138       1.223    bouyer 		    sizeof(sqh->qh.qh_elink),
   1139       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   1140       1.124  augustss 		delay(UHCI_QH_REMOVE_DELAY);
   1141       1.124  augustss 	}
   1142       1.124  augustss 
   1143       1.123  augustss 	pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh);
   1144       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1145       1.223    bouyer 	    sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
   1146       1.152  augustss 	pqh->hlink = sqh->hlink;
   1147        1.42  augustss 	pqh->qh.qh_hlink = sqh->qh.qh_hlink;
   1148       1.223    bouyer 	usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1149       1.223    bouyer 	    sizeof(pqh->qh.qh_hlink),
   1150       1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   1151       1.124  augustss 	delay(UHCI_QH_REMOVE_DELAY);
   1152       1.123  augustss 	if (sc->sc_hctl_end == sqh)
   1153       1.123  augustss 		sc->sc_hctl_end = pqh;
   1154       1.123  augustss }
   1155       1.123  augustss 
   1156       1.248       mrg /* Add low speed control QH, called with lock held. */
   1157       1.123  augustss void
   1158       1.123  augustss uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   1159       1.123  augustss {
   1160       1.123  augustss 	uhci_soft_qh_t *eqh;
   1161       1.123  augustss 
   1162       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   1163       1.248       mrg 
   1164  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1165  1.264.4.21     skrll 	DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
   1166  1.264.4.21     skrll 
   1167       1.123  augustss 	eqh = sc->sc_lctl_end;
   1168       1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1169       1.223    bouyer 	    sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
   1170       1.152  augustss 	sqh->hlink = eqh->hlink;
   1171       1.123  augustss 	sqh->qh.qh_hlink = eqh->qh.qh_hlink;
   1172       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
   1173       1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   1174       1.152  augustss 	eqh->hlink = sqh;
   1175       1.123  augustss 	eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
   1176       1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1177       1.223    bouyer 	    sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
   1178       1.123  augustss 	sc->sc_lctl_end = sqh;
   1179       1.123  augustss }
   1180       1.123  augustss 
   1181       1.248       mrg /* Remove low speed control QH, called with lock held. */
   1182       1.123  augustss void
   1183       1.123  augustss uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   1184       1.123  augustss {
   1185       1.123  augustss 	uhci_soft_qh_t *pqh;
   1186       1.256   tsutsui 	uint32_t elink;
   1187       1.123  augustss 
   1188       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   1189       1.248       mrg 
   1190  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1191  1.264.4.21     skrll 	DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
   1192  1.264.4.21     skrll 
   1193       1.124  augustss 	/* See comment in uhci_remove_hs_ctrl() */
   1194       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1195       1.223    bouyer 	    sizeof(sqh->qh.qh_elink),
   1196       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1197       1.256   tsutsui 	elink = le32toh(sqh->qh.qh_elink);
   1198       1.256   tsutsui 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1199       1.256   tsutsui 	    sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD);
   1200       1.256   tsutsui 	if (!(elink & UHCI_PTR_T)) {
   1201       1.124  augustss 		sqh->qh.qh_elink = htole32(UHCI_PTR_T);
   1202       1.223    bouyer 		usb_syncmem(&sqh->dma,
   1203       1.223    bouyer 		    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1204       1.223    bouyer 		    sizeof(sqh->qh.qh_elink),
   1205       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   1206       1.124  augustss 		delay(UHCI_QH_REMOVE_DELAY);
   1207       1.124  augustss 	}
   1208       1.123  augustss 	pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh);
   1209       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1210       1.223    bouyer 	    sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
   1211       1.152  augustss 	pqh->hlink = sqh->hlink;
   1212       1.123  augustss 	pqh->qh.qh_hlink = sqh->qh.qh_hlink;
   1213       1.223    bouyer 	usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1214       1.223    bouyer 	    sizeof(pqh->qh.qh_hlink),
   1215       1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   1216       1.124  augustss 	delay(UHCI_QH_REMOVE_DELAY);
   1217       1.123  augustss 	if (sc->sc_lctl_end == sqh)
   1218       1.123  augustss 		sc->sc_lctl_end = pqh;
   1219         1.1  augustss }
   1220         1.1  augustss 
   1221       1.248       mrg /* Add bulk QH, called with lock held. */
   1222         1.1  augustss void
   1223       1.119  augustss uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   1224         1.1  augustss {
   1225        1.42  augustss 	uhci_soft_qh_t *eqh;
   1226         1.1  augustss 
   1227       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   1228       1.248       mrg 
   1229  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1230  1.264.4.21     skrll 	DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
   1231  1.264.4.21     skrll 
   1232        1.42  augustss 	eqh = sc->sc_bulk_end;
   1233       1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1234       1.223    bouyer 	    sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
   1235       1.152  augustss 	sqh->hlink = eqh->hlink;
   1236        1.42  augustss 	sqh->qh.qh_hlink = eqh->qh.qh_hlink;
   1237       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
   1238       1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   1239       1.152  augustss 	eqh->hlink = sqh;
   1240       1.121  augustss 	eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
   1241       1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1242       1.223    bouyer 	    sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
   1243         1.1  augustss 	sc->sc_bulk_end = sqh;
   1244       1.123  augustss 	uhci_add_loop(sc);
   1245         1.1  augustss }
   1246         1.1  augustss 
   1247       1.248       mrg /* Remove bulk QH, called with lock held. */
   1248         1.1  augustss void
   1249       1.119  augustss uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   1250         1.1  augustss {
   1251         1.1  augustss 	uhci_soft_qh_t *pqh;
   1252         1.1  augustss 
   1253       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   1254       1.248       mrg 
   1255  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1256  1.264.4.21     skrll 	DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
   1257  1.264.4.21     skrll 
   1258       1.123  augustss 	uhci_rem_loop(sc);
   1259       1.124  augustss 	/* See comment in uhci_remove_hs_ctrl() */
   1260       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1261       1.223    bouyer 	    sizeof(sqh->qh.qh_elink),
   1262       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1263       1.124  augustss 	if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) {
   1264       1.124  augustss 		sqh->qh.qh_elink = htole32(UHCI_PTR_T);
   1265       1.223    bouyer 		usb_syncmem(&sqh->dma,
   1266       1.223    bouyer 		    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1267       1.223    bouyer 		    sizeof(sqh->qh.qh_elink),
   1268       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   1269       1.124  augustss 		delay(UHCI_QH_REMOVE_DELAY);
   1270       1.124  augustss 	}
   1271        1.92  augustss 	pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh);
   1272       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1273       1.223    bouyer 	    sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
   1274        1.42  augustss 	pqh->hlink       = sqh->hlink;
   1275        1.42  augustss 	pqh->qh.qh_hlink = sqh->qh.qh_hlink;
   1276       1.223    bouyer 	usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1277       1.223    bouyer 	    sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
   1278       1.124  augustss 	delay(UHCI_QH_REMOVE_DELAY);
   1279         1.1  augustss 	if (sc->sc_bulk_end == sqh)
   1280         1.1  augustss 		sc->sc_bulk_end = pqh;
   1281         1.1  augustss }
   1282         1.1  augustss 
   1283       1.141  augustss Static int uhci_intr1(uhci_softc_t *);
   1284       1.141  augustss 
   1285         1.1  augustss int
   1286       1.119  augustss uhci_intr(void *arg)
   1287         1.1  augustss {
   1288        1.44  augustss 	uhci_softc_t *sc = arg;
   1289       1.248       mrg 	int ret = 0;
   1290       1.248       mrg 
   1291  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1292  1.264.4.21     skrll 
   1293       1.248       mrg 	mutex_spin_enter(&sc->sc_intr_lock);
   1294       1.146  augustss 
   1295       1.216  drochner 	if (sc->sc_dying || !device_has_power(sc->sc_dev))
   1296       1.248       mrg 		goto done;
   1297       1.141  augustss 
   1298   1.264.4.7     skrll 	if (sc->sc_bus.ub_usepolling || UREAD2(sc, UHCI_INTR) == 0) {
   1299  1.264.4.21     skrll 		DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0);
   1300       1.248       mrg 		goto done;
   1301       1.141  augustss 	}
   1302       1.179   mycroft 
   1303       1.248       mrg 	ret = uhci_intr1(sc);
   1304       1.248       mrg 
   1305       1.248       mrg  done:
   1306       1.248       mrg 	mutex_spin_exit(&sc->sc_intr_lock);
   1307       1.248       mrg 	return ret;
   1308       1.141  augustss }
   1309       1.141  augustss 
   1310       1.141  augustss int
   1311       1.141  augustss uhci_intr1(uhci_softc_t *sc)
   1312       1.141  augustss {
   1313        1.44  augustss 	int status;
   1314        1.44  augustss 	int ack;
   1315         1.1  augustss 
   1316  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1317  1.264.4.21     skrll 
   1318        1.67  augustss #ifdef UHCI_DEBUG
   1319  1.264.4.46     skrll 	if (uhcidebug >= 15) {
   1320  1.264.4.27     skrll 		DPRINTF("sc %p", sc, 0, 0, 0);
   1321         1.1  augustss 		uhci_dumpregs(sc);
   1322         1.1  augustss 	}
   1323         1.1  augustss #endif
   1324       1.117  augustss 
   1325       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_intr_lock));
   1326       1.248       mrg 
   1327       1.153  augustss 	status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS;
   1328  1.264.4.59     skrll 	/* Check if the interrupt was for us. */
   1329  1.264.4.59     skrll 	if (status == 0)
   1330  1.264.4.13     skrll 		return 0;
   1331       1.127     soren 
   1332       1.117  augustss 	if (sc->sc_suspend != PWR_RESUME) {
   1333       1.201  jmcneill #ifdef DIAGNOSTIC
   1334       1.117  augustss 		printf("%s: interrupt while not operating ignored\n",
   1335       1.216  drochner 		       device_xname(sc->sc_dev));
   1336       1.201  jmcneill #endif
   1337       1.134  augustss 		UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */
   1338  1.264.4.13     skrll 		return 0;
   1339       1.117  augustss 	}
   1340        1.44  augustss 
   1341        1.44  augustss 	ack = 0;
   1342        1.44  augustss 	if (status & UHCI_STS_USBINT)
   1343        1.44  augustss 		ack |= UHCI_STS_USBINT;
   1344        1.44  augustss 	if (status & UHCI_STS_USBEI)
   1345        1.44  augustss 		ack |= UHCI_STS_USBEI;
   1346         1.1  augustss 	if (status & UHCI_STS_RD) {
   1347        1.44  augustss 		ack |= UHCI_STS_RD;
   1348       1.118  augustss #ifdef UHCI_DEBUG
   1349       1.216  drochner 		printf("%s: resume detect\n", device_xname(sc->sc_dev));
   1350       1.118  augustss #endif
   1351         1.1  augustss 	}
   1352         1.1  augustss 	if (status & UHCI_STS_HSE) {
   1353        1.44  augustss 		ack |= UHCI_STS_HSE;
   1354       1.216  drochner 		printf("%s: host system error\n", device_xname(sc->sc_dev));
   1355         1.1  augustss 	}
   1356         1.1  augustss 	if (status & UHCI_STS_HCPE) {
   1357        1.44  augustss 		ack |= UHCI_STS_HCPE;
   1358       1.152  augustss 		printf("%s: host controller process error\n",
   1359       1.216  drochner 		       device_xname(sc->sc_dev));
   1360        1.44  augustss 	}
   1361       1.233   msaitoh 
   1362       1.233   msaitoh 	/* When HCHalted=1 and Run/Stop=0 , it is normal */
   1363       1.233   msaitoh 	if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) {
   1364        1.44  augustss 		/* no acknowledge needed */
   1365       1.136  augustss 		if (!sc->sc_dying) {
   1366       1.152  augustss 			printf("%s: host controller halted\n",
   1367       1.216  drochner 			    device_xname(sc->sc_dev));
   1368       1.110  augustss #ifdef UHCI_DEBUG
   1369       1.136  augustss 			uhci_dump_all(sc);
   1370       1.110  augustss #endif
   1371       1.136  augustss 		}
   1372       1.136  augustss 		sc->sc_dying = 1;
   1373         1.1  augustss 	}
   1374        1.44  augustss 
   1375       1.132  augustss 	if (!ack)
   1376  1.264.4.13     skrll 		return 0;	/* nothing to acknowledge */
   1377       1.132  augustss 	UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */
   1378         1.1  augustss 
   1379        1.85  augustss 	usb_schedsoftintr(&sc->sc_bus);
   1380        1.85  augustss 
   1381  1.264.4.21     skrll 	DPRINTFN(15, "sc %p done", sc, 0, 0, 0);
   1382        1.85  augustss 
   1383  1.264.4.13     skrll 	return 1;
   1384        1.85  augustss }
   1385        1.85  augustss 
   1386        1.85  augustss void
   1387       1.133  augustss uhci_softintr(void *v)
   1388        1.85  augustss {
   1389       1.216  drochner 	struct usbd_bus *bus = v;
   1390  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_BUS2SC(bus);
   1391  1.264.4.39     skrll 	struct uhci_xfer *ux, *nextux;
   1392  1.264.4.61     skrll 	ux_completeq_t cq;
   1393        1.85  augustss 
   1394  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1395  1.264.4.27     skrll 	DPRINTF("sc %p", sc, 0, 0, 0);
   1396       1.248       mrg 
   1397  1.264.4.21     skrll 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
   1398        1.50  augustss 
   1399  1.264.4.61     skrll 	TAILQ_INIT(&cq);
   1400         1.1  augustss 	/*
   1401         1.1  augustss 	 * Interrupts on UHCI really suck.  When the host controller
   1402         1.1  augustss 	 * interrupts because a transfer is completed there is no
   1403         1.1  augustss 	 * way of knowing which transfer it was.  You can scan down
   1404         1.1  augustss 	 * the TDs and QHs of the previous frame to limit the search,
   1405         1.1  augustss 	 * but that assumes that the interrupt was not delayed by more
   1406         1.1  augustss 	 * than 1 ms, which may not always be true (e.g. after debug
   1407         1.1  augustss 	 * output on a slow console).
   1408         1.1  augustss 	 * We scan all interrupt descriptors to see if any have
   1409         1.1  augustss 	 * completed.
   1410         1.1  augustss 	 */
   1411  1.264.4.61     skrll 	TAILQ_FOREACH_SAFE(ux, &sc->sc_intrhead, ux_list, nextux) {
   1412  1.264.4.61     skrll 		uhci_check_intr(sc, ux, &cq);
   1413  1.264.4.61     skrll 	}
   1414  1.264.4.61     skrll 
   1415  1.264.4.61     skrll 	/*
   1416  1.264.4.61     skrll 	 * We abuse ux_list for the interrupt and complete lists and
   1417  1.264.4.61     skrll 	 * interrupt transfers will get re-added here so use
   1418  1.264.4.61     skrll 	 * the _SAFE version of TAILQ_FOREACH.
   1419  1.264.4.61     skrll 	 */
   1420  1.264.4.61     skrll 	TAILQ_FOREACH_SAFE(ux, &cq, ux_list, nextux) {
   1421  1.264.4.61     skrll 		DPRINTF("ux %p", ux, 0, 0, 0);
   1422  1.264.4.61     skrll 		usb_transfer_complete(&ux->ux_xfer);
   1423       1.178    martin 	}
   1424         1.1  augustss 
   1425       1.153  augustss 	if (sc->sc_softwake) {
   1426       1.153  augustss 		sc->sc_softwake = 0;
   1427       1.248       mrg 		cv_broadcast(&sc->sc_softwake_cv);
   1428       1.153  augustss 	}
   1429         1.1  augustss }
   1430         1.1  augustss 
   1431         1.1  augustss /* Check for an interrupt. */
   1432         1.1  augustss void
   1433  1.264.4.61     skrll uhci_check_intr(uhci_softc_t *sc, struct uhci_xfer *ux, ux_completeq_t *cqp)
   1434         1.1  augustss {
   1435  1.264.4.55     skrll 	uhci_soft_td_t *std, *fstd = NULL, *lstd = NULL;
   1436   1.264.4.1     skrll 	uint32_t status;
   1437         1.1  augustss 
   1438  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1439  1.264.4.39     skrll 	DPRINTFN(15, "ux %p", ux, 0, 0, 0);
   1440  1.264.4.31     skrll 
   1441  1.264.4.39     skrll 	KASSERT(ux != NULL);
   1442  1.264.4.31     skrll 
   1443  1.264.4.41     skrll 	struct usbd_xfer *xfer = &ux->ux_xfer;
   1444  1.264.4.39     skrll 	if (xfer->ux_status == USBD_CANCELLED ||
   1445  1.264.4.39     skrll 	    xfer->ux_status == USBD_TIMEOUT) {
   1446  1.264.4.39     skrll 		DPRINTF("aborted xfer %p", xfer, 0, 0, 0);
   1447       1.155  augustss 		return;
   1448       1.155  augustss 	}
   1449       1.155  augustss 
   1450  1.264.4.55     skrll 	switch (ux->ux_type) {
   1451  1.264.4.55     skrll 	case UX_CTRL:
   1452  1.264.4.55     skrll 		fstd = ux->ux_setup;
   1453  1.264.4.55     skrll 		lstd = ux->ux_stat;
   1454  1.264.4.55     skrll 		break;
   1455  1.264.4.55     skrll 	case UX_BULK:
   1456  1.264.4.55     skrll 	case UX_INTR:
   1457  1.264.4.55     skrll 	case UX_ISOC:
   1458  1.264.4.55     skrll 		fstd = ux->ux_stdstart;
   1459  1.264.4.55     skrll 		lstd = ux->ux_stdend;
   1460  1.264.4.55     skrll 		break;
   1461  1.264.4.55     skrll 	default:
   1462  1.264.4.55     skrll 		KASSERT(false);
   1463  1.264.4.55     skrll 		break;
   1464  1.264.4.55     skrll 	}
   1465  1.264.4.55     skrll 	if (fstd == NULL)
   1466         1.1  augustss 		return;
   1467  1.264.4.31     skrll 
   1468  1.264.4.31     skrll 	KASSERT(lstd != NULL);
   1469  1.264.4.31     skrll 
   1470       1.223    bouyer 	usb_syncmem(&lstd->dma,
   1471       1.223    bouyer 	    lstd->offs + offsetof(uhci_td_t, td_status),
   1472       1.223    bouyer 	    sizeof(lstd->td.td_status),
   1473       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1474       1.256   tsutsui 	status = le32toh(lstd->td.td_status);
   1475       1.256   tsutsui 	usb_syncmem(&lstd->dma,
   1476       1.256   tsutsui 	    lstd->offs + offsetof(uhci_td_t, td_status),
   1477       1.256   tsutsui 	    sizeof(lstd->td.td_status),
   1478       1.256   tsutsui 	    BUS_DMASYNC_PREREAD);
   1479       1.258     skrll 
   1480       1.258     skrll 	/* If the last TD is not marked active we can complete */
   1481       1.258     skrll 	if (!(status & UHCI_TD_ACTIVE)) {
   1482       1.258     skrll  done:
   1483  1.264.4.39     skrll 		DPRINTFN(12, "ux=%p done", ux, 0, 0, 0);
   1484  1.264.4.21     skrll 
   1485  1.264.4.39     skrll 		callout_stop(&xfer->ux_callout);
   1486  1.264.4.61     skrll 		uhci_idone(ux, cqp);
   1487       1.258     skrll 		return;
   1488       1.258     skrll 	}
   1489       1.258     skrll 
   1490       1.258     skrll 	/*
   1491       1.258     skrll 	 * If the last TD is still active we need to check whether there
   1492       1.258     skrll 	 * is an error somewhere in the middle, or whether there was a
   1493       1.258     skrll 	 * short packet (SPD and not ACTIVE).
   1494       1.258     skrll 	 */
   1495  1.264.4.39     skrll 	DPRINTFN(12, "active ux=%p", ux, 0, 0, 0);
   1496  1.264.4.55     skrll 	for (std = fstd; std != lstd; std = std->link.std) {
   1497       1.258     skrll 		usb_syncmem(&std->dma,
   1498       1.258     skrll 		    std->offs + offsetof(uhci_td_t, td_status),
   1499       1.258     skrll 		    sizeof(std->td.td_status),
   1500       1.258     skrll 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1501       1.258     skrll 		status = le32toh(std->td.td_status);
   1502       1.258     skrll 		usb_syncmem(&std->dma,
   1503       1.258     skrll 		    std->offs + offsetof(uhci_td_t, td_status),
   1504       1.258     skrll 		    sizeof(std->td.td_status), BUS_DMASYNC_PREREAD);
   1505       1.258     skrll 
   1506       1.258     skrll 		/* If there's an active TD the xfer isn't done. */
   1507       1.258     skrll 		if (status & UHCI_TD_ACTIVE) {
   1508  1.264.4.39     skrll 			DPRINTFN(12, "ux=%p std=%p still active",
   1509  1.264.4.39     skrll 			    ux, std, 0, 0);
   1510       1.258     skrll 			return;
   1511       1.258     skrll 		}
   1512       1.258     skrll 
   1513       1.258     skrll 		/* Any kind of error makes the xfer done. */
   1514       1.258     skrll 		if (status & UHCI_TD_STALLED)
   1515       1.258     skrll 			goto done;
   1516       1.258     skrll 
   1517       1.258     skrll 		/*
   1518       1.258     skrll 		 * If the data phase of a control transfer is short, we need
   1519       1.258     skrll 		 * to complete the status stage
   1520       1.258     skrll 		 */
   1521       1.258     skrll 
   1522  1.264.4.55     skrll 		if ((status & UHCI_TD_SPD) && ux->ux_type == UX_CTRL) {
   1523       1.258     skrll 			struct uhci_pipe *upipe =
   1524  1.264.4.50     skrll 			    UHCI_PIPE2UPIPE(xfer->ux_pipe);
   1525  1.264.4.33     skrll 			uhci_soft_qh_t *sqh = upipe->ctrl.sqh;
   1526  1.264.4.33     skrll 			uhci_soft_td_t *stat = upipe->ctrl.stat;
   1527       1.258     skrll 
   1528  1.264.4.39     skrll 			DPRINTFN(12, "ux=%p std=%p control status"
   1529  1.264.4.41     skrll 			    "phase needs completion", ux, ux->ux_stdstart, 0, 0);
   1530       1.258     skrll 
   1531       1.258     skrll 			sqh->qh.qh_elink =
   1532       1.258     skrll 			    htole32(stat->physaddr | UHCI_PTR_TD);
   1533       1.258     skrll 			usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
   1534       1.258     skrll 			    BUS_DMASYNC_PREWRITE);
   1535       1.258     skrll 			break;
   1536       1.258     skrll 		}
   1537       1.258     skrll 
   1538       1.258     skrll 		/* We want short packets, and it is short: it's done */
   1539       1.258     skrll 		usb_syncmem(&std->dma,
   1540       1.258     skrll 		    std->offs + offsetof(uhci_td_t, td_token),
   1541       1.258     skrll 		    sizeof(std->td.td_token),
   1542       1.258     skrll 		    BUS_DMASYNC_POSTWRITE);
   1543       1.258     skrll 
   1544       1.258     skrll 		if ((status & UHCI_TD_SPD) &&
   1545       1.258     skrll 			UHCI_TD_GET_ACTLEN(status) <
   1546       1.258     skrll 			UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) {
   1547       1.258     skrll 			goto done;
   1548        1.18  augustss 		}
   1549         1.1  augustss 	}
   1550         1.1  augustss }
   1551         1.1  augustss 
   1552       1.248       mrg /* Called with USB lock held. */
   1553         1.1  augustss void
   1554  1.264.4.61     skrll uhci_idone(struct uhci_xfer *ux, ux_completeq_t *cqp)
   1555         1.1  augustss {
   1556  1.264.4.41     skrll 	struct usbd_xfer *xfer = &ux->ux_xfer;
   1557  1.264.4.37     skrll 	uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer);
   1558  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   1559         1.1  augustss 	uhci_soft_td_t *std;
   1560   1.264.4.1     skrll 	uint32_t status = 0, nstatus;
   1561        1.26  augustss 	int actlen;
   1562         1.1  augustss 
   1563   1.264.4.7     skrll 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
   1564       1.248       mrg 
   1565  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1566  1.264.4.39     skrll 	DPRINTFN(12, "ux=%p", ux, 0, 0, 0);
   1567  1.264.4.21     skrll 
   1568         1.7  augustss #ifdef DIAGNOSTIC
   1569        1.92  augustss #ifdef UHCI_DEBUG
   1570  1.264.4.41     skrll 	if (ux->ux_isdone) {
   1571  1.264.4.31     skrll 		DPRINTF("--- dump start ---", 0, 0, 0, 0);
   1572  1.264.4.39     skrll 		uhci_dump_ii(ux);
   1573  1.264.4.31     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   1574         1.7  augustss 	}
   1575         1.7  augustss #endif
   1576  1.264.4.41     skrll 	KASSERT(!ux->ux_isdone);
   1577  1.264.4.66     skrll 	KASSERTMSG(!ux->ux_isdone, "xfer %p type %d status %d", xfer,
   1578  1.264.4.66     skrll 	    ux->ux_type, xfer->ux_status);
   1579  1.264.4.41     skrll 	ux->ux_isdone = true;
   1580  1.264.4.31     skrll #endif
   1581        1.48  augustss 
   1582   1.264.4.7     skrll 	if (xfer->ux_nframes != 0) {
   1583        1.48  augustss 		/* Isoc transfer, do things differently. */
   1584  1.264.4.33     skrll 		uhci_soft_td_t **stds = upipe->isoc.stds;
   1585       1.126  augustss 		int i, n, nframes, len;
   1586        1.48  augustss 
   1587  1.264.4.39     skrll 		DPRINTFN(5, "ux=%p isoc ready", ux, 0, 0, 0);
   1588        1.48  augustss 
   1589   1.264.4.7     skrll 		nframes = xfer->ux_nframes;
   1590        1.48  augustss 		actlen = 0;
   1591  1.264.4.61     skrll 		n = ux->ux_curframe;
   1592        1.48  augustss 		for (i = 0; i < nframes; i++) {
   1593        1.48  augustss 			std = stds[n];
   1594        1.59  augustss #ifdef UHCI_DEBUG
   1595  1.264.4.43     skrll 			if (uhcidebug >= 5) {
   1596  1.264.4.27     skrll 				DPRINTF("isoc TD %d", i, 0, 0, 0);
   1597  1.264.4.53     skrll 				DPRINTF("--- dump start ---", 0, 0, 0, 0);
   1598        1.48  augustss 				uhci_dump_td(std);
   1599  1.264.4.53     skrll 				DPRINTF("--- dump end ---", 0, 0, 0, 0);
   1600        1.48  augustss 			}
   1601        1.48  augustss #endif
   1602        1.48  augustss 			if (++n >= UHCI_VFRAMELIST_COUNT)
   1603        1.48  augustss 				n = 0;
   1604       1.223    bouyer 			usb_syncmem(&std->dma,
   1605       1.223    bouyer 			    std->offs + offsetof(uhci_td_t, td_status),
   1606       1.223    bouyer 			    sizeof(std->td.td_status),
   1607       1.223    bouyer 			    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1608        1.88   tsutsui 			status = le32toh(std->td.td_status);
   1609       1.126  augustss 			len = UHCI_TD_GET_ACTLEN(status);
   1610   1.264.4.7     skrll 			xfer->ux_frlengths[i] = len;
   1611       1.126  augustss 			actlen += len;
   1612        1.48  augustss 		}
   1613  1.264.4.33     skrll 		upipe->isoc.inuse -= nframes;
   1614   1.264.4.7     skrll 		xfer->ux_actlen = actlen;
   1615   1.264.4.7     skrll 		xfer->ux_status = USBD_NORMAL_COMPLETION;
   1616       1.140  augustss 		goto end;
   1617        1.48  augustss 	}
   1618        1.48  augustss 
   1619        1.59  augustss #ifdef UHCI_DEBUG
   1620  1.264.4.47     skrll 	DPRINTFN(10, "ux=%p, xfer=%p, pipe=%p ready", ux, xfer, upipe, 0);
   1621  1.264.4.47     skrll 	if (uhcidebug >= 10) {
   1622  1.264.4.47     skrll 		DPRINTF("--- dump start ---", 0, 0, 0, 0);
   1623  1.264.4.41     skrll 		uhci_dump_tds(ux->ux_stdstart);
   1624  1.264.4.47     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   1625  1.264.4.47     skrll 	}
   1626        1.48  augustss #endif
   1627        1.48  augustss 
   1628        1.26  augustss 	/* The transfer is done, compute actual length and status. */
   1629        1.26  augustss 	actlen = 0;
   1630  1.264.4.41     skrll 	for (std = ux->ux_stdstart; std != NULL; std = std->link.std) {
   1631       1.223    bouyer 		usb_syncmem(&std->dma, std->offs, sizeof(std->td),
   1632       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1633        1.88   tsutsui 		nstatus = le32toh(std->td.td_status);
   1634        1.64  augustss 		if (nstatus & UHCI_TD_ACTIVE)
   1635        1.26  augustss 			break;
   1636        1.67  augustss 
   1637        1.64  augustss 		status = nstatus;
   1638        1.88   tsutsui 		if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) !=
   1639        1.88   tsutsui 			UHCI_TD_PID_SETUP)
   1640        1.26  augustss 			actlen += UHCI_TD_GET_ACTLEN(status);
   1641       1.176   mycroft 		else {
   1642       1.176   mycroft 			/*
   1643       1.176   mycroft 			 * UHCI will report CRCTO in addition to a STALL or NAK
   1644       1.176   mycroft 			 * for a SETUP transaction.  See section 3.2.2, "TD
   1645       1.176   mycroft 			 * CONTROL AND STATUS".
   1646       1.176   mycroft 			 */
   1647       1.176   mycroft 			if (status & (UHCI_TD_STALLED | UHCI_TD_NAK))
   1648       1.176   mycroft 				status &= ~UHCI_TD_CRCTO;
   1649       1.176   mycroft 		}
   1650         1.1  augustss 	}
   1651        1.38  augustss 	/* If there are left over TDs we need to update the toggle. */
   1652        1.63  augustss 	if (std != NULL)
   1653        1.88   tsutsui 		upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token));
   1654        1.38  augustss 
   1655         1.1  augustss 	status &= UHCI_TD_ERROR;
   1656  1.264.4.29     skrll 	DPRINTFN(10, "actlen=%d, status=0x%x", actlen, status, 0, 0);
   1657   1.264.4.7     skrll 	xfer->ux_actlen = actlen;
   1658         1.1  augustss 	if (status != 0) {
   1659       1.122        tv 
   1660  1.264.4.21     skrll 		DPRINTFN((status == UHCI_TD_STALLED) * 10,
   1661  1.264.4.21     skrll 		    "error, addr=%d, endpt=0x%02x",
   1662  1.264.4.21     skrll 		    xfer->ux_pipe->up_dev->ud_addr,
   1663  1.264.4.21     skrll 		    xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress,
   1664  1.264.4.21     skrll 		    0, 0);
   1665  1.264.4.21     skrll 		DPRINTFN((status == UHCI_TD_STALLED) * 10,
   1666  1.264.4.21     skrll 		    "bitstuff=%d crcto   =%d nak     =%d babble  =%d",
   1667  1.264.4.45     skrll 		    !!(status & UHCI_TD_BITSTUFF),
   1668  1.264.4.45     skrll 		    !!(status & UHCI_TD_CRCTO),
   1669  1.264.4.45     skrll 		    !!(status & UHCI_TD_NAK),
   1670  1.264.4.45     skrll 		    !!(status & UHCI_TD_BABBLE));
   1671  1.264.4.21     skrll 		DPRINTFN((status == UHCI_TD_STALLED) * 10,
   1672  1.264.4.21     skrll 		    "dbuffer =%d stalled =%d active  =%d",
   1673  1.264.4.45     skrll 		    !!(status & UHCI_TD_DBUFFER),
   1674  1.264.4.45     skrll 		    !!(status & UHCI_TD_STALLED),
   1675  1.264.4.45     skrll 		    !!(status & UHCI_TD_ACTIVE),
   1676  1.264.4.21     skrll 		    0);
   1677       1.122        tv 
   1678         1.1  augustss 		if (status == UHCI_TD_STALLED)
   1679   1.264.4.7     skrll 			xfer->ux_status = USBD_STALLED;
   1680         1.1  augustss 		else
   1681   1.264.4.7     skrll 			xfer->ux_status = USBD_IOERROR; /* more info XXX */
   1682         1.1  augustss 	} else {
   1683   1.264.4.7     skrll 		xfer->ux_status = USBD_NORMAL_COMPLETION;
   1684         1.1  augustss 	}
   1685       1.140  augustss 
   1686       1.140  augustss  end:
   1687  1.264.4.61     skrll 	uhci_del_intr_list(sc, ux);
   1688  1.264.4.61     skrll 	if (cqp)
   1689  1.264.4.61     skrll 		TAILQ_INSERT_TAIL(cqp, ux, ux_list);
   1690  1.264.4.61     skrll 
   1691   1.264.4.7     skrll 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
   1692  1.264.4.39     skrll 	DPRINTFN(12, "ux=%p done", ux, 0, 0, 0);
   1693         1.1  augustss }
   1694         1.1  augustss 
   1695        1.13  augustss /*
   1696        1.13  augustss  * Called when a request does not complete.
   1697        1.13  augustss  */
   1698         1.1  augustss void
   1699       1.119  augustss uhci_timeout(void *addr)
   1700         1.1  augustss {
   1701  1.264.4.39     skrll 	struct usbd_xfer *xfer = addr;
   1702  1.264.4.39     skrll 	struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
   1703  1.264.4.39     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   1704       1.153  augustss 
   1705  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1706  1.264.4.21     skrll 
   1707  1.264.4.27     skrll 	DPRINTF("uxfer %p", uxfer, 0, 0, 0);
   1708       1.153  augustss 
   1709       1.153  augustss 	if (sc->sc_dying) {
   1710       1.248       mrg 		mutex_enter(&sc->sc_lock);
   1711  1.264.4.39     skrll 		uhci_abort_xfer(xfer, USBD_TIMEOUT);
   1712       1.248       mrg 		mutex_exit(&sc->sc_lock);
   1713       1.153  augustss 		return;
   1714       1.153  augustss 	}
   1715         1.1  augustss 
   1716       1.153  augustss 	/* Execute the abort in a process context. */
   1717  1.264.4.41     skrll 	usb_init_task(&uxfer->ux_aborttask, uhci_timeout_task, xfer,
   1718       1.252  jmcneill 	    USB_TASKQ_MPSAFE);
   1719  1.264.4.41     skrll 	usb_add_task(uxfer->ux_xfer.ux_pipe->up_dev, &uxfer->ux_aborttask,
   1720       1.204     joerg 	    USB_TASKQ_HC);
   1721       1.153  augustss }
   1722        1.51  augustss 
   1723       1.153  augustss void
   1724       1.153  augustss uhci_timeout_task(void *addr)
   1725       1.153  augustss {
   1726  1.264.4.25     skrll 	struct usbd_xfer *xfer = addr;
   1727  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   1728       1.153  augustss 
   1729  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1730  1.264.4.21     skrll 
   1731  1.264.4.27     skrll 	DPRINTF("xfer=%p", xfer, 0, 0, 0);
   1732        1.67  augustss 
   1733       1.248       mrg 	mutex_enter(&sc->sc_lock);
   1734       1.153  augustss 	uhci_abort_xfer(xfer, USBD_TIMEOUT);
   1735       1.248       mrg 	mutex_exit(&sc->sc_lock);
   1736         1.1  augustss }
   1737         1.1  augustss 
   1738         1.1  augustss /*
   1739         1.1  augustss  * Wait here until controller claims to have an interrupt.
   1740         1.1  augustss  * Then call uhci_intr and return.  Use timeout to avoid waiting
   1741         1.1  augustss  * too long.
   1742        1.13  augustss  * Only used during boot when interrupts are not enabled yet.
   1743         1.1  augustss  */
   1744         1.1  augustss void
   1745  1.264.4.25     skrll uhci_waitintr(uhci_softc_t *sc, struct usbd_xfer *xfer)
   1746         1.1  augustss {
   1747   1.264.4.7     skrll 	int timo = xfer->ux_timeout;
   1748  1.264.4.39     skrll 	struct uhci_xfer *ux;
   1749        1.13  augustss 
   1750       1.248       mrg 	mutex_enter(&sc->sc_lock);
   1751       1.248       mrg 
   1752  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1753  1.264.4.21     skrll 	DPRINTFN(10, "timeout = %dms", timo, 0, 0, 0);
   1754         1.1  augustss 
   1755   1.264.4.7     skrll 	xfer->ux_status = USBD_IN_PROGRESS;
   1756        1.26  augustss 	for (; timo >= 0; timo--) {
   1757       1.248       mrg 		usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_lock);
   1758  1.264.4.21     skrll 		DPRINTFN(20, "0x%04x",
   1759  1.264.4.21     skrll 		    UREAD2(sc, UHCI_STS), 0, 0, 0);
   1760         1.1  augustss 		if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) {
   1761       1.248       mrg 			mutex_spin_enter(&sc->sc_intr_lock);
   1762       1.141  augustss 			uhci_intr1(sc);
   1763       1.248       mrg 			mutex_spin_exit(&sc->sc_intr_lock);
   1764   1.264.4.7     skrll 			if (xfer->ux_status != USBD_IN_PROGRESS)
   1765       1.248       mrg 				goto done;
   1766         1.1  augustss 		}
   1767         1.1  augustss 	}
   1768        1.13  augustss 
   1769        1.13  augustss 	/* Timeout */
   1770  1.264.4.27     skrll 	DPRINTF("timeout", 0, 0, 0, 0);
   1771  1.264.4.60     skrll 	TAILQ_FOREACH(ux, &sc->sc_intrhead, ux_list)
   1772  1.264.4.41     skrll 		if (&ux->ux_xfer == xfer)
   1773  1.264.4.39     skrll 			break;
   1774  1.264.4.31     skrll 
   1775  1.264.4.39     skrll 	KASSERT(ux != NULL);
   1776  1.264.4.31     skrll 
   1777  1.264.4.61     skrll 	uhci_idone(ux, NULL);
   1778  1.264.4.61     skrll 	usb_transfer_complete(&ux->ux_xfer);
   1779       1.248       mrg 
   1780       1.248       mrg done:
   1781       1.248       mrg 	mutex_exit(&sc->sc_lock);
   1782         1.1  augustss }
   1783         1.1  augustss 
   1784         1.8  augustss void
   1785       1.119  augustss uhci_poll(struct usbd_bus *bus)
   1786         1.8  augustss {
   1787  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_BUS2SC(bus);
   1788         1.8  augustss 
   1789       1.248       mrg 	if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) {
   1790       1.248       mrg 		mutex_spin_enter(&sc->sc_intr_lock);
   1791       1.141  augustss 		uhci_intr1(sc);
   1792       1.248       mrg 		mutex_spin_exit(&sc->sc_intr_lock);
   1793       1.248       mrg 	}
   1794         1.8  augustss }
   1795         1.8  augustss 
   1796         1.1  augustss void
   1797       1.119  augustss uhci_reset(uhci_softc_t *sc)
   1798         1.1  augustss {
   1799         1.1  augustss 	int n;
   1800         1.1  augustss 
   1801         1.1  augustss 	UHCICMD(sc, UHCI_CMD_HCRESET);
   1802         1.1  augustss 	/* The reset bit goes low when the controller is done. */
   1803       1.152  augustss 	for (n = 0; n < UHCI_RESET_TIMEOUT &&
   1804         1.1  augustss 		    (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++)
   1805        1.92  augustss 		usb_delay_ms(&sc->sc_bus, 1);
   1806         1.1  augustss 	if (n >= UHCI_RESET_TIMEOUT)
   1807       1.152  augustss 		printf("%s: controller did not reset\n",
   1808       1.216  drochner 		       device_xname(sc->sc_dev));
   1809         1.1  augustss }
   1810         1.1  augustss 
   1811        1.16  augustss usbd_status
   1812       1.249  drochner uhci_run(uhci_softc_t *sc, int run, int locked)
   1813         1.1  augustss {
   1814       1.248       mrg 	int n, running;
   1815   1.264.4.1     skrll 	uint16_t cmd;
   1816         1.1  augustss 
   1817  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1818  1.264.4.21     skrll 
   1819         1.1  augustss 	run = run != 0;
   1820       1.249  drochner 	if (!locked)
   1821       1.249  drochner 		mutex_spin_enter(&sc->sc_intr_lock);
   1822  1.264.4.21     skrll 
   1823  1.264.4.27     skrll 	DPRINTF("setting run=%d", run, 0, 0, 0);
   1824        1.71  augustss 	cmd = UREAD2(sc, UHCI_CMD);
   1825        1.71  augustss 	if (run)
   1826        1.71  augustss 		cmd |= UHCI_CMD_RS;
   1827        1.71  augustss 	else
   1828        1.71  augustss 		cmd &= ~UHCI_CMD_RS;
   1829        1.71  augustss 	UHCICMD(sc, cmd);
   1830  1.264.4.54     skrll 	for (n = 0; n < 10; n++) {
   1831         1.1  augustss 		running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH);
   1832         1.1  augustss 		/* return when we've entered the state we want */
   1833         1.1  augustss 		if (run == running) {
   1834       1.249  drochner 			if (!locked)
   1835       1.249  drochner 				mutex_spin_exit(&sc->sc_intr_lock);
   1836  1.264.4.27     skrll 			DPRINTF("done cmd=0x%x sts=0x%x",
   1837  1.264.4.21     skrll 			    UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 0, 0);
   1838  1.264.4.13     skrll 			return USBD_NORMAL_COMPLETION;
   1839         1.1  augustss 		}
   1840       1.248       mrg 		usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock);
   1841         1.1  augustss 	}
   1842       1.249  drochner 	if (!locked)
   1843       1.249  drochner 		mutex_spin_exit(&sc->sc_intr_lock);
   1844       1.216  drochner 	printf("%s: cannot %s\n", device_xname(sc->sc_dev),
   1845        1.14  augustss 	       run ? "start" : "stop");
   1846  1.264.4.13     skrll 	return USBD_IOERROR;
   1847         1.1  augustss }
   1848         1.1  augustss 
   1849         1.1  augustss /*
   1850         1.1  augustss  * Memory management routines.
   1851         1.1  augustss  *  uhci_alloc_std allocates TDs
   1852         1.1  augustss  *  uhci_alloc_sqh allocates QHs
   1853         1.7  augustss  * These two routines do their own free list management,
   1854         1.1  augustss  * partly for speed, partly because allocating DMAable memory
   1855  1.264.4.28     skrll  * has page size granularity so much memory would be wasted if
   1856        1.16  augustss  * only one TD/QH (32 bytes) was placed in each allocated chunk.
   1857         1.1  augustss  */
   1858         1.1  augustss 
   1859         1.1  augustss uhci_soft_td_t *
   1860       1.119  augustss uhci_alloc_std(uhci_softc_t *sc)
   1861         1.1  augustss {
   1862         1.1  augustss 	uhci_soft_td_t *std;
   1863        1.63  augustss 	usbd_status err;
   1864        1.42  augustss 	int i, offs;
   1865         1.7  augustss 	usb_dma_t dma;
   1866         1.1  augustss 
   1867  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1868  1.264.4.21     skrll 
   1869  1.264.4.55     skrll 	mutex_enter(&sc->sc_lock);
   1870        1.63  augustss 	if (sc->sc_freetds == NULL) {
   1871  1.264.4.21     skrll 		DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
   1872  1.264.4.55     skrll 		mutex_exit(&sc->sc_lock);
   1873  1.264.4.55     skrll 
   1874        1.63  augustss 		err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK,
   1875        1.63  augustss 			  UHCI_TD_ALIGN, &dma);
   1876        1.63  augustss 		if (err)
   1877  1.264.4.52     skrll 			return NULL;
   1878  1.264.4.55     skrll 
   1879  1.264.4.55     skrll 		mutex_enter(&sc->sc_lock);
   1880       1.248       mrg 		for (i = 0; i < UHCI_STD_CHUNK; i++) {
   1881        1.42  augustss 			offs = i * UHCI_STD_SIZE;
   1882       1.159  augustss 			std = KERNADDR(&dma, offs);
   1883       1.160  augustss 			std->physaddr = DMAADDR(&dma, offs);
   1884       1.223    bouyer 			std->dma = dma;
   1885       1.223    bouyer 			std->offs = offs;
   1886        1.42  augustss 			std->link.std = sc->sc_freetds;
   1887         1.1  augustss 			sc->sc_freetds = std;
   1888         1.1  augustss 		}
   1889         1.1  augustss 	}
   1890         1.1  augustss 	std = sc->sc_freetds;
   1891        1.42  augustss 	sc->sc_freetds = std->link.std;
   1892  1.264.4.55     skrll 	mutex_exit(&sc->sc_lock);
   1893  1.264.4.55     skrll 
   1894        1.42  augustss 	memset(&std->td, 0, sizeof(uhci_td_t));
   1895  1.264.4.55     skrll 
   1896         1.1  augustss 	return std;
   1897         1.1  augustss }
   1898         1.1  augustss 
   1899  1.264.4.55     skrll #define TD_IS_FREE 0x12345678
   1900  1.264.4.55     skrll 
   1901         1.1  augustss void
   1902  1.264.4.55     skrll uhci_free_std_locked(uhci_softc_t *sc, uhci_soft_td_t *std)
   1903         1.1  augustss {
   1904  1.264.4.55     skrll 	KASSERT(mutex_owned(&sc->sc_lock));
   1905  1.264.4.55     skrll 
   1906         1.7  augustss #ifdef DIAGNOSTIC
   1907        1.88   tsutsui 	if (le32toh(std->td.td_token) == TD_IS_FREE) {
   1908  1.264.4.65     skrll 		printf("%s: freeing free TD %p\n", __func__, std);
   1909         1.7  augustss 		return;
   1910         1.7  augustss 	}
   1911        1.88   tsutsui 	std->td.td_token = htole32(TD_IS_FREE);
   1912         1.7  augustss #endif
   1913  1.264.4.55     skrll 
   1914        1.42  augustss 	std->link.std = sc->sc_freetds;
   1915         1.1  augustss 	sc->sc_freetds = std;
   1916         1.1  augustss }
   1917         1.1  augustss 
   1918  1.264.4.55     skrll void
   1919  1.264.4.55     skrll uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std)
   1920  1.264.4.55     skrll {
   1921  1.264.4.55     skrll 	mutex_enter(&sc->sc_lock);
   1922  1.264.4.55     skrll 	uhci_free_std_locked(sc, std);
   1923  1.264.4.55     skrll 	mutex_exit(&sc->sc_lock);
   1924  1.264.4.55     skrll }
   1925  1.264.4.55     skrll 
   1926         1.1  augustss uhci_soft_qh_t *
   1927       1.119  augustss uhci_alloc_sqh(uhci_softc_t *sc)
   1928         1.1  augustss {
   1929         1.1  augustss 	uhci_soft_qh_t *sqh;
   1930        1.63  augustss 	usbd_status err;
   1931         1.1  augustss 	int i, offs;
   1932         1.7  augustss 	usb_dma_t dma;
   1933         1.1  augustss 
   1934  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1935  1.264.4.21     skrll 
   1936  1.264.4.55     skrll 	mutex_enter(&sc->sc_lock);
   1937        1.63  augustss 	if (sc->sc_freeqhs == NULL) {
   1938  1.264.4.21     skrll 		DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
   1939  1.264.4.55     skrll 		mutex_exit(&sc->sc_lock);
   1940  1.264.4.55     skrll 
   1941        1.63  augustss 		err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK,
   1942        1.63  augustss 			  UHCI_QH_ALIGN, &dma);
   1943        1.63  augustss 		if (err)
   1944  1.264.4.52     skrll 			return NULL;
   1945  1.264.4.55     skrll 
   1946  1.264.4.55     skrll 		mutex_enter(&sc->sc_lock);
   1947  1.264.4.54     skrll 		for (i = 0; i < UHCI_SQH_CHUNK; i++) {
   1948        1.42  augustss 			offs = i * UHCI_SQH_SIZE;
   1949       1.159  augustss 			sqh = KERNADDR(&dma, offs);
   1950       1.160  augustss 			sqh->physaddr = DMAADDR(&dma, offs);
   1951       1.223    bouyer 			sqh->dma = dma;
   1952       1.223    bouyer 			sqh->offs = offs;
   1953        1.42  augustss 			sqh->hlink = sc->sc_freeqhs;
   1954         1.1  augustss 			sc->sc_freeqhs = sqh;
   1955         1.1  augustss 		}
   1956         1.1  augustss 	}
   1957         1.1  augustss 	sqh = sc->sc_freeqhs;
   1958        1.42  augustss 	sc->sc_freeqhs = sqh->hlink;
   1959  1.264.4.55     skrll 	mutex_exit(&sc->sc_lock);
   1960  1.264.4.55     skrll 
   1961        1.42  augustss 	memset(&sqh->qh, 0, sizeof(uhci_qh_t));
   1962  1.264.4.55     skrll 
   1963  1.264.4.13     skrll 	return sqh;
   1964         1.1  augustss }
   1965         1.1  augustss 
   1966         1.1  augustss void
   1967       1.119  augustss uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   1968         1.1  augustss {
   1969  1.264.4.55     skrll 	KASSERT(mutex_owned(&sc->sc_lock));
   1970  1.264.4.55     skrll 
   1971        1.42  augustss 	sqh->hlink = sc->sc_freeqhs;
   1972         1.1  augustss 	sc->sc_freeqhs = sqh;
   1973         1.1  augustss }
   1974         1.1  augustss 
   1975         1.1  augustss void
   1976       1.119  augustss uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std,
   1977       1.119  augustss 		    uhci_soft_td_t *stdend)
   1978         1.1  augustss {
   1979         1.1  augustss 	uhci_soft_td_t *p;
   1980       1.256   tsutsui 	uint32_t td_link;
   1981         1.1  augustss 
   1982       1.223    bouyer 	/*
   1983       1.223    bouyer 	 * to avoid race condition with the controller which may be looking
   1984       1.223    bouyer 	 * at this chain, we need to first invalidate all links, and
   1985       1.223    bouyer 	 * then wait for the controller to move to another queue
   1986       1.223    bouyer 	 */
   1987       1.223    bouyer 	for (p = std; p != stdend; p = p->link.std) {
   1988       1.223    bouyer 		usb_syncmem(&p->dma,
   1989       1.223    bouyer 		    p->offs + offsetof(uhci_td_t, td_link),
   1990       1.223    bouyer 		    sizeof(p->td.td_link),
   1991       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1992       1.256   tsutsui 		td_link = le32toh(p->td.td_link);
   1993       1.256   tsutsui 		usb_syncmem(&p->dma,
   1994       1.256   tsutsui 		    p->offs + offsetof(uhci_td_t, td_link),
   1995       1.256   tsutsui 		    sizeof(p->td.td_link),
   1996       1.256   tsutsui 		    BUS_DMASYNC_PREREAD);
   1997       1.256   tsutsui 		if ((td_link & UHCI_PTR_T) == 0) {
   1998       1.255   tsutsui 			p->td.td_link = htole32(UHCI_PTR_T);
   1999       1.223    bouyer 			usb_syncmem(&p->dma,
   2000       1.223    bouyer 			    p->offs + offsetof(uhci_td_t, td_link),
   2001       1.223    bouyer 			    sizeof(p->td.td_link),
   2002       1.223    bouyer 			    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2003       1.223    bouyer 		}
   2004       1.223    bouyer 	}
   2005       1.223    bouyer 	delay(UHCI_QH_REMOVE_DELAY);
   2006       1.223    bouyer 
   2007         1.1  augustss 	for (; std != stdend; std = p) {
   2008        1.42  augustss 		p = std->link.std;
   2009         1.1  augustss 		uhci_free_std(sc, std);
   2010         1.1  augustss 	}
   2011         1.1  augustss }
   2012         1.1  augustss 
   2013         1.1  augustss usbd_status
   2014  1.264.4.70     skrll uhci_alloc_std_chain(uhci_softc_t *sc, struct usbd_xfer *xfer, int len,
   2015  1.264.4.70     skrll     int rd, uhci_soft_td_t **sp)
   2016         1.1  augustss {
   2017  1.264.4.55     skrll 	struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
   2018  1.264.4.55     skrll 	uint16_t flags = xfer->ux_flags;
   2019  1.264.4.70     skrll 	uhci_soft_td_t *p;
   2020         1.1  augustss 
   2021  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2022  1.264.4.21     skrll 
   2023  1.264.4.55     skrll 	DPRINTFN(8, "xfer=%p pipe=%p", xfer, xfer->ux_pipe, 0, 0);
   2024       1.248       mrg 
   2025  1.264.4.55     skrll 	ASSERT_SLEEPABLE();
   2026  1.264.4.55     skrll 	KASSERT(sp);
   2027       1.248       mrg 
   2028  1.264.4.70     skrll 	int maxp = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize);
   2029         1.1  augustss 	if (maxp == 0) {
   2030  1.264.4.65     skrll 		printf("%s: maxp=0\n", __func__);
   2031  1.264.4.13     skrll 		return USBD_INVAL;
   2032         1.1  augustss 	}
   2033  1.264.4.55     skrll 	size_t ntd = (len + maxp - 1) / maxp;
   2034  1.264.4.70     skrll 	if (!rd && (flags & USBD_FORCE_SHORT_XFER)) {
   2035        1.73  augustss 		ntd++;
   2036  1.264.4.70     skrll 	}
   2037  1.264.4.55     skrll 	DPRINTFN(10, "maxp=%d ntd=%d", maxp, ntd, 0, 0);
   2038  1.264.4.21     skrll 
   2039  1.264.4.55     skrll 	uxfer->ux_stds = NULL;
   2040  1.264.4.55     skrll 	uxfer->ux_nstd = ntd;
   2041  1.264.4.70     skrll 	p = NULL;
   2042        1.73  augustss 	if (ntd == 0) {
   2043  1.264.4.55     skrll 		*sp = NULL;
   2044  1.264.4.27     skrll 		DPRINTF("ntd=0", 0, 0, 0, 0);
   2045  1.264.4.13     skrll 		return USBD_NORMAL_COMPLETION;
   2046        1.73  augustss 	}
   2047  1.264.4.55     skrll 	uxfer->ux_stds = kmem_alloc(sizeof(uhci_soft_td_t *) * ntd,
   2048  1.264.4.55     skrll 	    KM_SLEEP);
   2049  1.264.4.55     skrll 
   2050         1.1  augustss 	ntd--;
   2051  1.264.4.70     skrll 	for (int i = ntd; i >= 0; i--) {
   2052         1.1  augustss 		p = uhci_alloc_std(sc);
   2053        1.63  augustss 		if (p == NULL) {
   2054  1.264.4.70     skrll 			uhci_free_stds(sc, uxfer);
   2055  1.264.4.13     skrll 			return USBD_NOMEM;
   2056         1.1  augustss 		}
   2057  1.264.4.55     skrll 		uxfer->ux_stds[i] = p;
   2058         1.1  augustss 	}
   2059  1.264.4.70     skrll 
   2060  1.264.4.70     skrll 	*sp = uxfer->ux_stds[0];
   2061  1.264.4.21     skrll 
   2062  1.264.4.13     skrll 	return USBD_NORMAL_COMPLETION;
   2063         1.1  augustss }
   2064         1.1  augustss 
   2065  1.264.4.55     skrll Static void
   2066  1.264.4.55     skrll uhci_free_stds(uhci_softc_t *sc, struct uhci_xfer *ux)
   2067  1.264.4.55     skrll {
   2068  1.264.4.55     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2069  1.264.4.55     skrll 
   2070  1.264.4.55     skrll 	DPRINTFN(8, "ux=%p", ux, 0, 0, 0);
   2071  1.264.4.55     skrll 
   2072  1.264.4.55     skrll 	mutex_enter(&sc->sc_lock);
   2073  1.264.4.55     skrll 	for (size_t i = 0; i < ux->ux_nstd; i++) {
   2074  1.264.4.55     skrll 		uhci_soft_td_t *std = ux->ux_stds[i];
   2075  1.264.4.55     skrll #ifdef DIAGNOSTIC
   2076  1.264.4.55     skrll 		if (le32toh(std->td.td_token) == TD_IS_FREE) {
   2077  1.264.4.65     skrll 			printf("%s: freeing free TD %p\n", __func__, std);
   2078  1.264.4.55     skrll 			return;
   2079  1.264.4.55     skrll 		}
   2080  1.264.4.55     skrll 		std->td.td_token = htole32(TD_IS_FREE);
   2081  1.264.4.55     skrll #endif
   2082  1.264.4.55     skrll 		ux->ux_stds[i]->link.std = sc->sc_freetds;
   2083  1.264.4.55     skrll 		sc->sc_freetds = std;
   2084  1.264.4.55     skrll 	}
   2085  1.264.4.55     skrll 	mutex_exit(&sc->sc_lock);
   2086  1.264.4.55     skrll }
   2087  1.264.4.55     skrll 
   2088  1.264.4.55     skrll 
   2089  1.264.4.55     skrll Static void
   2090  1.264.4.55     skrll uhci_reset_std_chain(uhci_softc_t *sc, struct usbd_xfer *xfer,
   2091  1.264.4.58     skrll     int length, int isread, int *toggle, uhci_soft_td_t **lstd)
   2092  1.264.4.55     skrll {
   2093  1.264.4.55     skrll 	struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
   2094  1.264.4.55     skrll 	struct usbd_pipe *pipe = xfer->ux_pipe;
   2095  1.264.4.55     skrll 	usb_dma_t *dma = &xfer->ux_dmabuf;
   2096  1.264.4.55     skrll 	uint16_t flags = xfer->ux_flags;
   2097  1.264.4.55     skrll 	uhci_soft_td_t *std, *prev;
   2098  1.264.4.55     skrll 	int len = length;
   2099  1.264.4.55     skrll 	int tog = *toggle;
   2100  1.264.4.55     skrll 	int maxp;
   2101  1.264.4.55     skrll 	uint32_t status;
   2102  1.264.4.55     skrll 	size_t i;
   2103  1.264.4.55     skrll 
   2104  1.264.4.55     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2105  1.264.4.55     skrll 	DPRINTFN(8, "xfer=%p len %d isread %d toggle %d", xfer,
   2106  1.264.4.55     skrll 	    len, isread, *toggle);
   2107  1.264.4.55     skrll 
   2108  1.264.4.70     skrll 	KASSERT(len != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER)));
   2109  1.264.4.55     skrll 
   2110  1.264.4.55     skrll 	maxp = UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize);
   2111  1.264.4.55     skrll 	KASSERT(maxp != 0);
   2112  1.264.4.55     skrll 
   2113  1.264.4.70     skrll 	int addr = xfer->ux_pipe->up_dev->ud_addr;
   2114  1.264.4.70     skrll 	int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;
   2115  1.264.4.70     skrll 
   2116  1.264.4.55     skrll 	status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE);
   2117  1.264.4.55     skrll 	if (pipe->up_dev->ud_speed == USB_SPEED_LOW)
   2118  1.264.4.55     skrll 		status |= UHCI_TD_LS;
   2119  1.264.4.55     skrll 	if (flags & USBD_SHORT_XFER_OK)
   2120  1.264.4.55     skrll 		status |= UHCI_TD_SPD;
   2121  1.264.4.55     skrll 	usb_syncmem(dma, 0, len,
   2122  1.264.4.55     skrll 	    isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
   2123  1.264.4.55     skrll 	std = prev = NULL;
   2124  1.264.4.70     skrll 	for (i = 0; len != 0 && i < uxfer->ux_nstd; i++, prev = std) {
   2125  1.264.4.55     skrll 		int l = len;
   2126  1.264.4.55     skrll 		std = uxfer->ux_stds[i];
   2127  1.264.4.55     skrll 		if (l > maxp)
   2128  1.264.4.55     skrll 			l = maxp;
   2129  1.264.4.55     skrll 
   2130  1.264.4.55     skrll 		if (prev) {
   2131  1.264.4.55     skrll 			prev->link.std = std;
   2132  1.264.4.55     skrll 			prev->td.td_link = htole32(
   2133  1.264.4.55     skrll 			    std->physaddr | UHCI_PTR_VF | UHCI_PTR_TD
   2134  1.264.4.55     skrll 			    );
   2135  1.264.4.55     skrll 			usb_syncmem(&prev->dma, prev->offs, sizeof(prev->td),
   2136  1.264.4.55     skrll 			    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2137  1.264.4.55     skrll 		}
   2138  1.264.4.55     skrll 
   2139  1.264.4.55     skrll 		usb_syncmem(&std->dma, std->offs, sizeof(std->td),
   2140  1.264.4.55     skrll 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   2141  1.264.4.55     skrll 
   2142  1.264.4.70     skrll 		std->td.td_link = htole32(UHCI_PTR_T | UHCI_PTR_VF | UHCI_PTR_TD);
   2143  1.264.4.55     skrll 		std->td.td_status = htole32(status);
   2144  1.264.4.70     skrll 		std->td.td_token = htole32(
   2145  1.264.4.70     skrll 		    UHCI_TD_SET_ENDPT(UE_GET_ADDR(endpt)) |
   2146  1.264.4.70     skrll 		    UHCI_TD_SET_DEVADDR(addr) |
   2147  1.264.4.55     skrll 		    UHCI_TD_SET_PID(isread ? UHCI_TD_PID_IN : UHCI_TD_PID_OUT) |
   2148  1.264.4.55     skrll 		    UHCI_TD_SET_DT(tog) |
   2149  1.264.4.55     skrll 		    UHCI_TD_SET_MAXLEN(l)
   2150  1.264.4.55     skrll 		    );
   2151  1.264.4.70     skrll 		std->td.td_buffer = htole32(DMAADDR(dma, i * maxp));
   2152  1.264.4.70     skrll 
   2153  1.264.4.70     skrll 		std->link.std = NULL;
   2154  1.264.4.55     skrll 
   2155  1.264.4.55     skrll 		usb_syncmem(&std->dma, std->offs, sizeof(std->td),
   2156  1.264.4.55     skrll 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2157  1.264.4.55     skrll 		tog ^= 1;
   2158  1.264.4.55     skrll 
   2159  1.264.4.55     skrll 		len -= l;
   2160  1.264.4.55     skrll 	}
   2161  1.264.4.55     skrll 	KASSERTMSG(len == 0, "xfer %p alen %d len %d mps %d ux_nqtd %zu i %zu",
   2162  1.264.4.55     skrll 	    xfer, length, len, maxp, uxfer->ux_nstd, i);
   2163  1.264.4.55     skrll 
   2164  1.264.4.70     skrll 	if (!isread &&
   2165  1.264.4.70     skrll 	    (flags & USBD_FORCE_SHORT_XFER) &&
   2166  1.264.4.70     skrll 	    length % maxp == 0) {
   2167  1.264.4.70     skrll 		/* Force a 0 length transfer at the end. */
   2168  1.264.4.70     skrll 		KASSERTMSG(i < uxfer->ux_nstd, "i=%zu nstd=%zu", i,
   2169  1.264.4.70     skrll 		    uxfer->ux_nstd);
   2170  1.264.4.70     skrll 		std = uxfer->ux_stds[i++];
   2171  1.264.4.70     skrll 
   2172  1.264.4.70     skrll 		std->td.td_link = htole32(UHCI_PTR_T | UHCI_PTR_VF | UHCI_PTR_TD);
   2173  1.264.4.70     skrll 		std->td.td_status = htole32(status);
   2174  1.264.4.70     skrll 		std->td.td_token = htole32(
   2175  1.264.4.70     skrll 		    UHCI_TD_SET_ENDPT(UE_GET_ADDR(endpt)) |
   2176  1.264.4.70     skrll 		    UHCI_TD_SET_DEVADDR(addr) |
   2177  1.264.4.70     skrll 		    UHCI_TD_SET_PID(UHCI_TD_PID_OUT) |
   2178  1.264.4.70     skrll 		    UHCI_TD_SET_DT(tog) |
   2179  1.264.4.70     skrll 		    UHCI_TD_SET_MAXLEN(0)
   2180  1.264.4.70     skrll 		    );
   2181  1.264.4.70     skrll 		std->td.td_buffer = 0;
   2182  1.264.4.55     skrll 		usb_syncmem(&std->dma, std->offs, sizeof(std->td),
   2183  1.264.4.55     skrll 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2184  1.264.4.70     skrll 
   2185  1.264.4.70     skrll 		std->link.std = NULL;
   2186  1.264.4.70     skrll 		if (prev) {
   2187  1.264.4.70     skrll 			prev->link.std = std;
   2188  1.264.4.70     skrll 			prev->td.td_link = htole32(
   2189  1.264.4.70     skrll 			    std->physaddr | UHCI_PTR_VF | UHCI_PTR_TD
   2190  1.264.4.70     skrll 			    );
   2191  1.264.4.70     skrll 			usb_syncmem(&prev->dma, prev->offs, sizeof(prev->td),
   2192  1.264.4.70     skrll 			    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2193  1.264.4.70     skrll 		}
   2194  1.264.4.70     skrll 		tog ^= 1;
   2195  1.264.4.55     skrll 	}
   2196  1.264.4.55     skrll 	*lstd = std;
   2197  1.264.4.55     skrll 	*toggle = tog;
   2198  1.264.4.55     skrll }
   2199  1.264.4.55     skrll 
   2200        1.38  augustss void
   2201  1.264.4.25     skrll uhci_device_clear_toggle(struct usbd_pipe *pipe)
   2202        1.38  augustss {
   2203  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
   2204        1.38  augustss 	upipe->nexttoggle = 0;
   2205        1.38  augustss }
   2206        1.38  augustss 
   2207        1.38  augustss void
   2208  1.264.4.25     skrll uhci_noop(struct usbd_pipe *pipe)
   2209        1.38  augustss {
   2210        1.38  augustss }
   2211        1.38  augustss 
   2212  1.264.4.55     skrll int
   2213  1.264.4.55     skrll uhci_device_bulk_init(struct usbd_xfer *xfer)
   2214  1.264.4.55     skrll {
   2215  1.264.4.55     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2216  1.264.4.55     skrll 	struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
   2217  1.264.4.55     skrll 	usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc;
   2218  1.264.4.55     skrll 	int endpt = ed->bEndpointAddress;
   2219  1.264.4.55     skrll 	int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
   2220  1.264.4.55     skrll 	int len = xfer->ux_bufsize;
   2221  1.264.4.55     skrll 	int err = 0;
   2222  1.264.4.55     skrll 
   2223  1.264.4.55     skrll 
   2224  1.264.4.55     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2225  1.264.4.55     skrll 	DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, len, xfer->ux_flags, 0);
   2226  1.264.4.55     skrll 
   2227  1.264.4.55     skrll 	if (sc->sc_dying)
   2228  1.264.4.55     skrll 		return USBD_IOERROR;
   2229  1.264.4.55     skrll 
   2230  1.264.4.55     skrll 	KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
   2231  1.264.4.55     skrll 
   2232  1.264.4.55     skrll 	uxfer->ux_type = UX_BULK;
   2233  1.264.4.70     skrll 	err = uhci_alloc_std_chain(sc, xfer, len, isread, &uxfer->ux_stdstart);
   2234  1.264.4.55     skrll 	if (err)
   2235  1.264.4.55     skrll 		return err;
   2236  1.264.4.55     skrll 
   2237  1.264.4.55     skrll #ifdef UHCI_DEBUG
   2238  1.264.4.55     skrll 	if (uhcidebug >= 10) {
   2239  1.264.4.55     skrll 		DPRINTF("--- dump start ---", 0, 0, 0, 0);
   2240  1.264.4.55     skrll 		uhci_dump_tds(uxfer->ux_stdstart);
   2241  1.264.4.55     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   2242  1.264.4.55     skrll 	}
   2243  1.264.4.55     skrll #endif
   2244  1.264.4.55     skrll 
   2245  1.264.4.55     skrll 	return 0;
   2246  1.264.4.55     skrll }
   2247  1.264.4.55     skrll 
   2248  1.264.4.55     skrll Static void
   2249  1.264.4.55     skrll uhci_device_bulk_fini(struct usbd_xfer *xfer)
   2250  1.264.4.55     skrll {
   2251  1.264.4.55     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2252  1.264.4.55     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   2253  1.264.4.55     skrll 
   2254  1.264.4.55     skrll 	KASSERT(ux->ux_type == UX_BULK);
   2255  1.264.4.55     skrll 
   2256  1.264.4.55     skrll 	uhci_free_stds(sc, ux);
   2257  1.264.4.55     skrll 	if (ux->ux_nstd)
   2258  1.264.4.55     skrll 		kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd);
   2259  1.264.4.55     skrll }
   2260  1.264.4.55     skrll 
   2261         1.1  augustss usbd_status
   2262  1.264.4.25     skrll uhci_device_bulk_transfer(struct usbd_xfer *xfer)
   2263         1.1  augustss {
   2264  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2265        1.63  augustss 	usbd_status err;
   2266        1.16  augustss 
   2267        1.52  augustss 	/* Insert last in queue. */
   2268       1.248       mrg 	mutex_enter(&sc->sc_lock);
   2269        1.63  augustss 	err = usb_insert_transfer(xfer);
   2270       1.248       mrg 	mutex_exit(&sc->sc_lock);
   2271        1.63  augustss 	if (err)
   2272  1.264.4.13     skrll 		return err;
   2273        1.52  augustss 
   2274       1.152  augustss 	/*
   2275        1.92  augustss 	 * Pipe isn't running (otherwise err would be USBD_INPROG),
   2276        1.92  augustss 	 * so start it first.
   2277        1.67  augustss 	 */
   2278  1.264.4.13     skrll 	return uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
   2279        1.16  augustss }
   2280        1.16  augustss 
   2281        1.16  augustss usbd_status
   2282  1.264.4.25     skrll uhci_device_bulk_start(struct usbd_xfer *xfer)
   2283        1.16  augustss {
   2284  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   2285  1.264.4.39     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   2286  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2287        1.55  augustss 	uhci_soft_td_t *data, *dataend;
   2288         1.1  augustss 	uhci_soft_qh_t *sqh;
   2289  1.264.4.55     skrll 	int len;
   2290  1.264.4.55     skrll 	int endpt;
   2291  1.264.4.55     skrll 	int isread;
   2292         1.1  augustss 
   2293  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2294  1.264.4.55     skrll 	DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length,
   2295  1.264.4.55     skrll 	    xfer->ux_flags, 0);
   2296         1.1  augustss 
   2297        1.82  augustss 	if (sc->sc_dying)
   2298  1.264.4.13     skrll 		return USBD_IOERROR;
   2299        1.82  augustss 
   2300  1.264.4.31     skrll 	KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
   2301  1.264.4.55     skrll 	KASSERT(xfer->ux_length <= xfer->ux_bufsize);
   2302       1.248       mrg 
   2303   1.264.4.7     skrll 	len = xfer->ux_length;
   2304   1.264.4.7     skrll 	endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
   2305        1.45  augustss 	isread = UE_GET_DIR(endpt) == UE_DIR_IN;
   2306  1.264.4.33     skrll 	sqh = upipe->bulk.sqh;
   2307         1.1  augustss 
   2308  1.264.4.55     skrll 	/* Take lock here to protect nexttoggle */
   2309  1.264.4.55     skrll 	mutex_enter(&sc->sc_lock);
   2310         1.1  augustss 
   2311  1.264.4.55     skrll 	uhci_reset_std_chain(sc, xfer, len, isread, &upipe->nexttoggle,
   2312  1.264.4.58     skrll 	    &dataend);
   2313  1.264.4.55     skrll 
   2314  1.264.4.55     skrll 	data = ux->ux_stdstart;
   2315  1.264.4.55     skrll 	ux->ux_stdend = dataend;
   2316        1.88   tsutsui 	dataend->td.td_status |= htole32(UHCI_TD_IOC);
   2317       1.223    bouyer 	usb_syncmem(&dataend->dma,
   2318       1.223    bouyer 	    dataend->offs + offsetof(uhci_td_t, td_status),
   2319       1.223    bouyer 	    sizeof(dataend->td.td_status),
   2320       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2321       1.223    bouyer 
   2322        1.59  augustss #ifdef UHCI_DEBUG
   2323  1.264.4.55     skrll 	if (uhcidebug >= 10) {
   2324  1.264.4.47     skrll 		DPRINTF("--- dump start ---", 0, 0, 0, 0);
   2325  1.264.4.55     skrll 		DPRINTFN(10, "before transfer", 0, 0, 0, 0);
   2326  1.264.4.58     skrll 		uhci_dump_tds(data);
   2327  1.264.4.47     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   2328         1.1  augustss 	}
   2329         1.1  augustss #endif
   2330         1.1  augustss 
   2331  1.264.4.41     skrll 	KASSERT(ux->ux_isdone);
   2332         1.7  augustss #ifdef DIAGNOSTIC
   2333  1.264.4.41     skrll 	ux->ux_isdone = false;
   2334         1.7  augustss #endif
   2335         1.1  augustss 
   2336        1.55  augustss 	sqh->elink = data;
   2337       1.121  augustss 	sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD);
   2338       1.223    bouyer 	/* uhci_add_bulk() will do usb_syncmem(sqh) */
   2339         1.1  augustss 
   2340         1.1  augustss 	uhci_add_bulk(sc, sqh);
   2341  1.264.4.56     skrll 	uhci_add_intr_list(sc, ux);
   2342         1.1  augustss 
   2343   1.264.4.7     skrll 	if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
   2344   1.264.4.7     skrll 		callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
   2345  1.264.4.39     skrll 			    uhci_timeout, xfer);
   2346        1.13  augustss 	}
   2347   1.264.4.7     skrll 	xfer->ux_status = USBD_IN_PROGRESS;
   2348  1.264.4.55     skrll 	mutex_exit(&sc->sc_lock);
   2349         1.1  augustss 
   2350   1.264.4.7     skrll 	if (sc->sc_bus.ub_usepolling)
   2351        1.63  augustss 		uhci_waitintr(sc, xfer);
   2352        1.26  augustss 
   2353  1.264.4.13     skrll 	return USBD_IN_PROGRESS;
   2354         1.1  augustss }
   2355         1.1  augustss 
   2356         1.1  augustss /* Abort a device bulk request. */
   2357         1.1  augustss void
   2358  1.264.4.25     skrll uhci_device_bulk_abort(struct usbd_xfer *xfer)
   2359         1.1  augustss {
   2360  1.264.4.37     skrll 	uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer);
   2361       1.248       mrg 
   2362       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2363       1.248       mrg 
   2364  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2365  1.264.4.21     skrll 
   2366        1.66  augustss 	uhci_abort_xfer(xfer, USBD_CANCELLED);
   2367        1.33  augustss }
   2368        1.33  augustss 
   2369        1.92  augustss /*
   2370       1.154  augustss  * Abort a device request.
   2371       1.154  augustss  * If this routine is called at splusb() it guarantees that the request
   2372       1.154  augustss  * will be removed from the hardware scheduling and that the callback
   2373       1.154  augustss  * for it will be called with USBD_CANCELLED status.
   2374       1.154  augustss  * It's impossible to guarantee that the requested transfer will not
   2375       1.154  augustss  * have happened since the hardware runs concurrently.
   2376       1.154  augustss  * If the transaction has already happened we rely on the ordinary
   2377       1.154  augustss  * interrupt processing to process it.
   2378       1.248       mrg  * XXX This is most probably wrong.
   2379       1.248       mrg  * XXXMRG this doesn't make sense anymore.
   2380        1.92  augustss  */
   2381        1.33  augustss void
   2382  1.264.4.25     skrll uhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status)
   2383        1.33  augustss {
   2384  1.264.4.39     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   2385  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   2386  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2387        1.33  augustss 	uhci_soft_td_t *std;
   2388       1.188  augustss 	int wake;
   2389        1.65  augustss 
   2390  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2391  1.264.4.21     skrll 	DPRINTFN(1,"xfer=%p, status=%d", xfer, status, 0, 0);
   2392        1.33  augustss 
   2393       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2394   1.264.4.3     skrll 	ASSERT_SLEEPABLE();
   2395       1.248       mrg 
   2396       1.153  augustss 	if (sc->sc_dying) {
   2397       1.153  augustss 		/* If we're dying, just do the software part. */
   2398   1.264.4.7     skrll 		xfer->ux_status = status;	/* make software ignore it */
   2399   1.264.4.7     skrll 		callout_stop(&xfer->ux_callout);
   2400       1.153  augustss 		usb_transfer_complete(xfer);
   2401       1.194  christos 		return;
   2402        1.92  augustss 	}
   2403        1.92  augustss 
   2404       1.153  augustss 	/*
   2405       1.188  augustss 	 * If an abort is already in progress then just wait for it to
   2406       1.188  augustss 	 * complete and return.
   2407       1.188  augustss 	 */
   2408   1.264.4.7     skrll 	if (xfer->ux_hcflags & UXFER_ABORTING) {
   2409  1.264.4.21     skrll 		DPRINTFN(2, "already aborting", 0, 0, 0, 0);
   2410       1.188  augustss #ifdef DIAGNOSTIC
   2411       1.188  augustss 		if (status == USBD_TIMEOUT)
   2412  1.264.4.65     skrll 			printf("%s: TIMEOUT while aborting\n", __func__);
   2413       1.188  augustss #endif
   2414       1.188  augustss 		/* Override the status which might be USBD_TIMEOUT. */
   2415   1.264.4.7     skrll 		xfer->ux_status = status;
   2416  1.264.4.21     skrll 		DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0);
   2417   1.264.4.7     skrll 		xfer->ux_hcflags |= UXFER_ABORTWAIT;
   2418   1.264.4.7     skrll 		while (xfer->ux_hcflags & UXFER_ABORTING)
   2419   1.264.4.7     skrll 			cv_wait(&xfer->ux_hccv, &sc->sc_lock);
   2420       1.248       mrg 		goto done;
   2421       1.188  augustss 	}
   2422   1.264.4.7     skrll 	xfer->ux_hcflags |= UXFER_ABORTING;
   2423       1.188  augustss 
   2424       1.188  augustss 	/*
   2425       1.153  augustss 	 * Step 1: Make interrupt routine and hardware ignore xfer.
   2426       1.153  augustss 	 */
   2427   1.264.4.7     skrll 	xfer->ux_status = status;	/* make software ignore it */
   2428   1.264.4.7     skrll 	callout_stop(&xfer->ux_callout);
   2429  1.264.4.61     skrll 	uhci_del_intr_list(sc, ux);
   2430  1.264.4.61     skrll 
   2431  1.264.4.39     skrll 	DPRINTF("stop ux=%p", ux, 0, 0, 0);
   2432  1.264.4.41     skrll 	for (std = ux->ux_stdstart; std != NULL; std = std->link.std) {
   2433       1.223    bouyer 		usb_syncmem(&std->dma,
   2434       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_status),
   2435       1.223    bouyer 		    sizeof(std->td.td_status),
   2436       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   2437        1.92  augustss 		std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC));
   2438       1.223    bouyer 		usb_syncmem(&std->dma,
   2439       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_status),
   2440       1.223    bouyer 		    sizeof(std->td.td_status),
   2441       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2442       1.223    bouyer 	}
   2443        1.92  augustss 
   2444       1.162  augustss 	/*
   2445       1.153  augustss 	 * Step 2: Wait until we know hardware has finished any possible
   2446       1.153  augustss 	 * use of the xfer.  Also make sure the soft interrupt routine
   2447       1.153  augustss 	 * has run.
   2448       1.153  augustss 	 */
   2449       1.248       mrg 	/* Hardware finishes in 1ms */
   2450   1.264.4.7     skrll 	usb_delay_ms_locked(upipe->pipe.up_dev->ud_bus, 2, &sc->sc_lock);
   2451       1.153  augustss 	sc->sc_softwake = 1;
   2452       1.153  augustss 	usb_schedsoftintr(&sc->sc_bus);
   2453  1.264.4.27     skrll 	DPRINTF("cv_wait", 0, 0, 0, 0);
   2454       1.248       mrg 	cv_wait(&sc->sc_softwake_cv, &sc->sc_lock);
   2455       1.162  augustss 
   2456       1.153  augustss 	/*
   2457       1.153  augustss 	 * Step 3: Execute callback.
   2458       1.153  augustss 	 */
   2459  1.264.4.27     skrll 	DPRINTF("callback", 0, 0, 0, 0);
   2460       1.100  augustss #ifdef DIAGNOSTIC
   2461  1.264.4.41     skrll 	ux->ux_isdone = true;
   2462       1.100  augustss #endif
   2463   1.264.4.7     skrll 	wake = xfer->ux_hcflags & UXFER_ABORTWAIT;
   2464   1.264.4.7     skrll 	xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT);
   2465       1.106  augustss 	usb_transfer_complete(xfer);
   2466       1.188  augustss 	if (wake)
   2467   1.264.4.7     skrll 		cv_broadcast(&xfer->ux_hccv);
   2468       1.248       mrg done:
   2469       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2470         1.1  augustss }
   2471         1.1  augustss 
   2472         1.1  augustss /* Close a device bulk pipe. */
   2473         1.1  augustss void
   2474  1.264.4.25     skrll uhci_device_bulk_close(struct usbd_pipe *pipe)
   2475         1.1  augustss {
   2476  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
   2477  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
   2478         1.1  augustss 
   2479       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2480       1.248       mrg 
   2481  1.264.4.33     skrll 	uhci_free_sqh(sc, upipe->bulk.sqh);
   2482       1.236  drochner 
   2483   1.264.4.7     skrll 	pipe->up_endpoint->ue_toggle = upipe->nexttoggle;
   2484         1.1  augustss }
   2485         1.1  augustss 
   2486  1.264.4.55     skrll int
   2487  1.264.4.55     skrll uhci_device_ctrl_init(struct usbd_xfer *xfer)
   2488         1.1  augustss {
   2489  1.264.4.55     skrll 	struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
   2490  1.264.4.55     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   2491  1.264.4.55     skrll 	usb_device_request_t *req = &xfer->ux_request;
   2492  1.264.4.55     skrll 	struct usbd_device *dev = upipe->pipe.up_dev;
   2493  1.264.4.55     skrll 	uhci_softc_t *sc = dev->ud_bus->ub_hcpriv;
   2494  1.264.4.55     skrll 	int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
   2495  1.264.4.70     skrll 	uhci_soft_td_t *data;
   2496  1.264.4.55     skrll 	int len;
   2497        1.63  augustss 	usbd_status err;
   2498  1.264.4.55     skrll 	int isread;
   2499        1.16  augustss 
   2500  1.264.4.55     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2501  1.264.4.70     skrll 	DPRINTFN(3, "xfer=%p len=%d, addr=%d, endpt=%d", xfer, xfer->ux_bufsize,
   2502  1.264.4.70     skrll 	    dev->ud_addr, endpt);
   2503        1.16  augustss 
   2504  1.264.4.55     skrll 	isread = req->bmRequestType & UT_READ;
   2505  1.264.4.55     skrll 	len = xfer->ux_bufsize;
   2506         1.1  augustss 
   2507  1.264.4.55     skrll 	uxfer->ux_type = UX_CTRL;
   2508  1.264.4.55     skrll 	/* Set up data transaction */
   2509  1.264.4.55     skrll 	if (len != 0) {
   2510  1.264.4.70     skrll 		err = uhci_alloc_std_chain(sc, xfer, len, isread, &data);
   2511  1.264.4.55     skrll 		if (err)
   2512  1.264.4.55     skrll 			return err;
   2513  1.264.4.55     skrll 	}
   2514  1.264.4.55     skrll 	/* Set up interrupt info. */
   2515  1.264.4.70     skrll 	uxfer->ux_setup = upipe->ctrl.setup;
   2516  1.264.4.70     skrll 	uxfer->ux_stat = upipe->ctrl.stat;
   2517  1.264.4.55     skrll 	uxfer->ux_data = data;
   2518  1.264.4.55     skrll 
   2519  1.264.4.55     skrll 	return 0;
   2520  1.264.4.55     skrll }
   2521  1.264.4.55     skrll 
   2522  1.264.4.55     skrll Static void
   2523  1.264.4.55     skrll uhci_device_ctrl_fini(struct usbd_xfer *xfer)
   2524  1.264.4.55     skrll {
   2525  1.264.4.55     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2526  1.264.4.55     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   2527  1.264.4.55     skrll 
   2528  1.264.4.55     skrll 	KASSERT(ux->ux_type == UX_CTRL);
   2529  1.264.4.55     skrll 
   2530  1.264.4.55     skrll 	uhci_free_stds(sc, ux);
   2531  1.264.4.55     skrll 	if (ux->ux_nstd)
   2532  1.264.4.55     skrll 		kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd);
   2533  1.264.4.55     skrll }
   2534  1.264.4.55     skrll 
   2535  1.264.4.55     skrll usbd_status
   2536  1.264.4.55     skrll uhci_device_ctrl_transfer(struct usbd_xfer *xfer)
   2537  1.264.4.55     skrll {
   2538  1.264.4.55     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2539  1.264.4.55     skrll 	usbd_status err;
   2540  1.264.4.55     skrll 
   2541  1.264.4.55     skrll 	/* Insert last in queue. */
   2542  1.264.4.55     skrll 	mutex_enter(&sc->sc_lock);
   2543  1.264.4.55     skrll 	err = usb_insert_transfer(xfer);
   2544  1.264.4.55     skrll 	mutex_exit(&sc->sc_lock);
   2545  1.264.4.55     skrll 	if (err)
   2546  1.264.4.55     skrll 		return err;
   2547  1.264.4.55     skrll 
   2548  1.264.4.55     skrll 	/*
   2549  1.264.4.55     skrll 	 * Pipe isn't running (otherwise err would be USBD_INPROG),
   2550  1.264.4.55     skrll 	 * so start it first.
   2551  1.264.4.55     skrll 	 */
   2552  1.264.4.55     skrll 	return uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
   2553  1.264.4.55     skrll }
   2554  1.264.4.55     skrll 
   2555  1.264.4.55     skrll usbd_status
   2556  1.264.4.55     skrll uhci_device_ctrl_start(struct usbd_xfer *xfer)
   2557  1.264.4.55     skrll {
   2558  1.264.4.55     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2559  1.264.4.55     skrll 	struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
   2560  1.264.4.55     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   2561  1.264.4.55     skrll 	usb_device_request_t *req = &xfer->ux_request;
   2562  1.264.4.55     skrll 	struct usbd_device *dev = upipe->pipe.up_dev;
   2563  1.264.4.55     skrll 	int addr = dev->ud_addr;
   2564  1.264.4.55     skrll 	int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
   2565  1.264.4.55     skrll 	uhci_soft_td_t *setup, *stat, *next, *dataend;
   2566  1.264.4.55     skrll 	uhci_soft_qh_t *sqh;
   2567  1.264.4.55     skrll 	int len;
   2568  1.264.4.55     skrll 	int isread;
   2569  1.264.4.55     skrll 
   2570  1.264.4.55     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2571  1.264.4.55     skrll 
   2572  1.264.4.55     skrll 	if (sc->sc_dying)
   2573  1.264.4.55     skrll 		return USBD_IOERROR;
   2574  1.264.4.55     skrll 
   2575  1.264.4.55     skrll 	KASSERT(xfer->ux_rqflags & URQ_REQUEST);
   2576  1.264.4.55     skrll 
   2577  1.264.4.55     skrll 	DPRINTFN(3, "type=0x%02x, request=0x%02x, "
   2578  1.264.4.55     skrll 	    "wValue=0x%04x, wIndex=0x%04x",
   2579  1.264.4.55     skrll 	    req->bmRequestType, req->bRequest, UGETW(req->wValue),
   2580  1.264.4.55     skrll 	    UGETW(req->wIndex));
   2581  1.264.4.55     skrll 	DPRINTFN(3, "len=%d, addr=%d, endpt=%d",
   2582  1.264.4.55     skrll 	    UGETW(req->wLength), dev->ud_addr, endpt, 0);
   2583  1.264.4.55     skrll 
   2584  1.264.4.55     skrll 	isread = req->bmRequestType & UT_READ;
   2585  1.264.4.55     skrll 	len = UGETW(req->wLength);
   2586  1.264.4.55     skrll 
   2587  1.264.4.55     skrll 	setup = upipe->ctrl.setup;
   2588  1.264.4.55     skrll 	stat = upipe->ctrl.stat;
   2589  1.264.4.55     skrll 	sqh = upipe->ctrl.sqh;
   2590  1.264.4.55     skrll 
   2591  1.264.4.55     skrll 	memcpy(KERNADDR(&upipe->ctrl.reqdma, 0), req, sizeof(*req));
   2592  1.264.4.55     skrll 	usb_syncmem(&upipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE);
   2593  1.264.4.55     skrll 
   2594  1.264.4.55     skrll 	mutex_enter(&sc->sc_lock);
   2595  1.264.4.55     skrll 
   2596  1.264.4.55     skrll 	/* Set up data transaction */
   2597  1.264.4.55     skrll 	if (len != 0) {
   2598  1.264.4.55     skrll 		upipe->nexttoggle = 1;
   2599  1.264.4.55     skrll 		next = uxfer->ux_data;
   2600  1.264.4.55     skrll 		uhci_reset_std_chain(sc, xfer, len, isread,
   2601  1.264.4.58     skrll 		    &upipe->nexttoggle, &dataend);
   2602  1.264.4.55     skrll 		dataend->link.std = stat;
   2603  1.264.4.55     skrll 		dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD);
   2604  1.264.4.55     skrll 		usb_syncmem(&dataend->dma,
   2605  1.264.4.55     skrll 		    dataend->offs + offsetof(uhci_td_t, td_link),
   2606  1.264.4.55     skrll 		    sizeof(dataend->td.td_link),
   2607  1.264.4.55     skrll 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2608  1.264.4.55     skrll 	} else {
   2609  1.264.4.55     skrll 		next = stat;
   2610  1.264.4.55     skrll 	}
   2611  1.264.4.55     skrll 
   2612  1.264.4.70     skrll 	const uint32_t status = UHCI_TD_ZERO_ACTLEN(
   2613  1.264.4.55     skrll 	    UHCI_TD_SET_ERRCNT(3) |
   2614  1.264.4.70     skrll 	    UHCI_TD_ACTIVE |
   2615  1.264.4.70     skrll 	    (dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0)
   2616  1.264.4.55     skrll 	    );
   2617  1.264.4.70     skrll 	setup->link.std = next;
   2618  1.264.4.70     skrll 	setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD);
   2619  1.264.4.70     skrll 	setup->td.td_status = htole32(status);
   2620  1.264.4.70     skrll 	setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof(*req), endpt, addr));
   2621  1.264.4.70     skrll 	setup->td.td_buffer = htole32(DMAADDR(&upipe->ctrl.reqdma, 0));
   2622  1.264.4.70     skrll 
   2623  1.264.4.55     skrll 	usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td),
   2624  1.264.4.55     skrll 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2625  1.264.4.55     skrll 
   2626  1.264.4.55     skrll 	stat->link.std = NULL;
   2627  1.264.4.55     skrll 	stat->td.td_link = htole32(UHCI_PTR_T);
   2628  1.264.4.70     skrll 	stat->td.td_status = htole32(status | UHCI_TD_IOC);
   2629  1.264.4.55     skrll 	stat->td.td_token =
   2630  1.264.4.55     skrll 		htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) :
   2631  1.264.4.55     skrll 				 UHCI_TD_IN (0, endpt, addr, 1));
   2632  1.264.4.55     skrll 	stat->td.td_buffer = htole32(0);
   2633  1.264.4.55     skrll 	usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td),
   2634  1.264.4.55     skrll 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2635  1.264.4.55     skrll 
   2636  1.264.4.55     skrll #ifdef UHCI_DEBUG
   2637  1.264.4.55     skrll 	if (uhcidebug >= 10) {
   2638  1.264.4.55     skrll 		DPRINTF("--- dump start ---", 0, 0, 0, 0);
   2639  1.264.4.55     skrll 		DPRINTF("before transfer", 0, 0, 0, 0);
   2640  1.264.4.55     skrll 		uhci_dump_tds(setup);
   2641  1.264.4.55     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   2642  1.264.4.55     skrll 	}
   2643  1.264.4.55     skrll #endif
   2644  1.264.4.55     skrll 
   2645  1.264.4.55     skrll 	/* Set up interrupt info. */
   2646  1.264.4.55     skrll 	uxfer->ux_setup = setup;
   2647  1.264.4.55     skrll 	uxfer->ux_stat = stat;
   2648  1.264.4.55     skrll 	KASSERT(uxfer->ux_isdone);
   2649  1.264.4.55     skrll #ifdef DIAGNOSTIC
   2650  1.264.4.55     skrll 	uxfer->ux_isdone = false;
   2651  1.264.4.55     skrll #endif
   2652  1.264.4.55     skrll 
   2653  1.264.4.55     skrll 	sqh->elink = setup;
   2654  1.264.4.55     skrll 	sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD);
   2655  1.264.4.55     skrll 	/* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */
   2656  1.264.4.55     skrll 
   2657  1.264.4.55     skrll 	if (dev->ud_speed == USB_SPEED_LOW)
   2658  1.264.4.55     skrll 		uhci_add_ls_ctrl(sc, sqh);
   2659  1.264.4.55     skrll 	else
   2660  1.264.4.55     skrll 		uhci_add_hs_ctrl(sc, sqh);
   2661  1.264.4.56     skrll 	uhci_add_intr_list(sc, uxfer);
   2662  1.264.4.55     skrll #ifdef UHCI_DEBUG
   2663  1.264.4.55     skrll 	if (uhcidebug >= 12) {
   2664  1.264.4.55     skrll 		uhci_soft_td_t *std;
   2665  1.264.4.55     skrll 		uhci_soft_qh_t *xqh;
   2666  1.264.4.55     skrll 		uhci_soft_qh_t *sxqh;
   2667  1.264.4.55     skrll 		int maxqh = 0;
   2668  1.264.4.55     skrll 		uhci_physaddr_t link;
   2669  1.264.4.55     skrll 		DPRINTFN(12, "--- dump start ---", 0, 0, 0, 0);
   2670  1.264.4.55     skrll 		DPRINTFN(12, "follow from [0]", 0, 0, 0, 0);
   2671  1.264.4.55     skrll 		for (std = sc->sc_vframes[0].htd, link = 0;
   2672  1.264.4.55     skrll 		     (link & UHCI_PTR_QH) == 0;
   2673  1.264.4.55     skrll 		     std = std->link.std) {
   2674  1.264.4.55     skrll 			link = le32toh(std->td.td_link);
   2675  1.264.4.55     skrll 			uhci_dump_td(std);
   2676  1.264.4.55     skrll 		}
   2677  1.264.4.55     skrll 		sxqh = (uhci_soft_qh_t *)std;
   2678  1.264.4.55     skrll 		uhci_dump_qh(sxqh);
   2679  1.264.4.55     skrll 		for (xqh = sxqh;
   2680  1.264.4.55     skrll 		     xqh != NULL;
   2681  1.264.4.55     skrll 		     xqh = (maxqh++ == 5 || xqh->hlink == sxqh ||
   2682  1.264.4.55     skrll 			xqh->hlink == xqh ? NULL : xqh->hlink)) {
   2683  1.264.4.55     skrll 			uhci_dump_qh(xqh);
   2684  1.264.4.55     skrll 		}
   2685  1.264.4.55     skrll 		DPRINTFN(12, "Enqueued QH:", 0, 0, 0, 0);
   2686  1.264.4.55     skrll 		uhci_dump_qh(sqh);
   2687  1.264.4.55     skrll 		uhci_dump_tds(sqh->elink);
   2688  1.264.4.55     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   2689  1.264.4.55     skrll 	}
   2690  1.264.4.55     skrll #endif
   2691  1.264.4.55     skrll 	if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
   2692  1.264.4.55     skrll 		callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
   2693  1.264.4.55     skrll 			    uhci_timeout, xfer);
   2694  1.264.4.55     skrll 	}
   2695  1.264.4.55     skrll 	xfer->ux_status = USBD_IN_PROGRESS;
   2696  1.264.4.55     skrll 	mutex_exit(&sc->sc_lock);
   2697  1.264.4.55     skrll 
   2698  1.264.4.55     skrll 	if (sc->sc_bus.ub_usepolling)
   2699        1.63  augustss 		uhci_waitintr(sc, xfer);
   2700  1.264.4.55     skrll 
   2701  1.264.4.13     skrll 	return USBD_IN_PROGRESS;
   2702         1.1  augustss }
   2703         1.1  augustss 
   2704  1.264.4.55     skrll int
   2705  1.264.4.55     skrll uhci_device_intr_init(struct usbd_xfer *xfer)
   2706  1.264.4.55     skrll {
   2707  1.264.4.55     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2708  1.264.4.55     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   2709  1.264.4.55     skrll 	usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc;
   2710  1.264.4.55     skrll 	int endpt = ed->bEndpointAddress;
   2711  1.264.4.55     skrll 	int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
   2712  1.264.4.55     skrll 	int len = xfer->ux_bufsize;
   2713  1.264.4.55     skrll 	int err;
   2714  1.264.4.55     skrll 
   2715  1.264.4.55     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2716  1.264.4.55     skrll 
   2717  1.264.4.55     skrll 	DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length,
   2718  1.264.4.55     skrll 	    xfer->ux_flags, 0);
   2719  1.264.4.55     skrll 
   2720  1.264.4.55     skrll 	KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
   2721  1.264.4.55     skrll 	KASSERT(len != 0);
   2722  1.264.4.55     skrll 
   2723  1.264.4.55     skrll 	ux->ux_type = UX_INTR;
   2724  1.264.4.55     skrll 	ux->ux_nstd = 0;
   2725  1.264.4.70     skrll 	err = uhci_alloc_std_chain(sc, xfer, len, isread, &ux->ux_stdstart);
   2726  1.264.4.55     skrll 
   2727  1.264.4.55     skrll 	return err;
   2728  1.264.4.55     skrll }
   2729  1.264.4.55     skrll 
   2730  1.264.4.55     skrll Static void
   2731  1.264.4.55     skrll uhci_device_intr_fini(struct usbd_xfer *xfer)
   2732  1.264.4.55     skrll {
   2733  1.264.4.55     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2734  1.264.4.55     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   2735  1.264.4.55     skrll 
   2736  1.264.4.55     skrll 	KASSERT(ux->ux_type == UX_INTR);
   2737  1.264.4.55     skrll 
   2738  1.264.4.55     skrll 	uhci_free_stds(sc, ux);
   2739  1.264.4.55     skrll 	if (ux->ux_nstd)
   2740  1.264.4.55     skrll 		kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd);
   2741  1.264.4.55     skrll }
   2742  1.264.4.55     skrll 
   2743         1.1  augustss usbd_status
   2744  1.264.4.25     skrll uhci_device_intr_transfer(struct usbd_xfer *xfer)
   2745         1.1  augustss {
   2746  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2747        1.63  augustss 	usbd_status err;
   2748        1.16  augustss 
   2749        1.52  augustss 	/* Insert last in queue. */
   2750       1.248       mrg 	mutex_enter(&sc->sc_lock);
   2751        1.63  augustss 	err = usb_insert_transfer(xfer);
   2752       1.248       mrg 	mutex_exit(&sc->sc_lock);
   2753        1.63  augustss 	if (err)
   2754  1.264.4.13     skrll 		return err;
   2755        1.52  augustss 
   2756       1.152  augustss 	/*
   2757        1.92  augustss 	 * Pipe isn't running (otherwise err would be USBD_INPROG),
   2758        1.92  augustss 	 * so start it first.
   2759        1.67  augustss 	 */
   2760  1.264.4.13     skrll 	return uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
   2761        1.16  augustss }
   2762        1.16  augustss 
   2763        1.16  augustss usbd_status
   2764  1.264.4.25     skrll uhci_device_intr_start(struct usbd_xfer *xfer)
   2765        1.16  augustss {
   2766  1.264.4.39     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   2767  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   2768  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2769        1.55  augustss 	uhci_soft_td_t *data, *dataend;
   2770         1.1  augustss 	uhci_soft_qh_t *sqh;
   2771       1.187     skrll 	int isread, endpt;
   2772       1.248       mrg 	int i;
   2773         1.1  augustss 
   2774        1.82  augustss 	if (sc->sc_dying)
   2775  1.264.4.13     skrll 		return USBD_IOERROR;
   2776        1.82  augustss 
   2777  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2778  1.264.4.21     skrll 
   2779  1.264.4.55     skrll 	DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length,
   2780  1.264.4.55     skrll 	    xfer->ux_flags, 0);
   2781         1.1  augustss 
   2782  1.264.4.31     skrll 	KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
   2783  1.264.4.55     skrll 	KASSERT(xfer->ux_length <= xfer->ux_bufsize);
   2784       1.248       mrg 
   2785   1.264.4.7     skrll 	endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
   2786       1.187     skrll 	isread = UE_GET_DIR(endpt) == UE_DIR_IN;
   2787       1.187     skrll 
   2788  1.264.4.55     skrll 	data = ux->ux_stdstart;
   2789       1.187     skrll 
   2790  1.264.4.55     skrll 	KASSERT(ux->ux_isdone);
   2791  1.264.4.55     skrll #ifdef DIAGNOSTIC
   2792  1.264.4.55     skrll 	ux->ux_isdone = false;
   2793  1.264.4.55     skrll #endif
   2794  1.264.4.55     skrll 
   2795  1.264.4.55     skrll 	/* Take lock to protect nexttoggle */
   2796  1.264.4.55     skrll 	mutex_enter(&sc->sc_lock);
   2797  1.264.4.55     skrll 	uhci_reset_std_chain(sc, xfer, xfer->ux_length, isread,
   2798  1.264.4.58     skrll 	    &upipe->nexttoggle, &dataend);
   2799       1.248       mrg 
   2800        1.88   tsutsui 	dataend->td.td_status |= htole32(UHCI_TD_IOC);
   2801       1.223    bouyer 	usb_syncmem(&dataend->dma,
   2802       1.223    bouyer 	    dataend->offs + offsetof(uhci_td_t, td_status),
   2803       1.223    bouyer 	    sizeof(dataend->td.td_status),
   2804       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2805  1.264.4.55     skrll 	ux->ux_stdend = dataend;
   2806         1.1  augustss 
   2807        1.59  augustss #ifdef UHCI_DEBUG
   2808  1.264.4.43     skrll 	if (uhcidebug >= 10) {
   2809  1.264.4.47     skrll 		DPRINTF("--- dump start ---", 0, 0, 0, 0);
   2810        1.55  augustss 		uhci_dump_tds(data);
   2811  1.264.4.33     skrll 		uhci_dump_qh(upipe->intr.qhs[0]);
   2812  1.264.4.47     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   2813         1.1  augustss 	}
   2814         1.1  augustss #endif
   2815         1.1  augustss 
   2816  1.264.4.33     skrll 	DPRINTFN(10, "qhs[0]=%p", upipe->intr.qhs[0], 0, 0, 0);
   2817  1.264.4.33     skrll 	for (i = 0; i < upipe->intr.npoll; i++) {
   2818  1.264.4.33     skrll 		sqh = upipe->intr.qhs[i];
   2819        1.55  augustss 		sqh->elink = data;
   2820       1.121  augustss 		sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD);
   2821       1.223    bouyer 		usb_syncmem(&sqh->dma,
   2822       1.223    bouyer 		    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   2823       1.223    bouyer 		    sizeof(sqh->qh.qh_elink),
   2824       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2825         1.1  augustss 	}
   2826  1.264.4.56     skrll 	uhci_add_intr_list(sc, ux);
   2827   1.264.4.7     skrll 	xfer->ux_status = USBD_IN_PROGRESS;
   2828       1.248       mrg 	mutex_exit(&sc->sc_lock);
   2829         1.1  augustss 
   2830        1.59  augustss #ifdef UHCI_DEBUG
   2831  1.264.4.43     skrll 	if (uhcidebug >= 10) {
   2832  1.264.4.47     skrll 		DPRINTF("--- dump start ---", 0, 0, 0, 0);
   2833        1.55  augustss 		uhci_dump_tds(data);
   2834  1.264.4.33     skrll 		uhci_dump_qh(upipe->intr.qhs[0]);
   2835  1.264.4.47     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   2836         1.1  augustss 	}
   2837         1.1  augustss #endif
   2838         1.1  augustss 
   2839  1.264.4.13     skrll 	return USBD_IN_PROGRESS;
   2840         1.1  augustss }
   2841         1.1  augustss 
   2842         1.1  augustss /* Abort a device control request. */
   2843         1.1  augustss void
   2844  1.264.4.25     skrll uhci_device_ctrl_abort(struct usbd_xfer *xfer)
   2845         1.1  augustss {
   2846  1.264.4.37     skrll 	uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer);
   2847       1.248       mrg 
   2848       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2849       1.248       mrg 
   2850  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2851        1.66  augustss 	uhci_abort_xfer(xfer, USBD_CANCELLED);
   2852         1.1  augustss }
   2853         1.1  augustss 
   2854         1.1  augustss /* Close a device control pipe. */
   2855         1.1  augustss void
   2856  1.264.4.25     skrll uhci_device_ctrl_close(struct usbd_pipe *pipe)
   2857         1.1  augustss {
   2858  1.264.4.55     skrll 	uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
   2859  1.264.4.55     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
   2860  1.264.4.55     skrll 
   2861  1.264.4.55     skrll 	uhci_free_sqh(sc, upipe->ctrl.sqh);
   2862  1.264.4.55     skrll 	uhci_free_std_locked(sc, upipe->ctrl.setup);
   2863  1.264.4.55     skrll 	uhci_free_std_locked(sc, upipe->ctrl.stat);
   2864  1.264.4.55     skrll 
   2865         1.1  augustss }
   2866         1.1  augustss 
   2867         1.1  augustss /* Abort a device interrupt request. */
   2868         1.1  augustss void
   2869  1.264.4.25     skrll uhci_device_intr_abort(struct usbd_xfer *xfer)
   2870         1.1  augustss {
   2871  1.264.4.37     skrll 	uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer);
   2872       1.248       mrg 
   2873       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2874   1.264.4.7     skrll 	KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
   2875       1.248       mrg 
   2876  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2877  1.264.4.27     skrll 	DPRINTF("xfer=%p", xfer, 0, 0, 0);
   2878       1.264     skrll 
   2879        1.66  augustss 	uhci_abort_xfer(xfer, USBD_CANCELLED);
   2880         1.1  augustss }
   2881         1.1  augustss 
   2882         1.1  augustss /* Close a device interrupt pipe. */
   2883         1.1  augustss void
   2884  1.264.4.25     skrll uhci_device_intr_close(struct usbd_pipe *pipe)
   2885         1.1  augustss {
   2886  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
   2887  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
   2888        1.92  augustss 	int i, npoll;
   2889       1.248       mrg 
   2890       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2891         1.1  augustss 
   2892         1.1  augustss 	/* Unlink descriptors from controller data structures. */
   2893  1.264.4.33     skrll 	npoll = upipe->intr.npoll;
   2894         1.1  augustss 	for (i = 0; i < npoll; i++)
   2895  1.264.4.33     skrll 		uhci_remove_intr(sc, upipe->intr.qhs[i]);
   2896         1.1  augustss 
   2897       1.152  augustss 	/*
   2898         1.1  augustss 	 * We now have to wait for any activity on the physical
   2899         1.1  augustss 	 * descriptors to stop.
   2900         1.1  augustss 	 */
   2901       1.248       mrg 	usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock);
   2902         1.1  augustss 
   2903  1.264.4.54     skrll 	for (i = 0; i < npoll; i++)
   2904  1.264.4.33     skrll 		uhci_free_sqh(sc, upipe->intr.qhs[i]);
   2905  1.264.4.33     skrll 	kmem_free(upipe->intr.qhs, npoll * sizeof(uhci_soft_qh_t *));
   2906         1.1  augustss }
   2907         1.1  augustss 
   2908  1.264.4.55     skrll int
   2909  1.264.4.55     skrll uhci_device_isoc_init(struct usbd_xfer *xfer)
   2910         1.1  augustss {
   2911  1.264.4.55     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   2912         1.1  augustss 
   2913  1.264.4.55     skrll 	KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
   2914  1.264.4.55     skrll 	KASSERT(xfer->ux_nframes != 0);
   2915  1.264.4.55     skrll 	KASSERT(ux->ux_isdone);
   2916         1.1  augustss 
   2917  1.264.4.55     skrll 	ux->ux_type = UX_ISOC;
   2918  1.264.4.55     skrll 	return 0;
   2919  1.264.4.55     skrll }
   2920  1.264.4.47     skrll 
   2921  1.264.4.55     skrll Static void
   2922  1.264.4.55     skrll uhci_device_isoc_fini(struct usbd_xfer *xfer)
   2923  1.264.4.55     skrll {
   2924  1.264.4.55     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   2925         1.1  augustss 
   2926  1.264.4.55     skrll 	KASSERT(ux->ux_type == UX_ISOC);
   2927         1.1  augustss }
   2928         1.1  augustss 
   2929        1.16  augustss usbd_status
   2930  1.264.4.25     skrll uhci_device_isoc_transfer(struct usbd_xfer *xfer)
   2931        1.16  augustss {
   2932  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2933  1.264.4.68     skrll 	usbd_status err __diagused;
   2934        1.48  augustss 
   2935  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2936  1.264.4.21     skrll 	DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0);
   2937        1.48  augustss 
   2938        1.48  augustss 	/* Put it on our queue, */
   2939       1.248       mrg 	mutex_enter(&sc->sc_lock);
   2940        1.63  augustss 	err = usb_insert_transfer(xfer);
   2941       1.248       mrg 	mutex_exit(&sc->sc_lock);
   2942        1.48  augustss 
   2943  1.264.4.68     skrll 	KASSERT(err == USBD_NORMAL_COMPLETION);
   2944        1.48  augustss 
   2945        1.48  augustss 	/* insert into schedule, */
   2946        1.48  augustss 
   2947  1.264.4.55     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   2948  1.264.4.62     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   2949  1.264.4.33     skrll 	struct isoc *isoc = &upipe->isoc;
   2950  1.264.4.68     skrll 	uhci_soft_td_t *std = NULL;
   2951   1.264.4.1     skrll 	uint32_t buf, len, status, offs;
   2952       1.248       mrg 	int i, next, nframes;
   2953   1.264.4.7     skrll 	int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN;
   2954        1.48  augustss 
   2955  1.264.4.21     skrll 	DPRINTFN(5, "used=%d next=%d xfer=%p nframes=%d",
   2956  1.264.4.33     skrll 	    isoc->inuse, isoc->next, xfer, xfer->ux_nframes);
   2957        1.48  augustss 
   2958        1.82  augustss 	if (sc->sc_dying)
   2959  1.264.4.68     skrll 		return USBD_IOERROR;
   2960        1.82  augustss 
   2961   1.264.4.7     skrll 	if (xfer->ux_status == USBD_IN_PROGRESS) {
   2962        1.48  augustss 		/* This request has already been entered into the frame list */
   2963  1.264.4.64     skrll 		printf("%s: xfer=%p in frame list\n", __func__, xfer);
   2964        1.68  augustss 		/* XXX */
   2965        1.48  augustss 	}
   2966        1.48  augustss 
   2967        1.48  augustss #ifdef DIAGNOSTIC
   2968  1.264.4.33     skrll 	if (isoc->inuse >= UHCI_VFRAMELIST_COUNT)
   2969  1.264.4.65     skrll 		printf("%s: overflow!\n", __func__);
   2970        1.19  augustss #endif
   2971        1.16  augustss 
   2972  1.264.4.68     skrll 	KASSERT(xfer->ux_nframes != 0);
   2973  1.264.4.68     skrll 
   2974  1.264.4.67     skrll 	mutex_enter(&sc->sc_lock);
   2975  1.264.4.33     skrll 	next = isoc->next;
   2976        1.48  augustss 	if (next == -1) {
   2977        1.48  augustss 		/* Not in use yet, schedule it a few frames ahead. */
   2978        1.48  augustss 		next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT;
   2979  1.264.4.21     skrll 		DPRINTFN(2, "start next=%d", next, 0, 0, 0);
   2980        1.48  augustss 	}
   2981        1.48  augustss 
   2982   1.264.4.7     skrll 	xfer->ux_status = USBD_IN_PROGRESS;
   2983  1.264.4.62     skrll 	ux->ux_curframe = next;
   2984        1.48  augustss 
   2985   1.264.4.7     skrll 	buf = DMAADDR(&xfer->ux_dmabuf, 0);
   2986       1.223    bouyer 	offs = 0;
   2987        1.88   tsutsui 	status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) |
   2988        1.88   tsutsui 				     UHCI_TD_ACTIVE |
   2989        1.88   tsutsui 				     UHCI_TD_IOS);
   2990   1.264.4.7     skrll 	nframes = xfer->ux_nframes;
   2991        1.48  augustss 	for (i = 0; i < nframes; i++) {
   2992  1.264.4.33     skrll 		std = isoc->stds[next];
   2993        1.48  augustss 		if (++next >= UHCI_VFRAMELIST_COUNT)
   2994        1.48  augustss 			next = 0;
   2995   1.264.4.7     skrll 		len = xfer->ux_frlengths[i];
   2996        1.88   tsutsui 		std->td.td_buffer = htole32(buf);
   2997   1.264.4.7     skrll 		usb_syncmem(&xfer->ux_dmabuf, offs, len,
   2998       1.223    bouyer 		    rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
   2999        1.48  augustss 		if (i == nframes - 1)
   3000        1.88   tsutsui 			status |= UHCI_TD_IOC;
   3001        1.88   tsutsui 		std->td.td_status = htole32(status);
   3002        1.88   tsutsui 		std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK);
   3003        1.88   tsutsui 		std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len));
   3004       1.223    bouyer 		usb_syncmem(&std->dma, std->offs, sizeof(std->td),
   3005       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   3006        1.59  augustss #ifdef UHCI_DEBUG
   3007  1.264.4.43     skrll 		if (uhcidebug >= 5) {
   3008  1.264.4.47     skrll 			DPRINTF("--- dump start ---", 0, 0, 0, 0);
   3009  1.264.4.27     skrll 			DPRINTF("TD %d", i, 0, 0, 0);
   3010        1.48  augustss 			uhci_dump_td(std);
   3011  1.264.4.47     skrll 			DPRINTF("--- dump end ---", 0, 0, 0, 0);
   3012        1.48  augustss 		}
   3013        1.48  augustss #endif
   3014        1.48  augustss 		buf += len;
   3015       1.223    bouyer 		offs += len;
   3016        1.48  augustss 	}
   3017  1.264.4.33     skrll 	isoc->next = next;
   3018  1.264.4.33     skrll 	isoc->inuse += xfer->ux_nframes;
   3019        1.16  augustss 
   3020        1.48  augustss 	/* Set up interrupt info. */
   3021  1.264.4.68     skrll 	ux->ux_stdstart = std;
   3022  1.264.4.68     skrll 	ux->ux_stdend = std;
   3023  1.264.4.31     skrll 
   3024  1.264.4.41     skrll 	KASSERT(ux->ux_isdone);
   3025        1.48  augustss #ifdef DIAGNOSTIC
   3026  1.264.4.41     skrll 	ux->ux_isdone = false;
   3027        1.48  augustss #endif
   3028  1.264.4.56     skrll 	uhci_add_intr_list(sc, ux);
   3029       1.152  augustss 
   3030       1.248       mrg 	mutex_exit(&sc->sc_lock);
   3031        1.48  augustss 
   3032  1.264.4.13     skrll 	return USBD_IN_PROGRESS;
   3033        1.16  augustss }
   3034        1.16  augustss 
   3035        1.16  augustss void
   3036  1.264.4.25     skrll uhci_device_isoc_abort(struct usbd_xfer *xfer)
   3037        1.16  augustss {
   3038  1.264.4.61     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   3039  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   3040  1.264.4.61     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   3041  1.264.4.33     skrll 	uhci_soft_td_t **stds = upipe->isoc.stds;
   3042        1.48  augustss 	uhci_soft_td_t *std;
   3043       1.248       mrg 	int i, n, nframes, maxlen, len;
   3044        1.92  augustss 
   3045       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   3046        1.92  augustss 
   3047        1.92  augustss 	/* Transfer is already done. */
   3048   1.264.4.7     skrll 	if (xfer->ux_status != USBD_NOT_STARTED &&
   3049   1.264.4.7     skrll 	    xfer->ux_status != USBD_IN_PROGRESS) {
   3050        1.92  augustss 		return;
   3051        1.92  augustss 	}
   3052        1.48  augustss 
   3053        1.92  augustss 	/* Give xfer the requested abort code. */
   3054   1.264.4.7     skrll 	xfer->ux_status = USBD_CANCELLED;
   3055        1.48  augustss 
   3056        1.48  augustss 	/* make hardware ignore it, */
   3057   1.264.4.7     skrll 	nframes = xfer->ux_nframes;
   3058  1.264.4.61     skrll 	n = ux->ux_curframe;
   3059        1.92  augustss 	maxlen = 0;
   3060        1.48  augustss 	for (i = 0; i < nframes; i++) {
   3061        1.48  augustss 		std = stds[n];
   3062       1.223    bouyer 		usb_syncmem(&std->dma,
   3063       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_status),
   3064       1.223    bouyer 		    sizeof(std->td.td_status),
   3065       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   3066        1.88   tsutsui 		std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC));
   3067       1.223    bouyer 		usb_syncmem(&std->dma,
   3068       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_status),
   3069       1.223    bouyer 		    sizeof(std->td.td_status),
   3070       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   3071       1.223    bouyer 		usb_syncmem(&std->dma,
   3072       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_token),
   3073       1.223    bouyer 		    sizeof(std->td.td_token),
   3074       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE);
   3075       1.130   tsutsui 		len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token));
   3076        1.92  augustss 		if (len > maxlen)
   3077        1.92  augustss 			maxlen = len;
   3078        1.48  augustss 		if (++n >= UHCI_VFRAMELIST_COUNT)
   3079        1.48  augustss 			n = 0;
   3080        1.48  augustss 	}
   3081        1.48  augustss 
   3082        1.92  augustss 	/* and wait until we are sure the hardware has finished. */
   3083        1.92  augustss 	delay(maxlen);
   3084        1.92  augustss 
   3085        1.96  augustss #ifdef DIAGNOSTIC
   3086  1.264.4.61     skrll 	ux->ux_isdone = true;
   3087        1.96  augustss #endif
   3088  1.264.4.61     skrll 	/* Remove from interrupt list. */
   3089  1.264.4.61     skrll 	uhci_del_intr_list(sc, ux);
   3090  1.264.4.61     skrll 
   3091  1.264.4.61     skrll 	/* Run callback. */
   3092        1.92  augustss 	usb_transfer_complete(xfer);
   3093        1.48  augustss 
   3094       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   3095        1.16  augustss }
   3096        1.16  augustss 
   3097        1.16  augustss void
   3098  1.264.4.25     skrll uhci_device_isoc_close(struct usbd_pipe *pipe)
   3099        1.16  augustss {
   3100  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
   3101  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
   3102        1.48  augustss 	uhci_soft_td_t *std, *vstd;
   3103  1.264.4.33     skrll 	struct isoc *isoc;
   3104       1.248       mrg 	int i;
   3105       1.248       mrg 
   3106       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   3107        1.16  augustss 
   3108        1.16  augustss 	/*
   3109        1.16  augustss 	 * Make sure all TDs are marked as inactive.
   3110        1.16  augustss 	 * Wait for completion.
   3111        1.16  augustss 	 * Unschedule.
   3112        1.16  augustss 	 * Deallocate.
   3113        1.16  augustss 	 */
   3114  1.264.4.33     skrll 	isoc = &upipe->isoc;
   3115        1.16  augustss 
   3116       1.223    bouyer 	for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
   3117  1.264.4.33     skrll 		std = isoc->stds[i];
   3118       1.223    bouyer 		usb_syncmem(&std->dma,
   3119       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_status),
   3120       1.223    bouyer 		    sizeof(std->td.td_status),
   3121       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   3122       1.223    bouyer 		std->td.td_status &= htole32(~UHCI_TD_ACTIVE);
   3123       1.223    bouyer 		usb_syncmem(&std->dma,
   3124       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_status),
   3125       1.223    bouyer 		    sizeof(std->td.td_status),
   3126       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   3127       1.223    bouyer 	}
   3128       1.248       mrg 	/* wait for completion */
   3129       1.248       mrg 	usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock);
   3130        1.16  augustss 
   3131        1.16  augustss 	for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
   3132  1.264.4.33     skrll 		std = isoc->stds[i];
   3133        1.48  augustss 		for (vstd = sc->sc_vframes[i].htd;
   3134        1.67  augustss 		     vstd != NULL && vstd->link.std != std;
   3135        1.42  augustss 		     vstd = vstd->link.std)
   3136        1.16  augustss 			;
   3137        1.67  augustss 		if (vstd == NULL) {
   3138        1.16  augustss 			/*panic*/
   3139  1.264.4.65     skrll 			printf("%s: %p not found\n", __func__, std);
   3140       1.248       mrg 			mutex_exit(&sc->sc_lock);
   3141        1.16  augustss 			return;
   3142        1.16  augustss 		}
   3143        1.42  augustss 		vstd->link = std->link;
   3144       1.223    bouyer 		usb_syncmem(&std->dma,
   3145       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_link),
   3146       1.223    bouyer 		    sizeof(std->td.td_link),
   3147       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE);
   3148        1.42  augustss 		vstd->td.td_link = std->td.td_link;
   3149       1.223    bouyer 		usb_syncmem(&vstd->dma,
   3150       1.223    bouyer 		    vstd->offs + offsetof(uhci_td_t, td_link),
   3151       1.223    bouyer 		    sizeof(vstd->td.td_link),
   3152       1.223    bouyer 		    BUS_DMASYNC_PREWRITE);
   3153  1.264.4.55     skrll 		uhci_free_std_locked(sc, std);
   3154        1.16  augustss 	}
   3155        1.16  augustss 
   3156  1.264.4.35     skrll 	kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *));
   3157        1.16  augustss }
   3158        1.16  augustss 
   3159        1.16  augustss usbd_status
   3160  1.264.4.25     skrll uhci_setup_isoc(struct usbd_pipe *pipe)
   3161        1.16  augustss {
   3162  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
   3163  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
   3164   1.264.4.7     skrll 	int addr = upipe->pipe.up_dev->ud_addr;
   3165   1.264.4.7     skrll 	int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
   3166        1.45  augustss 	int rd = UE_GET_DIR(endpt) == UE_DIR_IN;
   3167        1.48  augustss 	uhci_soft_td_t *std, *vstd;
   3168   1.264.4.1     skrll 	uint32_t token;
   3169  1.264.4.33     skrll 	struct isoc *isoc;
   3170       1.248       mrg 	int i;
   3171        1.16  augustss 
   3172  1.264.4.33     skrll 	isoc = &upipe->isoc;
   3173  1.264.4.55     skrll 
   3174  1.264.4.55     skrll 	isoc->stds = kmem_alloc(
   3175  1.264.4.55     skrll 	    UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *), KM_SLEEP);
   3176  1.264.4.33     skrll 	if (isoc->stds == NULL)
   3177       1.248       mrg 		return USBD_NOMEM;
   3178        1.16  augustss 
   3179        1.88   tsutsui 	token = rd ? UHCI_TD_IN (0, endpt, addr, 0) :
   3180        1.88   tsutsui 		     UHCI_TD_OUT(0, endpt, addr, 0);
   3181        1.16  augustss 
   3182        1.48  augustss 	/* Allocate the TDs and mark as inactive; */
   3183        1.16  augustss 	for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
   3184        1.48  augustss 		std = uhci_alloc_std(sc);
   3185        1.48  augustss 		if (std == 0)
   3186        1.48  augustss 			goto bad;
   3187        1.88   tsutsui 		std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */
   3188        1.88   tsutsui 		std->td.td_token = htole32(token);
   3189       1.223    bouyer 		usb_syncmem(&std->dma, std->offs, sizeof(std->td),
   3190       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   3191  1.264.4.33     skrll 		isoc->stds[i] = std;
   3192        1.16  augustss 	}
   3193        1.16  augustss 
   3194  1.264.4.55     skrll 	mutex_enter(&sc->sc_lock);
   3195  1.264.4.55     skrll 
   3196        1.48  augustss 	/* Insert TDs into schedule. */
   3197        1.16  augustss 	for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
   3198  1.264.4.33     skrll 		std = isoc->stds[i];
   3199        1.48  augustss 		vstd = sc->sc_vframes[i].htd;
   3200       1.223    bouyer 		usb_syncmem(&vstd->dma,
   3201       1.223    bouyer 		    vstd->offs + offsetof(uhci_td_t, td_link),
   3202       1.223    bouyer 		    sizeof(vstd->td.td_link),
   3203       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE);
   3204        1.42  augustss 		std->link = vstd->link;
   3205        1.42  augustss 		std->td.td_link = vstd->td.td_link;
   3206       1.223    bouyer 		usb_syncmem(&std->dma,
   3207       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_link),
   3208       1.223    bouyer 		    sizeof(std->td.td_link),
   3209       1.223    bouyer 		    BUS_DMASYNC_PREWRITE);
   3210        1.42  augustss 		vstd->link.std = std;
   3211       1.121  augustss 		vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD);
   3212       1.223    bouyer 		usb_syncmem(&vstd->dma,
   3213       1.223    bouyer 		    vstd->offs + offsetof(uhci_td_t, td_link),
   3214       1.223    bouyer 		    sizeof(vstd->td.td_link),
   3215       1.223    bouyer 		    BUS_DMASYNC_PREWRITE);
   3216        1.16  augustss 	}
   3217       1.248       mrg 	mutex_exit(&sc->sc_lock);
   3218        1.16  augustss 
   3219  1.264.4.33     skrll 	isoc->next = -1;
   3220  1.264.4.33     skrll 	isoc->inuse = 0;
   3221        1.48  augustss 
   3222  1.264.4.13     skrll 	return USBD_NORMAL_COMPLETION;
   3223        1.16  augustss 
   3224        1.48  augustss  bad:
   3225        1.16  augustss 	while (--i >= 0)
   3226  1.264.4.33     skrll 		uhci_free_std(sc, isoc->stds[i]);
   3227  1.264.4.35     skrll 	kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *));
   3228  1.264.4.13     skrll 	return USBD_NOMEM;
   3229        1.16  augustss }
   3230        1.16  augustss 
   3231        1.16  augustss void
   3232  1.264.4.25     skrll uhci_device_isoc_done(struct usbd_xfer *xfer)
   3233        1.16  augustss {
   3234  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   3235  1.264.4.39     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   3236       1.223    bouyer 	int i, offs;
   3237   1.264.4.7     skrll 	int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN;
   3238       1.223    bouyer 
   3239  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3240  1.264.4.21     skrll 	DPRINTFN(4, "length=%d, ux_state=0x%08x",
   3241  1.264.4.21     skrll 	    xfer->ux_actlen, xfer->ux_state, 0, 0);
   3242        1.93  augustss 
   3243        1.93  augustss #ifdef DIAGNOSTIC
   3244  1.264.4.41     skrll 	if (ux->ux_stdend == NULL) {
   3245  1.264.4.65     skrll 		printf("%s: xfer=%p stdend==NULL\n", __func__, xfer);
   3246        1.93  augustss #ifdef UHCI_DEBUG
   3247  1.264.4.47     skrll 		DPRINTF("--- dump start ---", 0, 0, 0, 0);
   3248  1.264.4.39     skrll 		uhci_dump_ii(ux);
   3249  1.264.4.47     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   3250        1.93  augustss #endif
   3251        1.93  augustss 		return;
   3252        1.93  augustss 	}
   3253        1.93  augustss #endif
   3254        1.48  augustss 
   3255        1.48  augustss 	/* Turn off the interrupt since it is active even if the TD is not. */
   3256  1.264.4.41     skrll 	usb_syncmem(&ux->ux_stdend->dma,
   3257  1.264.4.41     skrll 	    ux->ux_stdend->offs + offsetof(uhci_td_t, td_status),
   3258  1.264.4.41     skrll 	    sizeof(ux->ux_stdend->td.td_status),
   3259       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   3260  1.264.4.41     skrll 	ux->ux_stdend->td.td_status &= htole32(~UHCI_TD_IOC);
   3261  1.264.4.41     skrll 	usb_syncmem(&ux->ux_stdend->dma,
   3262  1.264.4.41     skrll 	    ux->ux_stdend->offs + offsetof(uhci_td_t, td_status),
   3263  1.264.4.41     skrll 	    sizeof(ux->ux_stdend->td.td_status),
   3264       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   3265        1.48  augustss 
   3266       1.223    bouyer 	offs = 0;
   3267   1.264.4.7     skrll 	for (i = 0; i < xfer->ux_nframes; i++) {
   3268   1.264.4.7     skrll 		usb_syncmem(&xfer->ux_dmabuf, offs, xfer->ux_frlengths[i],
   3269       1.223    bouyer 		    rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
   3270   1.264.4.7     skrll 		offs += xfer->ux_frlengths[i];
   3271       1.223    bouyer 	}
   3272        1.16  augustss }
   3273        1.16  augustss 
   3274         1.1  augustss void
   3275  1.264.4.25     skrll uhci_device_intr_done(struct usbd_xfer *xfer)
   3276         1.1  augustss {
   3277  1.264.4.38     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   3278  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   3279         1.1  augustss 	uhci_soft_qh_t *sqh;
   3280  1.264.4.55     skrll 	int i, npoll;
   3281         1.1  augustss 
   3282  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3283  1.264.4.21     skrll 	DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0);
   3284         1.1  augustss 
   3285   1.264.4.7     skrll 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
   3286       1.248       mrg 
   3287  1.264.4.33     skrll 	npoll = upipe->intr.npoll;
   3288  1.264.4.54     skrll 	for (i = 0; i < npoll; i++) {
   3289  1.264.4.33     skrll 		sqh = upipe->intr.qhs[i];
   3290       1.121  augustss 		sqh->elink = NULL;
   3291        1.88   tsutsui 		sqh->qh.qh_elink = htole32(UHCI_PTR_T);
   3292       1.223    bouyer 		usb_syncmem(&sqh->dma,
   3293       1.223    bouyer 		    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   3294       1.223    bouyer 		    sizeof(sqh->qh.qh_elink),
   3295       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   3296         1.1  augustss 	}
   3297  1.264.4.63     skrll 	const int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
   3298  1.264.4.63     skrll 	const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN;
   3299  1.264.4.63     skrll 	usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
   3300  1.264.4.63     skrll 	    isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
   3301         1.1  augustss }
   3302         1.1  augustss 
   3303         1.1  augustss /* Deallocate request data structures */
   3304         1.1  augustss void
   3305  1.264.4.25     skrll uhci_device_ctrl_done(struct usbd_xfer *xfer)
   3306         1.1  augustss {
   3307  1.264.4.38     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   3308  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   3309   1.264.4.7     skrll 	int len = UGETW(xfer->ux_request.wLength);
   3310   1.264.4.7     skrll 	int isread = (xfer->ux_request.bmRequestType & UT_READ);
   3311         1.1  augustss 
   3312   1.264.4.7     skrll 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
   3313       1.248       mrg 
   3314  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3315  1.264.4.31     skrll 
   3316  1.264.4.32     skrll 	KASSERT(xfer->ux_rqflags & URQ_REQUEST);
   3317         1.1  augustss 
   3318  1.264.4.61     skrll 	/* XXXNH move to uhci_idone??? */
   3319   1.264.4.7     skrll 	if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW)
   3320  1.264.4.33     skrll 		uhci_remove_ls_ctrl(sc, upipe->ctrl.sqh);
   3321       1.123  augustss 	else
   3322  1.264.4.33     skrll 		uhci_remove_hs_ctrl(sc, upipe->ctrl.sqh);
   3323         1.1  augustss 
   3324       1.223    bouyer 	if (len) {
   3325   1.264.4.7     skrll 		usb_syncmem(&xfer->ux_dmabuf, 0, len,
   3326       1.223    bouyer 		    isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
   3327       1.223    bouyer 	}
   3328  1.264.4.33     skrll 	usb_syncmem(&upipe->ctrl.reqdma, 0,
   3329       1.223    bouyer 	    sizeof(usb_device_request_t),  BUS_DMASYNC_POSTWRITE);
   3330       1.223    bouyer 
   3331  1.264.4.27     skrll 	DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0);
   3332         1.1  augustss }
   3333         1.1  augustss 
   3334         1.1  augustss /* Deallocate request data structures */
   3335         1.1  augustss void
   3336  1.264.4.25     skrll uhci_device_bulk_done(struct usbd_xfer *xfer)
   3337         1.1  augustss {
   3338  1.264.4.39     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   3339  1.264.4.38     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   3340  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   3341  1.264.4.51     skrll 	usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc;
   3342  1.264.4.51     skrll 	int endpt = ed->bEndpointAddress;
   3343  1.264.4.51     skrll 	int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
   3344       1.169  augustss 
   3345  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3346  1.264.4.39     skrll 	DPRINTFN(5, "xfer=%p ux=%p sc=%p upipe=%p", xfer, ux, sc,
   3347  1.264.4.21     skrll 	    upipe);
   3348       1.169  augustss 
   3349       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   3350       1.248       mrg 
   3351  1.264.4.33     skrll 	uhci_remove_bulk(sc, upipe->bulk.sqh);
   3352        1.32  augustss 
   3353  1.264.4.51     skrll 	if (xfer->ux_length) {
   3354  1.264.4.51     skrll 		usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
   3355  1.264.4.51     skrll 		    isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
   3356  1.264.4.51     skrll 	}
   3357        1.32  augustss 
   3358  1.264.4.21     skrll 	DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0);
   3359         1.1  augustss }
   3360         1.1  augustss 
   3361         1.1  augustss /* Add interrupt QH, called with vflock. */
   3362         1.1  augustss void
   3363       1.119  augustss uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   3364         1.1  augustss {
   3365        1.92  augustss 	struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos];
   3366        1.42  augustss 	uhci_soft_qh_t *eqh;
   3367         1.1  augustss 
   3368  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3369  1.264.4.21     skrll 	DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0);
   3370        1.92  augustss 
   3371        1.42  augustss 	eqh = vf->eqh;
   3372       1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   3373       1.223    bouyer 	    sizeof(eqh->qh.qh_hlink),
   3374       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE);
   3375        1.42  augustss 	sqh->hlink       = eqh->hlink;
   3376        1.42  augustss 	sqh->qh.qh_hlink = eqh->qh.qh_hlink;
   3377       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
   3378       1.223    bouyer 	    sizeof(sqh->qh.qh_hlink),
   3379       1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   3380        1.42  augustss 	eqh->hlink       = sqh;
   3381       1.121  augustss 	eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
   3382       1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   3383       1.223    bouyer 	    sizeof(eqh->qh.qh_hlink),
   3384       1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   3385         1.1  augustss 	vf->eqh = sqh;
   3386         1.1  augustss 	vf->bandwidth++;
   3387         1.1  augustss }
   3388         1.1  augustss 
   3389       1.119  augustss /* Remove interrupt QH. */
   3390         1.1  augustss void
   3391       1.119  augustss uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   3392         1.1  augustss {
   3393        1.92  augustss 	struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos];
   3394         1.1  augustss 	uhci_soft_qh_t *pqh;
   3395         1.1  augustss 
   3396  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3397  1.264.4.21     skrll 	DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0);
   3398         1.1  augustss 
   3399       1.124  augustss 	/* See comment in uhci_remove_ctrl() */
   3400       1.223    bouyer 
   3401       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
   3402       1.223    bouyer 	    sizeof(sqh->qh.qh_elink),
   3403       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   3404       1.124  augustss 	if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) {
   3405       1.124  augustss 		sqh->qh.qh_elink = htole32(UHCI_PTR_T);
   3406       1.223    bouyer 		usb_syncmem(&sqh->dma,
   3407       1.223    bouyer 		    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   3408       1.223    bouyer 		    sizeof(sqh->qh.qh_elink),
   3409       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   3410       1.124  augustss 		delay(UHCI_QH_REMOVE_DELAY);
   3411       1.124  augustss 	}
   3412       1.124  augustss 
   3413        1.92  augustss 	pqh = uhci_find_prev_qh(vf->hqh, sqh);
   3414       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
   3415       1.223    bouyer 	    sizeof(sqh->qh.qh_hlink),
   3416       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   3417        1.42  augustss 	pqh->hlink       = sqh->hlink;
   3418        1.42  augustss 	pqh->qh.qh_hlink = sqh->qh.qh_hlink;
   3419       1.223    bouyer 	usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
   3420       1.223    bouyer 	    sizeof(pqh->qh.qh_hlink),
   3421       1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   3422       1.124  augustss 	delay(UHCI_QH_REMOVE_DELAY);
   3423         1.1  augustss 	if (vf->eqh == sqh)
   3424         1.1  augustss 		vf->eqh = pqh;
   3425         1.1  augustss 	vf->bandwidth--;
   3426         1.1  augustss }
   3427         1.1  augustss 
   3428         1.1  augustss usbd_status
   3429       1.119  augustss uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival)
   3430         1.1  augustss {
   3431         1.1  augustss 	uhci_soft_qh_t *sqh;
   3432       1.248       mrg 	int i, npoll;
   3433         1.1  augustss 	u_int bestbw, bw, bestoffs, offs;
   3434         1.1  augustss 
   3435  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3436  1.264.4.21     skrll 	DPRINTFN(2, "pipe=%p", upipe, 0, 0, 0);
   3437         1.1  augustss 	if (ival == 0) {
   3438  1.264.4.65     skrll 		printf("%s: 0 interval\n", __func__);
   3439  1.264.4.13     skrll 		return USBD_INVAL;
   3440         1.1  augustss 	}
   3441         1.1  augustss 
   3442         1.1  augustss 	if (ival > UHCI_VFRAMELIST_COUNT)
   3443         1.1  augustss 		ival = UHCI_VFRAMELIST_COUNT;
   3444         1.1  augustss 	npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival;
   3445  1.264.4.27     skrll 	DPRINTF("ival=%d npoll=%d", ival, npoll, 0, 0);
   3446         1.1  augustss 
   3447  1.264.4.33     skrll 	upipe->intr.npoll = npoll;
   3448  1.264.4.33     skrll 	upipe->intr.qhs =
   3449       1.248       mrg 		kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP);
   3450  1.264.4.33     skrll 	if (upipe->intr.qhs == NULL)
   3451       1.248       mrg 		return USBD_NOMEM;
   3452         1.1  augustss 
   3453       1.152  augustss 	/*
   3454         1.1  augustss 	 * Figure out which offset in the schedule that has most
   3455         1.1  augustss 	 * bandwidth left over.
   3456         1.1  augustss 	 */
   3457         1.1  augustss #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1))
   3458         1.1  augustss 	for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) {
   3459         1.1  augustss 		for (bw = i = 0; i < npoll; i++)
   3460         1.1  augustss 			bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth;
   3461         1.1  augustss 		if (bw < bestbw) {
   3462         1.1  augustss 			bestbw = bw;
   3463         1.1  augustss 			bestoffs = offs;
   3464         1.1  augustss 		}
   3465         1.1  augustss 	}
   3466  1.264.4.27     skrll 	DPRINTF("bw=%d offs=%d", bestbw, bestoffs, 0, 0);
   3467  1.264.4.54     skrll 	for (i = 0; i < npoll; i++) {
   3468  1.264.4.33     skrll 		upipe->intr.qhs[i] = sqh = uhci_alloc_sqh(sc);
   3469       1.121  augustss 		sqh->elink = NULL;
   3470        1.88   tsutsui 		sqh->qh.qh_elink = htole32(UHCI_PTR_T);
   3471       1.223    bouyer 		usb_syncmem(&sqh->dma,
   3472       1.223    bouyer 		    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   3473       1.223    bouyer 		    sizeof(sqh->qh.qh_elink),
   3474       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   3475         1.1  augustss 		sqh->pos = MOD(i * ival + bestoffs);
   3476         1.1  augustss 	}
   3477         1.1  augustss #undef MOD
   3478         1.1  augustss 
   3479  1.264.4.55     skrll 	mutex_enter(&sc->sc_lock);
   3480         1.1  augustss 	/* Enter QHs into the controller data structures. */
   3481  1.264.4.54     skrll 	for (i = 0; i < npoll; i++)
   3482  1.264.4.33     skrll 		uhci_add_intr(sc, upipe->intr.qhs[i]);
   3483       1.248       mrg 	mutex_exit(&sc->sc_lock);
   3484         1.1  augustss 
   3485  1.264.4.21     skrll 	DPRINTFN(5, "returns %p", upipe, 0, 0, 0);
   3486  1.264.4.21     skrll 
   3487  1.264.4.13     skrll 	return USBD_NORMAL_COMPLETION;
   3488         1.1  augustss }
   3489         1.1  augustss 
   3490         1.1  augustss /* Open a new pipe. */
   3491         1.1  augustss usbd_status
   3492  1.264.4.25     skrll uhci_open(struct usbd_pipe *pipe)
   3493         1.1  augustss {
   3494  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
   3495  1.264.4.12     skrll 	struct usbd_bus *bus = pipe->up_dev->ud_bus;
   3496  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
   3497   1.264.4.7     skrll 	usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc;
   3498       1.248       mrg 	usbd_status err = USBD_NOMEM;
   3499        1.79  augustss 	int ival;
   3500         1.1  augustss 
   3501  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3502  1.264.4.27     skrll 	DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)",
   3503  1.264.4.21     skrll 	    pipe, pipe->up_dev->ud_addr, ed->bEndpointAddress, bus->ub_rhaddr);
   3504        1.92  augustss 
   3505       1.248       mrg 	if (sc->sc_dying)
   3506       1.248       mrg 		return USBD_IOERROR;
   3507       1.248       mrg 
   3508        1.92  augustss 	upipe->aborting = 0;
   3509       1.236  drochner 	/* toggle state needed for bulk endpoints */
   3510   1.264.4.7     skrll 	upipe->nexttoggle = pipe->up_endpoint->ue_toggle;
   3511        1.92  augustss 
   3512  1.264.4.12     skrll 	if (pipe->up_dev->ud_addr == bus->ub_rhaddr) {
   3513         1.1  augustss 		switch (ed->bEndpointAddress) {
   3514         1.1  augustss 		case USB_CONTROL_ENDPOINT:
   3515  1.264.4.12     skrll 			pipe->up_methods = &roothub_ctrl_methods;
   3516         1.1  augustss 			break;
   3517  1.264.4.12     skrll 		case UE_DIR_IN | USBROOTHUB_INTR_ENDPT:
   3518   1.264.4.7     skrll 			pipe->up_methods = &uhci_root_intr_methods;
   3519         1.1  augustss 			break;
   3520         1.1  augustss 		default:
   3521  1.264.4.13     skrll 			return USBD_INVAL;
   3522         1.1  augustss 		}
   3523         1.1  augustss 	} else {
   3524         1.1  augustss 		switch (ed->bmAttributes & UE_XFERTYPE) {
   3525         1.1  augustss 		case UE_CONTROL:
   3526   1.264.4.7     skrll 			pipe->up_methods = &uhci_device_ctrl_methods;
   3527  1.264.4.33     skrll 			upipe->ctrl.sqh = uhci_alloc_sqh(sc);
   3528  1.264.4.33     skrll 			if (upipe->ctrl.sqh == NULL)
   3529         1.5  augustss 				goto bad;
   3530  1.264.4.33     skrll 			upipe->ctrl.setup = uhci_alloc_std(sc);
   3531  1.264.4.33     skrll 			if (upipe->ctrl.setup == NULL) {
   3532  1.264.4.33     skrll 				uhci_free_sqh(sc, upipe->ctrl.sqh);
   3533         1.5  augustss 				goto bad;
   3534         1.5  augustss 			}
   3535  1.264.4.33     skrll 			upipe->ctrl.stat = uhci_alloc_std(sc);
   3536  1.264.4.33     skrll 			if (upipe->ctrl.stat == NULL) {
   3537  1.264.4.33     skrll 				uhci_free_sqh(sc, upipe->ctrl.sqh);
   3538  1.264.4.33     skrll 				uhci_free_std(sc, upipe->ctrl.setup);
   3539         1.5  augustss 				goto bad;
   3540         1.5  augustss 			}
   3541       1.152  augustss 			err = usb_allocmem(&sc->sc_bus,
   3542       1.152  augustss 				  sizeof(usb_device_request_t),
   3543  1.264.4.33     skrll 				  0, &upipe->ctrl.reqdma);
   3544        1.63  augustss 			if (err) {
   3545  1.264.4.33     skrll 				uhci_free_sqh(sc, upipe->ctrl.sqh);
   3546  1.264.4.33     skrll 				uhci_free_std(sc, upipe->ctrl.setup);
   3547  1.264.4.33     skrll 				uhci_free_std(sc, upipe->ctrl.stat);
   3548         1.5  augustss 				goto bad;
   3549         1.5  augustss 			}
   3550         1.1  augustss 			break;
   3551         1.1  augustss 		case UE_INTERRUPT:
   3552   1.264.4.7     skrll 			pipe->up_methods = &uhci_device_intr_methods;
   3553   1.264.4.7     skrll 			ival = pipe->up_interval;
   3554        1.79  augustss 			if (ival == USBD_DEFAULT_INTERVAL)
   3555        1.79  augustss 				ival = ed->bInterval;
   3556  1.264.4.13     skrll 			return uhci_device_setintr(sc, upipe, ival);
   3557         1.1  augustss 		case UE_ISOCHRONOUS:
   3558  1.264.4.68     skrll 			pipe->up_serialise = false;
   3559   1.264.4.7     skrll 			pipe->up_methods = &uhci_device_isoc_methods;
   3560  1.264.4.13     skrll 			return uhci_setup_isoc(pipe);
   3561         1.1  augustss 		case UE_BULK:
   3562   1.264.4.7     skrll 			pipe->up_methods = &uhci_device_bulk_methods;
   3563  1.264.4.33     skrll 			upipe->bulk.sqh = uhci_alloc_sqh(sc);
   3564  1.264.4.33     skrll 			if (upipe->bulk.sqh == NULL)
   3565         1.5  augustss 				goto bad;
   3566         1.1  augustss 			break;
   3567         1.1  augustss 		}
   3568         1.1  augustss 	}
   3569  1.264.4.13     skrll 	return USBD_NORMAL_COMPLETION;
   3570         1.5  augustss 
   3571         1.5  augustss  bad:
   3572       1.248       mrg 	return USBD_NOMEM;
   3573         1.1  augustss }
   3574         1.1  augustss 
   3575         1.1  augustss /*
   3576         1.1  augustss  * Data structures and routines to emulate the root hub.
   3577         1.1  augustss  */
   3578         1.1  augustss /*
   3579       1.166   dsainty  * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also
   3580       1.166   dsainty  * enables the port, and also states that SET_FEATURE(PORT_ENABLE)
   3581       1.166   dsainty  * should not be used by the USB subsystem.  As we cannot issue a
   3582       1.166   dsainty  * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port
   3583       1.166   dsainty  * will be enabled as part of the reset.
   3584       1.166   dsainty  *
   3585       1.166   dsainty  * On the VT83C572, the port cannot be successfully enabled until the
   3586       1.166   dsainty  * outstanding "port enable change" and "connection status change"
   3587       1.166   dsainty  * events have been reset.
   3588       1.166   dsainty  */
   3589       1.166   dsainty Static usbd_status
   3590       1.166   dsainty uhci_portreset(uhci_softc_t *sc, int index)
   3591       1.166   dsainty {
   3592       1.166   dsainty 	int lim, port, x;
   3593  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3594       1.166   dsainty 
   3595       1.166   dsainty 	if (index == 1)
   3596       1.166   dsainty 		port = UHCI_PORTSC1;
   3597       1.166   dsainty 	else if (index == 2)
   3598       1.166   dsainty 		port = UHCI_PORTSC2;
   3599       1.166   dsainty 	else
   3600  1.264.4.13     skrll 		return USBD_IOERROR;
   3601       1.166   dsainty 
   3602       1.166   dsainty 	x = URWMASK(UREAD2(sc, port));
   3603       1.166   dsainty 	UWRITE2(sc, port, x | UHCI_PORTSC_PR);
   3604       1.166   dsainty 
   3605       1.166   dsainty 	usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY);
   3606       1.166   dsainty 
   3607  1.264.4.27     skrll 	DPRINTF("uhci port %d reset, status0 = 0x%04x", index,
   3608  1.264.4.21     skrll 	    UREAD2(sc, port), 0, 0);
   3609       1.166   dsainty 
   3610       1.166   dsainty 	x = URWMASK(UREAD2(sc, port));
   3611       1.222  drochner 	UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP));
   3612       1.166   dsainty 
   3613       1.166   dsainty 	delay(100);
   3614       1.166   dsainty 
   3615  1.264.4.27     skrll 	DPRINTF("uhci port %d reset, status1 = 0x%04x", index,
   3616  1.264.4.21     skrll 	    UREAD2(sc, port), 0, 0);
   3617       1.166   dsainty 
   3618       1.166   dsainty 	x = URWMASK(UREAD2(sc, port));
   3619       1.166   dsainty 	UWRITE2(sc, port, x  | UHCI_PORTSC_PE);
   3620       1.166   dsainty 
   3621       1.166   dsainty 	for (lim = 10; --lim > 0;) {
   3622       1.166   dsainty 		usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY);
   3623       1.166   dsainty 
   3624       1.166   dsainty 		x = UREAD2(sc, port);
   3625  1.264.4.27     skrll 		DPRINTF("uhci port %d iteration %u, status = 0x%04x", index,
   3626  1.264.4.21     skrll 		    lim, x, 0);
   3627       1.166   dsainty 
   3628       1.166   dsainty 		if (!(x & UHCI_PORTSC_CCS)) {
   3629       1.166   dsainty 			/*
   3630       1.166   dsainty 			 * No device is connected (or was disconnected
   3631       1.166   dsainty 			 * during reset).  Consider the port reset.
   3632       1.166   dsainty 			 * The delay must be long enough to ensure on
   3633       1.166   dsainty 			 * the initial iteration that the device
   3634       1.166   dsainty 			 * connection will have been registered.  50ms
   3635       1.166   dsainty 			 * appears to be sufficient, but 20ms is not.
   3636       1.166   dsainty 			 */
   3637  1.264.4.21     skrll 			DPRINTFN(3, "uhci port %d loop %u, device detached",
   3638  1.264.4.21     skrll 			    index, lim, 0, 0);
   3639       1.166   dsainty 			break;
   3640       1.166   dsainty 		}
   3641       1.166   dsainty 
   3642       1.166   dsainty 		if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) {
   3643       1.166   dsainty 			/*
   3644       1.166   dsainty 			 * Port enabled changed and/or connection
   3645       1.166   dsainty 			 * status changed were set.  Reset either or
   3646       1.166   dsainty 			 * both raised flags (by writing a 1 to that
   3647       1.166   dsainty 			 * bit), and wait again for state to settle.
   3648       1.166   dsainty 			 */
   3649       1.166   dsainty 			UWRITE2(sc, port, URWMASK(x) |
   3650       1.166   dsainty 				(x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)));
   3651       1.166   dsainty 			continue;
   3652       1.166   dsainty 		}
   3653       1.166   dsainty 
   3654       1.166   dsainty 		if (x & UHCI_PORTSC_PE)
   3655       1.166   dsainty 			/* Port is enabled */
   3656       1.166   dsainty 			break;
   3657       1.166   dsainty 
   3658       1.166   dsainty 		UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE);
   3659       1.166   dsainty 	}
   3660       1.166   dsainty 
   3661  1.264.4.21     skrll 	DPRINTFN(3, "uhci port %d reset, status2 = 0x%04x", index,
   3662  1.264.4.21     skrll 	    UREAD2(sc, port), 0, 0);
   3663       1.166   dsainty 
   3664       1.166   dsainty 	if (lim <= 0) {
   3665  1.264.4.27     skrll 		DPRINTF("uhci port %d reset timed out", index,
   3666  1.264.4.21     skrll 		    0, 0, 0);
   3667  1.264.4.13     skrll 		return USBD_TIMEOUT;
   3668       1.166   dsainty 	}
   3669       1.184     perry 
   3670       1.166   dsainty 	sc->sc_isreset = 1;
   3671  1.264.4.13     skrll 	return USBD_NORMAL_COMPLETION;
   3672       1.166   dsainty }
   3673       1.166   dsainty 
   3674  1.264.4.12     skrll Static int
   3675  1.264.4.12     skrll uhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req,
   3676  1.264.4.12     skrll     void *buf, int buflen)
   3677         1.1  augustss {
   3678  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_BUS2SC(bus);
   3679         1.1  augustss 	int port, x;
   3680  1.264.4.12     skrll 	int status, change, totlen = 0;
   3681  1.264.4.12     skrll 	uint16_t len, value, index;
   3682         1.1  augustss 	usb_port_status_t ps;
   3683        1.63  augustss 	usbd_status err;
   3684         1.1  augustss 
   3685  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3686  1.264.4.21     skrll 
   3687        1.82  augustss 	if (sc->sc_dying)
   3688  1.264.4.12     skrll 		return -1;
   3689         1.1  augustss 
   3690  1.264.4.27     skrll 	DPRINTF("type=0x%02x request=%02x", req->bmRequestType,
   3691  1.264.4.21     skrll 	    req->bRequest, 0, 0);
   3692         1.1  augustss 
   3693         1.1  augustss 	len = UGETW(req->wLength);
   3694         1.1  augustss 	value = UGETW(req->wValue);
   3695         1.1  augustss 	index = UGETW(req->wIndex);
   3696        1.49  augustss 
   3697         1.1  augustss #define C(x,y) ((x) | ((y) << 8))
   3698  1.264.4.12     skrll 	switch (C(req->bRequest, req->bmRequestType)) {
   3699         1.1  augustss 	case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
   3700  1.264.4.27     skrll 		DPRINTF("wValue=0x%04x", value, 0, 0, 0);
   3701       1.195  christos 		if (len == 0)
   3702       1.195  christos 			break;
   3703  1.264.4.12     skrll 		switch (value) {
   3704  1.264.4.12     skrll 		case C(0, UDESC_DEVICE): {
   3705  1.264.4.12     skrll 			usb_device_descriptor_t devd;
   3706  1.264.4.12     skrll 
   3707  1.264.4.12     skrll 			totlen = min(buflen, sizeof(devd));
   3708  1.264.4.12     skrll 			memcpy(&devd, buf, totlen);
   3709  1.264.4.12     skrll 			USETW(devd.idVendor, sc->sc_id_vendor);
   3710  1.264.4.12     skrll 			memcpy(buf, &devd, totlen);
   3711         1.1  augustss 			break;
   3712  1.264.4.12     skrll 		}
   3713  1.264.4.12     skrll 		case C(1, UDESC_STRING):
   3714       1.213  drochner #define sd ((usb_string_descriptor_t *)buf)
   3715  1.264.4.12     skrll 			/* Vendor */
   3716  1.264.4.12     skrll 			totlen = usb_makestrdesc(sd, len, sc->sc_vendor);
   3717  1.264.4.12     skrll 			break;
   3718  1.264.4.12     skrll 		case C(2, UDESC_STRING):
   3719  1.264.4.12     skrll 			/* Product */
   3720  1.264.4.12     skrll 			totlen = usb_makestrdesc(sd, len, "UHCI root hub");
   3721         1.1  augustss 			break;
   3722  1.264.4.12     skrll #undef sd
   3723         1.1  augustss 		default:
   3724  1.264.4.12     skrll 			/* default from usbroothub */
   3725  1.264.4.12     skrll 			return buflen;
   3726         1.1  augustss 		}
   3727         1.1  augustss 		break;
   3728  1.264.4.12     skrll 
   3729         1.1  augustss 	/* Hub requests */
   3730         1.1  augustss 	case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
   3731         1.1  augustss 		break;
   3732         1.1  augustss 	case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
   3733  1.264.4.27     skrll 		DPRINTF("UR_CLEAR_PORT_FEATURE port=%d feature=%d", index,
   3734  1.264.4.21     skrll 		    value, 0, 0);
   3735         1.1  augustss 		if (index == 1)
   3736         1.1  augustss 			port = UHCI_PORTSC1;
   3737         1.1  augustss 		else if (index == 2)
   3738         1.1  augustss 			port = UHCI_PORTSC2;
   3739         1.1  augustss 		else {
   3740  1.264.4.12     skrll 			return -1;
   3741         1.1  augustss 		}
   3742         1.1  augustss 		switch(value) {
   3743         1.1  augustss 		case UHF_PORT_ENABLE:
   3744       1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3745         1.1  augustss 			UWRITE2(sc, port, x & ~UHCI_PORTSC_PE);
   3746         1.1  augustss 			break;
   3747         1.1  augustss 		case UHF_PORT_SUSPEND:
   3748       1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3749       1.222  drochner 			if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */
   3750       1.222  drochner 				break;
   3751       1.222  drochner 			UWRITE2(sc, port, x | UHCI_PORTSC_RD);
   3752       1.222  drochner 			/* see USB2 spec ch. 7.1.7.7 */
   3753       1.222  drochner 			usb_delay_ms(&sc->sc_bus, 20);
   3754         1.1  augustss 			UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP);
   3755       1.222  drochner 			/* 10ms resume delay must be provided by caller */
   3756         1.1  augustss 			break;
   3757         1.1  augustss 		case UHF_PORT_RESET:
   3758       1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3759         1.1  augustss 			UWRITE2(sc, port, x & ~UHCI_PORTSC_PR);
   3760         1.1  augustss 			break;
   3761         1.1  augustss 		case UHF_C_PORT_CONNECTION:
   3762       1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3763         1.1  augustss 			UWRITE2(sc, port, x | UHCI_PORTSC_CSC);
   3764         1.1  augustss 			break;
   3765         1.1  augustss 		case UHF_C_PORT_ENABLE:
   3766       1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3767         1.1  augustss 			UWRITE2(sc, port, x | UHCI_PORTSC_POEDC);
   3768         1.1  augustss 			break;
   3769         1.1  augustss 		case UHF_C_PORT_OVER_CURRENT:
   3770       1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3771         1.1  augustss 			UWRITE2(sc, port, x | UHCI_PORTSC_OCIC);
   3772         1.1  augustss 			break;
   3773         1.1  augustss 		case UHF_C_PORT_RESET:
   3774         1.1  augustss 			sc->sc_isreset = 0;
   3775  1.264.4.16     skrll 			break;
   3776         1.1  augustss 		case UHF_PORT_CONNECTION:
   3777         1.1  augustss 		case UHF_PORT_OVER_CURRENT:
   3778         1.1  augustss 		case UHF_PORT_POWER:
   3779         1.1  augustss 		case UHF_PORT_LOW_SPEED:
   3780         1.1  augustss 		case UHF_C_PORT_SUSPEND:
   3781         1.1  augustss 		default:
   3782  1.264.4.12     skrll 			return -1;
   3783         1.1  augustss 		}
   3784         1.1  augustss 		break;
   3785         1.1  augustss 	case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER):
   3786         1.1  augustss 		if (index == 1)
   3787         1.1  augustss 			port = UHCI_PORTSC1;
   3788         1.1  augustss 		else if (index == 2)
   3789         1.1  augustss 			port = UHCI_PORTSC2;
   3790         1.1  augustss 		else {
   3791  1.264.4.12     skrll 			return -1;
   3792         1.1  augustss 		}
   3793         1.1  augustss 		if (len > 0) {
   3794   1.264.4.1     skrll 			*(uint8_t *)buf =
   3795  1.264.4.69     skrll 			    UHCI_PORTSC_GET_LS(UREAD2(sc, port));
   3796         1.1  augustss 			totlen = 1;
   3797         1.1  augustss 		}
   3798         1.1  augustss 		break;
   3799         1.1  augustss 	case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
   3800       1.195  christos 		if (len == 0)
   3801       1.195  christos 			break;
   3802       1.177    toshii 		if ((value & 0xff) != 0) {
   3803  1.264.4.12     skrll 			return -1;
   3804         1.1  augustss 		}
   3805  1.264.4.12     skrll 		usb_hub_descriptor_t hubd;
   3806  1.264.4.12     skrll 
   3807  1.264.4.12     skrll 		totlen = min(buflen, sizeof(hubd));
   3808  1.264.4.12     skrll 		memcpy(&hubd, buf, totlen);
   3809  1.264.4.12     skrll 		hubd.bNbrPorts = 2;
   3810  1.264.4.12     skrll 		memcpy(buf, &hubd, totlen);
   3811         1.1  augustss 		break;
   3812         1.1  augustss 	case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
   3813         1.1  augustss 		if (len != 4) {
   3814  1.264.4.12     skrll 			return -1;
   3815         1.1  augustss 		}
   3816         1.1  augustss 		memset(buf, 0, len);
   3817         1.1  augustss 		totlen = len;
   3818         1.1  augustss 		break;
   3819         1.1  augustss 	case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
   3820         1.1  augustss 		if (index == 1)
   3821         1.1  augustss 			port = UHCI_PORTSC1;
   3822         1.1  augustss 		else if (index == 2)
   3823         1.1  augustss 			port = UHCI_PORTSC2;
   3824         1.1  augustss 		else {
   3825  1.264.4.12     skrll 			return -1;
   3826         1.1  augustss 		}
   3827         1.1  augustss 		if (len != 4) {
   3828  1.264.4.12     skrll 			return -1;
   3829         1.1  augustss 		}
   3830         1.1  augustss 		x = UREAD2(sc, port);
   3831         1.1  augustss 		status = change = 0;
   3832       1.142  augustss 		if (x & UHCI_PORTSC_CCS)
   3833         1.1  augustss 			status |= UPS_CURRENT_CONNECT_STATUS;
   3834       1.152  augustss 		if (x & UHCI_PORTSC_CSC)
   3835         1.1  augustss 			change |= UPS_C_CONNECT_STATUS;
   3836       1.152  augustss 		if (x & UHCI_PORTSC_PE)
   3837         1.1  augustss 			status |= UPS_PORT_ENABLED;
   3838       1.152  augustss 		if (x & UHCI_PORTSC_POEDC)
   3839         1.1  augustss 			change |= UPS_C_PORT_ENABLED;
   3840       1.152  augustss 		if (x & UHCI_PORTSC_OCI)
   3841         1.1  augustss 			status |= UPS_OVERCURRENT_INDICATOR;
   3842       1.152  augustss 		if (x & UHCI_PORTSC_OCIC)
   3843         1.1  augustss 			change |= UPS_C_OVERCURRENT_INDICATOR;
   3844       1.152  augustss 		if (x & UHCI_PORTSC_SUSP)
   3845         1.1  augustss 			status |= UPS_SUSPEND;
   3846       1.152  augustss 		if (x & UHCI_PORTSC_LSDA)
   3847         1.1  augustss 			status |= UPS_LOW_SPEED;
   3848         1.1  augustss 		status |= UPS_PORT_POWER;
   3849         1.1  augustss 		if (sc->sc_isreset)
   3850         1.1  augustss 			change |= UPS_C_PORT_RESET;
   3851         1.1  augustss 		USETW(ps.wPortStatus, status);
   3852         1.1  augustss 		USETW(ps.wPortChange, change);
   3853  1.264.4.12     skrll 		totlen = min(len, sizeof(ps));
   3854  1.264.4.12     skrll 		memcpy(buf, &ps, totlen);
   3855         1.1  augustss 		break;
   3856         1.1  augustss 	case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
   3857  1.264.4.12     skrll 		return -1;
   3858         1.1  augustss 	case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
   3859         1.1  augustss 		break;
   3860         1.1  augustss 	case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
   3861         1.1  augustss 		if (index == 1)
   3862         1.1  augustss 			port = UHCI_PORTSC1;
   3863         1.1  augustss 		else if (index == 2)
   3864         1.1  augustss 			port = UHCI_PORTSC2;
   3865         1.1  augustss 		else {
   3866  1.264.4.12     skrll 			return -1;
   3867         1.1  augustss 		}
   3868         1.1  augustss 		switch(value) {
   3869         1.1  augustss 		case UHF_PORT_ENABLE:
   3870       1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3871         1.1  augustss 			UWRITE2(sc, port, x | UHCI_PORTSC_PE);
   3872         1.1  augustss 			break;
   3873         1.1  augustss 		case UHF_PORT_SUSPEND:
   3874       1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3875         1.1  augustss 			UWRITE2(sc, port, x | UHCI_PORTSC_SUSP);
   3876         1.1  augustss 			break;
   3877         1.1  augustss 		case UHF_PORT_RESET:
   3878       1.166   dsainty 			err = uhci_portreset(sc, index);
   3879  1.264.4.12     skrll 			if (err != USBD_NORMAL_COMPLETION)
   3880  1.264.4.12     skrll 				return -1;
   3881  1.264.4.12     skrll 			return 0;
   3882       1.111  augustss 		case UHF_PORT_POWER:
   3883       1.111  augustss 			/* Pretend we turned on power */
   3884  1.264.4.12     skrll 			return 0;
   3885         1.1  augustss 		case UHF_C_PORT_CONNECTION:
   3886         1.1  augustss 		case UHF_C_PORT_ENABLE:
   3887         1.1  augustss 		case UHF_C_PORT_OVER_CURRENT:
   3888         1.1  augustss 		case UHF_PORT_CONNECTION:
   3889         1.1  augustss 		case UHF_PORT_OVER_CURRENT:
   3890         1.1  augustss 		case UHF_PORT_LOW_SPEED:
   3891         1.1  augustss 		case UHF_C_PORT_SUSPEND:
   3892         1.1  augustss 		case UHF_C_PORT_RESET:
   3893         1.1  augustss 		default:
   3894  1.264.4.12     skrll 			return -1;
   3895         1.1  augustss 		}
   3896         1.1  augustss 		break;
   3897         1.1  augustss 	default:
   3898  1.264.4.12     skrll 		/* default from usbroothub */
   3899  1.264.4.27     skrll 		DPRINTF("returning %d (usbroothub default)",
   3900  1.264.4.21     skrll 		    buflen, 0, 0, 0);
   3901  1.264.4.12     skrll 		return buflen;
   3902         1.1  augustss 	}
   3903         1.1  augustss 
   3904  1.264.4.27     skrll 	DPRINTF("returning %d", totlen, 0, 0, 0);
   3905  1.264.4.21     skrll 
   3906  1.264.4.12     skrll 	return totlen;
   3907         1.1  augustss }
   3908         1.1  augustss 
   3909         1.1  augustss /* Abort a root interrupt request. */
   3910         1.1  augustss void
   3911  1.264.4.25     skrll uhci_root_intr_abort(struct usbd_xfer *xfer)
   3912         1.1  augustss {
   3913  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   3914        1.30  augustss 
   3915       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   3916   1.264.4.7     skrll 	KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
   3917       1.248       mrg 
   3918       1.234    dyoung 	callout_stop(&sc->sc_poll_handle);
   3919        1.96  augustss 	sc->sc_intr_xfer = NULL;
   3920        1.58  augustss 
   3921   1.264.4.7     skrll 	xfer->ux_status = USBD_CANCELLED;
   3922        1.96  augustss #ifdef DIAGNOSTIC
   3923  1.264.4.41     skrll 	UHCI_XFER2UXFER(xfer)->ux_isdone = true;
   3924        1.96  augustss #endif
   3925        1.63  augustss 	usb_transfer_complete(xfer);
   3926         1.1  augustss }
   3927         1.1  augustss 
   3928        1.16  augustss usbd_status
   3929  1.264.4.25     skrll uhci_root_intr_transfer(struct usbd_xfer *xfer)
   3930        1.16  augustss {
   3931  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   3932        1.63  augustss 	usbd_status err;
   3933        1.16  augustss 
   3934        1.52  augustss 	/* Insert last in queue. */
   3935       1.248       mrg 	mutex_enter(&sc->sc_lock);
   3936        1.63  augustss 	err = usb_insert_transfer(xfer);
   3937       1.248       mrg 	mutex_exit(&sc->sc_lock);
   3938        1.63  augustss 	if (err)
   3939  1.264.4.13     skrll 		return err;
   3940        1.52  augustss 
   3941       1.186     skrll 	/*
   3942       1.186     skrll 	 * Pipe isn't running (otherwise err would be USBD_INPROG),
   3943        1.67  augustss 	 * start first
   3944        1.67  augustss 	 */
   3945  1.264.4.13     skrll 	return uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
   3946        1.16  augustss }
   3947        1.16  augustss 
   3948         1.1  augustss /* Start a transfer on the root interrupt pipe */
   3949         1.1  augustss usbd_status
   3950  1.264.4.25     skrll uhci_root_intr_start(struct usbd_xfer *xfer)
   3951         1.1  augustss {
   3952  1.264.4.25     skrll 	struct usbd_pipe *pipe = xfer->ux_pipe;
   3953  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
   3954       1.174  drochner 	unsigned int ival;
   3955         1.1  augustss 
   3956  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3957  1.264.4.27     skrll 	DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length,
   3958  1.264.4.21     skrll 	    xfer->ux_flags, 0);
   3959        1.82  augustss 
   3960        1.82  augustss 	if (sc->sc_dying)
   3961  1.264.4.13     skrll 		return USBD_IOERROR;
   3962         1.1  augustss 
   3963       1.174  drochner 	/* XXX temporary variable needed to avoid gcc3 warning */
   3964   1.264.4.7     skrll 	ival = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval;
   3965       1.174  drochner 	sc->sc_ival = mstohz(ival);
   3966       1.234    dyoung 	callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer);
   3967        1.96  augustss 	sc->sc_intr_xfer = xfer;
   3968  1.264.4.13     skrll 	return USBD_IN_PROGRESS;
   3969         1.1  augustss }
   3970         1.1  augustss 
   3971         1.1  augustss /* Close the root interrupt pipe. */
   3972         1.1  augustss void
   3973  1.264.4.25     skrll uhci_root_intr_close(struct usbd_pipe *pipe)
   3974         1.1  augustss {
   3975  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
   3976  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3977        1.30  augustss 
   3978       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   3979       1.248       mrg 
   3980       1.234    dyoung 	callout_stop(&sc->sc_poll_handle);
   3981        1.96  augustss 	sc->sc_intr_xfer = NULL;
   3982         1.1  augustss }
   3983