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uhci.c revision 1.264.4.80
      1  1.264.4.80     skrll /*	$NetBSD: uhci.c,v 1.264.4.80 2017/08/28 17:52:28 skrll Exp $	*/
      2         1.1  augustss 
      3         1.1  augustss /*
      4       1.248       mrg  * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc.
      5         1.1  augustss  * All rights reserved.
      6         1.1  augustss  *
      7        1.11  augustss  * This code is derived from software contributed to The NetBSD Foundation
      8       1.113  augustss  * by Lennart Augustsson (lennart (at) augustsson.net) at
      9       1.248       mrg  * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca)
     10       1.248       mrg  * and Matthew R. Green (mrg (at) eterna.com.au).
     11         1.1  augustss  *
     12         1.1  augustss  * Redistribution and use in source and binary forms, with or without
     13         1.1  augustss  * modification, are permitted provided that the following conditions
     14         1.1  augustss  * are met:
     15         1.1  augustss  * 1. Redistributions of source code must retain the above copyright
     16         1.1  augustss  *    notice, this list of conditions and the following disclaimer.
     17         1.1  augustss  * 2. Redistributions in binary form must reproduce the above copyright
     18         1.1  augustss  *    notice, this list of conditions and the following disclaimer in the
     19         1.1  augustss  *    documentation and/or other materials provided with the distribution.
     20         1.1  augustss  *
     21         1.1  augustss  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     22         1.1  augustss  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     23         1.1  augustss  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     24         1.1  augustss  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     25         1.1  augustss  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     26         1.1  augustss  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     27         1.1  augustss  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     28         1.1  augustss  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     29         1.1  augustss  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     30         1.1  augustss  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     31         1.1  augustss  * POSSIBILITY OF SUCH DAMAGE.
     32         1.1  augustss  */
     33         1.1  augustss 
     34         1.1  augustss /*
     35         1.1  augustss  * USB Universal Host Controller driver.
     36        1.28  augustss  * Handles e.g. PIIX3 and PIIX4.
     37         1.1  augustss  *
     38       1.229  uebayasi  * UHCI spec: http://www.intel.com/technology/usb/spec.htm
     39       1.229  uebayasi  * USB spec: http://www.usb.org/developers/docs/
     40        1.71  augustss  * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf
     41        1.71  augustss  *             ftp://download.intel.com/design/intarch/datashts/29056201.pdf
     42         1.1  augustss  */
     43       1.143     lukem 
     44       1.143     lukem #include <sys/cdefs.h>
     45  1.264.4.80     skrll __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.264.4.80 2017/08/28 17:52:28 skrll Exp $");
     46  1.264.4.30     skrll 
     47  1.264.4.76     skrll #ifdef _KERNEL_OPT
     48  1.264.4.30     skrll #include "opt_usb.h"
     49  1.264.4.76     skrll #endif
     50         1.1  augustss 
     51         1.1  augustss #include <sys/param.h>
     52  1.264.4.20     skrll 
     53  1.264.4.20     skrll #include <sys/bus.h>
     54  1.264.4.20     skrll #include <sys/cpu.h>
     55  1.264.4.20     skrll #include <sys/device.h>
     56         1.1  augustss #include <sys/kernel.h>
     57       1.248       mrg #include <sys/kmem.h>
     58  1.264.4.20     skrll #include <sys/mutex.h>
     59         1.1  augustss #include <sys/proc.h>
     60         1.1  augustss #include <sys/queue.h>
     61  1.264.4.20     skrll #include <sys/select.h>
     62  1.264.4.20     skrll #include <sys/sysctl.h>
     63  1.264.4.20     skrll #include <sys/systm.h>
     64         1.1  augustss 
     65        1.39  augustss #include <machine/endian.h>
     66         1.7  augustss 
     67         1.1  augustss #include <dev/usb/usb.h>
     68         1.1  augustss #include <dev/usb/usbdi.h>
     69         1.1  augustss #include <dev/usb/usbdivar.h>
     70         1.7  augustss #include <dev/usb/usb_mem.h>
     71         1.1  augustss 
     72         1.1  augustss #include <dev/usb/uhcireg.h>
     73         1.1  augustss #include <dev/usb/uhcivar.h>
     74  1.264.4.11     skrll #include <dev/usb/usbroothub.h>
     75  1.264.4.21     skrll #include <dev/usb/usbhist.h>
     76         1.1  augustss 
     77       1.125  augustss /* Use bandwidth reclamation for control transfers. Some devices choke on it. */
     78       1.125  augustss /*#define UHCI_CTL_LOOP */
     79       1.125  augustss 
     80        1.67  augustss #ifdef UHCI_DEBUG
     81        1.92  augustss uhci_softc_t *thesc;
     82       1.125  augustss int uhcinoloop = 0;
     83        1.59  augustss #endif
     84        1.59  augustss 
     85  1.264.4.21     skrll #ifdef USB_DEBUG
     86  1.264.4.21     skrll #ifndef UHCI_DEBUG
     87  1.264.4.21     skrll #define uhcidebug 0
     88  1.264.4.21     skrll #else
     89  1.264.4.21     skrll static int uhcidebug = 0;
     90  1.264.4.21     skrll 
     91  1.264.4.21     skrll SYSCTL_SETUP(sysctl_hw_uhci_setup, "sysctl hw.uhci setup")
     92  1.264.4.21     skrll {
     93  1.264.4.21     skrll 	int err;
     94  1.264.4.21     skrll 	const struct sysctlnode *rnode;
     95  1.264.4.21     skrll 	const struct sysctlnode *cnode;
     96  1.264.4.21     skrll 
     97  1.264.4.21     skrll 	err = sysctl_createv(clog, 0, NULL, &rnode,
     98  1.264.4.21     skrll 	    CTLFLAG_PERMANENT, CTLTYPE_NODE, "uhci",
     99  1.264.4.21     skrll 	    SYSCTL_DESCR("uhci global controls"),
    100  1.264.4.21     skrll 	    NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
    101  1.264.4.21     skrll 
    102  1.264.4.21     skrll 	if (err)
    103  1.264.4.21     skrll 		goto fail;
    104  1.264.4.21     skrll 
    105  1.264.4.21     skrll 	/* control debugging printfs */
    106  1.264.4.21     skrll 	err = sysctl_createv(clog, 0, &rnode, &cnode,
    107  1.264.4.21     skrll 	    CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
    108  1.264.4.21     skrll 	    "debug", SYSCTL_DESCR("Enable debugging output"),
    109  1.264.4.21     skrll 	    NULL, 0, &uhcidebug, sizeof(uhcidebug), CTL_CREATE, CTL_EOL);
    110  1.264.4.21     skrll 	if (err)
    111  1.264.4.21     skrll 		goto fail;
    112  1.264.4.21     skrll 
    113  1.264.4.21     skrll 	return;
    114  1.264.4.21     skrll fail:
    115  1.264.4.21     skrll 	aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err);
    116  1.264.4.21     skrll }
    117  1.264.4.21     skrll 
    118  1.264.4.21     skrll #endif /* UHCI_DEBUG */
    119  1.264.4.21     skrll #endif /* USB_DEBUG */
    120  1.264.4.21     skrll 
    121  1.264.4.27     skrll #define	DPRINTF(FMT,A,B,C,D)	USBHIST_LOGN(uhcidebug,1,FMT,A,B,C,D)
    122  1.264.4.21     skrll #define	DPRINTFN(N,FMT,A,B,C,D)	USBHIST_LOGN(uhcidebug,N,FMT,A,B,C,D)
    123  1.264.4.21     skrll #define	UHCIHIST_FUNC()		USBHIST_FUNC()
    124  1.264.4.21     skrll #define	UHCIHIST_CALLED(name)	USBHIST_CALLED(uhcidebug)
    125  1.264.4.21     skrll 
    126        1.39  augustss /*
    127        1.39  augustss  * The UHCI controller is little endian, so on big endian machines
    128       1.181  drochner  * the data stored in memory needs to be swapped.
    129        1.39  augustss  */
    130        1.39  augustss 
    131         1.1  augustss struct uhci_pipe {
    132         1.1  augustss 	struct usbd_pipe pipe;
    133        1.32  augustss 	int nexttoggle;
    134        1.92  augustss 
    135        1.92  augustss 	u_char aborting;
    136  1.264.4.25     skrll 	struct usbd_xfer *abortstart, abortend;
    137        1.92  augustss 
    138         1.1  augustss 	/* Info needed for different pipe kinds. */
    139         1.1  augustss 	union {
    140         1.1  augustss 		/* Control pipe */
    141         1.1  augustss 		struct {
    142         1.1  augustss 			uhci_soft_qh_t *sqh;
    143         1.7  augustss 			usb_dma_t reqdma;
    144  1.264.4.55     skrll 			uhci_soft_td_t *setup;
    145  1.264.4.55     skrll 			uhci_soft_td_t *stat;
    146  1.264.4.33     skrll 		} ctrl;
    147         1.1  augustss 		/* Interrupt pipe */
    148         1.1  augustss 		struct {
    149         1.1  augustss 			int npoll;
    150         1.1  augustss 			uhci_soft_qh_t **qhs;
    151         1.1  augustss 		} intr;
    152         1.1  augustss 		/* Bulk pipe */
    153         1.1  augustss 		struct {
    154         1.1  augustss 			uhci_soft_qh_t *sqh;
    155         1.1  augustss 		} bulk;
    156  1.264.4.33     skrll 		/* Isochronous pipe */
    157  1.264.4.33     skrll 		struct isoc {
    158        1.16  augustss 			uhci_soft_td_t **stds;
    159        1.48  augustss 			int next, inuse;
    160  1.264.4.33     skrll 		} isoc;
    161  1.264.4.33     skrll 	};
    162         1.1  augustss };
    163         1.1  augustss 
    164  1.264.4.61     skrll typedef TAILQ_HEAD(ux_completeq, uhci_xfer) ux_completeq_t;
    165  1.264.4.61     skrll 
    166       1.142  augustss Static void		uhci_globalreset(uhci_softc_t *);
    167       1.166   dsainty Static usbd_status	uhci_portreset(uhci_softc_t*, int);
    168       1.142  augustss Static void		uhci_reset(uhci_softc_t *);
    169  1.264.4.15     skrll Static usbd_status	uhci_run(uhci_softc_t *, int, int);
    170       1.123  augustss Static uhci_soft_td_t  *uhci_alloc_std(uhci_softc_t *);
    171       1.119  augustss Static void		uhci_free_std(uhci_softc_t *, uhci_soft_td_t *);
    172  1.264.4.55     skrll Static void		uhci_free_std_locked(uhci_softc_t *, uhci_soft_td_t *);
    173       1.123  augustss Static uhci_soft_qh_t  *uhci_alloc_sqh(uhci_softc_t *);
    174       1.119  augustss Static void		uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *);
    175        1.16  augustss #if 0
    176       1.119  augustss Static void		uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *,
    177  1.264.4.48     skrll 			    uhci_intr_info_t *);
    178       1.119  augustss Static void		uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *);
    179        1.16  augustss #endif
    180         1.1  augustss 
    181  1.264.4.72     skrll #if 0
    182  1.264.4.55     skrll Static void		uhci_free_std_chain(uhci_softc_t *, uhci_soft_td_t *,
    183  1.264.4.55     skrll 			    uhci_soft_td_t *);
    184  1.264.4.72     skrll #endif
    185  1.264.4.74     skrll Static int		uhci_alloc_std_chain(uhci_softc_t *, struct usbd_xfer *,
    186  1.264.4.70     skrll 			    int, int, uhci_soft_td_t **);
    187  1.264.4.55     skrll Static void		uhci_free_stds(uhci_softc_t *, struct uhci_xfer *);
    188  1.264.4.55     skrll 
    189  1.264.4.55     skrll Static void		uhci_reset_std_chain(uhci_softc_t *, struct usbd_xfer *,
    190  1.264.4.58     skrll 			    int, int, int *, uhci_soft_td_t **);
    191  1.264.4.55     skrll 
    192       1.119  augustss Static void		uhci_poll_hub(void *);
    193  1.264.4.61     skrll Static void		uhci_check_intr(uhci_softc_t *, struct uhci_xfer *,
    194  1.264.4.61     skrll 			    ux_completeq_t *);
    195  1.264.4.61     skrll Static void		uhci_idone(struct uhci_xfer *, ux_completeq_t *);
    196       1.119  augustss 
    197  1.264.4.25     skrll Static void		uhci_abort_xfer(struct usbd_xfer *, usbd_status);
    198       1.119  augustss 
    199       1.119  augustss Static void		uhci_timeout(void *);
    200       1.153  augustss Static void		uhci_timeout_task(void *);
    201       1.123  augustss Static void		uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *);
    202       1.123  augustss Static void		uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *);
    203       1.119  augustss Static void		uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *);
    204       1.123  augustss Static void		uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *);
    205       1.123  augustss Static void		uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *);
    206       1.119  augustss Static void		uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *);
    207  1.264.4.15     skrll Static void		uhci_add_loop(uhci_softc_t *);
    208  1.264.4.15     skrll Static void		uhci_rem_loop(uhci_softc_t *);
    209       1.119  augustss 
    210  1.264.4.25     skrll Static usbd_status	uhci_setup_isoc(struct usbd_pipe *);
    211       1.119  augustss 
    212  1.264.4.36     skrll Static struct usbd_xfer *
    213  1.264.4.36     skrll 			uhci_allocx(struct usbd_bus *, unsigned int);
    214  1.264.4.25     skrll Static void		uhci_freex(struct usbd_bus *, struct usbd_xfer *);
    215       1.248       mrg Static void		uhci_get_lock(struct usbd_bus *, kmutex_t **);
    216  1.264.4.13     skrll Static int		uhci_roothub_ctrl(struct usbd_bus *,
    217  1.264.4.42     skrll 			    usb_device_request_t *, void *, int);
    218       1.119  augustss 
    219  1.264.4.55     skrll Static int		uhci_device_ctrl_init(struct usbd_xfer *);
    220  1.264.4.55     skrll Static void		uhci_device_ctrl_fini(struct usbd_xfer *);
    221  1.264.4.25     skrll Static usbd_status	uhci_device_ctrl_transfer(struct usbd_xfer *);
    222  1.264.4.25     skrll Static usbd_status	uhci_device_ctrl_start(struct usbd_xfer *);
    223  1.264.4.25     skrll Static void		uhci_device_ctrl_abort(struct usbd_xfer *);
    224  1.264.4.25     skrll Static void		uhci_device_ctrl_close(struct usbd_pipe *);
    225  1.264.4.25     skrll Static void		uhci_device_ctrl_done(struct usbd_xfer *);
    226  1.264.4.25     skrll 
    227  1.264.4.55     skrll Static int		uhci_device_intr_init(struct usbd_xfer *);
    228  1.264.4.55     skrll Static void		uhci_device_intr_fini(struct usbd_xfer *);
    229  1.264.4.25     skrll Static usbd_status	uhci_device_intr_transfer(struct usbd_xfer *);
    230  1.264.4.25     skrll Static usbd_status	uhci_device_intr_start(struct usbd_xfer *);
    231  1.264.4.25     skrll Static void		uhci_device_intr_abort(struct usbd_xfer *);
    232  1.264.4.25     skrll Static void		uhci_device_intr_close(struct usbd_pipe *);
    233  1.264.4.25     skrll Static void		uhci_device_intr_done(struct usbd_xfer *);
    234  1.264.4.25     skrll 
    235  1.264.4.55     skrll Static int		uhci_device_bulk_init(struct usbd_xfer *);
    236  1.264.4.55     skrll Static void		uhci_device_bulk_fini(struct usbd_xfer *);
    237  1.264.4.25     skrll Static usbd_status	uhci_device_bulk_transfer(struct usbd_xfer *);
    238  1.264.4.25     skrll Static usbd_status	uhci_device_bulk_start(struct usbd_xfer *);
    239  1.264.4.25     skrll Static void		uhci_device_bulk_abort(struct usbd_xfer *);
    240  1.264.4.25     skrll Static void		uhci_device_bulk_close(struct usbd_pipe *);
    241  1.264.4.25     skrll Static void		uhci_device_bulk_done(struct usbd_xfer *);
    242  1.264.4.25     skrll 
    243  1.264.4.55     skrll Static int		uhci_device_isoc_init(struct usbd_xfer *);
    244  1.264.4.55     skrll Static void		uhci_device_isoc_fini(struct usbd_xfer *);
    245  1.264.4.25     skrll Static usbd_status	uhci_device_isoc_transfer(struct usbd_xfer *);
    246  1.264.4.25     skrll Static void		uhci_device_isoc_abort(struct usbd_xfer *);
    247  1.264.4.25     skrll Static void		uhci_device_isoc_close(struct usbd_pipe *);
    248  1.264.4.25     skrll Static void		uhci_device_isoc_done(struct usbd_xfer *);
    249  1.264.4.25     skrll 
    250  1.264.4.25     skrll Static usbd_status	uhci_root_intr_transfer(struct usbd_xfer *);
    251  1.264.4.25     skrll Static usbd_status	uhci_root_intr_start(struct usbd_xfer *);
    252  1.264.4.25     skrll Static void		uhci_root_intr_abort(struct usbd_xfer *);
    253  1.264.4.25     skrll Static void		uhci_root_intr_close(struct usbd_pipe *);
    254  1.264.4.25     skrll Static void		uhci_root_intr_done(struct usbd_xfer *);
    255       1.119  augustss 
    256  1.264.4.25     skrll Static usbd_status	uhci_open(struct usbd_pipe *);
    257       1.119  augustss Static void		uhci_poll(struct usbd_bus *);
    258       1.133  augustss Static void		uhci_softintr(void *);
    259       1.119  augustss 
    260       1.119  augustss Static void		uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *);
    261       1.158  augustss Static void		uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *);
    262  1.264.4.15     skrll Static usbd_status	uhci_device_setintr(uhci_softc_t *,
    263  1.264.4.15     skrll 			    struct uhci_pipe *, int);
    264       1.119  augustss 
    265  1.264.4.25     skrll Static void		uhci_device_clear_toggle(struct usbd_pipe *);
    266  1.264.4.25     skrll Static void		uhci_noop(struct usbd_pipe *);
    267       1.119  augustss 
    268  1.264.4.42     skrll static inline uhci_soft_qh_t *
    269  1.264.4.42     skrll 			uhci_find_prev_qh(uhci_soft_qh_t *, uhci_soft_qh_t *);
    270       1.119  augustss 
    271       1.119  augustss #ifdef UHCI_DEBUG
    272       1.119  augustss Static void		uhci_dump_all(uhci_softc_t *);
    273       1.119  augustss Static void		uhci_dumpregs(uhci_softc_t *);
    274       1.119  augustss Static void		uhci_dump_qhs(uhci_soft_qh_t *);
    275       1.119  augustss Static void		uhci_dump_qh(uhci_soft_qh_t *);
    276       1.119  augustss Static void		uhci_dump_tds(uhci_soft_td_t *);
    277       1.119  augustss Static void		uhci_dump_td(uhci_soft_td_t *);
    278  1.264.4.40     skrll Static void		uhci_dump_ii(struct uhci_xfer *);
    279       1.119  augustss void			uhci_dump(void);
    280         1.1  augustss #endif
    281         1.1  augustss 
    282       1.112  augustss #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \
    283       1.112  augustss 			BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
    284       1.112  augustss #define UWRITE1(sc, r, x) \
    285       1.165   dsainty  do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \
    286       1.165   dsainty  } while (/*CONSTCOND*/0)
    287       1.112  augustss #define UWRITE2(sc, r, x) \
    288       1.165   dsainty  do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \
    289       1.165   dsainty  } while (/*CONSTCOND*/0)
    290       1.112  augustss #define UWRITE4(sc, r, x) \
    291       1.165   dsainty  do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \
    292       1.165   dsainty  } while (/*CONSTCOND*/0)
    293  1.264.4.42     skrll 
    294       1.196       mrg static __inline uint8_t
    295       1.196       mrg UREAD1(uhci_softc_t *sc, bus_size_t r)
    296       1.196       mrg {
    297       1.196       mrg 
    298       1.196       mrg 	UBARR(sc);
    299       1.196       mrg 	return bus_space_read_1(sc->iot, sc->ioh, r);
    300       1.196       mrg }
    301       1.196       mrg 
    302       1.196       mrg static __inline uint16_t
    303       1.196       mrg UREAD2(uhci_softc_t *sc, bus_size_t r)
    304       1.196       mrg {
    305       1.196       mrg 
    306       1.196       mrg 	UBARR(sc);
    307       1.196       mrg 	return bus_space_read_2(sc->iot, sc->ioh, r);
    308       1.196       mrg }
    309       1.196       mrg 
    310       1.260     joerg #ifdef UHCI_DEBUG
    311       1.196       mrg static __inline uint32_t
    312       1.196       mrg UREAD4(uhci_softc_t *sc, bus_size_t r)
    313       1.196       mrg {
    314       1.196       mrg 
    315       1.196       mrg 	UBARR(sc);
    316       1.196       mrg 	return bus_space_read_4(sc->iot, sc->ioh, r);
    317       1.196       mrg }
    318       1.260     joerg #endif
    319         1.1  augustss 
    320         1.1  augustss #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd)
    321         1.1  augustss #define UHCISTS(sc) UREAD2(sc, UHCI_STS)
    322         1.1  augustss 
    323       1.142  augustss #define UHCI_RESET_TIMEOUT 100	/* ms, reset timeout */
    324         1.1  augustss 
    325         1.1  augustss #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK)
    326         1.1  augustss 
    327       1.208  drochner const struct usbd_bus_methods uhci_bus_methods = {
    328   1.264.4.5     skrll 	.ubm_open =	uhci_open,
    329   1.264.4.5     skrll 	.ubm_softint =	uhci_softintr,
    330   1.264.4.5     skrll 	.ubm_dopoll =	uhci_poll,
    331   1.264.4.5     skrll 	.ubm_allocx =	uhci_allocx,
    332   1.264.4.5     skrll 	.ubm_freex =	uhci_freex,
    333   1.264.4.5     skrll 	.ubm_getlock =	uhci_get_lock,
    334  1.264.4.12     skrll 	.ubm_rhctrl =	uhci_roothub_ctrl,
    335         1.1  augustss };
    336         1.1  augustss 
    337       1.208  drochner const struct usbd_pipe_methods uhci_root_intr_methods = {
    338   1.264.4.5     skrll 	.upm_transfer =	uhci_root_intr_transfer,
    339   1.264.4.5     skrll 	.upm_start =	uhci_root_intr_start,
    340   1.264.4.5     skrll 	.upm_abort =	uhci_root_intr_abort,
    341   1.264.4.5     skrll 	.upm_close =	uhci_root_intr_close,
    342   1.264.4.5     skrll 	.upm_cleartoggle =	uhci_noop,
    343   1.264.4.5     skrll 	.upm_done =	uhci_root_intr_done,
    344         1.1  augustss };
    345         1.1  augustss 
    346       1.208  drochner const struct usbd_pipe_methods uhci_device_ctrl_methods = {
    347  1.264.4.55     skrll 	.upm_init =	uhci_device_ctrl_init,
    348  1.264.4.55     skrll 	.upm_fini =	uhci_device_ctrl_fini,
    349   1.264.4.5     skrll 	.upm_transfer =	uhci_device_ctrl_transfer,
    350   1.264.4.5     skrll 	.upm_start =	uhci_device_ctrl_start,
    351   1.264.4.5     skrll 	.upm_abort =	uhci_device_ctrl_abort,
    352   1.264.4.5     skrll 	.upm_close =	uhci_device_ctrl_close,
    353   1.264.4.5     skrll 	.upm_cleartoggle =	uhci_noop,
    354   1.264.4.5     skrll 	.upm_done =	uhci_device_ctrl_done,
    355         1.1  augustss };
    356         1.1  augustss 
    357       1.208  drochner const struct usbd_pipe_methods uhci_device_intr_methods = {
    358  1.264.4.55     skrll 	.upm_init =	uhci_device_intr_init,
    359  1.264.4.55     skrll 	.upm_fini =	uhci_device_intr_fini,
    360   1.264.4.5     skrll 	.upm_transfer =	uhci_device_intr_transfer,
    361   1.264.4.5     skrll 	.upm_start =	uhci_device_intr_start,
    362   1.264.4.5     skrll 	.upm_abort =	uhci_device_intr_abort,
    363   1.264.4.5     skrll 	.upm_close =	uhci_device_intr_close,
    364   1.264.4.5     skrll 	.upm_cleartoggle =	uhci_device_clear_toggle,
    365   1.264.4.5     skrll 	.upm_done =	uhci_device_intr_done,
    366         1.1  augustss };
    367         1.1  augustss 
    368       1.208  drochner const struct usbd_pipe_methods uhci_device_bulk_methods = {
    369  1.264.4.55     skrll 	.upm_init =	uhci_device_bulk_init,
    370  1.264.4.55     skrll 	.upm_fini =	uhci_device_bulk_fini,
    371   1.264.4.5     skrll 	.upm_transfer =	uhci_device_bulk_transfer,
    372   1.264.4.5     skrll 	.upm_start =	uhci_device_bulk_start,
    373   1.264.4.5     skrll 	.upm_abort =	uhci_device_bulk_abort,
    374   1.264.4.5     skrll 	.upm_close =	uhci_device_bulk_close,
    375   1.264.4.5     skrll 	.upm_cleartoggle =	uhci_device_clear_toggle,
    376   1.264.4.5     skrll 	.upm_done =	uhci_device_bulk_done,
    377         1.1  augustss };
    378         1.1  augustss 
    379       1.208  drochner const struct usbd_pipe_methods uhci_device_isoc_methods = {
    380  1.264.4.55     skrll 	.upm_init =	uhci_device_isoc_init,
    381  1.264.4.55     skrll 	.upm_fini =	uhci_device_isoc_fini,
    382   1.264.4.5     skrll 	.upm_transfer =	uhci_device_isoc_transfer,
    383   1.264.4.5     skrll 	.upm_abort =	uhci_device_isoc_abort,
    384   1.264.4.5     skrll 	.upm_close =	uhci_device_isoc_close,
    385   1.264.4.5     skrll 	.upm_cleartoggle =	uhci_noop,
    386   1.264.4.5     skrll 	.upm_done =	uhci_device_isoc_done,
    387        1.16  augustss };
    388        1.16  augustss 
    389  1.264.4.61     skrll static inline void
    390  1.264.4.61     skrll uhci_add_intr_list(uhci_softc_t *sc, struct uhci_xfer *ux)
    391  1.264.4.61     skrll {
    392  1.264.4.61     skrll 
    393  1.264.4.61     skrll 	TAILQ_INSERT_TAIL(&sc->sc_intrhead, ux, ux_list);
    394  1.264.4.61     skrll }
    395  1.264.4.61     skrll 
    396  1.264.4.61     skrll static inline void
    397  1.264.4.61     skrll uhci_del_intr_list(uhci_softc_t *sc, struct uhci_xfer *ux)
    398  1.264.4.61     skrll {
    399  1.264.4.61     skrll 
    400  1.264.4.61     skrll 	TAILQ_REMOVE(&sc->sc_intrhead, ux, ux_list);
    401  1.264.4.61     skrll }
    402        1.92  augustss 
    403       1.240  jakllsch static inline uhci_soft_qh_t *
    404       1.119  augustss uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh)
    405        1.92  augustss {
    406  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
    407  1.264.4.21     skrll 	DPRINTFN(15, "pqh=%p sqh=%p", pqh, sqh, 0, 0);
    408        1.92  augustss 
    409        1.92  augustss 	for (; pqh->hlink != sqh; pqh = pqh->hlink) {
    410       1.152  augustss #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG)
    411       1.223    bouyer 		usb_syncmem(&pqh->dma,
    412       1.223    bouyer 		    pqh->offs + offsetof(uhci_qh_t, qh_hlink),
    413       1.223    bouyer 		    sizeof(pqh->qh.qh_hlink),
    414       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE);
    415        1.92  augustss 		if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) {
    416  1.264.4.65     skrll 			printf("%s: QH not found\n", __func__);
    417  1.264.4.13     skrll 			return NULL;
    418        1.92  augustss 		}
    419        1.92  augustss #endif
    420        1.92  augustss 	}
    421  1.264.4.13     skrll 	return pqh;
    422        1.92  augustss }
    423        1.92  augustss 
    424         1.1  augustss void
    425       1.142  augustss uhci_globalreset(uhci_softc_t *sc)
    426         1.1  augustss {
    427         1.1  augustss 	UHCICMD(sc, UHCI_CMD_GRESET);	/* global reset */
    428        1.20  augustss 	usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */
    429         1.1  augustss 	UHCICMD(sc, 0);			/* do nothing */
    430         1.1  augustss }
    431         1.1  augustss 
    432  1.264.4.14     skrll int
    433       1.119  augustss uhci_init(uhci_softc_t *sc)
    434         1.1  augustss {
    435        1.63  augustss 	usbd_status err;
    436         1.1  augustss 	int i, j;
    437       1.123  augustss 	uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh;
    438         1.1  augustss 	uhci_soft_td_t *std;
    439         1.1  augustss 
    440  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
    441         1.1  augustss 
    442        1.67  augustss #ifdef UHCI_DEBUG
    443        1.92  augustss 	thesc = sc;
    444        1.92  augustss 
    445  1.264.4.43     skrll 	if (uhcidebug >= 2)
    446         1.1  augustss 		uhci_dumpregs(sc);
    447         1.1  augustss #endif
    448         1.1  augustss 
    449       1.219  jmcneill 	sc->sc_suspend = PWR_RESUME;
    450       1.219  jmcneill 
    451         1.1  augustss 	UWRITE2(sc, UHCI_INTR, 0);		/* disable interrupts */
    452       1.142  augustss 	uhci_globalreset(sc);			/* reset the controller */
    453       1.142  augustss 	uhci_reset(sc);
    454        1.24  augustss 
    455         1.1  augustss 	/* Allocate and initialize real frame array. */
    456       1.152  augustss 	err = usb_allocmem(&sc->sc_bus,
    457  1.264.4.49     skrll 	    UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t),
    458  1.264.4.49     skrll 	    UHCI_FRAMELIST_ALIGN, &sc->sc_dma);
    459        1.63  augustss 	if (err)
    460  1.264.4.13     skrll 		return err;
    461       1.159  augustss 	sc->sc_pframes = KERNADDR(&sc->sc_dma, 0);
    462         1.1  augustss 	UWRITE2(sc, UHCI_FRNUM, 0);		/* set frame number to 0 */
    463       1.160  augustss 	UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/
    464         1.1  augustss 
    465  1.264.4.55     skrll 	/* Initialise mutex early for uhci_alloc_* */
    466  1.264.4.55     skrll 	mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
    467  1.264.4.55     skrll 	mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB);
    468  1.264.4.55     skrll 
    469       1.152  augustss 	/*
    470       1.123  augustss 	 * Allocate a TD, inactive, that hangs from the last QH.
    471       1.123  augustss 	 * This is to avoid a bug in the PIIX that makes it run berserk
    472       1.123  augustss 	 * otherwise.
    473       1.123  augustss 	 */
    474       1.123  augustss 	std = uhci_alloc_std(sc);
    475       1.123  augustss 	if (std == NULL)
    476  1.264.4.14     skrll 		return ENOMEM;
    477       1.123  augustss 	std->link.std = NULL;
    478       1.123  augustss 	std->td.td_link = htole32(UHCI_PTR_T);
    479       1.123  augustss 	std->td.td_status = htole32(0); /* inactive */
    480       1.123  augustss 	std->td.td_token = htole32(0);
    481       1.123  augustss 	std->td.td_buffer = htole32(0);
    482       1.223    bouyer 	usb_syncmem(&std->dma, std->offs, sizeof(std->td),
    483       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
    484       1.123  augustss 
    485       1.123  augustss 	/* Allocate the dummy QH marking the end and used for looping the QHs.*/
    486       1.123  augustss 	lsqh = uhci_alloc_sqh(sc);
    487       1.123  augustss 	if (lsqh == NULL)
    488  1.264.4.55     skrll 		goto fail1;
    489       1.123  augustss 	lsqh->hlink = NULL;
    490       1.123  augustss 	lsqh->qh.qh_hlink = htole32(UHCI_PTR_T);	/* end of QH chain */
    491       1.123  augustss 	lsqh->elink = std;
    492       1.123  augustss 	lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD);
    493       1.123  augustss 	sc->sc_last_qh = lsqh;
    494       1.223    bouyer 	usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh),
    495       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
    496       1.123  augustss 
    497         1.1  augustss 	/* Allocate the dummy QH where bulk traffic will be queued. */
    498         1.1  augustss 	bsqh = uhci_alloc_sqh(sc);
    499        1.63  augustss 	if (bsqh == NULL)
    500  1.264.4.55     skrll 		goto fail2;
    501       1.123  augustss 	bsqh->hlink = lsqh;
    502       1.123  augustss 	bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH);
    503       1.121  augustss 	bsqh->elink = NULL;
    504        1.88   tsutsui 	bsqh->qh.qh_elink = htole32(UHCI_PTR_T);
    505         1.1  augustss 	sc->sc_bulk_start = sc->sc_bulk_end = bsqh;
    506       1.223    bouyer 	usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh),
    507       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
    508         1.1  augustss 
    509       1.123  augustss 	/* Allocate dummy QH where high speed control traffic will be queued. */
    510       1.123  augustss 	chsqh = uhci_alloc_sqh(sc);
    511       1.123  augustss 	if (chsqh == NULL)
    512  1.264.4.55     skrll 		goto fail3;
    513       1.123  augustss 	chsqh->hlink = bsqh;
    514       1.123  augustss 	chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH);
    515       1.123  augustss 	chsqh->elink = NULL;
    516       1.123  augustss 	chsqh->qh.qh_elink = htole32(UHCI_PTR_T);
    517       1.123  augustss 	sc->sc_hctl_start = sc->sc_hctl_end = chsqh;
    518       1.223    bouyer 	usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh),
    519       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
    520       1.123  augustss 
    521       1.123  augustss 	/* Allocate dummy QH where control traffic will be queued. */
    522       1.123  augustss 	clsqh = uhci_alloc_sqh(sc);
    523       1.123  augustss 	if (clsqh == NULL)
    524  1.264.4.55     skrll 		goto fail4;
    525       1.220    bouyer 	clsqh->hlink = chsqh;
    526       1.123  augustss 	clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH);
    527       1.123  augustss 	clsqh->elink = NULL;
    528       1.123  augustss 	clsqh->qh.qh_elink = htole32(UHCI_PTR_T);
    529       1.123  augustss 	sc->sc_lctl_start = sc->sc_lctl_end = clsqh;
    530       1.223    bouyer 	usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh),
    531       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
    532         1.1  augustss 
    533       1.152  augustss 	/*
    534         1.1  augustss 	 * Make all (virtual) frame list pointers point to the interrupt
    535         1.1  augustss 	 * queue heads and the interrupt queue heads at the control
    536         1.1  augustss 	 * queue head and point the physical frame list to the virtual.
    537         1.1  augustss 	 */
    538  1.264.4.24     skrll 	for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
    539         1.1  augustss 		std = uhci_alloc_std(sc);
    540         1.1  augustss 		sqh = uhci_alloc_sqh(sc);
    541        1.67  augustss 		if (std == NULL || sqh == NULL)
    542  1.264.4.13     skrll 			return USBD_NOMEM;
    543        1.42  augustss 		std->link.sqh = sqh;
    544       1.121  augustss 		std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH);
    545        1.88   tsutsui 		std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */
    546        1.88   tsutsui 		std->td.td_token = htole32(0);
    547        1.88   tsutsui 		std->td.td_buffer = htole32(0);
    548       1.223    bouyer 		usb_syncmem(&std->dma, std->offs, sizeof(std->td),
    549       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
    550       1.123  augustss 		sqh->hlink = clsqh;
    551       1.123  augustss 		sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH);
    552       1.121  augustss 		sqh->elink = NULL;
    553        1.88   tsutsui 		sqh->qh.qh_elink = htole32(UHCI_PTR_T);
    554       1.223    bouyer 		usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
    555       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
    556         1.1  augustss 		sc->sc_vframes[i].htd = std;
    557         1.1  augustss 		sc->sc_vframes[i].etd = std;
    558         1.1  augustss 		sc->sc_vframes[i].hqh = sqh;
    559         1.1  augustss 		sc->sc_vframes[i].eqh = sqh;
    560       1.152  augustss 		for (j = i;
    561       1.152  augustss 		     j < UHCI_FRAMELIST_COUNT;
    562         1.1  augustss 		     j += UHCI_VFRAMELIST_COUNT)
    563        1.88   tsutsui 			sc->sc_pframes[j] = htole32(std->physaddr);
    564         1.1  augustss 	}
    565       1.223    bouyer 	usb_syncmem(&sc->sc_dma, 0,
    566       1.223    bouyer 	    UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t),
    567       1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
    568       1.223    bouyer 
    569         1.1  augustss 
    570  1.264.4.39     skrll 	TAILQ_INIT(&sc->sc_intrhead);
    571         1.1  augustss 
    572       1.253  christos 	sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0,
    573       1.253  christos 	    "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL);
    574        1.76  augustss 
    575       1.248       mrg 	callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE);
    576       1.248       mrg 
    577         1.1  augustss 	/* Set up the bus struct. */
    578   1.264.4.7     skrll 	sc->sc_bus.ub_methods = &uhci_bus_methods;
    579   1.264.4.7     skrll 	sc->sc_bus.ub_pipesize = sizeof(struct uhci_pipe);
    580   1.264.4.7     skrll 	sc->sc_bus.ub_usedma = true;
    581         1.1  augustss 
    582       1.190  augustss 	UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */
    583       1.190  augustss 
    584  1.264.4.27     skrll 	DPRINTF("Enabling...", 0, 0, 0, 0);
    585       1.225    bouyer 
    586  1.264.4.24     skrll 	err = uhci_run(sc, 1, 0);		/* and here we go... */
    587       1.152  augustss 	UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE |
    588         1.1  augustss 		UHCI_INTR_IOCE | UHCI_INTR_SPIE);	/* enable interrupts */
    589       1.225    bouyer 	return err;
    590  1.264.4.55     skrll 
    591  1.264.4.55     skrll fail4:
    592  1.264.4.55     skrll 	uhci_free_sqh(sc, chsqh);
    593  1.264.4.55     skrll fail3:
    594  1.264.4.55     skrll 	uhci_free_sqh(sc, lsqh);
    595  1.264.4.55     skrll fail2:
    596  1.264.4.55     skrll 	uhci_free_sqh(sc, lsqh);
    597  1.264.4.55     skrll fail1:
    598  1.264.4.55     skrll 	uhci_free_std(sc, std);
    599  1.264.4.55     skrll 
    600  1.264.4.55     skrll 	return ENOMEM;
    601        1.53  augustss }
    602        1.53  augustss 
    603        1.53  augustss int
    604       1.215    dyoung uhci_activate(device_t self, enum devact act)
    605        1.53  augustss {
    606       1.215    dyoung 	struct uhci_softc *sc = device_private(self);
    607        1.53  augustss 
    608        1.53  augustss 	switch (act) {
    609        1.53  augustss 	case DVACT_DEACTIVATE:
    610       1.210  kiyohara 		sc->sc_dying = 1;
    611       1.230    dyoung 		return 0;
    612       1.230    dyoung 	default:
    613       1.230    dyoung 		return EOPNOTSUPP;
    614        1.53  augustss 	}
    615        1.53  augustss }
    616        1.53  augustss 
    617       1.215    dyoung void
    618       1.215    dyoung uhci_childdet(device_t self, device_t child)
    619       1.215    dyoung {
    620       1.215    dyoung 	struct uhci_softc *sc = device_private(self);
    621       1.215    dyoung 
    622       1.215    dyoung 	KASSERT(sc->sc_child == child);
    623       1.215    dyoung 	sc->sc_child = NULL;
    624       1.215    dyoung }
    625       1.215    dyoung 
    626        1.53  augustss int
    627       1.119  augustss uhci_detach(struct uhci_softc *sc, int flags)
    628        1.53  augustss {
    629        1.53  augustss 	int rv = 0;
    630        1.53  augustss 
    631        1.53  augustss 	if (sc->sc_child != NULL)
    632        1.53  augustss 		rv = config_detach(sc->sc_child, flags);
    633       1.152  augustss 
    634        1.53  augustss 	if (rv != 0)
    635  1.264.4.13     skrll 		return rv;
    636        1.53  augustss 
    637       1.226        ad 	callout_halt(&sc->sc_poll_handle, NULL);
    638       1.226        ad 	callout_destroy(&sc->sc_poll_handle);
    639       1.226        ad 
    640       1.248       mrg 	mutex_destroy(&sc->sc_lock);
    641       1.248       mrg 	mutex_destroy(&sc->sc_intr_lock);
    642       1.248       mrg 
    643       1.254  christos 	pool_cache_destroy(sc->sc_xferpool);
    644       1.254  christos 
    645        1.76  augustss 	/* XXX free other data structures XXX */
    646        1.53  augustss 
    647  1.264.4.13     skrll 	return rv;
    648         1.1  augustss }
    649         1.1  augustss 
    650  1.264.4.25     skrll struct usbd_xfer *
    651  1.264.4.36     skrll uhci_allocx(struct usbd_bus *bus, unsigned int nframes)
    652        1.76  augustss {
    653  1.264.4.37     skrll 	struct uhci_softc *sc = UHCI_BUS2SC(bus);
    654  1.264.4.25     skrll 	struct usbd_xfer *xfer;
    655        1.76  augustss 
    656       1.253  christos 	xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT);
    657        1.92  augustss 	if (xfer != NULL) {
    658       1.253  christos 		memset(xfer, 0, sizeof(struct uhci_xfer));
    659  1.264.4.31     skrll 
    660        1.92  augustss #ifdef DIAGNOSTIC
    661  1.264.4.40     skrll 		struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
    662  1.264.4.41     skrll 		uxfer->ux_isdone = true;
    663   1.264.4.7     skrll 		xfer->ux_state = XFER_BUSY;
    664        1.92  augustss #endif
    665        1.92  augustss 	}
    666  1.264.4.13     skrll 	return xfer;
    667        1.76  augustss }
    668        1.76  augustss 
    669        1.76  augustss void
    670  1.264.4.25     skrll uhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer)
    671        1.76  augustss {
    672  1.264.4.37     skrll 	struct uhci_softc *sc = UHCI_BUS2SC(bus);
    673  1.264.4.37     skrll 	struct uhci_xfer *uxfer __diagused = UHCI_XFER2UXFER(xfer);
    674        1.76  augustss 
    675  1.264.4.31     skrll 	KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer,
    676  1.264.4.31     skrll 	    xfer->ux_state);
    677  1.264.4.41     skrll 	KASSERTMSG(uxfer->ux_isdone, "xfer %p not done\n", xfer);
    678        1.93  augustss #ifdef DIAGNOSTIC
    679   1.264.4.7     skrll 	xfer->ux_state = XFER_FREE;
    680        1.93  augustss #endif
    681       1.253  christos 	pool_cache_put(sc->sc_xferpool, xfer);
    682        1.48  augustss }
    683        1.48  augustss 
    684       1.248       mrg Static void
    685       1.248       mrg uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock)
    686       1.248       mrg {
    687  1.264.4.37     skrll 	struct uhci_softc *sc = UHCI_BUS2SC(bus);
    688       1.248       mrg 
    689       1.248       mrg 	*lock = &sc->sc_lock;
    690       1.248       mrg }
    691       1.248       mrg 
    692       1.248       mrg 
    693        1.72  augustss /*
    694       1.212  jmcneill  * Handle suspend/resume.
    695       1.212  jmcneill  *
    696       1.212  jmcneill  * We need to switch to polling mode here, because this routine is
    697       1.212  jmcneill  * called from an interrupt context.  This is all right since we
    698       1.212  jmcneill  * are almost suspended anyway.
    699        1.72  augustss  */
    700       1.212  jmcneill bool
    701       1.232    dyoung uhci_resume(device_t dv, const pmf_qual_t *qual)
    702        1.72  augustss {
    703       1.212  jmcneill 	uhci_softc_t *sc = device_private(dv);
    704       1.212  jmcneill 	int cmd;
    705        1.72  augustss 
    706       1.248       mrg 	mutex_spin_enter(&sc->sc_intr_lock);
    707       1.193  augustss 
    708       1.212  jmcneill 	cmd = UREAD2(sc, UHCI_CMD);
    709   1.264.4.7     skrll 	sc->sc_bus.ub_usepolling++;
    710       1.214       smb 	UWRITE2(sc, UHCI_INTR, 0);
    711       1.214       smb 	uhci_globalreset(sc);
    712       1.214       smb 	uhci_reset(sc);
    713       1.212  jmcneill 	if (cmd & UHCI_CMD_RS)
    714       1.249  drochner 		uhci_run(sc, 0, 1);
    715       1.212  jmcneill 
    716       1.212  jmcneill 	/* restore saved state */
    717       1.212  jmcneill 	UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0));
    718       1.212  jmcneill 	UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum);
    719       1.212  jmcneill 	UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof);
    720       1.212  jmcneill 
    721       1.212  jmcneill 	UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */
    722       1.248       mrg 	usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock);
    723       1.212  jmcneill 	UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */
    724       1.212  jmcneill 	UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE |
    725       1.212  jmcneill 	    UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE);
    726       1.214       smb 	UHCICMD(sc, UHCI_CMD_MAXP);
    727       1.249  drochner 	uhci_run(sc, 1, 1); /* and start traffic again */
    728       1.248       mrg 	usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock);
    729   1.264.4.7     skrll 	sc->sc_bus.ub_usepolling--;
    730       1.212  jmcneill 	if (sc->sc_intr_xfer != NULL)
    731       1.234    dyoung 		callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub,
    732       1.212  jmcneill 		    sc->sc_intr_xfer);
    733       1.212  jmcneill #ifdef UHCI_DEBUG
    734  1.264.4.43     skrll 	if (uhcidebug >= 2)
    735       1.212  jmcneill 		uhci_dumpregs(sc);
    736       1.212  jmcneill #endif
    737       1.212  jmcneill 
    738       1.219  jmcneill 	sc->sc_suspend = PWR_RESUME;
    739       1.248       mrg 	mutex_spin_exit(&sc->sc_intr_lock);
    740       1.212  jmcneill 
    741       1.212  jmcneill 	return true;
    742        1.72  augustss }
    743        1.72  augustss 
    744       1.212  jmcneill bool
    745       1.232    dyoung uhci_suspend(device_t dv, const pmf_qual_t *qual)
    746        1.30  augustss {
    747       1.212  jmcneill 	uhci_softc_t *sc = device_private(dv);
    748        1.30  augustss 	int cmd;
    749        1.30  augustss 
    750       1.248       mrg 	mutex_spin_enter(&sc->sc_intr_lock);
    751       1.212  jmcneill 
    752        1.30  augustss 	cmd = UREAD2(sc, UHCI_CMD);
    753        1.30  augustss 
    754       1.212  jmcneill #ifdef UHCI_DEBUG
    755  1.264.4.43     skrll 	if (uhcidebug >= 2)
    756       1.212  jmcneill 		uhci_dumpregs(sc);
    757       1.212  jmcneill #endif
    758       1.212  jmcneill 	if (sc->sc_intr_xfer != NULL)
    759       1.234    dyoung 		callout_stop(&sc->sc_poll_handle);
    760       1.219  jmcneill 	sc->sc_suspend = PWR_SUSPEND;
    761   1.264.4.7     skrll 	sc->sc_bus.ub_usepolling++;
    762       1.219  jmcneill 
    763       1.249  drochner 	uhci_run(sc, 0, 1); /* stop the controller */
    764       1.212  jmcneill 	cmd &= ~UHCI_CMD_RS;
    765       1.212  jmcneill 
    766       1.212  jmcneill 	/* save some state if BIOS doesn't */
    767       1.212  jmcneill 	sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM);
    768       1.212  jmcneill 	sc->sc_saved_sof = UREAD1(sc, UHCI_SOF);
    769       1.212  jmcneill 
    770       1.212  jmcneill 	UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */
    771        1.30  augustss 
    772       1.212  jmcneill 	UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */
    773       1.248       mrg 	usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock);
    774   1.264.4.7     skrll 	sc->sc_bus.ub_usepolling--;
    775        1.86  augustss 
    776       1.248       mrg 	mutex_spin_exit(&sc->sc_intr_lock);
    777       1.212  jmcneill 
    778       1.212  jmcneill 	return true;
    779        1.30  augustss }
    780        1.30  augustss 
    781        1.59  augustss #ifdef UHCI_DEBUG
    782       1.101  augustss Static void
    783       1.119  augustss uhci_dumpregs(uhci_softc_t *sc)
    784         1.1  augustss {
    785  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
    786  1.264.4.27     skrll 	DPRINTF("cmd =%04x  sts    =%04x  intr   =%04x  frnum =%04x",
    787  1.264.4.21     skrll 	    UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS),
    788  1.264.4.21     skrll 	    UREAD2(sc, UHCI_INTR), UREAD2(sc, UHCI_FRNUM));
    789  1.264.4.27     skrll 	DPRINTF("sof =%04x  portsc1=%04x  portsc2=%04x  flbase=%08x",
    790  1.264.4.21     skrll 	    UREAD1(sc, UHCI_SOF), UREAD2(sc, UHCI_PORTSC1),
    791  1.264.4.21     skrll 	    UREAD2(sc, UHCI_PORTSC2), UREAD4(sc, UHCI_FLBASEADDR));
    792         1.1  augustss }
    793         1.1  augustss 
    794         1.1  augustss void
    795       1.119  augustss uhci_dump_td(uhci_soft_td_t *p)
    796         1.1  augustss {
    797  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
    798       1.250  christos 
    799       1.223    bouyer 	usb_syncmem(&p->dma, p->offs, sizeof(p->td),
    800       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
    801  1.264.4.21     skrll 
    802  1.264.4.44     skrll 	DPRINTF("TD(%p) at 0x%08x", p, p->physaddr, 0, 0);
    803  1.264.4.78     skrll 	DPRINTF("   link=0x%08x status=0x%08x "
    804  1.264.4.21     skrll 	    "token=0x%08x buffer=0x%08x",
    805  1.264.4.21     skrll 	     le32toh(p->td.td_link),
    806  1.264.4.21     skrll 	     le32toh(p->td.td_status),
    807  1.264.4.21     skrll 	     le32toh(p->td.td_token),
    808  1.264.4.21     skrll 	     le32toh(p->td.td_buffer));
    809  1.264.4.21     skrll 
    810  1.264.4.27     skrll 	DPRINTF("bitstuff=%d crcto   =%d nak     =%d babble  =%d",
    811  1.264.4.21     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_BITSTUFF),
    812  1.264.4.21     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_CRCTO),
    813  1.264.4.21     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_NAK),
    814  1.264.4.21     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_BABBLE));
    815  1.264.4.27     skrll 	DPRINTF("dbuffer =%d stalled =%d active  =%d ioc     =%d",
    816  1.264.4.21     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_DBUFFER),
    817  1.264.4.21     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_STALLED),
    818  1.264.4.21     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_ACTIVE),
    819  1.264.4.21     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_IOC));
    820  1.264.4.27     skrll 	DPRINTF("ios     =%d ls      =%d spd     =%d",
    821  1.264.4.21     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_IOS),
    822  1.264.4.21     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_LS),
    823  1.264.4.21     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_SPD), 0);
    824  1.264.4.27     skrll 	DPRINTF("errcnt  =%d actlen  =%d pid=%02x",
    825  1.264.4.21     skrll 	    UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)),
    826  1.264.4.21     skrll 	    UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)),
    827  1.264.4.21     skrll 	    UHCI_TD_GET_PID(le32toh(p->td.td_token)), 0);
    828  1.264.4.27     skrll 	DPRINTF("addr=%d  endpt=%d  D=%d  maxlen=%d,",
    829  1.264.4.21     skrll 	    UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)),
    830  1.264.4.21     skrll 	    UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)),
    831  1.264.4.21     skrll 	    UHCI_TD_GET_DT(le32toh(p->td.td_token)),
    832  1.264.4.21     skrll 	    UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token)));
    833         1.1  augustss }
    834         1.1  augustss 
    835         1.1  augustss void
    836       1.119  augustss uhci_dump_qh(uhci_soft_qh_t *sqh)
    837         1.1  augustss {
    838  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
    839  1.264.4.21     skrll 
    840       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
    841       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
    842  1.264.4.21     skrll 
    843  1.264.4.44     skrll 	DPRINTF("QH(%p) at 0x%08x: hlink=%08x elink=%08x", sqh,
    844        1.88   tsutsui 	    (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink),
    845  1.264.4.21     skrll 	    le32toh(sqh->qh.qh_elink));
    846  1.264.4.21     skrll 
    847       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD);
    848         1.1  augustss }
    849         1.1  augustss 
    850        1.13  augustss 
    851       1.110  augustss #if 1
    852         1.1  augustss void
    853       1.119  augustss uhci_dump(void)
    854         1.1  augustss {
    855       1.110  augustss 	uhci_dump_all(thesc);
    856       1.110  augustss }
    857       1.110  augustss #endif
    858         1.1  augustss 
    859       1.110  augustss void
    860       1.119  augustss uhci_dump_all(uhci_softc_t *sc)
    861       1.110  augustss {
    862         1.1  augustss 	uhci_dumpregs(sc);
    863       1.110  augustss 	/*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/
    864       1.261     skrll 	uhci_dump_qhs(sc->sc_lctl_start);
    865         1.1  augustss }
    866         1.1  augustss 
    867        1.67  augustss 
    868        1.67  augustss void
    869       1.119  augustss uhci_dump_qhs(uhci_soft_qh_t *sqh)
    870        1.67  augustss {
    871  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
    872  1.264.4.21     skrll 
    873        1.67  augustss 	uhci_dump_qh(sqh);
    874        1.67  augustss 
    875  1.264.4.18     skrll 	/*
    876  1.264.4.18     skrll 	 * uhci_dump_qhs displays all the QHs and TDs from the given QH onwards
    877        1.67  augustss 	 * Traverses sideways first, then down.
    878        1.67  augustss 	 *
    879        1.67  augustss 	 * QH1
    880        1.67  augustss 	 * QH2
    881        1.67  augustss 	 * No QH
    882        1.67  augustss 	 * TD2.1
    883        1.67  augustss 	 * TD2.2
    884        1.67  augustss 	 * TD1.1
    885        1.67  augustss 	 * etc.
    886        1.67  augustss 	 *
    887        1.67  augustss 	 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1.
    888        1.67  augustss 	 */
    889        1.67  augustss 
    890       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
    891       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
    892        1.88   tsutsui 	if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T))
    893        1.67  augustss 		uhci_dump_qhs(sqh->hlink);
    894        1.67  augustss 	else
    895  1.264.4.27     skrll 		DPRINTF("No QH", 0, 0, 0, 0);
    896       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD);
    897        1.67  augustss 
    898        1.88   tsutsui 	if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T))
    899        1.67  augustss 		uhci_dump_tds(sqh->elink);
    900        1.67  augustss 	else
    901  1.264.4.27     skrll 		DPRINTF("No QH", 0, 0, 0, 0);
    902        1.67  augustss }
    903        1.67  augustss 
    904         1.1  augustss void
    905       1.119  augustss uhci_dump_tds(uhci_soft_td_t *std)
    906         1.1  augustss {
    907        1.67  augustss 	uhci_soft_td_t *td;
    908       1.223    bouyer 	int stop;
    909        1.67  augustss 
    910  1.264.4.24     skrll 	for (td = std; td != NULL; td = td->link.std) {
    911        1.67  augustss 		uhci_dump_td(td);
    912         1.1  augustss 
    913  1.264.4.18     skrll 		/*
    914  1.264.4.18     skrll 		 * Check whether the link pointer in this TD marks
    915        1.67  augustss 		 * the link pointer as end of queue. This avoids
    916        1.67  augustss 		 * printing the free list in case the queue/TD has
    917        1.67  augustss 		 * already been moved there (seatbelt).
    918        1.67  augustss 		 */
    919       1.223    bouyer 		usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link),
    920       1.223    bouyer 		    sizeof(td->td.td_link),
    921       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
    922       1.223    bouyer 		stop = (le32toh(td->td.td_link) & UHCI_PTR_T ||
    923       1.223    bouyer 			le32toh(td->td.td_link) == 0);
    924       1.223    bouyer 		usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link),
    925       1.223    bouyer 		    sizeof(td->td.td_link), BUS_DMASYNC_PREREAD);
    926       1.223    bouyer 		if (stop)
    927        1.67  augustss 			break;
    928        1.67  augustss 	}
    929         1.1  augustss }
    930        1.92  augustss 
    931       1.101  augustss Static void
    932  1.264.4.40     skrll uhci_dump_ii(struct uhci_xfer *ux)
    933        1.92  augustss {
    934  1.264.4.25     skrll 	struct usbd_pipe *pipe;
    935        1.95  augustss 	usb_endpoint_descriptor_t *ed;
    936  1.264.4.25     skrll 	struct usbd_device *dev;
    937       1.152  augustss 
    938  1.264.4.39     skrll 	if (ux == NULL) {
    939  1.264.4.39     skrll 		printf("ux NULL\n");
    940   1.264.4.2     skrll 		return;
    941   1.264.4.2     skrll 	}
    942  1.264.4.41     skrll 	pipe = ux->ux_xfer.ux_pipe;
    943   1.264.4.2     skrll 	if (pipe == NULL) {
    944  1.264.4.41     skrll 		printf("ux %p: done=%d pipe=NULL\n", ux, ux->ux_isdone);
    945   1.264.4.2     skrll 		return;
    946       1.139  augustss 	}
    947   1.264.4.7     skrll 	if (pipe->up_endpoint == NULL) {
    948  1.264.4.40     skrll 		printf("ux %p: done=%d pipe=%p pipe->up_endpoint=NULL\n",
    949  1.264.4.41     skrll 		       ux, ux->ux_isdone, pipe);
    950   1.264.4.2     skrll 		return;
    951       1.139  augustss 	}
    952   1.264.4.7     skrll 	if (pipe->up_dev == NULL) {
    953  1.264.4.40     skrll 		printf("ux %p: done=%d pipe=%p pipe->up_dev=NULL\n",
    954  1.264.4.41     skrll 		       ux, ux->ux_isdone, pipe);
    955   1.264.4.2     skrll 		return;
    956        1.95  augustss 	}
    957   1.264.4.7     skrll 	ed = pipe->up_endpoint->ue_edesc;
    958   1.264.4.7     skrll 	dev = pipe->up_dev;
    959  1.264.4.40     skrll 	printf("ux %p: done=%d dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n",
    960  1.264.4.41     skrll 	       ux, ux->ux_isdone, dev,
    961   1.264.4.7     skrll 	       UGETW(dev->ud_ddesc.idVendor),
    962   1.264.4.7     skrll 	       UGETW(dev->ud_ddesc.idProduct),
    963   1.264.4.7     skrll 	       dev->ud_addr, pipe,
    964        1.92  augustss 	       ed->bEndpointAddress, ed->bmAttributes);
    965        1.92  augustss }
    966        1.92  augustss 
    967       1.120  augustss void uhci_dump_iis(struct uhci_softc *sc);
    968        1.92  augustss void
    969       1.119  augustss uhci_dump_iis(struct uhci_softc *sc)
    970        1.92  augustss {
    971  1.264.4.40     skrll 	struct uhci_xfer *ux;
    972        1.92  augustss 
    973  1.264.4.39     skrll 	printf("interrupt list:\n");
    974  1.264.4.60     skrll 	TAILQ_FOREACH(ux, &sc->sc_intrhead, ux_list)
    975  1.264.4.39     skrll 		uhci_dump_ii(ux);
    976        1.92  augustss }
    977        1.92  augustss 
    978       1.120  augustss void iidump(void);
    979       1.119  augustss void iidump(void) { uhci_dump_iis(thesc); }
    980        1.92  augustss 
    981         1.1  augustss #endif
    982         1.1  augustss 
    983         1.1  augustss /*
    984         1.1  augustss  * This routine is executed periodically and simulates interrupts
    985         1.1  augustss  * from the root controller interrupt pipe for port status change.
    986         1.1  augustss  */
    987         1.1  augustss void
    988       1.119  augustss uhci_poll_hub(void *addr)
    989         1.1  augustss {
    990  1.264.4.25     skrll 	struct usbd_xfer *xfer = addr;
    991  1.264.4.25     skrll 	struct usbd_pipe *pipe = xfer->ux_pipe;
    992       1.227    martin 	uhci_softc_t *sc;
    993         1.1  augustss 	u_char *p;
    994         1.1  augustss 
    995  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
    996         1.1  augustss 
    997   1.264.4.7     skrll 	if (__predict_false(pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL))
    998       1.228    martin 		return;	/* device has detached */
    999  1.264.4.37     skrll 	sc = UHCI_PIPE2SC(pipe);
   1000       1.234    dyoung 	callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer);
   1001        1.41  augustss 
   1002   1.264.4.7     skrll 	p = xfer->ux_buf;
   1003         1.1  augustss 	p[0] = 0;
   1004         1.1  augustss 	if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC))
   1005         1.1  augustss 		p[0] |= 1<<1;
   1006         1.1  augustss 	if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC))
   1007         1.1  augustss 		p[0] |= 1<<2;
   1008        1.41  augustss 	if (p[0] == 0)
   1009        1.41  augustss 		/* No change, try again in a while */
   1010        1.41  augustss 		return;
   1011        1.41  augustss 
   1012   1.264.4.7     skrll 	xfer->ux_actlen = 1;
   1013   1.264.4.7     skrll 	xfer->ux_status = USBD_NORMAL_COMPLETION;
   1014       1.248       mrg 	mutex_enter(&sc->sc_lock);
   1015        1.63  augustss 	usb_transfer_complete(xfer);
   1016       1.248       mrg 	mutex_exit(&sc->sc_lock);
   1017        1.41  augustss }
   1018        1.41  augustss 
   1019        1.41  augustss void
   1020  1.264.4.25     skrll uhci_root_intr_done(struct usbd_xfer *xfer)
   1021        1.84  augustss {
   1022        1.84  augustss }
   1023        1.84  augustss 
   1024       1.123  augustss /*
   1025       1.123  augustss  * Let the last QH loop back to the high speed control transfer QH.
   1026       1.123  augustss  * This is what intel calls "bandwidth reclamation" and improves
   1027       1.123  augustss  * USB performance a lot for some devices.
   1028       1.123  augustss  * If we are already looping, just count it.
   1029       1.123  augustss  */
   1030         1.1  augustss void
   1031  1.264.4.17     skrll uhci_add_loop(uhci_softc_t *sc)
   1032  1.264.4.17     skrll {
   1033  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1034  1.264.4.25     skrll 
   1035       1.125  augustss #ifdef UHCI_DEBUG
   1036       1.125  augustss 	if (uhcinoloop)
   1037       1.125  augustss 		return;
   1038       1.125  augustss #endif
   1039       1.123  augustss 	if (++sc->sc_loops == 1) {
   1040  1.264.4.21     skrll 		DPRINTFN(5, "add loop", 0, 0, 0, 0);
   1041       1.123  augustss 		/* Note, we don't loop back the soft pointer. */
   1042       1.152  augustss 		sc->sc_last_qh->qh.qh_hlink =
   1043       1.123  augustss 		    htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH);
   1044       1.223    bouyer 		usb_syncmem(&sc->sc_last_qh->dma,
   1045       1.223    bouyer 		    sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink),
   1046       1.223    bouyer 		    sizeof(sc->sc_last_qh->qh.qh_hlink),
   1047       1.223    bouyer 		    BUS_DMASYNC_PREWRITE);
   1048       1.123  augustss 	}
   1049       1.123  augustss }
   1050       1.123  augustss 
   1051       1.123  augustss void
   1052  1.264.4.17     skrll uhci_rem_loop(uhci_softc_t *sc)
   1053  1.264.4.17     skrll {
   1054  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1055  1.264.4.21     skrll 
   1056       1.125  augustss #ifdef UHCI_DEBUG
   1057       1.125  augustss 	if (uhcinoloop)
   1058       1.125  augustss 		return;
   1059       1.125  augustss #endif
   1060       1.123  augustss 	if (--sc->sc_loops == 0) {
   1061  1.264.4.21     skrll 		DPRINTFN(5, "remove loop", 0, 0, 0, 0);
   1062       1.123  augustss 		sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T);
   1063       1.223    bouyer 		usb_syncmem(&sc->sc_last_qh->dma,
   1064       1.223    bouyer 		    sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink),
   1065       1.223    bouyer 		    sizeof(sc->sc_last_qh->qh.qh_hlink),
   1066       1.223    bouyer 		    BUS_DMASYNC_PREWRITE);
   1067       1.123  augustss 	}
   1068       1.123  augustss }
   1069       1.123  augustss 
   1070       1.248       mrg /* Add high speed control QH, called with lock held. */
   1071       1.123  augustss void
   1072       1.123  augustss uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   1073         1.1  augustss {
   1074        1.42  augustss 	uhci_soft_qh_t *eqh;
   1075         1.1  augustss 
   1076  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1077  1.264.4.21     skrll 
   1078       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   1079       1.248       mrg 
   1080  1.264.4.21     skrll 	DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
   1081       1.123  augustss 	eqh = sc->sc_hctl_end;
   1082       1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1083       1.223    bouyer 	    sizeof(eqh->qh.qh_hlink),
   1084       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE);
   1085        1.42  augustss 	sqh->hlink       = eqh->hlink;
   1086        1.42  augustss 	sqh->qh.qh_hlink = eqh->qh.qh_hlink;
   1087       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
   1088       1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   1089        1.42  augustss 	eqh->hlink       = sqh;
   1090       1.121  augustss 	eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
   1091       1.123  augustss 	sc->sc_hctl_end = sqh;
   1092       1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1093       1.223    bouyer 	    sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
   1094       1.125  augustss #ifdef UHCI_CTL_LOOP
   1095       1.123  augustss 	uhci_add_loop(sc);
   1096       1.125  augustss #endif
   1097         1.1  augustss }
   1098         1.1  augustss 
   1099       1.248       mrg /* Remove high speed control QH, called with lock held. */
   1100         1.1  augustss void
   1101       1.123  augustss uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   1102         1.1  augustss {
   1103         1.1  augustss 	uhci_soft_qh_t *pqh;
   1104       1.256   tsutsui 	uint32_t elink;
   1105         1.1  augustss 
   1106  1.264.4.76     skrll 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
   1107       1.248       mrg 
   1108  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1109  1.264.4.21     skrll 	DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
   1110       1.125  augustss #ifdef UHCI_CTL_LOOP
   1111       1.123  augustss 	uhci_rem_loop(sc);
   1112       1.125  augustss #endif
   1113       1.124  augustss 	/*
   1114       1.124  augustss 	 * The T bit should be set in the elink of the QH so that the HC
   1115       1.124  augustss 	 * doesn't follow the pointer.  This condition may fail if the
   1116       1.124  augustss 	 * the transferred packet was short so that the QH still points
   1117       1.124  augustss 	 * at the last used TD.
   1118       1.124  augustss 	 * In this case we set the T bit and wait a little for the HC
   1119       1.124  augustss 	 * to stop looking at the TD.
   1120       1.223    bouyer 	 * Note that if the TD chain is large enough, the controller
   1121       1.223    bouyer 	 * may still be looking at the chain at the end of this function.
   1122       1.223    bouyer 	 * uhci_free_std_chain() will make sure the controller stops
   1123       1.223    bouyer 	 * looking at it quickly, but until then we should not change
   1124       1.223    bouyer 	 * sqh->hlink.
   1125       1.124  augustss 	 */
   1126       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1127       1.223    bouyer 	    sizeof(sqh->qh.qh_elink),
   1128       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1129       1.256   tsutsui 	elink = le32toh(sqh->qh.qh_elink);
   1130       1.256   tsutsui 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1131       1.256   tsutsui 	    sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD);
   1132       1.256   tsutsui 	if (!(elink & UHCI_PTR_T)) {
   1133       1.124  augustss 		sqh->qh.qh_elink = htole32(UHCI_PTR_T);
   1134       1.223    bouyer 		usb_syncmem(&sqh->dma,
   1135       1.223    bouyer 		    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1136       1.223    bouyer 		    sizeof(sqh->qh.qh_elink),
   1137       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   1138       1.124  augustss 		delay(UHCI_QH_REMOVE_DELAY);
   1139       1.124  augustss 	}
   1140       1.124  augustss 
   1141       1.123  augustss 	pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh);
   1142       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1143       1.223    bouyer 	    sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
   1144       1.152  augustss 	pqh->hlink = sqh->hlink;
   1145        1.42  augustss 	pqh->qh.qh_hlink = sqh->qh.qh_hlink;
   1146       1.223    bouyer 	usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1147  1.264.4.76     skrll 	    sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
   1148       1.124  augustss 	delay(UHCI_QH_REMOVE_DELAY);
   1149       1.123  augustss 	if (sc->sc_hctl_end == sqh)
   1150       1.123  augustss 		sc->sc_hctl_end = pqh;
   1151       1.123  augustss }
   1152       1.123  augustss 
   1153       1.248       mrg /* Add low speed control QH, called with lock held. */
   1154       1.123  augustss void
   1155       1.123  augustss uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   1156       1.123  augustss {
   1157       1.123  augustss 	uhci_soft_qh_t *eqh;
   1158       1.123  augustss 
   1159       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   1160       1.248       mrg 
   1161  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1162  1.264.4.21     skrll 	DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
   1163  1.264.4.21     skrll 
   1164       1.123  augustss 	eqh = sc->sc_lctl_end;
   1165       1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1166       1.223    bouyer 	    sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
   1167       1.152  augustss 	sqh->hlink = eqh->hlink;
   1168       1.123  augustss 	sqh->qh.qh_hlink = eqh->qh.qh_hlink;
   1169       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
   1170       1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   1171       1.152  augustss 	eqh->hlink = sqh;
   1172       1.123  augustss 	eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
   1173       1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1174       1.223    bouyer 	    sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
   1175       1.123  augustss 	sc->sc_lctl_end = sqh;
   1176       1.123  augustss }
   1177       1.123  augustss 
   1178       1.248       mrg /* Remove low speed control QH, called with lock held. */
   1179       1.123  augustss void
   1180       1.123  augustss uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   1181       1.123  augustss {
   1182       1.123  augustss 	uhci_soft_qh_t *pqh;
   1183       1.256   tsutsui 	uint32_t elink;
   1184       1.123  augustss 
   1185  1.264.4.76     skrll 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
   1186       1.248       mrg 
   1187  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1188  1.264.4.21     skrll 	DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
   1189  1.264.4.21     skrll 
   1190       1.124  augustss 	/* See comment in uhci_remove_hs_ctrl() */
   1191       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1192       1.223    bouyer 	    sizeof(sqh->qh.qh_elink),
   1193       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1194       1.256   tsutsui 	elink = le32toh(sqh->qh.qh_elink);
   1195       1.256   tsutsui 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1196       1.256   tsutsui 	    sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD);
   1197       1.256   tsutsui 	if (!(elink & UHCI_PTR_T)) {
   1198       1.124  augustss 		sqh->qh.qh_elink = htole32(UHCI_PTR_T);
   1199       1.223    bouyer 		usb_syncmem(&sqh->dma,
   1200       1.223    bouyer 		    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1201       1.223    bouyer 		    sizeof(sqh->qh.qh_elink),
   1202       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   1203       1.124  augustss 		delay(UHCI_QH_REMOVE_DELAY);
   1204       1.124  augustss 	}
   1205       1.123  augustss 	pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh);
   1206       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1207       1.223    bouyer 	    sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
   1208       1.152  augustss 	pqh->hlink = sqh->hlink;
   1209       1.123  augustss 	pqh->qh.qh_hlink = sqh->qh.qh_hlink;
   1210       1.223    bouyer 	usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1211       1.223    bouyer 	    sizeof(pqh->qh.qh_hlink),
   1212       1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   1213       1.124  augustss 	delay(UHCI_QH_REMOVE_DELAY);
   1214       1.123  augustss 	if (sc->sc_lctl_end == sqh)
   1215       1.123  augustss 		sc->sc_lctl_end = pqh;
   1216         1.1  augustss }
   1217         1.1  augustss 
   1218       1.248       mrg /* Add bulk QH, called with lock held. */
   1219         1.1  augustss void
   1220       1.119  augustss uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   1221         1.1  augustss {
   1222        1.42  augustss 	uhci_soft_qh_t *eqh;
   1223         1.1  augustss 
   1224       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   1225       1.248       mrg 
   1226  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1227  1.264.4.21     skrll 	DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
   1228  1.264.4.21     skrll 
   1229        1.42  augustss 	eqh = sc->sc_bulk_end;
   1230       1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1231       1.223    bouyer 	    sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
   1232       1.152  augustss 	sqh->hlink = eqh->hlink;
   1233        1.42  augustss 	sqh->qh.qh_hlink = eqh->qh.qh_hlink;
   1234       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
   1235       1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   1236       1.152  augustss 	eqh->hlink = sqh;
   1237       1.121  augustss 	eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
   1238       1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1239       1.223    bouyer 	    sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
   1240         1.1  augustss 	sc->sc_bulk_end = sqh;
   1241       1.123  augustss 	uhci_add_loop(sc);
   1242         1.1  augustss }
   1243         1.1  augustss 
   1244       1.248       mrg /* Remove bulk QH, called with lock held. */
   1245         1.1  augustss void
   1246       1.119  augustss uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   1247         1.1  augustss {
   1248         1.1  augustss 	uhci_soft_qh_t *pqh;
   1249         1.1  augustss 
   1250       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   1251       1.248       mrg 
   1252  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1253  1.264.4.21     skrll 	DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
   1254  1.264.4.21     skrll 
   1255       1.123  augustss 	uhci_rem_loop(sc);
   1256       1.124  augustss 	/* See comment in uhci_remove_hs_ctrl() */
   1257       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1258       1.223    bouyer 	    sizeof(sqh->qh.qh_elink),
   1259       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1260       1.124  augustss 	if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) {
   1261       1.124  augustss 		sqh->qh.qh_elink = htole32(UHCI_PTR_T);
   1262       1.223    bouyer 		usb_syncmem(&sqh->dma,
   1263       1.223    bouyer 		    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1264       1.223    bouyer 		    sizeof(sqh->qh.qh_elink),
   1265       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   1266       1.124  augustss 		delay(UHCI_QH_REMOVE_DELAY);
   1267       1.124  augustss 	}
   1268        1.92  augustss 	pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh);
   1269       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1270       1.223    bouyer 	    sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
   1271        1.42  augustss 	pqh->hlink       = sqh->hlink;
   1272        1.42  augustss 	pqh->qh.qh_hlink = sqh->qh.qh_hlink;
   1273       1.223    bouyer 	usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1274       1.223    bouyer 	    sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
   1275       1.124  augustss 	delay(UHCI_QH_REMOVE_DELAY);
   1276         1.1  augustss 	if (sc->sc_bulk_end == sqh)
   1277         1.1  augustss 		sc->sc_bulk_end = pqh;
   1278         1.1  augustss }
   1279         1.1  augustss 
   1280       1.141  augustss Static int uhci_intr1(uhci_softc_t *);
   1281       1.141  augustss 
   1282         1.1  augustss int
   1283       1.119  augustss uhci_intr(void *arg)
   1284         1.1  augustss {
   1285        1.44  augustss 	uhci_softc_t *sc = arg;
   1286       1.248       mrg 	int ret = 0;
   1287       1.248       mrg 
   1288  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1289  1.264.4.21     skrll 
   1290       1.248       mrg 	mutex_spin_enter(&sc->sc_intr_lock);
   1291       1.146  augustss 
   1292       1.216  drochner 	if (sc->sc_dying || !device_has_power(sc->sc_dev))
   1293       1.248       mrg 		goto done;
   1294       1.141  augustss 
   1295   1.264.4.7     skrll 	if (sc->sc_bus.ub_usepolling || UREAD2(sc, UHCI_INTR) == 0) {
   1296  1.264.4.21     skrll 		DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0);
   1297       1.248       mrg 		goto done;
   1298       1.141  augustss 	}
   1299       1.179   mycroft 
   1300       1.248       mrg 	ret = uhci_intr1(sc);
   1301       1.248       mrg 
   1302       1.248       mrg  done:
   1303       1.248       mrg 	mutex_spin_exit(&sc->sc_intr_lock);
   1304       1.248       mrg 	return ret;
   1305       1.141  augustss }
   1306       1.141  augustss 
   1307       1.141  augustss int
   1308       1.141  augustss uhci_intr1(uhci_softc_t *sc)
   1309       1.141  augustss {
   1310        1.44  augustss 	int status;
   1311        1.44  augustss 	int ack;
   1312         1.1  augustss 
   1313  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1314  1.264.4.21     skrll 
   1315        1.67  augustss #ifdef UHCI_DEBUG
   1316  1.264.4.46     skrll 	if (uhcidebug >= 15) {
   1317  1.264.4.27     skrll 		DPRINTF("sc %p", sc, 0, 0, 0);
   1318         1.1  augustss 		uhci_dumpregs(sc);
   1319         1.1  augustss 	}
   1320         1.1  augustss #endif
   1321       1.117  augustss 
   1322       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_intr_lock));
   1323       1.248       mrg 
   1324       1.153  augustss 	status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS;
   1325  1.264.4.59     skrll 	/* Check if the interrupt was for us. */
   1326  1.264.4.59     skrll 	if (status == 0)
   1327  1.264.4.13     skrll 		return 0;
   1328       1.127     soren 
   1329       1.117  augustss 	if (sc->sc_suspend != PWR_RESUME) {
   1330       1.201  jmcneill #ifdef DIAGNOSTIC
   1331       1.117  augustss 		printf("%s: interrupt while not operating ignored\n",
   1332       1.216  drochner 		       device_xname(sc->sc_dev));
   1333       1.201  jmcneill #endif
   1334       1.134  augustss 		UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */
   1335  1.264.4.13     skrll 		return 0;
   1336       1.117  augustss 	}
   1337        1.44  augustss 
   1338        1.44  augustss 	ack = 0;
   1339        1.44  augustss 	if (status & UHCI_STS_USBINT)
   1340        1.44  augustss 		ack |= UHCI_STS_USBINT;
   1341        1.44  augustss 	if (status & UHCI_STS_USBEI)
   1342        1.44  augustss 		ack |= UHCI_STS_USBEI;
   1343         1.1  augustss 	if (status & UHCI_STS_RD) {
   1344        1.44  augustss 		ack |= UHCI_STS_RD;
   1345       1.118  augustss #ifdef UHCI_DEBUG
   1346       1.216  drochner 		printf("%s: resume detect\n", device_xname(sc->sc_dev));
   1347       1.118  augustss #endif
   1348         1.1  augustss 	}
   1349         1.1  augustss 	if (status & UHCI_STS_HSE) {
   1350        1.44  augustss 		ack |= UHCI_STS_HSE;
   1351       1.216  drochner 		printf("%s: host system error\n", device_xname(sc->sc_dev));
   1352         1.1  augustss 	}
   1353         1.1  augustss 	if (status & UHCI_STS_HCPE) {
   1354        1.44  augustss 		ack |= UHCI_STS_HCPE;
   1355       1.152  augustss 		printf("%s: host controller process error\n",
   1356       1.216  drochner 		       device_xname(sc->sc_dev));
   1357        1.44  augustss 	}
   1358       1.233   msaitoh 
   1359       1.233   msaitoh 	/* When HCHalted=1 and Run/Stop=0 , it is normal */
   1360       1.233   msaitoh 	if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) {
   1361        1.44  augustss 		/* no acknowledge needed */
   1362       1.136  augustss 		if (!sc->sc_dying) {
   1363       1.152  augustss 			printf("%s: host controller halted\n",
   1364       1.216  drochner 			    device_xname(sc->sc_dev));
   1365       1.110  augustss #ifdef UHCI_DEBUG
   1366       1.136  augustss 			uhci_dump_all(sc);
   1367       1.110  augustss #endif
   1368       1.136  augustss 		}
   1369       1.136  augustss 		sc->sc_dying = 1;
   1370         1.1  augustss 	}
   1371        1.44  augustss 
   1372       1.132  augustss 	if (!ack)
   1373  1.264.4.13     skrll 		return 0;	/* nothing to acknowledge */
   1374       1.132  augustss 	UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */
   1375         1.1  augustss 
   1376        1.85  augustss 	usb_schedsoftintr(&sc->sc_bus);
   1377        1.85  augustss 
   1378  1.264.4.21     skrll 	DPRINTFN(15, "sc %p done", sc, 0, 0, 0);
   1379        1.85  augustss 
   1380  1.264.4.13     skrll 	return 1;
   1381        1.85  augustss }
   1382        1.85  augustss 
   1383        1.85  augustss void
   1384       1.133  augustss uhci_softintr(void *v)
   1385        1.85  augustss {
   1386       1.216  drochner 	struct usbd_bus *bus = v;
   1387  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_BUS2SC(bus);
   1388  1.264.4.39     skrll 	struct uhci_xfer *ux, *nextux;
   1389  1.264.4.61     skrll 	ux_completeq_t cq;
   1390        1.85  augustss 
   1391  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1392  1.264.4.27     skrll 	DPRINTF("sc %p", sc, 0, 0, 0);
   1393       1.248       mrg 
   1394  1.264.4.21     skrll 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
   1395        1.50  augustss 
   1396  1.264.4.61     skrll 	TAILQ_INIT(&cq);
   1397         1.1  augustss 	/*
   1398         1.1  augustss 	 * Interrupts on UHCI really suck.  When the host controller
   1399         1.1  augustss 	 * interrupts because a transfer is completed there is no
   1400         1.1  augustss 	 * way of knowing which transfer it was.  You can scan down
   1401         1.1  augustss 	 * the TDs and QHs of the previous frame to limit the search,
   1402         1.1  augustss 	 * but that assumes that the interrupt was not delayed by more
   1403         1.1  augustss 	 * than 1 ms, which may not always be true (e.g. after debug
   1404         1.1  augustss 	 * output on a slow console).
   1405         1.1  augustss 	 * We scan all interrupt descriptors to see if any have
   1406         1.1  augustss 	 * completed.
   1407         1.1  augustss 	 */
   1408  1.264.4.61     skrll 	TAILQ_FOREACH_SAFE(ux, &sc->sc_intrhead, ux_list, nextux) {
   1409  1.264.4.61     skrll 		uhci_check_intr(sc, ux, &cq);
   1410  1.264.4.61     skrll 	}
   1411  1.264.4.61     skrll 
   1412  1.264.4.61     skrll 	/*
   1413  1.264.4.61     skrll 	 * We abuse ux_list for the interrupt and complete lists and
   1414  1.264.4.61     skrll 	 * interrupt transfers will get re-added here so use
   1415  1.264.4.61     skrll 	 * the _SAFE version of TAILQ_FOREACH.
   1416  1.264.4.61     skrll 	 */
   1417  1.264.4.61     skrll 	TAILQ_FOREACH_SAFE(ux, &cq, ux_list, nextux) {
   1418  1.264.4.61     skrll 		DPRINTF("ux %p", ux, 0, 0, 0);
   1419  1.264.4.61     skrll 		usb_transfer_complete(&ux->ux_xfer);
   1420       1.178    martin 	}
   1421         1.1  augustss }
   1422         1.1  augustss 
   1423         1.1  augustss /* Check for an interrupt. */
   1424         1.1  augustss void
   1425  1.264.4.61     skrll uhci_check_intr(uhci_softc_t *sc, struct uhci_xfer *ux, ux_completeq_t *cqp)
   1426         1.1  augustss {
   1427  1.264.4.55     skrll 	uhci_soft_td_t *std, *fstd = NULL, *lstd = NULL;
   1428   1.264.4.1     skrll 	uint32_t status;
   1429         1.1  augustss 
   1430  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1431  1.264.4.39     skrll 	DPRINTFN(15, "ux %p", ux, 0, 0, 0);
   1432  1.264.4.31     skrll 
   1433  1.264.4.39     skrll 	KASSERT(ux != NULL);
   1434  1.264.4.31     skrll 
   1435  1.264.4.41     skrll 	struct usbd_xfer *xfer = &ux->ux_xfer;
   1436  1.264.4.39     skrll 	if (xfer->ux_status == USBD_CANCELLED ||
   1437  1.264.4.39     skrll 	    xfer->ux_status == USBD_TIMEOUT) {
   1438  1.264.4.39     skrll 		DPRINTF("aborted xfer %p", xfer, 0, 0, 0);
   1439       1.155  augustss 		return;
   1440       1.155  augustss 	}
   1441       1.155  augustss 
   1442  1.264.4.55     skrll 	switch (ux->ux_type) {
   1443  1.264.4.55     skrll 	case UX_CTRL:
   1444  1.264.4.55     skrll 		fstd = ux->ux_setup;
   1445  1.264.4.55     skrll 		lstd = ux->ux_stat;
   1446  1.264.4.55     skrll 		break;
   1447  1.264.4.55     skrll 	case UX_BULK:
   1448  1.264.4.55     skrll 	case UX_INTR:
   1449  1.264.4.55     skrll 	case UX_ISOC:
   1450  1.264.4.55     skrll 		fstd = ux->ux_stdstart;
   1451  1.264.4.55     skrll 		lstd = ux->ux_stdend;
   1452  1.264.4.55     skrll 		break;
   1453  1.264.4.55     skrll 	default:
   1454  1.264.4.55     skrll 		KASSERT(false);
   1455  1.264.4.55     skrll 		break;
   1456  1.264.4.55     skrll 	}
   1457  1.264.4.55     skrll 	if (fstd == NULL)
   1458         1.1  augustss 		return;
   1459  1.264.4.31     skrll 
   1460  1.264.4.31     skrll 	KASSERT(lstd != NULL);
   1461  1.264.4.31     skrll 
   1462       1.223    bouyer 	usb_syncmem(&lstd->dma,
   1463       1.223    bouyer 	    lstd->offs + offsetof(uhci_td_t, td_status),
   1464       1.223    bouyer 	    sizeof(lstd->td.td_status),
   1465       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1466       1.256   tsutsui 	status = le32toh(lstd->td.td_status);
   1467       1.256   tsutsui 	usb_syncmem(&lstd->dma,
   1468       1.256   tsutsui 	    lstd->offs + offsetof(uhci_td_t, td_status),
   1469       1.256   tsutsui 	    sizeof(lstd->td.td_status),
   1470       1.256   tsutsui 	    BUS_DMASYNC_PREREAD);
   1471       1.258     skrll 
   1472       1.258     skrll 	/* If the last TD is not marked active we can complete */
   1473       1.258     skrll 	if (!(status & UHCI_TD_ACTIVE)) {
   1474       1.258     skrll  done:
   1475  1.264.4.39     skrll 		DPRINTFN(12, "ux=%p done", ux, 0, 0, 0);
   1476  1.264.4.61     skrll 		uhci_idone(ux, cqp);
   1477       1.258     skrll 		return;
   1478       1.258     skrll 	}
   1479       1.258     skrll 
   1480       1.258     skrll 	/*
   1481       1.258     skrll 	 * If the last TD is still active we need to check whether there
   1482       1.258     skrll 	 * is an error somewhere in the middle, or whether there was a
   1483       1.258     skrll 	 * short packet (SPD and not ACTIVE).
   1484       1.258     skrll 	 */
   1485  1.264.4.39     skrll 	DPRINTFN(12, "active ux=%p", ux, 0, 0, 0);
   1486  1.264.4.55     skrll 	for (std = fstd; std != lstd; std = std->link.std) {
   1487       1.258     skrll 		usb_syncmem(&std->dma,
   1488       1.258     skrll 		    std->offs + offsetof(uhci_td_t, td_status),
   1489       1.258     skrll 		    sizeof(std->td.td_status),
   1490       1.258     skrll 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1491       1.258     skrll 		status = le32toh(std->td.td_status);
   1492       1.258     skrll 		usb_syncmem(&std->dma,
   1493       1.258     skrll 		    std->offs + offsetof(uhci_td_t, td_status),
   1494       1.258     skrll 		    sizeof(std->td.td_status), BUS_DMASYNC_PREREAD);
   1495       1.258     skrll 
   1496       1.258     skrll 		/* If there's an active TD the xfer isn't done. */
   1497       1.258     skrll 		if (status & UHCI_TD_ACTIVE) {
   1498  1.264.4.39     skrll 			DPRINTFN(12, "ux=%p std=%p still active",
   1499  1.264.4.39     skrll 			    ux, std, 0, 0);
   1500       1.258     skrll 			return;
   1501       1.258     skrll 		}
   1502       1.258     skrll 
   1503       1.258     skrll 		/* Any kind of error makes the xfer done. */
   1504       1.258     skrll 		if (status & UHCI_TD_STALLED)
   1505       1.258     skrll 			goto done;
   1506       1.258     skrll 
   1507       1.258     skrll 		/*
   1508       1.258     skrll 		 * If the data phase of a control transfer is short, we need
   1509       1.258     skrll 		 * to complete the status stage
   1510       1.258     skrll 		 */
   1511       1.258     skrll 
   1512  1.264.4.55     skrll 		if ((status & UHCI_TD_SPD) && ux->ux_type == UX_CTRL) {
   1513       1.258     skrll 			struct uhci_pipe *upipe =
   1514  1.264.4.50     skrll 			    UHCI_PIPE2UPIPE(xfer->ux_pipe);
   1515  1.264.4.33     skrll 			uhci_soft_qh_t *sqh = upipe->ctrl.sqh;
   1516  1.264.4.33     skrll 			uhci_soft_td_t *stat = upipe->ctrl.stat;
   1517       1.258     skrll 
   1518  1.264.4.39     skrll 			DPRINTFN(12, "ux=%p std=%p control status"
   1519  1.264.4.41     skrll 			    "phase needs completion", ux, ux->ux_stdstart, 0, 0);
   1520       1.258     skrll 
   1521       1.258     skrll 			sqh->qh.qh_elink =
   1522       1.258     skrll 			    htole32(stat->physaddr | UHCI_PTR_TD);
   1523       1.258     skrll 			usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
   1524       1.258     skrll 			    BUS_DMASYNC_PREWRITE);
   1525       1.258     skrll 			break;
   1526       1.258     skrll 		}
   1527       1.258     skrll 
   1528       1.258     skrll 		/* We want short packets, and it is short: it's done */
   1529       1.258     skrll 		usb_syncmem(&std->dma,
   1530       1.258     skrll 		    std->offs + offsetof(uhci_td_t, td_token),
   1531       1.258     skrll 		    sizeof(std->td.td_token),
   1532       1.258     skrll 		    BUS_DMASYNC_POSTWRITE);
   1533       1.258     skrll 
   1534       1.258     skrll 		if ((status & UHCI_TD_SPD) &&
   1535       1.258     skrll 			UHCI_TD_GET_ACTLEN(status) <
   1536       1.258     skrll 			UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) {
   1537       1.258     skrll 			goto done;
   1538        1.18  augustss 		}
   1539         1.1  augustss 	}
   1540         1.1  augustss }
   1541         1.1  augustss 
   1542       1.248       mrg /* Called with USB lock held. */
   1543         1.1  augustss void
   1544  1.264.4.61     skrll uhci_idone(struct uhci_xfer *ux, ux_completeq_t *cqp)
   1545         1.1  augustss {
   1546  1.264.4.79     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1547  1.264.4.41     skrll 	struct usbd_xfer *xfer = &ux->ux_xfer;
   1548  1.264.4.37     skrll 	uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer);
   1549  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   1550         1.1  augustss 	uhci_soft_td_t *std;
   1551   1.264.4.1     skrll 	uint32_t status = 0, nstatus;
   1552  1.264.4.79     skrll 	bool polling = sc->sc_bus.ub_usepolling;
   1553        1.26  augustss 	int actlen;
   1554         1.1  augustss 
   1555   1.264.4.7     skrll 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
   1556       1.248       mrg 
   1557  1.264.4.39     skrll 	DPRINTFN(12, "ux=%p", ux, 0, 0, 0);
   1558  1.264.4.21     skrll 
   1559  1.264.4.79     skrll 	/*
   1560  1.264.4.79     skrll 	 * Make sure the timeout handler didn't run or ran to the end
   1561  1.264.4.79     skrll 	 * and set the transfer status.
   1562  1.264.4.79     skrll 	 */
   1563  1.264.4.79     skrll 	callout_halt(&xfer->ux_callout, polling ? NULL : &sc->sc_lock);
   1564  1.264.4.79     skrll 	if (xfer->ux_status == USBD_CANCELLED ||
   1565  1.264.4.79     skrll 	    xfer->ux_status == USBD_TIMEOUT) {
   1566  1.264.4.79     skrll  		DPRINTF("aborted xfer=%p", xfer, 0, 0, 0);
   1567  1.264.4.79     skrll 		return;
   1568  1.264.4.79     skrll 	}
   1569  1.264.4.79     skrll 
   1570         1.7  augustss #ifdef DIAGNOSTIC
   1571        1.92  augustss #ifdef UHCI_DEBUG
   1572  1.264.4.41     skrll 	if (ux->ux_isdone) {
   1573  1.264.4.31     skrll 		DPRINTF("--- dump start ---", 0, 0, 0, 0);
   1574  1.264.4.39     skrll 		uhci_dump_ii(ux);
   1575  1.264.4.31     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   1576         1.7  augustss 	}
   1577         1.7  augustss #endif
   1578  1.264.4.41     skrll 	KASSERT(!ux->ux_isdone);
   1579  1.264.4.66     skrll 	KASSERTMSG(!ux->ux_isdone, "xfer %p type %d status %d", xfer,
   1580  1.264.4.66     skrll 	    ux->ux_type, xfer->ux_status);
   1581  1.264.4.41     skrll 	ux->ux_isdone = true;
   1582  1.264.4.31     skrll #endif
   1583        1.48  augustss 
   1584   1.264.4.7     skrll 	if (xfer->ux_nframes != 0) {
   1585        1.48  augustss 		/* Isoc transfer, do things differently. */
   1586  1.264.4.33     skrll 		uhci_soft_td_t **stds = upipe->isoc.stds;
   1587       1.126  augustss 		int i, n, nframes, len;
   1588        1.48  augustss 
   1589  1.264.4.39     skrll 		DPRINTFN(5, "ux=%p isoc ready", ux, 0, 0, 0);
   1590        1.48  augustss 
   1591   1.264.4.7     skrll 		nframes = xfer->ux_nframes;
   1592        1.48  augustss 		actlen = 0;
   1593  1.264.4.61     skrll 		n = ux->ux_curframe;
   1594        1.48  augustss 		for (i = 0; i < nframes; i++) {
   1595        1.48  augustss 			std = stds[n];
   1596        1.59  augustss #ifdef UHCI_DEBUG
   1597  1.264.4.43     skrll 			if (uhcidebug >= 5) {
   1598  1.264.4.27     skrll 				DPRINTF("isoc TD %d", i, 0, 0, 0);
   1599  1.264.4.53     skrll 				DPRINTF("--- dump start ---", 0, 0, 0, 0);
   1600        1.48  augustss 				uhci_dump_td(std);
   1601  1.264.4.53     skrll 				DPRINTF("--- dump end ---", 0, 0, 0, 0);
   1602        1.48  augustss 			}
   1603        1.48  augustss #endif
   1604        1.48  augustss 			if (++n >= UHCI_VFRAMELIST_COUNT)
   1605        1.48  augustss 				n = 0;
   1606       1.223    bouyer 			usb_syncmem(&std->dma,
   1607       1.223    bouyer 			    std->offs + offsetof(uhci_td_t, td_status),
   1608       1.223    bouyer 			    sizeof(std->td.td_status),
   1609       1.223    bouyer 			    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1610        1.88   tsutsui 			status = le32toh(std->td.td_status);
   1611       1.126  augustss 			len = UHCI_TD_GET_ACTLEN(status);
   1612   1.264.4.7     skrll 			xfer->ux_frlengths[i] = len;
   1613       1.126  augustss 			actlen += len;
   1614        1.48  augustss 		}
   1615  1.264.4.33     skrll 		upipe->isoc.inuse -= nframes;
   1616   1.264.4.7     skrll 		xfer->ux_actlen = actlen;
   1617   1.264.4.7     skrll 		xfer->ux_status = USBD_NORMAL_COMPLETION;
   1618       1.140  augustss 		goto end;
   1619        1.48  augustss 	}
   1620        1.48  augustss 
   1621        1.59  augustss #ifdef UHCI_DEBUG
   1622  1.264.4.47     skrll 	DPRINTFN(10, "ux=%p, xfer=%p, pipe=%p ready", ux, xfer, upipe, 0);
   1623  1.264.4.47     skrll 	if (uhcidebug >= 10) {
   1624  1.264.4.47     skrll 		DPRINTF("--- dump start ---", 0, 0, 0, 0);
   1625  1.264.4.41     skrll 		uhci_dump_tds(ux->ux_stdstart);
   1626  1.264.4.47     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   1627  1.264.4.47     skrll 	}
   1628        1.48  augustss #endif
   1629        1.48  augustss 
   1630        1.26  augustss 	/* The transfer is done, compute actual length and status. */
   1631        1.26  augustss 	actlen = 0;
   1632  1.264.4.41     skrll 	for (std = ux->ux_stdstart; std != NULL; std = std->link.std) {
   1633       1.223    bouyer 		usb_syncmem(&std->dma, std->offs, sizeof(std->td),
   1634       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1635        1.88   tsutsui 		nstatus = le32toh(std->td.td_status);
   1636        1.64  augustss 		if (nstatus & UHCI_TD_ACTIVE)
   1637        1.26  augustss 			break;
   1638        1.67  augustss 
   1639        1.64  augustss 		status = nstatus;
   1640        1.88   tsutsui 		if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) !=
   1641        1.88   tsutsui 			UHCI_TD_PID_SETUP)
   1642        1.26  augustss 			actlen += UHCI_TD_GET_ACTLEN(status);
   1643       1.176   mycroft 		else {
   1644       1.176   mycroft 			/*
   1645       1.176   mycroft 			 * UHCI will report CRCTO in addition to a STALL or NAK
   1646       1.176   mycroft 			 * for a SETUP transaction.  See section 3.2.2, "TD
   1647       1.176   mycroft 			 * CONTROL AND STATUS".
   1648       1.176   mycroft 			 */
   1649       1.176   mycroft 			if (status & (UHCI_TD_STALLED | UHCI_TD_NAK))
   1650       1.176   mycroft 				status &= ~UHCI_TD_CRCTO;
   1651       1.176   mycroft 		}
   1652         1.1  augustss 	}
   1653        1.38  augustss 	/* If there are left over TDs we need to update the toggle. */
   1654        1.63  augustss 	if (std != NULL)
   1655        1.88   tsutsui 		upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token));
   1656        1.38  augustss 
   1657         1.1  augustss 	status &= UHCI_TD_ERROR;
   1658  1.264.4.29     skrll 	DPRINTFN(10, "actlen=%d, status=0x%x", actlen, status, 0, 0);
   1659   1.264.4.7     skrll 	xfer->ux_actlen = actlen;
   1660         1.1  augustss 	if (status != 0) {
   1661       1.122        tv 
   1662  1.264.4.21     skrll 		DPRINTFN((status == UHCI_TD_STALLED) * 10,
   1663  1.264.4.21     skrll 		    "error, addr=%d, endpt=0x%02x",
   1664  1.264.4.21     skrll 		    xfer->ux_pipe->up_dev->ud_addr,
   1665  1.264.4.21     skrll 		    xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress,
   1666  1.264.4.21     skrll 		    0, 0);
   1667  1.264.4.21     skrll 		DPRINTFN((status == UHCI_TD_STALLED) * 10,
   1668  1.264.4.21     skrll 		    "bitstuff=%d crcto   =%d nak     =%d babble  =%d",
   1669  1.264.4.45     skrll 		    !!(status & UHCI_TD_BITSTUFF),
   1670  1.264.4.45     skrll 		    !!(status & UHCI_TD_CRCTO),
   1671  1.264.4.45     skrll 		    !!(status & UHCI_TD_NAK),
   1672  1.264.4.45     skrll 		    !!(status & UHCI_TD_BABBLE));
   1673  1.264.4.21     skrll 		DPRINTFN((status == UHCI_TD_STALLED) * 10,
   1674  1.264.4.21     skrll 		    "dbuffer =%d stalled =%d active  =%d",
   1675  1.264.4.45     skrll 		    !!(status & UHCI_TD_DBUFFER),
   1676  1.264.4.45     skrll 		    !!(status & UHCI_TD_STALLED),
   1677  1.264.4.45     skrll 		    !!(status & UHCI_TD_ACTIVE),
   1678  1.264.4.21     skrll 		    0);
   1679       1.122        tv 
   1680         1.1  augustss 		if (status == UHCI_TD_STALLED)
   1681   1.264.4.7     skrll 			xfer->ux_status = USBD_STALLED;
   1682         1.1  augustss 		else
   1683   1.264.4.7     skrll 			xfer->ux_status = USBD_IOERROR; /* more info XXX */
   1684         1.1  augustss 	} else {
   1685   1.264.4.7     skrll 		xfer->ux_status = USBD_NORMAL_COMPLETION;
   1686         1.1  augustss 	}
   1687       1.140  augustss 
   1688       1.140  augustss  end:
   1689  1.264.4.61     skrll 	uhci_del_intr_list(sc, ux);
   1690  1.264.4.61     skrll 	if (cqp)
   1691  1.264.4.61     skrll 		TAILQ_INSERT_TAIL(cqp, ux, ux_list);
   1692  1.264.4.61     skrll 
   1693   1.264.4.7     skrll 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
   1694  1.264.4.39     skrll 	DPRINTFN(12, "ux=%p done", ux, 0, 0, 0);
   1695         1.1  augustss }
   1696         1.1  augustss 
   1697        1.13  augustss /*
   1698        1.13  augustss  * Called when a request does not complete.
   1699        1.13  augustss  */
   1700         1.1  augustss void
   1701       1.119  augustss uhci_timeout(void *addr)
   1702         1.1  augustss {
   1703  1.264.4.79     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1704  1.264.4.39     skrll 	struct usbd_xfer *xfer = addr;
   1705  1.264.4.39     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   1706  1.264.4.79     skrll 	bool timeout = false;
   1707       1.153  augustss 
   1708  1.264.4.79     skrll 	DPRINTF("xfer %p", xfer, 0, 0, 0);
   1709       1.153  augustss 
   1710  1.264.4.79     skrll 	mutex_enter(&sc->sc_lock);
   1711       1.153  augustss 	if (sc->sc_dying) {
   1712       1.248       mrg 		mutex_exit(&sc->sc_lock);
   1713       1.153  augustss 		return;
   1714       1.153  augustss 	}
   1715  1.264.4.79     skrll 	if (xfer->ux_status != USBD_CANCELLED) {
   1716  1.264.4.79     skrll 		xfer->ux_status = USBD_TIMEOUT;
   1717  1.264.4.79     skrll 		timeout = true;
   1718  1.264.4.79     skrll 	}
   1719  1.264.4.79     skrll 	mutex_exit(&sc->sc_lock);
   1720         1.1  augustss 
   1721  1.264.4.79     skrll 	if (timeout) {
   1722  1.264.4.79     skrll 		struct usbd_device *dev = xfer->ux_pipe->up_dev;
   1723  1.264.4.79     skrll 
   1724  1.264.4.79     skrll 		/* Execute the abort in a process context. */
   1725  1.264.4.79     skrll 		usb_init_task(&xfer->ux_aborttask, uhci_timeout_task, xfer,
   1726  1.264.4.79     skrll 		    USB_TASKQ_MPSAFE);
   1727  1.264.4.79     skrll 		usb_add_task(dev, &xfer->ux_aborttask, USB_TASKQ_HC);
   1728  1.264.4.79     skrll 	}
   1729       1.153  augustss }
   1730        1.51  augustss 
   1731       1.153  augustss void
   1732       1.153  augustss uhci_timeout_task(void *addr)
   1733       1.153  augustss {
   1734  1.264.4.25     skrll 	struct usbd_xfer *xfer = addr;
   1735  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   1736       1.153  augustss 
   1737  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1738  1.264.4.21     skrll 
   1739  1.264.4.27     skrll 	DPRINTF("xfer=%p", xfer, 0, 0, 0);
   1740        1.67  augustss 
   1741       1.248       mrg 	mutex_enter(&sc->sc_lock);
   1742  1.264.4.79     skrll 	KASSERT(xfer->ux_status == USBD_TIMEOUT);
   1743       1.153  augustss 	uhci_abort_xfer(xfer, USBD_TIMEOUT);
   1744       1.248       mrg 	mutex_exit(&sc->sc_lock);
   1745         1.1  augustss }
   1746         1.1  augustss 
   1747         1.8  augustss void
   1748       1.119  augustss uhci_poll(struct usbd_bus *bus)
   1749         1.8  augustss {
   1750  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_BUS2SC(bus);
   1751         1.8  augustss 
   1752       1.248       mrg 	if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) {
   1753       1.248       mrg 		mutex_spin_enter(&sc->sc_intr_lock);
   1754       1.141  augustss 		uhci_intr1(sc);
   1755       1.248       mrg 		mutex_spin_exit(&sc->sc_intr_lock);
   1756       1.248       mrg 	}
   1757         1.8  augustss }
   1758         1.8  augustss 
   1759         1.1  augustss void
   1760       1.119  augustss uhci_reset(uhci_softc_t *sc)
   1761         1.1  augustss {
   1762         1.1  augustss 	int n;
   1763         1.1  augustss 
   1764         1.1  augustss 	UHCICMD(sc, UHCI_CMD_HCRESET);
   1765         1.1  augustss 	/* The reset bit goes low when the controller is done. */
   1766       1.152  augustss 	for (n = 0; n < UHCI_RESET_TIMEOUT &&
   1767         1.1  augustss 		    (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++)
   1768        1.92  augustss 		usb_delay_ms(&sc->sc_bus, 1);
   1769         1.1  augustss 	if (n >= UHCI_RESET_TIMEOUT)
   1770       1.152  augustss 		printf("%s: controller did not reset\n",
   1771       1.216  drochner 		       device_xname(sc->sc_dev));
   1772         1.1  augustss }
   1773         1.1  augustss 
   1774        1.16  augustss usbd_status
   1775       1.249  drochner uhci_run(uhci_softc_t *sc, int run, int locked)
   1776         1.1  augustss {
   1777       1.248       mrg 	int n, running;
   1778   1.264.4.1     skrll 	uint16_t cmd;
   1779         1.1  augustss 
   1780  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1781  1.264.4.21     skrll 
   1782         1.1  augustss 	run = run != 0;
   1783       1.249  drochner 	if (!locked)
   1784       1.249  drochner 		mutex_spin_enter(&sc->sc_intr_lock);
   1785  1.264.4.21     skrll 
   1786  1.264.4.27     skrll 	DPRINTF("setting run=%d", run, 0, 0, 0);
   1787        1.71  augustss 	cmd = UREAD2(sc, UHCI_CMD);
   1788        1.71  augustss 	if (run)
   1789        1.71  augustss 		cmd |= UHCI_CMD_RS;
   1790        1.71  augustss 	else
   1791        1.71  augustss 		cmd &= ~UHCI_CMD_RS;
   1792        1.71  augustss 	UHCICMD(sc, cmd);
   1793  1.264.4.54     skrll 	for (n = 0; n < 10; n++) {
   1794         1.1  augustss 		running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH);
   1795         1.1  augustss 		/* return when we've entered the state we want */
   1796         1.1  augustss 		if (run == running) {
   1797       1.249  drochner 			if (!locked)
   1798       1.249  drochner 				mutex_spin_exit(&sc->sc_intr_lock);
   1799  1.264.4.27     skrll 			DPRINTF("done cmd=0x%x sts=0x%x",
   1800  1.264.4.21     skrll 			    UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 0, 0);
   1801  1.264.4.13     skrll 			return USBD_NORMAL_COMPLETION;
   1802         1.1  augustss 		}
   1803       1.248       mrg 		usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock);
   1804         1.1  augustss 	}
   1805       1.249  drochner 	if (!locked)
   1806       1.249  drochner 		mutex_spin_exit(&sc->sc_intr_lock);
   1807       1.216  drochner 	printf("%s: cannot %s\n", device_xname(sc->sc_dev),
   1808        1.14  augustss 	       run ? "start" : "stop");
   1809  1.264.4.13     skrll 	return USBD_IOERROR;
   1810         1.1  augustss }
   1811         1.1  augustss 
   1812         1.1  augustss /*
   1813         1.1  augustss  * Memory management routines.
   1814         1.1  augustss  *  uhci_alloc_std allocates TDs
   1815         1.1  augustss  *  uhci_alloc_sqh allocates QHs
   1816         1.7  augustss  * These two routines do their own free list management,
   1817         1.1  augustss  * partly for speed, partly because allocating DMAable memory
   1818  1.264.4.28     skrll  * has page size granularity so much memory would be wasted if
   1819        1.16  augustss  * only one TD/QH (32 bytes) was placed in each allocated chunk.
   1820         1.1  augustss  */
   1821         1.1  augustss 
   1822         1.1  augustss uhci_soft_td_t *
   1823       1.119  augustss uhci_alloc_std(uhci_softc_t *sc)
   1824         1.1  augustss {
   1825         1.1  augustss 	uhci_soft_td_t *std;
   1826        1.63  augustss 	usbd_status err;
   1827        1.42  augustss 	int i, offs;
   1828         1.7  augustss 	usb_dma_t dma;
   1829         1.1  augustss 
   1830  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1831  1.264.4.21     skrll 
   1832  1.264.4.55     skrll 	mutex_enter(&sc->sc_lock);
   1833        1.63  augustss 	if (sc->sc_freetds == NULL) {
   1834  1.264.4.21     skrll 		DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
   1835  1.264.4.55     skrll 		mutex_exit(&sc->sc_lock);
   1836  1.264.4.55     skrll 
   1837        1.63  augustss 		err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK,
   1838        1.63  augustss 			  UHCI_TD_ALIGN, &dma);
   1839        1.63  augustss 		if (err)
   1840  1.264.4.52     skrll 			return NULL;
   1841  1.264.4.55     skrll 
   1842  1.264.4.55     skrll 		mutex_enter(&sc->sc_lock);
   1843       1.248       mrg 		for (i = 0; i < UHCI_STD_CHUNK; i++) {
   1844        1.42  augustss 			offs = i * UHCI_STD_SIZE;
   1845       1.159  augustss 			std = KERNADDR(&dma, offs);
   1846       1.160  augustss 			std->physaddr = DMAADDR(&dma, offs);
   1847       1.223    bouyer 			std->dma = dma;
   1848       1.223    bouyer 			std->offs = offs;
   1849        1.42  augustss 			std->link.std = sc->sc_freetds;
   1850         1.1  augustss 			sc->sc_freetds = std;
   1851         1.1  augustss 		}
   1852         1.1  augustss 	}
   1853         1.1  augustss 	std = sc->sc_freetds;
   1854        1.42  augustss 	sc->sc_freetds = std->link.std;
   1855  1.264.4.55     skrll 	mutex_exit(&sc->sc_lock);
   1856  1.264.4.55     skrll 
   1857        1.42  augustss 	memset(&std->td, 0, sizeof(uhci_td_t));
   1858  1.264.4.55     skrll 
   1859         1.1  augustss 	return std;
   1860         1.1  augustss }
   1861         1.1  augustss 
   1862  1.264.4.55     skrll #define TD_IS_FREE 0x12345678
   1863  1.264.4.55     skrll 
   1864         1.1  augustss void
   1865  1.264.4.55     skrll uhci_free_std_locked(uhci_softc_t *sc, uhci_soft_td_t *std)
   1866         1.1  augustss {
   1867  1.264.4.55     skrll 	KASSERT(mutex_owned(&sc->sc_lock));
   1868  1.264.4.55     skrll 
   1869         1.7  augustss #ifdef DIAGNOSTIC
   1870        1.88   tsutsui 	if (le32toh(std->td.td_token) == TD_IS_FREE) {
   1871  1.264.4.65     skrll 		printf("%s: freeing free TD %p\n", __func__, std);
   1872         1.7  augustss 		return;
   1873         1.7  augustss 	}
   1874        1.88   tsutsui 	std->td.td_token = htole32(TD_IS_FREE);
   1875         1.7  augustss #endif
   1876  1.264.4.55     skrll 
   1877        1.42  augustss 	std->link.std = sc->sc_freetds;
   1878         1.1  augustss 	sc->sc_freetds = std;
   1879         1.1  augustss }
   1880         1.1  augustss 
   1881  1.264.4.55     skrll void
   1882  1.264.4.55     skrll uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std)
   1883  1.264.4.55     skrll {
   1884  1.264.4.55     skrll 	mutex_enter(&sc->sc_lock);
   1885  1.264.4.55     skrll 	uhci_free_std_locked(sc, std);
   1886  1.264.4.55     skrll 	mutex_exit(&sc->sc_lock);
   1887  1.264.4.55     skrll }
   1888  1.264.4.55     skrll 
   1889         1.1  augustss uhci_soft_qh_t *
   1890       1.119  augustss uhci_alloc_sqh(uhci_softc_t *sc)
   1891         1.1  augustss {
   1892         1.1  augustss 	uhci_soft_qh_t *sqh;
   1893        1.63  augustss 	usbd_status err;
   1894         1.1  augustss 	int i, offs;
   1895         1.7  augustss 	usb_dma_t dma;
   1896         1.1  augustss 
   1897  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1898  1.264.4.21     skrll 
   1899  1.264.4.55     skrll 	mutex_enter(&sc->sc_lock);
   1900        1.63  augustss 	if (sc->sc_freeqhs == NULL) {
   1901  1.264.4.21     skrll 		DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
   1902  1.264.4.55     skrll 		mutex_exit(&sc->sc_lock);
   1903  1.264.4.55     skrll 
   1904        1.63  augustss 		err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK,
   1905        1.63  augustss 			  UHCI_QH_ALIGN, &dma);
   1906        1.63  augustss 		if (err)
   1907  1.264.4.52     skrll 			return NULL;
   1908  1.264.4.55     skrll 
   1909  1.264.4.55     skrll 		mutex_enter(&sc->sc_lock);
   1910  1.264.4.54     skrll 		for (i = 0; i < UHCI_SQH_CHUNK; i++) {
   1911        1.42  augustss 			offs = i * UHCI_SQH_SIZE;
   1912       1.159  augustss 			sqh = KERNADDR(&dma, offs);
   1913       1.160  augustss 			sqh->physaddr = DMAADDR(&dma, offs);
   1914       1.223    bouyer 			sqh->dma = dma;
   1915       1.223    bouyer 			sqh->offs = offs;
   1916        1.42  augustss 			sqh->hlink = sc->sc_freeqhs;
   1917         1.1  augustss 			sc->sc_freeqhs = sqh;
   1918         1.1  augustss 		}
   1919         1.1  augustss 	}
   1920         1.1  augustss 	sqh = sc->sc_freeqhs;
   1921        1.42  augustss 	sc->sc_freeqhs = sqh->hlink;
   1922  1.264.4.55     skrll 	mutex_exit(&sc->sc_lock);
   1923  1.264.4.55     skrll 
   1924        1.42  augustss 	memset(&sqh->qh, 0, sizeof(uhci_qh_t));
   1925  1.264.4.55     skrll 
   1926  1.264.4.13     skrll 	return sqh;
   1927         1.1  augustss }
   1928         1.1  augustss 
   1929         1.1  augustss void
   1930       1.119  augustss uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   1931         1.1  augustss {
   1932  1.264.4.55     skrll 	KASSERT(mutex_owned(&sc->sc_lock));
   1933  1.264.4.55     skrll 
   1934        1.42  augustss 	sqh->hlink = sc->sc_freeqhs;
   1935         1.1  augustss 	sc->sc_freeqhs = sqh;
   1936         1.1  augustss }
   1937         1.1  augustss 
   1938  1.264.4.72     skrll #if 0
   1939         1.1  augustss void
   1940       1.119  augustss uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std,
   1941       1.119  augustss 		    uhci_soft_td_t *stdend)
   1942         1.1  augustss {
   1943         1.1  augustss 	uhci_soft_td_t *p;
   1944       1.256   tsutsui 	uint32_t td_link;
   1945         1.1  augustss 
   1946       1.223    bouyer 	/*
   1947       1.223    bouyer 	 * to avoid race condition with the controller which may be looking
   1948       1.223    bouyer 	 * at this chain, we need to first invalidate all links, and
   1949       1.223    bouyer 	 * then wait for the controller to move to another queue
   1950       1.223    bouyer 	 */
   1951       1.223    bouyer 	for (p = std; p != stdend; p = p->link.std) {
   1952       1.223    bouyer 		usb_syncmem(&p->dma,
   1953       1.223    bouyer 		    p->offs + offsetof(uhci_td_t, td_link),
   1954       1.223    bouyer 		    sizeof(p->td.td_link),
   1955       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1956       1.256   tsutsui 		td_link = le32toh(p->td.td_link);
   1957       1.256   tsutsui 		usb_syncmem(&p->dma,
   1958       1.256   tsutsui 		    p->offs + offsetof(uhci_td_t, td_link),
   1959       1.256   tsutsui 		    sizeof(p->td.td_link),
   1960       1.256   tsutsui 		    BUS_DMASYNC_PREREAD);
   1961       1.256   tsutsui 		if ((td_link & UHCI_PTR_T) == 0) {
   1962       1.255   tsutsui 			p->td.td_link = htole32(UHCI_PTR_T);
   1963       1.223    bouyer 			usb_syncmem(&p->dma,
   1964       1.223    bouyer 			    p->offs + offsetof(uhci_td_t, td_link),
   1965       1.223    bouyer 			    sizeof(p->td.td_link),
   1966       1.223    bouyer 			    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   1967       1.223    bouyer 		}
   1968       1.223    bouyer 	}
   1969       1.223    bouyer 	delay(UHCI_QH_REMOVE_DELAY);
   1970       1.223    bouyer 
   1971         1.1  augustss 	for (; std != stdend; std = p) {
   1972        1.42  augustss 		p = std->link.std;
   1973         1.1  augustss 		uhci_free_std(sc, std);
   1974         1.1  augustss 	}
   1975         1.1  augustss }
   1976  1.264.4.72     skrll #endif
   1977         1.1  augustss 
   1978  1.264.4.74     skrll int
   1979  1.264.4.70     skrll uhci_alloc_std_chain(uhci_softc_t *sc, struct usbd_xfer *xfer, int len,
   1980  1.264.4.70     skrll     int rd, uhci_soft_td_t **sp)
   1981         1.1  augustss {
   1982  1.264.4.55     skrll 	struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
   1983  1.264.4.55     skrll 	uint16_t flags = xfer->ux_flags;
   1984  1.264.4.70     skrll 	uhci_soft_td_t *p;
   1985         1.1  augustss 
   1986  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1987  1.264.4.21     skrll 
   1988  1.264.4.55     skrll 	DPRINTFN(8, "xfer=%p pipe=%p", xfer, xfer->ux_pipe, 0, 0);
   1989       1.248       mrg 
   1990  1.264.4.55     skrll 	ASSERT_SLEEPABLE();
   1991  1.264.4.55     skrll 	KASSERT(sp);
   1992       1.248       mrg 
   1993  1.264.4.70     skrll 	int maxp = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize);
   1994         1.1  augustss 	if (maxp == 0) {
   1995  1.264.4.65     skrll 		printf("%s: maxp=0\n", __func__);
   1996  1.264.4.74     skrll 		return EINVAL;
   1997         1.1  augustss 	}
   1998  1.264.4.55     skrll 	size_t ntd = (len + maxp - 1) / maxp;
   1999  1.264.4.70     skrll 	if (!rd && (flags & USBD_FORCE_SHORT_XFER)) {
   2000        1.73  augustss 		ntd++;
   2001  1.264.4.70     skrll 	}
   2002  1.264.4.55     skrll 	DPRINTFN(10, "maxp=%d ntd=%d", maxp, ntd, 0, 0);
   2003  1.264.4.21     skrll 
   2004  1.264.4.55     skrll 	uxfer->ux_stds = NULL;
   2005  1.264.4.55     skrll 	uxfer->ux_nstd = ntd;
   2006        1.73  augustss 	if (ntd == 0) {
   2007  1.264.4.55     skrll 		*sp = NULL;
   2008  1.264.4.27     skrll 		DPRINTF("ntd=0", 0, 0, 0, 0);
   2009  1.264.4.74     skrll 		return 0;
   2010        1.73  augustss 	}
   2011  1.264.4.55     skrll 	uxfer->ux_stds = kmem_alloc(sizeof(uhci_soft_td_t *) * ntd,
   2012  1.264.4.55     skrll 	    KM_SLEEP);
   2013  1.264.4.55     skrll 
   2014  1.264.4.80     skrll 	for (int i = 0; i < ntd; i++) {
   2015         1.1  augustss 		p = uhci_alloc_std(sc);
   2016        1.63  augustss 		if (p == NULL) {
   2017  1.264.4.80     skrll 			if (i != 0) {
   2018  1.264.4.80     skrll 				uxfer->ux_nstd = i;
   2019  1.264.4.80     skrll 				uhci_free_stds(sc, uxfer);
   2020  1.264.4.80     skrll 			}
   2021  1.264.4.73     skrll 			kmem_free(uxfer->ux_stds,
   2022  1.264.4.73     skrll 			    sizeof(uhci_soft_td_t *) * ntd);
   2023  1.264.4.74     skrll 			return ENOMEM;
   2024         1.1  augustss 		}
   2025  1.264.4.55     skrll 		uxfer->ux_stds[i] = p;
   2026         1.1  augustss 	}
   2027  1.264.4.70     skrll 
   2028  1.264.4.70     skrll 	*sp = uxfer->ux_stds[0];
   2029  1.264.4.21     skrll 
   2030  1.264.4.74     skrll 	return 0;
   2031         1.1  augustss }
   2032         1.1  augustss 
   2033  1.264.4.55     skrll Static void
   2034  1.264.4.55     skrll uhci_free_stds(uhci_softc_t *sc, struct uhci_xfer *ux)
   2035  1.264.4.55     skrll {
   2036  1.264.4.55     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2037  1.264.4.55     skrll 
   2038  1.264.4.55     skrll 	DPRINTFN(8, "ux=%p", ux, 0, 0, 0);
   2039  1.264.4.55     skrll 
   2040  1.264.4.55     skrll 	mutex_enter(&sc->sc_lock);
   2041  1.264.4.55     skrll 	for (size_t i = 0; i < ux->ux_nstd; i++) {
   2042  1.264.4.55     skrll 		uhci_soft_td_t *std = ux->ux_stds[i];
   2043  1.264.4.55     skrll #ifdef DIAGNOSTIC
   2044  1.264.4.55     skrll 		if (le32toh(std->td.td_token) == TD_IS_FREE) {
   2045  1.264.4.65     skrll 			printf("%s: freeing free TD %p\n", __func__, std);
   2046  1.264.4.55     skrll 			return;
   2047  1.264.4.55     skrll 		}
   2048  1.264.4.55     skrll 		std->td.td_token = htole32(TD_IS_FREE);
   2049  1.264.4.55     skrll #endif
   2050  1.264.4.55     skrll 		ux->ux_stds[i]->link.std = sc->sc_freetds;
   2051  1.264.4.55     skrll 		sc->sc_freetds = std;
   2052  1.264.4.55     skrll 	}
   2053  1.264.4.55     skrll 	mutex_exit(&sc->sc_lock);
   2054  1.264.4.55     skrll }
   2055  1.264.4.55     skrll 
   2056  1.264.4.55     skrll 
   2057  1.264.4.55     skrll Static void
   2058  1.264.4.55     skrll uhci_reset_std_chain(uhci_softc_t *sc, struct usbd_xfer *xfer,
   2059  1.264.4.58     skrll     int length, int isread, int *toggle, uhci_soft_td_t **lstd)
   2060  1.264.4.55     skrll {
   2061  1.264.4.55     skrll 	struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
   2062  1.264.4.55     skrll 	struct usbd_pipe *pipe = xfer->ux_pipe;
   2063  1.264.4.55     skrll 	usb_dma_t *dma = &xfer->ux_dmabuf;
   2064  1.264.4.55     skrll 	uint16_t flags = xfer->ux_flags;
   2065  1.264.4.55     skrll 	uhci_soft_td_t *std, *prev;
   2066  1.264.4.55     skrll 	int len = length;
   2067  1.264.4.55     skrll 	int tog = *toggle;
   2068  1.264.4.55     skrll 	int maxp;
   2069  1.264.4.55     skrll 	uint32_t status;
   2070  1.264.4.55     skrll 	size_t i;
   2071  1.264.4.55     skrll 
   2072  1.264.4.55     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2073  1.264.4.55     skrll 	DPRINTFN(8, "xfer=%p len %d isread %d toggle %d", xfer,
   2074  1.264.4.55     skrll 	    len, isread, *toggle);
   2075  1.264.4.55     skrll 
   2076  1.264.4.70     skrll 	KASSERT(len != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER)));
   2077  1.264.4.55     skrll 
   2078  1.264.4.55     skrll 	maxp = UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize);
   2079  1.264.4.55     skrll 	KASSERT(maxp != 0);
   2080  1.264.4.55     skrll 
   2081  1.264.4.70     skrll 	int addr = xfer->ux_pipe->up_dev->ud_addr;
   2082  1.264.4.70     skrll 	int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;
   2083  1.264.4.70     skrll 
   2084  1.264.4.55     skrll 	status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE);
   2085  1.264.4.55     skrll 	if (pipe->up_dev->ud_speed == USB_SPEED_LOW)
   2086  1.264.4.55     skrll 		status |= UHCI_TD_LS;
   2087  1.264.4.55     skrll 	if (flags & USBD_SHORT_XFER_OK)
   2088  1.264.4.55     skrll 		status |= UHCI_TD_SPD;
   2089  1.264.4.55     skrll 	usb_syncmem(dma, 0, len,
   2090  1.264.4.55     skrll 	    isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
   2091  1.264.4.55     skrll 	std = prev = NULL;
   2092  1.264.4.70     skrll 	for (i = 0; len != 0 && i < uxfer->ux_nstd; i++, prev = std) {
   2093  1.264.4.55     skrll 		int l = len;
   2094  1.264.4.55     skrll 		std = uxfer->ux_stds[i];
   2095  1.264.4.55     skrll 		if (l > maxp)
   2096  1.264.4.55     skrll 			l = maxp;
   2097  1.264.4.55     skrll 
   2098  1.264.4.55     skrll 		if (prev) {
   2099  1.264.4.55     skrll 			prev->link.std = std;
   2100  1.264.4.55     skrll 			prev->td.td_link = htole32(
   2101  1.264.4.55     skrll 			    std->physaddr | UHCI_PTR_VF | UHCI_PTR_TD
   2102  1.264.4.55     skrll 			    );
   2103  1.264.4.55     skrll 			usb_syncmem(&prev->dma, prev->offs, sizeof(prev->td),
   2104  1.264.4.55     skrll 			    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2105  1.264.4.55     skrll 		}
   2106  1.264.4.55     skrll 
   2107  1.264.4.55     skrll 		usb_syncmem(&std->dma, std->offs, sizeof(std->td),
   2108  1.264.4.55     skrll 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   2109  1.264.4.55     skrll 
   2110  1.264.4.70     skrll 		std->td.td_link = htole32(UHCI_PTR_T | UHCI_PTR_VF | UHCI_PTR_TD);
   2111  1.264.4.55     skrll 		std->td.td_status = htole32(status);
   2112  1.264.4.70     skrll 		std->td.td_token = htole32(
   2113  1.264.4.70     skrll 		    UHCI_TD_SET_ENDPT(UE_GET_ADDR(endpt)) |
   2114  1.264.4.70     skrll 		    UHCI_TD_SET_DEVADDR(addr) |
   2115  1.264.4.55     skrll 		    UHCI_TD_SET_PID(isread ? UHCI_TD_PID_IN : UHCI_TD_PID_OUT) |
   2116  1.264.4.55     skrll 		    UHCI_TD_SET_DT(tog) |
   2117  1.264.4.55     skrll 		    UHCI_TD_SET_MAXLEN(l)
   2118  1.264.4.55     skrll 		    );
   2119  1.264.4.70     skrll 		std->td.td_buffer = htole32(DMAADDR(dma, i * maxp));
   2120  1.264.4.70     skrll 
   2121  1.264.4.70     skrll 		std->link.std = NULL;
   2122  1.264.4.55     skrll 
   2123  1.264.4.55     skrll 		usb_syncmem(&std->dma, std->offs, sizeof(std->td),
   2124  1.264.4.55     skrll 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2125  1.264.4.55     skrll 		tog ^= 1;
   2126  1.264.4.55     skrll 
   2127  1.264.4.55     skrll 		len -= l;
   2128  1.264.4.55     skrll 	}
   2129  1.264.4.55     skrll 	KASSERTMSG(len == 0, "xfer %p alen %d len %d mps %d ux_nqtd %zu i %zu",
   2130  1.264.4.55     skrll 	    xfer, length, len, maxp, uxfer->ux_nstd, i);
   2131  1.264.4.55     skrll 
   2132  1.264.4.70     skrll 	if (!isread &&
   2133  1.264.4.70     skrll 	    (flags & USBD_FORCE_SHORT_XFER) &&
   2134  1.264.4.70     skrll 	    length % maxp == 0) {
   2135  1.264.4.70     skrll 		/* Force a 0 length transfer at the end. */
   2136  1.264.4.70     skrll 		KASSERTMSG(i < uxfer->ux_nstd, "i=%zu nstd=%zu", i,
   2137  1.264.4.70     skrll 		    uxfer->ux_nstd);
   2138  1.264.4.70     skrll 		std = uxfer->ux_stds[i++];
   2139  1.264.4.70     skrll 
   2140  1.264.4.70     skrll 		std->td.td_link = htole32(UHCI_PTR_T | UHCI_PTR_VF | UHCI_PTR_TD);
   2141  1.264.4.70     skrll 		std->td.td_status = htole32(status);
   2142  1.264.4.70     skrll 		std->td.td_token = htole32(
   2143  1.264.4.70     skrll 		    UHCI_TD_SET_ENDPT(UE_GET_ADDR(endpt)) |
   2144  1.264.4.70     skrll 		    UHCI_TD_SET_DEVADDR(addr) |
   2145  1.264.4.70     skrll 		    UHCI_TD_SET_PID(UHCI_TD_PID_OUT) |
   2146  1.264.4.70     skrll 		    UHCI_TD_SET_DT(tog) |
   2147  1.264.4.70     skrll 		    UHCI_TD_SET_MAXLEN(0)
   2148  1.264.4.70     skrll 		    );
   2149  1.264.4.70     skrll 		std->td.td_buffer = 0;
   2150  1.264.4.55     skrll 		usb_syncmem(&std->dma, std->offs, sizeof(std->td),
   2151  1.264.4.55     skrll 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2152  1.264.4.70     skrll 
   2153  1.264.4.70     skrll 		std->link.std = NULL;
   2154  1.264.4.70     skrll 		if (prev) {
   2155  1.264.4.70     skrll 			prev->link.std = std;
   2156  1.264.4.70     skrll 			prev->td.td_link = htole32(
   2157  1.264.4.70     skrll 			    std->physaddr | UHCI_PTR_VF | UHCI_PTR_TD
   2158  1.264.4.70     skrll 			    );
   2159  1.264.4.70     skrll 			usb_syncmem(&prev->dma, prev->offs, sizeof(prev->td),
   2160  1.264.4.70     skrll 			    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2161  1.264.4.70     skrll 		}
   2162  1.264.4.70     skrll 		tog ^= 1;
   2163  1.264.4.55     skrll 	}
   2164  1.264.4.55     skrll 	*lstd = std;
   2165  1.264.4.55     skrll 	*toggle = tog;
   2166  1.264.4.55     skrll }
   2167  1.264.4.55     skrll 
   2168        1.38  augustss void
   2169  1.264.4.25     skrll uhci_device_clear_toggle(struct usbd_pipe *pipe)
   2170        1.38  augustss {
   2171  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
   2172        1.38  augustss 	upipe->nexttoggle = 0;
   2173        1.38  augustss }
   2174        1.38  augustss 
   2175        1.38  augustss void
   2176  1.264.4.25     skrll uhci_noop(struct usbd_pipe *pipe)
   2177        1.38  augustss {
   2178        1.38  augustss }
   2179        1.38  augustss 
   2180  1.264.4.55     skrll int
   2181  1.264.4.55     skrll uhci_device_bulk_init(struct usbd_xfer *xfer)
   2182  1.264.4.55     skrll {
   2183  1.264.4.55     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2184  1.264.4.55     skrll 	struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
   2185  1.264.4.55     skrll 	usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc;
   2186  1.264.4.55     skrll 	int endpt = ed->bEndpointAddress;
   2187  1.264.4.55     skrll 	int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
   2188  1.264.4.55     skrll 	int len = xfer->ux_bufsize;
   2189  1.264.4.55     skrll 	int err = 0;
   2190  1.264.4.55     skrll 
   2191  1.264.4.55     skrll 
   2192  1.264.4.55     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2193  1.264.4.55     skrll 	DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, len, xfer->ux_flags, 0);
   2194  1.264.4.55     skrll 
   2195  1.264.4.55     skrll 	if (sc->sc_dying)
   2196  1.264.4.55     skrll 		return USBD_IOERROR;
   2197  1.264.4.55     skrll 
   2198  1.264.4.55     skrll 	KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
   2199  1.264.4.55     skrll 
   2200  1.264.4.55     skrll 	uxfer->ux_type = UX_BULK;
   2201  1.264.4.70     skrll 	err = uhci_alloc_std_chain(sc, xfer, len, isread, &uxfer->ux_stdstart);
   2202  1.264.4.55     skrll 	if (err)
   2203  1.264.4.55     skrll 		return err;
   2204  1.264.4.55     skrll 
   2205  1.264.4.55     skrll #ifdef UHCI_DEBUG
   2206  1.264.4.55     skrll 	if (uhcidebug >= 10) {
   2207  1.264.4.55     skrll 		DPRINTF("--- dump start ---", 0, 0, 0, 0);
   2208  1.264.4.55     skrll 		uhci_dump_tds(uxfer->ux_stdstart);
   2209  1.264.4.55     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   2210  1.264.4.55     skrll 	}
   2211  1.264.4.55     skrll #endif
   2212  1.264.4.55     skrll 
   2213  1.264.4.55     skrll 	return 0;
   2214  1.264.4.55     skrll }
   2215  1.264.4.55     skrll 
   2216  1.264.4.55     skrll Static void
   2217  1.264.4.55     skrll uhci_device_bulk_fini(struct usbd_xfer *xfer)
   2218  1.264.4.55     skrll {
   2219  1.264.4.55     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2220  1.264.4.55     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   2221  1.264.4.55     skrll 
   2222  1.264.4.55     skrll 	KASSERT(ux->ux_type == UX_BULK);
   2223  1.264.4.55     skrll 
   2224  1.264.4.80     skrll 	if (ux->ux_nstd) {
   2225  1.264.4.80     skrll 		uhci_free_stds(sc, ux);
   2226  1.264.4.55     skrll 		kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd);
   2227  1.264.4.80     skrll 	}
   2228  1.264.4.55     skrll }
   2229  1.264.4.55     skrll 
   2230         1.1  augustss usbd_status
   2231  1.264.4.25     skrll uhci_device_bulk_transfer(struct usbd_xfer *xfer)
   2232         1.1  augustss {
   2233  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2234        1.63  augustss 	usbd_status err;
   2235        1.16  augustss 
   2236        1.52  augustss 	/* Insert last in queue. */
   2237       1.248       mrg 	mutex_enter(&sc->sc_lock);
   2238        1.63  augustss 	err = usb_insert_transfer(xfer);
   2239       1.248       mrg 	mutex_exit(&sc->sc_lock);
   2240        1.63  augustss 	if (err)
   2241  1.264.4.13     skrll 		return err;
   2242        1.52  augustss 
   2243       1.152  augustss 	/*
   2244        1.92  augustss 	 * Pipe isn't running (otherwise err would be USBD_INPROG),
   2245        1.92  augustss 	 * so start it first.
   2246        1.67  augustss 	 */
   2247  1.264.4.13     skrll 	return uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
   2248        1.16  augustss }
   2249        1.16  augustss 
   2250        1.16  augustss usbd_status
   2251  1.264.4.25     skrll uhci_device_bulk_start(struct usbd_xfer *xfer)
   2252        1.16  augustss {
   2253  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   2254  1.264.4.39     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   2255  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2256        1.55  augustss 	uhci_soft_td_t *data, *dataend;
   2257         1.1  augustss 	uhci_soft_qh_t *sqh;
   2258  1.264.4.55     skrll 	int len;
   2259  1.264.4.55     skrll 	int endpt;
   2260  1.264.4.55     skrll 	int isread;
   2261         1.1  augustss 
   2262  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2263  1.264.4.55     skrll 	DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length,
   2264  1.264.4.55     skrll 	    xfer->ux_flags, 0);
   2265         1.1  augustss 
   2266        1.82  augustss 	if (sc->sc_dying)
   2267  1.264.4.13     skrll 		return USBD_IOERROR;
   2268        1.82  augustss 
   2269  1.264.4.31     skrll 	KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
   2270  1.264.4.55     skrll 	KASSERT(xfer->ux_length <= xfer->ux_bufsize);
   2271       1.248       mrg 
   2272   1.264.4.7     skrll 	len = xfer->ux_length;
   2273   1.264.4.7     skrll 	endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
   2274        1.45  augustss 	isread = UE_GET_DIR(endpt) == UE_DIR_IN;
   2275  1.264.4.33     skrll 	sqh = upipe->bulk.sqh;
   2276         1.1  augustss 
   2277  1.264.4.55     skrll 	/* Take lock here to protect nexttoggle */
   2278  1.264.4.55     skrll 	mutex_enter(&sc->sc_lock);
   2279         1.1  augustss 
   2280  1.264.4.55     skrll 	uhci_reset_std_chain(sc, xfer, len, isread, &upipe->nexttoggle,
   2281  1.264.4.58     skrll 	    &dataend);
   2282  1.264.4.55     skrll 
   2283  1.264.4.55     skrll 	data = ux->ux_stdstart;
   2284  1.264.4.55     skrll 	ux->ux_stdend = dataend;
   2285        1.88   tsutsui 	dataend->td.td_status |= htole32(UHCI_TD_IOC);
   2286       1.223    bouyer 	usb_syncmem(&dataend->dma,
   2287       1.223    bouyer 	    dataend->offs + offsetof(uhci_td_t, td_status),
   2288       1.223    bouyer 	    sizeof(dataend->td.td_status),
   2289       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2290       1.223    bouyer 
   2291        1.59  augustss #ifdef UHCI_DEBUG
   2292  1.264.4.55     skrll 	if (uhcidebug >= 10) {
   2293  1.264.4.47     skrll 		DPRINTF("--- dump start ---", 0, 0, 0, 0);
   2294  1.264.4.55     skrll 		DPRINTFN(10, "before transfer", 0, 0, 0, 0);
   2295  1.264.4.58     skrll 		uhci_dump_tds(data);
   2296  1.264.4.47     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   2297         1.1  augustss 	}
   2298         1.1  augustss #endif
   2299         1.1  augustss 
   2300  1.264.4.41     skrll 	KASSERT(ux->ux_isdone);
   2301         1.7  augustss #ifdef DIAGNOSTIC
   2302  1.264.4.41     skrll 	ux->ux_isdone = false;
   2303         1.7  augustss #endif
   2304         1.1  augustss 
   2305        1.55  augustss 	sqh->elink = data;
   2306       1.121  augustss 	sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD);
   2307       1.223    bouyer 	/* uhci_add_bulk() will do usb_syncmem(sqh) */
   2308         1.1  augustss 
   2309         1.1  augustss 	uhci_add_bulk(sc, sqh);
   2310  1.264.4.56     skrll 	uhci_add_intr_list(sc, ux);
   2311         1.1  augustss 
   2312   1.264.4.7     skrll 	if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
   2313   1.264.4.7     skrll 		callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
   2314  1.264.4.39     skrll 			    uhci_timeout, xfer);
   2315        1.13  augustss 	}
   2316   1.264.4.7     skrll 	xfer->ux_status = USBD_IN_PROGRESS;
   2317  1.264.4.55     skrll 	mutex_exit(&sc->sc_lock);
   2318         1.1  augustss 
   2319  1.264.4.13     skrll 	return USBD_IN_PROGRESS;
   2320         1.1  augustss }
   2321         1.1  augustss 
   2322         1.1  augustss /* Abort a device bulk request. */
   2323         1.1  augustss void
   2324  1.264.4.25     skrll uhci_device_bulk_abort(struct usbd_xfer *xfer)
   2325         1.1  augustss {
   2326  1.264.4.37     skrll 	uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer);
   2327       1.248       mrg 
   2328       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2329       1.248       mrg 
   2330  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2331  1.264.4.21     skrll 
   2332        1.66  augustss 	uhci_abort_xfer(xfer, USBD_CANCELLED);
   2333        1.33  augustss }
   2334        1.33  augustss 
   2335        1.92  augustss /*
   2336  1.264.4.79     skrll  * Cancel or timeout a device request.  We have two cases to deal with
   2337  1.264.4.79     skrll  *
   2338  1.264.4.79     skrll  * 1) A driver wants to stop scheduled or inflight transfers
   2339  1.264.4.79     skrll  * 2) A transfer has timed out
   2340  1.264.4.79     skrll  *
   2341       1.154  augustss  * It's impossible to guarantee that the requested transfer will not
   2342  1.264.4.79     skrll  * have (partially) happened since the hardware runs concurrently.
   2343  1.264.4.79     skrll  *
   2344  1.264.4.79     skrll  * Transfer state is protected by the bus lock and we set the transfer status
   2345  1.264.4.79     skrll  * as soon as either of the above happens (with bus lock held).
   2346  1.264.4.79     skrll  *
   2347  1.264.4.79     skrll  * To allow the hardware time to notice we simply wait.
   2348        1.92  augustss  */
   2349        1.33  augustss void
   2350  1.264.4.25     skrll uhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status)
   2351        1.33  augustss {
   2352  1.264.4.39     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   2353  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   2354  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2355        1.33  augustss 	uhci_soft_td_t *std;
   2356       1.188  augustss 	int wake;
   2357        1.65  augustss 
   2358  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2359  1.264.4.21     skrll 	DPRINTFN(1,"xfer=%p, status=%d", xfer, status, 0, 0);
   2360        1.33  augustss 
   2361       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2362   1.264.4.3     skrll 	ASSERT_SLEEPABLE();
   2363       1.248       mrg 
   2364       1.153  augustss 	if (sc->sc_dying) {
   2365       1.153  augustss 		/* If we're dying, just do the software part. */
   2366   1.264.4.7     skrll 		xfer->ux_status = status;	/* make software ignore it */
   2367   1.264.4.7     skrll 		callout_stop(&xfer->ux_callout);
   2368       1.153  augustss 		usb_transfer_complete(xfer);
   2369       1.194  christos 		return;
   2370        1.92  augustss 	}
   2371        1.92  augustss 
   2372       1.153  augustss 	/*
   2373       1.188  augustss 	 * If an abort is already in progress then just wait for it to
   2374       1.188  augustss 	 * complete and return.
   2375       1.188  augustss 	 */
   2376   1.264.4.7     skrll 	if (xfer->ux_hcflags & UXFER_ABORTING) {
   2377  1.264.4.21     skrll 		DPRINTFN(2, "already aborting", 0, 0, 0, 0);
   2378       1.188  augustss #ifdef DIAGNOSTIC
   2379       1.188  augustss 		if (status == USBD_TIMEOUT)
   2380  1.264.4.65     skrll 			printf("%s: TIMEOUT while aborting\n", __func__);
   2381       1.188  augustss #endif
   2382       1.188  augustss 		/* Override the status which might be USBD_TIMEOUT. */
   2383   1.264.4.7     skrll 		xfer->ux_status = status;
   2384  1.264.4.21     skrll 		DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0);
   2385   1.264.4.7     skrll 		xfer->ux_hcflags |= UXFER_ABORTWAIT;
   2386   1.264.4.7     skrll 		while (xfer->ux_hcflags & UXFER_ABORTING)
   2387   1.264.4.7     skrll 			cv_wait(&xfer->ux_hccv, &sc->sc_lock);
   2388       1.248       mrg 		goto done;
   2389       1.188  augustss 	}
   2390   1.264.4.7     skrll 	xfer->ux_hcflags |= UXFER_ABORTING;
   2391       1.188  augustss 
   2392       1.188  augustss 	/*
   2393  1.264.4.79     skrll 	 * Step 1: When cancelling a transfer make sure the timeout handler
   2394  1.264.4.79     skrll 	 * didn't run or ran to the end and saw the USBD_CANCELLED status.
   2395  1.264.4.79     skrll 	 * Otherwise we must have got here via a timeout.
   2396  1.264.4.79     skrll 	 */
   2397  1.264.4.79     skrll 	if (status == USBD_CANCELLED) {
   2398  1.264.4.79     skrll 		xfer->ux_status = status;
   2399  1.264.4.79     skrll 		callout_halt(&xfer->ux_callout, &sc->sc_lock);
   2400  1.264.4.79     skrll 	} else {
   2401  1.264.4.79     skrll 		KASSERT(xfer->ux_status == USBD_TIMEOUT);
   2402  1.264.4.79     skrll 	}
   2403  1.264.4.79     skrll 
   2404  1.264.4.79     skrll 	/*
   2405  1.264.4.79     skrll 	 * Step 2: Make interrupt routine and hardware ignore xfer.
   2406       1.153  augustss 	 */
   2407  1.264.4.61     skrll 	uhci_del_intr_list(sc, ux);
   2408  1.264.4.61     skrll 
   2409  1.264.4.39     skrll 	DPRINTF("stop ux=%p", ux, 0, 0, 0);
   2410  1.264.4.41     skrll 	for (std = ux->ux_stdstart; std != NULL; std = std->link.std) {
   2411       1.223    bouyer 		usb_syncmem(&std->dma,
   2412       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_status),
   2413       1.223    bouyer 		    sizeof(std->td.td_status),
   2414       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   2415        1.92  augustss 		std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC));
   2416       1.223    bouyer 		usb_syncmem(&std->dma,
   2417       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_status),
   2418       1.223    bouyer 		    sizeof(std->td.td_status),
   2419       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2420       1.223    bouyer 	}
   2421        1.92  augustss 
   2422       1.162  augustss 	/*
   2423  1.264.4.79     skrll 	 * Step 3: Wait until we know hardware has finished any possible
   2424       1.153  augustss 	 * use of the xfer.  Also make sure the soft interrupt routine
   2425       1.153  augustss 	 * has run.
   2426       1.153  augustss 	 */
   2427       1.248       mrg 	/* Hardware finishes in 1ms */
   2428   1.264.4.7     skrll 	usb_delay_ms_locked(upipe->pipe.up_dev->ud_bus, 2, &sc->sc_lock);
   2429       1.162  augustss 
   2430       1.153  augustss 	/*
   2431  1.264.4.79     skrll 	 * Step 4: Execute callback.
   2432       1.153  augustss 	 */
   2433  1.264.4.27     skrll 	DPRINTF("callback", 0, 0, 0, 0);
   2434       1.100  augustss #ifdef DIAGNOSTIC
   2435  1.264.4.41     skrll 	ux->ux_isdone = true;
   2436       1.100  augustss #endif
   2437   1.264.4.7     skrll 	wake = xfer->ux_hcflags & UXFER_ABORTWAIT;
   2438   1.264.4.7     skrll 	xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT);
   2439       1.106  augustss 	usb_transfer_complete(xfer);
   2440       1.188  augustss 	if (wake)
   2441   1.264.4.7     skrll 		cv_broadcast(&xfer->ux_hccv);
   2442       1.248       mrg done:
   2443       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2444         1.1  augustss }
   2445         1.1  augustss 
   2446         1.1  augustss /* Close a device bulk pipe. */
   2447         1.1  augustss void
   2448  1.264.4.25     skrll uhci_device_bulk_close(struct usbd_pipe *pipe)
   2449         1.1  augustss {
   2450  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
   2451  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
   2452         1.1  augustss 
   2453       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2454       1.248       mrg 
   2455  1.264.4.33     skrll 	uhci_free_sqh(sc, upipe->bulk.sqh);
   2456       1.236  drochner 
   2457   1.264.4.7     skrll 	pipe->up_endpoint->ue_toggle = upipe->nexttoggle;
   2458         1.1  augustss }
   2459         1.1  augustss 
   2460  1.264.4.55     skrll int
   2461  1.264.4.55     skrll uhci_device_ctrl_init(struct usbd_xfer *xfer)
   2462         1.1  augustss {
   2463  1.264.4.55     skrll 	struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
   2464  1.264.4.55     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   2465  1.264.4.55     skrll 	usb_device_request_t *req = &xfer->ux_request;
   2466  1.264.4.55     skrll 	struct usbd_device *dev = upipe->pipe.up_dev;
   2467  1.264.4.55     skrll 	uhci_softc_t *sc = dev->ud_bus->ub_hcpriv;
   2468  1.264.4.76     skrll 	uhci_soft_td_t *data = NULL;
   2469  1.264.4.55     skrll 	int len;
   2470        1.63  augustss 	usbd_status err;
   2471  1.264.4.55     skrll 	int isread;
   2472        1.16  augustss 
   2473  1.264.4.55     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2474  1.264.4.70     skrll 	DPRINTFN(3, "xfer=%p len=%d, addr=%d, endpt=%d", xfer, xfer->ux_bufsize,
   2475  1.264.4.71     skrll 	    dev->ud_addr, upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress);
   2476        1.16  augustss 
   2477  1.264.4.55     skrll 	isread = req->bmRequestType & UT_READ;
   2478  1.264.4.55     skrll 	len = xfer->ux_bufsize;
   2479         1.1  augustss 
   2480  1.264.4.55     skrll 	uxfer->ux_type = UX_CTRL;
   2481  1.264.4.55     skrll 	/* Set up data transaction */
   2482  1.264.4.55     skrll 	if (len != 0) {
   2483  1.264.4.70     skrll 		err = uhci_alloc_std_chain(sc, xfer, len, isread, &data);
   2484  1.264.4.55     skrll 		if (err)
   2485  1.264.4.55     skrll 			return err;
   2486  1.264.4.55     skrll 	}
   2487  1.264.4.55     skrll 	/* Set up interrupt info. */
   2488  1.264.4.70     skrll 	uxfer->ux_setup = upipe->ctrl.setup;
   2489  1.264.4.70     skrll 	uxfer->ux_stat = upipe->ctrl.stat;
   2490  1.264.4.55     skrll 	uxfer->ux_data = data;
   2491  1.264.4.55     skrll 
   2492  1.264.4.55     skrll 	return 0;
   2493  1.264.4.55     skrll }
   2494  1.264.4.55     skrll 
   2495  1.264.4.55     skrll Static void
   2496  1.264.4.55     skrll uhci_device_ctrl_fini(struct usbd_xfer *xfer)
   2497  1.264.4.55     skrll {
   2498  1.264.4.55     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2499  1.264.4.55     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   2500  1.264.4.55     skrll 
   2501  1.264.4.55     skrll 	KASSERT(ux->ux_type == UX_CTRL);
   2502  1.264.4.55     skrll 
   2503  1.264.4.80     skrll 	if (ux->ux_nstd) {
   2504  1.264.4.80     skrll 		uhci_free_stds(sc, ux);
   2505  1.264.4.55     skrll 		kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd);
   2506  1.264.4.80     skrll 	}
   2507  1.264.4.55     skrll }
   2508  1.264.4.55     skrll 
   2509  1.264.4.55     skrll usbd_status
   2510  1.264.4.55     skrll uhci_device_ctrl_transfer(struct usbd_xfer *xfer)
   2511  1.264.4.55     skrll {
   2512  1.264.4.55     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2513  1.264.4.55     skrll 	usbd_status err;
   2514  1.264.4.55     skrll 
   2515  1.264.4.55     skrll 	/* Insert last in queue. */
   2516  1.264.4.55     skrll 	mutex_enter(&sc->sc_lock);
   2517  1.264.4.55     skrll 	err = usb_insert_transfer(xfer);
   2518  1.264.4.55     skrll 	mutex_exit(&sc->sc_lock);
   2519  1.264.4.55     skrll 	if (err)
   2520  1.264.4.55     skrll 		return err;
   2521  1.264.4.55     skrll 
   2522  1.264.4.55     skrll 	/*
   2523  1.264.4.55     skrll 	 * Pipe isn't running (otherwise err would be USBD_INPROG),
   2524  1.264.4.55     skrll 	 * so start it first.
   2525  1.264.4.55     skrll 	 */
   2526  1.264.4.55     skrll 	return uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
   2527  1.264.4.55     skrll }
   2528  1.264.4.55     skrll 
   2529  1.264.4.55     skrll usbd_status
   2530  1.264.4.55     skrll uhci_device_ctrl_start(struct usbd_xfer *xfer)
   2531  1.264.4.55     skrll {
   2532  1.264.4.55     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2533  1.264.4.55     skrll 	struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
   2534  1.264.4.55     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   2535  1.264.4.55     skrll 	usb_device_request_t *req = &xfer->ux_request;
   2536  1.264.4.55     skrll 	struct usbd_device *dev = upipe->pipe.up_dev;
   2537  1.264.4.55     skrll 	int addr = dev->ud_addr;
   2538  1.264.4.55     skrll 	int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
   2539  1.264.4.55     skrll 	uhci_soft_td_t *setup, *stat, *next, *dataend;
   2540  1.264.4.55     skrll 	uhci_soft_qh_t *sqh;
   2541  1.264.4.55     skrll 	int len;
   2542  1.264.4.55     skrll 	int isread;
   2543  1.264.4.55     skrll 
   2544  1.264.4.55     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2545  1.264.4.55     skrll 
   2546  1.264.4.55     skrll 	if (sc->sc_dying)
   2547  1.264.4.55     skrll 		return USBD_IOERROR;
   2548  1.264.4.55     skrll 
   2549  1.264.4.55     skrll 	KASSERT(xfer->ux_rqflags & URQ_REQUEST);
   2550  1.264.4.55     skrll 
   2551  1.264.4.55     skrll 	DPRINTFN(3, "type=0x%02x, request=0x%02x, "
   2552  1.264.4.55     skrll 	    "wValue=0x%04x, wIndex=0x%04x",
   2553  1.264.4.55     skrll 	    req->bmRequestType, req->bRequest, UGETW(req->wValue),
   2554  1.264.4.55     skrll 	    UGETW(req->wIndex));
   2555  1.264.4.55     skrll 	DPRINTFN(3, "len=%d, addr=%d, endpt=%d",
   2556  1.264.4.55     skrll 	    UGETW(req->wLength), dev->ud_addr, endpt, 0);
   2557  1.264.4.55     skrll 
   2558  1.264.4.55     skrll 	isread = req->bmRequestType & UT_READ;
   2559  1.264.4.55     skrll 	len = UGETW(req->wLength);
   2560  1.264.4.55     skrll 
   2561  1.264.4.55     skrll 	setup = upipe->ctrl.setup;
   2562  1.264.4.55     skrll 	stat = upipe->ctrl.stat;
   2563  1.264.4.55     skrll 	sqh = upipe->ctrl.sqh;
   2564  1.264.4.55     skrll 
   2565  1.264.4.55     skrll 	memcpy(KERNADDR(&upipe->ctrl.reqdma, 0), req, sizeof(*req));
   2566  1.264.4.55     skrll 	usb_syncmem(&upipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE);
   2567  1.264.4.55     skrll 
   2568  1.264.4.55     skrll 	mutex_enter(&sc->sc_lock);
   2569  1.264.4.55     skrll 
   2570  1.264.4.55     skrll 	/* Set up data transaction */
   2571  1.264.4.55     skrll 	if (len != 0) {
   2572  1.264.4.55     skrll 		upipe->nexttoggle = 1;
   2573  1.264.4.55     skrll 		next = uxfer->ux_data;
   2574  1.264.4.55     skrll 		uhci_reset_std_chain(sc, xfer, len, isread,
   2575  1.264.4.58     skrll 		    &upipe->nexttoggle, &dataend);
   2576  1.264.4.55     skrll 		dataend->link.std = stat;
   2577  1.264.4.55     skrll 		dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD);
   2578  1.264.4.55     skrll 		usb_syncmem(&dataend->dma,
   2579  1.264.4.55     skrll 		    dataend->offs + offsetof(uhci_td_t, td_link),
   2580  1.264.4.55     skrll 		    sizeof(dataend->td.td_link),
   2581  1.264.4.55     skrll 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2582  1.264.4.55     skrll 	} else {
   2583  1.264.4.55     skrll 		next = stat;
   2584  1.264.4.55     skrll 	}
   2585  1.264.4.55     skrll 
   2586  1.264.4.70     skrll 	const uint32_t status = UHCI_TD_ZERO_ACTLEN(
   2587  1.264.4.55     skrll 	    UHCI_TD_SET_ERRCNT(3) |
   2588  1.264.4.70     skrll 	    UHCI_TD_ACTIVE |
   2589  1.264.4.70     skrll 	    (dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0)
   2590  1.264.4.55     skrll 	    );
   2591  1.264.4.70     skrll 	setup->link.std = next;
   2592  1.264.4.70     skrll 	setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD);
   2593  1.264.4.70     skrll 	setup->td.td_status = htole32(status);
   2594  1.264.4.70     skrll 	setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof(*req), endpt, addr));
   2595  1.264.4.70     skrll 	setup->td.td_buffer = htole32(DMAADDR(&upipe->ctrl.reqdma, 0));
   2596  1.264.4.70     skrll 
   2597  1.264.4.55     skrll 	usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td),
   2598  1.264.4.55     skrll 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2599  1.264.4.55     skrll 
   2600  1.264.4.55     skrll 	stat->link.std = NULL;
   2601  1.264.4.55     skrll 	stat->td.td_link = htole32(UHCI_PTR_T);
   2602  1.264.4.70     skrll 	stat->td.td_status = htole32(status | UHCI_TD_IOC);
   2603  1.264.4.55     skrll 	stat->td.td_token =
   2604  1.264.4.55     skrll 		htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) :
   2605  1.264.4.55     skrll 				 UHCI_TD_IN (0, endpt, addr, 1));
   2606  1.264.4.55     skrll 	stat->td.td_buffer = htole32(0);
   2607  1.264.4.55     skrll 	usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td),
   2608  1.264.4.55     skrll 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2609  1.264.4.55     skrll 
   2610  1.264.4.55     skrll #ifdef UHCI_DEBUG
   2611  1.264.4.55     skrll 	if (uhcidebug >= 10) {
   2612  1.264.4.55     skrll 		DPRINTF("--- dump start ---", 0, 0, 0, 0);
   2613  1.264.4.55     skrll 		DPRINTF("before transfer", 0, 0, 0, 0);
   2614  1.264.4.55     skrll 		uhci_dump_tds(setup);
   2615  1.264.4.55     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   2616  1.264.4.55     skrll 	}
   2617  1.264.4.55     skrll #endif
   2618  1.264.4.55     skrll 
   2619  1.264.4.55     skrll 	/* Set up interrupt info. */
   2620  1.264.4.55     skrll 	uxfer->ux_setup = setup;
   2621  1.264.4.55     skrll 	uxfer->ux_stat = stat;
   2622  1.264.4.55     skrll 	KASSERT(uxfer->ux_isdone);
   2623  1.264.4.55     skrll #ifdef DIAGNOSTIC
   2624  1.264.4.55     skrll 	uxfer->ux_isdone = false;
   2625  1.264.4.55     skrll #endif
   2626  1.264.4.55     skrll 
   2627  1.264.4.55     skrll 	sqh->elink = setup;
   2628  1.264.4.55     skrll 	sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD);
   2629  1.264.4.55     skrll 	/* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */
   2630  1.264.4.55     skrll 
   2631  1.264.4.55     skrll 	if (dev->ud_speed == USB_SPEED_LOW)
   2632  1.264.4.55     skrll 		uhci_add_ls_ctrl(sc, sqh);
   2633  1.264.4.55     skrll 	else
   2634  1.264.4.55     skrll 		uhci_add_hs_ctrl(sc, sqh);
   2635  1.264.4.56     skrll 	uhci_add_intr_list(sc, uxfer);
   2636  1.264.4.55     skrll #ifdef UHCI_DEBUG
   2637  1.264.4.55     skrll 	if (uhcidebug >= 12) {
   2638  1.264.4.55     skrll 		uhci_soft_td_t *std;
   2639  1.264.4.55     skrll 		uhci_soft_qh_t *xqh;
   2640  1.264.4.55     skrll 		uhci_soft_qh_t *sxqh;
   2641  1.264.4.55     skrll 		int maxqh = 0;
   2642  1.264.4.55     skrll 		uhci_physaddr_t link;
   2643  1.264.4.55     skrll 		DPRINTFN(12, "--- dump start ---", 0, 0, 0, 0);
   2644  1.264.4.55     skrll 		DPRINTFN(12, "follow from [0]", 0, 0, 0, 0);
   2645  1.264.4.55     skrll 		for (std = sc->sc_vframes[0].htd, link = 0;
   2646  1.264.4.55     skrll 		     (link & UHCI_PTR_QH) == 0;
   2647  1.264.4.55     skrll 		     std = std->link.std) {
   2648  1.264.4.55     skrll 			link = le32toh(std->td.td_link);
   2649  1.264.4.55     skrll 			uhci_dump_td(std);
   2650  1.264.4.55     skrll 		}
   2651  1.264.4.55     skrll 		sxqh = (uhci_soft_qh_t *)std;
   2652  1.264.4.55     skrll 		uhci_dump_qh(sxqh);
   2653  1.264.4.55     skrll 		for (xqh = sxqh;
   2654  1.264.4.55     skrll 		     xqh != NULL;
   2655  1.264.4.55     skrll 		     xqh = (maxqh++ == 5 || xqh->hlink == sxqh ||
   2656  1.264.4.55     skrll 			xqh->hlink == xqh ? NULL : xqh->hlink)) {
   2657  1.264.4.55     skrll 			uhci_dump_qh(xqh);
   2658  1.264.4.55     skrll 		}
   2659  1.264.4.55     skrll 		DPRINTFN(12, "Enqueued QH:", 0, 0, 0, 0);
   2660  1.264.4.55     skrll 		uhci_dump_qh(sqh);
   2661  1.264.4.55     skrll 		uhci_dump_tds(sqh->elink);
   2662  1.264.4.55     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   2663  1.264.4.55     skrll 	}
   2664  1.264.4.55     skrll #endif
   2665  1.264.4.55     skrll 	if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
   2666  1.264.4.55     skrll 		callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
   2667  1.264.4.55     skrll 			    uhci_timeout, xfer);
   2668  1.264.4.55     skrll 	}
   2669  1.264.4.55     skrll 	xfer->ux_status = USBD_IN_PROGRESS;
   2670  1.264.4.55     skrll 	mutex_exit(&sc->sc_lock);
   2671  1.264.4.55     skrll 
   2672  1.264.4.13     skrll 	return USBD_IN_PROGRESS;
   2673         1.1  augustss }
   2674         1.1  augustss 
   2675  1.264.4.55     skrll int
   2676  1.264.4.55     skrll uhci_device_intr_init(struct usbd_xfer *xfer)
   2677  1.264.4.55     skrll {
   2678  1.264.4.55     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2679  1.264.4.55     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   2680  1.264.4.55     skrll 	usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc;
   2681  1.264.4.55     skrll 	int endpt = ed->bEndpointAddress;
   2682  1.264.4.55     skrll 	int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
   2683  1.264.4.55     skrll 	int len = xfer->ux_bufsize;
   2684  1.264.4.55     skrll 	int err;
   2685  1.264.4.55     skrll 
   2686  1.264.4.55     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2687  1.264.4.55     skrll 
   2688  1.264.4.55     skrll 	DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length,
   2689  1.264.4.55     skrll 	    xfer->ux_flags, 0);
   2690  1.264.4.55     skrll 
   2691  1.264.4.55     skrll 	KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
   2692  1.264.4.55     skrll 	KASSERT(len != 0);
   2693  1.264.4.55     skrll 
   2694  1.264.4.55     skrll 	ux->ux_type = UX_INTR;
   2695  1.264.4.55     skrll 	ux->ux_nstd = 0;
   2696  1.264.4.70     skrll 	err = uhci_alloc_std_chain(sc, xfer, len, isread, &ux->ux_stdstart);
   2697  1.264.4.55     skrll 
   2698  1.264.4.55     skrll 	return err;
   2699  1.264.4.55     skrll }
   2700  1.264.4.55     skrll 
   2701  1.264.4.55     skrll Static void
   2702  1.264.4.55     skrll uhci_device_intr_fini(struct usbd_xfer *xfer)
   2703  1.264.4.55     skrll {
   2704  1.264.4.55     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2705  1.264.4.55     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   2706  1.264.4.55     skrll 
   2707  1.264.4.55     skrll 	KASSERT(ux->ux_type == UX_INTR);
   2708  1.264.4.55     skrll 
   2709  1.264.4.80     skrll 	if (ux->ux_nstd) {
   2710  1.264.4.80     skrll 		uhci_free_stds(sc, ux);
   2711  1.264.4.55     skrll 		kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd);
   2712  1.264.4.80     skrll 	}
   2713  1.264.4.55     skrll }
   2714  1.264.4.55     skrll 
   2715         1.1  augustss usbd_status
   2716  1.264.4.25     skrll uhci_device_intr_transfer(struct usbd_xfer *xfer)
   2717         1.1  augustss {
   2718  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2719        1.63  augustss 	usbd_status err;
   2720        1.16  augustss 
   2721        1.52  augustss 	/* Insert last in queue. */
   2722       1.248       mrg 	mutex_enter(&sc->sc_lock);
   2723        1.63  augustss 	err = usb_insert_transfer(xfer);
   2724       1.248       mrg 	mutex_exit(&sc->sc_lock);
   2725        1.63  augustss 	if (err)
   2726  1.264.4.13     skrll 		return err;
   2727        1.52  augustss 
   2728       1.152  augustss 	/*
   2729        1.92  augustss 	 * Pipe isn't running (otherwise err would be USBD_INPROG),
   2730        1.92  augustss 	 * so start it first.
   2731        1.67  augustss 	 */
   2732  1.264.4.13     skrll 	return uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
   2733        1.16  augustss }
   2734        1.16  augustss 
   2735        1.16  augustss usbd_status
   2736  1.264.4.25     skrll uhci_device_intr_start(struct usbd_xfer *xfer)
   2737        1.16  augustss {
   2738  1.264.4.39     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   2739  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   2740  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2741        1.55  augustss 	uhci_soft_td_t *data, *dataend;
   2742         1.1  augustss 	uhci_soft_qh_t *sqh;
   2743       1.187     skrll 	int isread, endpt;
   2744       1.248       mrg 	int i;
   2745         1.1  augustss 
   2746        1.82  augustss 	if (sc->sc_dying)
   2747  1.264.4.13     skrll 		return USBD_IOERROR;
   2748        1.82  augustss 
   2749  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2750  1.264.4.21     skrll 
   2751  1.264.4.55     skrll 	DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length,
   2752  1.264.4.55     skrll 	    xfer->ux_flags, 0);
   2753         1.1  augustss 
   2754  1.264.4.31     skrll 	KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
   2755  1.264.4.55     skrll 	KASSERT(xfer->ux_length <= xfer->ux_bufsize);
   2756       1.248       mrg 
   2757   1.264.4.7     skrll 	endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
   2758       1.187     skrll 	isread = UE_GET_DIR(endpt) == UE_DIR_IN;
   2759       1.187     skrll 
   2760  1.264.4.55     skrll 	data = ux->ux_stdstart;
   2761       1.187     skrll 
   2762  1.264.4.55     skrll 	KASSERT(ux->ux_isdone);
   2763  1.264.4.55     skrll #ifdef DIAGNOSTIC
   2764  1.264.4.55     skrll 	ux->ux_isdone = false;
   2765  1.264.4.55     skrll #endif
   2766  1.264.4.55     skrll 
   2767  1.264.4.55     skrll 	/* Take lock to protect nexttoggle */
   2768  1.264.4.55     skrll 	mutex_enter(&sc->sc_lock);
   2769  1.264.4.55     skrll 	uhci_reset_std_chain(sc, xfer, xfer->ux_length, isread,
   2770  1.264.4.58     skrll 	    &upipe->nexttoggle, &dataend);
   2771       1.248       mrg 
   2772        1.88   tsutsui 	dataend->td.td_status |= htole32(UHCI_TD_IOC);
   2773       1.223    bouyer 	usb_syncmem(&dataend->dma,
   2774       1.223    bouyer 	    dataend->offs + offsetof(uhci_td_t, td_status),
   2775       1.223    bouyer 	    sizeof(dataend->td.td_status),
   2776       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2777  1.264.4.55     skrll 	ux->ux_stdend = dataend;
   2778         1.1  augustss 
   2779        1.59  augustss #ifdef UHCI_DEBUG
   2780  1.264.4.43     skrll 	if (uhcidebug >= 10) {
   2781  1.264.4.47     skrll 		DPRINTF("--- dump start ---", 0, 0, 0, 0);
   2782        1.55  augustss 		uhci_dump_tds(data);
   2783  1.264.4.33     skrll 		uhci_dump_qh(upipe->intr.qhs[0]);
   2784  1.264.4.47     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   2785         1.1  augustss 	}
   2786         1.1  augustss #endif
   2787         1.1  augustss 
   2788  1.264.4.33     skrll 	DPRINTFN(10, "qhs[0]=%p", upipe->intr.qhs[0], 0, 0, 0);
   2789  1.264.4.33     skrll 	for (i = 0; i < upipe->intr.npoll; i++) {
   2790  1.264.4.33     skrll 		sqh = upipe->intr.qhs[i];
   2791        1.55  augustss 		sqh->elink = data;
   2792       1.121  augustss 		sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD);
   2793       1.223    bouyer 		usb_syncmem(&sqh->dma,
   2794       1.223    bouyer 		    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   2795       1.223    bouyer 		    sizeof(sqh->qh.qh_elink),
   2796       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2797         1.1  augustss 	}
   2798  1.264.4.56     skrll 	uhci_add_intr_list(sc, ux);
   2799   1.264.4.7     skrll 	xfer->ux_status = USBD_IN_PROGRESS;
   2800       1.248       mrg 	mutex_exit(&sc->sc_lock);
   2801         1.1  augustss 
   2802        1.59  augustss #ifdef UHCI_DEBUG
   2803  1.264.4.43     skrll 	if (uhcidebug >= 10) {
   2804  1.264.4.47     skrll 		DPRINTF("--- dump start ---", 0, 0, 0, 0);
   2805        1.55  augustss 		uhci_dump_tds(data);
   2806  1.264.4.33     skrll 		uhci_dump_qh(upipe->intr.qhs[0]);
   2807  1.264.4.47     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   2808         1.1  augustss 	}
   2809         1.1  augustss #endif
   2810         1.1  augustss 
   2811  1.264.4.13     skrll 	return USBD_IN_PROGRESS;
   2812         1.1  augustss }
   2813         1.1  augustss 
   2814         1.1  augustss /* Abort a device control request. */
   2815         1.1  augustss void
   2816  1.264.4.25     skrll uhci_device_ctrl_abort(struct usbd_xfer *xfer)
   2817         1.1  augustss {
   2818  1.264.4.37     skrll 	uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer);
   2819       1.248       mrg 
   2820       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2821       1.248       mrg 
   2822  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2823        1.66  augustss 	uhci_abort_xfer(xfer, USBD_CANCELLED);
   2824         1.1  augustss }
   2825         1.1  augustss 
   2826         1.1  augustss /* Close a device control pipe. */
   2827         1.1  augustss void
   2828  1.264.4.25     skrll uhci_device_ctrl_close(struct usbd_pipe *pipe)
   2829         1.1  augustss {
   2830  1.264.4.55     skrll 	uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
   2831  1.264.4.55     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
   2832  1.264.4.55     skrll 
   2833  1.264.4.55     skrll 	uhci_free_sqh(sc, upipe->ctrl.sqh);
   2834  1.264.4.55     skrll 	uhci_free_std_locked(sc, upipe->ctrl.setup);
   2835  1.264.4.55     skrll 	uhci_free_std_locked(sc, upipe->ctrl.stat);
   2836  1.264.4.55     skrll 
   2837         1.1  augustss }
   2838         1.1  augustss 
   2839         1.1  augustss /* Abort a device interrupt request. */
   2840         1.1  augustss void
   2841  1.264.4.25     skrll uhci_device_intr_abort(struct usbd_xfer *xfer)
   2842         1.1  augustss {
   2843  1.264.4.37     skrll 	uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer);
   2844       1.248       mrg 
   2845       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2846   1.264.4.7     skrll 	KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
   2847       1.248       mrg 
   2848  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2849  1.264.4.27     skrll 	DPRINTF("xfer=%p", xfer, 0, 0, 0);
   2850       1.264     skrll 
   2851        1.66  augustss 	uhci_abort_xfer(xfer, USBD_CANCELLED);
   2852         1.1  augustss }
   2853         1.1  augustss 
   2854         1.1  augustss /* Close a device interrupt pipe. */
   2855         1.1  augustss void
   2856  1.264.4.25     skrll uhci_device_intr_close(struct usbd_pipe *pipe)
   2857         1.1  augustss {
   2858  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
   2859  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
   2860        1.92  augustss 	int i, npoll;
   2861       1.248       mrg 
   2862       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2863         1.1  augustss 
   2864         1.1  augustss 	/* Unlink descriptors from controller data structures. */
   2865  1.264.4.33     skrll 	npoll = upipe->intr.npoll;
   2866         1.1  augustss 	for (i = 0; i < npoll; i++)
   2867  1.264.4.33     skrll 		uhci_remove_intr(sc, upipe->intr.qhs[i]);
   2868         1.1  augustss 
   2869       1.152  augustss 	/*
   2870         1.1  augustss 	 * We now have to wait for any activity on the physical
   2871         1.1  augustss 	 * descriptors to stop.
   2872         1.1  augustss 	 */
   2873       1.248       mrg 	usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock);
   2874         1.1  augustss 
   2875  1.264.4.54     skrll 	for (i = 0; i < npoll; i++)
   2876  1.264.4.33     skrll 		uhci_free_sqh(sc, upipe->intr.qhs[i]);
   2877  1.264.4.33     skrll 	kmem_free(upipe->intr.qhs, npoll * sizeof(uhci_soft_qh_t *));
   2878         1.1  augustss }
   2879         1.1  augustss 
   2880  1.264.4.55     skrll int
   2881  1.264.4.55     skrll uhci_device_isoc_init(struct usbd_xfer *xfer)
   2882         1.1  augustss {
   2883  1.264.4.55     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   2884         1.1  augustss 
   2885  1.264.4.55     skrll 	KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
   2886  1.264.4.55     skrll 	KASSERT(xfer->ux_nframes != 0);
   2887  1.264.4.55     skrll 	KASSERT(ux->ux_isdone);
   2888         1.1  augustss 
   2889  1.264.4.55     skrll 	ux->ux_type = UX_ISOC;
   2890  1.264.4.55     skrll 	return 0;
   2891  1.264.4.55     skrll }
   2892  1.264.4.47     skrll 
   2893  1.264.4.55     skrll Static void
   2894  1.264.4.55     skrll uhci_device_isoc_fini(struct usbd_xfer *xfer)
   2895  1.264.4.55     skrll {
   2896  1.264.4.76     skrll 	struct uhci_xfer *ux __diagused = UHCI_XFER2UXFER(xfer);
   2897         1.1  augustss 
   2898  1.264.4.55     skrll 	KASSERT(ux->ux_type == UX_ISOC);
   2899         1.1  augustss }
   2900         1.1  augustss 
   2901        1.16  augustss usbd_status
   2902  1.264.4.25     skrll uhci_device_isoc_transfer(struct usbd_xfer *xfer)
   2903        1.16  augustss {
   2904  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2905  1.264.4.68     skrll 	usbd_status err __diagused;
   2906        1.48  augustss 
   2907  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2908  1.264.4.21     skrll 	DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0);
   2909        1.48  augustss 
   2910        1.48  augustss 	/* Put it on our queue, */
   2911       1.248       mrg 	mutex_enter(&sc->sc_lock);
   2912        1.63  augustss 	err = usb_insert_transfer(xfer);
   2913       1.248       mrg 	mutex_exit(&sc->sc_lock);
   2914        1.48  augustss 
   2915  1.264.4.68     skrll 	KASSERT(err == USBD_NORMAL_COMPLETION);
   2916        1.48  augustss 
   2917        1.48  augustss 	/* insert into schedule, */
   2918        1.48  augustss 
   2919  1.264.4.55     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   2920  1.264.4.62     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   2921  1.264.4.33     skrll 	struct isoc *isoc = &upipe->isoc;
   2922  1.264.4.68     skrll 	uhci_soft_td_t *std = NULL;
   2923   1.264.4.1     skrll 	uint32_t buf, len, status, offs;
   2924       1.248       mrg 	int i, next, nframes;
   2925   1.264.4.7     skrll 	int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN;
   2926        1.48  augustss 
   2927  1.264.4.21     skrll 	DPRINTFN(5, "used=%d next=%d xfer=%p nframes=%d",
   2928  1.264.4.33     skrll 	    isoc->inuse, isoc->next, xfer, xfer->ux_nframes);
   2929        1.48  augustss 
   2930        1.82  augustss 	if (sc->sc_dying)
   2931  1.264.4.68     skrll 		return USBD_IOERROR;
   2932        1.82  augustss 
   2933   1.264.4.7     skrll 	if (xfer->ux_status == USBD_IN_PROGRESS) {
   2934        1.48  augustss 		/* This request has already been entered into the frame list */
   2935  1.264.4.64     skrll 		printf("%s: xfer=%p in frame list\n", __func__, xfer);
   2936        1.68  augustss 		/* XXX */
   2937        1.48  augustss 	}
   2938        1.48  augustss 
   2939        1.48  augustss #ifdef DIAGNOSTIC
   2940  1.264.4.33     skrll 	if (isoc->inuse >= UHCI_VFRAMELIST_COUNT)
   2941  1.264.4.65     skrll 		printf("%s: overflow!\n", __func__);
   2942        1.19  augustss #endif
   2943        1.16  augustss 
   2944  1.264.4.68     skrll 	KASSERT(xfer->ux_nframes != 0);
   2945  1.264.4.68     skrll 
   2946  1.264.4.67     skrll 	mutex_enter(&sc->sc_lock);
   2947  1.264.4.33     skrll 	next = isoc->next;
   2948        1.48  augustss 	if (next == -1) {
   2949        1.48  augustss 		/* Not in use yet, schedule it a few frames ahead. */
   2950        1.48  augustss 		next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT;
   2951  1.264.4.21     skrll 		DPRINTFN(2, "start next=%d", next, 0, 0, 0);
   2952        1.48  augustss 	}
   2953        1.48  augustss 
   2954   1.264.4.7     skrll 	xfer->ux_status = USBD_IN_PROGRESS;
   2955  1.264.4.62     skrll 	ux->ux_curframe = next;
   2956        1.48  augustss 
   2957   1.264.4.7     skrll 	buf = DMAADDR(&xfer->ux_dmabuf, 0);
   2958       1.223    bouyer 	offs = 0;
   2959        1.88   tsutsui 	status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) |
   2960        1.88   tsutsui 				     UHCI_TD_ACTIVE |
   2961        1.88   tsutsui 				     UHCI_TD_IOS);
   2962   1.264.4.7     skrll 	nframes = xfer->ux_nframes;
   2963        1.48  augustss 	for (i = 0; i < nframes; i++) {
   2964  1.264.4.33     skrll 		std = isoc->stds[next];
   2965        1.48  augustss 		if (++next >= UHCI_VFRAMELIST_COUNT)
   2966        1.48  augustss 			next = 0;
   2967   1.264.4.7     skrll 		len = xfer->ux_frlengths[i];
   2968        1.88   tsutsui 		std->td.td_buffer = htole32(buf);
   2969   1.264.4.7     skrll 		usb_syncmem(&xfer->ux_dmabuf, offs, len,
   2970       1.223    bouyer 		    rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
   2971        1.48  augustss 		if (i == nframes - 1)
   2972        1.88   tsutsui 			status |= UHCI_TD_IOC;
   2973        1.88   tsutsui 		std->td.td_status = htole32(status);
   2974        1.88   tsutsui 		std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK);
   2975        1.88   tsutsui 		std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len));
   2976       1.223    bouyer 		usb_syncmem(&std->dma, std->offs, sizeof(std->td),
   2977       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2978        1.59  augustss #ifdef UHCI_DEBUG
   2979  1.264.4.43     skrll 		if (uhcidebug >= 5) {
   2980  1.264.4.47     skrll 			DPRINTF("--- dump start ---", 0, 0, 0, 0);
   2981  1.264.4.27     skrll 			DPRINTF("TD %d", i, 0, 0, 0);
   2982        1.48  augustss 			uhci_dump_td(std);
   2983  1.264.4.47     skrll 			DPRINTF("--- dump end ---", 0, 0, 0, 0);
   2984        1.48  augustss 		}
   2985        1.48  augustss #endif
   2986        1.48  augustss 		buf += len;
   2987       1.223    bouyer 		offs += len;
   2988        1.48  augustss 	}
   2989  1.264.4.33     skrll 	isoc->next = next;
   2990  1.264.4.33     skrll 	isoc->inuse += xfer->ux_nframes;
   2991        1.16  augustss 
   2992        1.48  augustss 	/* Set up interrupt info. */
   2993  1.264.4.68     skrll 	ux->ux_stdstart = std;
   2994  1.264.4.68     skrll 	ux->ux_stdend = std;
   2995  1.264.4.31     skrll 
   2996  1.264.4.41     skrll 	KASSERT(ux->ux_isdone);
   2997        1.48  augustss #ifdef DIAGNOSTIC
   2998  1.264.4.41     skrll 	ux->ux_isdone = false;
   2999        1.48  augustss #endif
   3000  1.264.4.56     skrll 	uhci_add_intr_list(sc, ux);
   3001       1.152  augustss 
   3002       1.248       mrg 	mutex_exit(&sc->sc_lock);
   3003        1.48  augustss 
   3004  1.264.4.13     skrll 	return USBD_IN_PROGRESS;
   3005        1.16  augustss }
   3006        1.16  augustss 
   3007        1.16  augustss void
   3008  1.264.4.25     skrll uhci_device_isoc_abort(struct usbd_xfer *xfer)
   3009        1.16  augustss {
   3010  1.264.4.61     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   3011  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   3012  1.264.4.61     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   3013  1.264.4.33     skrll 	uhci_soft_td_t **stds = upipe->isoc.stds;
   3014        1.48  augustss 	uhci_soft_td_t *std;
   3015       1.248       mrg 	int i, n, nframes, maxlen, len;
   3016        1.92  augustss 
   3017       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   3018        1.92  augustss 
   3019        1.92  augustss 	/* Transfer is already done. */
   3020   1.264.4.7     skrll 	if (xfer->ux_status != USBD_NOT_STARTED &&
   3021   1.264.4.7     skrll 	    xfer->ux_status != USBD_IN_PROGRESS) {
   3022        1.92  augustss 		return;
   3023        1.92  augustss 	}
   3024        1.48  augustss 
   3025        1.92  augustss 	/* Give xfer the requested abort code. */
   3026   1.264.4.7     skrll 	xfer->ux_status = USBD_CANCELLED;
   3027        1.48  augustss 
   3028        1.48  augustss 	/* make hardware ignore it, */
   3029   1.264.4.7     skrll 	nframes = xfer->ux_nframes;
   3030  1.264.4.61     skrll 	n = ux->ux_curframe;
   3031        1.92  augustss 	maxlen = 0;
   3032        1.48  augustss 	for (i = 0; i < nframes; i++) {
   3033        1.48  augustss 		std = stds[n];
   3034       1.223    bouyer 		usb_syncmem(&std->dma,
   3035       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_status),
   3036       1.223    bouyer 		    sizeof(std->td.td_status),
   3037       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   3038        1.88   tsutsui 		std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC));
   3039       1.223    bouyer 		usb_syncmem(&std->dma,
   3040       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_status),
   3041       1.223    bouyer 		    sizeof(std->td.td_status),
   3042       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   3043       1.223    bouyer 		usb_syncmem(&std->dma,
   3044       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_token),
   3045       1.223    bouyer 		    sizeof(std->td.td_token),
   3046       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE);
   3047       1.130   tsutsui 		len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token));
   3048        1.92  augustss 		if (len > maxlen)
   3049        1.92  augustss 			maxlen = len;
   3050        1.48  augustss 		if (++n >= UHCI_VFRAMELIST_COUNT)
   3051        1.48  augustss 			n = 0;
   3052        1.48  augustss 	}
   3053        1.48  augustss 
   3054        1.92  augustss 	/* and wait until we are sure the hardware has finished. */
   3055        1.92  augustss 	delay(maxlen);
   3056        1.92  augustss 
   3057        1.96  augustss #ifdef DIAGNOSTIC
   3058  1.264.4.61     skrll 	ux->ux_isdone = true;
   3059        1.96  augustss #endif
   3060  1.264.4.61     skrll 	/* Remove from interrupt list. */
   3061  1.264.4.61     skrll 	uhci_del_intr_list(sc, ux);
   3062  1.264.4.61     skrll 
   3063  1.264.4.61     skrll 	/* Run callback. */
   3064        1.92  augustss 	usb_transfer_complete(xfer);
   3065        1.48  augustss 
   3066       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   3067        1.16  augustss }
   3068        1.16  augustss 
   3069        1.16  augustss void
   3070  1.264.4.25     skrll uhci_device_isoc_close(struct usbd_pipe *pipe)
   3071        1.16  augustss {
   3072  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
   3073  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
   3074        1.48  augustss 	uhci_soft_td_t *std, *vstd;
   3075  1.264.4.33     skrll 	struct isoc *isoc;
   3076       1.248       mrg 	int i;
   3077       1.248       mrg 
   3078       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   3079        1.16  augustss 
   3080        1.16  augustss 	/*
   3081        1.16  augustss 	 * Make sure all TDs are marked as inactive.
   3082        1.16  augustss 	 * Wait for completion.
   3083        1.16  augustss 	 * Unschedule.
   3084        1.16  augustss 	 * Deallocate.
   3085        1.16  augustss 	 */
   3086  1.264.4.33     skrll 	isoc = &upipe->isoc;
   3087        1.16  augustss 
   3088       1.223    bouyer 	for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
   3089  1.264.4.33     skrll 		std = isoc->stds[i];
   3090       1.223    bouyer 		usb_syncmem(&std->dma,
   3091       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_status),
   3092       1.223    bouyer 		    sizeof(std->td.td_status),
   3093       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   3094       1.223    bouyer 		std->td.td_status &= htole32(~UHCI_TD_ACTIVE);
   3095       1.223    bouyer 		usb_syncmem(&std->dma,
   3096       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_status),
   3097       1.223    bouyer 		    sizeof(std->td.td_status),
   3098       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   3099       1.223    bouyer 	}
   3100       1.248       mrg 	/* wait for completion */
   3101       1.248       mrg 	usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock);
   3102        1.16  augustss 
   3103        1.16  augustss 	for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
   3104  1.264.4.33     skrll 		std = isoc->stds[i];
   3105        1.48  augustss 		for (vstd = sc->sc_vframes[i].htd;
   3106        1.67  augustss 		     vstd != NULL && vstd->link.std != std;
   3107        1.42  augustss 		     vstd = vstd->link.std)
   3108        1.16  augustss 			;
   3109        1.67  augustss 		if (vstd == NULL) {
   3110        1.16  augustss 			/*panic*/
   3111  1.264.4.65     skrll 			printf("%s: %p not found\n", __func__, std);
   3112       1.248       mrg 			mutex_exit(&sc->sc_lock);
   3113        1.16  augustss 			return;
   3114        1.16  augustss 		}
   3115        1.42  augustss 		vstd->link = std->link;
   3116       1.223    bouyer 		usb_syncmem(&std->dma,
   3117       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_link),
   3118       1.223    bouyer 		    sizeof(std->td.td_link),
   3119       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE);
   3120        1.42  augustss 		vstd->td.td_link = std->td.td_link;
   3121       1.223    bouyer 		usb_syncmem(&vstd->dma,
   3122       1.223    bouyer 		    vstd->offs + offsetof(uhci_td_t, td_link),
   3123       1.223    bouyer 		    sizeof(vstd->td.td_link),
   3124       1.223    bouyer 		    BUS_DMASYNC_PREWRITE);
   3125  1.264.4.55     skrll 		uhci_free_std_locked(sc, std);
   3126        1.16  augustss 	}
   3127        1.16  augustss 
   3128  1.264.4.35     skrll 	kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *));
   3129        1.16  augustss }
   3130        1.16  augustss 
   3131        1.16  augustss usbd_status
   3132  1.264.4.25     skrll uhci_setup_isoc(struct usbd_pipe *pipe)
   3133        1.16  augustss {
   3134  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
   3135  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
   3136   1.264.4.7     skrll 	int addr = upipe->pipe.up_dev->ud_addr;
   3137   1.264.4.7     skrll 	int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
   3138        1.45  augustss 	int rd = UE_GET_DIR(endpt) == UE_DIR_IN;
   3139        1.48  augustss 	uhci_soft_td_t *std, *vstd;
   3140   1.264.4.1     skrll 	uint32_t token;
   3141  1.264.4.33     skrll 	struct isoc *isoc;
   3142       1.248       mrg 	int i;
   3143        1.16  augustss 
   3144  1.264.4.33     skrll 	isoc = &upipe->isoc;
   3145  1.264.4.55     skrll 
   3146  1.264.4.55     skrll 	isoc->stds = kmem_alloc(
   3147  1.264.4.55     skrll 	    UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *), KM_SLEEP);
   3148  1.264.4.33     skrll 	if (isoc->stds == NULL)
   3149       1.248       mrg 		return USBD_NOMEM;
   3150        1.16  augustss 
   3151        1.88   tsutsui 	token = rd ? UHCI_TD_IN (0, endpt, addr, 0) :
   3152        1.88   tsutsui 		     UHCI_TD_OUT(0, endpt, addr, 0);
   3153        1.16  augustss 
   3154        1.48  augustss 	/* Allocate the TDs and mark as inactive; */
   3155        1.16  augustss 	for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
   3156        1.48  augustss 		std = uhci_alloc_std(sc);
   3157        1.48  augustss 		if (std == 0)
   3158        1.48  augustss 			goto bad;
   3159        1.88   tsutsui 		std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */
   3160        1.88   tsutsui 		std->td.td_token = htole32(token);
   3161       1.223    bouyer 		usb_syncmem(&std->dma, std->offs, sizeof(std->td),
   3162       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   3163  1.264.4.33     skrll 		isoc->stds[i] = std;
   3164        1.16  augustss 	}
   3165        1.16  augustss 
   3166  1.264.4.55     skrll 	mutex_enter(&sc->sc_lock);
   3167  1.264.4.55     skrll 
   3168        1.48  augustss 	/* Insert TDs into schedule. */
   3169        1.16  augustss 	for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
   3170  1.264.4.33     skrll 		std = isoc->stds[i];
   3171        1.48  augustss 		vstd = sc->sc_vframes[i].htd;
   3172       1.223    bouyer 		usb_syncmem(&vstd->dma,
   3173       1.223    bouyer 		    vstd->offs + offsetof(uhci_td_t, td_link),
   3174       1.223    bouyer 		    sizeof(vstd->td.td_link),
   3175       1.223    bouyer 		    BUS_DMASYNC_POSTWRITE);
   3176        1.42  augustss 		std->link = vstd->link;
   3177        1.42  augustss 		std->td.td_link = vstd->td.td_link;
   3178       1.223    bouyer 		usb_syncmem(&std->dma,
   3179       1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_link),
   3180       1.223    bouyer 		    sizeof(std->td.td_link),
   3181       1.223    bouyer 		    BUS_DMASYNC_PREWRITE);
   3182        1.42  augustss 		vstd->link.std = std;
   3183       1.121  augustss 		vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD);
   3184       1.223    bouyer 		usb_syncmem(&vstd->dma,
   3185       1.223    bouyer 		    vstd->offs + offsetof(uhci_td_t, td_link),
   3186       1.223    bouyer 		    sizeof(vstd->td.td_link),
   3187       1.223    bouyer 		    BUS_DMASYNC_PREWRITE);
   3188        1.16  augustss 	}
   3189       1.248       mrg 	mutex_exit(&sc->sc_lock);
   3190        1.16  augustss 
   3191  1.264.4.33     skrll 	isoc->next = -1;
   3192  1.264.4.33     skrll 	isoc->inuse = 0;
   3193        1.48  augustss 
   3194  1.264.4.13     skrll 	return USBD_NORMAL_COMPLETION;
   3195        1.16  augustss 
   3196        1.48  augustss  bad:
   3197        1.16  augustss 	while (--i >= 0)
   3198  1.264.4.33     skrll 		uhci_free_std(sc, isoc->stds[i]);
   3199  1.264.4.35     skrll 	kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *));
   3200  1.264.4.13     skrll 	return USBD_NOMEM;
   3201        1.16  augustss }
   3202        1.16  augustss 
   3203        1.16  augustss void
   3204  1.264.4.25     skrll uhci_device_isoc_done(struct usbd_xfer *xfer)
   3205        1.16  augustss {
   3206  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   3207  1.264.4.39     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   3208       1.223    bouyer 	int i, offs;
   3209   1.264.4.7     skrll 	int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN;
   3210       1.223    bouyer 
   3211  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3212  1.264.4.21     skrll 	DPRINTFN(4, "length=%d, ux_state=0x%08x",
   3213  1.264.4.21     skrll 	    xfer->ux_actlen, xfer->ux_state, 0, 0);
   3214        1.93  augustss 
   3215        1.93  augustss #ifdef DIAGNOSTIC
   3216  1.264.4.41     skrll 	if (ux->ux_stdend == NULL) {
   3217  1.264.4.65     skrll 		printf("%s: xfer=%p stdend==NULL\n", __func__, xfer);
   3218        1.93  augustss #ifdef UHCI_DEBUG
   3219  1.264.4.47     skrll 		DPRINTF("--- dump start ---", 0, 0, 0, 0);
   3220  1.264.4.39     skrll 		uhci_dump_ii(ux);
   3221  1.264.4.47     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   3222        1.93  augustss #endif
   3223        1.93  augustss 		return;
   3224        1.93  augustss 	}
   3225        1.93  augustss #endif
   3226        1.48  augustss 
   3227        1.48  augustss 	/* Turn off the interrupt since it is active even if the TD is not. */
   3228  1.264.4.41     skrll 	usb_syncmem(&ux->ux_stdend->dma,
   3229  1.264.4.41     skrll 	    ux->ux_stdend->offs + offsetof(uhci_td_t, td_status),
   3230  1.264.4.41     skrll 	    sizeof(ux->ux_stdend->td.td_status),
   3231       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   3232  1.264.4.41     skrll 	ux->ux_stdend->td.td_status &= htole32(~UHCI_TD_IOC);
   3233  1.264.4.41     skrll 	usb_syncmem(&ux->ux_stdend->dma,
   3234  1.264.4.41     skrll 	    ux->ux_stdend->offs + offsetof(uhci_td_t, td_status),
   3235  1.264.4.41     skrll 	    sizeof(ux->ux_stdend->td.td_status),
   3236       1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   3237        1.48  augustss 
   3238       1.223    bouyer 	offs = 0;
   3239   1.264.4.7     skrll 	for (i = 0; i < xfer->ux_nframes; i++) {
   3240   1.264.4.7     skrll 		usb_syncmem(&xfer->ux_dmabuf, offs, xfer->ux_frlengths[i],
   3241       1.223    bouyer 		    rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
   3242   1.264.4.7     skrll 		offs += xfer->ux_frlengths[i];
   3243       1.223    bouyer 	}
   3244        1.16  augustss }
   3245        1.16  augustss 
   3246         1.1  augustss void
   3247  1.264.4.25     skrll uhci_device_intr_done(struct usbd_xfer *xfer)
   3248         1.1  augustss {
   3249  1.264.4.76     skrll 	uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer);
   3250  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   3251         1.1  augustss 	uhci_soft_qh_t *sqh;
   3252  1.264.4.55     skrll 	int i, npoll;
   3253         1.1  augustss 
   3254  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3255  1.264.4.21     skrll 	DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0);
   3256         1.1  augustss 
   3257   1.264.4.7     skrll 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
   3258       1.248       mrg 
   3259  1.264.4.33     skrll 	npoll = upipe->intr.npoll;
   3260  1.264.4.54     skrll 	for (i = 0; i < npoll; i++) {
   3261  1.264.4.33     skrll 		sqh = upipe->intr.qhs[i];
   3262       1.121  augustss 		sqh->elink = NULL;
   3263        1.88   tsutsui 		sqh->qh.qh_elink = htole32(UHCI_PTR_T);
   3264       1.223    bouyer 		usb_syncmem(&sqh->dma,
   3265       1.223    bouyer 		    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   3266       1.223    bouyer 		    sizeof(sqh->qh.qh_elink),
   3267       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   3268         1.1  augustss 	}
   3269  1.264.4.63     skrll 	const int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
   3270  1.264.4.63     skrll 	const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN;
   3271  1.264.4.63     skrll 	usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
   3272  1.264.4.63     skrll 	    isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
   3273         1.1  augustss }
   3274         1.1  augustss 
   3275         1.1  augustss /* Deallocate request data structures */
   3276         1.1  augustss void
   3277  1.264.4.25     skrll uhci_device_ctrl_done(struct usbd_xfer *xfer)
   3278         1.1  augustss {
   3279  1.264.4.38     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   3280  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   3281   1.264.4.7     skrll 	int len = UGETW(xfer->ux_request.wLength);
   3282   1.264.4.7     skrll 	int isread = (xfer->ux_request.bmRequestType & UT_READ);
   3283         1.1  augustss 
   3284   1.264.4.7     skrll 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
   3285       1.248       mrg 
   3286  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3287  1.264.4.31     skrll 
   3288  1.264.4.32     skrll 	KASSERT(xfer->ux_rqflags & URQ_REQUEST);
   3289         1.1  augustss 
   3290  1.264.4.61     skrll 	/* XXXNH move to uhci_idone??? */
   3291   1.264.4.7     skrll 	if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW)
   3292  1.264.4.33     skrll 		uhci_remove_ls_ctrl(sc, upipe->ctrl.sqh);
   3293       1.123  augustss 	else
   3294  1.264.4.33     skrll 		uhci_remove_hs_ctrl(sc, upipe->ctrl.sqh);
   3295         1.1  augustss 
   3296       1.223    bouyer 	if (len) {
   3297   1.264.4.7     skrll 		usb_syncmem(&xfer->ux_dmabuf, 0, len,
   3298       1.223    bouyer 		    isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
   3299       1.223    bouyer 	}
   3300  1.264.4.33     skrll 	usb_syncmem(&upipe->ctrl.reqdma, 0,
   3301       1.223    bouyer 	    sizeof(usb_device_request_t),  BUS_DMASYNC_POSTWRITE);
   3302       1.223    bouyer 
   3303  1.264.4.27     skrll 	DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0);
   3304         1.1  augustss }
   3305         1.1  augustss 
   3306         1.1  augustss /* Deallocate request data structures */
   3307         1.1  augustss void
   3308  1.264.4.25     skrll uhci_device_bulk_done(struct usbd_xfer *xfer)
   3309         1.1  augustss {
   3310  1.264.4.38     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   3311  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   3312  1.264.4.51     skrll 	usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc;
   3313  1.264.4.51     skrll 	int endpt = ed->bEndpointAddress;
   3314  1.264.4.51     skrll 	int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
   3315       1.169  augustss 
   3316  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3317  1.264.4.72     skrll 	DPRINTFN(5, "xfer=%p sc=%p upipe=%p", xfer, sc, upipe, 0);
   3318       1.169  augustss 
   3319       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   3320       1.248       mrg 
   3321  1.264.4.33     skrll 	uhci_remove_bulk(sc, upipe->bulk.sqh);
   3322        1.32  augustss 
   3323  1.264.4.51     skrll 	if (xfer->ux_length) {
   3324  1.264.4.51     skrll 		usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
   3325  1.264.4.51     skrll 		    isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
   3326  1.264.4.51     skrll 	}
   3327        1.32  augustss 
   3328  1.264.4.21     skrll 	DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0);
   3329         1.1  augustss }
   3330         1.1  augustss 
   3331         1.1  augustss /* Add interrupt QH, called with vflock. */
   3332         1.1  augustss void
   3333       1.119  augustss uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   3334         1.1  augustss {
   3335        1.92  augustss 	struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos];
   3336        1.42  augustss 	uhci_soft_qh_t *eqh;
   3337         1.1  augustss 
   3338  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3339  1.264.4.21     skrll 	DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0);
   3340        1.92  augustss 
   3341        1.42  augustss 	eqh = vf->eqh;
   3342       1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   3343  1.264.4.77     skrll 	    sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
   3344        1.42  augustss 	sqh->hlink       = eqh->hlink;
   3345        1.42  augustss 	sqh->qh.qh_hlink = eqh->qh.qh_hlink;
   3346       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
   3347  1.264.4.77     skrll 	    sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
   3348        1.42  augustss 	eqh->hlink       = sqh;
   3349       1.121  augustss 	eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
   3350       1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   3351  1.264.4.77     skrll 	    sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
   3352         1.1  augustss 	vf->eqh = sqh;
   3353         1.1  augustss 	vf->bandwidth++;
   3354         1.1  augustss }
   3355         1.1  augustss 
   3356       1.119  augustss /* Remove interrupt QH. */
   3357         1.1  augustss void
   3358       1.119  augustss uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   3359         1.1  augustss {
   3360        1.92  augustss 	struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos];
   3361         1.1  augustss 	uhci_soft_qh_t *pqh;
   3362         1.1  augustss 
   3363  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3364  1.264.4.21     skrll 	DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0);
   3365         1.1  augustss 
   3366       1.124  augustss 	/* See comment in uhci_remove_ctrl() */
   3367       1.223    bouyer 
   3368       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
   3369       1.223    bouyer 	    sizeof(sqh->qh.qh_elink),
   3370       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   3371       1.124  augustss 	if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) {
   3372       1.124  augustss 		sqh->qh.qh_elink = htole32(UHCI_PTR_T);
   3373       1.223    bouyer 		usb_syncmem(&sqh->dma,
   3374       1.223    bouyer 		    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   3375       1.223    bouyer 		    sizeof(sqh->qh.qh_elink),
   3376       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   3377       1.124  augustss 		delay(UHCI_QH_REMOVE_DELAY);
   3378       1.124  augustss 	}
   3379       1.124  augustss 
   3380        1.92  augustss 	pqh = uhci_find_prev_qh(vf->hqh, sqh);
   3381       1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
   3382       1.223    bouyer 	    sizeof(sqh->qh.qh_hlink),
   3383       1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   3384        1.42  augustss 	pqh->hlink       = sqh->hlink;
   3385        1.42  augustss 	pqh->qh.qh_hlink = sqh->qh.qh_hlink;
   3386       1.223    bouyer 	usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
   3387       1.223    bouyer 	    sizeof(pqh->qh.qh_hlink),
   3388       1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   3389       1.124  augustss 	delay(UHCI_QH_REMOVE_DELAY);
   3390         1.1  augustss 	if (vf->eqh == sqh)
   3391         1.1  augustss 		vf->eqh = pqh;
   3392         1.1  augustss 	vf->bandwidth--;
   3393         1.1  augustss }
   3394         1.1  augustss 
   3395         1.1  augustss usbd_status
   3396       1.119  augustss uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival)
   3397         1.1  augustss {
   3398         1.1  augustss 	uhci_soft_qh_t *sqh;
   3399       1.248       mrg 	int i, npoll;
   3400         1.1  augustss 	u_int bestbw, bw, bestoffs, offs;
   3401         1.1  augustss 
   3402  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3403  1.264.4.21     skrll 	DPRINTFN(2, "pipe=%p", upipe, 0, 0, 0);
   3404         1.1  augustss 	if (ival == 0) {
   3405  1.264.4.65     skrll 		printf("%s: 0 interval\n", __func__);
   3406  1.264.4.13     skrll 		return USBD_INVAL;
   3407         1.1  augustss 	}
   3408         1.1  augustss 
   3409         1.1  augustss 	if (ival > UHCI_VFRAMELIST_COUNT)
   3410         1.1  augustss 		ival = UHCI_VFRAMELIST_COUNT;
   3411         1.1  augustss 	npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival;
   3412  1.264.4.27     skrll 	DPRINTF("ival=%d npoll=%d", ival, npoll, 0, 0);
   3413         1.1  augustss 
   3414  1.264.4.33     skrll 	upipe->intr.npoll = npoll;
   3415  1.264.4.33     skrll 	upipe->intr.qhs =
   3416       1.248       mrg 		kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP);
   3417         1.1  augustss 
   3418       1.152  augustss 	/*
   3419         1.1  augustss 	 * Figure out which offset in the schedule that has most
   3420         1.1  augustss 	 * bandwidth left over.
   3421         1.1  augustss 	 */
   3422         1.1  augustss #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1))
   3423         1.1  augustss 	for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) {
   3424         1.1  augustss 		for (bw = i = 0; i < npoll; i++)
   3425         1.1  augustss 			bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth;
   3426         1.1  augustss 		if (bw < bestbw) {
   3427         1.1  augustss 			bestbw = bw;
   3428         1.1  augustss 			bestoffs = offs;
   3429         1.1  augustss 		}
   3430         1.1  augustss 	}
   3431  1.264.4.27     skrll 	DPRINTF("bw=%d offs=%d", bestbw, bestoffs, 0, 0);
   3432  1.264.4.54     skrll 	for (i = 0; i < npoll; i++) {
   3433  1.264.4.33     skrll 		upipe->intr.qhs[i] = sqh = uhci_alloc_sqh(sc);
   3434       1.121  augustss 		sqh->elink = NULL;
   3435        1.88   tsutsui 		sqh->qh.qh_elink = htole32(UHCI_PTR_T);
   3436       1.223    bouyer 		usb_syncmem(&sqh->dma,
   3437       1.223    bouyer 		    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   3438       1.223    bouyer 		    sizeof(sqh->qh.qh_elink),
   3439       1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   3440         1.1  augustss 		sqh->pos = MOD(i * ival + bestoffs);
   3441         1.1  augustss 	}
   3442         1.1  augustss #undef MOD
   3443         1.1  augustss 
   3444  1.264.4.55     skrll 	mutex_enter(&sc->sc_lock);
   3445         1.1  augustss 	/* Enter QHs into the controller data structures. */
   3446  1.264.4.54     skrll 	for (i = 0; i < npoll; i++)
   3447  1.264.4.33     skrll 		uhci_add_intr(sc, upipe->intr.qhs[i]);
   3448       1.248       mrg 	mutex_exit(&sc->sc_lock);
   3449         1.1  augustss 
   3450  1.264.4.21     skrll 	DPRINTFN(5, "returns %p", upipe, 0, 0, 0);
   3451  1.264.4.21     skrll 
   3452  1.264.4.13     skrll 	return USBD_NORMAL_COMPLETION;
   3453         1.1  augustss }
   3454         1.1  augustss 
   3455         1.1  augustss /* Open a new pipe. */
   3456         1.1  augustss usbd_status
   3457  1.264.4.25     skrll uhci_open(struct usbd_pipe *pipe)
   3458         1.1  augustss {
   3459  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
   3460  1.264.4.12     skrll 	struct usbd_bus *bus = pipe->up_dev->ud_bus;
   3461  1.264.4.50     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
   3462   1.264.4.7     skrll 	usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc;
   3463       1.248       mrg 	usbd_status err = USBD_NOMEM;
   3464        1.79  augustss 	int ival;
   3465         1.1  augustss 
   3466  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3467  1.264.4.27     skrll 	DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)",
   3468  1.264.4.21     skrll 	    pipe, pipe->up_dev->ud_addr, ed->bEndpointAddress, bus->ub_rhaddr);
   3469        1.92  augustss 
   3470       1.248       mrg 	if (sc->sc_dying)
   3471       1.248       mrg 		return USBD_IOERROR;
   3472       1.248       mrg 
   3473        1.92  augustss 	upipe->aborting = 0;
   3474       1.236  drochner 	/* toggle state needed for bulk endpoints */
   3475   1.264.4.7     skrll 	upipe->nexttoggle = pipe->up_endpoint->ue_toggle;
   3476        1.92  augustss 
   3477  1.264.4.12     skrll 	if (pipe->up_dev->ud_addr == bus->ub_rhaddr) {
   3478         1.1  augustss 		switch (ed->bEndpointAddress) {
   3479         1.1  augustss 		case USB_CONTROL_ENDPOINT:
   3480  1.264.4.12     skrll 			pipe->up_methods = &roothub_ctrl_methods;
   3481         1.1  augustss 			break;
   3482  1.264.4.12     skrll 		case UE_DIR_IN | USBROOTHUB_INTR_ENDPT:
   3483   1.264.4.7     skrll 			pipe->up_methods = &uhci_root_intr_methods;
   3484         1.1  augustss 			break;
   3485         1.1  augustss 		default:
   3486  1.264.4.13     skrll 			return USBD_INVAL;
   3487         1.1  augustss 		}
   3488         1.1  augustss 	} else {
   3489         1.1  augustss 		switch (ed->bmAttributes & UE_XFERTYPE) {
   3490         1.1  augustss 		case UE_CONTROL:
   3491   1.264.4.7     skrll 			pipe->up_methods = &uhci_device_ctrl_methods;
   3492  1.264.4.33     skrll 			upipe->ctrl.sqh = uhci_alloc_sqh(sc);
   3493  1.264.4.33     skrll 			if (upipe->ctrl.sqh == NULL)
   3494         1.5  augustss 				goto bad;
   3495  1.264.4.33     skrll 			upipe->ctrl.setup = uhci_alloc_std(sc);
   3496  1.264.4.33     skrll 			if (upipe->ctrl.setup == NULL) {
   3497  1.264.4.33     skrll 				uhci_free_sqh(sc, upipe->ctrl.sqh);
   3498         1.5  augustss 				goto bad;
   3499         1.5  augustss 			}
   3500  1.264.4.33     skrll 			upipe->ctrl.stat = uhci_alloc_std(sc);
   3501  1.264.4.33     skrll 			if (upipe->ctrl.stat == NULL) {
   3502  1.264.4.33     skrll 				uhci_free_sqh(sc, upipe->ctrl.sqh);
   3503  1.264.4.33     skrll 				uhci_free_std(sc, upipe->ctrl.setup);
   3504         1.5  augustss 				goto bad;
   3505         1.5  augustss 			}
   3506       1.152  augustss 			err = usb_allocmem(&sc->sc_bus,
   3507       1.152  augustss 				  sizeof(usb_device_request_t),
   3508  1.264.4.33     skrll 				  0, &upipe->ctrl.reqdma);
   3509        1.63  augustss 			if (err) {
   3510  1.264.4.33     skrll 				uhci_free_sqh(sc, upipe->ctrl.sqh);
   3511  1.264.4.33     skrll 				uhci_free_std(sc, upipe->ctrl.setup);
   3512  1.264.4.33     skrll 				uhci_free_std(sc, upipe->ctrl.stat);
   3513         1.5  augustss 				goto bad;
   3514         1.5  augustss 			}
   3515         1.1  augustss 			break;
   3516         1.1  augustss 		case UE_INTERRUPT:
   3517   1.264.4.7     skrll 			pipe->up_methods = &uhci_device_intr_methods;
   3518   1.264.4.7     skrll 			ival = pipe->up_interval;
   3519        1.79  augustss 			if (ival == USBD_DEFAULT_INTERVAL)
   3520        1.79  augustss 				ival = ed->bInterval;
   3521  1.264.4.13     skrll 			return uhci_device_setintr(sc, upipe, ival);
   3522         1.1  augustss 		case UE_ISOCHRONOUS:
   3523  1.264.4.68     skrll 			pipe->up_serialise = false;
   3524   1.264.4.7     skrll 			pipe->up_methods = &uhci_device_isoc_methods;
   3525  1.264.4.13     skrll 			return uhci_setup_isoc(pipe);
   3526         1.1  augustss 		case UE_BULK:
   3527   1.264.4.7     skrll 			pipe->up_methods = &uhci_device_bulk_methods;
   3528  1.264.4.33     skrll 			upipe->bulk.sqh = uhci_alloc_sqh(sc);
   3529  1.264.4.33     skrll 			if (upipe->bulk.sqh == NULL)
   3530         1.5  augustss 				goto bad;
   3531         1.1  augustss 			break;
   3532         1.1  augustss 		}
   3533         1.1  augustss 	}
   3534  1.264.4.13     skrll 	return USBD_NORMAL_COMPLETION;
   3535         1.5  augustss 
   3536         1.5  augustss  bad:
   3537       1.248       mrg 	return USBD_NOMEM;
   3538         1.1  augustss }
   3539         1.1  augustss 
   3540         1.1  augustss /*
   3541         1.1  augustss  * Data structures and routines to emulate the root hub.
   3542         1.1  augustss  */
   3543         1.1  augustss /*
   3544       1.166   dsainty  * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also
   3545       1.166   dsainty  * enables the port, and also states that SET_FEATURE(PORT_ENABLE)
   3546       1.166   dsainty  * should not be used by the USB subsystem.  As we cannot issue a
   3547       1.166   dsainty  * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port
   3548       1.166   dsainty  * will be enabled as part of the reset.
   3549       1.166   dsainty  *
   3550       1.166   dsainty  * On the VT83C572, the port cannot be successfully enabled until the
   3551       1.166   dsainty  * outstanding "port enable change" and "connection status change"
   3552       1.166   dsainty  * events have been reset.
   3553       1.166   dsainty  */
   3554       1.166   dsainty Static usbd_status
   3555       1.166   dsainty uhci_portreset(uhci_softc_t *sc, int index)
   3556       1.166   dsainty {
   3557       1.166   dsainty 	int lim, port, x;
   3558  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3559       1.166   dsainty 
   3560       1.166   dsainty 	if (index == 1)
   3561       1.166   dsainty 		port = UHCI_PORTSC1;
   3562       1.166   dsainty 	else if (index == 2)
   3563       1.166   dsainty 		port = UHCI_PORTSC2;
   3564       1.166   dsainty 	else
   3565  1.264.4.13     skrll 		return USBD_IOERROR;
   3566       1.166   dsainty 
   3567       1.166   dsainty 	x = URWMASK(UREAD2(sc, port));
   3568       1.166   dsainty 	UWRITE2(sc, port, x | UHCI_PORTSC_PR);
   3569       1.166   dsainty 
   3570       1.166   dsainty 	usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY);
   3571       1.166   dsainty 
   3572  1.264.4.27     skrll 	DPRINTF("uhci port %d reset, status0 = 0x%04x", index,
   3573  1.264.4.21     skrll 	    UREAD2(sc, port), 0, 0);
   3574       1.166   dsainty 
   3575       1.166   dsainty 	x = URWMASK(UREAD2(sc, port));
   3576       1.222  drochner 	UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP));
   3577       1.166   dsainty 
   3578       1.166   dsainty 	delay(100);
   3579       1.166   dsainty 
   3580  1.264.4.27     skrll 	DPRINTF("uhci port %d reset, status1 = 0x%04x", index,
   3581  1.264.4.21     skrll 	    UREAD2(sc, port), 0, 0);
   3582       1.166   dsainty 
   3583       1.166   dsainty 	x = URWMASK(UREAD2(sc, port));
   3584       1.166   dsainty 	UWRITE2(sc, port, x  | UHCI_PORTSC_PE);
   3585       1.166   dsainty 
   3586       1.166   dsainty 	for (lim = 10; --lim > 0;) {
   3587       1.166   dsainty 		usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY);
   3588       1.166   dsainty 
   3589       1.166   dsainty 		x = UREAD2(sc, port);
   3590  1.264.4.27     skrll 		DPRINTF("uhci port %d iteration %u, status = 0x%04x", index,
   3591  1.264.4.21     skrll 		    lim, x, 0);
   3592       1.166   dsainty 
   3593       1.166   dsainty 		if (!(x & UHCI_PORTSC_CCS)) {
   3594       1.166   dsainty 			/*
   3595       1.166   dsainty 			 * No device is connected (or was disconnected
   3596       1.166   dsainty 			 * during reset).  Consider the port reset.
   3597       1.166   dsainty 			 * The delay must be long enough to ensure on
   3598       1.166   dsainty 			 * the initial iteration that the device
   3599       1.166   dsainty 			 * connection will have been registered.  50ms
   3600       1.166   dsainty 			 * appears to be sufficient, but 20ms is not.
   3601       1.166   dsainty 			 */
   3602  1.264.4.21     skrll 			DPRINTFN(3, "uhci port %d loop %u, device detached",
   3603  1.264.4.21     skrll 			    index, lim, 0, 0);
   3604       1.166   dsainty 			break;
   3605       1.166   dsainty 		}
   3606       1.166   dsainty 
   3607       1.166   dsainty 		if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) {
   3608       1.166   dsainty 			/*
   3609       1.166   dsainty 			 * Port enabled changed and/or connection
   3610       1.166   dsainty 			 * status changed were set.  Reset either or
   3611       1.166   dsainty 			 * both raised flags (by writing a 1 to that
   3612       1.166   dsainty 			 * bit), and wait again for state to settle.
   3613       1.166   dsainty 			 */
   3614       1.166   dsainty 			UWRITE2(sc, port, URWMASK(x) |
   3615       1.166   dsainty 				(x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)));
   3616       1.166   dsainty 			continue;
   3617       1.166   dsainty 		}
   3618       1.166   dsainty 
   3619       1.166   dsainty 		if (x & UHCI_PORTSC_PE)
   3620       1.166   dsainty 			/* Port is enabled */
   3621       1.166   dsainty 			break;
   3622       1.166   dsainty 
   3623       1.166   dsainty 		UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE);
   3624       1.166   dsainty 	}
   3625       1.166   dsainty 
   3626  1.264.4.21     skrll 	DPRINTFN(3, "uhci port %d reset, status2 = 0x%04x", index,
   3627  1.264.4.21     skrll 	    UREAD2(sc, port), 0, 0);
   3628       1.166   dsainty 
   3629       1.166   dsainty 	if (lim <= 0) {
   3630  1.264.4.27     skrll 		DPRINTF("uhci port %d reset timed out", index,
   3631  1.264.4.21     skrll 		    0, 0, 0);
   3632  1.264.4.13     skrll 		return USBD_TIMEOUT;
   3633       1.166   dsainty 	}
   3634       1.184     perry 
   3635       1.166   dsainty 	sc->sc_isreset = 1;
   3636  1.264.4.13     skrll 	return USBD_NORMAL_COMPLETION;
   3637       1.166   dsainty }
   3638       1.166   dsainty 
   3639  1.264.4.12     skrll Static int
   3640  1.264.4.12     skrll uhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req,
   3641  1.264.4.12     skrll     void *buf, int buflen)
   3642         1.1  augustss {
   3643  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_BUS2SC(bus);
   3644         1.1  augustss 	int port, x;
   3645  1.264.4.12     skrll 	int status, change, totlen = 0;
   3646  1.264.4.12     skrll 	uint16_t len, value, index;
   3647         1.1  augustss 	usb_port_status_t ps;
   3648        1.63  augustss 	usbd_status err;
   3649         1.1  augustss 
   3650  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3651  1.264.4.21     skrll 
   3652        1.82  augustss 	if (sc->sc_dying)
   3653  1.264.4.12     skrll 		return -1;
   3654         1.1  augustss 
   3655  1.264.4.27     skrll 	DPRINTF("type=0x%02x request=%02x", req->bmRequestType,
   3656  1.264.4.21     skrll 	    req->bRequest, 0, 0);
   3657         1.1  augustss 
   3658         1.1  augustss 	len = UGETW(req->wLength);
   3659         1.1  augustss 	value = UGETW(req->wValue);
   3660         1.1  augustss 	index = UGETW(req->wIndex);
   3661        1.49  augustss 
   3662         1.1  augustss #define C(x,y) ((x) | ((y) << 8))
   3663  1.264.4.12     skrll 	switch (C(req->bRequest, req->bmRequestType)) {
   3664         1.1  augustss 	case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
   3665  1.264.4.27     skrll 		DPRINTF("wValue=0x%04x", value, 0, 0, 0);
   3666       1.195  christos 		if (len == 0)
   3667       1.195  christos 			break;
   3668  1.264.4.12     skrll 		switch (value) {
   3669  1.264.4.12     skrll 		case C(0, UDESC_DEVICE): {
   3670  1.264.4.12     skrll 			usb_device_descriptor_t devd;
   3671  1.264.4.12     skrll 
   3672  1.264.4.12     skrll 			totlen = min(buflen, sizeof(devd));
   3673  1.264.4.12     skrll 			memcpy(&devd, buf, totlen);
   3674  1.264.4.12     skrll 			USETW(devd.idVendor, sc->sc_id_vendor);
   3675  1.264.4.12     skrll 			memcpy(buf, &devd, totlen);
   3676         1.1  augustss 			break;
   3677  1.264.4.12     skrll 		}
   3678  1.264.4.12     skrll 		case C(1, UDESC_STRING):
   3679       1.213  drochner #define sd ((usb_string_descriptor_t *)buf)
   3680  1.264.4.12     skrll 			/* Vendor */
   3681  1.264.4.12     skrll 			totlen = usb_makestrdesc(sd, len, sc->sc_vendor);
   3682  1.264.4.12     skrll 			break;
   3683  1.264.4.12     skrll 		case C(2, UDESC_STRING):
   3684  1.264.4.12     skrll 			/* Product */
   3685  1.264.4.12     skrll 			totlen = usb_makestrdesc(sd, len, "UHCI root hub");
   3686         1.1  augustss 			break;
   3687  1.264.4.12     skrll #undef sd
   3688         1.1  augustss 		default:
   3689  1.264.4.12     skrll 			/* default from usbroothub */
   3690  1.264.4.12     skrll 			return buflen;
   3691         1.1  augustss 		}
   3692         1.1  augustss 		break;
   3693  1.264.4.12     skrll 
   3694         1.1  augustss 	/* Hub requests */
   3695         1.1  augustss 	case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
   3696         1.1  augustss 		break;
   3697         1.1  augustss 	case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
   3698  1.264.4.27     skrll 		DPRINTF("UR_CLEAR_PORT_FEATURE port=%d feature=%d", index,
   3699  1.264.4.21     skrll 		    value, 0, 0);
   3700         1.1  augustss 		if (index == 1)
   3701         1.1  augustss 			port = UHCI_PORTSC1;
   3702         1.1  augustss 		else if (index == 2)
   3703         1.1  augustss 			port = UHCI_PORTSC2;
   3704         1.1  augustss 		else {
   3705  1.264.4.12     skrll 			return -1;
   3706         1.1  augustss 		}
   3707         1.1  augustss 		switch(value) {
   3708         1.1  augustss 		case UHF_PORT_ENABLE:
   3709       1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3710         1.1  augustss 			UWRITE2(sc, port, x & ~UHCI_PORTSC_PE);
   3711         1.1  augustss 			break;
   3712         1.1  augustss 		case UHF_PORT_SUSPEND:
   3713       1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3714       1.222  drochner 			if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */
   3715       1.222  drochner 				break;
   3716       1.222  drochner 			UWRITE2(sc, port, x | UHCI_PORTSC_RD);
   3717       1.222  drochner 			/* see USB2 spec ch. 7.1.7.7 */
   3718       1.222  drochner 			usb_delay_ms(&sc->sc_bus, 20);
   3719         1.1  augustss 			UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP);
   3720       1.222  drochner 			/* 10ms resume delay must be provided by caller */
   3721         1.1  augustss 			break;
   3722         1.1  augustss 		case UHF_PORT_RESET:
   3723       1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3724         1.1  augustss 			UWRITE2(sc, port, x & ~UHCI_PORTSC_PR);
   3725         1.1  augustss 			break;
   3726         1.1  augustss 		case UHF_C_PORT_CONNECTION:
   3727       1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3728         1.1  augustss 			UWRITE2(sc, port, x | UHCI_PORTSC_CSC);
   3729         1.1  augustss 			break;
   3730         1.1  augustss 		case UHF_C_PORT_ENABLE:
   3731       1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3732         1.1  augustss 			UWRITE2(sc, port, x | UHCI_PORTSC_POEDC);
   3733         1.1  augustss 			break;
   3734         1.1  augustss 		case UHF_C_PORT_OVER_CURRENT:
   3735       1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3736         1.1  augustss 			UWRITE2(sc, port, x | UHCI_PORTSC_OCIC);
   3737         1.1  augustss 			break;
   3738         1.1  augustss 		case UHF_C_PORT_RESET:
   3739         1.1  augustss 			sc->sc_isreset = 0;
   3740  1.264.4.16     skrll 			break;
   3741         1.1  augustss 		case UHF_PORT_CONNECTION:
   3742         1.1  augustss 		case UHF_PORT_OVER_CURRENT:
   3743         1.1  augustss 		case UHF_PORT_POWER:
   3744         1.1  augustss 		case UHF_PORT_LOW_SPEED:
   3745         1.1  augustss 		case UHF_C_PORT_SUSPEND:
   3746         1.1  augustss 		default:
   3747  1.264.4.12     skrll 			return -1;
   3748         1.1  augustss 		}
   3749         1.1  augustss 		break;
   3750         1.1  augustss 	case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER):
   3751         1.1  augustss 		if (index == 1)
   3752         1.1  augustss 			port = UHCI_PORTSC1;
   3753         1.1  augustss 		else if (index == 2)
   3754         1.1  augustss 			port = UHCI_PORTSC2;
   3755         1.1  augustss 		else {
   3756  1.264.4.12     skrll 			return -1;
   3757         1.1  augustss 		}
   3758         1.1  augustss 		if (len > 0) {
   3759   1.264.4.1     skrll 			*(uint8_t *)buf =
   3760  1.264.4.69     skrll 			    UHCI_PORTSC_GET_LS(UREAD2(sc, port));
   3761         1.1  augustss 			totlen = 1;
   3762         1.1  augustss 		}
   3763         1.1  augustss 		break;
   3764         1.1  augustss 	case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
   3765       1.195  christos 		if (len == 0)
   3766       1.195  christos 			break;
   3767       1.177    toshii 		if ((value & 0xff) != 0) {
   3768  1.264.4.12     skrll 			return -1;
   3769         1.1  augustss 		}
   3770  1.264.4.12     skrll 		usb_hub_descriptor_t hubd;
   3771  1.264.4.12     skrll 
   3772  1.264.4.12     skrll 		totlen = min(buflen, sizeof(hubd));
   3773  1.264.4.12     skrll 		memcpy(&hubd, buf, totlen);
   3774  1.264.4.12     skrll 		hubd.bNbrPorts = 2;
   3775  1.264.4.12     skrll 		memcpy(buf, &hubd, totlen);
   3776         1.1  augustss 		break;
   3777         1.1  augustss 	case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
   3778         1.1  augustss 		if (len != 4) {
   3779  1.264.4.12     skrll 			return -1;
   3780         1.1  augustss 		}
   3781         1.1  augustss 		memset(buf, 0, len);
   3782         1.1  augustss 		totlen = len;
   3783         1.1  augustss 		break;
   3784         1.1  augustss 	case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
   3785         1.1  augustss 		if (index == 1)
   3786         1.1  augustss 			port = UHCI_PORTSC1;
   3787         1.1  augustss 		else if (index == 2)
   3788         1.1  augustss 			port = UHCI_PORTSC2;
   3789         1.1  augustss 		else {
   3790  1.264.4.12     skrll 			return -1;
   3791         1.1  augustss 		}
   3792         1.1  augustss 		if (len != 4) {
   3793  1.264.4.12     skrll 			return -1;
   3794         1.1  augustss 		}
   3795         1.1  augustss 		x = UREAD2(sc, port);
   3796         1.1  augustss 		status = change = 0;
   3797       1.142  augustss 		if (x & UHCI_PORTSC_CCS)
   3798         1.1  augustss 			status |= UPS_CURRENT_CONNECT_STATUS;
   3799       1.152  augustss 		if (x & UHCI_PORTSC_CSC)
   3800         1.1  augustss 			change |= UPS_C_CONNECT_STATUS;
   3801       1.152  augustss 		if (x & UHCI_PORTSC_PE)
   3802         1.1  augustss 			status |= UPS_PORT_ENABLED;
   3803       1.152  augustss 		if (x & UHCI_PORTSC_POEDC)
   3804         1.1  augustss 			change |= UPS_C_PORT_ENABLED;
   3805       1.152  augustss 		if (x & UHCI_PORTSC_OCI)
   3806         1.1  augustss 			status |= UPS_OVERCURRENT_INDICATOR;
   3807       1.152  augustss 		if (x & UHCI_PORTSC_OCIC)
   3808         1.1  augustss 			change |= UPS_C_OVERCURRENT_INDICATOR;
   3809       1.152  augustss 		if (x & UHCI_PORTSC_SUSP)
   3810         1.1  augustss 			status |= UPS_SUSPEND;
   3811       1.152  augustss 		if (x & UHCI_PORTSC_LSDA)
   3812         1.1  augustss 			status |= UPS_LOW_SPEED;
   3813         1.1  augustss 		status |= UPS_PORT_POWER;
   3814         1.1  augustss 		if (sc->sc_isreset)
   3815         1.1  augustss 			change |= UPS_C_PORT_RESET;
   3816         1.1  augustss 		USETW(ps.wPortStatus, status);
   3817         1.1  augustss 		USETW(ps.wPortChange, change);
   3818  1.264.4.12     skrll 		totlen = min(len, sizeof(ps));
   3819  1.264.4.12     skrll 		memcpy(buf, &ps, totlen);
   3820         1.1  augustss 		break;
   3821         1.1  augustss 	case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
   3822  1.264.4.12     skrll 		return -1;
   3823         1.1  augustss 	case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
   3824         1.1  augustss 		break;
   3825         1.1  augustss 	case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
   3826         1.1  augustss 		if (index == 1)
   3827         1.1  augustss 			port = UHCI_PORTSC1;
   3828         1.1  augustss 		else if (index == 2)
   3829         1.1  augustss 			port = UHCI_PORTSC2;
   3830         1.1  augustss 		else {
   3831  1.264.4.12     skrll 			return -1;
   3832         1.1  augustss 		}
   3833         1.1  augustss 		switch(value) {
   3834         1.1  augustss 		case UHF_PORT_ENABLE:
   3835       1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3836         1.1  augustss 			UWRITE2(sc, port, x | UHCI_PORTSC_PE);
   3837         1.1  augustss 			break;
   3838         1.1  augustss 		case UHF_PORT_SUSPEND:
   3839       1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3840         1.1  augustss 			UWRITE2(sc, port, x | UHCI_PORTSC_SUSP);
   3841         1.1  augustss 			break;
   3842         1.1  augustss 		case UHF_PORT_RESET:
   3843       1.166   dsainty 			err = uhci_portreset(sc, index);
   3844  1.264.4.12     skrll 			if (err != USBD_NORMAL_COMPLETION)
   3845  1.264.4.12     skrll 				return -1;
   3846  1.264.4.12     skrll 			return 0;
   3847       1.111  augustss 		case UHF_PORT_POWER:
   3848       1.111  augustss 			/* Pretend we turned on power */
   3849  1.264.4.12     skrll 			return 0;
   3850         1.1  augustss 		case UHF_C_PORT_CONNECTION:
   3851         1.1  augustss 		case UHF_C_PORT_ENABLE:
   3852         1.1  augustss 		case UHF_C_PORT_OVER_CURRENT:
   3853         1.1  augustss 		case UHF_PORT_CONNECTION:
   3854         1.1  augustss 		case UHF_PORT_OVER_CURRENT:
   3855         1.1  augustss 		case UHF_PORT_LOW_SPEED:
   3856         1.1  augustss 		case UHF_C_PORT_SUSPEND:
   3857         1.1  augustss 		case UHF_C_PORT_RESET:
   3858         1.1  augustss 		default:
   3859  1.264.4.12     skrll 			return -1;
   3860         1.1  augustss 		}
   3861         1.1  augustss 		break;
   3862         1.1  augustss 	default:
   3863  1.264.4.12     skrll 		/* default from usbroothub */
   3864  1.264.4.27     skrll 		DPRINTF("returning %d (usbroothub default)",
   3865  1.264.4.21     skrll 		    buflen, 0, 0, 0);
   3866  1.264.4.12     skrll 		return buflen;
   3867         1.1  augustss 	}
   3868         1.1  augustss 
   3869  1.264.4.27     skrll 	DPRINTF("returning %d", totlen, 0, 0, 0);
   3870  1.264.4.21     skrll 
   3871  1.264.4.12     skrll 	return totlen;
   3872         1.1  augustss }
   3873         1.1  augustss 
   3874         1.1  augustss /* Abort a root interrupt request. */
   3875         1.1  augustss void
   3876  1.264.4.25     skrll uhci_root_intr_abort(struct usbd_xfer *xfer)
   3877         1.1  augustss {
   3878  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   3879        1.30  augustss 
   3880       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   3881   1.264.4.7     skrll 	KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
   3882       1.248       mrg 
   3883       1.234    dyoung 	callout_stop(&sc->sc_poll_handle);
   3884        1.96  augustss 	sc->sc_intr_xfer = NULL;
   3885        1.58  augustss 
   3886   1.264.4.7     skrll 	xfer->ux_status = USBD_CANCELLED;
   3887        1.96  augustss #ifdef DIAGNOSTIC
   3888  1.264.4.41     skrll 	UHCI_XFER2UXFER(xfer)->ux_isdone = true;
   3889        1.96  augustss #endif
   3890        1.63  augustss 	usb_transfer_complete(xfer);
   3891         1.1  augustss }
   3892         1.1  augustss 
   3893        1.16  augustss usbd_status
   3894  1.264.4.25     skrll uhci_root_intr_transfer(struct usbd_xfer *xfer)
   3895        1.16  augustss {
   3896  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   3897        1.63  augustss 	usbd_status err;
   3898        1.16  augustss 
   3899        1.52  augustss 	/* Insert last in queue. */
   3900       1.248       mrg 	mutex_enter(&sc->sc_lock);
   3901        1.63  augustss 	err = usb_insert_transfer(xfer);
   3902       1.248       mrg 	mutex_exit(&sc->sc_lock);
   3903        1.63  augustss 	if (err)
   3904  1.264.4.13     skrll 		return err;
   3905        1.52  augustss 
   3906       1.186     skrll 	/*
   3907       1.186     skrll 	 * Pipe isn't running (otherwise err would be USBD_INPROG),
   3908        1.67  augustss 	 * start first
   3909        1.67  augustss 	 */
   3910  1.264.4.13     skrll 	return uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
   3911        1.16  augustss }
   3912        1.16  augustss 
   3913         1.1  augustss /* Start a transfer on the root interrupt pipe */
   3914         1.1  augustss usbd_status
   3915  1.264.4.25     skrll uhci_root_intr_start(struct usbd_xfer *xfer)
   3916         1.1  augustss {
   3917  1.264.4.25     skrll 	struct usbd_pipe *pipe = xfer->ux_pipe;
   3918  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
   3919       1.174  drochner 	unsigned int ival;
   3920         1.1  augustss 
   3921  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3922  1.264.4.27     skrll 	DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length,
   3923  1.264.4.21     skrll 	    xfer->ux_flags, 0);
   3924        1.82  augustss 
   3925        1.82  augustss 	if (sc->sc_dying)
   3926  1.264.4.13     skrll 		return USBD_IOERROR;
   3927         1.1  augustss 
   3928       1.174  drochner 	/* XXX temporary variable needed to avoid gcc3 warning */
   3929   1.264.4.7     skrll 	ival = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval;
   3930       1.174  drochner 	sc->sc_ival = mstohz(ival);
   3931       1.234    dyoung 	callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer);
   3932        1.96  augustss 	sc->sc_intr_xfer = xfer;
   3933  1.264.4.13     skrll 	return USBD_IN_PROGRESS;
   3934         1.1  augustss }
   3935         1.1  augustss 
   3936         1.1  augustss /* Close the root interrupt pipe. */
   3937         1.1  augustss void
   3938  1.264.4.25     skrll uhci_root_intr_close(struct usbd_pipe *pipe)
   3939         1.1  augustss {
   3940  1.264.4.37     skrll 	uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
   3941  1.264.4.21     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3942        1.30  augustss 
   3943       1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   3944       1.248       mrg 
   3945       1.234    dyoung 	callout_stop(&sc->sc_poll_handle);
   3946        1.96  augustss 	sc->sc_intr_xfer = NULL;
   3947         1.1  augustss }
   3948