uhci.c revision 1.272 1 1.272 christos /* $NetBSD: uhci.c,v 1.272 2016/05/06 20:12:54 christos Exp $ */
2 1.1 augustss
3 1.1 augustss /*
4 1.248 mrg * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc.
5 1.1 augustss * All rights reserved.
6 1.1 augustss *
7 1.11 augustss * This code is derived from software contributed to The NetBSD Foundation
8 1.113 augustss * by Lennart Augustsson (lennart (at) augustsson.net) at
9 1.248 mrg * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca)
10 1.248 mrg * and Matthew R. Green (mrg (at) eterna.com.au).
11 1.1 augustss *
12 1.1 augustss * Redistribution and use in source and binary forms, with or without
13 1.1 augustss * modification, are permitted provided that the following conditions
14 1.1 augustss * are met:
15 1.1 augustss * 1. Redistributions of source code must retain the above copyright
16 1.1 augustss * notice, this list of conditions and the following disclaimer.
17 1.1 augustss * 2. Redistributions in binary form must reproduce the above copyright
18 1.1 augustss * notice, this list of conditions and the following disclaimer in the
19 1.1 augustss * documentation and/or other materials provided with the distribution.
20 1.1 augustss *
21 1.1 augustss * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22 1.1 augustss * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 1.1 augustss * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 1.1 augustss * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25 1.1 augustss * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 1.1 augustss * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 1.1 augustss * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 1.1 augustss * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 1.1 augustss * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 1.1 augustss * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 1.1 augustss * POSSIBILITY OF SUCH DAMAGE.
32 1.1 augustss */
33 1.1 augustss
34 1.1 augustss /*
35 1.1 augustss * USB Universal Host Controller driver.
36 1.28 augustss * Handles e.g. PIIX3 and PIIX4.
37 1.1 augustss *
38 1.229 uebayasi * UHCI spec: http://www.intel.com/technology/usb/spec.htm
39 1.229 uebayasi * USB spec: http://www.usb.org/developers/docs/
40 1.71 augustss * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf
41 1.71 augustss * ftp://download.intel.com/design/intarch/datashts/29056201.pdf
42 1.1 augustss */
43 1.143 lukem
44 1.143 lukem #include <sys/cdefs.h>
45 1.272 christos __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.272 2016/05/06 20:12:54 christos Exp $");
46 1.268 skrll
47 1.268 skrll #include "opt_usb.h"
48 1.1 augustss
49 1.1 augustss #include <sys/param.h>
50 1.268 skrll
51 1.268 skrll #include <sys/bus.h>
52 1.268 skrll #include <sys/cpu.h>
53 1.268 skrll #include <sys/device.h>
54 1.1 augustss #include <sys/kernel.h>
55 1.248 mrg #include <sys/kmem.h>
56 1.268 skrll #include <sys/mutex.h>
57 1.1 augustss #include <sys/proc.h>
58 1.1 augustss #include <sys/queue.h>
59 1.268 skrll #include <sys/select.h>
60 1.268 skrll #include <sys/sysctl.h>
61 1.268 skrll #include <sys/systm.h>
62 1.1 augustss
63 1.39 augustss #include <machine/endian.h>
64 1.7 augustss
65 1.1 augustss #include <dev/usb/usb.h>
66 1.1 augustss #include <dev/usb/usbdi.h>
67 1.1 augustss #include <dev/usb/usbdivar.h>
68 1.7 augustss #include <dev/usb/usb_mem.h>
69 1.1 augustss
70 1.1 augustss #include <dev/usb/uhcireg.h>
71 1.1 augustss #include <dev/usb/uhcivar.h>
72 1.268 skrll #include <dev/usb/usbroothub.h>
73 1.268 skrll #include <dev/usb/usbhist.h>
74 1.1 augustss
75 1.125 augustss /* Use bandwidth reclamation for control transfers. Some devices choke on it. */
76 1.125 augustss /*#define UHCI_CTL_LOOP */
77 1.125 augustss
78 1.67 augustss #ifdef UHCI_DEBUG
79 1.92 augustss uhci_softc_t *thesc;
80 1.125 augustss int uhcinoloop = 0;
81 1.268 skrll #endif
82 1.268 skrll
83 1.268 skrll #ifdef USB_DEBUG
84 1.268 skrll #ifndef UHCI_DEBUG
85 1.268 skrll #define uhcidebug 0
86 1.59 augustss #else
87 1.268 skrll static int uhcidebug = 0;
88 1.268 skrll
89 1.268 skrll SYSCTL_SETUP(sysctl_hw_uhci_setup, "sysctl hw.uhci setup")
90 1.268 skrll {
91 1.268 skrll int err;
92 1.268 skrll const struct sysctlnode *rnode;
93 1.268 skrll const struct sysctlnode *cnode;
94 1.268 skrll
95 1.268 skrll err = sysctl_createv(clog, 0, NULL, &rnode,
96 1.268 skrll CTLFLAG_PERMANENT, CTLTYPE_NODE, "uhci",
97 1.268 skrll SYSCTL_DESCR("uhci global controls"),
98 1.268 skrll NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
99 1.268 skrll
100 1.268 skrll if (err)
101 1.268 skrll goto fail;
102 1.268 skrll
103 1.268 skrll /* control debugging printfs */
104 1.268 skrll err = sysctl_createv(clog, 0, &rnode, &cnode,
105 1.268 skrll CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
106 1.268 skrll "debug", SYSCTL_DESCR("Enable debugging output"),
107 1.268 skrll NULL, 0, &uhcidebug, sizeof(uhcidebug), CTL_CREATE, CTL_EOL);
108 1.268 skrll if (err)
109 1.268 skrll goto fail;
110 1.268 skrll
111 1.268 skrll return;
112 1.268 skrll fail:
113 1.268 skrll aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err);
114 1.268 skrll }
115 1.268 skrll
116 1.268 skrll #endif /* UHCI_DEBUG */
117 1.268 skrll #endif /* USB_DEBUG */
118 1.268 skrll
119 1.268 skrll #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,1,FMT,A,B,C,D)
120 1.268 skrll #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,N,FMT,A,B,C,D)
121 1.268 skrll #define UHCIHIST_FUNC() USBHIST_FUNC()
122 1.268 skrll #define UHCIHIST_CALLED(name) USBHIST_CALLED(uhcidebug)
123 1.59 augustss
124 1.39 augustss /*
125 1.39 augustss * The UHCI controller is little endian, so on big endian machines
126 1.181 drochner * the data stored in memory needs to be swapped.
127 1.39 augustss */
128 1.39 augustss
129 1.1 augustss struct uhci_pipe {
130 1.1 augustss struct usbd_pipe pipe;
131 1.32 augustss int nexttoggle;
132 1.92 augustss
133 1.92 augustss u_char aborting;
134 1.268 skrll struct usbd_xfer *abortstart, abortend;
135 1.92 augustss
136 1.1 augustss /* Info needed for different pipe kinds. */
137 1.1 augustss union {
138 1.1 augustss /* Control pipe */
139 1.1 augustss struct {
140 1.1 augustss uhci_soft_qh_t *sqh;
141 1.7 augustss usb_dma_t reqdma;
142 1.268 skrll uhci_soft_td_t *setup;
143 1.268 skrll uhci_soft_td_t *stat;
144 1.268 skrll } ctrl;
145 1.1 augustss /* Interrupt pipe */
146 1.1 augustss struct {
147 1.1 augustss int npoll;
148 1.1 augustss uhci_soft_qh_t **qhs;
149 1.1 augustss } intr;
150 1.1 augustss /* Bulk pipe */
151 1.1 augustss struct {
152 1.1 augustss uhci_soft_qh_t *sqh;
153 1.1 augustss } bulk;
154 1.268 skrll /* Isochronous pipe */
155 1.268 skrll struct isoc {
156 1.16 augustss uhci_soft_td_t **stds;
157 1.48 augustss int next, inuse;
158 1.268 skrll } isoc;
159 1.268 skrll };
160 1.1 augustss };
161 1.1 augustss
162 1.268 skrll typedef TAILQ_HEAD(ux_completeq, uhci_xfer) ux_completeq_t;
163 1.268 skrll
164 1.142 augustss Static void uhci_globalreset(uhci_softc_t *);
165 1.166 dsainty Static usbd_status uhci_portreset(uhci_softc_t*, int);
166 1.142 augustss Static void uhci_reset(uhci_softc_t *);
167 1.268 skrll Static usbd_status uhci_run(uhci_softc_t *, int, int);
168 1.123 augustss Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *);
169 1.119 augustss Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *);
170 1.268 skrll Static void uhci_free_std_locked(uhci_softc_t *, uhci_soft_td_t *);
171 1.123 augustss Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *);
172 1.119 augustss Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *);
173 1.16 augustss #if 0
174 1.119 augustss Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *,
175 1.268 skrll uhci_intr_info_t *);
176 1.119 augustss Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *);
177 1.16 augustss #endif
178 1.1 augustss
179 1.268 skrll #if 0
180 1.268 skrll Static void uhci_free_std_chain(uhci_softc_t *, uhci_soft_td_t *,
181 1.268 skrll uhci_soft_td_t *);
182 1.268 skrll #endif
183 1.268 skrll Static int uhci_alloc_std_chain(uhci_softc_t *, struct usbd_xfer *,
184 1.268 skrll int, int, uhci_soft_td_t **);
185 1.268 skrll Static void uhci_free_stds(uhci_softc_t *, struct uhci_xfer *);
186 1.268 skrll
187 1.268 skrll Static void uhci_reset_std_chain(uhci_softc_t *, struct usbd_xfer *,
188 1.268 skrll int, int, int *, uhci_soft_td_t **);
189 1.268 skrll
190 1.119 augustss Static void uhci_poll_hub(void *);
191 1.268 skrll Static void uhci_check_intr(uhci_softc_t *, struct uhci_xfer *,
192 1.268 skrll ux_completeq_t *);
193 1.268 skrll Static void uhci_idone(struct uhci_xfer *, ux_completeq_t *);
194 1.119 augustss
195 1.268 skrll Static void uhci_abort_xfer(struct usbd_xfer *, usbd_status);
196 1.119 augustss
197 1.119 augustss Static void uhci_timeout(void *);
198 1.153 augustss Static void uhci_timeout_task(void *);
199 1.123 augustss Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *);
200 1.123 augustss Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *);
201 1.119 augustss Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *);
202 1.123 augustss Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *);
203 1.123 augustss Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *);
204 1.119 augustss Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *);
205 1.268 skrll Static void uhci_add_loop(uhci_softc_t *);
206 1.268 skrll Static void uhci_rem_loop(uhci_softc_t *);
207 1.119 augustss
208 1.268 skrll Static usbd_status uhci_setup_isoc(struct usbd_pipe *);
209 1.119 augustss
210 1.268 skrll Static struct usbd_xfer *
211 1.268 skrll uhci_allocx(struct usbd_bus *, unsigned int);
212 1.268 skrll Static void uhci_freex(struct usbd_bus *, struct usbd_xfer *);
213 1.248 mrg Static void uhci_get_lock(struct usbd_bus *, kmutex_t **);
214 1.268 skrll Static int uhci_roothub_ctrl(struct usbd_bus *,
215 1.268 skrll usb_device_request_t *, void *, int);
216 1.119 augustss
217 1.268 skrll Static int uhci_device_ctrl_init(struct usbd_xfer *);
218 1.268 skrll Static void uhci_device_ctrl_fini(struct usbd_xfer *);
219 1.268 skrll Static usbd_status uhci_device_ctrl_transfer(struct usbd_xfer *);
220 1.268 skrll Static usbd_status uhci_device_ctrl_start(struct usbd_xfer *);
221 1.268 skrll Static void uhci_device_ctrl_abort(struct usbd_xfer *);
222 1.268 skrll Static void uhci_device_ctrl_close(struct usbd_pipe *);
223 1.268 skrll Static void uhci_device_ctrl_done(struct usbd_xfer *);
224 1.268 skrll
225 1.268 skrll Static int uhci_device_intr_init(struct usbd_xfer *);
226 1.268 skrll Static void uhci_device_intr_fini(struct usbd_xfer *);
227 1.268 skrll Static usbd_status uhci_device_intr_transfer(struct usbd_xfer *);
228 1.268 skrll Static usbd_status uhci_device_intr_start(struct usbd_xfer *);
229 1.268 skrll Static void uhci_device_intr_abort(struct usbd_xfer *);
230 1.268 skrll Static void uhci_device_intr_close(struct usbd_pipe *);
231 1.268 skrll Static void uhci_device_intr_done(struct usbd_xfer *);
232 1.268 skrll
233 1.268 skrll Static int uhci_device_bulk_init(struct usbd_xfer *);
234 1.268 skrll Static void uhci_device_bulk_fini(struct usbd_xfer *);
235 1.268 skrll Static usbd_status uhci_device_bulk_transfer(struct usbd_xfer *);
236 1.268 skrll Static usbd_status uhci_device_bulk_start(struct usbd_xfer *);
237 1.268 skrll Static void uhci_device_bulk_abort(struct usbd_xfer *);
238 1.268 skrll Static void uhci_device_bulk_close(struct usbd_pipe *);
239 1.268 skrll Static void uhci_device_bulk_done(struct usbd_xfer *);
240 1.268 skrll
241 1.268 skrll Static int uhci_device_isoc_init(struct usbd_xfer *);
242 1.268 skrll Static void uhci_device_isoc_fini(struct usbd_xfer *);
243 1.268 skrll Static usbd_status uhci_device_isoc_transfer(struct usbd_xfer *);
244 1.268 skrll Static void uhci_device_isoc_abort(struct usbd_xfer *);
245 1.268 skrll Static void uhci_device_isoc_close(struct usbd_pipe *);
246 1.268 skrll Static void uhci_device_isoc_done(struct usbd_xfer *);
247 1.268 skrll
248 1.268 skrll Static usbd_status uhci_root_intr_transfer(struct usbd_xfer *);
249 1.268 skrll Static usbd_status uhci_root_intr_start(struct usbd_xfer *);
250 1.268 skrll Static void uhci_root_intr_abort(struct usbd_xfer *);
251 1.268 skrll Static void uhci_root_intr_close(struct usbd_pipe *);
252 1.268 skrll Static void uhci_root_intr_done(struct usbd_xfer *);
253 1.119 augustss
254 1.268 skrll Static usbd_status uhci_open(struct usbd_pipe *);
255 1.119 augustss Static void uhci_poll(struct usbd_bus *);
256 1.133 augustss Static void uhci_softintr(void *);
257 1.119 augustss
258 1.119 augustss Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *);
259 1.158 augustss Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *);
260 1.268 skrll Static usbd_status uhci_device_setintr(uhci_softc_t *,
261 1.268 skrll struct uhci_pipe *, int);
262 1.119 augustss
263 1.268 skrll Static void uhci_device_clear_toggle(struct usbd_pipe *);
264 1.268 skrll Static void uhci_noop(struct usbd_pipe *);
265 1.119 augustss
266 1.268 skrll static inline uhci_soft_qh_t *
267 1.268 skrll uhci_find_prev_qh(uhci_soft_qh_t *, uhci_soft_qh_t *);
268 1.119 augustss
269 1.119 augustss #ifdef UHCI_DEBUG
270 1.119 augustss Static void uhci_dump_all(uhci_softc_t *);
271 1.119 augustss Static void uhci_dumpregs(uhci_softc_t *);
272 1.119 augustss Static void uhci_dump_qhs(uhci_soft_qh_t *);
273 1.119 augustss Static void uhci_dump_qh(uhci_soft_qh_t *);
274 1.119 augustss Static void uhci_dump_tds(uhci_soft_td_t *);
275 1.119 augustss Static void uhci_dump_td(uhci_soft_td_t *);
276 1.268 skrll Static void uhci_dump_ii(struct uhci_xfer *);
277 1.119 augustss void uhci_dump(void);
278 1.1 augustss #endif
279 1.1 augustss
280 1.112 augustss #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \
281 1.112 augustss BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
282 1.112 augustss #define UWRITE1(sc, r, x) \
283 1.165 dsainty do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \
284 1.165 dsainty } while (/*CONSTCOND*/0)
285 1.112 augustss #define UWRITE2(sc, r, x) \
286 1.165 dsainty do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \
287 1.165 dsainty } while (/*CONSTCOND*/0)
288 1.112 augustss #define UWRITE4(sc, r, x) \
289 1.165 dsainty do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \
290 1.165 dsainty } while (/*CONSTCOND*/0)
291 1.268 skrll
292 1.196 mrg static __inline uint8_t
293 1.196 mrg UREAD1(uhci_softc_t *sc, bus_size_t r)
294 1.196 mrg {
295 1.196 mrg
296 1.196 mrg UBARR(sc);
297 1.196 mrg return bus_space_read_1(sc->iot, sc->ioh, r);
298 1.196 mrg }
299 1.196 mrg
300 1.196 mrg static __inline uint16_t
301 1.196 mrg UREAD2(uhci_softc_t *sc, bus_size_t r)
302 1.196 mrg {
303 1.196 mrg
304 1.196 mrg UBARR(sc);
305 1.196 mrg return bus_space_read_2(sc->iot, sc->ioh, r);
306 1.196 mrg }
307 1.196 mrg
308 1.260 joerg #ifdef UHCI_DEBUG
309 1.196 mrg static __inline uint32_t
310 1.196 mrg UREAD4(uhci_softc_t *sc, bus_size_t r)
311 1.196 mrg {
312 1.196 mrg
313 1.196 mrg UBARR(sc);
314 1.196 mrg return bus_space_read_4(sc->iot, sc->ioh, r);
315 1.196 mrg }
316 1.260 joerg #endif
317 1.1 augustss
318 1.1 augustss #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd)
319 1.1 augustss #define UHCISTS(sc) UREAD2(sc, UHCI_STS)
320 1.1 augustss
321 1.142 augustss #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */
322 1.1 augustss
323 1.1 augustss #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK)
324 1.1 augustss
325 1.208 drochner const struct usbd_bus_methods uhci_bus_methods = {
326 1.268 skrll .ubm_open = uhci_open,
327 1.268 skrll .ubm_softint = uhci_softintr,
328 1.268 skrll .ubm_dopoll = uhci_poll,
329 1.268 skrll .ubm_allocx = uhci_allocx,
330 1.268 skrll .ubm_freex = uhci_freex,
331 1.268 skrll .ubm_getlock = uhci_get_lock,
332 1.268 skrll .ubm_rhctrl = uhci_roothub_ctrl,
333 1.1 augustss };
334 1.1 augustss
335 1.208 drochner const struct usbd_pipe_methods uhci_root_intr_methods = {
336 1.268 skrll .upm_transfer = uhci_root_intr_transfer,
337 1.268 skrll .upm_start = uhci_root_intr_start,
338 1.268 skrll .upm_abort = uhci_root_intr_abort,
339 1.268 skrll .upm_close = uhci_root_intr_close,
340 1.268 skrll .upm_cleartoggle = uhci_noop,
341 1.268 skrll .upm_done = uhci_root_intr_done,
342 1.1 augustss };
343 1.1 augustss
344 1.208 drochner const struct usbd_pipe_methods uhci_device_ctrl_methods = {
345 1.268 skrll .upm_init = uhci_device_ctrl_init,
346 1.268 skrll .upm_fini = uhci_device_ctrl_fini,
347 1.268 skrll .upm_transfer = uhci_device_ctrl_transfer,
348 1.268 skrll .upm_start = uhci_device_ctrl_start,
349 1.268 skrll .upm_abort = uhci_device_ctrl_abort,
350 1.268 skrll .upm_close = uhci_device_ctrl_close,
351 1.268 skrll .upm_cleartoggle = uhci_noop,
352 1.268 skrll .upm_done = uhci_device_ctrl_done,
353 1.1 augustss };
354 1.1 augustss
355 1.208 drochner const struct usbd_pipe_methods uhci_device_intr_methods = {
356 1.268 skrll .upm_init = uhci_device_intr_init,
357 1.268 skrll .upm_fini = uhci_device_intr_fini,
358 1.268 skrll .upm_transfer = uhci_device_intr_transfer,
359 1.268 skrll .upm_start = uhci_device_intr_start,
360 1.268 skrll .upm_abort = uhci_device_intr_abort,
361 1.268 skrll .upm_close = uhci_device_intr_close,
362 1.268 skrll .upm_cleartoggle = uhci_device_clear_toggle,
363 1.268 skrll .upm_done = uhci_device_intr_done,
364 1.1 augustss };
365 1.1 augustss
366 1.208 drochner const struct usbd_pipe_methods uhci_device_bulk_methods = {
367 1.268 skrll .upm_init = uhci_device_bulk_init,
368 1.268 skrll .upm_fini = uhci_device_bulk_fini,
369 1.268 skrll .upm_transfer = uhci_device_bulk_transfer,
370 1.268 skrll .upm_start = uhci_device_bulk_start,
371 1.268 skrll .upm_abort = uhci_device_bulk_abort,
372 1.268 skrll .upm_close = uhci_device_bulk_close,
373 1.268 skrll .upm_cleartoggle = uhci_device_clear_toggle,
374 1.268 skrll .upm_done = uhci_device_bulk_done,
375 1.1 augustss };
376 1.1 augustss
377 1.208 drochner const struct usbd_pipe_methods uhci_device_isoc_methods = {
378 1.268 skrll .upm_init = uhci_device_isoc_init,
379 1.268 skrll .upm_fini = uhci_device_isoc_fini,
380 1.268 skrll .upm_transfer = uhci_device_isoc_transfer,
381 1.268 skrll .upm_abort = uhci_device_isoc_abort,
382 1.268 skrll .upm_close = uhci_device_isoc_close,
383 1.268 skrll .upm_cleartoggle = uhci_noop,
384 1.268 skrll .upm_done = uhci_device_isoc_done,
385 1.16 augustss };
386 1.16 augustss
387 1.268 skrll static inline void
388 1.268 skrll uhci_add_intr_list(uhci_softc_t *sc, struct uhci_xfer *ux)
389 1.268 skrll {
390 1.268 skrll
391 1.268 skrll TAILQ_INSERT_TAIL(&sc->sc_intrhead, ux, ux_list);
392 1.268 skrll }
393 1.268 skrll
394 1.268 skrll static inline void
395 1.268 skrll uhci_del_intr_list(uhci_softc_t *sc, struct uhci_xfer *ux)
396 1.268 skrll {
397 1.268 skrll
398 1.268 skrll TAILQ_REMOVE(&sc->sc_intrhead, ux, ux_list);
399 1.268 skrll }
400 1.92 augustss
401 1.240 jakllsch static inline uhci_soft_qh_t *
402 1.119 augustss uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh)
403 1.92 augustss {
404 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
405 1.268 skrll DPRINTFN(15, "pqh=%p sqh=%p", pqh, sqh, 0, 0);
406 1.92 augustss
407 1.92 augustss for (; pqh->hlink != sqh; pqh = pqh->hlink) {
408 1.152 augustss #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG)
409 1.223 bouyer usb_syncmem(&pqh->dma,
410 1.223 bouyer pqh->offs + offsetof(uhci_qh_t, qh_hlink),
411 1.223 bouyer sizeof(pqh->qh.qh_hlink),
412 1.223 bouyer BUS_DMASYNC_POSTWRITE);
413 1.92 augustss if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) {
414 1.268 skrll printf("%s: QH not found\n", __func__);
415 1.268 skrll return NULL;
416 1.92 augustss }
417 1.92 augustss #endif
418 1.92 augustss }
419 1.268 skrll return pqh;
420 1.92 augustss }
421 1.92 augustss
422 1.1 augustss void
423 1.142 augustss uhci_globalreset(uhci_softc_t *sc)
424 1.1 augustss {
425 1.1 augustss UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */
426 1.20 augustss usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */
427 1.1 augustss UHCICMD(sc, 0); /* do nothing */
428 1.1 augustss }
429 1.1 augustss
430 1.268 skrll int
431 1.119 augustss uhci_init(uhci_softc_t *sc)
432 1.1 augustss {
433 1.63 augustss usbd_status err;
434 1.1 augustss int i, j;
435 1.123 augustss uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh;
436 1.1 augustss uhci_soft_td_t *std;
437 1.1 augustss
438 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
439 1.1 augustss
440 1.67 augustss #ifdef UHCI_DEBUG
441 1.92 augustss thesc = sc;
442 1.92 augustss
443 1.268 skrll if (uhcidebug >= 2)
444 1.1 augustss uhci_dumpregs(sc);
445 1.1 augustss #endif
446 1.1 augustss
447 1.219 jmcneill sc->sc_suspend = PWR_RESUME;
448 1.219 jmcneill
449 1.1 augustss UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */
450 1.142 augustss uhci_globalreset(sc); /* reset the controller */
451 1.142 augustss uhci_reset(sc);
452 1.24 augustss
453 1.1 augustss /* Allocate and initialize real frame array. */
454 1.152 augustss err = usb_allocmem(&sc->sc_bus,
455 1.268 skrll UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t),
456 1.268 skrll UHCI_FRAMELIST_ALIGN, &sc->sc_dma);
457 1.63 augustss if (err)
458 1.268 skrll return err;
459 1.159 augustss sc->sc_pframes = KERNADDR(&sc->sc_dma, 0);
460 1.1 augustss UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */
461 1.160 augustss UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/
462 1.1 augustss
463 1.268 skrll /* Initialise mutex early for uhci_alloc_* */
464 1.268 skrll mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
465 1.268 skrll mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB);
466 1.268 skrll
467 1.152 augustss /*
468 1.123 augustss * Allocate a TD, inactive, that hangs from the last QH.
469 1.123 augustss * This is to avoid a bug in the PIIX that makes it run berserk
470 1.123 augustss * otherwise.
471 1.123 augustss */
472 1.123 augustss std = uhci_alloc_std(sc);
473 1.123 augustss if (std == NULL)
474 1.268 skrll return ENOMEM;
475 1.123 augustss std->link.std = NULL;
476 1.123 augustss std->td.td_link = htole32(UHCI_PTR_T);
477 1.123 augustss std->td.td_status = htole32(0); /* inactive */
478 1.123 augustss std->td.td_token = htole32(0);
479 1.123 augustss std->td.td_buffer = htole32(0);
480 1.223 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
481 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
482 1.123 augustss
483 1.123 augustss /* Allocate the dummy QH marking the end and used for looping the QHs.*/
484 1.123 augustss lsqh = uhci_alloc_sqh(sc);
485 1.123 augustss if (lsqh == NULL)
486 1.268 skrll goto fail1;
487 1.123 augustss lsqh->hlink = NULL;
488 1.123 augustss lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */
489 1.123 augustss lsqh->elink = std;
490 1.123 augustss lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD);
491 1.123 augustss sc->sc_last_qh = lsqh;
492 1.223 bouyer usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh),
493 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
494 1.123 augustss
495 1.1 augustss /* Allocate the dummy QH where bulk traffic will be queued. */
496 1.1 augustss bsqh = uhci_alloc_sqh(sc);
497 1.63 augustss if (bsqh == NULL)
498 1.268 skrll goto fail2;
499 1.123 augustss bsqh->hlink = lsqh;
500 1.123 augustss bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH);
501 1.121 augustss bsqh->elink = NULL;
502 1.88 tsutsui bsqh->qh.qh_elink = htole32(UHCI_PTR_T);
503 1.1 augustss sc->sc_bulk_start = sc->sc_bulk_end = bsqh;
504 1.223 bouyer usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh),
505 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
506 1.1 augustss
507 1.123 augustss /* Allocate dummy QH where high speed control traffic will be queued. */
508 1.123 augustss chsqh = uhci_alloc_sqh(sc);
509 1.123 augustss if (chsqh == NULL)
510 1.268 skrll goto fail3;
511 1.123 augustss chsqh->hlink = bsqh;
512 1.123 augustss chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH);
513 1.123 augustss chsqh->elink = NULL;
514 1.123 augustss chsqh->qh.qh_elink = htole32(UHCI_PTR_T);
515 1.123 augustss sc->sc_hctl_start = sc->sc_hctl_end = chsqh;
516 1.223 bouyer usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh),
517 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
518 1.123 augustss
519 1.123 augustss /* Allocate dummy QH where control traffic will be queued. */
520 1.123 augustss clsqh = uhci_alloc_sqh(sc);
521 1.123 augustss if (clsqh == NULL)
522 1.268 skrll goto fail4;
523 1.220 bouyer clsqh->hlink = chsqh;
524 1.123 augustss clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH);
525 1.123 augustss clsqh->elink = NULL;
526 1.123 augustss clsqh->qh.qh_elink = htole32(UHCI_PTR_T);
527 1.123 augustss sc->sc_lctl_start = sc->sc_lctl_end = clsqh;
528 1.223 bouyer usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh),
529 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
530 1.1 augustss
531 1.152 augustss /*
532 1.1 augustss * Make all (virtual) frame list pointers point to the interrupt
533 1.1 augustss * queue heads and the interrupt queue heads at the control
534 1.1 augustss * queue head and point the physical frame list to the virtual.
535 1.1 augustss */
536 1.267 skrll for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
537 1.1 augustss std = uhci_alloc_std(sc);
538 1.1 augustss sqh = uhci_alloc_sqh(sc);
539 1.67 augustss if (std == NULL || sqh == NULL)
540 1.268 skrll return USBD_NOMEM;
541 1.42 augustss std->link.sqh = sqh;
542 1.121 augustss std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH);
543 1.88 tsutsui std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */
544 1.88 tsutsui std->td.td_token = htole32(0);
545 1.88 tsutsui std->td.td_buffer = htole32(0);
546 1.223 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
547 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
548 1.123 augustss sqh->hlink = clsqh;
549 1.123 augustss sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH);
550 1.121 augustss sqh->elink = NULL;
551 1.88 tsutsui sqh->qh.qh_elink = htole32(UHCI_PTR_T);
552 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
553 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
554 1.1 augustss sc->sc_vframes[i].htd = std;
555 1.1 augustss sc->sc_vframes[i].etd = std;
556 1.1 augustss sc->sc_vframes[i].hqh = sqh;
557 1.1 augustss sc->sc_vframes[i].eqh = sqh;
558 1.152 augustss for (j = i;
559 1.152 augustss j < UHCI_FRAMELIST_COUNT;
560 1.1 augustss j += UHCI_VFRAMELIST_COUNT)
561 1.88 tsutsui sc->sc_pframes[j] = htole32(std->physaddr);
562 1.1 augustss }
563 1.223 bouyer usb_syncmem(&sc->sc_dma, 0,
564 1.223 bouyer UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t),
565 1.223 bouyer BUS_DMASYNC_PREWRITE);
566 1.223 bouyer
567 1.1 augustss
568 1.268 skrll TAILQ_INIT(&sc->sc_intrhead);
569 1.1 augustss
570 1.253 christos sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0,
571 1.253 christos "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL);
572 1.76 augustss
573 1.248 mrg callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE);
574 1.248 mrg
575 1.248 mrg cv_init(&sc->sc_softwake_cv, "uhciab");
576 1.96 augustss
577 1.1 augustss /* Set up the bus struct. */
578 1.268 skrll sc->sc_bus.ub_methods = &uhci_bus_methods;
579 1.268 skrll sc->sc_bus.ub_pipesize = sizeof(struct uhci_pipe);
580 1.268 skrll sc->sc_bus.ub_usedma = true;
581 1.1 augustss
582 1.190 augustss UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */
583 1.190 augustss
584 1.268 skrll DPRINTF("Enabling...", 0, 0, 0, 0);
585 1.225 bouyer
586 1.268 skrll err = uhci_run(sc, 1, 0); /* and here we go... */
587 1.152 augustss UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE |
588 1.1 augustss UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */
589 1.225 bouyer return err;
590 1.268 skrll
591 1.268 skrll fail4:
592 1.268 skrll uhci_free_sqh(sc, chsqh);
593 1.268 skrll fail3:
594 1.268 skrll uhci_free_sqh(sc, lsqh);
595 1.268 skrll fail2:
596 1.268 skrll uhci_free_sqh(sc, lsqh);
597 1.268 skrll fail1:
598 1.268 skrll uhci_free_std(sc, std);
599 1.268 skrll
600 1.268 skrll return ENOMEM;
601 1.53 augustss }
602 1.53 augustss
603 1.53 augustss int
604 1.215 dyoung uhci_activate(device_t self, enum devact act)
605 1.53 augustss {
606 1.215 dyoung struct uhci_softc *sc = device_private(self);
607 1.53 augustss
608 1.53 augustss switch (act) {
609 1.53 augustss case DVACT_DEACTIVATE:
610 1.210 kiyohara sc->sc_dying = 1;
611 1.230 dyoung return 0;
612 1.230 dyoung default:
613 1.230 dyoung return EOPNOTSUPP;
614 1.53 augustss }
615 1.53 augustss }
616 1.53 augustss
617 1.215 dyoung void
618 1.215 dyoung uhci_childdet(device_t self, device_t child)
619 1.215 dyoung {
620 1.215 dyoung struct uhci_softc *sc = device_private(self);
621 1.215 dyoung
622 1.215 dyoung KASSERT(sc->sc_child == child);
623 1.215 dyoung sc->sc_child = NULL;
624 1.215 dyoung }
625 1.215 dyoung
626 1.53 augustss int
627 1.119 augustss uhci_detach(struct uhci_softc *sc, int flags)
628 1.53 augustss {
629 1.53 augustss int rv = 0;
630 1.53 augustss
631 1.53 augustss if (sc->sc_child != NULL)
632 1.53 augustss rv = config_detach(sc->sc_child, flags);
633 1.152 augustss
634 1.53 augustss if (rv != 0)
635 1.268 skrll return rv;
636 1.53 augustss
637 1.226 ad callout_halt(&sc->sc_poll_handle, NULL);
638 1.226 ad callout_destroy(&sc->sc_poll_handle);
639 1.226 ad
640 1.248 mrg cv_destroy(&sc->sc_softwake_cv);
641 1.248 mrg
642 1.248 mrg mutex_destroy(&sc->sc_lock);
643 1.248 mrg mutex_destroy(&sc->sc_intr_lock);
644 1.248 mrg
645 1.254 christos pool_cache_destroy(sc->sc_xferpool);
646 1.254 christos
647 1.76 augustss /* XXX free other data structures XXX */
648 1.53 augustss
649 1.268 skrll return rv;
650 1.76 augustss }
651 1.76 augustss
652 1.268 skrll struct usbd_xfer *
653 1.268 skrll uhci_allocx(struct usbd_bus *bus, unsigned int nframes)
654 1.76 augustss {
655 1.268 skrll struct uhci_softc *sc = UHCI_BUS2SC(bus);
656 1.268 skrll struct usbd_xfer *xfer;
657 1.76 augustss
658 1.253 christos xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT);
659 1.92 augustss if (xfer != NULL) {
660 1.253 christos memset(xfer, 0, sizeof(struct uhci_xfer));
661 1.268 skrll
662 1.92 augustss #ifdef DIAGNOSTIC
663 1.268 skrll struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
664 1.268 skrll uxfer->ux_isdone = true;
665 1.268 skrll xfer->ux_state = XFER_BUSY;
666 1.92 augustss #endif
667 1.92 augustss }
668 1.268 skrll return xfer;
669 1.76 augustss }
670 1.76 augustss
671 1.76 augustss void
672 1.268 skrll uhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer)
673 1.76 augustss {
674 1.268 skrll struct uhci_softc *sc = UHCI_BUS2SC(bus);
675 1.268 skrll struct uhci_xfer *uxfer __diagused = UHCI_XFER2UXFER(xfer);
676 1.76 augustss
677 1.268 skrll KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer,
678 1.268 skrll xfer->ux_state);
679 1.268 skrll KASSERTMSG(uxfer->ux_isdone, "xfer %p not done\n", xfer);
680 1.93 augustss #ifdef DIAGNOSTIC
681 1.268 skrll xfer->ux_state = XFER_FREE;
682 1.93 augustss #endif
683 1.253 christos pool_cache_put(sc->sc_xferpool, xfer);
684 1.48 augustss }
685 1.48 augustss
686 1.248 mrg Static void
687 1.248 mrg uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock)
688 1.248 mrg {
689 1.268 skrll struct uhci_softc *sc = UHCI_BUS2SC(bus);
690 1.248 mrg
691 1.248 mrg *lock = &sc->sc_lock;
692 1.248 mrg }
693 1.248 mrg
694 1.248 mrg
695 1.72 augustss /*
696 1.212 jmcneill * Handle suspend/resume.
697 1.212 jmcneill *
698 1.212 jmcneill * We need to switch to polling mode here, because this routine is
699 1.212 jmcneill * called from an interrupt context. This is all right since we
700 1.212 jmcneill * are almost suspended anyway.
701 1.72 augustss */
702 1.212 jmcneill bool
703 1.232 dyoung uhci_resume(device_t dv, const pmf_qual_t *qual)
704 1.72 augustss {
705 1.212 jmcneill uhci_softc_t *sc = device_private(dv);
706 1.212 jmcneill int cmd;
707 1.72 augustss
708 1.248 mrg mutex_spin_enter(&sc->sc_intr_lock);
709 1.193 augustss
710 1.212 jmcneill cmd = UREAD2(sc, UHCI_CMD);
711 1.268 skrll sc->sc_bus.ub_usepolling++;
712 1.214 smb UWRITE2(sc, UHCI_INTR, 0);
713 1.214 smb uhci_globalreset(sc);
714 1.214 smb uhci_reset(sc);
715 1.212 jmcneill if (cmd & UHCI_CMD_RS)
716 1.249 drochner uhci_run(sc, 0, 1);
717 1.212 jmcneill
718 1.212 jmcneill /* restore saved state */
719 1.212 jmcneill UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0));
720 1.212 jmcneill UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum);
721 1.212 jmcneill UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof);
722 1.212 jmcneill
723 1.212 jmcneill UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */
724 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock);
725 1.212 jmcneill UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */
726 1.212 jmcneill UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE |
727 1.212 jmcneill UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE);
728 1.214 smb UHCICMD(sc, UHCI_CMD_MAXP);
729 1.249 drochner uhci_run(sc, 1, 1); /* and start traffic again */
730 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock);
731 1.268 skrll sc->sc_bus.ub_usepolling--;
732 1.212 jmcneill if (sc->sc_intr_xfer != NULL)
733 1.234 dyoung callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub,
734 1.212 jmcneill sc->sc_intr_xfer);
735 1.212 jmcneill #ifdef UHCI_DEBUG
736 1.268 skrll if (uhcidebug >= 2)
737 1.212 jmcneill uhci_dumpregs(sc);
738 1.212 jmcneill #endif
739 1.212 jmcneill
740 1.219 jmcneill sc->sc_suspend = PWR_RESUME;
741 1.248 mrg mutex_spin_exit(&sc->sc_intr_lock);
742 1.212 jmcneill
743 1.212 jmcneill return true;
744 1.72 augustss }
745 1.72 augustss
746 1.212 jmcneill bool
747 1.232 dyoung uhci_suspend(device_t dv, const pmf_qual_t *qual)
748 1.30 augustss {
749 1.212 jmcneill uhci_softc_t *sc = device_private(dv);
750 1.30 augustss int cmd;
751 1.30 augustss
752 1.248 mrg mutex_spin_enter(&sc->sc_intr_lock);
753 1.212 jmcneill
754 1.30 augustss cmd = UREAD2(sc, UHCI_CMD);
755 1.30 augustss
756 1.212 jmcneill #ifdef UHCI_DEBUG
757 1.268 skrll if (uhcidebug >= 2)
758 1.212 jmcneill uhci_dumpregs(sc);
759 1.212 jmcneill #endif
760 1.212 jmcneill if (sc->sc_intr_xfer != NULL)
761 1.234 dyoung callout_stop(&sc->sc_poll_handle);
762 1.219 jmcneill sc->sc_suspend = PWR_SUSPEND;
763 1.268 skrll sc->sc_bus.ub_usepolling++;
764 1.219 jmcneill
765 1.249 drochner uhci_run(sc, 0, 1); /* stop the controller */
766 1.212 jmcneill cmd &= ~UHCI_CMD_RS;
767 1.212 jmcneill
768 1.212 jmcneill /* save some state if BIOS doesn't */
769 1.212 jmcneill sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM);
770 1.212 jmcneill sc->sc_saved_sof = UREAD1(sc, UHCI_SOF);
771 1.212 jmcneill
772 1.212 jmcneill UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */
773 1.30 augustss
774 1.212 jmcneill UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */
775 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock);
776 1.268 skrll sc->sc_bus.ub_usepolling--;
777 1.86 augustss
778 1.248 mrg mutex_spin_exit(&sc->sc_intr_lock);
779 1.212 jmcneill
780 1.212 jmcneill return true;
781 1.30 augustss }
782 1.30 augustss
783 1.59 augustss #ifdef UHCI_DEBUG
784 1.101 augustss Static void
785 1.119 augustss uhci_dumpregs(uhci_softc_t *sc)
786 1.1 augustss {
787 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
788 1.268 skrll DPRINTF("cmd =%04x sts =%04x intr =%04x frnum =%04x",
789 1.268 skrll UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS),
790 1.268 skrll UREAD2(sc, UHCI_INTR), UREAD2(sc, UHCI_FRNUM));
791 1.268 skrll DPRINTF("sof =%04x portsc1=%04x portsc2=%04x flbase=%08x",
792 1.268 skrll UREAD1(sc, UHCI_SOF), UREAD2(sc, UHCI_PORTSC1),
793 1.268 skrll UREAD2(sc, UHCI_PORTSC2), UREAD4(sc, UHCI_FLBASEADDR));
794 1.1 augustss }
795 1.1 augustss
796 1.1 augustss void
797 1.119 augustss uhci_dump_td(uhci_soft_td_t *p)
798 1.1 augustss {
799 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
800 1.250 christos
801 1.223 bouyer usb_syncmem(&p->dma, p->offs, sizeof(p->td),
802 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
803 1.268 skrll
804 1.268 skrll DPRINTF("TD(%p) at 0x%08x", p, p->physaddr, 0, 0);
805 1.268 skrll DPRINTF(" link=0x%08x status=0x%08x "
806 1.268 skrll "token=0x%08x buffer=0x%08x",
807 1.268 skrll le32toh(p->td.td_link),
808 1.268 skrll le32toh(p->td.td_status),
809 1.268 skrll le32toh(p->td.td_token),
810 1.268 skrll le32toh(p->td.td_buffer));
811 1.268 skrll
812 1.268 skrll DPRINTF("bitstuff=%d crcto =%d nak =%d babble =%d",
813 1.268 skrll !!(le32toh(p->td.td_status) & UHCI_TD_BITSTUFF),
814 1.268 skrll !!(le32toh(p->td.td_status) & UHCI_TD_CRCTO),
815 1.268 skrll !!(le32toh(p->td.td_status) & UHCI_TD_NAK),
816 1.268 skrll !!(le32toh(p->td.td_status) & UHCI_TD_BABBLE));
817 1.268 skrll DPRINTF("dbuffer =%d stalled =%d active =%d ioc =%d",
818 1.268 skrll !!(le32toh(p->td.td_status) & UHCI_TD_DBUFFER),
819 1.268 skrll !!(le32toh(p->td.td_status) & UHCI_TD_STALLED),
820 1.268 skrll !!(le32toh(p->td.td_status) & UHCI_TD_ACTIVE),
821 1.268 skrll !!(le32toh(p->td.td_status) & UHCI_TD_IOC));
822 1.268 skrll DPRINTF("ios =%d ls =%d spd =%d",
823 1.268 skrll !!(le32toh(p->td.td_status) & UHCI_TD_IOS),
824 1.268 skrll !!(le32toh(p->td.td_status) & UHCI_TD_LS),
825 1.268 skrll !!(le32toh(p->td.td_status) & UHCI_TD_SPD), 0);
826 1.268 skrll DPRINTF("errcnt =%d actlen =%d pid=%02x",
827 1.268 skrll UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)),
828 1.268 skrll UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)),
829 1.268 skrll UHCI_TD_GET_PID(le32toh(p->td.td_token)), 0);
830 1.268 skrll DPRINTF("addr=%d endpt=%d D=%d maxlen=%d,",
831 1.268 skrll UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)),
832 1.268 skrll UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)),
833 1.268 skrll UHCI_TD_GET_DT(le32toh(p->td.td_token)),
834 1.268 skrll UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token)));
835 1.1 augustss }
836 1.1 augustss
837 1.1 augustss void
838 1.119 augustss uhci_dump_qh(uhci_soft_qh_t *sqh)
839 1.1 augustss {
840 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
841 1.268 skrll
842 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
843 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
844 1.268 skrll
845 1.268 skrll DPRINTF("QH(%p) at 0x%08x: hlink=%08x elink=%08x", sqh,
846 1.88 tsutsui (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink),
847 1.268 skrll le32toh(sqh->qh.qh_elink));
848 1.268 skrll
849 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD);
850 1.1 augustss }
851 1.1 augustss
852 1.13 augustss
853 1.110 augustss #if 1
854 1.1 augustss void
855 1.119 augustss uhci_dump(void)
856 1.1 augustss {
857 1.110 augustss uhci_dump_all(thesc);
858 1.110 augustss }
859 1.110 augustss #endif
860 1.1 augustss
861 1.110 augustss void
862 1.119 augustss uhci_dump_all(uhci_softc_t *sc)
863 1.110 augustss {
864 1.1 augustss uhci_dumpregs(sc);
865 1.110 augustss /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/
866 1.261 skrll uhci_dump_qhs(sc->sc_lctl_start);
867 1.1 augustss }
868 1.1 augustss
869 1.67 augustss
870 1.67 augustss void
871 1.119 augustss uhci_dump_qhs(uhci_soft_qh_t *sqh)
872 1.67 augustss {
873 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
874 1.268 skrll
875 1.67 augustss uhci_dump_qh(sqh);
876 1.67 augustss
877 1.268 skrll /*
878 1.268 skrll * uhci_dump_qhs displays all the QHs and TDs from the given QH onwards
879 1.67 augustss * Traverses sideways first, then down.
880 1.67 augustss *
881 1.67 augustss * QH1
882 1.67 augustss * QH2
883 1.67 augustss * No QH
884 1.67 augustss * TD2.1
885 1.67 augustss * TD2.2
886 1.67 augustss * TD1.1
887 1.67 augustss * etc.
888 1.67 augustss *
889 1.67 augustss * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1.
890 1.67 augustss */
891 1.67 augustss
892 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
893 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
894 1.88 tsutsui if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T))
895 1.67 augustss uhci_dump_qhs(sqh->hlink);
896 1.67 augustss else
897 1.268 skrll DPRINTF("No QH", 0, 0, 0, 0);
898 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD);
899 1.67 augustss
900 1.88 tsutsui if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T))
901 1.67 augustss uhci_dump_tds(sqh->elink);
902 1.67 augustss else
903 1.268 skrll DPRINTF("No QH", 0, 0, 0, 0);
904 1.67 augustss }
905 1.67 augustss
906 1.1 augustss void
907 1.119 augustss uhci_dump_tds(uhci_soft_td_t *std)
908 1.1 augustss {
909 1.67 augustss uhci_soft_td_t *td;
910 1.223 bouyer int stop;
911 1.67 augustss
912 1.267 skrll for (td = std; td != NULL; td = td->link.std) {
913 1.67 augustss uhci_dump_td(td);
914 1.1 augustss
915 1.268 skrll /*
916 1.268 skrll * Check whether the link pointer in this TD marks
917 1.67 augustss * the link pointer as end of queue. This avoids
918 1.67 augustss * printing the free list in case the queue/TD has
919 1.67 augustss * already been moved there (seatbelt).
920 1.67 augustss */
921 1.223 bouyer usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link),
922 1.223 bouyer sizeof(td->td.td_link),
923 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
924 1.223 bouyer stop = (le32toh(td->td.td_link) & UHCI_PTR_T ||
925 1.223 bouyer le32toh(td->td.td_link) == 0);
926 1.223 bouyer usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link),
927 1.223 bouyer sizeof(td->td.td_link), BUS_DMASYNC_PREREAD);
928 1.223 bouyer if (stop)
929 1.67 augustss break;
930 1.67 augustss }
931 1.1 augustss }
932 1.92 augustss
933 1.101 augustss Static void
934 1.268 skrll uhci_dump_ii(struct uhci_xfer *ux)
935 1.92 augustss {
936 1.268 skrll struct usbd_pipe *pipe;
937 1.95 augustss usb_endpoint_descriptor_t *ed;
938 1.268 skrll struct usbd_device *dev;
939 1.152 augustss
940 1.268 skrll if (ux == NULL) {
941 1.268 skrll printf("ux NULL\n");
942 1.268 skrll return;
943 1.268 skrll }
944 1.268 skrll pipe = ux->ux_xfer.ux_pipe;
945 1.268 skrll if (pipe == NULL) {
946 1.268 skrll printf("ux %p: done=%d pipe=NULL\n", ux, ux->ux_isdone);
947 1.268 skrll return;
948 1.268 skrll }
949 1.268 skrll if (pipe->up_endpoint == NULL) {
950 1.268 skrll printf("ux %p: done=%d pipe=%p pipe->up_endpoint=NULL\n",
951 1.268 skrll ux, ux->ux_isdone, pipe);
952 1.268 skrll return;
953 1.268 skrll }
954 1.268 skrll if (pipe->up_dev == NULL) {
955 1.268 skrll printf("ux %p: done=%d pipe=%p pipe->up_dev=NULL\n",
956 1.268 skrll ux, ux->ux_isdone, pipe);
957 1.268 skrll return;
958 1.268 skrll }
959 1.268 skrll ed = pipe->up_endpoint->ue_edesc;
960 1.268 skrll dev = pipe->up_dev;
961 1.268 skrll printf("ux %p: done=%d dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n",
962 1.268 skrll ux, ux->ux_isdone, dev,
963 1.268 skrll UGETW(dev->ud_ddesc.idVendor),
964 1.268 skrll UGETW(dev->ud_ddesc.idProduct),
965 1.268 skrll dev->ud_addr, pipe,
966 1.92 augustss ed->bEndpointAddress, ed->bmAttributes);
967 1.92 augustss }
968 1.92 augustss
969 1.120 augustss void uhci_dump_iis(struct uhci_softc *sc);
970 1.92 augustss void
971 1.119 augustss uhci_dump_iis(struct uhci_softc *sc)
972 1.92 augustss {
973 1.268 skrll struct uhci_xfer *ux;
974 1.92 augustss
975 1.268 skrll printf("interrupt list:\n");
976 1.268 skrll TAILQ_FOREACH(ux, &sc->sc_intrhead, ux_list)
977 1.268 skrll uhci_dump_ii(ux);
978 1.92 augustss }
979 1.92 augustss
980 1.120 augustss void iidump(void);
981 1.119 augustss void iidump(void) { uhci_dump_iis(thesc); }
982 1.92 augustss
983 1.1 augustss #endif
984 1.1 augustss
985 1.1 augustss /*
986 1.1 augustss * This routine is executed periodically and simulates interrupts
987 1.1 augustss * from the root controller interrupt pipe for port status change.
988 1.1 augustss */
989 1.1 augustss void
990 1.119 augustss uhci_poll_hub(void *addr)
991 1.1 augustss {
992 1.268 skrll struct usbd_xfer *xfer = addr;
993 1.268 skrll struct usbd_pipe *pipe = xfer->ux_pipe;
994 1.227 martin uhci_softc_t *sc;
995 1.1 augustss u_char *p;
996 1.1 augustss
997 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
998 1.1 augustss
999 1.268 skrll if (__predict_false(pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL))
1000 1.228 martin return; /* device has detached */
1001 1.268 skrll sc = UHCI_PIPE2SC(pipe);
1002 1.234 dyoung callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer);
1003 1.41 augustss
1004 1.268 skrll p = xfer->ux_buf;
1005 1.1 augustss p[0] = 0;
1006 1.1 augustss if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC))
1007 1.1 augustss p[0] |= 1<<1;
1008 1.1 augustss if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC))
1009 1.1 augustss p[0] |= 1<<2;
1010 1.41 augustss if (p[0] == 0)
1011 1.41 augustss /* No change, try again in a while */
1012 1.41 augustss return;
1013 1.41 augustss
1014 1.268 skrll xfer->ux_actlen = 1;
1015 1.268 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1016 1.248 mrg mutex_enter(&sc->sc_lock);
1017 1.63 augustss usb_transfer_complete(xfer);
1018 1.248 mrg mutex_exit(&sc->sc_lock);
1019 1.41 augustss }
1020 1.41 augustss
1021 1.41 augustss void
1022 1.268 skrll uhci_root_intr_done(struct usbd_xfer *xfer)
1023 1.41 augustss {
1024 1.1 augustss }
1025 1.1 augustss
1026 1.123 augustss /*
1027 1.123 augustss * Let the last QH loop back to the high speed control transfer QH.
1028 1.123 augustss * This is what intel calls "bandwidth reclamation" and improves
1029 1.123 augustss * USB performance a lot for some devices.
1030 1.123 augustss * If we are already looping, just count it.
1031 1.123 augustss */
1032 1.1 augustss void
1033 1.268 skrll uhci_add_loop(uhci_softc_t *sc)
1034 1.268 skrll {
1035 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1036 1.268 skrll
1037 1.125 augustss #ifdef UHCI_DEBUG
1038 1.125 augustss if (uhcinoloop)
1039 1.125 augustss return;
1040 1.125 augustss #endif
1041 1.123 augustss if (++sc->sc_loops == 1) {
1042 1.268 skrll DPRINTFN(5, "add loop", 0, 0, 0, 0);
1043 1.123 augustss /* Note, we don't loop back the soft pointer. */
1044 1.152 augustss sc->sc_last_qh->qh.qh_hlink =
1045 1.123 augustss htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH);
1046 1.223 bouyer usb_syncmem(&sc->sc_last_qh->dma,
1047 1.223 bouyer sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink),
1048 1.223 bouyer sizeof(sc->sc_last_qh->qh.qh_hlink),
1049 1.223 bouyer BUS_DMASYNC_PREWRITE);
1050 1.123 augustss }
1051 1.123 augustss }
1052 1.123 augustss
1053 1.123 augustss void
1054 1.268 skrll uhci_rem_loop(uhci_softc_t *sc)
1055 1.268 skrll {
1056 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1057 1.268 skrll
1058 1.125 augustss #ifdef UHCI_DEBUG
1059 1.125 augustss if (uhcinoloop)
1060 1.125 augustss return;
1061 1.125 augustss #endif
1062 1.123 augustss if (--sc->sc_loops == 0) {
1063 1.268 skrll DPRINTFN(5, "remove loop", 0, 0, 0, 0);
1064 1.123 augustss sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T);
1065 1.223 bouyer usb_syncmem(&sc->sc_last_qh->dma,
1066 1.223 bouyer sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink),
1067 1.223 bouyer sizeof(sc->sc_last_qh->qh.qh_hlink),
1068 1.223 bouyer BUS_DMASYNC_PREWRITE);
1069 1.123 augustss }
1070 1.123 augustss }
1071 1.123 augustss
1072 1.248 mrg /* Add high speed control QH, called with lock held. */
1073 1.123 augustss void
1074 1.123 augustss uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1075 1.1 augustss {
1076 1.42 augustss uhci_soft_qh_t *eqh;
1077 1.1 augustss
1078 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1079 1.268 skrll
1080 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
1081 1.248 mrg
1082 1.268 skrll DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
1083 1.123 augustss eqh = sc->sc_hctl_end;
1084 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1085 1.223 bouyer sizeof(eqh->qh.qh_hlink),
1086 1.223 bouyer BUS_DMASYNC_POSTWRITE);
1087 1.42 augustss sqh->hlink = eqh->hlink;
1088 1.42 augustss sqh->qh.qh_hlink = eqh->qh.qh_hlink;
1089 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1090 1.223 bouyer BUS_DMASYNC_PREWRITE);
1091 1.42 augustss eqh->hlink = sqh;
1092 1.121 augustss eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
1093 1.123 augustss sc->sc_hctl_end = sqh;
1094 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1095 1.223 bouyer sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
1096 1.125 augustss #ifdef UHCI_CTL_LOOP
1097 1.123 augustss uhci_add_loop(sc);
1098 1.125 augustss #endif
1099 1.1 augustss }
1100 1.1 augustss
1101 1.248 mrg /* Remove high speed control QH, called with lock held. */
1102 1.1 augustss void
1103 1.123 augustss uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1104 1.1 augustss {
1105 1.1 augustss uhci_soft_qh_t *pqh;
1106 1.256 tsutsui uint32_t elink;
1107 1.1 augustss
1108 1.272 christos KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1109 1.248 mrg
1110 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1111 1.268 skrll DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
1112 1.125 augustss #ifdef UHCI_CTL_LOOP
1113 1.123 augustss uhci_rem_loop(sc);
1114 1.125 augustss #endif
1115 1.124 augustss /*
1116 1.124 augustss * The T bit should be set in the elink of the QH so that the HC
1117 1.124 augustss * doesn't follow the pointer. This condition may fail if the
1118 1.124 augustss * the transferred packet was short so that the QH still points
1119 1.124 augustss * at the last used TD.
1120 1.124 augustss * In this case we set the T bit and wait a little for the HC
1121 1.124 augustss * to stop looking at the TD.
1122 1.223 bouyer * Note that if the TD chain is large enough, the controller
1123 1.223 bouyer * may still be looking at the chain at the end of this function.
1124 1.223 bouyer * uhci_free_std_chain() will make sure the controller stops
1125 1.223 bouyer * looking at it quickly, but until then we should not change
1126 1.223 bouyer * sqh->hlink.
1127 1.124 augustss */
1128 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
1129 1.223 bouyer sizeof(sqh->qh.qh_elink),
1130 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1131 1.256 tsutsui elink = le32toh(sqh->qh.qh_elink);
1132 1.256 tsutsui usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
1133 1.256 tsutsui sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD);
1134 1.256 tsutsui if (!(elink & UHCI_PTR_T)) {
1135 1.124 augustss sqh->qh.qh_elink = htole32(UHCI_PTR_T);
1136 1.223 bouyer usb_syncmem(&sqh->dma,
1137 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
1138 1.223 bouyer sizeof(sqh->qh.qh_elink),
1139 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1140 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1141 1.124 augustss }
1142 1.124 augustss
1143 1.123 augustss pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh);
1144 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
1145 1.223 bouyer sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
1146 1.152 augustss pqh->hlink = sqh->hlink;
1147 1.42 augustss pqh->qh.qh_hlink = sqh->qh.qh_hlink;
1148 1.223 bouyer usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
1149 1.272 christos sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
1150 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1151 1.123 augustss if (sc->sc_hctl_end == sqh)
1152 1.123 augustss sc->sc_hctl_end = pqh;
1153 1.123 augustss }
1154 1.123 augustss
1155 1.248 mrg /* Add low speed control QH, called with lock held. */
1156 1.123 augustss void
1157 1.123 augustss uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1158 1.123 augustss {
1159 1.123 augustss uhci_soft_qh_t *eqh;
1160 1.123 augustss
1161 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
1162 1.248 mrg
1163 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1164 1.268 skrll DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
1165 1.268 skrll
1166 1.123 augustss eqh = sc->sc_lctl_end;
1167 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1168 1.223 bouyer sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
1169 1.152 augustss sqh->hlink = eqh->hlink;
1170 1.123 augustss sqh->qh.qh_hlink = eqh->qh.qh_hlink;
1171 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1172 1.223 bouyer BUS_DMASYNC_PREWRITE);
1173 1.152 augustss eqh->hlink = sqh;
1174 1.123 augustss eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
1175 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1176 1.223 bouyer sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
1177 1.123 augustss sc->sc_lctl_end = sqh;
1178 1.123 augustss }
1179 1.123 augustss
1180 1.248 mrg /* Remove low speed control QH, called with lock held. */
1181 1.123 augustss void
1182 1.123 augustss uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1183 1.123 augustss {
1184 1.123 augustss uhci_soft_qh_t *pqh;
1185 1.256 tsutsui uint32_t elink;
1186 1.123 augustss
1187 1.272 christos KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1188 1.248 mrg
1189 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1190 1.268 skrll DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
1191 1.268 skrll
1192 1.124 augustss /* See comment in uhci_remove_hs_ctrl() */
1193 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
1194 1.223 bouyer sizeof(sqh->qh.qh_elink),
1195 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1196 1.256 tsutsui elink = le32toh(sqh->qh.qh_elink);
1197 1.256 tsutsui usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
1198 1.256 tsutsui sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD);
1199 1.256 tsutsui if (!(elink & UHCI_PTR_T)) {
1200 1.124 augustss sqh->qh.qh_elink = htole32(UHCI_PTR_T);
1201 1.223 bouyer usb_syncmem(&sqh->dma,
1202 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
1203 1.223 bouyer sizeof(sqh->qh.qh_elink),
1204 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1205 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1206 1.124 augustss }
1207 1.123 augustss pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh);
1208 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
1209 1.223 bouyer sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
1210 1.152 augustss pqh->hlink = sqh->hlink;
1211 1.123 augustss pqh->qh.qh_hlink = sqh->qh.qh_hlink;
1212 1.223 bouyer usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
1213 1.223 bouyer sizeof(pqh->qh.qh_hlink),
1214 1.223 bouyer BUS_DMASYNC_PREWRITE);
1215 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1216 1.123 augustss if (sc->sc_lctl_end == sqh)
1217 1.123 augustss sc->sc_lctl_end = pqh;
1218 1.1 augustss }
1219 1.1 augustss
1220 1.248 mrg /* Add bulk QH, called with lock held. */
1221 1.1 augustss void
1222 1.119 augustss uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1223 1.1 augustss {
1224 1.42 augustss uhci_soft_qh_t *eqh;
1225 1.1 augustss
1226 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
1227 1.248 mrg
1228 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1229 1.268 skrll DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
1230 1.268 skrll
1231 1.42 augustss eqh = sc->sc_bulk_end;
1232 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1233 1.223 bouyer sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
1234 1.152 augustss sqh->hlink = eqh->hlink;
1235 1.42 augustss sqh->qh.qh_hlink = eqh->qh.qh_hlink;
1236 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1237 1.223 bouyer BUS_DMASYNC_PREWRITE);
1238 1.152 augustss eqh->hlink = sqh;
1239 1.121 augustss eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
1240 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1241 1.223 bouyer sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
1242 1.1 augustss sc->sc_bulk_end = sqh;
1243 1.123 augustss uhci_add_loop(sc);
1244 1.1 augustss }
1245 1.1 augustss
1246 1.248 mrg /* Remove bulk QH, called with lock held. */
1247 1.1 augustss void
1248 1.119 augustss uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1249 1.1 augustss {
1250 1.1 augustss uhci_soft_qh_t *pqh;
1251 1.1 augustss
1252 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
1253 1.248 mrg
1254 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1255 1.268 skrll DPRINTFN(10, "sqh %p", sqh, 0, 0, 0);
1256 1.268 skrll
1257 1.123 augustss uhci_rem_loop(sc);
1258 1.124 augustss /* See comment in uhci_remove_hs_ctrl() */
1259 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
1260 1.223 bouyer sizeof(sqh->qh.qh_elink),
1261 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1262 1.124 augustss if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) {
1263 1.124 augustss sqh->qh.qh_elink = htole32(UHCI_PTR_T);
1264 1.223 bouyer usb_syncmem(&sqh->dma,
1265 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
1266 1.223 bouyer sizeof(sqh->qh.qh_elink),
1267 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1268 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1269 1.124 augustss }
1270 1.92 augustss pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh);
1271 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
1272 1.223 bouyer sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
1273 1.42 augustss pqh->hlink = sqh->hlink;
1274 1.42 augustss pqh->qh.qh_hlink = sqh->qh.qh_hlink;
1275 1.223 bouyer usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
1276 1.223 bouyer sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
1277 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
1278 1.1 augustss if (sc->sc_bulk_end == sqh)
1279 1.1 augustss sc->sc_bulk_end = pqh;
1280 1.1 augustss }
1281 1.1 augustss
1282 1.141 augustss Static int uhci_intr1(uhci_softc_t *);
1283 1.141 augustss
1284 1.1 augustss int
1285 1.119 augustss uhci_intr(void *arg)
1286 1.1 augustss {
1287 1.44 augustss uhci_softc_t *sc = arg;
1288 1.248 mrg int ret = 0;
1289 1.248 mrg
1290 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1291 1.268 skrll
1292 1.248 mrg mutex_spin_enter(&sc->sc_intr_lock);
1293 1.146 augustss
1294 1.216 drochner if (sc->sc_dying || !device_has_power(sc->sc_dev))
1295 1.248 mrg goto done;
1296 1.141 augustss
1297 1.268 skrll if (sc->sc_bus.ub_usepolling || UREAD2(sc, UHCI_INTR) == 0) {
1298 1.268 skrll DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0);
1299 1.248 mrg goto done;
1300 1.141 augustss }
1301 1.179 mycroft
1302 1.248 mrg ret = uhci_intr1(sc);
1303 1.248 mrg
1304 1.248 mrg done:
1305 1.248 mrg mutex_spin_exit(&sc->sc_intr_lock);
1306 1.248 mrg return ret;
1307 1.141 augustss }
1308 1.141 augustss
1309 1.141 augustss int
1310 1.141 augustss uhci_intr1(uhci_softc_t *sc)
1311 1.141 augustss {
1312 1.44 augustss int status;
1313 1.44 augustss int ack;
1314 1.1 augustss
1315 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1316 1.268 skrll
1317 1.67 augustss #ifdef UHCI_DEBUG
1318 1.268 skrll if (uhcidebug >= 15) {
1319 1.268 skrll DPRINTF("sc %p", sc, 0, 0, 0);
1320 1.1 augustss uhci_dumpregs(sc);
1321 1.1 augustss }
1322 1.1 augustss #endif
1323 1.117 augustss
1324 1.248 mrg KASSERT(mutex_owned(&sc->sc_intr_lock));
1325 1.248 mrg
1326 1.153 augustss status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS;
1327 1.268 skrll /* Check if the interrupt was for us. */
1328 1.268 skrll if (status == 0)
1329 1.268 skrll return 0;
1330 1.127 soren
1331 1.117 augustss if (sc->sc_suspend != PWR_RESUME) {
1332 1.201 jmcneill #ifdef DIAGNOSTIC
1333 1.117 augustss printf("%s: interrupt while not operating ignored\n",
1334 1.216 drochner device_xname(sc->sc_dev));
1335 1.201 jmcneill #endif
1336 1.134 augustss UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */
1337 1.268 skrll return 0;
1338 1.117 augustss }
1339 1.44 augustss
1340 1.44 augustss ack = 0;
1341 1.44 augustss if (status & UHCI_STS_USBINT)
1342 1.44 augustss ack |= UHCI_STS_USBINT;
1343 1.44 augustss if (status & UHCI_STS_USBEI)
1344 1.44 augustss ack |= UHCI_STS_USBEI;
1345 1.1 augustss if (status & UHCI_STS_RD) {
1346 1.44 augustss ack |= UHCI_STS_RD;
1347 1.118 augustss #ifdef UHCI_DEBUG
1348 1.216 drochner printf("%s: resume detect\n", device_xname(sc->sc_dev));
1349 1.118 augustss #endif
1350 1.1 augustss }
1351 1.1 augustss if (status & UHCI_STS_HSE) {
1352 1.44 augustss ack |= UHCI_STS_HSE;
1353 1.216 drochner printf("%s: host system error\n", device_xname(sc->sc_dev));
1354 1.1 augustss }
1355 1.1 augustss if (status & UHCI_STS_HCPE) {
1356 1.44 augustss ack |= UHCI_STS_HCPE;
1357 1.152 augustss printf("%s: host controller process error\n",
1358 1.216 drochner device_xname(sc->sc_dev));
1359 1.44 augustss }
1360 1.233 msaitoh
1361 1.233 msaitoh /* When HCHalted=1 and Run/Stop=0 , it is normal */
1362 1.233 msaitoh if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) {
1363 1.44 augustss /* no acknowledge needed */
1364 1.136 augustss if (!sc->sc_dying) {
1365 1.152 augustss printf("%s: host controller halted\n",
1366 1.216 drochner device_xname(sc->sc_dev));
1367 1.110 augustss #ifdef UHCI_DEBUG
1368 1.136 augustss uhci_dump_all(sc);
1369 1.110 augustss #endif
1370 1.136 augustss }
1371 1.136 augustss sc->sc_dying = 1;
1372 1.1 augustss }
1373 1.44 augustss
1374 1.132 augustss if (!ack)
1375 1.268 skrll return 0; /* nothing to acknowledge */
1376 1.132 augustss UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */
1377 1.1 augustss
1378 1.85 augustss usb_schedsoftintr(&sc->sc_bus);
1379 1.85 augustss
1380 1.268 skrll DPRINTFN(15, "sc %p done", sc, 0, 0, 0);
1381 1.85 augustss
1382 1.268 skrll return 1;
1383 1.85 augustss }
1384 1.85 augustss
1385 1.85 augustss void
1386 1.133 augustss uhci_softintr(void *v)
1387 1.85 augustss {
1388 1.216 drochner struct usbd_bus *bus = v;
1389 1.268 skrll uhci_softc_t *sc = UHCI_BUS2SC(bus);
1390 1.268 skrll struct uhci_xfer *ux, *nextux;
1391 1.268 skrll ux_completeq_t cq;
1392 1.85 augustss
1393 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1394 1.268 skrll DPRINTF("sc %p", sc, 0, 0, 0);
1395 1.248 mrg
1396 1.268 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1397 1.50 augustss
1398 1.268 skrll TAILQ_INIT(&cq);
1399 1.1 augustss /*
1400 1.1 augustss * Interrupts on UHCI really suck. When the host controller
1401 1.1 augustss * interrupts because a transfer is completed there is no
1402 1.1 augustss * way of knowing which transfer it was. You can scan down
1403 1.1 augustss * the TDs and QHs of the previous frame to limit the search,
1404 1.1 augustss * but that assumes that the interrupt was not delayed by more
1405 1.1 augustss * than 1 ms, which may not always be true (e.g. after debug
1406 1.1 augustss * output on a slow console).
1407 1.1 augustss * We scan all interrupt descriptors to see if any have
1408 1.1 augustss * completed.
1409 1.1 augustss */
1410 1.268 skrll TAILQ_FOREACH_SAFE(ux, &sc->sc_intrhead, ux_list, nextux) {
1411 1.268 skrll uhci_check_intr(sc, ux, &cq);
1412 1.268 skrll }
1413 1.268 skrll
1414 1.268 skrll /*
1415 1.268 skrll * We abuse ux_list for the interrupt and complete lists and
1416 1.268 skrll * interrupt transfers will get re-added here so use
1417 1.268 skrll * the _SAFE version of TAILQ_FOREACH.
1418 1.268 skrll */
1419 1.268 skrll TAILQ_FOREACH_SAFE(ux, &cq, ux_list, nextux) {
1420 1.268 skrll DPRINTF("ux %p", ux, 0, 0, 0);
1421 1.268 skrll usb_transfer_complete(&ux->ux_xfer);
1422 1.178 martin }
1423 1.1 augustss
1424 1.153 augustss if (sc->sc_softwake) {
1425 1.153 augustss sc->sc_softwake = 0;
1426 1.248 mrg cv_broadcast(&sc->sc_softwake_cv);
1427 1.153 augustss }
1428 1.1 augustss }
1429 1.1 augustss
1430 1.1 augustss /* Check for an interrupt. */
1431 1.1 augustss void
1432 1.268 skrll uhci_check_intr(uhci_softc_t *sc, struct uhci_xfer *ux, ux_completeq_t *cqp)
1433 1.1 augustss {
1434 1.268 skrll uhci_soft_td_t *std, *fstd = NULL, *lstd = NULL;
1435 1.268 skrll uint32_t status;
1436 1.1 augustss
1437 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1438 1.268 skrll DPRINTFN(15, "ux %p", ux, 0, 0, 0);
1439 1.268 skrll
1440 1.268 skrll KASSERT(ux != NULL);
1441 1.268 skrll
1442 1.268 skrll struct usbd_xfer *xfer = &ux->ux_xfer;
1443 1.268 skrll if (xfer->ux_status == USBD_CANCELLED ||
1444 1.268 skrll xfer->ux_status == USBD_TIMEOUT) {
1445 1.268 skrll DPRINTF("aborted xfer %p", xfer, 0, 0, 0);
1446 1.1 augustss return;
1447 1.1 augustss }
1448 1.268 skrll
1449 1.268 skrll switch (ux->ux_type) {
1450 1.268 skrll case UX_CTRL:
1451 1.268 skrll fstd = ux->ux_setup;
1452 1.268 skrll lstd = ux->ux_stat;
1453 1.268 skrll break;
1454 1.268 skrll case UX_BULK:
1455 1.268 skrll case UX_INTR:
1456 1.268 skrll case UX_ISOC:
1457 1.268 skrll fstd = ux->ux_stdstart;
1458 1.268 skrll lstd = ux->ux_stdend;
1459 1.268 skrll break;
1460 1.268 skrll default:
1461 1.268 skrll KASSERT(false);
1462 1.268 skrll break;
1463 1.268 skrll }
1464 1.268 skrll if (fstd == NULL)
1465 1.155 augustss return;
1466 1.155 augustss
1467 1.268 skrll KASSERT(lstd != NULL);
1468 1.268 skrll
1469 1.223 bouyer usb_syncmem(&lstd->dma,
1470 1.223 bouyer lstd->offs + offsetof(uhci_td_t, td_status),
1471 1.223 bouyer sizeof(lstd->td.td_status),
1472 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1473 1.256 tsutsui status = le32toh(lstd->td.td_status);
1474 1.256 tsutsui usb_syncmem(&lstd->dma,
1475 1.256 tsutsui lstd->offs + offsetof(uhci_td_t, td_status),
1476 1.256 tsutsui sizeof(lstd->td.td_status),
1477 1.256 tsutsui BUS_DMASYNC_PREREAD);
1478 1.258 skrll
1479 1.258 skrll /* If the last TD is not marked active we can complete */
1480 1.258 skrll if (!(status & UHCI_TD_ACTIVE)) {
1481 1.258 skrll done:
1482 1.268 skrll DPRINTFN(12, "ux=%p done", ux, 0, 0, 0);
1483 1.268 skrll
1484 1.268 skrll callout_stop(&xfer->ux_callout);
1485 1.268 skrll uhci_idone(ux, cqp);
1486 1.258 skrll return;
1487 1.258 skrll }
1488 1.258 skrll
1489 1.258 skrll /*
1490 1.258 skrll * If the last TD is still active we need to check whether there
1491 1.258 skrll * is an error somewhere in the middle, or whether there was a
1492 1.258 skrll * short packet (SPD and not ACTIVE).
1493 1.258 skrll */
1494 1.268 skrll DPRINTFN(12, "active ux=%p", ux, 0, 0, 0);
1495 1.268 skrll for (std = fstd; std != lstd; std = std->link.std) {
1496 1.258 skrll usb_syncmem(&std->dma,
1497 1.258 skrll std->offs + offsetof(uhci_td_t, td_status),
1498 1.258 skrll sizeof(std->td.td_status),
1499 1.258 skrll BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1500 1.258 skrll status = le32toh(std->td.td_status);
1501 1.258 skrll usb_syncmem(&std->dma,
1502 1.258 skrll std->offs + offsetof(uhci_td_t, td_status),
1503 1.258 skrll sizeof(std->td.td_status), BUS_DMASYNC_PREREAD);
1504 1.258 skrll
1505 1.258 skrll /* If there's an active TD the xfer isn't done. */
1506 1.258 skrll if (status & UHCI_TD_ACTIVE) {
1507 1.268 skrll DPRINTFN(12, "ux=%p std=%p still active",
1508 1.268 skrll ux, std, 0, 0);
1509 1.258 skrll return;
1510 1.258 skrll }
1511 1.258 skrll
1512 1.258 skrll /* Any kind of error makes the xfer done. */
1513 1.258 skrll if (status & UHCI_TD_STALLED)
1514 1.258 skrll goto done;
1515 1.258 skrll
1516 1.258 skrll /*
1517 1.258 skrll * If the data phase of a control transfer is short, we need
1518 1.258 skrll * to complete the status stage
1519 1.258 skrll */
1520 1.258 skrll
1521 1.268 skrll if ((status & UHCI_TD_SPD) && ux->ux_type == UX_CTRL) {
1522 1.258 skrll struct uhci_pipe *upipe =
1523 1.268 skrll UHCI_PIPE2UPIPE(xfer->ux_pipe);
1524 1.268 skrll uhci_soft_qh_t *sqh = upipe->ctrl.sqh;
1525 1.268 skrll uhci_soft_td_t *stat = upipe->ctrl.stat;
1526 1.268 skrll
1527 1.268 skrll DPRINTFN(12, "ux=%p std=%p control status"
1528 1.268 skrll "phase needs completion", ux, ux->ux_stdstart, 0, 0);
1529 1.258 skrll
1530 1.258 skrll sqh->qh.qh_elink =
1531 1.258 skrll htole32(stat->physaddr | UHCI_PTR_TD);
1532 1.258 skrll usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1533 1.258 skrll BUS_DMASYNC_PREWRITE);
1534 1.258 skrll break;
1535 1.258 skrll }
1536 1.258 skrll
1537 1.258 skrll /* We want short packets, and it is short: it's done */
1538 1.258 skrll usb_syncmem(&std->dma,
1539 1.258 skrll std->offs + offsetof(uhci_td_t, td_token),
1540 1.258 skrll sizeof(std->td.td_token),
1541 1.258 skrll BUS_DMASYNC_POSTWRITE);
1542 1.258 skrll
1543 1.258 skrll if ((status & UHCI_TD_SPD) &&
1544 1.258 skrll UHCI_TD_GET_ACTLEN(status) <
1545 1.258 skrll UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) {
1546 1.258 skrll goto done;
1547 1.18 augustss }
1548 1.1 augustss }
1549 1.1 augustss }
1550 1.1 augustss
1551 1.248 mrg /* Called with USB lock held. */
1552 1.1 augustss void
1553 1.268 skrll uhci_idone(struct uhci_xfer *ux, ux_completeq_t *cqp)
1554 1.1 augustss {
1555 1.268 skrll struct usbd_xfer *xfer = &ux->ux_xfer;
1556 1.268 skrll uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer);
1557 1.268 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
1558 1.1 augustss uhci_soft_td_t *std;
1559 1.268 skrll uint32_t status = 0, nstatus;
1560 1.26 augustss int actlen;
1561 1.1 augustss
1562 1.268 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1563 1.268 skrll
1564 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1565 1.268 skrll DPRINTFN(12, "ux=%p", ux, 0, 0, 0);
1566 1.248 mrg
1567 1.7 augustss #ifdef DIAGNOSTIC
1568 1.92 augustss #ifdef UHCI_DEBUG
1569 1.268 skrll if (ux->ux_isdone) {
1570 1.268 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
1571 1.268 skrll uhci_dump_ii(ux);
1572 1.268 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
1573 1.268 skrll }
1574 1.92 augustss #endif
1575 1.268 skrll KASSERT(!ux->ux_isdone);
1576 1.268 skrll KASSERTMSG(!ux->ux_isdone, "xfer %p type %d status %d", xfer,
1577 1.268 skrll ux->ux_type, xfer->ux_status);
1578 1.268 skrll ux->ux_isdone = true;
1579 1.7 augustss #endif
1580 1.48 augustss
1581 1.268 skrll if (xfer->ux_nframes != 0) {
1582 1.48 augustss /* Isoc transfer, do things differently. */
1583 1.268 skrll uhci_soft_td_t **stds = upipe->isoc.stds;
1584 1.126 augustss int i, n, nframes, len;
1585 1.48 augustss
1586 1.268 skrll DPRINTFN(5, "ux=%p isoc ready", ux, 0, 0, 0);
1587 1.48 augustss
1588 1.268 skrll nframes = xfer->ux_nframes;
1589 1.48 augustss actlen = 0;
1590 1.268 skrll n = ux->ux_curframe;
1591 1.48 augustss for (i = 0; i < nframes; i++) {
1592 1.48 augustss std = stds[n];
1593 1.59 augustss #ifdef UHCI_DEBUG
1594 1.268 skrll if (uhcidebug >= 5) {
1595 1.268 skrll DPRINTF("isoc TD %d", i, 0, 0, 0);
1596 1.268 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
1597 1.48 augustss uhci_dump_td(std);
1598 1.268 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
1599 1.48 augustss }
1600 1.48 augustss #endif
1601 1.48 augustss if (++n >= UHCI_VFRAMELIST_COUNT)
1602 1.48 augustss n = 0;
1603 1.223 bouyer usb_syncmem(&std->dma,
1604 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
1605 1.223 bouyer sizeof(std->td.td_status),
1606 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1607 1.88 tsutsui status = le32toh(std->td.td_status);
1608 1.126 augustss len = UHCI_TD_GET_ACTLEN(status);
1609 1.268 skrll xfer->ux_frlengths[i] = len;
1610 1.126 augustss actlen += len;
1611 1.48 augustss }
1612 1.268 skrll upipe->isoc.inuse -= nframes;
1613 1.268 skrll xfer->ux_actlen = actlen;
1614 1.268 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1615 1.140 augustss goto end;
1616 1.48 augustss }
1617 1.48 augustss
1618 1.59 augustss #ifdef UHCI_DEBUG
1619 1.268 skrll DPRINTFN(10, "ux=%p, xfer=%p, pipe=%p ready", ux, xfer, upipe, 0);
1620 1.268 skrll if (uhcidebug >= 10) {
1621 1.268 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
1622 1.268 skrll uhci_dump_tds(ux->ux_stdstart);
1623 1.268 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
1624 1.268 skrll }
1625 1.48 augustss #endif
1626 1.48 augustss
1627 1.26 augustss /* The transfer is done, compute actual length and status. */
1628 1.26 augustss actlen = 0;
1629 1.268 skrll for (std = ux->ux_stdstart; std != NULL; std = std->link.std) {
1630 1.223 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
1631 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1632 1.88 tsutsui nstatus = le32toh(std->td.td_status);
1633 1.64 augustss if (nstatus & UHCI_TD_ACTIVE)
1634 1.26 augustss break;
1635 1.67 augustss
1636 1.64 augustss status = nstatus;
1637 1.88 tsutsui if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) !=
1638 1.88 tsutsui UHCI_TD_PID_SETUP)
1639 1.26 augustss actlen += UHCI_TD_GET_ACTLEN(status);
1640 1.176 mycroft else {
1641 1.176 mycroft /*
1642 1.176 mycroft * UHCI will report CRCTO in addition to a STALL or NAK
1643 1.176 mycroft * for a SETUP transaction. See section 3.2.2, "TD
1644 1.176 mycroft * CONTROL AND STATUS".
1645 1.176 mycroft */
1646 1.176 mycroft if (status & (UHCI_TD_STALLED | UHCI_TD_NAK))
1647 1.176 mycroft status &= ~UHCI_TD_CRCTO;
1648 1.176 mycroft }
1649 1.1 augustss }
1650 1.38 augustss /* If there are left over TDs we need to update the toggle. */
1651 1.63 augustss if (std != NULL)
1652 1.88 tsutsui upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token));
1653 1.38 augustss
1654 1.1 augustss status &= UHCI_TD_ERROR;
1655 1.268 skrll DPRINTFN(10, "actlen=%d, status=0x%x", actlen, status, 0, 0);
1656 1.268 skrll xfer->ux_actlen = actlen;
1657 1.1 augustss if (status != 0) {
1658 1.122 tv
1659 1.268 skrll DPRINTFN((status == UHCI_TD_STALLED) * 10,
1660 1.268 skrll "error, addr=%d, endpt=0x%02x",
1661 1.268 skrll xfer->ux_pipe->up_dev->ud_addr,
1662 1.268 skrll xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress,
1663 1.268 skrll 0, 0);
1664 1.268 skrll DPRINTFN((status == UHCI_TD_STALLED) * 10,
1665 1.268 skrll "bitstuff=%d crcto =%d nak =%d babble =%d",
1666 1.268 skrll !!(status & UHCI_TD_BITSTUFF),
1667 1.268 skrll !!(status & UHCI_TD_CRCTO),
1668 1.268 skrll !!(status & UHCI_TD_NAK),
1669 1.268 skrll !!(status & UHCI_TD_BABBLE));
1670 1.268 skrll DPRINTFN((status == UHCI_TD_STALLED) * 10,
1671 1.268 skrll "dbuffer =%d stalled =%d active =%d",
1672 1.268 skrll !!(status & UHCI_TD_DBUFFER),
1673 1.268 skrll !!(status & UHCI_TD_STALLED),
1674 1.268 skrll !!(status & UHCI_TD_ACTIVE),
1675 1.268 skrll 0);
1676 1.122 tv
1677 1.1 augustss if (status == UHCI_TD_STALLED)
1678 1.268 skrll xfer->ux_status = USBD_STALLED;
1679 1.1 augustss else
1680 1.268 skrll xfer->ux_status = USBD_IOERROR; /* more info XXX */
1681 1.1 augustss } else {
1682 1.268 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1683 1.1 augustss }
1684 1.140 augustss
1685 1.140 augustss end:
1686 1.268 skrll uhci_del_intr_list(sc, ux);
1687 1.268 skrll if (cqp)
1688 1.268 skrll TAILQ_INSERT_TAIL(cqp, ux, ux_list);
1689 1.268 skrll
1690 1.268 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1691 1.268 skrll DPRINTFN(12, "ux=%p done", ux, 0, 0, 0);
1692 1.1 augustss }
1693 1.1 augustss
1694 1.13 augustss /*
1695 1.13 augustss * Called when a request does not complete.
1696 1.13 augustss */
1697 1.1 augustss void
1698 1.119 augustss uhci_timeout(void *addr)
1699 1.1 augustss {
1700 1.268 skrll struct usbd_xfer *xfer = addr;
1701 1.268 skrll struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
1702 1.268 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
1703 1.153 augustss
1704 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1705 1.268 skrll
1706 1.268 skrll DPRINTF("uxfer %p", uxfer, 0, 0, 0);
1707 1.153 augustss
1708 1.153 augustss if (sc->sc_dying) {
1709 1.248 mrg mutex_enter(&sc->sc_lock);
1710 1.268 skrll uhci_abort_xfer(xfer, USBD_TIMEOUT);
1711 1.248 mrg mutex_exit(&sc->sc_lock);
1712 1.153 augustss return;
1713 1.153 augustss }
1714 1.1 augustss
1715 1.153 augustss /* Execute the abort in a process context. */
1716 1.268 skrll usb_init_task(&uxfer->ux_aborttask, uhci_timeout_task, xfer,
1717 1.252 jmcneill USB_TASKQ_MPSAFE);
1718 1.268 skrll usb_add_task(uxfer->ux_xfer.ux_pipe->up_dev, &uxfer->ux_aborttask,
1719 1.204 joerg USB_TASKQ_HC);
1720 1.153 augustss }
1721 1.51 augustss
1722 1.153 augustss void
1723 1.153 augustss uhci_timeout_task(void *addr)
1724 1.153 augustss {
1725 1.268 skrll struct usbd_xfer *xfer = addr;
1726 1.268 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
1727 1.268 skrll
1728 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1729 1.153 augustss
1730 1.268 skrll DPRINTF("xfer=%p", xfer, 0, 0, 0);
1731 1.67 augustss
1732 1.248 mrg mutex_enter(&sc->sc_lock);
1733 1.153 augustss uhci_abort_xfer(xfer, USBD_TIMEOUT);
1734 1.248 mrg mutex_exit(&sc->sc_lock);
1735 1.1 augustss }
1736 1.1 augustss
1737 1.8 augustss void
1738 1.119 augustss uhci_poll(struct usbd_bus *bus)
1739 1.8 augustss {
1740 1.268 skrll uhci_softc_t *sc = UHCI_BUS2SC(bus);
1741 1.8 augustss
1742 1.248 mrg if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) {
1743 1.248 mrg mutex_spin_enter(&sc->sc_intr_lock);
1744 1.141 augustss uhci_intr1(sc);
1745 1.248 mrg mutex_spin_exit(&sc->sc_intr_lock);
1746 1.248 mrg }
1747 1.8 augustss }
1748 1.8 augustss
1749 1.1 augustss void
1750 1.119 augustss uhci_reset(uhci_softc_t *sc)
1751 1.1 augustss {
1752 1.1 augustss int n;
1753 1.1 augustss
1754 1.1 augustss UHCICMD(sc, UHCI_CMD_HCRESET);
1755 1.1 augustss /* The reset bit goes low when the controller is done. */
1756 1.152 augustss for (n = 0; n < UHCI_RESET_TIMEOUT &&
1757 1.1 augustss (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++)
1758 1.92 augustss usb_delay_ms(&sc->sc_bus, 1);
1759 1.1 augustss if (n >= UHCI_RESET_TIMEOUT)
1760 1.152 augustss printf("%s: controller did not reset\n",
1761 1.216 drochner device_xname(sc->sc_dev));
1762 1.1 augustss }
1763 1.1 augustss
1764 1.16 augustss usbd_status
1765 1.249 drochner uhci_run(uhci_softc_t *sc, int run, int locked)
1766 1.1 augustss {
1767 1.248 mrg int n, running;
1768 1.268 skrll uint16_t cmd;
1769 1.268 skrll
1770 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1771 1.1 augustss
1772 1.1 augustss run = run != 0;
1773 1.249 drochner if (!locked)
1774 1.249 drochner mutex_spin_enter(&sc->sc_intr_lock);
1775 1.268 skrll
1776 1.268 skrll DPRINTF("setting run=%d", run, 0, 0, 0);
1777 1.71 augustss cmd = UREAD2(sc, UHCI_CMD);
1778 1.71 augustss if (run)
1779 1.71 augustss cmd |= UHCI_CMD_RS;
1780 1.71 augustss else
1781 1.71 augustss cmd &= ~UHCI_CMD_RS;
1782 1.71 augustss UHCICMD(sc, cmd);
1783 1.267 skrll for (n = 0; n < 10; n++) {
1784 1.1 augustss running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH);
1785 1.1 augustss /* return when we've entered the state we want */
1786 1.1 augustss if (run == running) {
1787 1.249 drochner if (!locked)
1788 1.249 drochner mutex_spin_exit(&sc->sc_intr_lock);
1789 1.268 skrll DPRINTF("done cmd=0x%x sts=0x%x",
1790 1.268 skrll UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 0, 0);
1791 1.268 skrll return USBD_NORMAL_COMPLETION;
1792 1.1 augustss }
1793 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock);
1794 1.1 augustss }
1795 1.249 drochner if (!locked)
1796 1.249 drochner mutex_spin_exit(&sc->sc_intr_lock);
1797 1.216 drochner printf("%s: cannot %s\n", device_xname(sc->sc_dev),
1798 1.14 augustss run ? "start" : "stop");
1799 1.268 skrll return USBD_IOERROR;
1800 1.1 augustss }
1801 1.1 augustss
1802 1.1 augustss /*
1803 1.1 augustss * Memory management routines.
1804 1.1 augustss * uhci_alloc_std allocates TDs
1805 1.1 augustss * uhci_alloc_sqh allocates QHs
1806 1.7 augustss * These two routines do their own free list management,
1807 1.1 augustss * partly for speed, partly because allocating DMAable memory
1808 1.268 skrll * has page size granularity so much memory would be wasted if
1809 1.16 augustss * only one TD/QH (32 bytes) was placed in each allocated chunk.
1810 1.1 augustss */
1811 1.1 augustss
1812 1.1 augustss uhci_soft_td_t *
1813 1.119 augustss uhci_alloc_std(uhci_softc_t *sc)
1814 1.1 augustss {
1815 1.1 augustss uhci_soft_td_t *std;
1816 1.63 augustss usbd_status err;
1817 1.42 augustss int i, offs;
1818 1.7 augustss usb_dma_t dma;
1819 1.1 augustss
1820 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1821 1.268 skrll
1822 1.268 skrll mutex_enter(&sc->sc_lock);
1823 1.63 augustss if (sc->sc_freetds == NULL) {
1824 1.268 skrll DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
1825 1.268 skrll mutex_exit(&sc->sc_lock);
1826 1.268 skrll
1827 1.63 augustss err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK,
1828 1.63 augustss UHCI_TD_ALIGN, &dma);
1829 1.63 augustss if (err)
1830 1.268 skrll return NULL;
1831 1.268 skrll
1832 1.268 skrll mutex_enter(&sc->sc_lock);
1833 1.248 mrg for (i = 0; i < UHCI_STD_CHUNK; i++) {
1834 1.42 augustss offs = i * UHCI_STD_SIZE;
1835 1.159 augustss std = KERNADDR(&dma, offs);
1836 1.160 augustss std->physaddr = DMAADDR(&dma, offs);
1837 1.223 bouyer std->dma = dma;
1838 1.223 bouyer std->offs = offs;
1839 1.42 augustss std->link.std = sc->sc_freetds;
1840 1.1 augustss sc->sc_freetds = std;
1841 1.1 augustss }
1842 1.1 augustss }
1843 1.1 augustss std = sc->sc_freetds;
1844 1.42 augustss sc->sc_freetds = std->link.std;
1845 1.268 skrll mutex_exit(&sc->sc_lock);
1846 1.268 skrll
1847 1.42 augustss memset(&std->td, 0, sizeof(uhci_td_t));
1848 1.268 skrll
1849 1.1 augustss return std;
1850 1.1 augustss }
1851 1.1 augustss
1852 1.268 skrll #define TD_IS_FREE 0x12345678
1853 1.268 skrll
1854 1.1 augustss void
1855 1.268 skrll uhci_free_std_locked(uhci_softc_t *sc, uhci_soft_td_t *std)
1856 1.1 augustss {
1857 1.268 skrll KASSERT(mutex_owned(&sc->sc_lock));
1858 1.268 skrll
1859 1.7 augustss #ifdef DIAGNOSTIC
1860 1.88 tsutsui if (le32toh(std->td.td_token) == TD_IS_FREE) {
1861 1.268 skrll printf("%s: freeing free TD %p\n", __func__, std);
1862 1.7 augustss return;
1863 1.7 augustss }
1864 1.88 tsutsui std->td.td_token = htole32(TD_IS_FREE);
1865 1.7 augustss #endif
1866 1.268 skrll
1867 1.42 augustss std->link.std = sc->sc_freetds;
1868 1.1 augustss sc->sc_freetds = std;
1869 1.1 augustss }
1870 1.1 augustss
1871 1.268 skrll void
1872 1.268 skrll uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std)
1873 1.268 skrll {
1874 1.268 skrll mutex_enter(&sc->sc_lock);
1875 1.268 skrll uhci_free_std_locked(sc, std);
1876 1.268 skrll mutex_exit(&sc->sc_lock);
1877 1.268 skrll }
1878 1.268 skrll
1879 1.1 augustss uhci_soft_qh_t *
1880 1.119 augustss uhci_alloc_sqh(uhci_softc_t *sc)
1881 1.1 augustss {
1882 1.1 augustss uhci_soft_qh_t *sqh;
1883 1.63 augustss usbd_status err;
1884 1.1 augustss int i, offs;
1885 1.7 augustss usb_dma_t dma;
1886 1.1 augustss
1887 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1888 1.268 skrll
1889 1.268 skrll mutex_enter(&sc->sc_lock);
1890 1.63 augustss if (sc->sc_freeqhs == NULL) {
1891 1.268 skrll DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
1892 1.268 skrll mutex_exit(&sc->sc_lock);
1893 1.268 skrll
1894 1.63 augustss err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK,
1895 1.63 augustss UHCI_QH_ALIGN, &dma);
1896 1.63 augustss if (err)
1897 1.268 skrll return NULL;
1898 1.268 skrll
1899 1.268 skrll mutex_enter(&sc->sc_lock);
1900 1.267 skrll for (i = 0; i < UHCI_SQH_CHUNK; i++) {
1901 1.42 augustss offs = i * UHCI_SQH_SIZE;
1902 1.159 augustss sqh = KERNADDR(&dma, offs);
1903 1.160 augustss sqh->physaddr = DMAADDR(&dma, offs);
1904 1.223 bouyer sqh->dma = dma;
1905 1.223 bouyer sqh->offs = offs;
1906 1.42 augustss sqh->hlink = sc->sc_freeqhs;
1907 1.1 augustss sc->sc_freeqhs = sqh;
1908 1.1 augustss }
1909 1.1 augustss }
1910 1.1 augustss sqh = sc->sc_freeqhs;
1911 1.42 augustss sc->sc_freeqhs = sqh->hlink;
1912 1.268 skrll mutex_exit(&sc->sc_lock);
1913 1.268 skrll
1914 1.42 augustss memset(&sqh->qh, 0, sizeof(uhci_qh_t));
1915 1.268 skrll
1916 1.268 skrll return sqh;
1917 1.1 augustss }
1918 1.1 augustss
1919 1.1 augustss void
1920 1.119 augustss uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1921 1.1 augustss {
1922 1.268 skrll KASSERT(mutex_owned(&sc->sc_lock));
1923 1.268 skrll
1924 1.42 augustss sqh->hlink = sc->sc_freeqhs;
1925 1.1 augustss sc->sc_freeqhs = sqh;
1926 1.1 augustss }
1927 1.1 augustss
1928 1.268 skrll #if 0
1929 1.1 augustss void
1930 1.119 augustss uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std,
1931 1.119 augustss uhci_soft_td_t *stdend)
1932 1.1 augustss {
1933 1.1 augustss uhci_soft_td_t *p;
1934 1.256 tsutsui uint32_t td_link;
1935 1.1 augustss
1936 1.223 bouyer /*
1937 1.223 bouyer * to avoid race condition with the controller which may be looking
1938 1.223 bouyer * at this chain, we need to first invalidate all links, and
1939 1.223 bouyer * then wait for the controller to move to another queue
1940 1.223 bouyer */
1941 1.223 bouyer for (p = std; p != stdend; p = p->link.std) {
1942 1.223 bouyer usb_syncmem(&p->dma,
1943 1.223 bouyer p->offs + offsetof(uhci_td_t, td_link),
1944 1.223 bouyer sizeof(p->td.td_link),
1945 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1946 1.256 tsutsui td_link = le32toh(p->td.td_link);
1947 1.256 tsutsui usb_syncmem(&p->dma,
1948 1.256 tsutsui p->offs + offsetof(uhci_td_t, td_link),
1949 1.256 tsutsui sizeof(p->td.td_link),
1950 1.256 tsutsui BUS_DMASYNC_PREREAD);
1951 1.256 tsutsui if ((td_link & UHCI_PTR_T) == 0) {
1952 1.255 tsutsui p->td.td_link = htole32(UHCI_PTR_T);
1953 1.223 bouyer usb_syncmem(&p->dma,
1954 1.223 bouyer p->offs + offsetof(uhci_td_t, td_link),
1955 1.223 bouyer sizeof(p->td.td_link),
1956 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1957 1.223 bouyer }
1958 1.223 bouyer }
1959 1.223 bouyer delay(UHCI_QH_REMOVE_DELAY);
1960 1.223 bouyer
1961 1.1 augustss for (; std != stdend; std = p) {
1962 1.42 augustss p = std->link.std;
1963 1.1 augustss uhci_free_std(sc, std);
1964 1.1 augustss }
1965 1.1 augustss }
1966 1.268 skrll #endif
1967 1.268 skrll
1968 1.268 skrll int
1969 1.268 skrll uhci_alloc_std_chain(uhci_softc_t *sc, struct usbd_xfer *xfer, int len,
1970 1.268 skrll int rd, uhci_soft_td_t **sp)
1971 1.268 skrll {
1972 1.268 skrll struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
1973 1.268 skrll uint16_t flags = xfer->ux_flags;
1974 1.268 skrll uhci_soft_td_t *p;
1975 1.268 skrll
1976 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
1977 1.1 augustss
1978 1.268 skrll DPRINTFN(8, "xfer=%p pipe=%p", xfer, xfer->ux_pipe, 0, 0);
1979 1.248 mrg
1980 1.268 skrll ASSERT_SLEEPABLE();
1981 1.268 skrll KASSERT(sp);
1982 1.248 mrg
1983 1.268 skrll int maxp = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize);
1984 1.1 augustss if (maxp == 0) {
1985 1.268 skrll printf("%s: maxp=0\n", __func__);
1986 1.268 skrll return EINVAL;
1987 1.1 augustss }
1988 1.268 skrll size_t ntd = (len + maxp - 1) / maxp;
1989 1.268 skrll if (!rd && (flags & USBD_FORCE_SHORT_XFER)) {
1990 1.73 augustss ntd++;
1991 1.268 skrll }
1992 1.268 skrll DPRINTFN(10, "maxp=%d ntd=%d", maxp, ntd, 0, 0);
1993 1.268 skrll
1994 1.268 skrll uxfer->ux_stds = NULL;
1995 1.268 skrll uxfer->ux_nstd = ntd;
1996 1.268 skrll p = NULL;
1997 1.73 augustss if (ntd == 0) {
1998 1.268 skrll *sp = NULL;
1999 1.268 skrll DPRINTF("ntd=0", 0, 0, 0, 0);
2000 1.268 skrll return 0;
2001 1.73 augustss }
2002 1.268 skrll uxfer->ux_stds = kmem_alloc(sizeof(uhci_soft_td_t *) * ntd,
2003 1.268 skrll KM_SLEEP);
2004 1.268 skrll
2005 1.1 augustss ntd--;
2006 1.268 skrll for (int i = ntd; i >= 0; i--) {
2007 1.1 augustss p = uhci_alloc_std(sc);
2008 1.63 augustss if (p == NULL) {
2009 1.268 skrll uhci_free_stds(sc, uxfer);
2010 1.268 skrll kmem_free(uxfer->ux_stds,
2011 1.268 skrll sizeof(uhci_soft_td_t *) * ntd);
2012 1.268 skrll return ENOMEM;
2013 1.268 skrll }
2014 1.268 skrll uxfer->ux_stds[i] = p;
2015 1.1 augustss }
2016 1.1 augustss
2017 1.268 skrll *sp = uxfer->ux_stds[0];
2018 1.268 skrll
2019 1.268 skrll return 0;
2020 1.38 augustss }
2021 1.38 augustss
2022 1.268 skrll Static void
2023 1.268 skrll uhci_free_stds(uhci_softc_t *sc, struct uhci_xfer *ux)
2024 1.38 augustss {
2025 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2026 1.38 augustss
2027 1.268 skrll DPRINTFN(8, "ux=%p", ux, 0, 0, 0);
2028 1.16 augustss
2029 1.248 mrg mutex_enter(&sc->sc_lock);
2030 1.268 skrll for (size_t i = 0; i < ux->ux_nstd; i++) {
2031 1.268 skrll uhci_soft_td_t *std = ux->ux_stds[i];
2032 1.268 skrll #ifdef DIAGNOSTIC
2033 1.268 skrll if (le32toh(std->td.td_token) == TD_IS_FREE) {
2034 1.268 skrll printf("%s: freeing free TD %p\n", __func__, std);
2035 1.268 skrll return;
2036 1.268 skrll }
2037 1.268 skrll std->td.td_token = htole32(TD_IS_FREE);
2038 1.268 skrll #endif
2039 1.268 skrll ux->ux_stds[i]->link.std = sc->sc_freetds;
2040 1.268 skrll sc->sc_freetds = std;
2041 1.268 skrll }
2042 1.248 mrg mutex_exit(&sc->sc_lock);
2043 1.268 skrll }
2044 1.52 augustss
2045 1.16 augustss
2046 1.268 skrll Static void
2047 1.268 skrll uhci_reset_std_chain(uhci_softc_t *sc, struct usbd_xfer *xfer,
2048 1.268 skrll int length, int isread, int *toggle, uhci_soft_td_t **lstd)
2049 1.16 augustss {
2050 1.268 skrll struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
2051 1.268 skrll struct usbd_pipe *pipe = xfer->ux_pipe;
2052 1.268 skrll usb_dma_t *dma = &xfer->ux_dmabuf;
2053 1.268 skrll uint16_t flags = xfer->ux_flags;
2054 1.268 skrll uhci_soft_td_t *std, *prev;
2055 1.268 skrll int len = length;
2056 1.268 skrll int tog = *toggle;
2057 1.268 skrll int maxp;
2058 1.268 skrll uint32_t status;
2059 1.268 skrll size_t i;
2060 1.268 skrll
2061 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2062 1.268 skrll DPRINTFN(8, "xfer=%p len %d isread %d toggle %d", xfer,
2063 1.268 skrll len, isread, *toggle);
2064 1.1 augustss
2065 1.268 skrll KASSERT(len != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER)));
2066 1.1 augustss
2067 1.268 skrll maxp = UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize);
2068 1.268 skrll KASSERT(maxp != 0);
2069 1.82 augustss
2070 1.268 skrll int addr = xfer->ux_pipe->up_dev->ud_addr;
2071 1.268 skrll int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;
2072 1.1 augustss
2073 1.268 skrll status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE);
2074 1.268 skrll if (pipe->up_dev->ud_speed == USB_SPEED_LOW)
2075 1.268 skrll status |= UHCI_TD_LS;
2076 1.268 skrll if (flags & USBD_SHORT_XFER_OK)
2077 1.268 skrll status |= UHCI_TD_SPD;
2078 1.268 skrll usb_syncmem(dma, 0, len,
2079 1.268 skrll isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
2080 1.268 skrll std = prev = NULL;
2081 1.268 skrll for (i = 0; len != 0 && i < uxfer->ux_nstd; i++, prev = std) {
2082 1.268 skrll int l = len;
2083 1.268 skrll std = uxfer->ux_stds[i];
2084 1.268 skrll if (l > maxp)
2085 1.268 skrll l = maxp;
2086 1.268 skrll
2087 1.268 skrll if (prev) {
2088 1.268 skrll prev->link.std = std;
2089 1.268 skrll prev->td.td_link = htole32(
2090 1.268 skrll std->physaddr | UHCI_PTR_VF | UHCI_PTR_TD
2091 1.268 skrll );
2092 1.268 skrll usb_syncmem(&prev->dma, prev->offs, sizeof(prev->td),
2093 1.268 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2094 1.268 skrll }
2095 1.268 skrll
2096 1.268 skrll usb_syncmem(&std->dma, std->offs, sizeof(std->td),
2097 1.268 skrll BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2098 1.268 skrll
2099 1.268 skrll std->td.td_link = htole32(UHCI_PTR_T | UHCI_PTR_VF | UHCI_PTR_TD);
2100 1.268 skrll std->td.td_status = htole32(status);
2101 1.268 skrll std->td.td_token = htole32(
2102 1.268 skrll UHCI_TD_SET_ENDPT(UE_GET_ADDR(endpt)) |
2103 1.268 skrll UHCI_TD_SET_DEVADDR(addr) |
2104 1.268 skrll UHCI_TD_SET_PID(isread ? UHCI_TD_PID_IN : UHCI_TD_PID_OUT) |
2105 1.268 skrll UHCI_TD_SET_DT(tog) |
2106 1.268 skrll UHCI_TD_SET_MAXLEN(l)
2107 1.268 skrll );
2108 1.268 skrll std->td.td_buffer = htole32(DMAADDR(dma, i * maxp));
2109 1.268 skrll
2110 1.268 skrll std->link.std = NULL;
2111 1.268 skrll
2112 1.268 skrll usb_syncmem(&std->dma, std->offs, sizeof(std->td),
2113 1.268 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2114 1.268 skrll tog ^= 1;
2115 1.268 skrll
2116 1.268 skrll len -= l;
2117 1.268 skrll }
2118 1.268 skrll KASSERTMSG(len == 0, "xfer %p alen %d len %d mps %d ux_nqtd %zu i %zu",
2119 1.268 skrll xfer, length, len, maxp, uxfer->ux_nstd, i);
2120 1.268 skrll
2121 1.268 skrll if (!isread &&
2122 1.268 skrll (flags & USBD_FORCE_SHORT_XFER) &&
2123 1.268 skrll length % maxp == 0) {
2124 1.268 skrll /* Force a 0 length transfer at the end. */
2125 1.268 skrll KASSERTMSG(i < uxfer->ux_nstd, "i=%zu nstd=%zu", i,
2126 1.268 skrll uxfer->ux_nstd);
2127 1.268 skrll std = uxfer->ux_stds[i++];
2128 1.268 skrll
2129 1.268 skrll std->td.td_link = htole32(UHCI_PTR_T | UHCI_PTR_VF | UHCI_PTR_TD);
2130 1.268 skrll std->td.td_status = htole32(status);
2131 1.268 skrll std->td.td_token = htole32(
2132 1.268 skrll UHCI_TD_SET_ENDPT(UE_GET_ADDR(endpt)) |
2133 1.268 skrll UHCI_TD_SET_DEVADDR(addr) |
2134 1.268 skrll UHCI_TD_SET_PID(UHCI_TD_PID_OUT) |
2135 1.268 skrll UHCI_TD_SET_DT(tog) |
2136 1.268 skrll UHCI_TD_SET_MAXLEN(0)
2137 1.268 skrll );
2138 1.268 skrll std->td.td_buffer = 0;
2139 1.268 skrll usb_syncmem(&std->dma, std->offs, sizeof(std->td),
2140 1.268 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2141 1.268 skrll
2142 1.268 skrll std->link.std = NULL;
2143 1.268 skrll if (prev) {
2144 1.268 skrll prev->link.std = std;
2145 1.268 skrll prev->td.td_link = htole32(
2146 1.268 skrll std->physaddr | UHCI_PTR_VF | UHCI_PTR_TD
2147 1.268 skrll );
2148 1.268 skrll usb_syncmem(&prev->dma, prev->offs, sizeof(prev->td),
2149 1.268 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2150 1.268 skrll }
2151 1.268 skrll tog ^= 1;
2152 1.268 skrll }
2153 1.268 skrll *lstd = std;
2154 1.268 skrll *toggle = tog;
2155 1.268 skrll }
2156 1.268 skrll
2157 1.268 skrll void
2158 1.268 skrll uhci_device_clear_toggle(struct usbd_pipe *pipe)
2159 1.268 skrll {
2160 1.268 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
2161 1.268 skrll upipe->nexttoggle = 0;
2162 1.268 skrll }
2163 1.268 skrll
2164 1.268 skrll void
2165 1.268 skrll uhci_noop(struct usbd_pipe *pipe)
2166 1.268 skrll {
2167 1.268 skrll }
2168 1.268 skrll
2169 1.268 skrll int
2170 1.268 skrll uhci_device_bulk_init(struct usbd_xfer *xfer)
2171 1.268 skrll {
2172 1.268 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2173 1.268 skrll struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
2174 1.268 skrll usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc;
2175 1.268 skrll int endpt = ed->bEndpointAddress;
2176 1.268 skrll int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2177 1.268 skrll int len = xfer->ux_bufsize;
2178 1.268 skrll int err = 0;
2179 1.268 skrll
2180 1.268 skrll
2181 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2182 1.268 skrll DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, len, xfer->ux_flags, 0);
2183 1.268 skrll
2184 1.268 skrll if (sc->sc_dying)
2185 1.268 skrll return USBD_IOERROR;
2186 1.268 skrll
2187 1.268 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
2188 1.268 skrll
2189 1.268 skrll uxfer->ux_type = UX_BULK;
2190 1.268 skrll err = uhci_alloc_std_chain(sc, xfer, len, isread, &uxfer->ux_stdstart);
2191 1.268 skrll if (err)
2192 1.268 skrll return err;
2193 1.268 skrll
2194 1.268 skrll #ifdef UHCI_DEBUG
2195 1.268 skrll if (uhcidebug >= 10) {
2196 1.268 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
2197 1.268 skrll uhci_dump_tds(uxfer->ux_stdstart);
2198 1.268 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
2199 1.268 skrll }
2200 1.268 skrll #endif
2201 1.268 skrll
2202 1.268 skrll return 0;
2203 1.268 skrll }
2204 1.268 skrll
2205 1.268 skrll Static void
2206 1.268 skrll uhci_device_bulk_fini(struct usbd_xfer *xfer)
2207 1.268 skrll {
2208 1.268 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2209 1.268 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
2210 1.268 skrll
2211 1.268 skrll KASSERT(ux->ux_type == UX_BULK);
2212 1.268 skrll
2213 1.268 skrll uhci_free_stds(sc, ux);
2214 1.268 skrll if (ux->ux_nstd)
2215 1.268 skrll kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd);
2216 1.268 skrll }
2217 1.268 skrll
2218 1.268 skrll usbd_status
2219 1.268 skrll uhci_device_bulk_transfer(struct usbd_xfer *xfer)
2220 1.268 skrll {
2221 1.268 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2222 1.268 skrll usbd_status err;
2223 1.268 skrll
2224 1.268 skrll /* Insert last in queue. */
2225 1.248 mrg mutex_enter(&sc->sc_lock);
2226 1.268 skrll err = usb_insert_transfer(xfer);
2227 1.268 skrll mutex_exit(&sc->sc_lock);
2228 1.268 skrll if (err)
2229 1.268 skrll return err;
2230 1.268 skrll
2231 1.268 skrll /*
2232 1.268 skrll * Pipe isn't running (otherwise err would be USBD_INPROG),
2233 1.268 skrll * so start it first.
2234 1.268 skrll */
2235 1.268 skrll return uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2236 1.268 skrll }
2237 1.248 mrg
2238 1.268 skrll usbd_status
2239 1.268 skrll uhci_device_bulk_start(struct usbd_xfer *xfer)
2240 1.268 skrll {
2241 1.268 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
2242 1.268 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
2243 1.268 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2244 1.268 skrll uhci_soft_td_t *data, *dataend;
2245 1.268 skrll uhci_soft_qh_t *sqh;
2246 1.268 skrll int len;
2247 1.268 skrll int endpt;
2248 1.268 skrll int isread;
2249 1.268 skrll
2250 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2251 1.268 skrll DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length,
2252 1.268 skrll xfer->ux_flags, 0);
2253 1.268 skrll
2254 1.268 skrll if (sc->sc_dying)
2255 1.268 skrll return USBD_IOERROR;
2256 1.268 skrll
2257 1.268 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
2258 1.268 skrll KASSERT(xfer->ux_length <= xfer->ux_bufsize);
2259 1.268 skrll
2260 1.268 skrll len = xfer->ux_length;
2261 1.268 skrll endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
2262 1.45 augustss isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2263 1.268 skrll sqh = upipe->bulk.sqh;
2264 1.1 augustss
2265 1.268 skrll /* Take lock here to protect nexttoggle */
2266 1.268 skrll mutex_enter(&sc->sc_lock);
2267 1.1 augustss
2268 1.268 skrll uhci_reset_std_chain(sc, xfer, len, isread, &upipe->nexttoggle,
2269 1.268 skrll &dataend);
2270 1.268 skrll
2271 1.268 skrll data = ux->ux_stdstart;
2272 1.268 skrll ux->ux_stdend = dataend;
2273 1.88 tsutsui dataend->td.td_status |= htole32(UHCI_TD_IOC);
2274 1.223 bouyer usb_syncmem(&dataend->dma,
2275 1.223 bouyer dataend->offs + offsetof(uhci_td_t, td_status),
2276 1.223 bouyer sizeof(dataend->td.td_status),
2277 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2278 1.223 bouyer
2279 1.59 augustss #ifdef UHCI_DEBUG
2280 1.268 skrll if (uhcidebug >= 10) {
2281 1.268 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
2282 1.268 skrll DPRINTFN(10, "before transfer", 0, 0, 0, 0);
2283 1.55 augustss uhci_dump_tds(data);
2284 1.268 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
2285 1.1 augustss }
2286 1.1 augustss #endif
2287 1.1 augustss
2288 1.268 skrll KASSERT(ux->ux_isdone);
2289 1.7 augustss #ifdef DIAGNOSTIC
2290 1.268 skrll ux->ux_isdone = false;
2291 1.7 augustss #endif
2292 1.1 augustss
2293 1.55 augustss sqh->elink = data;
2294 1.121 augustss sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD);
2295 1.223 bouyer /* uhci_add_bulk() will do usb_syncmem(sqh) */
2296 1.1 augustss
2297 1.1 augustss uhci_add_bulk(sc, sqh);
2298 1.268 skrll uhci_add_intr_list(sc, ux);
2299 1.1 augustss
2300 1.268 skrll if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
2301 1.268 skrll callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
2302 1.268 skrll uhci_timeout, xfer);
2303 1.13 augustss }
2304 1.268 skrll xfer->ux_status = USBD_IN_PROGRESS;
2305 1.268 skrll mutex_exit(&sc->sc_lock);
2306 1.1 augustss
2307 1.268 skrll return USBD_IN_PROGRESS;
2308 1.1 augustss }
2309 1.1 augustss
2310 1.1 augustss /* Abort a device bulk request. */
2311 1.1 augustss void
2312 1.268 skrll uhci_device_bulk_abort(struct usbd_xfer *xfer)
2313 1.1 augustss {
2314 1.268 skrll uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer);
2315 1.248 mrg
2316 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2317 1.248 mrg
2318 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2319 1.268 skrll
2320 1.66 augustss uhci_abort_xfer(xfer, USBD_CANCELLED);
2321 1.33 augustss }
2322 1.33 augustss
2323 1.92 augustss /*
2324 1.154 augustss * Abort a device request.
2325 1.154 augustss * If this routine is called at splusb() it guarantees that the request
2326 1.154 augustss * will be removed from the hardware scheduling and that the callback
2327 1.154 augustss * for it will be called with USBD_CANCELLED status.
2328 1.154 augustss * It's impossible to guarantee that the requested transfer will not
2329 1.154 augustss * have happened since the hardware runs concurrently.
2330 1.154 augustss * If the transaction has already happened we rely on the ordinary
2331 1.154 augustss * interrupt processing to process it.
2332 1.248 mrg * XXX This is most probably wrong.
2333 1.248 mrg * XXXMRG this doesn't make sense anymore.
2334 1.92 augustss */
2335 1.33 augustss void
2336 1.268 skrll uhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status)
2337 1.33 augustss {
2338 1.268 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
2339 1.268 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
2340 1.268 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2341 1.33 augustss uhci_soft_td_t *std;
2342 1.188 augustss int wake;
2343 1.65 augustss
2344 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2345 1.268 skrll DPRINTFN(1,"xfer=%p, status=%d", xfer, status, 0, 0);
2346 1.33 augustss
2347 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2348 1.268 skrll ASSERT_SLEEPABLE();
2349 1.248 mrg
2350 1.153 augustss if (sc->sc_dying) {
2351 1.153 augustss /* If we're dying, just do the software part. */
2352 1.268 skrll xfer->ux_status = status; /* make software ignore it */
2353 1.268 skrll callout_stop(&xfer->ux_callout);
2354 1.153 augustss usb_transfer_complete(xfer);
2355 1.194 christos return;
2356 1.92 augustss }
2357 1.92 augustss
2358 1.153 augustss /*
2359 1.188 augustss * If an abort is already in progress then just wait for it to
2360 1.188 augustss * complete and return.
2361 1.188 augustss */
2362 1.268 skrll if (xfer->ux_hcflags & UXFER_ABORTING) {
2363 1.268 skrll DPRINTFN(2, "already aborting", 0, 0, 0, 0);
2364 1.188 augustss #ifdef DIAGNOSTIC
2365 1.188 augustss if (status == USBD_TIMEOUT)
2366 1.268 skrll printf("%s: TIMEOUT while aborting\n", __func__);
2367 1.188 augustss #endif
2368 1.188 augustss /* Override the status which might be USBD_TIMEOUT. */
2369 1.268 skrll xfer->ux_status = status;
2370 1.268 skrll DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0);
2371 1.268 skrll xfer->ux_hcflags |= UXFER_ABORTWAIT;
2372 1.268 skrll while (xfer->ux_hcflags & UXFER_ABORTING)
2373 1.268 skrll cv_wait(&xfer->ux_hccv, &sc->sc_lock);
2374 1.248 mrg goto done;
2375 1.188 augustss }
2376 1.268 skrll xfer->ux_hcflags |= UXFER_ABORTING;
2377 1.188 augustss
2378 1.188 augustss /*
2379 1.153 augustss * Step 1: Make interrupt routine and hardware ignore xfer.
2380 1.153 augustss */
2381 1.268 skrll xfer->ux_status = status; /* make software ignore it */
2382 1.268 skrll callout_stop(&xfer->ux_callout);
2383 1.268 skrll uhci_del_intr_list(sc, ux);
2384 1.268 skrll
2385 1.268 skrll DPRINTF("stop ux=%p", ux, 0, 0, 0);
2386 1.268 skrll for (std = ux->ux_stdstart; std != NULL; std = std->link.std) {
2387 1.223 bouyer usb_syncmem(&std->dma,
2388 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
2389 1.223 bouyer sizeof(std->td.td_status),
2390 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2391 1.92 augustss std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC));
2392 1.223 bouyer usb_syncmem(&std->dma,
2393 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
2394 1.223 bouyer sizeof(std->td.td_status),
2395 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2396 1.223 bouyer }
2397 1.92 augustss
2398 1.162 augustss /*
2399 1.153 augustss * Step 2: Wait until we know hardware has finished any possible
2400 1.153 augustss * use of the xfer. Also make sure the soft interrupt routine
2401 1.153 augustss * has run.
2402 1.153 augustss */
2403 1.248 mrg /* Hardware finishes in 1ms */
2404 1.268 skrll usb_delay_ms_locked(upipe->pipe.up_dev->ud_bus, 2, &sc->sc_lock);
2405 1.153 augustss sc->sc_softwake = 1;
2406 1.153 augustss usb_schedsoftintr(&sc->sc_bus);
2407 1.268 skrll DPRINTF("cv_wait", 0, 0, 0, 0);
2408 1.248 mrg cv_wait(&sc->sc_softwake_cv, &sc->sc_lock);
2409 1.162 augustss
2410 1.153 augustss /*
2411 1.153 augustss * Step 3: Execute callback.
2412 1.153 augustss */
2413 1.268 skrll DPRINTF("callback", 0, 0, 0, 0);
2414 1.100 augustss #ifdef DIAGNOSTIC
2415 1.268 skrll ux->ux_isdone = true;
2416 1.100 augustss #endif
2417 1.268 skrll wake = xfer->ux_hcflags & UXFER_ABORTWAIT;
2418 1.268 skrll xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT);
2419 1.106 augustss usb_transfer_complete(xfer);
2420 1.188 augustss if (wake)
2421 1.268 skrll cv_broadcast(&xfer->ux_hccv);
2422 1.248 mrg done:
2423 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2424 1.1 augustss }
2425 1.1 augustss
2426 1.1 augustss /* Close a device bulk pipe. */
2427 1.1 augustss void
2428 1.268 skrll uhci_device_bulk_close(struct usbd_pipe *pipe)
2429 1.1 augustss {
2430 1.268 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
2431 1.268 skrll uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
2432 1.1 augustss
2433 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2434 1.248 mrg
2435 1.268 skrll uhci_free_sqh(sc, upipe->bulk.sqh);
2436 1.236 drochner
2437 1.268 skrll pipe->up_endpoint->ue_toggle = upipe->nexttoggle;
2438 1.268 skrll }
2439 1.268 skrll
2440 1.268 skrll int
2441 1.268 skrll uhci_device_ctrl_init(struct usbd_xfer *xfer)
2442 1.268 skrll {
2443 1.268 skrll struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
2444 1.268 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
2445 1.268 skrll usb_device_request_t *req = &xfer->ux_request;
2446 1.268 skrll struct usbd_device *dev = upipe->pipe.up_dev;
2447 1.268 skrll uhci_softc_t *sc = dev->ud_bus->ub_hcpriv;
2448 1.270 joerg uhci_soft_td_t *data = NULL;
2449 1.268 skrll int len;
2450 1.268 skrll usbd_status err;
2451 1.268 skrll int isread;
2452 1.268 skrll
2453 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2454 1.268 skrll DPRINTFN(3, "xfer=%p len=%d, addr=%d, endpt=%d", xfer, xfer->ux_bufsize,
2455 1.268 skrll dev->ud_addr, upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress);
2456 1.268 skrll
2457 1.268 skrll isread = req->bmRequestType & UT_READ;
2458 1.268 skrll len = xfer->ux_bufsize;
2459 1.268 skrll
2460 1.268 skrll uxfer->ux_type = UX_CTRL;
2461 1.268 skrll /* Set up data transaction */
2462 1.268 skrll if (len != 0) {
2463 1.268 skrll err = uhci_alloc_std_chain(sc, xfer, len, isread, &data);
2464 1.268 skrll if (err)
2465 1.268 skrll return err;
2466 1.268 skrll }
2467 1.268 skrll /* Set up interrupt info. */
2468 1.268 skrll uxfer->ux_setup = upipe->ctrl.setup;
2469 1.268 skrll uxfer->ux_stat = upipe->ctrl.stat;
2470 1.268 skrll uxfer->ux_data = data;
2471 1.268 skrll
2472 1.268 skrll return 0;
2473 1.268 skrll }
2474 1.268 skrll
2475 1.268 skrll Static void
2476 1.268 skrll uhci_device_ctrl_fini(struct usbd_xfer *xfer)
2477 1.268 skrll {
2478 1.268 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2479 1.268 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
2480 1.268 skrll
2481 1.268 skrll KASSERT(ux->ux_type == UX_CTRL);
2482 1.268 skrll
2483 1.268 skrll uhci_free_stds(sc, ux);
2484 1.268 skrll if (ux->ux_nstd)
2485 1.268 skrll kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd);
2486 1.1 augustss }
2487 1.1 augustss
2488 1.1 augustss usbd_status
2489 1.268 skrll uhci_device_ctrl_transfer(struct usbd_xfer *xfer)
2490 1.1 augustss {
2491 1.268 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2492 1.63 augustss usbd_status err;
2493 1.16 augustss
2494 1.52 augustss /* Insert last in queue. */
2495 1.248 mrg mutex_enter(&sc->sc_lock);
2496 1.63 augustss err = usb_insert_transfer(xfer);
2497 1.248 mrg mutex_exit(&sc->sc_lock);
2498 1.63 augustss if (err)
2499 1.268 skrll return err;
2500 1.52 augustss
2501 1.152 augustss /*
2502 1.92 augustss * Pipe isn't running (otherwise err would be USBD_INPROG),
2503 1.92 augustss * so start it first.
2504 1.67 augustss */
2505 1.268 skrll return uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2506 1.16 augustss }
2507 1.16 augustss
2508 1.16 augustss usbd_status
2509 1.268 skrll uhci_device_ctrl_start(struct usbd_xfer *xfer)
2510 1.16 augustss {
2511 1.268 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2512 1.268 skrll struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
2513 1.268 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
2514 1.268 skrll usb_device_request_t *req = &xfer->ux_request;
2515 1.268 skrll struct usbd_device *dev = upipe->pipe.up_dev;
2516 1.268 skrll int addr = dev->ud_addr;
2517 1.268 skrll int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
2518 1.268 skrll uhci_soft_td_t *setup, *stat, *next, *dataend;
2519 1.268 skrll uhci_soft_qh_t *sqh;
2520 1.268 skrll int len;
2521 1.268 skrll int isread;
2522 1.268 skrll
2523 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2524 1.1 augustss
2525 1.82 augustss if (sc->sc_dying)
2526 1.268 skrll return USBD_IOERROR;
2527 1.268 skrll
2528 1.268 skrll KASSERT(xfer->ux_rqflags & URQ_REQUEST);
2529 1.268 skrll
2530 1.268 skrll DPRINTFN(3, "type=0x%02x, request=0x%02x, "
2531 1.268 skrll "wValue=0x%04x, wIndex=0x%04x",
2532 1.268 skrll req->bmRequestType, req->bRequest, UGETW(req->wValue),
2533 1.268 skrll UGETW(req->wIndex));
2534 1.268 skrll DPRINTFN(3, "len=%d, addr=%d, endpt=%d",
2535 1.268 skrll UGETW(req->wLength), dev->ud_addr, endpt, 0);
2536 1.268 skrll
2537 1.268 skrll isread = req->bmRequestType & UT_READ;
2538 1.268 skrll len = UGETW(req->wLength);
2539 1.268 skrll
2540 1.268 skrll setup = upipe->ctrl.setup;
2541 1.268 skrll stat = upipe->ctrl.stat;
2542 1.268 skrll sqh = upipe->ctrl.sqh;
2543 1.268 skrll
2544 1.268 skrll memcpy(KERNADDR(&upipe->ctrl.reqdma, 0), req, sizeof(*req));
2545 1.268 skrll usb_syncmem(&upipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE);
2546 1.268 skrll
2547 1.268 skrll mutex_enter(&sc->sc_lock);
2548 1.268 skrll
2549 1.268 skrll /* Set up data transaction */
2550 1.268 skrll if (len != 0) {
2551 1.268 skrll upipe->nexttoggle = 1;
2552 1.268 skrll next = uxfer->ux_data;
2553 1.268 skrll uhci_reset_std_chain(sc, xfer, len, isread,
2554 1.268 skrll &upipe->nexttoggle, &dataend);
2555 1.268 skrll dataend->link.std = stat;
2556 1.268 skrll dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD);
2557 1.268 skrll usb_syncmem(&dataend->dma,
2558 1.268 skrll dataend->offs + offsetof(uhci_td_t, td_link),
2559 1.268 skrll sizeof(dataend->td.td_link),
2560 1.268 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2561 1.268 skrll } else {
2562 1.268 skrll next = stat;
2563 1.268 skrll }
2564 1.82 augustss
2565 1.268 skrll const uint32_t status = UHCI_TD_ZERO_ACTLEN(
2566 1.268 skrll UHCI_TD_SET_ERRCNT(3) |
2567 1.268 skrll UHCI_TD_ACTIVE |
2568 1.268 skrll (dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0)
2569 1.268 skrll );
2570 1.268 skrll setup->link.std = next;
2571 1.268 skrll setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD);
2572 1.268 skrll setup->td.td_status = htole32(status);
2573 1.268 skrll setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof(*req), endpt, addr));
2574 1.268 skrll setup->td.td_buffer = htole32(DMAADDR(&upipe->ctrl.reqdma, 0));
2575 1.268 skrll
2576 1.268 skrll usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td),
2577 1.268 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2578 1.268 skrll
2579 1.268 skrll stat->link.std = NULL;
2580 1.268 skrll stat->td.td_link = htole32(UHCI_PTR_T);
2581 1.268 skrll stat->td.td_status = htole32(status | UHCI_TD_IOC);
2582 1.268 skrll stat->td.td_token =
2583 1.268 skrll htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) :
2584 1.268 skrll UHCI_TD_IN (0, endpt, addr, 1));
2585 1.268 skrll stat->td.td_buffer = htole32(0);
2586 1.268 skrll usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td),
2587 1.268 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2588 1.268 skrll
2589 1.268 skrll #ifdef UHCI_DEBUG
2590 1.268 skrll if (uhcidebug >= 10) {
2591 1.268 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
2592 1.268 skrll DPRINTF("before transfer", 0, 0, 0, 0);
2593 1.268 skrll uhci_dump_tds(setup);
2594 1.268 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
2595 1.268 skrll }
2596 1.268 skrll #endif
2597 1.268 skrll
2598 1.268 skrll /* Set up interrupt info. */
2599 1.268 skrll uxfer->ux_setup = setup;
2600 1.268 skrll uxfer->ux_stat = stat;
2601 1.268 skrll KASSERT(uxfer->ux_isdone);
2602 1.48 augustss #ifdef DIAGNOSTIC
2603 1.268 skrll uxfer->ux_isdone = false;
2604 1.48 augustss #endif
2605 1.1 augustss
2606 1.268 skrll sqh->elink = setup;
2607 1.268 skrll sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD);
2608 1.268 skrll /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */
2609 1.268 skrll
2610 1.268 skrll if (dev->ud_speed == USB_SPEED_LOW)
2611 1.268 skrll uhci_add_ls_ctrl(sc, sqh);
2612 1.268 skrll else
2613 1.268 skrll uhci_add_hs_ctrl(sc, sqh);
2614 1.268 skrll uhci_add_intr_list(sc, uxfer);
2615 1.268 skrll #ifdef UHCI_DEBUG
2616 1.268 skrll if (uhcidebug >= 12) {
2617 1.268 skrll uhci_soft_td_t *std;
2618 1.268 skrll uhci_soft_qh_t *xqh;
2619 1.268 skrll uhci_soft_qh_t *sxqh;
2620 1.268 skrll int maxqh = 0;
2621 1.268 skrll uhci_physaddr_t link;
2622 1.268 skrll DPRINTFN(12, "--- dump start ---", 0, 0, 0, 0);
2623 1.268 skrll DPRINTFN(12, "follow from [0]", 0, 0, 0, 0);
2624 1.268 skrll for (std = sc->sc_vframes[0].htd, link = 0;
2625 1.268 skrll (link & UHCI_PTR_QH) == 0;
2626 1.268 skrll std = std->link.std) {
2627 1.268 skrll link = le32toh(std->td.td_link);
2628 1.268 skrll uhci_dump_td(std);
2629 1.268 skrll }
2630 1.268 skrll sxqh = (uhci_soft_qh_t *)std;
2631 1.268 skrll uhci_dump_qh(sxqh);
2632 1.268 skrll for (xqh = sxqh;
2633 1.268 skrll xqh != NULL;
2634 1.268 skrll xqh = (maxqh++ == 5 || xqh->hlink == sxqh ||
2635 1.268 skrll xqh->hlink == xqh ? NULL : xqh->hlink)) {
2636 1.268 skrll uhci_dump_qh(xqh);
2637 1.268 skrll }
2638 1.268 skrll DPRINTFN(12, "Enqueued QH:", 0, 0, 0, 0);
2639 1.268 skrll uhci_dump_qh(sqh);
2640 1.268 skrll uhci_dump_tds(sqh->elink);
2641 1.268 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
2642 1.268 skrll }
2643 1.268 skrll #endif
2644 1.268 skrll if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
2645 1.268 skrll callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
2646 1.268 skrll uhci_timeout, xfer);
2647 1.268 skrll }
2648 1.268 skrll xfer->ux_status = USBD_IN_PROGRESS;
2649 1.248 mrg mutex_exit(&sc->sc_lock);
2650 1.1 augustss
2651 1.268 skrll return USBD_IN_PROGRESS;
2652 1.268 skrll }
2653 1.268 skrll
2654 1.268 skrll int
2655 1.268 skrll uhci_device_intr_init(struct usbd_xfer *xfer)
2656 1.268 skrll {
2657 1.268 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2658 1.268 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
2659 1.268 skrll usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc;
2660 1.268 skrll int endpt = ed->bEndpointAddress;
2661 1.268 skrll int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2662 1.268 skrll int len = xfer->ux_bufsize;
2663 1.268 skrll int err;
2664 1.268 skrll
2665 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2666 1.268 skrll
2667 1.268 skrll DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length,
2668 1.268 skrll xfer->ux_flags, 0);
2669 1.268 skrll
2670 1.268 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
2671 1.268 skrll KASSERT(len != 0);
2672 1.268 skrll
2673 1.268 skrll ux->ux_type = UX_INTR;
2674 1.268 skrll ux->ux_nstd = 0;
2675 1.268 skrll err = uhci_alloc_std_chain(sc, xfer, len, isread, &ux->ux_stdstart);
2676 1.268 skrll
2677 1.268 skrll return err;
2678 1.268 skrll }
2679 1.268 skrll
2680 1.268 skrll Static void
2681 1.268 skrll uhci_device_intr_fini(struct usbd_xfer *xfer)
2682 1.268 skrll {
2683 1.268 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2684 1.268 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
2685 1.268 skrll
2686 1.268 skrll KASSERT(ux->ux_type == UX_INTR);
2687 1.268 skrll
2688 1.268 skrll uhci_free_stds(sc, ux);
2689 1.268 skrll if (ux->ux_nstd)
2690 1.268 skrll kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd);
2691 1.1 augustss }
2692 1.1 augustss
2693 1.1 augustss usbd_status
2694 1.268 skrll uhci_device_intr_transfer(struct usbd_xfer *xfer)
2695 1.1 augustss {
2696 1.268 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2697 1.63 augustss usbd_status err;
2698 1.16 augustss
2699 1.52 augustss /* Insert last in queue. */
2700 1.248 mrg mutex_enter(&sc->sc_lock);
2701 1.63 augustss err = usb_insert_transfer(xfer);
2702 1.248 mrg mutex_exit(&sc->sc_lock);
2703 1.63 augustss if (err)
2704 1.268 skrll return err;
2705 1.52 augustss
2706 1.152 augustss /*
2707 1.92 augustss * Pipe isn't running (otherwise err would be USBD_INPROG),
2708 1.92 augustss * so start it first.
2709 1.67 augustss */
2710 1.268 skrll return uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2711 1.16 augustss }
2712 1.16 augustss
2713 1.16 augustss usbd_status
2714 1.268 skrll uhci_device_intr_start(struct usbd_xfer *xfer)
2715 1.16 augustss {
2716 1.268 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
2717 1.268 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
2718 1.268 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2719 1.55 augustss uhci_soft_td_t *data, *dataend;
2720 1.1 augustss uhci_soft_qh_t *sqh;
2721 1.187 skrll int isread, endpt;
2722 1.248 mrg int i;
2723 1.1 augustss
2724 1.82 augustss if (sc->sc_dying)
2725 1.268 skrll return USBD_IOERROR;
2726 1.82 augustss
2727 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2728 1.1 augustss
2729 1.268 skrll DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length,
2730 1.268 skrll xfer->ux_flags, 0);
2731 1.1 augustss
2732 1.268 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
2733 1.268 skrll KASSERT(xfer->ux_length <= xfer->ux_bufsize);
2734 1.248 mrg
2735 1.268 skrll endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
2736 1.187 skrll isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2737 1.187 skrll
2738 1.268 skrll data = ux->ux_stdstart;
2739 1.268 skrll
2740 1.268 skrll KASSERT(ux->ux_isdone);
2741 1.268 skrll #ifdef DIAGNOSTIC
2742 1.268 skrll ux->ux_isdone = false;
2743 1.268 skrll #endif
2744 1.187 skrll
2745 1.268 skrll /* Take lock to protect nexttoggle */
2746 1.268 skrll mutex_enter(&sc->sc_lock);
2747 1.268 skrll uhci_reset_std_chain(sc, xfer, xfer->ux_length, isread,
2748 1.268 skrll &upipe->nexttoggle, &dataend);
2749 1.248 mrg
2750 1.88 tsutsui dataend->td.td_status |= htole32(UHCI_TD_IOC);
2751 1.223 bouyer usb_syncmem(&dataend->dma,
2752 1.223 bouyer dataend->offs + offsetof(uhci_td_t, td_status),
2753 1.223 bouyer sizeof(dataend->td.td_status),
2754 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2755 1.268 skrll ux->ux_stdend = dataend;
2756 1.1 augustss
2757 1.59 augustss #ifdef UHCI_DEBUG
2758 1.268 skrll if (uhcidebug >= 10) {
2759 1.268 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
2760 1.55 augustss uhci_dump_tds(data);
2761 1.268 skrll uhci_dump_qh(upipe->intr.qhs[0]);
2762 1.268 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
2763 1.1 augustss }
2764 1.1 augustss #endif
2765 1.1 augustss
2766 1.268 skrll DPRINTFN(10, "qhs[0]=%p", upipe->intr.qhs[0], 0, 0, 0);
2767 1.268 skrll for (i = 0; i < upipe->intr.npoll; i++) {
2768 1.268 skrll sqh = upipe->intr.qhs[i];
2769 1.55 augustss sqh->elink = data;
2770 1.121 augustss sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD);
2771 1.223 bouyer usb_syncmem(&sqh->dma,
2772 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
2773 1.223 bouyer sizeof(sqh->qh.qh_elink),
2774 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2775 1.1 augustss }
2776 1.268 skrll uhci_add_intr_list(sc, ux);
2777 1.268 skrll xfer->ux_status = USBD_IN_PROGRESS;
2778 1.248 mrg mutex_exit(&sc->sc_lock);
2779 1.1 augustss
2780 1.59 augustss #ifdef UHCI_DEBUG
2781 1.268 skrll if (uhcidebug >= 10) {
2782 1.268 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
2783 1.55 augustss uhci_dump_tds(data);
2784 1.268 skrll uhci_dump_qh(upipe->intr.qhs[0]);
2785 1.268 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
2786 1.1 augustss }
2787 1.1 augustss #endif
2788 1.1 augustss
2789 1.268 skrll return USBD_IN_PROGRESS;
2790 1.1 augustss }
2791 1.1 augustss
2792 1.1 augustss /* Abort a device control request. */
2793 1.1 augustss void
2794 1.268 skrll uhci_device_ctrl_abort(struct usbd_xfer *xfer)
2795 1.1 augustss {
2796 1.268 skrll uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer);
2797 1.248 mrg
2798 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2799 1.248 mrg
2800 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2801 1.66 augustss uhci_abort_xfer(xfer, USBD_CANCELLED);
2802 1.1 augustss }
2803 1.1 augustss
2804 1.1 augustss /* Close a device control pipe. */
2805 1.1 augustss void
2806 1.268 skrll uhci_device_ctrl_close(struct usbd_pipe *pipe)
2807 1.1 augustss {
2808 1.268 skrll uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
2809 1.268 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
2810 1.268 skrll
2811 1.268 skrll uhci_free_sqh(sc, upipe->ctrl.sqh);
2812 1.268 skrll uhci_free_std_locked(sc, upipe->ctrl.setup);
2813 1.268 skrll uhci_free_std_locked(sc, upipe->ctrl.stat);
2814 1.268 skrll
2815 1.1 augustss }
2816 1.1 augustss
2817 1.1 augustss /* Abort a device interrupt request. */
2818 1.1 augustss void
2819 1.268 skrll uhci_device_intr_abort(struct usbd_xfer *xfer)
2820 1.1 augustss {
2821 1.268 skrll uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer);
2822 1.248 mrg
2823 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2824 1.268 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
2825 1.248 mrg
2826 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2827 1.268 skrll DPRINTF("xfer=%p", xfer, 0, 0, 0);
2828 1.264 skrll
2829 1.66 augustss uhci_abort_xfer(xfer, USBD_CANCELLED);
2830 1.1 augustss }
2831 1.1 augustss
2832 1.1 augustss /* Close a device interrupt pipe. */
2833 1.1 augustss void
2834 1.268 skrll uhci_device_intr_close(struct usbd_pipe *pipe)
2835 1.1 augustss {
2836 1.268 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
2837 1.268 skrll uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
2838 1.92 augustss int i, npoll;
2839 1.248 mrg
2840 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2841 1.1 augustss
2842 1.1 augustss /* Unlink descriptors from controller data structures. */
2843 1.268 skrll npoll = upipe->intr.npoll;
2844 1.1 augustss for (i = 0; i < npoll; i++)
2845 1.268 skrll uhci_remove_intr(sc, upipe->intr.qhs[i]);
2846 1.1 augustss
2847 1.152 augustss /*
2848 1.1 augustss * We now have to wait for any activity on the physical
2849 1.1 augustss * descriptors to stop.
2850 1.1 augustss */
2851 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock);
2852 1.1 augustss
2853 1.267 skrll for (i = 0; i < npoll; i++)
2854 1.268 skrll uhci_free_sqh(sc, upipe->intr.qhs[i]);
2855 1.268 skrll kmem_free(upipe->intr.qhs, npoll * sizeof(uhci_soft_qh_t *));
2856 1.1 augustss }
2857 1.1 augustss
2858 1.268 skrll int
2859 1.268 skrll uhci_device_isoc_init(struct usbd_xfer *xfer)
2860 1.1 augustss {
2861 1.268 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
2862 1.248 mrg
2863 1.268 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
2864 1.268 skrll KASSERT(xfer->ux_nframes != 0);
2865 1.268 skrll KASSERT(ux->ux_isdone);
2866 1.1 augustss
2867 1.268 skrll ux->ux_type = UX_ISOC;
2868 1.268 skrll return 0;
2869 1.268 skrll }
2870 1.1 augustss
2871 1.268 skrll Static void
2872 1.268 skrll uhci_device_isoc_fini(struct usbd_xfer *xfer)
2873 1.268 skrll {
2874 1.269 skrll struct uhci_xfer *ux __diagused = UHCI_XFER2UXFER(xfer);
2875 1.1 augustss
2876 1.268 skrll KASSERT(ux->ux_type == UX_ISOC);
2877 1.1 augustss }
2878 1.1 augustss
2879 1.16 augustss usbd_status
2880 1.268 skrll uhci_device_isoc_transfer(struct usbd_xfer *xfer)
2881 1.16 augustss {
2882 1.268 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2883 1.268 skrll usbd_status err __diagused;
2884 1.48 augustss
2885 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
2886 1.268 skrll DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0);
2887 1.48 augustss
2888 1.48 augustss /* Put it on our queue, */
2889 1.248 mrg mutex_enter(&sc->sc_lock);
2890 1.63 augustss err = usb_insert_transfer(xfer);
2891 1.248 mrg mutex_exit(&sc->sc_lock);
2892 1.48 augustss
2893 1.268 skrll KASSERT(err == USBD_NORMAL_COMPLETION);
2894 1.48 augustss
2895 1.48 augustss /* insert into schedule, */
2896 1.48 augustss
2897 1.268 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
2898 1.268 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
2899 1.268 skrll struct isoc *isoc = &upipe->isoc;
2900 1.268 skrll uhci_soft_td_t *std = NULL;
2901 1.268 skrll uint32_t buf, len, status, offs;
2902 1.248 mrg int i, next, nframes;
2903 1.268 skrll int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN;
2904 1.48 augustss
2905 1.268 skrll DPRINTFN(5, "used=%d next=%d xfer=%p nframes=%d",
2906 1.268 skrll isoc->inuse, isoc->next, xfer, xfer->ux_nframes);
2907 1.48 augustss
2908 1.82 augustss if (sc->sc_dying)
2909 1.268 skrll return USBD_IOERROR;
2910 1.82 augustss
2911 1.268 skrll if (xfer->ux_status == USBD_IN_PROGRESS) {
2912 1.48 augustss /* This request has already been entered into the frame list */
2913 1.268 skrll printf("%s: xfer=%p in frame list\n", __func__, xfer);
2914 1.68 augustss /* XXX */
2915 1.48 augustss }
2916 1.48 augustss
2917 1.48 augustss #ifdef DIAGNOSTIC
2918 1.268 skrll if (isoc->inuse >= UHCI_VFRAMELIST_COUNT)
2919 1.268 skrll printf("%s: overflow!\n", __func__);
2920 1.19 augustss #endif
2921 1.16 augustss
2922 1.268 skrll KASSERT(xfer->ux_nframes != 0);
2923 1.268 skrll
2924 1.268 skrll mutex_enter(&sc->sc_lock);
2925 1.268 skrll next = isoc->next;
2926 1.48 augustss if (next == -1) {
2927 1.48 augustss /* Not in use yet, schedule it a few frames ahead. */
2928 1.48 augustss next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT;
2929 1.268 skrll DPRINTFN(2, "start next=%d", next, 0, 0, 0);
2930 1.48 augustss }
2931 1.48 augustss
2932 1.268 skrll xfer->ux_status = USBD_IN_PROGRESS;
2933 1.268 skrll ux->ux_curframe = next;
2934 1.48 augustss
2935 1.268 skrll buf = DMAADDR(&xfer->ux_dmabuf, 0);
2936 1.223 bouyer offs = 0;
2937 1.88 tsutsui status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) |
2938 1.88 tsutsui UHCI_TD_ACTIVE |
2939 1.88 tsutsui UHCI_TD_IOS);
2940 1.268 skrll nframes = xfer->ux_nframes;
2941 1.48 augustss for (i = 0; i < nframes; i++) {
2942 1.268 skrll std = isoc->stds[next];
2943 1.48 augustss if (++next >= UHCI_VFRAMELIST_COUNT)
2944 1.48 augustss next = 0;
2945 1.268 skrll len = xfer->ux_frlengths[i];
2946 1.88 tsutsui std->td.td_buffer = htole32(buf);
2947 1.268 skrll usb_syncmem(&xfer->ux_dmabuf, offs, len,
2948 1.223 bouyer rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
2949 1.48 augustss if (i == nframes - 1)
2950 1.88 tsutsui status |= UHCI_TD_IOC;
2951 1.88 tsutsui std->td.td_status = htole32(status);
2952 1.88 tsutsui std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK);
2953 1.88 tsutsui std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len));
2954 1.223 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
2955 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2956 1.59 augustss #ifdef UHCI_DEBUG
2957 1.268 skrll if (uhcidebug >= 5) {
2958 1.268 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
2959 1.268 skrll DPRINTF("TD %d", i, 0, 0, 0);
2960 1.48 augustss uhci_dump_td(std);
2961 1.268 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
2962 1.48 augustss }
2963 1.48 augustss #endif
2964 1.48 augustss buf += len;
2965 1.223 bouyer offs += len;
2966 1.48 augustss }
2967 1.268 skrll isoc->next = next;
2968 1.268 skrll isoc->inuse += xfer->ux_nframes;
2969 1.16 augustss
2970 1.268 skrll /* Set up interrupt info. */
2971 1.268 skrll ux->ux_stdstart = std;
2972 1.268 skrll ux->ux_stdend = std;
2973 1.96 augustss
2974 1.268 skrll KASSERT(ux->ux_isdone);
2975 1.48 augustss #ifdef DIAGNOSTIC
2976 1.268 skrll ux->ux_isdone = false;
2977 1.48 augustss #endif
2978 1.268 skrll uhci_add_intr_list(sc, ux);
2979 1.152 augustss
2980 1.248 mrg mutex_exit(&sc->sc_lock);
2981 1.48 augustss
2982 1.268 skrll return USBD_IN_PROGRESS;
2983 1.16 augustss }
2984 1.16 augustss
2985 1.16 augustss void
2986 1.268 skrll uhci_device_isoc_abort(struct usbd_xfer *xfer)
2987 1.16 augustss {
2988 1.268 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
2989 1.268 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
2990 1.268 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
2991 1.268 skrll uhci_soft_td_t **stds = upipe->isoc.stds;
2992 1.48 augustss uhci_soft_td_t *std;
2993 1.248 mrg int i, n, nframes, maxlen, len;
2994 1.92 augustss
2995 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
2996 1.92 augustss
2997 1.92 augustss /* Transfer is already done. */
2998 1.268 skrll if (xfer->ux_status != USBD_NOT_STARTED &&
2999 1.268 skrll xfer->ux_status != USBD_IN_PROGRESS) {
3000 1.92 augustss return;
3001 1.92 augustss }
3002 1.48 augustss
3003 1.92 augustss /* Give xfer the requested abort code. */
3004 1.268 skrll xfer->ux_status = USBD_CANCELLED;
3005 1.48 augustss
3006 1.48 augustss /* make hardware ignore it, */
3007 1.268 skrll nframes = xfer->ux_nframes;
3008 1.268 skrll n = ux->ux_curframe;
3009 1.92 augustss maxlen = 0;
3010 1.48 augustss for (i = 0; i < nframes; i++) {
3011 1.48 augustss std = stds[n];
3012 1.223 bouyer usb_syncmem(&std->dma,
3013 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
3014 1.223 bouyer sizeof(std->td.td_status),
3015 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3016 1.88 tsutsui std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC));
3017 1.223 bouyer usb_syncmem(&std->dma,
3018 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
3019 1.223 bouyer sizeof(std->td.td_status),
3020 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3021 1.223 bouyer usb_syncmem(&std->dma,
3022 1.223 bouyer std->offs + offsetof(uhci_td_t, td_token),
3023 1.223 bouyer sizeof(std->td.td_token),
3024 1.223 bouyer BUS_DMASYNC_POSTWRITE);
3025 1.130 tsutsui len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token));
3026 1.92 augustss if (len > maxlen)
3027 1.92 augustss maxlen = len;
3028 1.48 augustss if (++n >= UHCI_VFRAMELIST_COUNT)
3029 1.48 augustss n = 0;
3030 1.48 augustss }
3031 1.48 augustss
3032 1.92 augustss /* and wait until we are sure the hardware has finished. */
3033 1.92 augustss delay(maxlen);
3034 1.92 augustss
3035 1.96 augustss #ifdef DIAGNOSTIC
3036 1.268 skrll ux->ux_isdone = true;
3037 1.96 augustss #endif
3038 1.268 skrll /* Remove from interrupt list. */
3039 1.268 skrll uhci_del_intr_list(sc, ux);
3040 1.268 skrll
3041 1.268 skrll /* Run callback. */
3042 1.92 augustss usb_transfer_complete(xfer);
3043 1.48 augustss
3044 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
3045 1.16 augustss }
3046 1.16 augustss
3047 1.16 augustss void
3048 1.268 skrll uhci_device_isoc_close(struct usbd_pipe *pipe)
3049 1.16 augustss {
3050 1.268 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
3051 1.268 skrll uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
3052 1.48 augustss uhci_soft_td_t *std, *vstd;
3053 1.268 skrll struct isoc *isoc;
3054 1.248 mrg int i;
3055 1.248 mrg
3056 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
3057 1.16 augustss
3058 1.16 augustss /*
3059 1.16 augustss * Make sure all TDs are marked as inactive.
3060 1.16 augustss * Wait for completion.
3061 1.16 augustss * Unschedule.
3062 1.16 augustss * Deallocate.
3063 1.16 augustss */
3064 1.268 skrll isoc = &upipe->isoc;
3065 1.16 augustss
3066 1.223 bouyer for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
3067 1.268 skrll std = isoc->stds[i];
3068 1.223 bouyer usb_syncmem(&std->dma,
3069 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
3070 1.223 bouyer sizeof(std->td.td_status),
3071 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3072 1.223 bouyer std->td.td_status &= htole32(~UHCI_TD_ACTIVE);
3073 1.223 bouyer usb_syncmem(&std->dma,
3074 1.223 bouyer std->offs + offsetof(uhci_td_t, td_status),
3075 1.223 bouyer sizeof(std->td.td_status),
3076 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3077 1.223 bouyer }
3078 1.248 mrg /* wait for completion */
3079 1.248 mrg usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock);
3080 1.16 augustss
3081 1.16 augustss for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
3082 1.268 skrll std = isoc->stds[i];
3083 1.48 augustss for (vstd = sc->sc_vframes[i].htd;
3084 1.67 augustss vstd != NULL && vstd->link.std != std;
3085 1.42 augustss vstd = vstd->link.std)
3086 1.16 augustss ;
3087 1.67 augustss if (vstd == NULL) {
3088 1.16 augustss /*panic*/
3089 1.268 skrll printf("%s: %p not found\n", __func__, std);
3090 1.248 mrg mutex_exit(&sc->sc_lock);
3091 1.16 augustss return;
3092 1.16 augustss }
3093 1.42 augustss vstd->link = std->link;
3094 1.223 bouyer usb_syncmem(&std->dma,
3095 1.223 bouyer std->offs + offsetof(uhci_td_t, td_link),
3096 1.223 bouyer sizeof(std->td.td_link),
3097 1.223 bouyer BUS_DMASYNC_POSTWRITE);
3098 1.42 augustss vstd->td.td_link = std->td.td_link;
3099 1.223 bouyer usb_syncmem(&vstd->dma,
3100 1.223 bouyer vstd->offs + offsetof(uhci_td_t, td_link),
3101 1.223 bouyer sizeof(vstd->td.td_link),
3102 1.223 bouyer BUS_DMASYNC_PREWRITE);
3103 1.268 skrll uhci_free_std_locked(sc, std);
3104 1.16 augustss }
3105 1.16 augustss
3106 1.268 skrll kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *));
3107 1.16 augustss }
3108 1.16 augustss
3109 1.16 augustss usbd_status
3110 1.268 skrll uhci_setup_isoc(struct usbd_pipe *pipe)
3111 1.16 augustss {
3112 1.268 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
3113 1.268 skrll uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
3114 1.268 skrll int addr = upipe->pipe.up_dev->ud_addr;
3115 1.268 skrll int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
3116 1.45 augustss int rd = UE_GET_DIR(endpt) == UE_DIR_IN;
3117 1.48 augustss uhci_soft_td_t *std, *vstd;
3118 1.268 skrll uint32_t token;
3119 1.268 skrll struct isoc *isoc;
3120 1.248 mrg int i;
3121 1.16 augustss
3122 1.268 skrll isoc = &upipe->isoc;
3123 1.268 skrll
3124 1.268 skrll isoc->stds = kmem_alloc(
3125 1.268 skrll UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *), KM_SLEEP);
3126 1.268 skrll if (isoc->stds == NULL)
3127 1.248 mrg return USBD_NOMEM;
3128 1.16 augustss
3129 1.88 tsutsui token = rd ? UHCI_TD_IN (0, endpt, addr, 0) :
3130 1.88 tsutsui UHCI_TD_OUT(0, endpt, addr, 0);
3131 1.16 augustss
3132 1.48 augustss /* Allocate the TDs and mark as inactive; */
3133 1.16 augustss for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
3134 1.48 augustss std = uhci_alloc_std(sc);
3135 1.48 augustss if (std == 0)
3136 1.48 augustss goto bad;
3137 1.88 tsutsui std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */
3138 1.88 tsutsui std->td.td_token = htole32(token);
3139 1.223 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
3140 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3141 1.268 skrll isoc->stds[i] = std;
3142 1.16 augustss }
3143 1.16 augustss
3144 1.268 skrll mutex_enter(&sc->sc_lock);
3145 1.268 skrll
3146 1.48 augustss /* Insert TDs into schedule. */
3147 1.16 augustss for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
3148 1.268 skrll std = isoc->stds[i];
3149 1.48 augustss vstd = sc->sc_vframes[i].htd;
3150 1.223 bouyer usb_syncmem(&vstd->dma,
3151 1.223 bouyer vstd->offs + offsetof(uhci_td_t, td_link),
3152 1.223 bouyer sizeof(vstd->td.td_link),
3153 1.223 bouyer BUS_DMASYNC_POSTWRITE);
3154 1.42 augustss std->link = vstd->link;
3155 1.42 augustss std->td.td_link = vstd->td.td_link;
3156 1.223 bouyer usb_syncmem(&std->dma,
3157 1.223 bouyer std->offs + offsetof(uhci_td_t, td_link),
3158 1.223 bouyer sizeof(std->td.td_link),
3159 1.223 bouyer BUS_DMASYNC_PREWRITE);
3160 1.42 augustss vstd->link.std = std;
3161 1.121 augustss vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD);
3162 1.223 bouyer usb_syncmem(&vstd->dma,
3163 1.223 bouyer vstd->offs + offsetof(uhci_td_t, td_link),
3164 1.223 bouyer sizeof(vstd->td.td_link),
3165 1.223 bouyer BUS_DMASYNC_PREWRITE);
3166 1.16 augustss }
3167 1.248 mrg mutex_exit(&sc->sc_lock);
3168 1.16 augustss
3169 1.268 skrll isoc->next = -1;
3170 1.268 skrll isoc->inuse = 0;
3171 1.48 augustss
3172 1.268 skrll return USBD_NORMAL_COMPLETION;
3173 1.16 augustss
3174 1.48 augustss bad:
3175 1.16 augustss while (--i >= 0)
3176 1.268 skrll uhci_free_std(sc, isoc->stds[i]);
3177 1.268 skrll kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *));
3178 1.268 skrll return USBD_NOMEM;
3179 1.16 augustss }
3180 1.16 augustss
3181 1.16 augustss void
3182 1.268 skrll uhci_device_isoc_done(struct usbd_xfer *xfer)
3183 1.16 augustss {
3184 1.268 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
3185 1.268 skrll struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
3186 1.223 bouyer int i, offs;
3187 1.268 skrll int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN;
3188 1.170 augustss
3189 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3190 1.268 skrll DPRINTFN(4, "length=%d, ux_state=0x%08x",
3191 1.268 skrll xfer->ux_actlen, xfer->ux_state, 0, 0);
3192 1.96 augustss
3193 1.93 augustss #ifdef DIAGNOSTIC
3194 1.268 skrll if (ux->ux_stdend == NULL) {
3195 1.268 skrll printf("%s: xfer=%p stdend==NULL\n", __func__, xfer);
3196 1.93 augustss #ifdef UHCI_DEBUG
3197 1.268 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
3198 1.268 skrll uhci_dump_ii(ux);
3199 1.268 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
3200 1.93 augustss #endif
3201 1.93 augustss return;
3202 1.93 augustss }
3203 1.93 augustss #endif
3204 1.48 augustss
3205 1.48 augustss /* Turn off the interrupt since it is active even if the TD is not. */
3206 1.268 skrll usb_syncmem(&ux->ux_stdend->dma,
3207 1.268 skrll ux->ux_stdend->offs + offsetof(uhci_td_t, td_status),
3208 1.268 skrll sizeof(ux->ux_stdend->td.td_status),
3209 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3210 1.268 skrll ux->ux_stdend->td.td_status &= htole32(~UHCI_TD_IOC);
3211 1.268 skrll usb_syncmem(&ux->ux_stdend->dma,
3212 1.268 skrll ux->ux_stdend->offs + offsetof(uhci_td_t, td_status),
3213 1.268 skrll sizeof(ux->ux_stdend->td.td_status),
3214 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3215 1.48 augustss
3216 1.223 bouyer offs = 0;
3217 1.268 skrll for (i = 0; i < xfer->ux_nframes; i++) {
3218 1.268 skrll usb_syncmem(&xfer->ux_dmabuf, offs, xfer->ux_frlengths[i],
3219 1.223 bouyer rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
3220 1.268 skrll offs += xfer->ux_frlengths[i];
3221 1.223 bouyer }
3222 1.16 augustss }
3223 1.16 augustss
3224 1.1 augustss void
3225 1.268 skrll uhci_device_intr_done(struct usbd_xfer *xfer)
3226 1.1 augustss {
3227 1.269 skrll uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer);
3228 1.268 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
3229 1.1 augustss uhci_soft_qh_t *sqh;
3230 1.268 skrll int i, npoll;
3231 1.1 augustss
3232 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3233 1.268 skrll DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0);
3234 1.1 augustss
3235 1.268 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
3236 1.248 mrg
3237 1.268 skrll npoll = upipe->intr.npoll;
3238 1.267 skrll for (i = 0; i < npoll; i++) {
3239 1.268 skrll sqh = upipe->intr.qhs[i];
3240 1.121 augustss sqh->elink = NULL;
3241 1.88 tsutsui sqh->qh.qh_elink = htole32(UHCI_PTR_T);
3242 1.223 bouyer usb_syncmem(&sqh->dma,
3243 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
3244 1.223 bouyer sizeof(sqh->qh.qh_elink),
3245 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3246 1.1 augustss }
3247 1.268 skrll const int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
3248 1.268 skrll const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3249 1.268 skrll usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
3250 1.223 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
3251 1.1 augustss }
3252 1.1 augustss
3253 1.1 augustss /* Deallocate request data structures */
3254 1.1 augustss void
3255 1.268 skrll uhci_device_ctrl_done(struct usbd_xfer *xfer)
3256 1.1 augustss {
3257 1.268 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
3258 1.268 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
3259 1.268 skrll int len = UGETW(xfer->ux_request.wLength);
3260 1.268 skrll int isread = (xfer->ux_request.bmRequestType & UT_READ);
3261 1.1 augustss
3262 1.268 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
3263 1.248 mrg
3264 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3265 1.169 augustss
3266 1.268 skrll KASSERT(xfer->ux_rqflags & URQ_REQUEST);
3267 1.1 augustss
3268 1.268 skrll /* XXXNH move to uhci_idone??? */
3269 1.268 skrll if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW)
3270 1.268 skrll uhci_remove_ls_ctrl(sc, upipe->ctrl.sqh);
3271 1.123 augustss else
3272 1.268 skrll uhci_remove_hs_ctrl(sc, upipe->ctrl.sqh);
3273 1.49 augustss
3274 1.223 bouyer if (len) {
3275 1.268 skrll usb_syncmem(&xfer->ux_dmabuf, 0, len,
3276 1.223 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
3277 1.223 bouyer }
3278 1.268 skrll usb_syncmem(&upipe->ctrl.reqdma, 0,
3279 1.223 bouyer sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE);
3280 1.223 bouyer
3281 1.268 skrll DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0);
3282 1.1 augustss }
3283 1.1 augustss
3284 1.1 augustss /* Deallocate request data structures */
3285 1.1 augustss void
3286 1.268 skrll uhci_device_bulk_done(struct usbd_xfer *xfer)
3287 1.1 augustss {
3288 1.268 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
3289 1.268 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
3290 1.268 skrll usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc;
3291 1.268 skrll int endpt = ed->bEndpointAddress;
3292 1.268 skrll int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3293 1.169 augustss
3294 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3295 1.268 skrll DPRINTFN(5, "xfer=%p sc=%p upipe=%p", xfer, sc, upipe, 0);
3296 1.169 augustss
3297 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
3298 1.248 mrg
3299 1.268 skrll uhci_remove_bulk(sc, upipe->bulk.sqh);
3300 1.1 augustss
3301 1.268 skrll if (xfer->ux_length) {
3302 1.268 skrll usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
3303 1.268 skrll isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
3304 1.268 skrll }
3305 1.1 augustss
3306 1.268 skrll DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0);
3307 1.1 augustss }
3308 1.1 augustss
3309 1.1 augustss /* Add interrupt QH, called with vflock. */
3310 1.1 augustss void
3311 1.119 augustss uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
3312 1.1 augustss {
3313 1.92 augustss struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos];
3314 1.42 augustss uhci_soft_qh_t *eqh;
3315 1.1 augustss
3316 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3317 1.268 skrll DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0);
3318 1.92 augustss
3319 1.42 augustss eqh = vf->eqh;
3320 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
3321 1.223 bouyer sizeof(eqh->qh.qh_hlink),
3322 1.223 bouyer BUS_DMASYNC_POSTWRITE);
3323 1.42 augustss sqh->hlink = eqh->hlink;
3324 1.42 augustss sqh->qh.qh_hlink = eqh->qh.qh_hlink;
3325 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
3326 1.223 bouyer sizeof(sqh->qh.qh_hlink),
3327 1.223 bouyer BUS_DMASYNC_PREWRITE);
3328 1.42 augustss eqh->hlink = sqh;
3329 1.121 augustss eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
3330 1.223 bouyer usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
3331 1.223 bouyer sizeof(eqh->qh.qh_hlink),
3332 1.223 bouyer BUS_DMASYNC_PREWRITE);
3333 1.1 augustss vf->eqh = sqh;
3334 1.1 augustss vf->bandwidth++;
3335 1.1 augustss }
3336 1.1 augustss
3337 1.119 augustss /* Remove interrupt QH. */
3338 1.1 augustss void
3339 1.119 augustss uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
3340 1.1 augustss {
3341 1.92 augustss struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos];
3342 1.1 augustss uhci_soft_qh_t *pqh;
3343 1.1 augustss
3344 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3345 1.268 skrll DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0);
3346 1.1 augustss
3347 1.124 augustss /* See comment in uhci_remove_ctrl() */
3348 1.223 bouyer
3349 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
3350 1.223 bouyer sizeof(sqh->qh.qh_elink),
3351 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3352 1.124 augustss if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) {
3353 1.124 augustss sqh->qh.qh_elink = htole32(UHCI_PTR_T);
3354 1.223 bouyer usb_syncmem(&sqh->dma,
3355 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
3356 1.223 bouyer sizeof(sqh->qh.qh_elink),
3357 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3358 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
3359 1.124 augustss }
3360 1.124 augustss
3361 1.92 augustss pqh = uhci_find_prev_qh(vf->hqh, sqh);
3362 1.223 bouyer usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
3363 1.223 bouyer sizeof(sqh->qh.qh_hlink),
3364 1.223 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3365 1.42 augustss pqh->hlink = sqh->hlink;
3366 1.42 augustss pqh->qh.qh_hlink = sqh->qh.qh_hlink;
3367 1.223 bouyer usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
3368 1.223 bouyer sizeof(pqh->qh.qh_hlink),
3369 1.223 bouyer BUS_DMASYNC_PREWRITE);
3370 1.124 augustss delay(UHCI_QH_REMOVE_DELAY);
3371 1.1 augustss if (vf->eqh == sqh)
3372 1.1 augustss vf->eqh = pqh;
3373 1.1 augustss vf->bandwidth--;
3374 1.1 augustss }
3375 1.1 augustss
3376 1.1 augustss usbd_status
3377 1.119 augustss uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival)
3378 1.1 augustss {
3379 1.1 augustss uhci_soft_qh_t *sqh;
3380 1.248 mrg int i, npoll;
3381 1.1 augustss u_int bestbw, bw, bestoffs, offs;
3382 1.1 augustss
3383 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3384 1.268 skrll DPRINTFN(2, "pipe=%p", upipe, 0, 0, 0);
3385 1.1 augustss if (ival == 0) {
3386 1.268 skrll printf("%s: 0 interval\n", __func__);
3387 1.268 skrll return USBD_INVAL;
3388 1.1 augustss }
3389 1.1 augustss
3390 1.1 augustss if (ival > UHCI_VFRAMELIST_COUNT)
3391 1.1 augustss ival = UHCI_VFRAMELIST_COUNT;
3392 1.1 augustss npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival;
3393 1.268 skrll DPRINTF("ival=%d npoll=%d", ival, npoll, 0, 0);
3394 1.1 augustss
3395 1.268 skrll upipe->intr.npoll = npoll;
3396 1.268 skrll upipe->intr.qhs =
3397 1.248 mrg kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP);
3398 1.268 skrll if (upipe->intr.qhs == NULL)
3399 1.248 mrg return USBD_NOMEM;
3400 1.1 augustss
3401 1.152 augustss /*
3402 1.1 augustss * Figure out which offset in the schedule that has most
3403 1.1 augustss * bandwidth left over.
3404 1.1 augustss */
3405 1.1 augustss #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1))
3406 1.1 augustss for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) {
3407 1.1 augustss for (bw = i = 0; i < npoll; i++)
3408 1.1 augustss bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth;
3409 1.1 augustss if (bw < bestbw) {
3410 1.1 augustss bestbw = bw;
3411 1.1 augustss bestoffs = offs;
3412 1.1 augustss }
3413 1.1 augustss }
3414 1.268 skrll DPRINTF("bw=%d offs=%d", bestbw, bestoffs, 0, 0);
3415 1.267 skrll for (i = 0; i < npoll; i++) {
3416 1.268 skrll upipe->intr.qhs[i] = sqh = uhci_alloc_sqh(sc);
3417 1.121 augustss sqh->elink = NULL;
3418 1.88 tsutsui sqh->qh.qh_elink = htole32(UHCI_PTR_T);
3419 1.223 bouyer usb_syncmem(&sqh->dma,
3420 1.223 bouyer sqh->offs + offsetof(uhci_qh_t, qh_elink),
3421 1.223 bouyer sizeof(sqh->qh.qh_elink),
3422 1.223 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3423 1.1 augustss sqh->pos = MOD(i * ival + bestoffs);
3424 1.1 augustss }
3425 1.1 augustss #undef MOD
3426 1.1 augustss
3427 1.268 skrll mutex_enter(&sc->sc_lock);
3428 1.1 augustss /* Enter QHs into the controller data structures. */
3429 1.267 skrll for (i = 0; i < npoll; i++)
3430 1.268 skrll uhci_add_intr(sc, upipe->intr.qhs[i]);
3431 1.248 mrg mutex_exit(&sc->sc_lock);
3432 1.1 augustss
3433 1.268 skrll DPRINTFN(5, "returns %p", upipe, 0, 0, 0);
3434 1.268 skrll
3435 1.268 skrll return USBD_NORMAL_COMPLETION;
3436 1.1 augustss }
3437 1.1 augustss
3438 1.1 augustss /* Open a new pipe. */
3439 1.1 augustss usbd_status
3440 1.268 skrll uhci_open(struct usbd_pipe *pipe)
3441 1.1 augustss {
3442 1.268 skrll uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
3443 1.268 skrll struct usbd_bus *bus = pipe->up_dev->ud_bus;
3444 1.268 skrll struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
3445 1.268 skrll usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc;
3446 1.248 mrg usbd_status err = USBD_NOMEM;
3447 1.79 augustss int ival;
3448 1.1 augustss
3449 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3450 1.268 skrll DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)",
3451 1.268 skrll pipe, pipe->up_dev->ud_addr, ed->bEndpointAddress, bus->ub_rhaddr);
3452 1.92 augustss
3453 1.248 mrg if (sc->sc_dying)
3454 1.248 mrg return USBD_IOERROR;
3455 1.248 mrg
3456 1.92 augustss upipe->aborting = 0;
3457 1.236 drochner /* toggle state needed for bulk endpoints */
3458 1.268 skrll upipe->nexttoggle = pipe->up_endpoint->ue_toggle;
3459 1.92 augustss
3460 1.268 skrll if (pipe->up_dev->ud_addr == bus->ub_rhaddr) {
3461 1.1 augustss switch (ed->bEndpointAddress) {
3462 1.1 augustss case USB_CONTROL_ENDPOINT:
3463 1.268 skrll pipe->up_methods = &roothub_ctrl_methods;
3464 1.1 augustss break;
3465 1.268 skrll case UE_DIR_IN | USBROOTHUB_INTR_ENDPT:
3466 1.268 skrll pipe->up_methods = &uhci_root_intr_methods;
3467 1.1 augustss break;
3468 1.1 augustss default:
3469 1.268 skrll return USBD_INVAL;
3470 1.1 augustss }
3471 1.1 augustss } else {
3472 1.1 augustss switch (ed->bmAttributes & UE_XFERTYPE) {
3473 1.1 augustss case UE_CONTROL:
3474 1.268 skrll pipe->up_methods = &uhci_device_ctrl_methods;
3475 1.268 skrll upipe->ctrl.sqh = uhci_alloc_sqh(sc);
3476 1.268 skrll if (upipe->ctrl.sqh == NULL)
3477 1.5 augustss goto bad;
3478 1.268 skrll upipe->ctrl.setup = uhci_alloc_std(sc);
3479 1.268 skrll if (upipe->ctrl.setup == NULL) {
3480 1.268 skrll uhci_free_sqh(sc, upipe->ctrl.sqh);
3481 1.5 augustss goto bad;
3482 1.5 augustss }
3483 1.268 skrll upipe->ctrl.stat = uhci_alloc_std(sc);
3484 1.268 skrll if (upipe->ctrl.stat == NULL) {
3485 1.268 skrll uhci_free_sqh(sc, upipe->ctrl.sqh);
3486 1.268 skrll uhci_free_std(sc, upipe->ctrl.setup);
3487 1.5 augustss goto bad;
3488 1.5 augustss }
3489 1.152 augustss err = usb_allocmem(&sc->sc_bus,
3490 1.152 augustss sizeof(usb_device_request_t),
3491 1.268 skrll 0, &upipe->ctrl.reqdma);
3492 1.63 augustss if (err) {
3493 1.268 skrll uhci_free_sqh(sc, upipe->ctrl.sqh);
3494 1.268 skrll uhci_free_std(sc, upipe->ctrl.setup);
3495 1.268 skrll uhci_free_std(sc, upipe->ctrl.stat);
3496 1.5 augustss goto bad;
3497 1.5 augustss }
3498 1.1 augustss break;
3499 1.1 augustss case UE_INTERRUPT:
3500 1.268 skrll pipe->up_methods = &uhci_device_intr_methods;
3501 1.268 skrll ival = pipe->up_interval;
3502 1.79 augustss if (ival == USBD_DEFAULT_INTERVAL)
3503 1.79 augustss ival = ed->bInterval;
3504 1.268 skrll return uhci_device_setintr(sc, upipe, ival);
3505 1.1 augustss case UE_ISOCHRONOUS:
3506 1.268 skrll pipe->up_serialise = false;
3507 1.268 skrll pipe->up_methods = &uhci_device_isoc_methods;
3508 1.268 skrll return uhci_setup_isoc(pipe);
3509 1.1 augustss case UE_BULK:
3510 1.268 skrll pipe->up_methods = &uhci_device_bulk_methods;
3511 1.268 skrll upipe->bulk.sqh = uhci_alloc_sqh(sc);
3512 1.268 skrll if (upipe->bulk.sqh == NULL)
3513 1.5 augustss goto bad;
3514 1.1 augustss break;
3515 1.1 augustss }
3516 1.1 augustss }
3517 1.268 skrll return USBD_NORMAL_COMPLETION;
3518 1.5 augustss
3519 1.5 augustss bad:
3520 1.248 mrg return USBD_NOMEM;
3521 1.1 augustss }
3522 1.1 augustss
3523 1.1 augustss /*
3524 1.1 augustss * Data structures and routines to emulate the root hub.
3525 1.1 augustss */
3526 1.1 augustss /*
3527 1.166 dsainty * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also
3528 1.166 dsainty * enables the port, and also states that SET_FEATURE(PORT_ENABLE)
3529 1.166 dsainty * should not be used by the USB subsystem. As we cannot issue a
3530 1.166 dsainty * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port
3531 1.166 dsainty * will be enabled as part of the reset.
3532 1.166 dsainty *
3533 1.166 dsainty * On the VT83C572, the port cannot be successfully enabled until the
3534 1.166 dsainty * outstanding "port enable change" and "connection status change"
3535 1.166 dsainty * events have been reset.
3536 1.166 dsainty */
3537 1.166 dsainty Static usbd_status
3538 1.166 dsainty uhci_portreset(uhci_softc_t *sc, int index)
3539 1.166 dsainty {
3540 1.166 dsainty int lim, port, x;
3541 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3542 1.166 dsainty
3543 1.166 dsainty if (index == 1)
3544 1.166 dsainty port = UHCI_PORTSC1;
3545 1.166 dsainty else if (index == 2)
3546 1.166 dsainty port = UHCI_PORTSC2;
3547 1.166 dsainty else
3548 1.268 skrll return USBD_IOERROR;
3549 1.166 dsainty
3550 1.166 dsainty x = URWMASK(UREAD2(sc, port));
3551 1.166 dsainty UWRITE2(sc, port, x | UHCI_PORTSC_PR);
3552 1.166 dsainty
3553 1.166 dsainty usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY);
3554 1.166 dsainty
3555 1.268 skrll DPRINTF("uhci port %d reset, status0 = 0x%04x", index,
3556 1.268 skrll UREAD2(sc, port), 0, 0);
3557 1.166 dsainty
3558 1.166 dsainty x = URWMASK(UREAD2(sc, port));
3559 1.222 drochner UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP));
3560 1.166 dsainty
3561 1.166 dsainty delay(100);
3562 1.166 dsainty
3563 1.268 skrll DPRINTF("uhci port %d reset, status1 = 0x%04x", index,
3564 1.268 skrll UREAD2(sc, port), 0, 0);
3565 1.166 dsainty
3566 1.166 dsainty x = URWMASK(UREAD2(sc, port));
3567 1.166 dsainty UWRITE2(sc, port, x | UHCI_PORTSC_PE);
3568 1.166 dsainty
3569 1.166 dsainty for (lim = 10; --lim > 0;) {
3570 1.166 dsainty usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY);
3571 1.166 dsainty
3572 1.166 dsainty x = UREAD2(sc, port);
3573 1.268 skrll DPRINTF("uhci port %d iteration %u, status = 0x%04x", index,
3574 1.268 skrll lim, x, 0);
3575 1.166 dsainty
3576 1.166 dsainty if (!(x & UHCI_PORTSC_CCS)) {
3577 1.166 dsainty /*
3578 1.166 dsainty * No device is connected (or was disconnected
3579 1.166 dsainty * during reset). Consider the port reset.
3580 1.166 dsainty * The delay must be long enough to ensure on
3581 1.166 dsainty * the initial iteration that the device
3582 1.166 dsainty * connection will have been registered. 50ms
3583 1.166 dsainty * appears to be sufficient, but 20ms is not.
3584 1.166 dsainty */
3585 1.268 skrll DPRINTFN(3, "uhci port %d loop %u, device detached",
3586 1.268 skrll index, lim, 0, 0);
3587 1.166 dsainty break;
3588 1.166 dsainty }
3589 1.166 dsainty
3590 1.166 dsainty if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) {
3591 1.166 dsainty /*
3592 1.166 dsainty * Port enabled changed and/or connection
3593 1.166 dsainty * status changed were set. Reset either or
3594 1.166 dsainty * both raised flags (by writing a 1 to that
3595 1.166 dsainty * bit), and wait again for state to settle.
3596 1.166 dsainty */
3597 1.166 dsainty UWRITE2(sc, port, URWMASK(x) |
3598 1.166 dsainty (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)));
3599 1.166 dsainty continue;
3600 1.166 dsainty }
3601 1.166 dsainty
3602 1.166 dsainty if (x & UHCI_PORTSC_PE)
3603 1.166 dsainty /* Port is enabled */
3604 1.166 dsainty break;
3605 1.166 dsainty
3606 1.166 dsainty UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE);
3607 1.166 dsainty }
3608 1.166 dsainty
3609 1.268 skrll DPRINTFN(3, "uhci port %d reset, status2 = 0x%04x", index,
3610 1.268 skrll UREAD2(sc, port), 0, 0);
3611 1.166 dsainty
3612 1.166 dsainty if (lim <= 0) {
3613 1.268 skrll DPRINTF("uhci port %d reset timed out", index,
3614 1.268 skrll 0, 0, 0);
3615 1.268 skrll return USBD_TIMEOUT;
3616 1.166 dsainty }
3617 1.184 perry
3618 1.166 dsainty sc->sc_isreset = 1;
3619 1.268 skrll return USBD_NORMAL_COMPLETION;
3620 1.166 dsainty }
3621 1.166 dsainty
3622 1.268 skrll Static int
3623 1.268 skrll uhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req,
3624 1.268 skrll void *buf, int buflen)
3625 1.1 augustss {
3626 1.268 skrll uhci_softc_t *sc = UHCI_BUS2SC(bus);
3627 1.1 augustss int port, x;
3628 1.268 skrll int status, change, totlen = 0;
3629 1.268 skrll uint16_t len, value, index;
3630 1.1 augustss usb_port_status_t ps;
3631 1.63 augustss usbd_status err;
3632 1.1 augustss
3633 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3634 1.268 skrll
3635 1.82 augustss if (sc->sc_dying)
3636 1.268 skrll return -1;
3637 1.1 augustss
3638 1.268 skrll DPRINTF("type=0x%02x request=%02x", req->bmRequestType,
3639 1.268 skrll req->bRequest, 0, 0);
3640 1.1 augustss
3641 1.1 augustss len = UGETW(req->wLength);
3642 1.1 augustss value = UGETW(req->wValue);
3643 1.1 augustss index = UGETW(req->wIndex);
3644 1.49 augustss
3645 1.1 augustss #define C(x,y) ((x) | ((y) << 8))
3646 1.268 skrll switch (C(req->bRequest, req->bmRequestType)) {
3647 1.1 augustss case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3648 1.268 skrll DPRINTF("wValue=0x%04x", value, 0, 0, 0);
3649 1.195 christos if (len == 0)
3650 1.195 christos break;
3651 1.268 skrll switch (value) {
3652 1.268 skrll case C(0, UDESC_DEVICE): {
3653 1.268 skrll usb_device_descriptor_t devd;
3654 1.268 skrll
3655 1.268 skrll totlen = min(buflen, sizeof(devd));
3656 1.268 skrll memcpy(&devd, buf, totlen);
3657 1.268 skrll USETW(devd.idVendor, sc->sc_id_vendor);
3658 1.268 skrll memcpy(buf, &devd, totlen);
3659 1.1 augustss break;
3660 1.268 skrll }
3661 1.268 skrll case C(1, UDESC_STRING):
3662 1.213 drochner #define sd ((usb_string_descriptor_t *)buf)
3663 1.268 skrll /* Vendor */
3664 1.268 skrll totlen = usb_makestrdesc(sd, len, sc->sc_vendor);
3665 1.268 skrll break;
3666 1.268 skrll case C(2, UDESC_STRING):
3667 1.268 skrll /* Product */
3668 1.268 skrll totlen = usb_makestrdesc(sd, len, "UHCI root hub");
3669 1.268 skrll break;
3670 1.213 drochner #undef sd
3671 1.1 augustss default:
3672 1.268 skrll /* default from usbroothub */
3673 1.268 skrll return buflen;
3674 1.1 augustss }
3675 1.1 augustss break;
3676 1.268 skrll
3677 1.1 augustss /* Hub requests */
3678 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3679 1.1 augustss break;
3680 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3681 1.268 skrll DPRINTF("UR_CLEAR_PORT_FEATURE port=%d feature=%d", index,
3682 1.268 skrll value, 0, 0);
3683 1.1 augustss if (index == 1)
3684 1.1 augustss port = UHCI_PORTSC1;
3685 1.1 augustss else if (index == 2)
3686 1.1 augustss port = UHCI_PORTSC2;
3687 1.1 augustss else {
3688 1.268 skrll return -1;
3689 1.1 augustss }
3690 1.1 augustss switch(value) {
3691 1.1 augustss case UHF_PORT_ENABLE:
3692 1.137 augustss x = URWMASK(UREAD2(sc, port));
3693 1.1 augustss UWRITE2(sc, port, x & ~UHCI_PORTSC_PE);
3694 1.1 augustss break;
3695 1.1 augustss case UHF_PORT_SUSPEND:
3696 1.137 augustss x = URWMASK(UREAD2(sc, port));
3697 1.222 drochner if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */
3698 1.222 drochner break;
3699 1.222 drochner UWRITE2(sc, port, x | UHCI_PORTSC_RD);
3700 1.222 drochner /* see USB2 spec ch. 7.1.7.7 */
3701 1.222 drochner usb_delay_ms(&sc->sc_bus, 20);
3702 1.1 augustss UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP);
3703 1.222 drochner /* 10ms resume delay must be provided by caller */
3704 1.1 augustss break;
3705 1.1 augustss case UHF_PORT_RESET:
3706 1.137 augustss x = URWMASK(UREAD2(sc, port));
3707 1.1 augustss UWRITE2(sc, port, x & ~UHCI_PORTSC_PR);
3708 1.1 augustss break;
3709 1.1 augustss case UHF_C_PORT_CONNECTION:
3710 1.137 augustss x = URWMASK(UREAD2(sc, port));
3711 1.1 augustss UWRITE2(sc, port, x | UHCI_PORTSC_CSC);
3712 1.1 augustss break;
3713 1.1 augustss case UHF_C_PORT_ENABLE:
3714 1.137 augustss x = URWMASK(UREAD2(sc, port));
3715 1.1 augustss UWRITE2(sc, port, x | UHCI_PORTSC_POEDC);
3716 1.1 augustss break;
3717 1.1 augustss case UHF_C_PORT_OVER_CURRENT:
3718 1.137 augustss x = URWMASK(UREAD2(sc, port));
3719 1.1 augustss UWRITE2(sc, port, x | UHCI_PORTSC_OCIC);
3720 1.1 augustss break;
3721 1.1 augustss case UHF_C_PORT_RESET:
3722 1.1 augustss sc->sc_isreset = 0;
3723 1.268 skrll break;
3724 1.1 augustss case UHF_PORT_CONNECTION:
3725 1.1 augustss case UHF_PORT_OVER_CURRENT:
3726 1.1 augustss case UHF_PORT_POWER:
3727 1.1 augustss case UHF_PORT_LOW_SPEED:
3728 1.1 augustss case UHF_C_PORT_SUSPEND:
3729 1.1 augustss default:
3730 1.268 skrll return -1;
3731 1.1 augustss }
3732 1.1 augustss break;
3733 1.1 augustss case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER):
3734 1.1 augustss if (index == 1)
3735 1.1 augustss port = UHCI_PORTSC1;
3736 1.1 augustss else if (index == 2)
3737 1.1 augustss port = UHCI_PORTSC2;
3738 1.1 augustss else {
3739 1.268 skrll return -1;
3740 1.1 augustss }
3741 1.1 augustss if (len > 0) {
3742 1.268 skrll *(uint8_t *)buf =
3743 1.268 skrll UHCI_PORTSC_GET_LS(UREAD2(sc, port));
3744 1.1 augustss totlen = 1;
3745 1.1 augustss }
3746 1.1 augustss break;
3747 1.1 augustss case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3748 1.195 christos if (len == 0)
3749 1.195 christos break;
3750 1.177 toshii if ((value & 0xff) != 0) {
3751 1.268 skrll return -1;
3752 1.1 augustss }
3753 1.268 skrll usb_hub_descriptor_t hubd;
3754 1.268 skrll
3755 1.268 skrll totlen = min(buflen, sizeof(hubd));
3756 1.268 skrll memcpy(&hubd, buf, totlen);
3757 1.268 skrll hubd.bNbrPorts = 2;
3758 1.268 skrll memcpy(buf, &hubd, totlen);
3759 1.1 augustss break;
3760 1.1 augustss case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3761 1.1 augustss if (len != 4) {
3762 1.268 skrll return -1;
3763 1.1 augustss }
3764 1.1 augustss memset(buf, 0, len);
3765 1.1 augustss totlen = len;
3766 1.1 augustss break;
3767 1.1 augustss case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3768 1.1 augustss if (index == 1)
3769 1.1 augustss port = UHCI_PORTSC1;
3770 1.1 augustss else if (index == 2)
3771 1.1 augustss port = UHCI_PORTSC2;
3772 1.1 augustss else {
3773 1.268 skrll return -1;
3774 1.1 augustss }
3775 1.1 augustss if (len != 4) {
3776 1.268 skrll return -1;
3777 1.1 augustss }
3778 1.1 augustss x = UREAD2(sc, port);
3779 1.1 augustss status = change = 0;
3780 1.142 augustss if (x & UHCI_PORTSC_CCS)
3781 1.1 augustss status |= UPS_CURRENT_CONNECT_STATUS;
3782 1.152 augustss if (x & UHCI_PORTSC_CSC)
3783 1.1 augustss change |= UPS_C_CONNECT_STATUS;
3784 1.152 augustss if (x & UHCI_PORTSC_PE)
3785 1.1 augustss status |= UPS_PORT_ENABLED;
3786 1.152 augustss if (x & UHCI_PORTSC_POEDC)
3787 1.1 augustss change |= UPS_C_PORT_ENABLED;
3788 1.152 augustss if (x & UHCI_PORTSC_OCI)
3789 1.1 augustss status |= UPS_OVERCURRENT_INDICATOR;
3790 1.152 augustss if (x & UHCI_PORTSC_OCIC)
3791 1.1 augustss change |= UPS_C_OVERCURRENT_INDICATOR;
3792 1.152 augustss if (x & UHCI_PORTSC_SUSP)
3793 1.1 augustss status |= UPS_SUSPEND;
3794 1.152 augustss if (x & UHCI_PORTSC_LSDA)
3795 1.1 augustss status |= UPS_LOW_SPEED;
3796 1.1 augustss status |= UPS_PORT_POWER;
3797 1.1 augustss if (sc->sc_isreset)
3798 1.1 augustss change |= UPS_C_PORT_RESET;
3799 1.1 augustss USETW(ps.wPortStatus, status);
3800 1.1 augustss USETW(ps.wPortChange, change);
3801 1.268 skrll totlen = min(len, sizeof(ps));
3802 1.268 skrll memcpy(buf, &ps, totlen);
3803 1.1 augustss break;
3804 1.1 augustss case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3805 1.268 skrll return -1;
3806 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3807 1.1 augustss break;
3808 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3809 1.1 augustss if (index == 1)
3810 1.1 augustss port = UHCI_PORTSC1;
3811 1.1 augustss else if (index == 2)
3812 1.1 augustss port = UHCI_PORTSC2;
3813 1.1 augustss else {
3814 1.268 skrll return -1;
3815 1.1 augustss }
3816 1.1 augustss switch(value) {
3817 1.1 augustss case UHF_PORT_ENABLE:
3818 1.137 augustss x = URWMASK(UREAD2(sc, port));
3819 1.1 augustss UWRITE2(sc, port, x | UHCI_PORTSC_PE);
3820 1.1 augustss break;
3821 1.1 augustss case UHF_PORT_SUSPEND:
3822 1.137 augustss x = URWMASK(UREAD2(sc, port));
3823 1.1 augustss UWRITE2(sc, port, x | UHCI_PORTSC_SUSP);
3824 1.1 augustss break;
3825 1.1 augustss case UHF_PORT_RESET:
3826 1.166 dsainty err = uhci_portreset(sc, index);
3827 1.268 skrll if (err != USBD_NORMAL_COMPLETION)
3828 1.268 skrll return -1;
3829 1.268 skrll return 0;
3830 1.111 augustss case UHF_PORT_POWER:
3831 1.111 augustss /* Pretend we turned on power */
3832 1.268 skrll return 0;
3833 1.1 augustss case UHF_C_PORT_CONNECTION:
3834 1.1 augustss case UHF_C_PORT_ENABLE:
3835 1.1 augustss case UHF_C_PORT_OVER_CURRENT:
3836 1.1 augustss case UHF_PORT_CONNECTION:
3837 1.1 augustss case UHF_PORT_OVER_CURRENT:
3838 1.1 augustss case UHF_PORT_LOW_SPEED:
3839 1.1 augustss case UHF_C_PORT_SUSPEND:
3840 1.1 augustss case UHF_C_PORT_RESET:
3841 1.1 augustss default:
3842 1.268 skrll return -1;
3843 1.1 augustss }
3844 1.1 augustss break;
3845 1.1 augustss default:
3846 1.268 skrll /* default from usbroothub */
3847 1.268 skrll DPRINTF("returning %d (usbroothub default)",
3848 1.268 skrll buflen, 0, 0, 0);
3849 1.268 skrll return buflen;
3850 1.1 augustss }
3851 1.1 augustss
3852 1.268 skrll DPRINTF("returning %d", totlen, 0, 0, 0);
3853 1.1 augustss
3854 1.268 skrll return totlen;
3855 1.1 augustss }
3856 1.1 augustss
3857 1.1 augustss /* Abort a root interrupt request. */
3858 1.1 augustss void
3859 1.268 skrll uhci_root_intr_abort(struct usbd_xfer *xfer)
3860 1.1 augustss {
3861 1.268 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
3862 1.30 augustss
3863 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
3864 1.268 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
3865 1.248 mrg
3866 1.234 dyoung callout_stop(&sc->sc_poll_handle);
3867 1.96 augustss sc->sc_intr_xfer = NULL;
3868 1.58 augustss
3869 1.268 skrll xfer->ux_status = USBD_CANCELLED;
3870 1.96 augustss #ifdef DIAGNOSTIC
3871 1.268 skrll UHCI_XFER2UXFER(xfer)->ux_isdone = true;
3872 1.96 augustss #endif
3873 1.63 augustss usb_transfer_complete(xfer);
3874 1.1 augustss }
3875 1.1 augustss
3876 1.16 augustss usbd_status
3877 1.268 skrll uhci_root_intr_transfer(struct usbd_xfer *xfer)
3878 1.16 augustss {
3879 1.268 skrll uhci_softc_t *sc = UHCI_XFER2SC(xfer);
3880 1.63 augustss usbd_status err;
3881 1.16 augustss
3882 1.52 augustss /* Insert last in queue. */
3883 1.248 mrg mutex_enter(&sc->sc_lock);
3884 1.63 augustss err = usb_insert_transfer(xfer);
3885 1.248 mrg mutex_exit(&sc->sc_lock);
3886 1.63 augustss if (err)
3887 1.268 skrll return err;
3888 1.52 augustss
3889 1.186 skrll /*
3890 1.186 skrll * Pipe isn't running (otherwise err would be USBD_INPROG),
3891 1.67 augustss * start first
3892 1.67 augustss */
3893 1.268 skrll return uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
3894 1.16 augustss }
3895 1.16 augustss
3896 1.1 augustss /* Start a transfer on the root interrupt pipe */
3897 1.1 augustss usbd_status
3898 1.268 skrll uhci_root_intr_start(struct usbd_xfer *xfer)
3899 1.1 augustss {
3900 1.268 skrll struct usbd_pipe *pipe = xfer->ux_pipe;
3901 1.268 skrll uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
3902 1.174 drochner unsigned int ival;
3903 1.1 augustss
3904 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3905 1.268 skrll DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length,
3906 1.268 skrll xfer->ux_flags, 0);
3907 1.82 augustss
3908 1.82 augustss if (sc->sc_dying)
3909 1.268 skrll return USBD_IOERROR;
3910 1.1 augustss
3911 1.174 drochner /* XXX temporary variable needed to avoid gcc3 warning */
3912 1.268 skrll ival = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval;
3913 1.174 drochner sc->sc_ival = mstohz(ival);
3914 1.234 dyoung callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer);
3915 1.96 augustss sc->sc_intr_xfer = xfer;
3916 1.268 skrll return USBD_IN_PROGRESS;
3917 1.1 augustss }
3918 1.1 augustss
3919 1.1 augustss /* Close the root interrupt pipe. */
3920 1.1 augustss void
3921 1.268 skrll uhci_root_intr_close(struct usbd_pipe *pipe)
3922 1.1 augustss {
3923 1.268 skrll uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
3924 1.268 skrll UHCIHIST_FUNC(); UHCIHIST_CALLED();
3925 1.30 augustss
3926 1.248 mrg KASSERT(mutex_owned(&sc->sc_lock));
3927 1.248 mrg
3928 1.234 dyoung callout_stop(&sc->sc_poll_handle);
3929 1.96 augustss sc->sc_intr_xfer = NULL;
3930 1.1 augustss }
3931