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uhci.c revision 1.283
      1  1.283  riastrad /*	$NetBSD: uhci.c,v 1.283 2018/09/03 16:29:34 riastradh Exp $	*/
      2    1.1  augustss 
      3    1.1  augustss /*
      4  1.248       mrg  * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc.
      5    1.1  augustss  * All rights reserved.
      6    1.1  augustss  *
      7   1.11  augustss  * This code is derived from software contributed to The NetBSD Foundation
      8  1.113  augustss  * by Lennart Augustsson (lennart (at) augustsson.net) at
      9  1.248       mrg  * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca)
     10  1.248       mrg  * and Matthew R. Green (mrg (at) eterna.com.au).
     11    1.1  augustss  *
     12    1.1  augustss  * Redistribution and use in source and binary forms, with or without
     13    1.1  augustss  * modification, are permitted provided that the following conditions
     14    1.1  augustss  * are met:
     15    1.1  augustss  * 1. Redistributions of source code must retain the above copyright
     16    1.1  augustss  *    notice, this list of conditions and the following disclaimer.
     17    1.1  augustss  * 2. Redistributions in binary form must reproduce the above copyright
     18    1.1  augustss  *    notice, this list of conditions and the following disclaimer in the
     19    1.1  augustss  *    documentation and/or other materials provided with the distribution.
     20    1.1  augustss  *
     21    1.1  augustss  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     22    1.1  augustss  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     23    1.1  augustss  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     24    1.1  augustss  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     25    1.1  augustss  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     26    1.1  augustss  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     27    1.1  augustss  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     28    1.1  augustss  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     29    1.1  augustss  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     30    1.1  augustss  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     31    1.1  augustss  * POSSIBILITY OF SUCH DAMAGE.
     32    1.1  augustss  */
     33    1.1  augustss 
     34    1.1  augustss /*
     35    1.1  augustss  * USB Universal Host Controller driver.
     36   1.28  augustss  * Handles e.g. PIIX3 and PIIX4.
     37    1.1  augustss  *
     38  1.229  uebayasi  * UHCI spec: http://www.intel.com/technology/usb/spec.htm
     39  1.229  uebayasi  * USB spec: http://www.usb.org/developers/docs/
     40   1.71  augustss  * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf
     41   1.71  augustss  *             ftp://download.intel.com/design/intarch/datashts/29056201.pdf
     42    1.1  augustss  */
     43  1.143     lukem 
     44  1.143     lukem #include <sys/cdefs.h>
     45  1.283  riastrad __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.283 2018/09/03 16:29:34 riastradh Exp $");
     46  1.268     skrll 
     47  1.273     pooka #ifdef _KERNEL_OPT
     48  1.268     skrll #include "opt_usb.h"
     49  1.273     pooka #endif
     50    1.1  augustss 
     51    1.1  augustss #include <sys/param.h>
     52  1.268     skrll 
     53  1.268     skrll #include <sys/bus.h>
     54  1.268     skrll #include <sys/cpu.h>
     55  1.268     skrll #include <sys/device.h>
     56    1.1  augustss #include <sys/kernel.h>
     57  1.248       mrg #include <sys/kmem.h>
     58  1.268     skrll #include <sys/mutex.h>
     59    1.1  augustss #include <sys/proc.h>
     60    1.1  augustss #include <sys/queue.h>
     61  1.268     skrll #include <sys/select.h>
     62  1.268     skrll #include <sys/sysctl.h>
     63  1.268     skrll #include <sys/systm.h>
     64    1.1  augustss 
     65   1.39  augustss #include <machine/endian.h>
     66    1.7  augustss 
     67    1.1  augustss #include <dev/usb/usb.h>
     68    1.1  augustss #include <dev/usb/usbdi.h>
     69    1.1  augustss #include <dev/usb/usbdivar.h>
     70    1.7  augustss #include <dev/usb/usb_mem.h>
     71    1.1  augustss 
     72    1.1  augustss #include <dev/usb/uhcireg.h>
     73    1.1  augustss #include <dev/usb/uhcivar.h>
     74  1.268     skrll #include <dev/usb/usbroothub.h>
     75  1.268     skrll #include <dev/usb/usbhist.h>
     76    1.1  augustss 
     77  1.125  augustss /* Use bandwidth reclamation for control transfers. Some devices choke on it. */
     78  1.125  augustss /*#define UHCI_CTL_LOOP */
     79  1.125  augustss 
     80   1.67  augustss #ifdef UHCI_DEBUG
     81   1.92  augustss uhci_softc_t *thesc;
     82  1.125  augustss int uhcinoloop = 0;
     83  1.268     skrll #endif
     84  1.268     skrll 
     85  1.268     skrll #ifdef USB_DEBUG
     86  1.268     skrll #ifndef UHCI_DEBUG
     87  1.268     skrll #define uhcidebug 0
     88   1.59  augustss #else
     89  1.268     skrll static int uhcidebug = 0;
     90  1.268     skrll 
     91  1.268     skrll SYSCTL_SETUP(sysctl_hw_uhci_setup, "sysctl hw.uhci setup")
     92  1.268     skrll {
     93  1.268     skrll 	int err;
     94  1.268     skrll 	const struct sysctlnode *rnode;
     95  1.268     skrll 	const struct sysctlnode *cnode;
     96  1.268     skrll 
     97  1.268     skrll 	err = sysctl_createv(clog, 0, NULL, &rnode,
     98  1.268     skrll 	    CTLFLAG_PERMANENT, CTLTYPE_NODE, "uhci",
     99  1.268     skrll 	    SYSCTL_DESCR("uhci global controls"),
    100  1.268     skrll 	    NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
    101  1.268     skrll 
    102  1.268     skrll 	if (err)
    103  1.268     skrll 		goto fail;
    104  1.268     skrll 
    105  1.268     skrll 	/* control debugging printfs */
    106  1.268     skrll 	err = sysctl_createv(clog, 0, &rnode, &cnode,
    107  1.268     skrll 	    CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
    108  1.268     skrll 	    "debug", SYSCTL_DESCR("Enable debugging output"),
    109  1.268     skrll 	    NULL, 0, &uhcidebug, sizeof(uhcidebug), CTL_CREATE, CTL_EOL);
    110  1.268     skrll 	if (err)
    111  1.268     skrll 		goto fail;
    112  1.268     skrll 
    113  1.268     skrll 	return;
    114  1.268     skrll fail:
    115  1.268     skrll 	aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err);
    116  1.268     skrll }
    117  1.268     skrll 
    118  1.268     skrll #endif /* UHCI_DEBUG */
    119  1.268     skrll #endif /* USB_DEBUG */
    120  1.268     skrll 
    121  1.268     skrll #define	DPRINTF(FMT,A,B,C,D)	USBHIST_LOGN(uhcidebug,1,FMT,A,B,C,D)
    122  1.268     skrll #define	DPRINTFN(N,FMT,A,B,C,D)	USBHIST_LOGN(uhcidebug,N,FMT,A,B,C,D)
    123  1.268     skrll #define	UHCIHIST_FUNC()		USBHIST_FUNC()
    124  1.268     skrll #define	UHCIHIST_CALLED(name)	USBHIST_CALLED(uhcidebug)
    125   1.59  augustss 
    126   1.39  augustss /*
    127   1.39  augustss  * The UHCI controller is little endian, so on big endian machines
    128  1.181  drochner  * the data stored in memory needs to be swapped.
    129   1.39  augustss  */
    130   1.39  augustss 
    131    1.1  augustss struct uhci_pipe {
    132    1.1  augustss 	struct usbd_pipe pipe;
    133   1.32  augustss 	int nexttoggle;
    134   1.92  augustss 
    135   1.92  augustss 	u_char aborting;
    136  1.268     skrll 	struct usbd_xfer *abortstart, abortend;
    137   1.92  augustss 
    138    1.1  augustss 	/* Info needed for different pipe kinds. */
    139    1.1  augustss 	union {
    140    1.1  augustss 		/* Control pipe */
    141    1.1  augustss 		struct {
    142    1.1  augustss 			uhci_soft_qh_t *sqh;
    143    1.7  augustss 			usb_dma_t reqdma;
    144  1.268     skrll 			uhci_soft_td_t *setup;
    145  1.268     skrll 			uhci_soft_td_t *stat;
    146  1.268     skrll 		} ctrl;
    147    1.1  augustss 		/* Interrupt pipe */
    148    1.1  augustss 		struct {
    149    1.1  augustss 			int npoll;
    150    1.1  augustss 			uhci_soft_qh_t **qhs;
    151    1.1  augustss 		} intr;
    152    1.1  augustss 		/* Bulk pipe */
    153    1.1  augustss 		struct {
    154    1.1  augustss 			uhci_soft_qh_t *sqh;
    155    1.1  augustss 		} bulk;
    156  1.268     skrll 		/* Isochronous pipe */
    157  1.268     skrll 		struct isoc {
    158   1.16  augustss 			uhci_soft_td_t **stds;
    159   1.48  augustss 			int next, inuse;
    160  1.268     skrll 		} isoc;
    161  1.268     skrll 	};
    162    1.1  augustss };
    163    1.1  augustss 
    164  1.268     skrll typedef TAILQ_HEAD(ux_completeq, uhci_xfer) ux_completeq_t;
    165  1.268     skrll 
    166  1.142  augustss Static void		uhci_globalreset(uhci_softc_t *);
    167  1.166   dsainty Static usbd_status	uhci_portreset(uhci_softc_t*, int);
    168  1.142  augustss Static void		uhci_reset(uhci_softc_t *);
    169  1.268     skrll Static usbd_status	uhci_run(uhci_softc_t *, int, int);
    170  1.123  augustss Static uhci_soft_td_t  *uhci_alloc_std(uhci_softc_t *);
    171  1.119  augustss Static void		uhci_free_std(uhci_softc_t *, uhci_soft_td_t *);
    172  1.268     skrll Static void		uhci_free_std_locked(uhci_softc_t *, uhci_soft_td_t *);
    173  1.123  augustss Static uhci_soft_qh_t  *uhci_alloc_sqh(uhci_softc_t *);
    174  1.119  augustss Static void		uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *);
    175   1.16  augustss #if 0
    176  1.119  augustss Static void		uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *,
    177  1.268     skrll 			    uhci_intr_info_t *);
    178  1.119  augustss Static void		uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *);
    179   1.16  augustss #endif
    180    1.1  augustss 
    181  1.268     skrll #if 0
    182  1.268     skrll Static void		uhci_free_std_chain(uhci_softc_t *, uhci_soft_td_t *,
    183  1.268     skrll 			    uhci_soft_td_t *);
    184  1.268     skrll #endif
    185  1.268     skrll Static int		uhci_alloc_std_chain(uhci_softc_t *, struct usbd_xfer *,
    186  1.268     skrll 			    int, int, uhci_soft_td_t **);
    187  1.268     skrll Static void		uhci_free_stds(uhci_softc_t *, struct uhci_xfer *);
    188  1.268     skrll 
    189  1.268     skrll Static void		uhci_reset_std_chain(uhci_softc_t *, struct usbd_xfer *,
    190  1.268     skrll 			    int, int, int *, uhci_soft_td_t **);
    191  1.268     skrll 
    192  1.119  augustss Static void		uhci_poll_hub(void *);
    193  1.268     skrll Static void		uhci_check_intr(uhci_softc_t *, struct uhci_xfer *,
    194  1.268     skrll 			    ux_completeq_t *);
    195  1.268     skrll Static void		uhci_idone(struct uhci_xfer *, ux_completeq_t *);
    196  1.119  augustss 
    197  1.268     skrll Static void		uhci_abort_xfer(struct usbd_xfer *, usbd_status);
    198  1.119  augustss 
    199  1.119  augustss Static void		uhci_timeout(void *);
    200  1.153  augustss Static void		uhci_timeout_task(void *);
    201  1.123  augustss Static void		uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *);
    202  1.123  augustss Static void		uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *);
    203  1.119  augustss Static void		uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *);
    204  1.123  augustss Static void		uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *);
    205  1.123  augustss Static void		uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *);
    206  1.119  augustss Static void		uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *);
    207  1.268     skrll Static void		uhci_add_loop(uhci_softc_t *);
    208  1.268     skrll Static void		uhci_rem_loop(uhci_softc_t *);
    209  1.119  augustss 
    210  1.268     skrll Static usbd_status	uhci_setup_isoc(struct usbd_pipe *);
    211  1.119  augustss 
    212  1.268     skrll Static struct usbd_xfer *
    213  1.268     skrll 			uhci_allocx(struct usbd_bus *, unsigned int);
    214  1.268     skrll Static void		uhci_freex(struct usbd_bus *, struct usbd_xfer *);
    215  1.248       mrg Static void		uhci_get_lock(struct usbd_bus *, kmutex_t **);
    216  1.268     skrll Static int		uhci_roothub_ctrl(struct usbd_bus *,
    217  1.268     skrll 			    usb_device_request_t *, void *, int);
    218  1.119  augustss 
    219  1.268     skrll Static int		uhci_device_ctrl_init(struct usbd_xfer *);
    220  1.268     skrll Static void		uhci_device_ctrl_fini(struct usbd_xfer *);
    221  1.268     skrll Static usbd_status	uhci_device_ctrl_transfer(struct usbd_xfer *);
    222  1.268     skrll Static usbd_status	uhci_device_ctrl_start(struct usbd_xfer *);
    223  1.268     skrll Static void		uhci_device_ctrl_abort(struct usbd_xfer *);
    224  1.268     skrll Static void		uhci_device_ctrl_close(struct usbd_pipe *);
    225  1.268     skrll Static void		uhci_device_ctrl_done(struct usbd_xfer *);
    226  1.268     skrll 
    227  1.268     skrll Static int		uhci_device_intr_init(struct usbd_xfer *);
    228  1.268     skrll Static void		uhci_device_intr_fini(struct usbd_xfer *);
    229  1.268     skrll Static usbd_status	uhci_device_intr_transfer(struct usbd_xfer *);
    230  1.268     skrll Static usbd_status	uhci_device_intr_start(struct usbd_xfer *);
    231  1.268     skrll Static void		uhci_device_intr_abort(struct usbd_xfer *);
    232  1.268     skrll Static void		uhci_device_intr_close(struct usbd_pipe *);
    233  1.268     skrll Static void		uhci_device_intr_done(struct usbd_xfer *);
    234  1.268     skrll 
    235  1.268     skrll Static int		uhci_device_bulk_init(struct usbd_xfer *);
    236  1.268     skrll Static void		uhci_device_bulk_fini(struct usbd_xfer *);
    237  1.268     skrll Static usbd_status	uhci_device_bulk_transfer(struct usbd_xfer *);
    238  1.268     skrll Static usbd_status	uhci_device_bulk_start(struct usbd_xfer *);
    239  1.268     skrll Static void		uhci_device_bulk_abort(struct usbd_xfer *);
    240  1.268     skrll Static void		uhci_device_bulk_close(struct usbd_pipe *);
    241  1.268     skrll Static void		uhci_device_bulk_done(struct usbd_xfer *);
    242  1.268     skrll 
    243  1.268     skrll Static int		uhci_device_isoc_init(struct usbd_xfer *);
    244  1.268     skrll Static void		uhci_device_isoc_fini(struct usbd_xfer *);
    245  1.268     skrll Static usbd_status	uhci_device_isoc_transfer(struct usbd_xfer *);
    246  1.268     skrll Static void		uhci_device_isoc_abort(struct usbd_xfer *);
    247  1.268     skrll Static void		uhci_device_isoc_close(struct usbd_pipe *);
    248  1.268     skrll Static void		uhci_device_isoc_done(struct usbd_xfer *);
    249  1.268     skrll 
    250  1.268     skrll Static usbd_status	uhci_root_intr_transfer(struct usbd_xfer *);
    251  1.268     skrll Static usbd_status	uhci_root_intr_start(struct usbd_xfer *);
    252  1.268     skrll Static void		uhci_root_intr_abort(struct usbd_xfer *);
    253  1.268     skrll Static void		uhci_root_intr_close(struct usbd_pipe *);
    254  1.268     skrll Static void		uhci_root_intr_done(struct usbd_xfer *);
    255  1.119  augustss 
    256  1.268     skrll Static usbd_status	uhci_open(struct usbd_pipe *);
    257  1.119  augustss Static void		uhci_poll(struct usbd_bus *);
    258  1.133  augustss Static void		uhci_softintr(void *);
    259  1.119  augustss 
    260  1.119  augustss Static void		uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *);
    261  1.158  augustss Static void		uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *);
    262  1.268     skrll Static usbd_status	uhci_device_setintr(uhci_softc_t *,
    263  1.268     skrll 			    struct uhci_pipe *, int);
    264  1.119  augustss 
    265  1.268     skrll Static void		uhci_device_clear_toggle(struct usbd_pipe *);
    266  1.268     skrll Static void		uhci_noop(struct usbd_pipe *);
    267  1.119  augustss 
    268  1.268     skrll static inline uhci_soft_qh_t *
    269  1.268     skrll 			uhci_find_prev_qh(uhci_soft_qh_t *, uhci_soft_qh_t *);
    270  1.119  augustss 
    271  1.119  augustss #ifdef UHCI_DEBUG
    272  1.119  augustss Static void		uhci_dump_all(uhci_softc_t *);
    273  1.119  augustss Static void		uhci_dumpregs(uhci_softc_t *);
    274  1.119  augustss Static void		uhci_dump_qhs(uhci_soft_qh_t *);
    275  1.119  augustss Static void		uhci_dump_qh(uhci_soft_qh_t *);
    276  1.119  augustss Static void		uhci_dump_tds(uhci_soft_td_t *);
    277  1.119  augustss Static void		uhci_dump_td(uhci_soft_td_t *);
    278  1.268     skrll Static void		uhci_dump_ii(struct uhci_xfer *);
    279  1.119  augustss void			uhci_dump(void);
    280    1.1  augustss #endif
    281    1.1  augustss 
    282  1.112  augustss #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \
    283  1.112  augustss 			BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
    284  1.112  augustss #define UWRITE1(sc, r, x) \
    285  1.165   dsainty  do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \
    286  1.165   dsainty  } while (/*CONSTCOND*/0)
    287  1.112  augustss #define UWRITE2(sc, r, x) \
    288  1.165   dsainty  do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \
    289  1.165   dsainty  } while (/*CONSTCOND*/0)
    290  1.112  augustss #define UWRITE4(sc, r, x) \
    291  1.165   dsainty  do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \
    292  1.165   dsainty  } while (/*CONSTCOND*/0)
    293  1.268     skrll 
    294  1.196       mrg static __inline uint8_t
    295  1.196       mrg UREAD1(uhci_softc_t *sc, bus_size_t r)
    296  1.196       mrg {
    297  1.196       mrg 
    298  1.196       mrg 	UBARR(sc);
    299  1.196       mrg 	return bus_space_read_1(sc->iot, sc->ioh, r);
    300  1.196       mrg }
    301  1.196       mrg 
    302  1.196       mrg static __inline uint16_t
    303  1.196       mrg UREAD2(uhci_softc_t *sc, bus_size_t r)
    304  1.196       mrg {
    305  1.196       mrg 
    306  1.196       mrg 	UBARR(sc);
    307  1.196       mrg 	return bus_space_read_2(sc->iot, sc->ioh, r);
    308  1.196       mrg }
    309  1.196       mrg 
    310  1.260     joerg #ifdef UHCI_DEBUG
    311  1.196       mrg static __inline uint32_t
    312  1.196       mrg UREAD4(uhci_softc_t *sc, bus_size_t r)
    313  1.196       mrg {
    314  1.196       mrg 
    315  1.196       mrg 	UBARR(sc);
    316  1.196       mrg 	return bus_space_read_4(sc->iot, sc->ioh, r);
    317  1.196       mrg }
    318  1.260     joerg #endif
    319    1.1  augustss 
    320    1.1  augustss #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd)
    321    1.1  augustss #define UHCISTS(sc) UREAD2(sc, UHCI_STS)
    322    1.1  augustss 
    323  1.142  augustss #define UHCI_RESET_TIMEOUT 100	/* ms, reset timeout */
    324    1.1  augustss 
    325    1.1  augustss #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK)
    326    1.1  augustss 
    327  1.208  drochner const struct usbd_bus_methods uhci_bus_methods = {
    328  1.268     skrll 	.ubm_open =	uhci_open,
    329  1.268     skrll 	.ubm_softint =	uhci_softintr,
    330  1.268     skrll 	.ubm_dopoll =	uhci_poll,
    331  1.268     skrll 	.ubm_allocx =	uhci_allocx,
    332  1.268     skrll 	.ubm_freex =	uhci_freex,
    333  1.268     skrll 	.ubm_getlock =	uhci_get_lock,
    334  1.268     skrll 	.ubm_rhctrl =	uhci_roothub_ctrl,
    335    1.1  augustss };
    336    1.1  augustss 
    337  1.208  drochner const struct usbd_pipe_methods uhci_root_intr_methods = {
    338  1.268     skrll 	.upm_transfer =	uhci_root_intr_transfer,
    339  1.268     skrll 	.upm_start =	uhci_root_intr_start,
    340  1.268     skrll 	.upm_abort =	uhci_root_intr_abort,
    341  1.268     skrll 	.upm_close =	uhci_root_intr_close,
    342  1.268     skrll 	.upm_cleartoggle =	uhci_noop,
    343  1.268     skrll 	.upm_done =	uhci_root_intr_done,
    344    1.1  augustss };
    345    1.1  augustss 
    346  1.208  drochner const struct usbd_pipe_methods uhci_device_ctrl_methods = {
    347  1.268     skrll 	.upm_init =	uhci_device_ctrl_init,
    348  1.268     skrll 	.upm_fini =	uhci_device_ctrl_fini,
    349  1.268     skrll 	.upm_transfer =	uhci_device_ctrl_transfer,
    350  1.268     skrll 	.upm_start =	uhci_device_ctrl_start,
    351  1.268     skrll 	.upm_abort =	uhci_device_ctrl_abort,
    352  1.268     skrll 	.upm_close =	uhci_device_ctrl_close,
    353  1.268     skrll 	.upm_cleartoggle =	uhci_noop,
    354  1.268     skrll 	.upm_done =	uhci_device_ctrl_done,
    355    1.1  augustss };
    356    1.1  augustss 
    357  1.208  drochner const struct usbd_pipe_methods uhci_device_intr_methods = {
    358  1.268     skrll 	.upm_init =	uhci_device_intr_init,
    359  1.268     skrll 	.upm_fini =	uhci_device_intr_fini,
    360  1.268     skrll 	.upm_transfer =	uhci_device_intr_transfer,
    361  1.268     skrll 	.upm_start =	uhci_device_intr_start,
    362  1.268     skrll 	.upm_abort =	uhci_device_intr_abort,
    363  1.268     skrll 	.upm_close =	uhci_device_intr_close,
    364  1.268     skrll 	.upm_cleartoggle =	uhci_device_clear_toggle,
    365  1.268     skrll 	.upm_done =	uhci_device_intr_done,
    366    1.1  augustss };
    367    1.1  augustss 
    368  1.208  drochner const struct usbd_pipe_methods uhci_device_bulk_methods = {
    369  1.268     skrll 	.upm_init =	uhci_device_bulk_init,
    370  1.268     skrll 	.upm_fini =	uhci_device_bulk_fini,
    371  1.268     skrll 	.upm_transfer =	uhci_device_bulk_transfer,
    372  1.268     skrll 	.upm_start =	uhci_device_bulk_start,
    373  1.268     skrll 	.upm_abort =	uhci_device_bulk_abort,
    374  1.268     skrll 	.upm_close =	uhci_device_bulk_close,
    375  1.268     skrll 	.upm_cleartoggle =	uhci_device_clear_toggle,
    376  1.268     skrll 	.upm_done =	uhci_device_bulk_done,
    377    1.1  augustss };
    378    1.1  augustss 
    379  1.208  drochner const struct usbd_pipe_methods uhci_device_isoc_methods = {
    380  1.268     skrll 	.upm_init =	uhci_device_isoc_init,
    381  1.268     skrll 	.upm_fini =	uhci_device_isoc_fini,
    382  1.268     skrll 	.upm_transfer =	uhci_device_isoc_transfer,
    383  1.268     skrll 	.upm_abort =	uhci_device_isoc_abort,
    384  1.268     skrll 	.upm_close =	uhci_device_isoc_close,
    385  1.268     skrll 	.upm_cleartoggle =	uhci_noop,
    386  1.268     skrll 	.upm_done =	uhci_device_isoc_done,
    387   1.16  augustss };
    388   1.16  augustss 
    389  1.268     skrll static inline void
    390  1.268     skrll uhci_add_intr_list(uhci_softc_t *sc, struct uhci_xfer *ux)
    391  1.268     skrll {
    392  1.268     skrll 
    393  1.268     skrll 	TAILQ_INSERT_TAIL(&sc->sc_intrhead, ux, ux_list);
    394  1.268     skrll }
    395  1.268     skrll 
    396  1.268     skrll static inline void
    397  1.268     skrll uhci_del_intr_list(uhci_softc_t *sc, struct uhci_xfer *ux)
    398  1.268     skrll {
    399  1.268     skrll 
    400  1.268     skrll 	TAILQ_REMOVE(&sc->sc_intrhead, ux, ux_list);
    401  1.268     skrll }
    402   1.92  augustss 
    403  1.240  jakllsch static inline uhci_soft_qh_t *
    404  1.119  augustss uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh)
    405   1.92  augustss {
    406  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
    407  1.277  pgoyette 	DPRINTFN(15, "pqh=%#jx sqh=%#jx", (uintptr_t)pqh, (uintptr_t)sqh, 0, 0);
    408   1.92  augustss 
    409   1.92  augustss 	for (; pqh->hlink != sqh; pqh = pqh->hlink) {
    410  1.152  augustss #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG)
    411  1.223    bouyer 		usb_syncmem(&pqh->dma,
    412  1.223    bouyer 		    pqh->offs + offsetof(uhci_qh_t, qh_hlink),
    413  1.223    bouyer 		    sizeof(pqh->qh.qh_hlink),
    414  1.223    bouyer 		    BUS_DMASYNC_POSTWRITE);
    415   1.92  augustss 		if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) {
    416  1.268     skrll 			printf("%s: QH not found\n", __func__);
    417  1.268     skrll 			return NULL;
    418   1.92  augustss 		}
    419   1.92  augustss #endif
    420   1.92  augustss 	}
    421  1.268     skrll 	return pqh;
    422   1.92  augustss }
    423   1.92  augustss 
    424    1.1  augustss void
    425  1.142  augustss uhci_globalreset(uhci_softc_t *sc)
    426    1.1  augustss {
    427    1.1  augustss 	UHCICMD(sc, UHCI_CMD_GRESET);	/* global reset */
    428   1.20  augustss 	usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */
    429    1.1  augustss 	UHCICMD(sc, 0);			/* do nothing */
    430    1.1  augustss }
    431    1.1  augustss 
    432  1.268     skrll int
    433  1.119  augustss uhci_init(uhci_softc_t *sc)
    434    1.1  augustss {
    435   1.63  augustss 	usbd_status err;
    436    1.1  augustss 	int i, j;
    437  1.123  augustss 	uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh;
    438    1.1  augustss 	uhci_soft_td_t *std;
    439    1.1  augustss 
    440  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
    441    1.1  augustss 
    442   1.67  augustss #ifdef UHCI_DEBUG
    443   1.92  augustss 	thesc = sc;
    444   1.92  augustss 
    445  1.268     skrll 	if (uhcidebug >= 2)
    446    1.1  augustss 		uhci_dumpregs(sc);
    447    1.1  augustss #endif
    448    1.1  augustss 
    449  1.219  jmcneill 	sc->sc_suspend = PWR_RESUME;
    450  1.219  jmcneill 
    451    1.1  augustss 	UWRITE2(sc, UHCI_INTR, 0);		/* disable interrupts */
    452  1.142  augustss 	uhci_globalreset(sc);			/* reset the controller */
    453  1.142  augustss 	uhci_reset(sc);
    454   1.24  augustss 
    455    1.1  augustss 	/* Allocate and initialize real frame array. */
    456  1.152  augustss 	err = usb_allocmem(&sc->sc_bus,
    457  1.268     skrll 	    UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t),
    458  1.268     skrll 	    UHCI_FRAMELIST_ALIGN, &sc->sc_dma);
    459   1.63  augustss 	if (err)
    460  1.268     skrll 		return err;
    461  1.159  augustss 	sc->sc_pframes = KERNADDR(&sc->sc_dma, 0);
    462    1.1  augustss 	UWRITE2(sc, UHCI_FRNUM, 0);		/* set frame number to 0 */
    463  1.160  augustss 	UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/
    464    1.1  augustss 
    465  1.268     skrll 	/* Initialise mutex early for uhci_alloc_* */
    466  1.268     skrll 	mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
    467  1.268     skrll 	mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB);
    468  1.268     skrll 
    469  1.152  augustss 	/*
    470  1.123  augustss 	 * Allocate a TD, inactive, that hangs from the last QH.
    471  1.123  augustss 	 * This is to avoid a bug in the PIIX that makes it run berserk
    472  1.123  augustss 	 * otherwise.
    473  1.123  augustss 	 */
    474  1.123  augustss 	std = uhci_alloc_std(sc);
    475  1.123  augustss 	if (std == NULL)
    476  1.268     skrll 		return ENOMEM;
    477  1.123  augustss 	std->link.std = NULL;
    478  1.123  augustss 	std->td.td_link = htole32(UHCI_PTR_T);
    479  1.123  augustss 	std->td.td_status = htole32(0); /* inactive */
    480  1.123  augustss 	std->td.td_token = htole32(0);
    481  1.123  augustss 	std->td.td_buffer = htole32(0);
    482  1.223    bouyer 	usb_syncmem(&std->dma, std->offs, sizeof(std->td),
    483  1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
    484  1.123  augustss 
    485  1.123  augustss 	/* Allocate the dummy QH marking the end and used for looping the QHs.*/
    486  1.123  augustss 	lsqh = uhci_alloc_sqh(sc);
    487  1.123  augustss 	if (lsqh == NULL)
    488  1.268     skrll 		goto fail1;
    489  1.123  augustss 	lsqh->hlink = NULL;
    490  1.123  augustss 	lsqh->qh.qh_hlink = htole32(UHCI_PTR_T);	/* end of QH chain */
    491  1.123  augustss 	lsqh->elink = std;
    492  1.123  augustss 	lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD);
    493  1.123  augustss 	sc->sc_last_qh = lsqh;
    494  1.223    bouyer 	usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh),
    495  1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
    496  1.123  augustss 
    497    1.1  augustss 	/* Allocate the dummy QH where bulk traffic will be queued. */
    498    1.1  augustss 	bsqh = uhci_alloc_sqh(sc);
    499   1.63  augustss 	if (bsqh == NULL)
    500  1.268     skrll 		goto fail2;
    501  1.123  augustss 	bsqh->hlink = lsqh;
    502  1.123  augustss 	bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH);
    503  1.121  augustss 	bsqh->elink = NULL;
    504   1.88   tsutsui 	bsqh->qh.qh_elink = htole32(UHCI_PTR_T);
    505    1.1  augustss 	sc->sc_bulk_start = sc->sc_bulk_end = bsqh;
    506  1.223    bouyer 	usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh),
    507  1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
    508    1.1  augustss 
    509  1.123  augustss 	/* Allocate dummy QH where high speed control traffic will be queued. */
    510  1.123  augustss 	chsqh = uhci_alloc_sqh(sc);
    511  1.123  augustss 	if (chsqh == NULL)
    512  1.268     skrll 		goto fail3;
    513  1.123  augustss 	chsqh->hlink = bsqh;
    514  1.123  augustss 	chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH);
    515  1.123  augustss 	chsqh->elink = NULL;
    516  1.123  augustss 	chsqh->qh.qh_elink = htole32(UHCI_PTR_T);
    517  1.123  augustss 	sc->sc_hctl_start = sc->sc_hctl_end = chsqh;
    518  1.223    bouyer 	usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh),
    519  1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
    520  1.123  augustss 
    521  1.123  augustss 	/* Allocate dummy QH where control traffic will be queued. */
    522  1.123  augustss 	clsqh = uhci_alloc_sqh(sc);
    523  1.123  augustss 	if (clsqh == NULL)
    524  1.268     skrll 		goto fail4;
    525  1.220    bouyer 	clsqh->hlink = chsqh;
    526  1.123  augustss 	clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH);
    527  1.123  augustss 	clsqh->elink = NULL;
    528  1.123  augustss 	clsqh->qh.qh_elink = htole32(UHCI_PTR_T);
    529  1.123  augustss 	sc->sc_lctl_start = sc->sc_lctl_end = clsqh;
    530  1.223    bouyer 	usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh),
    531  1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
    532    1.1  augustss 
    533  1.152  augustss 	/*
    534    1.1  augustss 	 * Make all (virtual) frame list pointers point to the interrupt
    535    1.1  augustss 	 * queue heads and the interrupt queue heads at the control
    536    1.1  augustss 	 * queue head and point the physical frame list to the virtual.
    537    1.1  augustss 	 */
    538  1.267     skrll 	for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
    539    1.1  augustss 		std = uhci_alloc_std(sc);
    540    1.1  augustss 		sqh = uhci_alloc_sqh(sc);
    541   1.67  augustss 		if (std == NULL || sqh == NULL)
    542  1.268     skrll 			return USBD_NOMEM;
    543   1.42  augustss 		std->link.sqh = sqh;
    544  1.121  augustss 		std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH);
    545   1.88   tsutsui 		std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */
    546   1.88   tsutsui 		std->td.td_token = htole32(0);
    547   1.88   tsutsui 		std->td.td_buffer = htole32(0);
    548  1.223    bouyer 		usb_syncmem(&std->dma, std->offs, sizeof(std->td),
    549  1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
    550  1.123  augustss 		sqh->hlink = clsqh;
    551  1.123  augustss 		sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH);
    552  1.121  augustss 		sqh->elink = NULL;
    553   1.88   tsutsui 		sqh->qh.qh_elink = htole32(UHCI_PTR_T);
    554  1.223    bouyer 		usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
    555  1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
    556    1.1  augustss 		sc->sc_vframes[i].htd = std;
    557    1.1  augustss 		sc->sc_vframes[i].etd = std;
    558    1.1  augustss 		sc->sc_vframes[i].hqh = sqh;
    559    1.1  augustss 		sc->sc_vframes[i].eqh = sqh;
    560  1.152  augustss 		for (j = i;
    561  1.152  augustss 		     j < UHCI_FRAMELIST_COUNT;
    562    1.1  augustss 		     j += UHCI_VFRAMELIST_COUNT)
    563   1.88   tsutsui 			sc->sc_pframes[j] = htole32(std->physaddr);
    564    1.1  augustss 	}
    565  1.223    bouyer 	usb_syncmem(&sc->sc_dma, 0,
    566  1.223    bouyer 	    UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t),
    567  1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
    568  1.223    bouyer 
    569    1.1  augustss 
    570  1.268     skrll 	TAILQ_INIT(&sc->sc_intrhead);
    571    1.1  augustss 
    572  1.253  christos 	sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0,
    573  1.253  christos 	    "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL);
    574   1.76  augustss 
    575  1.248       mrg 	callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE);
    576  1.248       mrg 
    577    1.1  augustss 	/* Set up the bus struct. */
    578  1.268     skrll 	sc->sc_bus.ub_methods = &uhci_bus_methods;
    579  1.268     skrll 	sc->sc_bus.ub_pipesize = sizeof(struct uhci_pipe);
    580  1.268     skrll 	sc->sc_bus.ub_usedma = true;
    581    1.1  augustss 
    582  1.190  augustss 	UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */
    583  1.190  augustss 
    584  1.268     skrll 	DPRINTF("Enabling...", 0, 0, 0, 0);
    585  1.225    bouyer 
    586  1.268     skrll 	err = uhci_run(sc, 1, 0);		/* and here we go... */
    587  1.152  augustss 	UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE |
    588    1.1  augustss 		UHCI_INTR_IOCE | UHCI_INTR_SPIE);	/* enable interrupts */
    589  1.225    bouyer 	return err;
    590  1.268     skrll 
    591  1.268     skrll fail4:
    592  1.268     skrll 	uhci_free_sqh(sc, chsqh);
    593  1.268     skrll fail3:
    594  1.268     skrll 	uhci_free_sqh(sc, lsqh);
    595  1.268     skrll fail2:
    596  1.268     skrll 	uhci_free_sqh(sc, lsqh);
    597  1.268     skrll fail1:
    598  1.268     skrll 	uhci_free_std(sc, std);
    599  1.268     skrll 
    600  1.268     skrll 	return ENOMEM;
    601   1.53  augustss }
    602   1.53  augustss 
    603   1.53  augustss int
    604  1.215    dyoung uhci_activate(device_t self, enum devact act)
    605   1.53  augustss {
    606  1.215    dyoung 	struct uhci_softc *sc = device_private(self);
    607   1.53  augustss 
    608   1.53  augustss 	switch (act) {
    609   1.53  augustss 	case DVACT_DEACTIVATE:
    610  1.210  kiyohara 		sc->sc_dying = 1;
    611  1.230    dyoung 		return 0;
    612  1.230    dyoung 	default:
    613  1.230    dyoung 		return EOPNOTSUPP;
    614   1.53  augustss 	}
    615   1.53  augustss }
    616   1.53  augustss 
    617  1.215    dyoung void
    618  1.215    dyoung uhci_childdet(device_t self, device_t child)
    619  1.215    dyoung {
    620  1.215    dyoung 	struct uhci_softc *sc = device_private(self);
    621  1.215    dyoung 
    622  1.215    dyoung 	KASSERT(sc->sc_child == child);
    623  1.215    dyoung 	sc->sc_child = NULL;
    624  1.215    dyoung }
    625  1.215    dyoung 
    626   1.53  augustss int
    627  1.119  augustss uhci_detach(struct uhci_softc *sc, int flags)
    628   1.53  augustss {
    629   1.53  augustss 	int rv = 0;
    630   1.53  augustss 
    631   1.53  augustss 	if (sc->sc_child != NULL)
    632   1.53  augustss 		rv = config_detach(sc->sc_child, flags);
    633  1.152  augustss 
    634   1.53  augustss 	if (rv != 0)
    635  1.268     skrll 		return rv;
    636   1.53  augustss 
    637  1.226        ad 	callout_halt(&sc->sc_poll_handle, NULL);
    638  1.226        ad 	callout_destroy(&sc->sc_poll_handle);
    639  1.226        ad 
    640  1.248       mrg 	mutex_destroy(&sc->sc_lock);
    641  1.248       mrg 	mutex_destroy(&sc->sc_intr_lock);
    642  1.248       mrg 
    643  1.254  christos 	pool_cache_destroy(sc->sc_xferpool);
    644  1.254  christos 
    645   1.76  augustss 	/* XXX free other data structures XXX */
    646   1.53  augustss 
    647  1.268     skrll 	return rv;
    648   1.76  augustss }
    649   1.76  augustss 
    650  1.268     skrll struct usbd_xfer *
    651  1.268     skrll uhci_allocx(struct usbd_bus *bus, unsigned int nframes)
    652   1.76  augustss {
    653  1.268     skrll 	struct uhci_softc *sc = UHCI_BUS2SC(bus);
    654  1.268     skrll 	struct usbd_xfer *xfer;
    655   1.76  augustss 
    656  1.279     skrll 	xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK);
    657   1.92  augustss 	if (xfer != NULL) {
    658  1.253  christos 		memset(xfer, 0, sizeof(struct uhci_xfer));
    659  1.268     skrll 
    660  1.281       mrg 		/* Initialise this always so we can call remove on it. */
    661  1.281       mrg 		usb_init_task(&xfer->ux_aborttask, uhci_timeout_task, xfer,
    662  1.281       mrg 		    USB_TASKQ_MPSAFE);
    663   1.92  augustss #ifdef DIAGNOSTIC
    664  1.268     skrll 		struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
    665  1.268     skrll 		uxfer->ux_isdone = true;
    666  1.268     skrll 		xfer->ux_state = XFER_BUSY;
    667   1.92  augustss #endif
    668   1.92  augustss 	}
    669  1.268     skrll 	return xfer;
    670   1.76  augustss }
    671   1.76  augustss 
    672   1.76  augustss void
    673  1.268     skrll uhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer)
    674   1.76  augustss {
    675  1.268     skrll 	struct uhci_softc *sc = UHCI_BUS2SC(bus);
    676  1.268     skrll 	struct uhci_xfer *uxfer __diagused = UHCI_XFER2UXFER(xfer);
    677   1.76  augustss 
    678  1.268     skrll 	KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer,
    679  1.268     skrll 	    xfer->ux_state);
    680  1.268     skrll 	KASSERTMSG(uxfer->ux_isdone, "xfer %p not done\n", xfer);
    681   1.93  augustss #ifdef DIAGNOSTIC
    682  1.268     skrll 	xfer->ux_state = XFER_FREE;
    683   1.93  augustss #endif
    684  1.253  christos 	pool_cache_put(sc->sc_xferpool, xfer);
    685   1.48  augustss }
    686   1.48  augustss 
    687  1.248       mrg Static void
    688  1.248       mrg uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock)
    689  1.248       mrg {
    690  1.268     skrll 	struct uhci_softc *sc = UHCI_BUS2SC(bus);
    691  1.248       mrg 
    692  1.248       mrg 	*lock = &sc->sc_lock;
    693  1.248       mrg }
    694  1.248       mrg 
    695  1.248       mrg 
    696   1.72  augustss /*
    697  1.212  jmcneill  * Handle suspend/resume.
    698  1.212  jmcneill  *
    699  1.212  jmcneill  * We need to switch to polling mode here, because this routine is
    700  1.212  jmcneill  * called from an interrupt context.  This is all right since we
    701  1.212  jmcneill  * are almost suspended anyway.
    702   1.72  augustss  */
    703  1.212  jmcneill bool
    704  1.232    dyoung uhci_resume(device_t dv, const pmf_qual_t *qual)
    705   1.72  augustss {
    706  1.212  jmcneill 	uhci_softc_t *sc = device_private(dv);
    707  1.212  jmcneill 	int cmd;
    708   1.72  augustss 
    709  1.248       mrg 	mutex_spin_enter(&sc->sc_intr_lock);
    710  1.193  augustss 
    711  1.212  jmcneill 	cmd = UREAD2(sc, UHCI_CMD);
    712  1.268     skrll 	sc->sc_bus.ub_usepolling++;
    713  1.214       smb 	UWRITE2(sc, UHCI_INTR, 0);
    714  1.214       smb 	uhci_globalreset(sc);
    715  1.214       smb 	uhci_reset(sc);
    716  1.212  jmcneill 	if (cmd & UHCI_CMD_RS)
    717  1.249  drochner 		uhci_run(sc, 0, 1);
    718  1.212  jmcneill 
    719  1.212  jmcneill 	/* restore saved state */
    720  1.212  jmcneill 	UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0));
    721  1.212  jmcneill 	UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum);
    722  1.212  jmcneill 	UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof);
    723  1.212  jmcneill 
    724  1.212  jmcneill 	UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */
    725  1.248       mrg 	usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock);
    726  1.212  jmcneill 	UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */
    727  1.212  jmcneill 	UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE |
    728  1.212  jmcneill 	    UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE);
    729  1.214       smb 	UHCICMD(sc, UHCI_CMD_MAXP);
    730  1.249  drochner 	uhci_run(sc, 1, 1); /* and start traffic again */
    731  1.248       mrg 	usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock);
    732  1.268     skrll 	sc->sc_bus.ub_usepolling--;
    733  1.212  jmcneill 	if (sc->sc_intr_xfer != NULL)
    734  1.234    dyoung 		callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub,
    735  1.212  jmcneill 		    sc->sc_intr_xfer);
    736  1.212  jmcneill #ifdef UHCI_DEBUG
    737  1.268     skrll 	if (uhcidebug >= 2)
    738  1.212  jmcneill 		uhci_dumpregs(sc);
    739  1.212  jmcneill #endif
    740  1.212  jmcneill 
    741  1.219  jmcneill 	sc->sc_suspend = PWR_RESUME;
    742  1.248       mrg 	mutex_spin_exit(&sc->sc_intr_lock);
    743  1.212  jmcneill 
    744  1.212  jmcneill 	return true;
    745   1.72  augustss }
    746   1.72  augustss 
    747  1.212  jmcneill bool
    748  1.232    dyoung uhci_suspend(device_t dv, const pmf_qual_t *qual)
    749   1.30  augustss {
    750  1.212  jmcneill 	uhci_softc_t *sc = device_private(dv);
    751   1.30  augustss 	int cmd;
    752   1.30  augustss 
    753  1.248       mrg 	mutex_spin_enter(&sc->sc_intr_lock);
    754  1.212  jmcneill 
    755   1.30  augustss 	cmd = UREAD2(sc, UHCI_CMD);
    756   1.30  augustss 
    757  1.212  jmcneill #ifdef UHCI_DEBUG
    758  1.268     skrll 	if (uhcidebug >= 2)
    759  1.212  jmcneill 		uhci_dumpregs(sc);
    760  1.212  jmcneill #endif
    761  1.212  jmcneill 	if (sc->sc_intr_xfer != NULL)
    762  1.234    dyoung 		callout_stop(&sc->sc_poll_handle);
    763  1.219  jmcneill 	sc->sc_suspend = PWR_SUSPEND;
    764  1.268     skrll 	sc->sc_bus.ub_usepolling++;
    765  1.219  jmcneill 
    766  1.249  drochner 	uhci_run(sc, 0, 1); /* stop the controller */
    767  1.212  jmcneill 	cmd &= ~UHCI_CMD_RS;
    768  1.212  jmcneill 
    769  1.212  jmcneill 	/* save some state if BIOS doesn't */
    770  1.212  jmcneill 	sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM);
    771  1.212  jmcneill 	sc->sc_saved_sof = UREAD1(sc, UHCI_SOF);
    772  1.212  jmcneill 
    773  1.212  jmcneill 	UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */
    774   1.30  augustss 
    775  1.212  jmcneill 	UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */
    776  1.248       mrg 	usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock);
    777  1.268     skrll 	sc->sc_bus.ub_usepolling--;
    778   1.86  augustss 
    779  1.248       mrg 	mutex_spin_exit(&sc->sc_intr_lock);
    780  1.212  jmcneill 
    781  1.212  jmcneill 	return true;
    782   1.30  augustss }
    783   1.30  augustss 
    784   1.59  augustss #ifdef UHCI_DEBUG
    785  1.101  augustss Static void
    786  1.119  augustss uhci_dumpregs(uhci_softc_t *sc)
    787    1.1  augustss {
    788  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
    789  1.277  pgoyette 	DPRINTF("cmd =%04jx  sts    =%04jx  intr   =%04jx  frnum =%04jx",
    790  1.268     skrll 	    UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS),
    791  1.268     skrll 	    UREAD2(sc, UHCI_INTR), UREAD2(sc, UHCI_FRNUM));
    792  1.277  pgoyette 	DPRINTF("sof =%04jx  portsc1=%04jx  portsc2=%04jx  flbase=%08jx",
    793  1.268     skrll 	    UREAD1(sc, UHCI_SOF), UREAD2(sc, UHCI_PORTSC1),
    794  1.268     skrll 	    UREAD2(sc, UHCI_PORTSC2), UREAD4(sc, UHCI_FLBASEADDR));
    795    1.1  augustss }
    796    1.1  augustss 
    797    1.1  augustss void
    798  1.119  augustss uhci_dump_td(uhci_soft_td_t *p)
    799    1.1  augustss {
    800  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
    801  1.250  christos 
    802  1.223    bouyer 	usb_syncmem(&p->dma, p->offs, sizeof(p->td),
    803  1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
    804  1.268     skrll 
    805  1.277  pgoyette 	DPRINTF("TD(%#jx) at 0x%08jx", (uintptr_t)p, p->physaddr, 0, 0);
    806  1.277  pgoyette 	DPRINTF("   link=0x%08jx status=0x%08jx "
    807  1.268     skrll 	    "token=0x%08x buffer=0x%08x",
    808  1.268     skrll 	     le32toh(p->td.td_link),
    809  1.268     skrll 	     le32toh(p->td.td_status),
    810  1.268     skrll 	     le32toh(p->td.td_token),
    811  1.268     skrll 	     le32toh(p->td.td_buffer));
    812  1.268     skrll 
    813  1.277  pgoyette 	DPRINTF("bitstuff=%jd crcto   =%jd nak     =%jd babble  =%jd",
    814  1.268     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_BITSTUFF),
    815  1.268     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_CRCTO),
    816  1.268     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_NAK),
    817  1.268     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_BABBLE));
    818  1.277  pgoyette 	DPRINTF("dbuffer =%jd stalled =%jd active  =%jd ioc     =%jd",
    819  1.268     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_DBUFFER),
    820  1.268     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_STALLED),
    821  1.268     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_ACTIVE),
    822  1.268     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_IOC));
    823  1.277  pgoyette 	DPRINTF("ios     =%jd ls      =%jd spd     =%jd",
    824  1.268     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_IOS),
    825  1.268     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_LS),
    826  1.268     skrll 	    !!(le32toh(p->td.td_status) & UHCI_TD_SPD), 0);
    827  1.268     skrll 	DPRINTF("errcnt  =%d actlen  =%d pid=%02x",
    828  1.268     skrll 	    UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)),
    829  1.268     skrll 	    UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)),
    830  1.268     skrll 	    UHCI_TD_GET_PID(le32toh(p->td.td_token)), 0);
    831  1.277  pgoyette 	DPRINTF("addr=%jd  endpt=%jd  D=%jd  maxlen=%jd,",
    832  1.268     skrll 	    UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)),
    833  1.268     skrll 	    UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)),
    834  1.268     skrll 	    UHCI_TD_GET_DT(le32toh(p->td.td_token)),
    835  1.268     skrll 	    UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token)));
    836    1.1  augustss }
    837    1.1  augustss 
    838    1.1  augustss void
    839  1.119  augustss uhci_dump_qh(uhci_soft_qh_t *sqh)
    840    1.1  augustss {
    841  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
    842  1.268     skrll 
    843  1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
    844  1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
    845  1.268     skrll 
    846  1.277  pgoyette 	DPRINTF("QH(%#jx) at 0x%08jx: hlink=%08jx elink=%08jx", (uintptr_t)sqh,
    847   1.88   tsutsui 	    (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink),
    848  1.268     skrll 	    le32toh(sqh->qh.qh_elink));
    849  1.268     skrll 
    850  1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD);
    851    1.1  augustss }
    852    1.1  augustss 
    853   1.13  augustss 
    854  1.110  augustss #if 1
    855    1.1  augustss void
    856  1.119  augustss uhci_dump(void)
    857    1.1  augustss {
    858  1.110  augustss 	uhci_dump_all(thesc);
    859  1.110  augustss }
    860  1.110  augustss #endif
    861    1.1  augustss 
    862  1.110  augustss void
    863  1.119  augustss uhci_dump_all(uhci_softc_t *sc)
    864  1.110  augustss {
    865    1.1  augustss 	uhci_dumpregs(sc);
    866  1.110  augustss 	/*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/
    867  1.261     skrll 	uhci_dump_qhs(sc->sc_lctl_start);
    868    1.1  augustss }
    869    1.1  augustss 
    870   1.67  augustss 
    871   1.67  augustss void
    872  1.119  augustss uhci_dump_qhs(uhci_soft_qh_t *sqh)
    873   1.67  augustss {
    874  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
    875  1.268     skrll 
    876   1.67  augustss 	uhci_dump_qh(sqh);
    877   1.67  augustss 
    878  1.268     skrll 	/*
    879  1.268     skrll 	 * uhci_dump_qhs displays all the QHs and TDs from the given QH onwards
    880   1.67  augustss 	 * Traverses sideways first, then down.
    881   1.67  augustss 	 *
    882   1.67  augustss 	 * QH1
    883   1.67  augustss 	 * QH2
    884   1.67  augustss 	 * No QH
    885   1.67  augustss 	 * TD2.1
    886   1.67  augustss 	 * TD2.2
    887   1.67  augustss 	 * TD1.1
    888   1.67  augustss 	 * etc.
    889   1.67  augustss 	 *
    890   1.67  augustss 	 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1.
    891   1.67  augustss 	 */
    892   1.67  augustss 
    893  1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
    894  1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
    895   1.88   tsutsui 	if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T))
    896   1.67  augustss 		uhci_dump_qhs(sqh->hlink);
    897   1.67  augustss 	else
    898  1.268     skrll 		DPRINTF("No QH", 0, 0, 0, 0);
    899  1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD);
    900   1.67  augustss 
    901   1.88   tsutsui 	if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T))
    902   1.67  augustss 		uhci_dump_tds(sqh->elink);
    903   1.67  augustss 	else
    904  1.268     skrll 		DPRINTF("No QH", 0, 0, 0, 0);
    905   1.67  augustss }
    906   1.67  augustss 
    907    1.1  augustss void
    908  1.119  augustss uhci_dump_tds(uhci_soft_td_t *std)
    909    1.1  augustss {
    910   1.67  augustss 	uhci_soft_td_t *td;
    911  1.223    bouyer 	int stop;
    912   1.67  augustss 
    913  1.267     skrll 	for (td = std; td != NULL; td = td->link.std) {
    914   1.67  augustss 		uhci_dump_td(td);
    915    1.1  augustss 
    916  1.268     skrll 		/*
    917  1.268     skrll 		 * Check whether the link pointer in this TD marks
    918   1.67  augustss 		 * the link pointer as end of queue. This avoids
    919   1.67  augustss 		 * printing the free list in case the queue/TD has
    920   1.67  augustss 		 * already been moved there (seatbelt).
    921   1.67  augustss 		 */
    922  1.223    bouyer 		usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link),
    923  1.223    bouyer 		    sizeof(td->td.td_link),
    924  1.223    bouyer 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
    925  1.223    bouyer 		stop = (le32toh(td->td.td_link) & UHCI_PTR_T ||
    926  1.223    bouyer 			le32toh(td->td.td_link) == 0);
    927  1.223    bouyer 		usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link),
    928  1.223    bouyer 		    sizeof(td->td.td_link), BUS_DMASYNC_PREREAD);
    929  1.223    bouyer 		if (stop)
    930   1.67  augustss 			break;
    931   1.67  augustss 	}
    932    1.1  augustss }
    933   1.92  augustss 
    934  1.101  augustss Static void
    935  1.268     skrll uhci_dump_ii(struct uhci_xfer *ux)
    936   1.92  augustss {
    937  1.268     skrll 	struct usbd_pipe *pipe;
    938   1.95  augustss 	usb_endpoint_descriptor_t *ed;
    939  1.268     skrll 	struct usbd_device *dev;
    940  1.152  augustss 
    941  1.268     skrll 	if (ux == NULL) {
    942  1.268     skrll 		printf("ux NULL\n");
    943  1.268     skrll 		return;
    944  1.268     skrll 	}
    945  1.268     skrll 	pipe = ux->ux_xfer.ux_pipe;
    946  1.268     skrll 	if (pipe == NULL) {
    947  1.268     skrll 		printf("ux %p: done=%d pipe=NULL\n", ux, ux->ux_isdone);
    948  1.268     skrll 		return;
    949  1.268     skrll 	}
    950  1.268     skrll 	if (pipe->up_endpoint == NULL) {
    951  1.268     skrll 		printf("ux %p: done=%d pipe=%p pipe->up_endpoint=NULL\n",
    952  1.268     skrll 		       ux, ux->ux_isdone, pipe);
    953  1.268     skrll 		return;
    954  1.268     skrll 	}
    955  1.268     skrll 	if (pipe->up_dev == NULL) {
    956  1.268     skrll 		printf("ux %p: done=%d pipe=%p pipe->up_dev=NULL\n",
    957  1.268     skrll 		       ux, ux->ux_isdone, pipe);
    958  1.268     skrll 		return;
    959  1.268     skrll 	}
    960  1.268     skrll 	ed = pipe->up_endpoint->ue_edesc;
    961  1.268     skrll 	dev = pipe->up_dev;
    962  1.268     skrll 	printf("ux %p: done=%d dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n",
    963  1.268     skrll 	       ux, ux->ux_isdone, dev,
    964  1.268     skrll 	       UGETW(dev->ud_ddesc.idVendor),
    965  1.268     skrll 	       UGETW(dev->ud_ddesc.idProduct),
    966  1.268     skrll 	       dev->ud_addr, pipe,
    967   1.92  augustss 	       ed->bEndpointAddress, ed->bmAttributes);
    968   1.92  augustss }
    969   1.92  augustss 
    970  1.120  augustss void uhci_dump_iis(struct uhci_softc *sc);
    971   1.92  augustss void
    972  1.119  augustss uhci_dump_iis(struct uhci_softc *sc)
    973   1.92  augustss {
    974  1.268     skrll 	struct uhci_xfer *ux;
    975   1.92  augustss 
    976  1.268     skrll 	printf("interrupt list:\n");
    977  1.268     skrll 	TAILQ_FOREACH(ux, &sc->sc_intrhead, ux_list)
    978  1.268     skrll 		uhci_dump_ii(ux);
    979   1.92  augustss }
    980   1.92  augustss 
    981  1.120  augustss void iidump(void);
    982  1.119  augustss void iidump(void) { uhci_dump_iis(thesc); }
    983   1.92  augustss 
    984    1.1  augustss #endif
    985    1.1  augustss 
    986    1.1  augustss /*
    987    1.1  augustss  * This routine is executed periodically and simulates interrupts
    988    1.1  augustss  * from the root controller interrupt pipe for port status change.
    989    1.1  augustss  */
    990    1.1  augustss void
    991  1.119  augustss uhci_poll_hub(void *addr)
    992    1.1  augustss {
    993  1.268     skrll 	struct usbd_xfer *xfer = addr;
    994  1.268     skrll 	struct usbd_pipe *pipe = xfer->ux_pipe;
    995  1.227    martin 	uhci_softc_t *sc;
    996    1.1  augustss 	u_char *p;
    997    1.1  augustss 
    998  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
    999    1.1  augustss 
   1000  1.268     skrll 	if (__predict_false(pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL))
   1001  1.228    martin 		return;	/* device has detached */
   1002  1.268     skrll 	sc = UHCI_PIPE2SC(pipe);
   1003  1.234    dyoung 	callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer);
   1004   1.41  augustss 
   1005  1.268     skrll 	p = xfer->ux_buf;
   1006    1.1  augustss 	p[0] = 0;
   1007    1.1  augustss 	if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC))
   1008    1.1  augustss 		p[0] |= 1<<1;
   1009    1.1  augustss 	if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC))
   1010    1.1  augustss 		p[0] |= 1<<2;
   1011   1.41  augustss 	if (p[0] == 0)
   1012   1.41  augustss 		/* No change, try again in a while */
   1013   1.41  augustss 		return;
   1014   1.41  augustss 
   1015  1.268     skrll 	xfer->ux_actlen = 1;
   1016  1.268     skrll 	xfer->ux_status = USBD_NORMAL_COMPLETION;
   1017  1.248       mrg 	mutex_enter(&sc->sc_lock);
   1018   1.63  augustss 	usb_transfer_complete(xfer);
   1019  1.248       mrg 	mutex_exit(&sc->sc_lock);
   1020   1.41  augustss }
   1021   1.41  augustss 
   1022   1.41  augustss void
   1023  1.268     skrll uhci_root_intr_done(struct usbd_xfer *xfer)
   1024   1.41  augustss {
   1025    1.1  augustss }
   1026    1.1  augustss 
   1027  1.123  augustss /*
   1028  1.123  augustss  * Let the last QH loop back to the high speed control transfer QH.
   1029  1.123  augustss  * This is what intel calls "bandwidth reclamation" and improves
   1030  1.123  augustss  * USB performance a lot for some devices.
   1031  1.123  augustss  * If we are already looping, just count it.
   1032  1.123  augustss  */
   1033    1.1  augustss void
   1034  1.268     skrll uhci_add_loop(uhci_softc_t *sc)
   1035  1.268     skrll {
   1036  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1037  1.268     skrll 
   1038  1.125  augustss #ifdef UHCI_DEBUG
   1039  1.125  augustss 	if (uhcinoloop)
   1040  1.125  augustss 		return;
   1041  1.125  augustss #endif
   1042  1.123  augustss 	if (++sc->sc_loops == 1) {
   1043  1.268     skrll 		DPRINTFN(5, "add loop", 0, 0, 0, 0);
   1044  1.123  augustss 		/* Note, we don't loop back the soft pointer. */
   1045  1.152  augustss 		sc->sc_last_qh->qh.qh_hlink =
   1046  1.123  augustss 		    htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH);
   1047  1.223    bouyer 		usb_syncmem(&sc->sc_last_qh->dma,
   1048  1.223    bouyer 		    sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink),
   1049  1.223    bouyer 		    sizeof(sc->sc_last_qh->qh.qh_hlink),
   1050  1.223    bouyer 		    BUS_DMASYNC_PREWRITE);
   1051  1.123  augustss 	}
   1052  1.123  augustss }
   1053  1.123  augustss 
   1054  1.123  augustss void
   1055  1.268     skrll uhci_rem_loop(uhci_softc_t *sc)
   1056  1.268     skrll {
   1057  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1058  1.268     skrll 
   1059  1.125  augustss #ifdef UHCI_DEBUG
   1060  1.125  augustss 	if (uhcinoloop)
   1061  1.125  augustss 		return;
   1062  1.125  augustss #endif
   1063  1.123  augustss 	if (--sc->sc_loops == 0) {
   1064  1.268     skrll 		DPRINTFN(5, "remove loop", 0, 0, 0, 0);
   1065  1.123  augustss 		sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T);
   1066  1.223    bouyer 		usb_syncmem(&sc->sc_last_qh->dma,
   1067  1.223    bouyer 		    sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink),
   1068  1.223    bouyer 		    sizeof(sc->sc_last_qh->qh.qh_hlink),
   1069  1.223    bouyer 		    BUS_DMASYNC_PREWRITE);
   1070  1.123  augustss 	}
   1071  1.123  augustss }
   1072  1.123  augustss 
   1073  1.248       mrg /* Add high speed control QH, called with lock held. */
   1074  1.123  augustss void
   1075  1.123  augustss uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   1076    1.1  augustss {
   1077   1.42  augustss 	uhci_soft_qh_t *eqh;
   1078    1.1  augustss 
   1079  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1080  1.268     skrll 
   1081  1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   1082  1.248       mrg 
   1083  1.277  pgoyette 	DPRINTFN(10, "sqh %#jx", (uintptr_t)sqh, 0, 0, 0);
   1084  1.123  augustss 	eqh = sc->sc_hctl_end;
   1085  1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1086  1.223    bouyer 	    sizeof(eqh->qh.qh_hlink),
   1087  1.223    bouyer 	    BUS_DMASYNC_POSTWRITE);
   1088   1.42  augustss 	sqh->hlink       = eqh->hlink;
   1089   1.42  augustss 	sqh->qh.qh_hlink = eqh->qh.qh_hlink;
   1090  1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
   1091  1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   1092   1.42  augustss 	eqh->hlink       = sqh;
   1093  1.121  augustss 	eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
   1094  1.123  augustss 	sc->sc_hctl_end = sqh;
   1095  1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1096  1.223    bouyer 	    sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
   1097  1.125  augustss #ifdef UHCI_CTL_LOOP
   1098  1.123  augustss 	uhci_add_loop(sc);
   1099  1.125  augustss #endif
   1100    1.1  augustss }
   1101    1.1  augustss 
   1102  1.248       mrg /* Remove high speed control QH, called with lock held. */
   1103    1.1  augustss void
   1104  1.123  augustss uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   1105    1.1  augustss {
   1106    1.1  augustss 	uhci_soft_qh_t *pqh;
   1107  1.256   tsutsui 	uint32_t elink;
   1108    1.1  augustss 
   1109  1.272  christos 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
   1110  1.248       mrg 
   1111  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1112  1.277  pgoyette 	DPRINTFN(10, "sqh %#jx", (uintptr_t)sqh, 0, 0, 0);
   1113  1.125  augustss #ifdef UHCI_CTL_LOOP
   1114  1.123  augustss 	uhci_rem_loop(sc);
   1115  1.125  augustss #endif
   1116  1.124  augustss 	/*
   1117  1.124  augustss 	 * The T bit should be set in the elink of the QH so that the HC
   1118  1.124  augustss 	 * doesn't follow the pointer.  This condition may fail if the
   1119  1.124  augustss 	 * the transferred packet was short so that the QH still points
   1120  1.124  augustss 	 * at the last used TD.
   1121  1.124  augustss 	 * In this case we set the T bit and wait a little for the HC
   1122  1.124  augustss 	 * to stop looking at the TD.
   1123  1.223    bouyer 	 * Note that if the TD chain is large enough, the controller
   1124  1.223    bouyer 	 * may still be looking at the chain at the end of this function.
   1125  1.223    bouyer 	 * uhci_free_std_chain() will make sure the controller stops
   1126  1.223    bouyer 	 * looking at it quickly, but until then we should not change
   1127  1.223    bouyer 	 * sqh->hlink.
   1128  1.124  augustss 	 */
   1129  1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1130  1.223    bouyer 	    sizeof(sqh->qh.qh_elink),
   1131  1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1132  1.256   tsutsui 	elink = le32toh(sqh->qh.qh_elink);
   1133  1.256   tsutsui 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1134  1.256   tsutsui 	    sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD);
   1135  1.256   tsutsui 	if (!(elink & UHCI_PTR_T)) {
   1136  1.124  augustss 		sqh->qh.qh_elink = htole32(UHCI_PTR_T);
   1137  1.223    bouyer 		usb_syncmem(&sqh->dma,
   1138  1.223    bouyer 		    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1139  1.223    bouyer 		    sizeof(sqh->qh.qh_elink),
   1140  1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   1141  1.124  augustss 		delay(UHCI_QH_REMOVE_DELAY);
   1142  1.124  augustss 	}
   1143  1.124  augustss 
   1144  1.123  augustss 	pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh);
   1145  1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1146  1.223    bouyer 	    sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
   1147  1.152  augustss 	pqh->hlink = sqh->hlink;
   1148   1.42  augustss 	pqh->qh.qh_hlink = sqh->qh.qh_hlink;
   1149  1.223    bouyer 	usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1150  1.272  christos 	    sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
   1151  1.124  augustss 	delay(UHCI_QH_REMOVE_DELAY);
   1152  1.123  augustss 	if (sc->sc_hctl_end == sqh)
   1153  1.123  augustss 		sc->sc_hctl_end = pqh;
   1154  1.123  augustss }
   1155  1.123  augustss 
   1156  1.248       mrg /* Add low speed control QH, called with lock held. */
   1157  1.123  augustss void
   1158  1.123  augustss uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   1159  1.123  augustss {
   1160  1.123  augustss 	uhci_soft_qh_t *eqh;
   1161  1.123  augustss 
   1162  1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   1163  1.248       mrg 
   1164  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1165  1.277  pgoyette 	DPRINTFN(10, "sqh %#jx", (uintptr_t)sqh, 0, 0, 0);
   1166  1.268     skrll 
   1167  1.123  augustss 	eqh = sc->sc_lctl_end;
   1168  1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1169  1.223    bouyer 	    sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
   1170  1.152  augustss 	sqh->hlink = eqh->hlink;
   1171  1.123  augustss 	sqh->qh.qh_hlink = eqh->qh.qh_hlink;
   1172  1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
   1173  1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   1174  1.152  augustss 	eqh->hlink = sqh;
   1175  1.123  augustss 	eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
   1176  1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1177  1.223    bouyer 	    sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
   1178  1.123  augustss 	sc->sc_lctl_end = sqh;
   1179  1.123  augustss }
   1180  1.123  augustss 
   1181  1.248       mrg /* Remove low speed control QH, called with lock held. */
   1182  1.123  augustss void
   1183  1.123  augustss uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   1184  1.123  augustss {
   1185  1.123  augustss 	uhci_soft_qh_t *pqh;
   1186  1.256   tsutsui 	uint32_t elink;
   1187  1.123  augustss 
   1188  1.272  christos 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
   1189  1.248       mrg 
   1190  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1191  1.277  pgoyette 	DPRINTFN(10, "sqh %#jx", (uintptr_t)sqh, 0, 0, 0);
   1192  1.268     skrll 
   1193  1.124  augustss 	/* See comment in uhci_remove_hs_ctrl() */
   1194  1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1195  1.223    bouyer 	    sizeof(sqh->qh.qh_elink),
   1196  1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1197  1.256   tsutsui 	elink = le32toh(sqh->qh.qh_elink);
   1198  1.256   tsutsui 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1199  1.256   tsutsui 	    sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD);
   1200  1.256   tsutsui 	if (!(elink & UHCI_PTR_T)) {
   1201  1.124  augustss 		sqh->qh.qh_elink = htole32(UHCI_PTR_T);
   1202  1.223    bouyer 		usb_syncmem(&sqh->dma,
   1203  1.223    bouyer 		    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1204  1.223    bouyer 		    sizeof(sqh->qh.qh_elink),
   1205  1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   1206  1.124  augustss 		delay(UHCI_QH_REMOVE_DELAY);
   1207  1.124  augustss 	}
   1208  1.123  augustss 	pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh);
   1209  1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1210  1.223    bouyer 	    sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
   1211  1.152  augustss 	pqh->hlink = sqh->hlink;
   1212  1.123  augustss 	pqh->qh.qh_hlink = sqh->qh.qh_hlink;
   1213  1.223    bouyer 	usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1214  1.223    bouyer 	    sizeof(pqh->qh.qh_hlink),
   1215  1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   1216  1.124  augustss 	delay(UHCI_QH_REMOVE_DELAY);
   1217  1.123  augustss 	if (sc->sc_lctl_end == sqh)
   1218  1.123  augustss 		sc->sc_lctl_end = pqh;
   1219    1.1  augustss }
   1220    1.1  augustss 
   1221  1.248       mrg /* Add bulk QH, called with lock held. */
   1222    1.1  augustss void
   1223  1.119  augustss uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   1224    1.1  augustss {
   1225   1.42  augustss 	uhci_soft_qh_t *eqh;
   1226    1.1  augustss 
   1227  1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   1228  1.248       mrg 
   1229  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1230  1.277  pgoyette 	DPRINTFN(10, "sqh %#jx", (uintptr_t)sqh, 0, 0, 0);
   1231  1.268     skrll 
   1232   1.42  augustss 	eqh = sc->sc_bulk_end;
   1233  1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1234  1.223    bouyer 	    sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
   1235  1.152  augustss 	sqh->hlink = eqh->hlink;
   1236   1.42  augustss 	sqh->qh.qh_hlink = eqh->qh.qh_hlink;
   1237  1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
   1238  1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   1239  1.152  augustss 	eqh->hlink = sqh;
   1240  1.121  augustss 	eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
   1241  1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1242  1.223    bouyer 	    sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
   1243    1.1  augustss 	sc->sc_bulk_end = sqh;
   1244  1.123  augustss 	uhci_add_loop(sc);
   1245    1.1  augustss }
   1246    1.1  augustss 
   1247  1.248       mrg /* Remove bulk QH, called with lock held. */
   1248    1.1  augustss void
   1249  1.119  augustss uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   1250    1.1  augustss {
   1251    1.1  augustss 	uhci_soft_qh_t *pqh;
   1252    1.1  augustss 
   1253  1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   1254  1.248       mrg 
   1255  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1256  1.277  pgoyette 	DPRINTFN(10, "sqh %#jx", (uintptr_t)sqh, 0, 0, 0);
   1257  1.268     skrll 
   1258  1.123  augustss 	uhci_rem_loop(sc);
   1259  1.124  augustss 	/* See comment in uhci_remove_hs_ctrl() */
   1260  1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1261  1.223    bouyer 	    sizeof(sqh->qh.qh_elink),
   1262  1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1263  1.124  augustss 	if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) {
   1264  1.124  augustss 		sqh->qh.qh_elink = htole32(UHCI_PTR_T);
   1265  1.223    bouyer 		usb_syncmem(&sqh->dma,
   1266  1.223    bouyer 		    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   1267  1.223    bouyer 		    sizeof(sqh->qh.qh_elink),
   1268  1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   1269  1.124  augustss 		delay(UHCI_QH_REMOVE_DELAY);
   1270  1.124  augustss 	}
   1271   1.92  augustss 	pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh);
   1272  1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1273  1.223    bouyer 	    sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
   1274   1.42  augustss 	pqh->hlink       = sqh->hlink;
   1275   1.42  augustss 	pqh->qh.qh_hlink = sqh->qh.qh_hlink;
   1276  1.223    bouyer 	usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
   1277  1.223    bouyer 	    sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
   1278  1.124  augustss 	delay(UHCI_QH_REMOVE_DELAY);
   1279    1.1  augustss 	if (sc->sc_bulk_end == sqh)
   1280    1.1  augustss 		sc->sc_bulk_end = pqh;
   1281    1.1  augustss }
   1282    1.1  augustss 
   1283  1.141  augustss Static int uhci_intr1(uhci_softc_t *);
   1284  1.141  augustss 
   1285    1.1  augustss int
   1286  1.119  augustss uhci_intr(void *arg)
   1287    1.1  augustss {
   1288   1.44  augustss 	uhci_softc_t *sc = arg;
   1289  1.248       mrg 	int ret = 0;
   1290  1.248       mrg 
   1291  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1292  1.268     skrll 
   1293  1.248       mrg 	mutex_spin_enter(&sc->sc_intr_lock);
   1294  1.146  augustss 
   1295  1.216  drochner 	if (sc->sc_dying || !device_has_power(sc->sc_dev))
   1296  1.248       mrg 		goto done;
   1297  1.141  augustss 
   1298  1.268     skrll 	if (sc->sc_bus.ub_usepolling || UREAD2(sc, UHCI_INTR) == 0) {
   1299  1.268     skrll 		DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0);
   1300  1.248       mrg 		goto done;
   1301  1.141  augustss 	}
   1302  1.179   mycroft 
   1303  1.248       mrg 	ret = uhci_intr1(sc);
   1304  1.248       mrg 
   1305  1.248       mrg  done:
   1306  1.248       mrg 	mutex_spin_exit(&sc->sc_intr_lock);
   1307  1.248       mrg 	return ret;
   1308  1.141  augustss }
   1309  1.141  augustss 
   1310  1.141  augustss int
   1311  1.141  augustss uhci_intr1(uhci_softc_t *sc)
   1312  1.141  augustss {
   1313   1.44  augustss 	int status;
   1314   1.44  augustss 	int ack;
   1315    1.1  augustss 
   1316  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1317  1.268     skrll 
   1318   1.67  augustss #ifdef UHCI_DEBUG
   1319  1.268     skrll 	if (uhcidebug >= 15) {
   1320  1.277  pgoyette 		DPRINTF("sc %#jx", (uintptr_t)sc, 0, 0, 0);
   1321    1.1  augustss 		uhci_dumpregs(sc);
   1322    1.1  augustss 	}
   1323    1.1  augustss #endif
   1324  1.117  augustss 
   1325  1.248       mrg 	KASSERT(mutex_owned(&sc->sc_intr_lock));
   1326  1.248       mrg 
   1327  1.153  augustss 	status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS;
   1328  1.268     skrll 	/* Check if the interrupt was for us. */
   1329  1.268     skrll 	if (status == 0)
   1330  1.268     skrll 		return 0;
   1331  1.127     soren 
   1332  1.117  augustss 	if (sc->sc_suspend != PWR_RESUME) {
   1333  1.201  jmcneill #ifdef DIAGNOSTIC
   1334  1.117  augustss 		printf("%s: interrupt while not operating ignored\n",
   1335  1.216  drochner 		       device_xname(sc->sc_dev));
   1336  1.201  jmcneill #endif
   1337  1.134  augustss 		UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */
   1338  1.268     skrll 		return 0;
   1339  1.117  augustss 	}
   1340   1.44  augustss 
   1341   1.44  augustss 	ack = 0;
   1342   1.44  augustss 	if (status & UHCI_STS_USBINT)
   1343   1.44  augustss 		ack |= UHCI_STS_USBINT;
   1344   1.44  augustss 	if (status & UHCI_STS_USBEI)
   1345   1.44  augustss 		ack |= UHCI_STS_USBEI;
   1346    1.1  augustss 	if (status & UHCI_STS_RD) {
   1347   1.44  augustss 		ack |= UHCI_STS_RD;
   1348  1.118  augustss #ifdef UHCI_DEBUG
   1349  1.216  drochner 		printf("%s: resume detect\n", device_xname(sc->sc_dev));
   1350  1.118  augustss #endif
   1351    1.1  augustss 	}
   1352    1.1  augustss 	if (status & UHCI_STS_HSE) {
   1353   1.44  augustss 		ack |= UHCI_STS_HSE;
   1354  1.216  drochner 		printf("%s: host system error\n", device_xname(sc->sc_dev));
   1355    1.1  augustss 	}
   1356    1.1  augustss 	if (status & UHCI_STS_HCPE) {
   1357   1.44  augustss 		ack |= UHCI_STS_HCPE;
   1358  1.152  augustss 		printf("%s: host controller process error\n",
   1359  1.216  drochner 		       device_xname(sc->sc_dev));
   1360   1.44  augustss 	}
   1361  1.233   msaitoh 
   1362  1.233   msaitoh 	/* When HCHalted=1 and Run/Stop=0 , it is normal */
   1363  1.233   msaitoh 	if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) {
   1364   1.44  augustss 		/* no acknowledge needed */
   1365  1.136  augustss 		if (!sc->sc_dying) {
   1366  1.152  augustss 			printf("%s: host controller halted\n",
   1367  1.216  drochner 			    device_xname(sc->sc_dev));
   1368  1.110  augustss #ifdef UHCI_DEBUG
   1369  1.136  augustss 			uhci_dump_all(sc);
   1370  1.110  augustss #endif
   1371  1.136  augustss 		}
   1372  1.136  augustss 		sc->sc_dying = 1;
   1373    1.1  augustss 	}
   1374   1.44  augustss 
   1375  1.132  augustss 	if (!ack)
   1376  1.268     skrll 		return 0;	/* nothing to acknowledge */
   1377  1.132  augustss 	UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */
   1378    1.1  augustss 
   1379   1.85  augustss 	usb_schedsoftintr(&sc->sc_bus);
   1380   1.85  augustss 
   1381  1.277  pgoyette 	DPRINTFN(15, "sc %#jx done", (uintptr_t)sc, 0, 0, 0);
   1382   1.85  augustss 
   1383  1.268     skrll 	return 1;
   1384   1.85  augustss }
   1385   1.85  augustss 
   1386   1.85  augustss void
   1387  1.133  augustss uhci_softintr(void *v)
   1388   1.85  augustss {
   1389  1.216  drochner 	struct usbd_bus *bus = v;
   1390  1.268     skrll 	uhci_softc_t *sc = UHCI_BUS2SC(bus);
   1391  1.268     skrll 	struct uhci_xfer *ux, *nextux;
   1392  1.268     skrll 	ux_completeq_t cq;
   1393   1.85  augustss 
   1394  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1395  1.277  pgoyette 	DPRINTF("sc %#jx", (uintptr_t)sc, 0, 0, 0);
   1396  1.248       mrg 
   1397  1.268     skrll 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
   1398   1.50  augustss 
   1399  1.268     skrll 	TAILQ_INIT(&cq);
   1400    1.1  augustss 	/*
   1401    1.1  augustss 	 * Interrupts on UHCI really suck.  When the host controller
   1402    1.1  augustss 	 * interrupts because a transfer is completed there is no
   1403    1.1  augustss 	 * way of knowing which transfer it was.  You can scan down
   1404    1.1  augustss 	 * the TDs and QHs of the previous frame to limit the search,
   1405    1.1  augustss 	 * but that assumes that the interrupt was not delayed by more
   1406    1.1  augustss 	 * than 1 ms, which may not always be true (e.g. after debug
   1407    1.1  augustss 	 * output on a slow console).
   1408    1.1  augustss 	 * We scan all interrupt descriptors to see if any have
   1409    1.1  augustss 	 * completed.
   1410    1.1  augustss 	 */
   1411  1.268     skrll 	TAILQ_FOREACH_SAFE(ux, &sc->sc_intrhead, ux_list, nextux) {
   1412  1.268     skrll 		uhci_check_intr(sc, ux, &cq);
   1413  1.268     skrll 	}
   1414  1.268     skrll 
   1415  1.268     skrll 	/*
   1416  1.268     skrll 	 * We abuse ux_list for the interrupt and complete lists and
   1417  1.268     skrll 	 * interrupt transfers will get re-added here so use
   1418  1.268     skrll 	 * the _SAFE version of TAILQ_FOREACH.
   1419  1.268     skrll 	 */
   1420  1.268     skrll 	TAILQ_FOREACH_SAFE(ux, &cq, ux_list, nextux) {
   1421  1.277  pgoyette 		DPRINTF("ux %#jx", (uintptr_t)ux, 0, 0, 0);
   1422  1.268     skrll 		usb_transfer_complete(&ux->ux_xfer);
   1423  1.178    martin 	}
   1424    1.1  augustss 
   1425  1.281       mrg 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
   1426    1.1  augustss }
   1427    1.1  augustss 
   1428    1.1  augustss /* Check for an interrupt. */
   1429    1.1  augustss void
   1430  1.268     skrll uhci_check_intr(uhci_softc_t *sc, struct uhci_xfer *ux, ux_completeq_t *cqp)
   1431    1.1  augustss {
   1432  1.268     skrll 	uhci_soft_td_t *std, *fstd = NULL, *lstd = NULL;
   1433  1.268     skrll 	uint32_t status;
   1434    1.1  augustss 
   1435  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1436  1.277  pgoyette 	DPRINTFN(15, "ux %#jx", (uintptr_t)ux, 0, 0, 0);
   1437  1.268     skrll 
   1438  1.268     skrll 	KASSERT(ux != NULL);
   1439  1.268     skrll 
   1440  1.268     skrll 	struct usbd_xfer *xfer = &ux->ux_xfer;
   1441  1.268     skrll 	if (xfer->ux_status == USBD_CANCELLED ||
   1442  1.268     skrll 	    xfer->ux_status == USBD_TIMEOUT) {
   1443  1.277  pgoyette 		DPRINTF("aborted xfer %#jx", (uintptr_t)xfer, 0, 0, 0);
   1444    1.1  augustss 		return;
   1445    1.1  augustss 	}
   1446  1.268     skrll 
   1447  1.268     skrll 	switch (ux->ux_type) {
   1448  1.268     skrll 	case UX_CTRL:
   1449  1.268     skrll 		fstd = ux->ux_setup;
   1450  1.268     skrll 		lstd = ux->ux_stat;
   1451  1.268     skrll 		break;
   1452  1.268     skrll 	case UX_BULK:
   1453  1.268     skrll 	case UX_INTR:
   1454  1.268     skrll 	case UX_ISOC:
   1455  1.268     skrll 		fstd = ux->ux_stdstart;
   1456  1.268     skrll 		lstd = ux->ux_stdend;
   1457  1.268     skrll 		break;
   1458  1.268     skrll 	default:
   1459  1.268     skrll 		KASSERT(false);
   1460  1.268     skrll 		break;
   1461  1.268     skrll 	}
   1462  1.268     skrll 	if (fstd == NULL)
   1463  1.155  augustss 		return;
   1464  1.155  augustss 
   1465  1.268     skrll 	KASSERT(lstd != NULL);
   1466  1.268     skrll 
   1467  1.223    bouyer 	usb_syncmem(&lstd->dma,
   1468  1.223    bouyer 	    lstd->offs + offsetof(uhci_td_t, td_status),
   1469  1.223    bouyer 	    sizeof(lstd->td.td_status),
   1470  1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1471  1.256   tsutsui 	status = le32toh(lstd->td.td_status);
   1472  1.256   tsutsui 	usb_syncmem(&lstd->dma,
   1473  1.256   tsutsui 	    lstd->offs + offsetof(uhci_td_t, td_status),
   1474  1.256   tsutsui 	    sizeof(lstd->td.td_status),
   1475  1.256   tsutsui 	    BUS_DMASYNC_PREREAD);
   1476  1.258     skrll 
   1477  1.258     skrll 	/* If the last TD is not marked active we can complete */
   1478  1.258     skrll 	if (!(status & UHCI_TD_ACTIVE)) {
   1479  1.258     skrll  done:
   1480  1.277  pgoyette 		DPRINTFN(12, "ux=%#jx done", (uintptr_t)ux, 0, 0, 0);
   1481  1.268     skrll 		uhci_idone(ux, cqp);
   1482  1.258     skrll 		return;
   1483  1.258     skrll 	}
   1484  1.258     skrll 
   1485  1.258     skrll 	/*
   1486  1.258     skrll 	 * If the last TD is still active we need to check whether there
   1487  1.258     skrll 	 * is an error somewhere in the middle, or whether there was a
   1488  1.258     skrll 	 * short packet (SPD and not ACTIVE).
   1489  1.258     skrll 	 */
   1490  1.277  pgoyette 	DPRINTFN(12, "active ux=%#jx", (uintptr_t)ux, 0, 0, 0);
   1491  1.268     skrll 	for (std = fstd; std != lstd; std = std->link.std) {
   1492  1.258     skrll 		usb_syncmem(&std->dma,
   1493  1.258     skrll 		    std->offs + offsetof(uhci_td_t, td_status),
   1494  1.258     skrll 		    sizeof(std->td.td_status),
   1495  1.258     skrll 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1496  1.258     skrll 		status = le32toh(std->td.td_status);
   1497  1.258     skrll 		usb_syncmem(&std->dma,
   1498  1.258     skrll 		    std->offs + offsetof(uhci_td_t, td_status),
   1499  1.258     skrll 		    sizeof(std->td.td_status), BUS_DMASYNC_PREREAD);
   1500  1.258     skrll 
   1501  1.258     skrll 		/* If there's an active TD the xfer isn't done. */
   1502  1.258     skrll 		if (status & UHCI_TD_ACTIVE) {
   1503  1.277  pgoyette 			DPRINTFN(12, "ux=%#jx std=%#jx still active",
   1504  1.277  pgoyette 			    (uintptr_t)ux, (uintptr_t)std, 0, 0);
   1505  1.258     skrll 			return;
   1506  1.258     skrll 		}
   1507  1.258     skrll 
   1508  1.258     skrll 		/* Any kind of error makes the xfer done. */
   1509  1.258     skrll 		if (status & UHCI_TD_STALLED)
   1510  1.258     skrll 			goto done;
   1511  1.258     skrll 
   1512  1.258     skrll 		/*
   1513  1.258     skrll 		 * If the data phase of a control transfer is short, we need
   1514  1.258     skrll 		 * to complete the status stage
   1515  1.258     skrll 		 */
   1516  1.258     skrll 
   1517  1.268     skrll 		if ((status & UHCI_TD_SPD) && ux->ux_type == UX_CTRL) {
   1518  1.258     skrll 			struct uhci_pipe *upipe =
   1519  1.268     skrll 			    UHCI_PIPE2UPIPE(xfer->ux_pipe);
   1520  1.268     skrll 			uhci_soft_qh_t *sqh = upipe->ctrl.sqh;
   1521  1.268     skrll 			uhci_soft_td_t *stat = upipe->ctrl.stat;
   1522  1.268     skrll 
   1523  1.277  pgoyette 			DPRINTFN(12, "ux=%#jx std=%#jx control status"
   1524  1.277  pgoyette 			    "phase needs completion", (uintptr_t)ux,
   1525  1.277  pgoyette 			    (uintptr_t)ux->ux_stdstart, 0, 0);
   1526  1.258     skrll 
   1527  1.258     skrll 			sqh->qh.qh_elink =
   1528  1.258     skrll 			    htole32(stat->physaddr | UHCI_PTR_TD);
   1529  1.258     skrll 			usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
   1530  1.258     skrll 			    BUS_DMASYNC_PREWRITE);
   1531  1.258     skrll 			break;
   1532  1.258     skrll 		}
   1533  1.258     skrll 
   1534  1.258     skrll 		/* We want short packets, and it is short: it's done */
   1535  1.258     skrll 		usb_syncmem(&std->dma,
   1536  1.258     skrll 		    std->offs + offsetof(uhci_td_t, td_token),
   1537  1.258     skrll 		    sizeof(std->td.td_token),
   1538  1.258     skrll 		    BUS_DMASYNC_POSTWRITE);
   1539  1.258     skrll 
   1540  1.258     skrll 		if ((status & UHCI_TD_SPD) &&
   1541  1.258     skrll 			UHCI_TD_GET_ACTLEN(status) <
   1542  1.258     skrll 			UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) {
   1543  1.258     skrll 			goto done;
   1544   1.18  augustss 		}
   1545    1.1  augustss 	}
   1546    1.1  augustss }
   1547    1.1  augustss 
   1548  1.248       mrg /* Called with USB lock held. */
   1549    1.1  augustss void
   1550  1.268     skrll uhci_idone(struct uhci_xfer *ux, ux_completeq_t *cqp)
   1551    1.1  augustss {
   1552  1.281       mrg 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1553  1.268     skrll 	struct usbd_xfer *xfer = &ux->ux_xfer;
   1554  1.268     skrll 	uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer);
   1555  1.268     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   1556    1.1  augustss 	uhci_soft_td_t *std;
   1557  1.268     skrll 	uint32_t status = 0, nstatus;
   1558  1.282     prlw1 	bool polling __diagused = sc->sc_bus.ub_usepolling;
   1559   1.26  augustss 	int actlen;
   1560    1.1  augustss 
   1561  1.281       mrg 	KASSERT(polling || mutex_owned(&sc->sc_lock));
   1562  1.268     skrll 
   1563  1.277  pgoyette 	DPRINTFN(12, "ux=%#jx", (uintptr_t)ux, 0, 0, 0);
   1564  1.248       mrg 
   1565  1.281       mrg 	/*
   1566  1.281       mrg 	 * If software has completed it, either by cancellation
   1567  1.281       mrg 	 * or timeout, drop it on the floor.
   1568  1.281       mrg 	 */
   1569  1.281       mrg 	if (xfer->ux_status != USBD_IN_PROGRESS) {
   1570  1.281       mrg 		KASSERT(xfer->ux_status == USBD_CANCELLED ||
   1571  1.281       mrg 		    xfer->ux_status == USBD_TIMEOUT);
   1572  1.281       mrg 		DPRINTF("aborted xfer=%#jx", (uintptr_t)xfer, 0, 0, 0);
   1573  1.281       mrg 		return;
   1574  1.281       mrg 	}
   1575  1.281       mrg 
   1576  1.281       mrg 	/*
   1577  1.281       mrg 	 * Cancel the timeout and the task, which have not yet
   1578  1.281       mrg 	 * run.  If they have already fired, at worst they are
   1579  1.281       mrg 	 * waiting for the lock.  They will see that the xfer
   1580  1.281       mrg 	 * is no longer in progress and give up.
   1581  1.281       mrg 	 */
   1582  1.281       mrg 	callout_stop(&xfer->ux_callout);
   1583  1.281       mrg 	usb_rem_task(xfer->ux_pipe->up_dev, &xfer->ux_aborttask);
   1584  1.281       mrg 
   1585    1.7  augustss #ifdef DIAGNOSTIC
   1586   1.92  augustss #ifdef UHCI_DEBUG
   1587  1.268     skrll 	if (ux->ux_isdone) {
   1588  1.268     skrll 		DPRINTF("--- dump start ---", 0, 0, 0, 0);
   1589  1.268     skrll 		uhci_dump_ii(ux);
   1590  1.268     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   1591  1.268     skrll 	}
   1592   1.92  augustss #endif
   1593  1.268     skrll 	KASSERT(!ux->ux_isdone);
   1594  1.268     skrll 	KASSERTMSG(!ux->ux_isdone, "xfer %p type %d status %d", xfer,
   1595  1.268     skrll 	    ux->ux_type, xfer->ux_status);
   1596  1.268     skrll 	ux->ux_isdone = true;
   1597    1.7  augustss #endif
   1598   1.48  augustss 
   1599  1.268     skrll 	if (xfer->ux_nframes != 0) {
   1600   1.48  augustss 		/* Isoc transfer, do things differently. */
   1601  1.268     skrll 		uhci_soft_td_t **stds = upipe->isoc.stds;
   1602  1.126  augustss 		int i, n, nframes, len;
   1603   1.48  augustss 
   1604  1.277  pgoyette 		DPRINTFN(5, "ux=%#jx isoc ready", (uintptr_t)ux, 0, 0, 0);
   1605   1.48  augustss 
   1606  1.268     skrll 		nframes = xfer->ux_nframes;
   1607   1.48  augustss 		actlen = 0;
   1608  1.268     skrll 		n = ux->ux_curframe;
   1609   1.48  augustss 		for (i = 0; i < nframes; i++) {
   1610   1.48  augustss 			std = stds[n];
   1611   1.59  augustss #ifdef UHCI_DEBUG
   1612  1.268     skrll 			if (uhcidebug >= 5) {
   1613  1.277  pgoyette 				DPRINTF("isoc TD %jd", i, 0, 0, 0);
   1614  1.268     skrll 				DPRINTF("--- dump start ---", 0, 0, 0, 0);
   1615   1.48  augustss 				uhci_dump_td(std);
   1616  1.268     skrll 				DPRINTF("--- dump end ---", 0, 0, 0, 0);
   1617   1.48  augustss 			}
   1618   1.48  augustss #endif
   1619   1.48  augustss 			if (++n >= UHCI_VFRAMELIST_COUNT)
   1620   1.48  augustss 				n = 0;
   1621  1.223    bouyer 			usb_syncmem(&std->dma,
   1622  1.223    bouyer 			    std->offs + offsetof(uhci_td_t, td_status),
   1623  1.223    bouyer 			    sizeof(std->td.td_status),
   1624  1.223    bouyer 			    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1625   1.88   tsutsui 			status = le32toh(std->td.td_status);
   1626  1.126  augustss 			len = UHCI_TD_GET_ACTLEN(status);
   1627  1.268     skrll 			xfer->ux_frlengths[i] = len;
   1628  1.126  augustss 			actlen += len;
   1629   1.48  augustss 		}
   1630  1.268     skrll 		upipe->isoc.inuse -= nframes;
   1631  1.268     skrll 		xfer->ux_actlen = actlen;
   1632  1.268     skrll 		xfer->ux_status = USBD_NORMAL_COMPLETION;
   1633  1.140  augustss 		goto end;
   1634   1.48  augustss 	}
   1635   1.48  augustss 
   1636   1.59  augustss #ifdef UHCI_DEBUG
   1637  1.277  pgoyette 	DPRINTFN(10, "ux=%#jx, xfer=%#jx, pipe=%#jx ready", (uintptr_t)ux,
   1638  1.277  pgoyette 	    (uintptr_t)xfer, (uintptr_t)upipe, 0);
   1639  1.268     skrll 	if (uhcidebug >= 10) {
   1640  1.268     skrll 		DPRINTF("--- dump start ---", 0, 0, 0, 0);
   1641  1.268     skrll 		uhci_dump_tds(ux->ux_stdstart);
   1642  1.268     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   1643  1.268     skrll 	}
   1644   1.48  augustss #endif
   1645   1.48  augustss 
   1646   1.26  augustss 	/* The transfer is done, compute actual length and status. */
   1647   1.26  augustss 	actlen = 0;
   1648  1.268     skrll 	for (std = ux->ux_stdstart; std != NULL; std = std->link.std) {
   1649  1.223    bouyer 		usb_syncmem(&std->dma, std->offs, sizeof(std->td),
   1650  1.223    bouyer 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1651   1.88   tsutsui 		nstatus = le32toh(std->td.td_status);
   1652   1.64  augustss 		if (nstatus & UHCI_TD_ACTIVE)
   1653   1.26  augustss 			break;
   1654   1.67  augustss 
   1655   1.64  augustss 		status = nstatus;
   1656   1.88   tsutsui 		if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) !=
   1657   1.88   tsutsui 			UHCI_TD_PID_SETUP)
   1658   1.26  augustss 			actlen += UHCI_TD_GET_ACTLEN(status);
   1659  1.176   mycroft 		else {
   1660  1.176   mycroft 			/*
   1661  1.176   mycroft 			 * UHCI will report CRCTO in addition to a STALL or NAK
   1662  1.176   mycroft 			 * for a SETUP transaction.  See section 3.2.2, "TD
   1663  1.176   mycroft 			 * CONTROL AND STATUS".
   1664  1.176   mycroft 			 */
   1665  1.176   mycroft 			if (status & (UHCI_TD_STALLED | UHCI_TD_NAK))
   1666  1.176   mycroft 				status &= ~UHCI_TD_CRCTO;
   1667  1.176   mycroft 		}
   1668    1.1  augustss 	}
   1669   1.38  augustss 	/* If there are left over TDs we need to update the toggle. */
   1670   1.63  augustss 	if (std != NULL)
   1671   1.88   tsutsui 		upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token));
   1672   1.38  augustss 
   1673    1.1  augustss 	status &= UHCI_TD_ERROR;
   1674  1.277  pgoyette 	DPRINTFN(10, "actlen=%jd, status=0x%jx", actlen, status, 0, 0);
   1675  1.268     skrll 	xfer->ux_actlen = actlen;
   1676    1.1  augustss 	if (status != 0) {
   1677  1.122        tv 
   1678  1.268     skrll 		DPRINTFN((status == UHCI_TD_STALLED) * 10,
   1679  1.277  pgoyette 		    "error, addr=%jd, endpt=0x%02jx",
   1680  1.268     skrll 		    xfer->ux_pipe->up_dev->ud_addr,
   1681  1.268     skrll 		    xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress,
   1682  1.268     skrll 		    0, 0);
   1683  1.268     skrll 		DPRINTFN((status == UHCI_TD_STALLED) * 10,
   1684  1.277  pgoyette 		    "bitstuff=%jd crcto   =%jd nak     =%jd babble  =%jd",
   1685  1.268     skrll 		    !!(status & UHCI_TD_BITSTUFF),
   1686  1.268     skrll 		    !!(status & UHCI_TD_CRCTO),
   1687  1.268     skrll 		    !!(status & UHCI_TD_NAK),
   1688  1.268     skrll 		    !!(status & UHCI_TD_BABBLE));
   1689  1.268     skrll 		DPRINTFN((status == UHCI_TD_STALLED) * 10,
   1690  1.277  pgoyette 		    "dbuffer =%jd stalled =%jd active  =%jd",
   1691  1.268     skrll 		    !!(status & UHCI_TD_DBUFFER),
   1692  1.268     skrll 		    !!(status & UHCI_TD_STALLED),
   1693  1.268     skrll 		    !!(status & UHCI_TD_ACTIVE),
   1694  1.268     skrll 		    0);
   1695  1.122        tv 
   1696    1.1  augustss 		if (status == UHCI_TD_STALLED)
   1697  1.268     skrll 			xfer->ux_status = USBD_STALLED;
   1698    1.1  augustss 		else
   1699  1.268     skrll 			xfer->ux_status = USBD_IOERROR; /* more info XXX */
   1700    1.1  augustss 	} else {
   1701  1.268     skrll 		xfer->ux_status = USBD_NORMAL_COMPLETION;
   1702    1.1  augustss 	}
   1703  1.140  augustss 
   1704  1.140  augustss  end:
   1705  1.268     skrll 	uhci_del_intr_list(sc, ux);
   1706  1.268     skrll 	if (cqp)
   1707  1.268     skrll 		TAILQ_INSERT_TAIL(cqp, ux, ux_list);
   1708  1.268     skrll 
   1709  1.281       mrg 	KASSERT(polling || mutex_owned(&sc->sc_lock));
   1710  1.277  pgoyette 	DPRINTFN(12, "ux=%#jx done", (uintptr_t)ux, 0, 0, 0);
   1711    1.1  augustss }
   1712    1.1  augustss 
   1713   1.13  augustss /*
   1714   1.13  augustss  * Called when a request does not complete.
   1715   1.13  augustss  */
   1716    1.1  augustss void
   1717  1.119  augustss uhci_timeout(void *addr)
   1718    1.1  augustss {
   1719  1.281       mrg 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1720  1.268     skrll 	struct usbd_xfer *xfer = addr;
   1721  1.268     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   1722  1.281       mrg 	struct usbd_device *dev = xfer->ux_pipe->up_dev;
   1723  1.153  augustss 
   1724  1.281       mrg 	DPRINTF("xfer %#jx", (uintptr_t)xfer, 0, 0, 0);
   1725  1.153  augustss 
   1726  1.281       mrg 	mutex_enter(&sc->sc_lock);
   1727  1.281       mrg 	if (!sc->sc_dying && xfer->ux_status == USBD_IN_PROGRESS)
   1728  1.281       mrg 		usb_add_task(dev, &xfer->ux_aborttask, USB_TASKQ_HC);
   1729  1.281       mrg 	mutex_exit(&sc->sc_lock);
   1730  1.153  augustss }
   1731   1.51  augustss 
   1732  1.153  augustss void
   1733  1.153  augustss uhci_timeout_task(void *addr)
   1734  1.153  augustss {
   1735  1.268     skrll 	struct usbd_xfer *xfer = addr;
   1736  1.268     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   1737  1.268     skrll 
   1738  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1739  1.153  augustss 
   1740  1.277  pgoyette 	DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0);
   1741   1.67  augustss 
   1742  1.248       mrg 	mutex_enter(&sc->sc_lock);
   1743  1.153  augustss 	uhci_abort_xfer(xfer, USBD_TIMEOUT);
   1744  1.248       mrg 	mutex_exit(&sc->sc_lock);
   1745    1.1  augustss }
   1746    1.1  augustss 
   1747    1.8  augustss void
   1748  1.119  augustss uhci_poll(struct usbd_bus *bus)
   1749    1.8  augustss {
   1750  1.268     skrll 	uhci_softc_t *sc = UHCI_BUS2SC(bus);
   1751    1.8  augustss 
   1752  1.248       mrg 	if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) {
   1753  1.248       mrg 		mutex_spin_enter(&sc->sc_intr_lock);
   1754  1.141  augustss 		uhci_intr1(sc);
   1755  1.248       mrg 		mutex_spin_exit(&sc->sc_intr_lock);
   1756  1.248       mrg 	}
   1757    1.8  augustss }
   1758    1.8  augustss 
   1759    1.1  augustss void
   1760  1.119  augustss uhci_reset(uhci_softc_t *sc)
   1761    1.1  augustss {
   1762    1.1  augustss 	int n;
   1763    1.1  augustss 
   1764    1.1  augustss 	UHCICMD(sc, UHCI_CMD_HCRESET);
   1765    1.1  augustss 	/* The reset bit goes low when the controller is done. */
   1766  1.152  augustss 	for (n = 0; n < UHCI_RESET_TIMEOUT &&
   1767    1.1  augustss 		    (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++)
   1768   1.92  augustss 		usb_delay_ms(&sc->sc_bus, 1);
   1769    1.1  augustss 	if (n >= UHCI_RESET_TIMEOUT)
   1770  1.152  augustss 		printf("%s: controller did not reset\n",
   1771  1.216  drochner 		       device_xname(sc->sc_dev));
   1772    1.1  augustss }
   1773    1.1  augustss 
   1774   1.16  augustss usbd_status
   1775  1.249  drochner uhci_run(uhci_softc_t *sc, int run, int locked)
   1776    1.1  augustss {
   1777  1.248       mrg 	int n, running;
   1778  1.268     skrll 	uint16_t cmd;
   1779  1.268     skrll 
   1780  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1781    1.1  augustss 
   1782    1.1  augustss 	run = run != 0;
   1783  1.249  drochner 	if (!locked)
   1784  1.249  drochner 		mutex_spin_enter(&sc->sc_intr_lock);
   1785  1.268     skrll 
   1786  1.277  pgoyette 	DPRINTF("setting run=%jd", run, 0, 0, 0);
   1787   1.71  augustss 	cmd = UREAD2(sc, UHCI_CMD);
   1788   1.71  augustss 	if (run)
   1789   1.71  augustss 		cmd |= UHCI_CMD_RS;
   1790   1.71  augustss 	else
   1791   1.71  augustss 		cmd &= ~UHCI_CMD_RS;
   1792   1.71  augustss 	UHCICMD(sc, cmd);
   1793  1.267     skrll 	for (n = 0; n < 10; n++) {
   1794    1.1  augustss 		running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH);
   1795    1.1  augustss 		/* return when we've entered the state we want */
   1796    1.1  augustss 		if (run == running) {
   1797  1.249  drochner 			if (!locked)
   1798  1.249  drochner 				mutex_spin_exit(&sc->sc_intr_lock);
   1799  1.277  pgoyette 			DPRINTF("done cmd=0x%jx sts=0x%jx",
   1800  1.268     skrll 			    UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 0, 0);
   1801  1.268     skrll 			return USBD_NORMAL_COMPLETION;
   1802    1.1  augustss 		}
   1803  1.248       mrg 		usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock);
   1804    1.1  augustss 	}
   1805  1.249  drochner 	if (!locked)
   1806  1.249  drochner 		mutex_spin_exit(&sc->sc_intr_lock);
   1807  1.216  drochner 	printf("%s: cannot %s\n", device_xname(sc->sc_dev),
   1808   1.14  augustss 	       run ? "start" : "stop");
   1809  1.268     skrll 	return USBD_IOERROR;
   1810    1.1  augustss }
   1811    1.1  augustss 
   1812    1.1  augustss /*
   1813    1.1  augustss  * Memory management routines.
   1814    1.1  augustss  *  uhci_alloc_std allocates TDs
   1815    1.1  augustss  *  uhci_alloc_sqh allocates QHs
   1816    1.7  augustss  * These two routines do their own free list management,
   1817    1.1  augustss  * partly for speed, partly because allocating DMAable memory
   1818  1.268     skrll  * has page size granularity so much memory would be wasted if
   1819   1.16  augustss  * only one TD/QH (32 bytes) was placed in each allocated chunk.
   1820    1.1  augustss  */
   1821    1.1  augustss 
   1822    1.1  augustss uhci_soft_td_t *
   1823  1.119  augustss uhci_alloc_std(uhci_softc_t *sc)
   1824    1.1  augustss {
   1825    1.1  augustss 	uhci_soft_td_t *std;
   1826   1.63  augustss 	usbd_status err;
   1827   1.42  augustss 	int i, offs;
   1828    1.7  augustss 	usb_dma_t dma;
   1829    1.1  augustss 
   1830  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1831  1.268     skrll 
   1832  1.268     skrll 	mutex_enter(&sc->sc_lock);
   1833   1.63  augustss 	if (sc->sc_freetds == NULL) {
   1834  1.268     skrll 		DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
   1835  1.268     skrll 		mutex_exit(&sc->sc_lock);
   1836  1.268     skrll 
   1837   1.63  augustss 		err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK,
   1838   1.63  augustss 			  UHCI_TD_ALIGN, &dma);
   1839   1.63  augustss 		if (err)
   1840  1.268     skrll 			return NULL;
   1841  1.268     skrll 
   1842  1.268     skrll 		mutex_enter(&sc->sc_lock);
   1843  1.248       mrg 		for (i = 0; i < UHCI_STD_CHUNK; i++) {
   1844   1.42  augustss 			offs = i * UHCI_STD_SIZE;
   1845  1.159  augustss 			std = KERNADDR(&dma, offs);
   1846  1.160  augustss 			std->physaddr = DMAADDR(&dma, offs);
   1847  1.223    bouyer 			std->dma = dma;
   1848  1.223    bouyer 			std->offs = offs;
   1849   1.42  augustss 			std->link.std = sc->sc_freetds;
   1850    1.1  augustss 			sc->sc_freetds = std;
   1851    1.1  augustss 		}
   1852    1.1  augustss 	}
   1853    1.1  augustss 	std = sc->sc_freetds;
   1854   1.42  augustss 	sc->sc_freetds = std->link.std;
   1855  1.268     skrll 	mutex_exit(&sc->sc_lock);
   1856  1.268     skrll 
   1857   1.42  augustss 	memset(&std->td, 0, sizeof(uhci_td_t));
   1858  1.268     skrll 
   1859    1.1  augustss 	return std;
   1860    1.1  augustss }
   1861    1.1  augustss 
   1862  1.268     skrll #define TD_IS_FREE 0x12345678
   1863  1.268     skrll 
   1864    1.1  augustss void
   1865  1.268     skrll uhci_free_std_locked(uhci_softc_t *sc, uhci_soft_td_t *std)
   1866    1.1  augustss {
   1867  1.268     skrll 	KASSERT(mutex_owned(&sc->sc_lock));
   1868  1.268     skrll 
   1869    1.7  augustss #ifdef DIAGNOSTIC
   1870   1.88   tsutsui 	if (le32toh(std->td.td_token) == TD_IS_FREE) {
   1871  1.268     skrll 		printf("%s: freeing free TD %p\n", __func__, std);
   1872    1.7  augustss 		return;
   1873    1.7  augustss 	}
   1874   1.88   tsutsui 	std->td.td_token = htole32(TD_IS_FREE);
   1875    1.7  augustss #endif
   1876  1.268     skrll 
   1877   1.42  augustss 	std->link.std = sc->sc_freetds;
   1878    1.1  augustss 	sc->sc_freetds = std;
   1879    1.1  augustss }
   1880    1.1  augustss 
   1881  1.268     skrll void
   1882  1.268     skrll uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std)
   1883  1.268     skrll {
   1884  1.268     skrll 	mutex_enter(&sc->sc_lock);
   1885  1.268     skrll 	uhci_free_std_locked(sc, std);
   1886  1.268     skrll 	mutex_exit(&sc->sc_lock);
   1887  1.268     skrll }
   1888  1.268     skrll 
   1889    1.1  augustss uhci_soft_qh_t *
   1890  1.119  augustss uhci_alloc_sqh(uhci_softc_t *sc)
   1891    1.1  augustss {
   1892    1.1  augustss 	uhci_soft_qh_t *sqh;
   1893   1.63  augustss 	usbd_status err;
   1894    1.1  augustss 	int i, offs;
   1895    1.7  augustss 	usb_dma_t dma;
   1896    1.1  augustss 
   1897  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1898  1.268     skrll 
   1899  1.268     skrll 	mutex_enter(&sc->sc_lock);
   1900   1.63  augustss 	if (sc->sc_freeqhs == NULL) {
   1901  1.268     skrll 		DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
   1902  1.268     skrll 		mutex_exit(&sc->sc_lock);
   1903  1.268     skrll 
   1904   1.63  augustss 		err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK,
   1905   1.63  augustss 			  UHCI_QH_ALIGN, &dma);
   1906   1.63  augustss 		if (err)
   1907  1.268     skrll 			return NULL;
   1908  1.268     skrll 
   1909  1.268     skrll 		mutex_enter(&sc->sc_lock);
   1910  1.267     skrll 		for (i = 0; i < UHCI_SQH_CHUNK; i++) {
   1911   1.42  augustss 			offs = i * UHCI_SQH_SIZE;
   1912  1.159  augustss 			sqh = KERNADDR(&dma, offs);
   1913  1.160  augustss 			sqh->physaddr = DMAADDR(&dma, offs);
   1914  1.223    bouyer 			sqh->dma = dma;
   1915  1.223    bouyer 			sqh->offs = offs;
   1916   1.42  augustss 			sqh->hlink = sc->sc_freeqhs;
   1917    1.1  augustss 			sc->sc_freeqhs = sqh;
   1918    1.1  augustss 		}
   1919    1.1  augustss 	}
   1920    1.1  augustss 	sqh = sc->sc_freeqhs;
   1921   1.42  augustss 	sc->sc_freeqhs = sqh->hlink;
   1922  1.268     skrll 	mutex_exit(&sc->sc_lock);
   1923  1.268     skrll 
   1924   1.42  augustss 	memset(&sqh->qh, 0, sizeof(uhci_qh_t));
   1925  1.268     skrll 
   1926  1.268     skrll 	return sqh;
   1927    1.1  augustss }
   1928    1.1  augustss 
   1929    1.1  augustss void
   1930  1.119  augustss uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   1931    1.1  augustss {
   1932  1.268     skrll 	KASSERT(mutex_owned(&sc->sc_lock));
   1933  1.268     skrll 
   1934   1.42  augustss 	sqh->hlink = sc->sc_freeqhs;
   1935    1.1  augustss 	sc->sc_freeqhs = sqh;
   1936    1.1  augustss }
   1937    1.1  augustss 
   1938  1.268     skrll #if 0
   1939    1.1  augustss void
   1940  1.119  augustss uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std,
   1941  1.119  augustss 		    uhci_soft_td_t *stdend)
   1942    1.1  augustss {
   1943    1.1  augustss 	uhci_soft_td_t *p;
   1944  1.256   tsutsui 	uint32_t td_link;
   1945    1.1  augustss 
   1946  1.223    bouyer 	/*
   1947  1.223    bouyer 	 * to avoid race condition with the controller which may be looking
   1948  1.223    bouyer 	 * at this chain, we need to first invalidate all links, and
   1949  1.223    bouyer 	 * then wait for the controller to move to another queue
   1950  1.223    bouyer 	 */
   1951  1.223    bouyer 	for (p = std; p != stdend; p = p->link.std) {
   1952  1.223    bouyer 		usb_syncmem(&p->dma,
   1953  1.223    bouyer 		    p->offs + offsetof(uhci_td_t, td_link),
   1954  1.223    bouyer 		    sizeof(p->td.td_link),
   1955  1.223    bouyer 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   1956  1.256   tsutsui 		td_link = le32toh(p->td.td_link);
   1957  1.256   tsutsui 		usb_syncmem(&p->dma,
   1958  1.256   tsutsui 		    p->offs + offsetof(uhci_td_t, td_link),
   1959  1.256   tsutsui 		    sizeof(p->td.td_link),
   1960  1.256   tsutsui 		    BUS_DMASYNC_PREREAD);
   1961  1.256   tsutsui 		if ((td_link & UHCI_PTR_T) == 0) {
   1962  1.255   tsutsui 			p->td.td_link = htole32(UHCI_PTR_T);
   1963  1.223    bouyer 			usb_syncmem(&p->dma,
   1964  1.223    bouyer 			    p->offs + offsetof(uhci_td_t, td_link),
   1965  1.223    bouyer 			    sizeof(p->td.td_link),
   1966  1.223    bouyer 			    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   1967  1.223    bouyer 		}
   1968  1.223    bouyer 	}
   1969  1.223    bouyer 	delay(UHCI_QH_REMOVE_DELAY);
   1970  1.223    bouyer 
   1971    1.1  augustss 	for (; std != stdend; std = p) {
   1972   1.42  augustss 		p = std->link.std;
   1973    1.1  augustss 		uhci_free_std(sc, std);
   1974    1.1  augustss 	}
   1975    1.1  augustss }
   1976  1.268     skrll #endif
   1977  1.268     skrll 
   1978  1.268     skrll int
   1979  1.268     skrll uhci_alloc_std_chain(uhci_softc_t *sc, struct usbd_xfer *xfer, int len,
   1980  1.268     skrll     int rd, uhci_soft_td_t **sp)
   1981  1.268     skrll {
   1982  1.268     skrll 	struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
   1983  1.268     skrll 	uint16_t flags = xfer->ux_flags;
   1984  1.268     skrll 	uhci_soft_td_t *p;
   1985  1.268     skrll 
   1986  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   1987    1.1  augustss 
   1988  1.277  pgoyette 	DPRINTFN(8, "xfer=%#jx pipe=%#jx", (uintptr_t)xfer,
   1989  1.277  pgoyette 	    (uintptr_t)xfer->ux_pipe, 0, 0);
   1990  1.248       mrg 
   1991  1.268     skrll 	ASSERT_SLEEPABLE();
   1992  1.268     skrll 	KASSERT(sp);
   1993  1.248       mrg 
   1994  1.268     skrll 	int maxp = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize);
   1995    1.1  augustss 	if (maxp == 0) {
   1996  1.268     skrll 		printf("%s: maxp=0\n", __func__);
   1997  1.268     skrll 		return EINVAL;
   1998    1.1  augustss 	}
   1999  1.268     skrll 	size_t ntd = (len + maxp - 1) / maxp;
   2000  1.268     skrll 	if (!rd && (flags & USBD_FORCE_SHORT_XFER)) {
   2001   1.73  augustss 		ntd++;
   2002  1.268     skrll 	}
   2003  1.277  pgoyette 	DPRINTFN(10, "maxp=%jd ntd=%jd", maxp, ntd, 0, 0);
   2004  1.268     skrll 
   2005  1.268     skrll 	uxfer->ux_stds = NULL;
   2006  1.268     skrll 	uxfer->ux_nstd = ntd;
   2007   1.73  augustss 	if (ntd == 0) {
   2008  1.268     skrll 		*sp = NULL;
   2009  1.268     skrll 		DPRINTF("ntd=0", 0, 0, 0, 0);
   2010  1.268     skrll 		return 0;
   2011   1.73  augustss 	}
   2012  1.268     skrll 	uxfer->ux_stds = kmem_alloc(sizeof(uhci_soft_td_t *) * ntd,
   2013  1.268     skrll 	    KM_SLEEP);
   2014  1.268     skrll 
   2015  1.276     skrll 	for (int i = 0; i < ntd; i++) {
   2016    1.1  augustss 		p = uhci_alloc_std(sc);
   2017   1.63  augustss 		if (p == NULL) {
   2018  1.276     skrll 			if (i != 0) {
   2019  1.276     skrll 				uxfer->ux_nstd = i;
   2020  1.276     skrll 				uhci_free_stds(sc, uxfer);
   2021  1.276     skrll 			}
   2022  1.268     skrll 			kmem_free(uxfer->ux_stds,
   2023  1.268     skrll 			    sizeof(uhci_soft_td_t *) * ntd);
   2024  1.268     skrll 			return ENOMEM;
   2025  1.268     skrll 		}
   2026  1.268     skrll 		uxfer->ux_stds[i] = p;
   2027    1.1  augustss 	}
   2028    1.1  augustss 
   2029  1.268     skrll 	*sp = uxfer->ux_stds[0];
   2030  1.268     skrll 
   2031  1.268     skrll 	return 0;
   2032   1.38  augustss }
   2033   1.38  augustss 
   2034  1.268     skrll Static void
   2035  1.268     skrll uhci_free_stds(uhci_softc_t *sc, struct uhci_xfer *ux)
   2036   1.38  augustss {
   2037  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2038   1.38  augustss 
   2039  1.277  pgoyette 	DPRINTFN(8, "ux=%#jx", (uintptr_t)ux, 0, 0, 0);
   2040   1.16  augustss 
   2041  1.248       mrg 	mutex_enter(&sc->sc_lock);
   2042  1.268     skrll 	for (size_t i = 0; i < ux->ux_nstd; i++) {
   2043  1.268     skrll 		uhci_soft_td_t *std = ux->ux_stds[i];
   2044  1.268     skrll #ifdef DIAGNOSTIC
   2045  1.268     skrll 		if (le32toh(std->td.td_token) == TD_IS_FREE) {
   2046  1.268     skrll 			printf("%s: freeing free TD %p\n", __func__, std);
   2047  1.268     skrll 			return;
   2048  1.268     skrll 		}
   2049  1.268     skrll 		std->td.td_token = htole32(TD_IS_FREE);
   2050  1.268     skrll #endif
   2051  1.268     skrll 		ux->ux_stds[i]->link.std = sc->sc_freetds;
   2052  1.268     skrll 		sc->sc_freetds = std;
   2053  1.268     skrll 	}
   2054  1.248       mrg 	mutex_exit(&sc->sc_lock);
   2055  1.268     skrll }
   2056   1.52  augustss 
   2057   1.16  augustss 
   2058  1.268     skrll Static void
   2059  1.268     skrll uhci_reset_std_chain(uhci_softc_t *sc, struct usbd_xfer *xfer,
   2060  1.268     skrll     int length, int isread, int *toggle, uhci_soft_td_t **lstd)
   2061   1.16  augustss {
   2062  1.268     skrll 	struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
   2063  1.268     skrll 	struct usbd_pipe *pipe = xfer->ux_pipe;
   2064  1.268     skrll 	usb_dma_t *dma = &xfer->ux_dmabuf;
   2065  1.268     skrll 	uint16_t flags = xfer->ux_flags;
   2066  1.268     skrll 	uhci_soft_td_t *std, *prev;
   2067  1.268     skrll 	int len = length;
   2068  1.268     skrll 	int tog = *toggle;
   2069  1.268     skrll 	int maxp;
   2070  1.268     skrll 	uint32_t status;
   2071  1.268     skrll 	size_t i;
   2072  1.268     skrll 
   2073  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2074  1.277  pgoyette 	DPRINTFN(8, "xfer=%#jx len %jd isread %jd toggle %jd", (uintptr_t)xfer,
   2075  1.268     skrll 	    len, isread, *toggle);
   2076    1.1  augustss 
   2077  1.268     skrll 	KASSERT(len != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER)));
   2078    1.1  augustss 
   2079  1.268     skrll 	maxp = UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize);
   2080  1.268     skrll 	KASSERT(maxp != 0);
   2081   1.82  augustss 
   2082  1.268     skrll 	int addr = xfer->ux_pipe->up_dev->ud_addr;
   2083  1.268     skrll 	int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;
   2084    1.1  augustss 
   2085  1.268     skrll 	status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE);
   2086  1.268     skrll 	if (pipe->up_dev->ud_speed == USB_SPEED_LOW)
   2087  1.268     skrll 		status |= UHCI_TD_LS;
   2088  1.268     skrll 	if (flags & USBD_SHORT_XFER_OK)
   2089  1.268     skrll 		status |= UHCI_TD_SPD;
   2090  1.268     skrll 	usb_syncmem(dma, 0, len,
   2091  1.268     skrll 	    isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
   2092  1.268     skrll 	std = prev = NULL;
   2093  1.268     skrll 	for (i = 0; len != 0 && i < uxfer->ux_nstd; i++, prev = std) {
   2094  1.268     skrll 		int l = len;
   2095  1.268     skrll 		std = uxfer->ux_stds[i];
   2096  1.268     skrll 		if (l > maxp)
   2097  1.268     skrll 			l = maxp;
   2098  1.268     skrll 
   2099  1.268     skrll 		if (prev) {
   2100  1.268     skrll 			prev->link.std = std;
   2101  1.268     skrll 			prev->td.td_link = htole32(
   2102  1.268     skrll 			    std->physaddr | UHCI_PTR_VF | UHCI_PTR_TD
   2103  1.268     skrll 			    );
   2104  1.268     skrll 			usb_syncmem(&prev->dma, prev->offs, sizeof(prev->td),
   2105  1.268     skrll 			    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2106  1.268     skrll 		}
   2107  1.268     skrll 
   2108  1.268     skrll 		usb_syncmem(&std->dma, std->offs, sizeof(std->td),
   2109  1.268     skrll 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   2110  1.268     skrll 
   2111  1.268     skrll 		std->td.td_link = htole32(UHCI_PTR_T | UHCI_PTR_VF | UHCI_PTR_TD);
   2112  1.268     skrll 		std->td.td_status = htole32(status);
   2113  1.268     skrll 		std->td.td_token = htole32(
   2114  1.268     skrll 		    UHCI_TD_SET_ENDPT(UE_GET_ADDR(endpt)) |
   2115  1.268     skrll 		    UHCI_TD_SET_DEVADDR(addr) |
   2116  1.268     skrll 		    UHCI_TD_SET_PID(isread ? UHCI_TD_PID_IN : UHCI_TD_PID_OUT) |
   2117  1.268     skrll 		    UHCI_TD_SET_DT(tog) |
   2118  1.268     skrll 		    UHCI_TD_SET_MAXLEN(l)
   2119  1.268     skrll 		    );
   2120  1.268     skrll 		std->td.td_buffer = htole32(DMAADDR(dma, i * maxp));
   2121  1.268     skrll 
   2122  1.268     skrll 		std->link.std = NULL;
   2123  1.268     skrll 
   2124  1.268     skrll 		usb_syncmem(&std->dma, std->offs, sizeof(std->td),
   2125  1.268     skrll 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2126  1.268     skrll 		tog ^= 1;
   2127  1.268     skrll 
   2128  1.268     skrll 		len -= l;
   2129  1.268     skrll 	}
   2130  1.268     skrll 	KASSERTMSG(len == 0, "xfer %p alen %d len %d mps %d ux_nqtd %zu i %zu",
   2131  1.268     skrll 	    xfer, length, len, maxp, uxfer->ux_nstd, i);
   2132  1.268     skrll 
   2133  1.268     skrll 	if (!isread &&
   2134  1.268     skrll 	    (flags & USBD_FORCE_SHORT_XFER) &&
   2135  1.268     skrll 	    length % maxp == 0) {
   2136  1.268     skrll 		/* Force a 0 length transfer at the end. */
   2137  1.268     skrll 		KASSERTMSG(i < uxfer->ux_nstd, "i=%zu nstd=%zu", i,
   2138  1.268     skrll 		    uxfer->ux_nstd);
   2139  1.268     skrll 		std = uxfer->ux_stds[i++];
   2140  1.268     skrll 
   2141  1.268     skrll 		std->td.td_link = htole32(UHCI_PTR_T | UHCI_PTR_VF | UHCI_PTR_TD);
   2142  1.268     skrll 		std->td.td_status = htole32(status);
   2143  1.268     skrll 		std->td.td_token = htole32(
   2144  1.268     skrll 		    UHCI_TD_SET_ENDPT(UE_GET_ADDR(endpt)) |
   2145  1.268     skrll 		    UHCI_TD_SET_DEVADDR(addr) |
   2146  1.268     skrll 		    UHCI_TD_SET_PID(UHCI_TD_PID_OUT) |
   2147  1.268     skrll 		    UHCI_TD_SET_DT(tog) |
   2148  1.268     skrll 		    UHCI_TD_SET_MAXLEN(0)
   2149  1.268     skrll 		    );
   2150  1.268     skrll 		std->td.td_buffer = 0;
   2151  1.268     skrll 		usb_syncmem(&std->dma, std->offs, sizeof(std->td),
   2152  1.268     skrll 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2153  1.268     skrll 
   2154  1.268     skrll 		std->link.std = NULL;
   2155  1.268     skrll 		if (prev) {
   2156  1.268     skrll 			prev->link.std = std;
   2157  1.268     skrll 			prev->td.td_link = htole32(
   2158  1.268     skrll 			    std->physaddr | UHCI_PTR_VF | UHCI_PTR_TD
   2159  1.268     skrll 			    );
   2160  1.268     skrll 			usb_syncmem(&prev->dma, prev->offs, sizeof(prev->td),
   2161  1.268     skrll 			    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2162  1.268     skrll 		}
   2163  1.268     skrll 		tog ^= 1;
   2164  1.268     skrll 	}
   2165  1.268     skrll 	*lstd = std;
   2166  1.268     skrll 	*toggle = tog;
   2167  1.268     skrll }
   2168  1.268     skrll 
   2169  1.268     skrll void
   2170  1.268     skrll uhci_device_clear_toggle(struct usbd_pipe *pipe)
   2171  1.268     skrll {
   2172  1.268     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
   2173  1.268     skrll 	upipe->nexttoggle = 0;
   2174  1.268     skrll }
   2175  1.268     skrll 
   2176  1.268     skrll void
   2177  1.268     skrll uhci_noop(struct usbd_pipe *pipe)
   2178  1.268     skrll {
   2179  1.268     skrll }
   2180  1.268     skrll 
   2181  1.268     skrll int
   2182  1.268     skrll uhci_device_bulk_init(struct usbd_xfer *xfer)
   2183  1.268     skrll {
   2184  1.268     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2185  1.268     skrll 	struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
   2186  1.268     skrll 	usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc;
   2187  1.268     skrll 	int endpt = ed->bEndpointAddress;
   2188  1.268     skrll 	int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
   2189  1.268     skrll 	int len = xfer->ux_bufsize;
   2190  1.268     skrll 	int err = 0;
   2191  1.268     skrll 
   2192  1.268     skrll 
   2193  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2194  1.277  pgoyette 	DPRINTFN(3, "xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, len,
   2195  1.277  pgoyette 	    xfer->ux_flags, 0);
   2196  1.268     skrll 
   2197  1.268     skrll 	if (sc->sc_dying)
   2198  1.268     skrll 		return USBD_IOERROR;
   2199  1.268     skrll 
   2200  1.268     skrll 	KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
   2201  1.268     skrll 
   2202  1.268     skrll 	uxfer->ux_type = UX_BULK;
   2203  1.268     skrll 	err = uhci_alloc_std_chain(sc, xfer, len, isread, &uxfer->ux_stdstart);
   2204  1.268     skrll 	if (err)
   2205  1.268     skrll 		return err;
   2206  1.268     skrll 
   2207  1.268     skrll #ifdef UHCI_DEBUG
   2208  1.268     skrll 	if (uhcidebug >= 10) {
   2209  1.268     skrll 		DPRINTF("--- dump start ---", 0, 0, 0, 0);
   2210  1.268     skrll 		uhci_dump_tds(uxfer->ux_stdstart);
   2211  1.268     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   2212  1.268     skrll 	}
   2213  1.268     skrll #endif
   2214  1.268     skrll 
   2215  1.268     skrll 	return 0;
   2216  1.268     skrll }
   2217  1.268     skrll 
   2218  1.268     skrll Static void
   2219  1.268     skrll uhci_device_bulk_fini(struct usbd_xfer *xfer)
   2220  1.268     skrll {
   2221  1.268     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2222  1.268     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   2223  1.268     skrll 
   2224  1.268     skrll 	KASSERT(ux->ux_type == UX_BULK);
   2225  1.268     skrll 
   2226  1.276     skrll 	if (ux->ux_nstd) {
   2227  1.276     skrll 		uhci_free_stds(sc, ux);
   2228  1.268     skrll 		kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd);
   2229  1.276     skrll 	}
   2230  1.268     skrll }
   2231  1.268     skrll 
   2232  1.268     skrll usbd_status
   2233  1.268     skrll uhci_device_bulk_transfer(struct usbd_xfer *xfer)
   2234  1.268     skrll {
   2235  1.268     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2236  1.268     skrll 	usbd_status err;
   2237  1.268     skrll 
   2238  1.268     skrll 	/* Insert last in queue. */
   2239  1.248       mrg 	mutex_enter(&sc->sc_lock);
   2240  1.268     skrll 	err = usb_insert_transfer(xfer);
   2241  1.268     skrll 	mutex_exit(&sc->sc_lock);
   2242  1.268     skrll 	if (err)
   2243  1.268     skrll 		return err;
   2244  1.268     skrll 
   2245  1.268     skrll 	/*
   2246  1.268     skrll 	 * Pipe isn't running (otherwise err would be USBD_INPROG),
   2247  1.268     skrll 	 * so start it first.
   2248  1.268     skrll 	 */
   2249  1.268     skrll 	return uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
   2250  1.268     skrll }
   2251  1.248       mrg 
   2252  1.268     skrll usbd_status
   2253  1.268     skrll uhci_device_bulk_start(struct usbd_xfer *xfer)
   2254  1.268     skrll {
   2255  1.268     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   2256  1.268     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   2257  1.268     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2258  1.268     skrll 	uhci_soft_td_t *data, *dataend;
   2259  1.268     skrll 	uhci_soft_qh_t *sqh;
   2260  1.268     skrll 	int len;
   2261  1.268     skrll 	int endpt;
   2262  1.268     skrll 	int isread;
   2263  1.268     skrll 
   2264  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2265  1.277  pgoyette 	DPRINTFN(3, "xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer,
   2266  1.277  pgoyette 	    xfer->ux_length, xfer->ux_flags, 0);
   2267  1.268     skrll 
   2268  1.268     skrll 	if (sc->sc_dying)
   2269  1.268     skrll 		return USBD_IOERROR;
   2270  1.268     skrll 
   2271  1.268     skrll 	KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
   2272  1.268     skrll 	KASSERT(xfer->ux_length <= xfer->ux_bufsize);
   2273  1.268     skrll 
   2274  1.268     skrll 	len = xfer->ux_length;
   2275  1.268     skrll 	endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
   2276   1.45  augustss 	isread = UE_GET_DIR(endpt) == UE_DIR_IN;
   2277  1.268     skrll 	sqh = upipe->bulk.sqh;
   2278    1.1  augustss 
   2279  1.268     skrll 	/* Take lock here to protect nexttoggle */
   2280  1.268     skrll 	mutex_enter(&sc->sc_lock);
   2281    1.1  augustss 
   2282  1.268     skrll 	uhci_reset_std_chain(sc, xfer, len, isread, &upipe->nexttoggle,
   2283  1.268     skrll 	    &dataend);
   2284  1.268     skrll 
   2285  1.268     skrll 	data = ux->ux_stdstart;
   2286  1.268     skrll 	ux->ux_stdend = dataend;
   2287   1.88   tsutsui 	dataend->td.td_status |= htole32(UHCI_TD_IOC);
   2288  1.223    bouyer 	usb_syncmem(&dataend->dma,
   2289  1.223    bouyer 	    dataend->offs + offsetof(uhci_td_t, td_status),
   2290  1.223    bouyer 	    sizeof(dataend->td.td_status),
   2291  1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2292  1.223    bouyer 
   2293   1.59  augustss #ifdef UHCI_DEBUG
   2294  1.268     skrll 	if (uhcidebug >= 10) {
   2295  1.268     skrll 		DPRINTF("--- dump start ---", 0, 0, 0, 0);
   2296  1.268     skrll 		DPRINTFN(10, "before transfer", 0, 0, 0, 0);
   2297   1.55  augustss 		uhci_dump_tds(data);
   2298  1.268     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   2299    1.1  augustss 	}
   2300    1.1  augustss #endif
   2301    1.1  augustss 
   2302  1.268     skrll 	KASSERT(ux->ux_isdone);
   2303    1.7  augustss #ifdef DIAGNOSTIC
   2304  1.268     skrll 	ux->ux_isdone = false;
   2305    1.7  augustss #endif
   2306    1.1  augustss 
   2307   1.55  augustss 	sqh->elink = data;
   2308  1.121  augustss 	sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD);
   2309  1.223    bouyer 	/* uhci_add_bulk() will do usb_syncmem(sqh) */
   2310    1.1  augustss 
   2311    1.1  augustss 	uhci_add_bulk(sc, sqh);
   2312  1.268     skrll 	uhci_add_intr_list(sc, ux);
   2313    1.1  augustss 
   2314  1.268     skrll 	if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
   2315  1.268     skrll 		callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
   2316  1.268     skrll 			    uhci_timeout, xfer);
   2317   1.13  augustss 	}
   2318  1.268     skrll 	xfer->ux_status = USBD_IN_PROGRESS;
   2319  1.268     skrll 	mutex_exit(&sc->sc_lock);
   2320    1.1  augustss 
   2321  1.268     skrll 	return USBD_IN_PROGRESS;
   2322    1.1  augustss }
   2323    1.1  augustss 
   2324    1.1  augustss /* Abort a device bulk request. */
   2325    1.1  augustss void
   2326  1.268     skrll uhci_device_bulk_abort(struct usbd_xfer *xfer)
   2327    1.1  augustss {
   2328  1.268     skrll 	uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer);
   2329  1.248       mrg 
   2330  1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2331  1.248       mrg 
   2332  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2333  1.268     skrll 
   2334   1.66  augustss 	uhci_abort_xfer(xfer, USBD_CANCELLED);
   2335   1.33  augustss }
   2336   1.33  augustss 
   2337   1.92  augustss /*
   2338  1.281       mrg  * Cancel or timeout a device request.  We have two cases to deal with
   2339  1.281       mrg  *
   2340  1.281       mrg  * 1) A driver wants to stop scheduled or inflight transfers
   2341  1.281       mrg  * 2) A transfer has timed out
   2342  1.281       mrg  *
   2343  1.154  augustss  * It's impossible to guarantee that the requested transfer will not
   2344  1.281       mrg  * have (partially) happened since the hardware runs concurrently.
   2345  1.281       mrg  *
   2346  1.281       mrg  * Transfer state is protected by the bus lock and we set the transfer status
   2347  1.281       mrg  * as soon as either of the above happens (with bus lock held).
   2348  1.281       mrg  *
   2349  1.281       mrg  * To allow the hardware time to notice we simply wait.
   2350   1.92  augustss  */
   2351   1.33  augustss void
   2352  1.268     skrll uhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status)
   2353   1.33  augustss {
   2354  1.281       mrg 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2355  1.268     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   2356  1.268     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   2357  1.268     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2358   1.33  augustss 	uhci_soft_td_t *std;
   2359   1.65  augustss 
   2360  1.281       mrg 	KASSERTMSG((status == USBD_CANCELLED || status == USBD_TIMEOUT),
   2361  1.281       mrg 	    "invalid status for abort: %d", (int)status);
   2362  1.281       mrg 
   2363  1.277  pgoyette 	DPRINTFN(1,"xfer=%#jx, status=%jd", (uintptr_t)xfer, status, 0, 0);
   2364   1.33  augustss 
   2365  1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2366  1.268     skrll 	ASSERT_SLEEPABLE();
   2367  1.248       mrg 
   2368  1.281       mrg 	if (status == USBD_CANCELLED) {
   2369  1.281       mrg 		/*
   2370  1.281       mrg 		 * We are synchronously aborting.  Try to stop the
   2371  1.281       mrg 		 * callout and task, but if we can't, wait for them to
   2372  1.281       mrg 		 * complete.
   2373  1.281       mrg 		 */
   2374  1.281       mrg 		callout_halt(&xfer->ux_callout, &sc->sc_lock);
   2375  1.281       mrg 		usb_rem_task_wait(xfer->ux_pipe->up_dev, &xfer->ux_aborttask,
   2376  1.281       mrg 		    USB_TASKQ_HC, &sc->sc_lock);
   2377  1.281       mrg 	} else {
   2378  1.281       mrg 		/* Otherwise, we are timing out.  */
   2379  1.281       mrg 		KASSERT(status == USBD_TIMEOUT);
   2380  1.281       mrg 	}
   2381  1.281       mrg 
   2382  1.281       mrg 	/*
   2383  1.281       mrg 	 * The xfer cannot have been cancelled already.  It is the
   2384  1.281       mrg 	 * responsibility of the caller of usbd_abort_pipe not to try
   2385  1.281       mrg 	 * to abort a pipe multiple times, whether concurrently or
   2386  1.281       mrg 	 * sequentially.
   2387  1.281       mrg 	 */
   2388  1.281       mrg 	KASSERT(xfer->ux_status != USBD_CANCELLED);
   2389  1.281       mrg 
   2390  1.281       mrg 	/* Only the timeout, which runs only once, can time it out.  */
   2391  1.281       mrg 	KASSERT(xfer->ux_status != USBD_TIMEOUT);
   2392  1.281       mrg 
   2393  1.281       mrg 	/* If anyone else beat us, we're done.  */
   2394  1.281       mrg 	if (xfer->ux_status != USBD_IN_PROGRESS)
   2395  1.194  christos 		return;
   2396  1.281       mrg 
   2397  1.281       mrg 	/* We beat everyone else.  Claim the status.  */
   2398  1.281       mrg 	xfer->ux_status = status;
   2399   1.92  augustss 
   2400  1.153  augustss 	/*
   2401  1.281       mrg 	 * If we're dying, skip the hardware action and just notify the
   2402  1.281       mrg 	 * software that we're done.
   2403  1.188  augustss 	 */
   2404  1.281       mrg 	if (sc->sc_dying) {
   2405  1.281       mrg 		DPRINTFN(4, "xfer %#jx dying %ju", (uintptr_t)xfer,
   2406  1.281       mrg 		    xfer->ux_status, 0, 0);
   2407  1.281       mrg 		goto dying;
   2408  1.188  augustss 	}
   2409  1.188  augustss 
   2410  1.188  augustss 	/*
   2411  1.281       mrg 	 * HC Step 1: Make interrupt routine and hardware ignore xfer.
   2412  1.153  augustss 	 */
   2413  1.268     skrll 	uhci_del_intr_list(sc, ux);
   2414  1.268     skrll 
   2415  1.277  pgoyette 	DPRINTF("stop ux=%#jx", (uintptr_t)ux, 0, 0, 0);
   2416  1.268     skrll 	for (std = ux->ux_stdstart; std != NULL; std = std->link.std) {
   2417  1.223    bouyer 		usb_syncmem(&std->dma,
   2418  1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_status),
   2419  1.223    bouyer 		    sizeof(std->td.td_status),
   2420  1.223    bouyer 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   2421   1.92  augustss 		std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC));
   2422  1.223    bouyer 		usb_syncmem(&std->dma,
   2423  1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_status),
   2424  1.223    bouyer 		    sizeof(std->td.td_status),
   2425  1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2426  1.223    bouyer 	}
   2427   1.92  augustss 
   2428  1.162  augustss 	/*
   2429  1.281       mrg 	 * HC Step 2: Wait until we know hardware has finished any possible
   2430  1.281       mrg 	 * use of the xfer.
   2431  1.153  augustss 	 */
   2432  1.248       mrg 	/* Hardware finishes in 1ms */
   2433  1.268     skrll 	usb_delay_ms_locked(upipe->pipe.up_dev->ud_bus, 2, &sc->sc_lock);
   2434  1.162  augustss 
   2435  1.153  augustss 	/*
   2436  1.281       mrg 	 * HC Step 3: Notify completion to waiting xfers.
   2437  1.153  augustss 	 */
   2438  1.281       mrg dying:
   2439  1.100  augustss #ifdef DIAGNOSTIC
   2440  1.268     skrll 	ux->ux_isdone = true;
   2441  1.100  augustss #endif
   2442  1.106  augustss 	usb_transfer_complete(xfer);
   2443  1.281       mrg 	DPRINTFN(14, "end", 0, 0, 0, 0);
   2444  1.281       mrg 
   2445  1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2446    1.1  augustss }
   2447    1.1  augustss 
   2448    1.1  augustss /* Close a device bulk pipe. */
   2449    1.1  augustss void
   2450  1.268     skrll uhci_device_bulk_close(struct usbd_pipe *pipe)
   2451    1.1  augustss {
   2452  1.268     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
   2453  1.268     skrll 	uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
   2454    1.1  augustss 
   2455  1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2456  1.248       mrg 
   2457  1.268     skrll 	uhci_free_sqh(sc, upipe->bulk.sqh);
   2458  1.236  drochner 
   2459  1.268     skrll 	pipe->up_endpoint->ue_toggle = upipe->nexttoggle;
   2460  1.268     skrll }
   2461  1.268     skrll 
   2462  1.268     skrll int
   2463  1.268     skrll uhci_device_ctrl_init(struct usbd_xfer *xfer)
   2464  1.268     skrll {
   2465  1.268     skrll 	struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
   2466  1.268     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   2467  1.268     skrll 	usb_device_request_t *req = &xfer->ux_request;
   2468  1.268     skrll 	struct usbd_device *dev = upipe->pipe.up_dev;
   2469  1.268     skrll 	uhci_softc_t *sc = dev->ud_bus->ub_hcpriv;
   2470  1.270     joerg 	uhci_soft_td_t *data = NULL;
   2471  1.268     skrll 	int len;
   2472  1.268     skrll 	usbd_status err;
   2473  1.268     skrll 	int isread;
   2474  1.268     skrll 
   2475  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2476  1.277  pgoyette 	DPRINTFN(3, "xfer=%#jx len=%jd, addr=%jd, endpt=%jd",
   2477  1.277  pgoyette 	    (uintptr_t)xfer, xfer->ux_bufsize, dev->ud_addr,
   2478  1.277  pgoyette 	    upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress);
   2479  1.268     skrll 
   2480  1.268     skrll 	isread = req->bmRequestType & UT_READ;
   2481  1.268     skrll 	len = xfer->ux_bufsize;
   2482  1.268     skrll 
   2483  1.268     skrll 	uxfer->ux_type = UX_CTRL;
   2484  1.268     skrll 	/* Set up data transaction */
   2485  1.268     skrll 	if (len != 0) {
   2486  1.268     skrll 		err = uhci_alloc_std_chain(sc, xfer, len, isread, &data);
   2487  1.268     skrll 		if (err)
   2488  1.268     skrll 			return err;
   2489  1.268     skrll 	}
   2490  1.268     skrll 	/* Set up interrupt info. */
   2491  1.268     skrll 	uxfer->ux_setup = upipe->ctrl.setup;
   2492  1.268     skrll 	uxfer->ux_stat = upipe->ctrl.stat;
   2493  1.268     skrll 	uxfer->ux_data = data;
   2494  1.268     skrll 
   2495  1.268     skrll 	return 0;
   2496  1.268     skrll }
   2497  1.268     skrll 
   2498  1.268     skrll Static void
   2499  1.268     skrll uhci_device_ctrl_fini(struct usbd_xfer *xfer)
   2500  1.268     skrll {
   2501  1.268     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2502  1.268     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   2503  1.268     skrll 
   2504  1.268     skrll 	KASSERT(ux->ux_type == UX_CTRL);
   2505  1.268     skrll 
   2506  1.276     skrll 	if (ux->ux_nstd) {
   2507  1.276     skrll 		uhci_free_stds(sc, ux);
   2508  1.268     skrll 		kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd);
   2509  1.276     skrll 	}
   2510    1.1  augustss }
   2511    1.1  augustss 
   2512    1.1  augustss usbd_status
   2513  1.268     skrll uhci_device_ctrl_transfer(struct usbd_xfer *xfer)
   2514    1.1  augustss {
   2515  1.268     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2516   1.63  augustss 	usbd_status err;
   2517   1.16  augustss 
   2518   1.52  augustss 	/* Insert last in queue. */
   2519  1.248       mrg 	mutex_enter(&sc->sc_lock);
   2520   1.63  augustss 	err = usb_insert_transfer(xfer);
   2521  1.248       mrg 	mutex_exit(&sc->sc_lock);
   2522   1.63  augustss 	if (err)
   2523  1.268     skrll 		return err;
   2524   1.52  augustss 
   2525  1.152  augustss 	/*
   2526   1.92  augustss 	 * Pipe isn't running (otherwise err would be USBD_INPROG),
   2527   1.92  augustss 	 * so start it first.
   2528   1.67  augustss 	 */
   2529  1.268     skrll 	return uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
   2530   1.16  augustss }
   2531   1.16  augustss 
   2532   1.16  augustss usbd_status
   2533  1.268     skrll uhci_device_ctrl_start(struct usbd_xfer *xfer)
   2534   1.16  augustss {
   2535  1.268     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2536  1.268     skrll 	struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer);
   2537  1.268     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   2538  1.268     skrll 	usb_device_request_t *req = &xfer->ux_request;
   2539  1.268     skrll 	struct usbd_device *dev = upipe->pipe.up_dev;
   2540  1.268     skrll 	int addr = dev->ud_addr;
   2541  1.268     skrll 	int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
   2542  1.268     skrll 	uhci_soft_td_t *setup, *stat, *next, *dataend;
   2543  1.268     skrll 	uhci_soft_qh_t *sqh;
   2544  1.268     skrll 	int len;
   2545  1.268     skrll 	int isread;
   2546  1.268     skrll 
   2547  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2548    1.1  augustss 
   2549   1.82  augustss 	if (sc->sc_dying)
   2550  1.268     skrll 		return USBD_IOERROR;
   2551  1.268     skrll 
   2552  1.268     skrll 	KASSERT(xfer->ux_rqflags & URQ_REQUEST);
   2553  1.268     skrll 
   2554  1.277  pgoyette 	DPRINTFN(3, "type=0x%02jx, request=0x%02jx, "
   2555  1.277  pgoyette 	    "wValue=0x%04jx, wIndex=0x%04jx",
   2556  1.268     skrll 	    req->bmRequestType, req->bRequest, UGETW(req->wValue),
   2557  1.268     skrll 	    UGETW(req->wIndex));
   2558  1.277  pgoyette 	DPRINTFN(3, "len=%jd, addr=%jd, endpt=%jd",
   2559  1.268     skrll 	    UGETW(req->wLength), dev->ud_addr, endpt, 0);
   2560  1.268     skrll 
   2561  1.268     skrll 	isread = req->bmRequestType & UT_READ;
   2562  1.268     skrll 	len = UGETW(req->wLength);
   2563  1.268     skrll 
   2564  1.268     skrll 	setup = upipe->ctrl.setup;
   2565  1.268     skrll 	stat = upipe->ctrl.stat;
   2566  1.268     skrll 	sqh = upipe->ctrl.sqh;
   2567  1.268     skrll 
   2568  1.268     skrll 	memcpy(KERNADDR(&upipe->ctrl.reqdma, 0), req, sizeof(*req));
   2569  1.268     skrll 	usb_syncmem(&upipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE);
   2570  1.268     skrll 
   2571  1.268     skrll 	mutex_enter(&sc->sc_lock);
   2572  1.268     skrll 
   2573  1.268     skrll 	/* Set up data transaction */
   2574  1.268     skrll 	if (len != 0) {
   2575  1.268     skrll 		upipe->nexttoggle = 1;
   2576  1.268     skrll 		next = uxfer->ux_data;
   2577  1.268     skrll 		uhci_reset_std_chain(sc, xfer, len, isread,
   2578  1.268     skrll 		    &upipe->nexttoggle, &dataend);
   2579  1.268     skrll 		dataend->link.std = stat;
   2580  1.268     skrll 		dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD);
   2581  1.268     skrll 		usb_syncmem(&dataend->dma,
   2582  1.268     skrll 		    dataend->offs + offsetof(uhci_td_t, td_link),
   2583  1.268     skrll 		    sizeof(dataend->td.td_link),
   2584  1.268     skrll 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2585  1.268     skrll 	} else {
   2586  1.268     skrll 		next = stat;
   2587  1.268     skrll 	}
   2588   1.82  augustss 
   2589  1.268     skrll 	const uint32_t status = UHCI_TD_ZERO_ACTLEN(
   2590  1.268     skrll 	    UHCI_TD_SET_ERRCNT(3) |
   2591  1.268     skrll 	    UHCI_TD_ACTIVE |
   2592  1.268     skrll 	    (dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0)
   2593  1.268     skrll 	    );
   2594  1.268     skrll 	setup->link.std = next;
   2595  1.268     skrll 	setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD);
   2596  1.268     skrll 	setup->td.td_status = htole32(status);
   2597  1.268     skrll 	setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof(*req), endpt, addr));
   2598  1.268     skrll 	setup->td.td_buffer = htole32(DMAADDR(&upipe->ctrl.reqdma, 0));
   2599  1.268     skrll 
   2600  1.268     skrll 	usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td),
   2601  1.268     skrll 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2602  1.268     skrll 
   2603  1.268     skrll 	stat->link.std = NULL;
   2604  1.268     skrll 	stat->td.td_link = htole32(UHCI_PTR_T);
   2605  1.268     skrll 	stat->td.td_status = htole32(status | UHCI_TD_IOC);
   2606  1.268     skrll 	stat->td.td_token =
   2607  1.268     skrll 		htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) :
   2608  1.268     skrll 				 UHCI_TD_IN (0, endpt, addr, 1));
   2609  1.268     skrll 	stat->td.td_buffer = htole32(0);
   2610  1.268     skrll 	usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td),
   2611  1.268     skrll 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2612  1.268     skrll 
   2613  1.268     skrll #ifdef UHCI_DEBUG
   2614  1.268     skrll 	if (uhcidebug >= 10) {
   2615  1.268     skrll 		DPRINTF("--- dump start ---", 0, 0, 0, 0);
   2616  1.268     skrll 		DPRINTF("before transfer", 0, 0, 0, 0);
   2617  1.268     skrll 		uhci_dump_tds(setup);
   2618  1.268     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   2619  1.268     skrll 	}
   2620  1.268     skrll #endif
   2621  1.268     skrll 
   2622  1.268     skrll 	/* Set up interrupt info. */
   2623  1.268     skrll 	uxfer->ux_setup = setup;
   2624  1.268     skrll 	uxfer->ux_stat = stat;
   2625  1.268     skrll 	KASSERT(uxfer->ux_isdone);
   2626   1.48  augustss #ifdef DIAGNOSTIC
   2627  1.268     skrll 	uxfer->ux_isdone = false;
   2628   1.48  augustss #endif
   2629    1.1  augustss 
   2630  1.268     skrll 	sqh->elink = setup;
   2631  1.268     skrll 	sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD);
   2632  1.268     skrll 	/* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */
   2633  1.268     skrll 
   2634  1.268     skrll 	if (dev->ud_speed == USB_SPEED_LOW)
   2635  1.268     skrll 		uhci_add_ls_ctrl(sc, sqh);
   2636  1.268     skrll 	else
   2637  1.268     skrll 		uhci_add_hs_ctrl(sc, sqh);
   2638  1.268     skrll 	uhci_add_intr_list(sc, uxfer);
   2639  1.268     skrll #ifdef UHCI_DEBUG
   2640  1.268     skrll 	if (uhcidebug >= 12) {
   2641  1.268     skrll 		uhci_soft_td_t *std;
   2642  1.268     skrll 		uhci_soft_qh_t *xqh;
   2643  1.268     skrll 		uhci_soft_qh_t *sxqh;
   2644  1.268     skrll 		int maxqh = 0;
   2645  1.268     skrll 		uhci_physaddr_t link;
   2646  1.268     skrll 		DPRINTFN(12, "--- dump start ---", 0, 0, 0, 0);
   2647  1.268     skrll 		DPRINTFN(12, "follow from [0]", 0, 0, 0, 0);
   2648  1.268     skrll 		for (std = sc->sc_vframes[0].htd, link = 0;
   2649  1.268     skrll 		     (link & UHCI_PTR_QH) == 0;
   2650  1.268     skrll 		     std = std->link.std) {
   2651  1.268     skrll 			link = le32toh(std->td.td_link);
   2652  1.268     skrll 			uhci_dump_td(std);
   2653  1.268     skrll 		}
   2654  1.268     skrll 		sxqh = (uhci_soft_qh_t *)std;
   2655  1.268     skrll 		uhci_dump_qh(sxqh);
   2656  1.268     skrll 		for (xqh = sxqh;
   2657  1.268     skrll 		     xqh != NULL;
   2658  1.268     skrll 		     xqh = (maxqh++ == 5 || xqh->hlink == sxqh ||
   2659  1.268     skrll 			xqh->hlink == xqh ? NULL : xqh->hlink)) {
   2660  1.268     skrll 			uhci_dump_qh(xqh);
   2661  1.268     skrll 		}
   2662  1.268     skrll 		DPRINTFN(12, "Enqueued QH:", 0, 0, 0, 0);
   2663  1.268     skrll 		uhci_dump_qh(sqh);
   2664  1.268     skrll 		uhci_dump_tds(sqh->elink);
   2665  1.268     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   2666  1.268     skrll 	}
   2667  1.268     skrll #endif
   2668  1.268     skrll 	if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
   2669  1.268     skrll 		callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
   2670  1.268     skrll 			    uhci_timeout, xfer);
   2671  1.268     skrll 	}
   2672  1.268     skrll 	xfer->ux_status = USBD_IN_PROGRESS;
   2673  1.248       mrg 	mutex_exit(&sc->sc_lock);
   2674    1.1  augustss 
   2675  1.268     skrll 	return USBD_IN_PROGRESS;
   2676  1.268     skrll }
   2677  1.268     skrll 
   2678  1.268     skrll int
   2679  1.268     skrll uhci_device_intr_init(struct usbd_xfer *xfer)
   2680  1.268     skrll {
   2681  1.268     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2682  1.268     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   2683  1.268     skrll 	usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc;
   2684  1.268     skrll 	int endpt = ed->bEndpointAddress;
   2685  1.268     skrll 	int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
   2686  1.268     skrll 	int len = xfer->ux_bufsize;
   2687  1.268     skrll 	int err;
   2688  1.268     skrll 
   2689  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2690  1.268     skrll 
   2691  1.277  pgoyette 	DPRINTFN(3, "xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer,
   2692  1.277  pgoyette 	    xfer->ux_length, xfer->ux_flags, 0);
   2693  1.268     skrll 
   2694  1.268     skrll 	KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
   2695  1.268     skrll 	KASSERT(len != 0);
   2696  1.268     skrll 
   2697  1.268     skrll 	ux->ux_type = UX_INTR;
   2698  1.268     skrll 	ux->ux_nstd = 0;
   2699  1.268     skrll 	err = uhci_alloc_std_chain(sc, xfer, len, isread, &ux->ux_stdstart);
   2700  1.268     skrll 
   2701  1.268     skrll 	return err;
   2702  1.268     skrll }
   2703  1.268     skrll 
   2704  1.268     skrll Static void
   2705  1.268     skrll uhci_device_intr_fini(struct usbd_xfer *xfer)
   2706  1.268     skrll {
   2707  1.268     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2708  1.268     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   2709  1.268     skrll 
   2710  1.268     skrll 	KASSERT(ux->ux_type == UX_INTR);
   2711  1.268     skrll 
   2712  1.276     skrll 	if (ux->ux_nstd) {
   2713  1.276     skrll 		uhci_free_stds(sc, ux);
   2714  1.268     skrll 		kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd);
   2715  1.276     skrll 	}
   2716    1.1  augustss }
   2717    1.1  augustss 
   2718    1.1  augustss usbd_status
   2719  1.268     skrll uhci_device_intr_transfer(struct usbd_xfer *xfer)
   2720    1.1  augustss {
   2721  1.268     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2722   1.63  augustss 	usbd_status err;
   2723   1.16  augustss 
   2724   1.52  augustss 	/* Insert last in queue. */
   2725  1.248       mrg 	mutex_enter(&sc->sc_lock);
   2726   1.63  augustss 	err = usb_insert_transfer(xfer);
   2727  1.248       mrg 	mutex_exit(&sc->sc_lock);
   2728   1.63  augustss 	if (err)
   2729  1.268     skrll 		return err;
   2730   1.52  augustss 
   2731  1.152  augustss 	/*
   2732   1.92  augustss 	 * Pipe isn't running (otherwise err would be USBD_INPROG),
   2733   1.92  augustss 	 * so start it first.
   2734   1.67  augustss 	 */
   2735  1.268     skrll 	return uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
   2736   1.16  augustss }
   2737   1.16  augustss 
   2738   1.16  augustss usbd_status
   2739  1.268     skrll uhci_device_intr_start(struct usbd_xfer *xfer)
   2740   1.16  augustss {
   2741  1.268     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   2742  1.268     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   2743  1.268     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2744   1.55  augustss 	uhci_soft_td_t *data, *dataend;
   2745    1.1  augustss 	uhci_soft_qh_t *sqh;
   2746  1.187     skrll 	int isread, endpt;
   2747  1.248       mrg 	int i;
   2748    1.1  augustss 
   2749   1.82  augustss 	if (sc->sc_dying)
   2750  1.268     skrll 		return USBD_IOERROR;
   2751   1.82  augustss 
   2752  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2753    1.1  augustss 
   2754  1.277  pgoyette 	DPRINTFN(3, "xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer,
   2755  1.277  pgoyette 	    xfer->ux_length, xfer->ux_flags, 0);
   2756    1.1  augustss 
   2757  1.268     skrll 	KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
   2758  1.268     skrll 	KASSERT(xfer->ux_length <= xfer->ux_bufsize);
   2759  1.248       mrg 
   2760  1.268     skrll 	endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
   2761  1.187     skrll 	isread = UE_GET_DIR(endpt) == UE_DIR_IN;
   2762  1.187     skrll 
   2763  1.268     skrll 	data = ux->ux_stdstart;
   2764  1.268     skrll 
   2765  1.268     skrll 	KASSERT(ux->ux_isdone);
   2766  1.268     skrll #ifdef DIAGNOSTIC
   2767  1.268     skrll 	ux->ux_isdone = false;
   2768  1.268     skrll #endif
   2769  1.187     skrll 
   2770  1.268     skrll 	/* Take lock to protect nexttoggle */
   2771  1.278  christos 	if (!sc->sc_bus.ub_usepolling)
   2772  1.278  christos 		mutex_enter(&sc->sc_lock);
   2773  1.268     skrll 	uhci_reset_std_chain(sc, xfer, xfer->ux_length, isread,
   2774  1.268     skrll 	    &upipe->nexttoggle, &dataend);
   2775  1.248       mrg 
   2776   1.88   tsutsui 	dataend->td.td_status |= htole32(UHCI_TD_IOC);
   2777  1.223    bouyer 	usb_syncmem(&dataend->dma,
   2778  1.223    bouyer 	    dataend->offs + offsetof(uhci_td_t, td_status),
   2779  1.223    bouyer 	    sizeof(dataend->td.td_status),
   2780  1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2781  1.268     skrll 	ux->ux_stdend = dataend;
   2782    1.1  augustss 
   2783   1.59  augustss #ifdef UHCI_DEBUG
   2784  1.268     skrll 	if (uhcidebug >= 10) {
   2785  1.268     skrll 		DPRINTF("--- dump start ---", 0, 0, 0, 0);
   2786   1.55  augustss 		uhci_dump_tds(data);
   2787  1.268     skrll 		uhci_dump_qh(upipe->intr.qhs[0]);
   2788  1.268     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   2789    1.1  augustss 	}
   2790    1.1  augustss #endif
   2791    1.1  augustss 
   2792  1.277  pgoyette 	DPRINTFN(10, "qhs[0]=%#jx", (uintptr_t)upipe->intr.qhs[0], 0, 0, 0);
   2793  1.268     skrll 	for (i = 0; i < upipe->intr.npoll; i++) {
   2794  1.268     skrll 		sqh = upipe->intr.qhs[i];
   2795   1.55  augustss 		sqh->elink = data;
   2796  1.121  augustss 		sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD);
   2797  1.223    bouyer 		usb_syncmem(&sqh->dma,
   2798  1.223    bouyer 		    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   2799  1.223    bouyer 		    sizeof(sqh->qh.qh_elink),
   2800  1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2801    1.1  augustss 	}
   2802  1.268     skrll 	uhci_add_intr_list(sc, ux);
   2803  1.268     skrll 	xfer->ux_status = USBD_IN_PROGRESS;
   2804  1.278  christos 	if (!sc->sc_bus.ub_usepolling)
   2805  1.278  christos 		mutex_exit(&sc->sc_lock);
   2806    1.1  augustss 
   2807   1.59  augustss #ifdef UHCI_DEBUG
   2808  1.268     skrll 	if (uhcidebug >= 10) {
   2809  1.268     skrll 		DPRINTF("--- dump start ---", 0, 0, 0, 0);
   2810   1.55  augustss 		uhci_dump_tds(data);
   2811  1.268     skrll 		uhci_dump_qh(upipe->intr.qhs[0]);
   2812  1.268     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   2813    1.1  augustss 	}
   2814    1.1  augustss #endif
   2815    1.1  augustss 
   2816  1.268     skrll 	return USBD_IN_PROGRESS;
   2817    1.1  augustss }
   2818    1.1  augustss 
   2819    1.1  augustss /* Abort a device control request. */
   2820    1.1  augustss void
   2821  1.268     skrll uhci_device_ctrl_abort(struct usbd_xfer *xfer)
   2822    1.1  augustss {
   2823  1.268     skrll 	uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer);
   2824  1.248       mrg 
   2825  1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2826  1.248       mrg 
   2827  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2828   1.66  augustss 	uhci_abort_xfer(xfer, USBD_CANCELLED);
   2829    1.1  augustss }
   2830    1.1  augustss 
   2831    1.1  augustss /* Close a device control pipe. */
   2832    1.1  augustss void
   2833  1.268     skrll uhci_device_ctrl_close(struct usbd_pipe *pipe)
   2834    1.1  augustss {
   2835  1.268     skrll 	uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
   2836  1.268     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
   2837  1.268     skrll 
   2838  1.268     skrll 	uhci_free_sqh(sc, upipe->ctrl.sqh);
   2839  1.268     skrll 	uhci_free_std_locked(sc, upipe->ctrl.setup);
   2840  1.268     skrll 	uhci_free_std_locked(sc, upipe->ctrl.stat);
   2841  1.268     skrll 
   2842    1.1  augustss }
   2843    1.1  augustss 
   2844    1.1  augustss /* Abort a device interrupt request. */
   2845    1.1  augustss void
   2846  1.268     skrll uhci_device_intr_abort(struct usbd_xfer *xfer)
   2847    1.1  augustss {
   2848  1.268     skrll 	uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer);
   2849  1.248       mrg 
   2850  1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2851  1.268     skrll 	KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
   2852  1.248       mrg 
   2853  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2854  1.277  pgoyette 	DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0);
   2855  1.264     skrll 
   2856   1.66  augustss 	uhci_abort_xfer(xfer, USBD_CANCELLED);
   2857    1.1  augustss }
   2858    1.1  augustss 
   2859    1.1  augustss /* Close a device interrupt pipe. */
   2860    1.1  augustss void
   2861  1.268     skrll uhci_device_intr_close(struct usbd_pipe *pipe)
   2862    1.1  augustss {
   2863  1.268     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
   2864  1.268     skrll 	uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
   2865   1.92  augustss 	int i, npoll;
   2866  1.248       mrg 
   2867  1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   2868    1.1  augustss 
   2869    1.1  augustss 	/* Unlink descriptors from controller data structures. */
   2870  1.268     skrll 	npoll = upipe->intr.npoll;
   2871    1.1  augustss 	for (i = 0; i < npoll; i++)
   2872  1.268     skrll 		uhci_remove_intr(sc, upipe->intr.qhs[i]);
   2873    1.1  augustss 
   2874  1.152  augustss 	/*
   2875    1.1  augustss 	 * We now have to wait for any activity on the physical
   2876    1.1  augustss 	 * descriptors to stop.
   2877    1.1  augustss 	 */
   2878  1.248       mrg 	usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock);
   2879    1.1  augustss 
   2880  1.267     skrll 	for (i = 0; i < npoll; i++)
   2881  1.268     skrll 		uhci_free_sqh(sc, upipe->intr.qhs[i]);
   2882  1.268     skrll 	kmem_free(upipe->intr.qhs, npoll * sizeof(uhci_soft_qh_t *));
   2883    1.1  augustss }
   2884    1.1  augustss 
   2885  1.268     skrll int
   2886  1.268     skrll uhci_device_isoc_init(struct usbd_xfer *xfer)
   2887    1.1  augustss {
   2888  1.268     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   2889  1.248       mrg 
   2890  1.268     skrll 	KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
   2891  1.268     skrll 	KASSERT(xfer->ux_nframes != 0);
   2892  1.268     skrll 	KASSERT(ux->ux_isdone);
   2893    1.1  augustss 
   2894  1.268     skrll 	ux->ux_type = UX_ISOC;
   2895  1.268     skrll 	return 0;
   2896  1.268     skrll }
   2897    1.1  augustss 
   2898  1.268     skrll Static void
   2899  1.268     skrll uhci_device_isoc_fini(struct usbd_xfer *xfer)
   2900  1.268     skrll {
   2901  1.269     skrll 	struct uhci_xfer *ux __diagused = UHCI_XFER2UXFER(xfer);
   2902    1.1  augustss 
   2903  1.268     skrll 	KASSERT(ux->ux_type == UX_ISOC);
   2904    1.1  augustss }
   2905    1.1  augustss 
   2906   1.16  augustss usbd_status
   2907  1.268     skrll uhci_device_isoc_transfer(struct usbd_xfer *xfer)
   2908   1.16  augustss {
   2909  1.268     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   2910  1.268     skrll 	usbd_status err __diagused;
   2911   1.48  augustss 
   2912  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   2913  1.277  pgoyette 	DPRINTFN(5, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0);
   2914   1.48  augustss 
   2915   1.48  augustss 	/* Put it on our queue, */
   2916  1.248       mrg 	mutex_enter(&sc->sc_lock);
   2917   1.63  augustss 	err = usb_insert_transfer(xfer);
   2918  1.248       mrg 	mutex_exit(&sc->sc_lock);
   2919   1.48  augustss 
   2920  1.268     skrll 	KASSERT(err == USBD_NORMAL_COMPLETION);
   2921   1.48  augustss 
   2922   1.48  augustss 	/* insert into schedule, */
   2923   1.48  augustss 
   2924  1.268     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   2925  1.268     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   2926  1.268     skrll 	struct isoc *isoc = &upipe->isoc;
   2927  1.268     skrll 	uhci_soft_td_t *std = NULL;
   2928  1.268     skrll 	uint32_t buf, len, status, offs;
   2929  1.248       mrg 	int i, next, nframes;
   2930  1.268     skrll 	int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN;
   2931   1.48  augustss 
   2932  1.277  pgoyette 	DPRINTFN(5, "used=%jd next=%jd xfer=%#jx nframes=%jd",
   2933  1.277  pgoyette 	    isoc->inuse, isoc->next, (uintptr_t)xfer, xfer->ux_nframes);
   2934   1.48  augustss 
   2935   1.82  augustss 	if (sc->sc_dying)
   2936  1.268     skrll 		return USBD_IOERROR;
   2937   1.82  augustss 
   2938  1.268     skrll 	if (xfer->ux_status == USBD_IN_PROGRESS) {
   2939   1.48  augustss 		/* This request has already been entered into the frame list */
   2940  1.268     skrll 		printf("%s: xfer=%p in frame list\n", __func__, xfer);
   2941   1.68  augustss 		/* XXX */
   2942   1.48  augustss 	}
   2943   1.48  augustss 
   2944   1.48  augustss #ifdef DIAGNOSTIC
   2945  1.268     skrll 	if (isoc->inuse >= UHCI_VFRAMELIST_COUNT)
   2946  1.268     skrll 		printf("%s: overflow!\n", __func__);
   2947   1.19  augustss #endif
   2948   1.16  augustss 
   2949  1.268     skrll 	KASSERT(xfer->ux_nframes != 0);
   2950  1.268     skrll 
   2951  1.268     skrll 	mutex_enter(&sc->sc_lock);
   2952  1.268     skrll 	next = isoc->next;
   2953   1.48  augustss 	if (next == -1) {
   2954   1.48  augustss 		/* Not in use yet, schedule it a few frames ahead. */
   2955   1.48  augustss 		next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT;
   2956  1.277  pgoyette 		DPRINTFN(2, "start next=%jd", next, 0, 0, 0);
   2957   1.48  augustss 	}
   2958   1.48  augustss 
   2959  1.268     skrll 	xfer->ux_status = USBD_IN_PROGRESS;
   2960  1.268     skrll 	ux->ux_curframe = next;
   2961   1.48  augustss 
   2962  1.268     skrll 	buf = DMAADDR(&xfer->ux_dmabuf, 0);
   2963  1.223    bouyer 	offs = 0;
   2964   1.88   tsutsui 	status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) |
   2965   1.88   tsutsui 				     UHCI_TD_ACTIVE |
   2966   1.88   tsutsui 				     UHCI_TD_IOS);
   2967  1.268     skrll 	nframes = xfer->ux_nframes;
   2968   1.48  augustss 	for (i = 0; i < nframes; i++) {
   2969  1.268     skrll 		std = isoc->stds[next];
   2970   1.48  augustss 		if (++next >= UHCI_VFRAMELIST_COUNT)
   2971   1.48  augustss 			next = 0;
   2972  1.268     skrll 		len = xfer->ux_frlengths[i];
   2973   1.88   tsutsui 		std->td.td_buffer = htole32(buf);
   2974  1.268     skrll 		usb_syncmem(&xfer->ux_dmabuf, offs, len,
   2975  1.223    bouyer 		    rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
   2976   1.48  augustss 		if (i == nframes - 1)
   2977   1.88   tsutsui 			status |= UHCI_TD_IOC;
   2978   1.88   tsutsui 		std->td.td_status = htole32(status);
   2979   1.88   tsutsui 		std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK);
   2980   1.88   tsutsui 		std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len));
   2981  1.223    bouyer 		usb_syncmem(&std->dma, std->offs, sizeof(std->td),
   2982  1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   2983   1.59  augustss #ifdef UHCI_DEBUG
   2984  1.268     skrll 		if (uhcidebug >= 5) {
   2985  1.268     skrll 			DPRINTF("--- dump start ---", 0, 0, 0, 0);
   2986  1.277  pgoyette 			DPRINTF("TD %jd", i, 0, 0, 0);
   2987   1.48  augustss 			uhci_dump_td(std);
   2988  1.268     skrll 			DPRINTF("--- dump end ---", 0, 0, 0, 0);
   2989   1.48  augustss 		}
   2990   1.48  augustss #endif
   2991   1.48  augustss 		buf += len;
   2992  1.223    bouyer 		offs += len;
   2993   1.48  augustss 	}
   2994  1.268     skrll 	isoc->next = next;
   2995  1.268     skrll 	isoc->inuse += xfer->ux_nframes;
   2996   1.16  augustss 
   2997  1.268     skrll 	/* Set up interrupt info. */
   2998  1.268     skrll 	ux->ux_stdstart = std;
   2999  1.268     skrll 	ux->ux_stdend = std;
   3000   1.96  augustss 
   3001  1.268     skrll 	KASSERT(ux->ux_isdone);
   3002   1.48  augustss #ifdef DIAGNOSTIC
   3003  1.268     skrll 	ux->ux_isdone = false;
   3004   1.48  augustss #endif
   3005  1.268     skrll 	uhci_add_intr_list(sc, ux);
   3006  1.152  augustss 
   3007  1.248       mrg 	mutex_exit(&sc->sc_lock);
   3008   1.48  augustss 
   3009  1.268     skrll 	return USBD_IN_PROGRESS;
   3010   1.16  augustss }
   3011   1.16  augustss 
   3012   1.16  augustss void
   3013  1.268     skrll uhci_device_isoc_abort(struct usbd_xfer *xfer)
   3014   1.16  augustss {
   3015  1.268     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   3016  1.268     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   3017  1.268     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   3018  1.268     skrll 	uhci_soft_td_t **stds = upipe->isoc.stds;
   3019   1.48  augustss 	uhci_soft_td_t *std;
   3020  1.248       mrg 	int i, n, nframes, maxlen, len;
   3021   1.92  augustss 
   3022  1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   3023   1.92  augustss 
   3024   1.92  augustss 	/* Transfer is already done. */
   3025  1.268     skrll 	if (xfer->ux_status != USBD_NOT_STARTED &&
   3026  1.268     skrll 	    xfer->ux_status != USBD_IN_PROGRESS) {
   3027   1.92  augustss 		return;
   3028   1.92  augustss 	}
   3029   1.48  augustss 
   3030   1.92  augustss 	/* Give xfer the requested abort code. */
   3031  1.268     skrll 	xfer->ux_status = USBD_CANCELLED;
   3032   1.48  augustss 
   3033   1.48  augustss 	/* make hardware ignore it, */
   3034  1.268     skrll 	nframes = xfer->ux_nframes;
   3035  1.268     skrll 	n = ux->ux_curframe;
   3036   1.92  augustss 	maxlen = 0;
   3037   1.48  augustss 	for (i = 0; i < nframes; i++) {
   3038   1.48  augustss 		std = stds[n];
   3039  1.223    bouyer 		usb_syncmem(&std->dma,
   3040  1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_status),
   3041  1.223    bouyer 		    sizeof(std->td.td_status),
   3042  1.223    bouyer 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   3043   1.88   tsutsui 		std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC));
   3044  1.223    bouyer 		usb_syncmem(&std->dma,
   3045  1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_status),
   3046  1.223    bouyer 		    sizeof(std->td.td_status),
   3047  1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   3048  1.223    bouyer 		usb_syncmem(&std->dma,
   3049  1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_token),
   3050  1.223    bouyer 		    sizeof(std->td.td_token),
   3051  1.223    bouyer 		    BUS_DMASYNC_POSTWRITE);
   3052  1.130   tsutsui 		len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token));
   3053   1.92  augustss 		if (len > maxlen)
   3054   1.92  augustss 			maxlen = len;
   3055   1.48  augustss 		if (++n >= UHCI_VFRAMELIST_COUNT)
   3056   1.48  augustss 			n = 0;
   3057   1.48  augustss 	}
   3058   1.48  augustss 
   3059   1.92  augustss 	/* and wait until we are sure the hardware has finished. */
   3060   1.92  augustss 	delay(maxlen);
   3061   1.92  augustss 
   3062   1.96  augustss #ifdef DIAGNOSTIC
   3063  1.268     skrll 	ux->ux_isdone = true;
   3064   1.96  augustss #endif
   3065  1.268     skrll 	/* Remove from interrupt list. */
   3066  1.268     skrll 	uhci_del_intr_list(sc, ux);
   3067  1.268     skrll 
   3068  1.268     skrll 	/* Run callback. */
   3069   1.92  augustss 	usb_transfer_complete(xfer);
   3070   1.48  augustss 
   3071  1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   3072   1.16  augustss }
   3073   1.16  augustss 
   3074   1.16  augustss void
   3075  1.268     skrll uhci_device_isoc_close(struct usbd_pipe *pipe)
   3076   1.16  augustss {
   3077  1.268     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
   3078  1.268     skrll 	uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
   3079   1.48  augustss 	uhci_soft_td_t *std, *vstd;
   3080  1.268     skrll 	struct isoc *isoc;
   3081  1.248       mrg 	int i;
   3082  1.248       mrg 
   3083  1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   3084   1.16  augustss 
   3085   1.16  augustss 	/*
   3086   1.16  augustss 	 * Make sure all TDs are marked as inactive.
   3087   1.16  augustss 	 * Wait for completion.
   3088   1.16  augustss 	 * Unschedule.
   3089   1.16  augustss 	 * Deallocate.
   3090   1.16  augustss 	 */
   3091  1.268     skrll 	isoc = &upipe->isoc;
   3092   1.16  augustss 
   3093  1.223    bouyer 	for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
   3094  1.268     skrll 		std = isoc->stds[i];
   3095  1.223    bouyer 		usb_syncmem(&std->dma,
   3096  1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_status),
   3097  1.223    bouyer 		    sizeof(std->td.td_status),
   3098  1.223    bouyer 		    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   3099  1.223    bouyer 		std->td.td_status &= htole32(~UHCI_TD_ACTIVE);
   3100  1.223    bouyer 		usb_syncmem(&std->dma,
   3101  1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_status),
   3102  1.223    bouyer 		    sizeof(std->td.td_status),
   3103  1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   3104  1.223    bouyer 	}
   3105  1.248       mrg 	/* wait for completion */
   3106  1.248       mrg 	usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock);
   3107   1.16  augustss 
   3108   1.16  augustss 	for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
   3109  1.268     skrll 		std = isoc->stds[i];
   3110   1.48  augustss 		for (vstd = sc->sc_vframes[i].htd;
   3111   1.67  augustss 		     vstd != NULL && vstd->link.std != std;
   3112   1.42  augustss 		     vstd = vstd->link.std)
   3113   1.16  augustss 			;
   3114   1.67  augustss 		if (vstd == NULL) {
   3115   1.16  augustss 			/*panic*/
   3116  1.268     skrll 			printf("%s: %p not found\n", __func__, std);
   3117  1.248       mrg 			mutex_exit(&sc->sc_lock);
   3118   1.16  augustss 			return;
   3119   1.16  augustss 		}
   3120   1.42  augustss 		vstd->link = std->link;
   3121  1.223    bouyer 		usb_syncmem(&std->dma,
   3122  1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_link),
   3123  1.223    bouyer 		    sizeof(std->td.td_link),
   3124  1.223    bouyer 		    BUS_DMASYNC_POSTWRITE);
   3125   1.42  augustss 		vstd->td.td_link = std->td.td_link;
   3126  1.223    bouyer 		usb_syncmem(&vstd->dma,
   3127  1.223    bouyer 		    vstd->offs + offsetof(uhci_td_t, td_link),
   3128  1.223    bouyer 		    sizeof(vstd->td.td_link),
   3129  1.223    bouyer 		    BUS_DMASYNC_PREWRITE);
   3130  1.268     skrll 		uhci_free_std_locked(sc, std);
   3131   1.16  augustss 	}
   3132   1.16  augustss 
   3133  1.268     skrll 	kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *));
   3134   1.16  augustss }
   3135   1.16  augustss 
   3136   1.16  augustss usbd_status
   3137  1.268     skrll uhci_setup_isoc(struct usbd_pipe *pipe)
   3138   1.16  augustss {
   3139  1.268     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
   3140  1.268     skrll 	uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
   3141  1.268     skrll 	int addr = upipe->pipe.up_dev->ud_addr;
   3142  1.268     skrll 	int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
   3143   1.45  augustss 	int rd = UE_GET_DIR(endpt) == UE_DIR_IN;
   3144   1.48  augustss 	uhci_soft_td_t *std, *vstd;
   3145  1.268     skrll 	uint32_t token;
   3146  1.268     skrll 	struct isoc *isoc;
   3147  1.248       mrg 	int i;
   3148   1.16  augustss 
   3149  1.268     skrll 	isoc = &upipe->isoc;
   3150  1.268     skrll 
   3151  1.268     skrll 	isoc->stds = kmem_alloc(
   3152  1.268     skrll 	    UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *), KM_SLEEP);
   3153  1.268     skrll 	if (isoc->stds == NULL)
   3154  1.248       mrg 		return USBD_NOMEM;
   3155   1.16  augustss 
   3156   1.88   tsutsui 	token = rd ? UHCI_TD_IN (0, endpt, addr, 0) :
   3157   1.88   tsutsui 		     UHCI_TD_OUT(0, endpt, addr, 0);
   3158   1.16  augustss 
   3159   1.48  augustss 	/* Allocate the TDs and mark as inactive; */
   3160   1.16  augustss 	for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
   3161   1.48  augustss 		std = uhci_alloc_std(sc);
   3162   1.48  augustss 		if (std == 0)
   3163   1.48  augustss 			goto bad;
   3164   1.88   tsutsui 		std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */
   3165   1.88   tsutsui 		std->td.td_token = htole32(token);
   3166  1.223    bouyer 		usb_syncmem(&std->dma, std->offs, sizeof(std->td),
   3167  1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   3168  1.268     skrll 		isoc->stds[i] = std;
   3169   1.16  augustss 	}
   3170   1.16  augustss 
   3171  1.268     skrll 	mutex_enter(&sc->sc_lock);
   3172  1.268     skrll 
   3173   1.48  augustss 	/* Insert TDs into schedule. */
   3174   1.16  augustss 	for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
   3175  1.268     skrll 		std = isoc->stds[i];
   3176   1.48  augustss 		vstd = sc->sc_vframes[i].htd;
   3177  1.223    bouyer 		usb_syncmem(&vstd->dma,
   3178  1.223    bouyer 		    vstd->offs + offsetof(uhci_td_t, td_link),
   3179  1.223    bouyer 		    sizeof(vstd->td.td_link),
   3180  1.223    bouyer 		    BUS_DMASYNC_POSTWRITE);
   3181   1.42  augustss 		std->link = vstd->link;
   3182   1.42  augustss 		std->td.td_link = vstd->td.td_link;
   3183  1.223    bouyer 		usb_syncmem(&std->dma,
   3184  1.223    bouyer 		    std->offs + offsetof(uhci_td_t, td_link),
   3185  1.223    bouyer 		    sizeof(std->td.td_link),
   3186  1.223    bouyer 		    BUS_DMASYNC_PREWRITE);
   3187   1.42  augustss 		vstd->link.std = std;
   3188  1.121  augustss 		vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD);
   3189  1.223    bouyer 		usb_syncmem(&vstd->dma,
   3190  1.223    bouyer 		    vstd->offs + offsetof(uhci_td_t, td_link),
   3191  1.223    bouyer 		    sizeof(vstd->td.td_link),
   3192  1.223    bouyer 		    BUS_DMASYNC_PREWRITE);
   3193   1.16  augustss 	}
   3194  1.248       mrg 	mutex_exit(&sc->sc_lock);
   3195   1.16  augustss 
   3196  1.268     skrll 	isoc->next = -1;
   3197  1.268     skrll 	isoc->inuse = 0;
   3198   1.48  augustss 
   3199  1.268     skrll 	return USBD_NORMAL_COMPLETION;
   3200   1.16  augustss 
   3201   1.48  augustss  bad:
   3202   1.16  augustss 	while (--i >= 0)
   3203  1.268     skrll 		uhci_free_std(sc, isoc->stds[i]);
   3204  1.268     skrll 	kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *));
   3205  1.268     skrll 	return USBD_NOMEM;
   3206   1.16  augustss }
   3207   1.16  augustss 
   3208   1.16  augustss void
   3209  1.268     skrll uhci_device_isoc_done(struct usbd_xfer *xfer)
   3210   1.16  augustss {
   3211  1.268     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   3212  1.268     skrll 	struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer);
   3213  1.223    bouyer 	int i, offs;
   3214  1.268     skrll 	int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN;
   3215  1.170  augustss 
   3216  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3217  1.277  pgoyette 	DPRINTFN(4, "length=%jd, ux_state=0x%08jx",
   3218  1.268     skrll 	    xfer->ux_actlen, xfer->ux_state, 0, 0);
   3219   1.96  augustss 
   3220   1.93  augustss #ifdef DIAGNOSTIC
   3221  1.268     skrll 	if (ux->ux_stdend == NULL) {
   3222  1.268     skrll 		printf("%s: xfer=%p stdend==NULL\n", __func__, xfer);
   3223   1.93  augustss #ifdef UHCI_DEBUG
   3224  1.268     skrll 		DPRINTF("--- dump start ---", 0, 0, 0, 0);
   3225  1.268     skrll 		uhci_dump_ii(ux);
   3226  1.268     skrll 		DPRINTF("--- dump end ---", 0, 0, 0, 0);
   3227   1.93  augustss #endif
   3228   1.93  augustss 		return;
   3229   1.93  augustss 	}
   3230   1.93  augustss #endif
   3231   1.48  augustss 
   3232   1.48  augustss 	/* Turn off the interrupt since it is active even if the TD is not. */
   3233  1.268     skrll 	usb_syncmem(&ux->ux_stdend->dma,
   3234  1.268     skrll 	    ux->ux_stdend->offs + offsetof(uhci_td_t, td_status),
   3235  1.268     skrll 	    sizeof(ux->ux_stdend->td.td_status),
   3236  1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   3237  1.268     skrll 	ux->ux_stdend->td.td_status &= htole32(~UHCI_TD_IOC);
   3238  1.268     skrll 	usb_syncmem(&ux->ux_stdend->dma,
   3239  1.268     skrll 	    ux->ux_stdend->offs + offsetof(uhci_td_t, td_status),
   3240  1.268     skrll 	    sizeof(ux->ux_stdend->td.td_status),
   3241  1.223    bouyer 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   3242   1.48  augustss 
   3243  1.223    bouyer 	offs = 0;
   3244  1.268     skrll 	for (i = 0; i < xfer->ux_nframes; i++) {
   3245  1.268     skrll 		usb_syncmem(&xfer->ux_dmabuf, offs, xfer->ux_frlengths[i],
   3246  1.223    bouyer 		    rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
   3247  1.268     skrll 		offs += xfer->ux_frlengths[i];
   3248  1.223    bouyer 	}
   3249   1.16  augustss }
   3250   1.16  augustss 
   3251    1.1  augustss void
   3252  1.268     skrll uhci_device_intr_done(struct usbd_xfer *xfer)
   3253    1.1  augustss {
   3254  1.269     skrll 	uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer);
   3255  1.268     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   3256    1.1  augustss 	uhci_soft_qh_t *sqh;
   3257  1.268     skrll 	int i, npoll;
   3258    1.1  augustss 
   3259  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3260  1.277  pgoyette 	DPRINTFN(5, "length=%jd", xfer->ux_actlen, 0, 0, 0);
   3261    1.1  augustss 
   3262  1.268     skrll 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
   3263  1.248       mrg 
   3264  1.268     skrll 	npoll = upipe->intr.npoll;
   3265  1.267     skrll 	for (i = 0; i < npoll; i++) {
   3266  1.268     skrll 		sqh = upipe->intr.qhs[i];
   3267  1.121  augustss 		sqh->elink = NULL;
   3268   1.88   tsutsui 		sqh->qh.qh_elink = htole32(UHCI_PTR_T);
   3269  1.223    bouyer 		usb_syncmem(&sqh->dma,
   3270  1.223    bouyer 		    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   3271  1.223    bouyer 		    sizeof(sqh->qh.qh_elink),
   3272  1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   3273    1.1  augustss 	}
   3274  1.268     skrll 	const int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress;
   3275  1.268     skrll 	const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN;
   3276  1.268     skrll 	usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
   3277  1.223    bouyer 	    isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
   3278    1.1  augustss }
   3279    1.1  augustss 
   3280    1.1  augustss /* Deallocate request data structures */
   3281    1.1  augustss void
   3282  1.268     skrll uhci_device_ctrl_done(struct usbd_xfer *xfer)
   3283    1.1  augustss {
   3284  1.268     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   3285  1.268     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   3286  1.268     skrll 	int len = UGETW(xfer->ux_request.wLength);
   3287  1.268     skrll 	int isread = (xfer->ux_request.bmRequestType & UT_READ);
   3288    1.1  augustss 
   3289  1.268     skrll 	KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
   3290  1.248       mrg 
   3291  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3292  1.169  augustss 
   3293  1.268     skrll 	KASSERT(xfer->ux_rqflags & URQ_REQUEST);
   3294    1.1  augustss 
   3295  1.268     skrll 	/* XXXNH move to uhci_idone??? */
   3296  1.268     skrll 	if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW)
   3297  1.268     skrll 		uhci_remove_ls_ctrl(sc, upipe->ctrl.sqh);
   3298  1.123  augustss 	else
   3299  1.268     skrll 		uhci_remove_hs_ctrl(sc, upipe->ctrl.sqh);
   3300   1.49  augustss 
   3301  1.223    bouyer 	if (len) {
   3302  1.268     skrll 		usb_syncmem(&xfer->ux_dmabuf, 0, len,
   3303  1.223    bouyer 		    isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
   3304  1.223    bouyer 	}
   3305  1.268     skrll 	usb_syncmem(&upipe->ctrl.reqdma, 0,
   3306  1.223    bouyer 	    sizeof(usb_device_request_t),  BUS_DMASYNC_POSTWRITE);
   3307  1.223    bouyer 
   3308  1.277  pgoyette 	DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0);
   3309    1.1  augustss }
   3310    1.1  augustss 
   3311    1.1  augustss /* Deallocate request data structures */
   3312    1.1  augustss void
   3313  1.268     skrll uhci_device_bulk_done(struct usbd_xfer *xfer)
   3314    1.1  augustss {
   3315  1.268     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   3316  1.268     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe);
   3317  1.268     skrll 	usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc;
   3318  1.268     skrll 	int endpt = ed->bEndpointAddress;
   3319  1.268     skrll 	int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
   3320  1.169  augustss 
   3321  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3322  1.277  pgoyette 	DPRINTFN(5, "xfer=%#jx sc=%#jx upipe=%#jx", (uintptr_t)xfer,
   3323  1.277  pgoyette 	    (uintptr_t)sc, (uintptr_t)upipe, 0);
   3324  1.169  augustss 
   3325  1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   3326  1.248       mrg 
   3327  1.268     skrll 	uhci_remove_bulk(sc, upipe->bulk.sqh);
   3328    1.1  augustss 
   3329  1.268     skrll 	if (xfer->ux_length) {
   3330  1.268     skrll 		usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
   3331  1.268     skrll 		    isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
   3332  1.268     skrll 	}
   3333    1.1  augustss 
   3334  1.277  pgoyette 	DPRINTFN(5, "length=%jd", xfer->ux_actlen, 0, 0, 0);
   3335    1.1  augustss }
   3336    1.1  augustss 
   3337    1.1  augustss /* Add interrupt QH, called with vflock. */
   3338    1.1  augustss void
   3339  1.119  augustss uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   3340    1.1  augustss {
   3341   1.92  augustss 	struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos];
   3342   1.42  augustss 	uhci_soft_qh_t *eqh;
   3343    1.1  augustss 
   3344  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3345  1.277  pgoyette 	DPRINTFN(4, "n=%jd sqh=%#jx", sqh->pos, (uintptr_t)sqh, 0, 0);
   3346   1.92  augustss 
   3347   1.42  augustss 	eqh = vf->eqh;
   3348  1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   3349  1.223    bouyer 	    sizeof(eqh->qh.qh_hlink),
   3350  1.223    bouyer 	    BUS_DMASYNC_POSTWRITE);
   3351   1.42  augustss 	sqh->hlink       = eqh->hlink;
   3352   1.42  augustss 	sqh->qh.qh_hlink = eqh->qh.qh_hlink;
   3353  1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
   3354  1.223    bouyer 	    sizeof(sqh->qh.qh_hlink),
   3355  1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   3356   1.42  augustss 	eqh->hlink       = sqh;
   3357  1.121  augustss 	eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
   3358  1.223    bouyer 	usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
   3359  1.223    bouyer 	    sizeof(eqh->qh.qh_hlink),
   3360  1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   3361    1.1  augustss 	vf->eqh = sqh;
   3362    1.1  augustss 	vf->bandwidth++;
   3363    1.1  augustss }
   3364    1.1  augustss 
   3365  1.119  augustss /* Remove interrupt QH. */
   3366    1.1  augustss void
   3367  1.119  augustss uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
   3368    1.1  augustss {
   3369   1.92  augustss 	struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos];
   3370    1.1  augustss 	uhci_soft_qh_t *pqh;
   3371    1.1  augustss 
   3372  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3373  1.277  pgoyette 	DPRINTFN(4, "n=%jd sqh=%#jx", sqh->pos, (uintptr_t)sqh, 0, 0);
   3374    1.1  augustss 
   3375  1.124  augustss 	/* See comment in uhci_remove_ctrl() */
   3376  1.223    bouyer 
   3377  1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
   3378  1.223    bouyer 	    sizeof(sqh->qh.qh_elink),
   3379  1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   3380  1.124  augustss 	if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) {
   3381  1.124  augustss 		sqh->qh.qh_elink = htole32(UHCI_PTR_T);
   3382  1.223    bouyer 		usb_syncmem(&sqh->dma,
   3383  1.223    bouyer 		    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   3384  1.223    bouyer 		    sizeof(sqh->qh.qh_elink),
   3385  1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   3386  1.124  augustss 		delay(UHCI_QH_REMOVE_DELAY);
   3387  1.124  augustss 	}
   3388  1.124  augustss 
   3389   1.92  augustss 	pqh = uhci_find_prev_qh(vf->hqh, sqh);
   3390  1.223    bouyer 	usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
   3391  1.223    bouyer 	    sizeof(sqh->qh.qh_hlink),
   3392  1.223    bouyer 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
   3393   1.42  augustss 	pqh->hlink       = sqh->hlink;
   3394   1.42  augustss 	pqh->qh.qh_hlink = sqh->qh.qh_hlink;
   3395  1.223    bouyer 	usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
   3396  1.223    bouyer 	    sizeof(pqh->qh.qh_hlink),
   3397  1.223    bouyer 	    BUS_DMASYNC_PREWRITE);
   3398  1.124  augustss 	delay(UHCI_QH_REMOVE_DELAY);
   3399    1.1  augustss 	if (vf->eqh == sqh)
   3400    1.1  augustss 		vf->eqh = pqh;
   3401    1.1  augustss 	vf->bandwidth--;
   3402    1.1  augustss }
   3403    1.1  augustss 
   3404    1.1  augustss usbd_status
   3405  1.119  augustss uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival)
   3406    1.1  augustss {
   3407    1.1  augustss 	uhci_soft_qh_t *sqh;
   3408  1.248       mrg 	int i, npoll;
   3409    1.1  augustss 	u_int bestbw, bw, bestoffs, offs;
   3410    1.1  augustss 
   3411  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3412  1.277  pgoyette 	DPRINTFN(2, "pipe=%#jx", (uintptr_t)upipe, 0, 0, 0);
   3413    1.1  augustss 	if (ival == 0) {
   3414  1.268     skrll 		printf("%s: 0 interval\n", __func__);
   3415  1.268     skrll 		return USBD_INVAL;
   3416    1.1  augustss 	}
   3417    1.1  augustss 
   3418    1.1  augustss 	if (ival > UHCI_VFRAMELIST_COUNT)
   3419    1.1  augustss 		ival = UHCI_VFRAMELIST_COUNT;
   3420    1.1  augustss 	npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival;
   3421  1.277  pgoyette 	DPRINTF("ival=%jd npoll=%jd", ival, npoll, 0, 0);
   3422    1.1  augustss 
   3423  1.268     skrll 	upipe->intr.npoll = npoll;
   3424  1.268     skrll 	upipe->intr.qhs =
   3425  1.248       mrg 		kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP);
   3426    1.1  augustss 
   3427  1.152  augustss 	/*
   3428    1.1  augustss 	 * Figure out which offset in the schedule that has most
   3429    1.1  augustss 	 * bandwidth left over.
   3430    1.1  augustss 	 */
   3431    1.1  augustss #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1))
   3432    1.1  augustss 	for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) {
   3433    1.1  augustss 		for (bw = i = 0; i < npoll; i++)
   3434    1.1  augustss 			bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth;
   3435    1.1  augustss 		if (bw < bestbw) {
   3436    1.1  augustss 			bestbw = bw;
   3437    1.1  augustss 			bestoffs = offs;
   3438    1.1  augustss 		}
   3439    1.1  augustss 	}
   3440  1.277  pgoyette 	DPRINTF("bw=%jd offs=%jd", bestbw, bestoffs, 0, 0);
   3441  1.267     skrll 	for (i = 0; i < npoll; i++) {
   3442  1.268     skrll 		upipe->intr.qhs[i] = sqh = uhci_alloc_sqh(sc);
   3443  1.121  augustss 		sqh->elink = NULL;
   3444   1.88   tsutsui 		sqh->qh.qh_elink = htole32(UHCI_PTR_T);
   3445  1.223    bouyer 		usb_syncmem(&sqh->dma,
   3446  1.223    bouyer 		    sqh->offs + offsetof(uhci_qh_t, qh_elink),
   3447  1.223    bouyer 		    sizeof(sqh->qh.qh_elink),
   3448  1.223    bouyer 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
   3449    1.1  augustss 		sqh->pos = MOD(i * ival + bestoffs);
   3450    1.1  augustss 	}
   3451    1.1  augustss #undef MOD
   3452    1.1  augustss 
   3453  1.268     skrll 	mutex_enter(&sc->sc_lock);
   3454    1.1  augustss 	/* Enter QHs into the controller data structures. */
   3455  1.267     skrll 	for (i = 0; i < npoll; i++)
   3456  1.268     skrll 		uhci_add_intr(sc, upipe->intr.qhs[i]);
   3457  1.248       mrg 	mutex_exit(&sc->sc_lock);
   3458    1.1  augustss 
   3459  1.277  pgoyette 	DPRINTFN(5, "returns %#jx", (uintptr_t)upipe, 0, 0, 0);
   3460  1.268     skrll 
   3461  1.268     skrll 	return USBD_NORMAL_COMPLETION;
   3462    1.1  augustss }
   3463    1.1  augustss 
   3464    1.1  augustss /* Open a new pipe. */
   3465    1.1  augustss usbd_status
   3466  1.268     skrll uhci_open(struct usbd_pipe *pipe)
   3467    1.1  augustss {
   3468  1.268     skrll 	uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
   3469  1.268     skrll 	struct usbd_bus *bus = pipe->up_dev->ud_bus;
   3470  1.268     skrll 	struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe);
   3471  1.268     skrll 	usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc;
   3472  1.248       mrg 	usbd_status err = USBD_NOMEM;
   3473   1.79  augustss 	int ival;
   3474    1.1  augustss 
   3475  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3476  1.277  pgoyette 	DPRINTF("pipe=%#jx, addr=%jd, endpt=%jd (%jd)",
   3477  1.277  pgoyette 	    (uintptr_t)pipe, pipe->up_dev->ud_addr, ed->bEndpointAddress,
   3478  1.277  pgoyette 	    bus->ub_rhaddr);
   3479   1.92  augustss 
   3480  1.248       mrg 	if (sc->sc_dying)
   3481  1.248       mrg 		return USBD_IOERROR;
   3482  1.248       mrg 
   3483   1.92  augustss 	upipe->aborting = 0;
   3484  1.236  drochner 	/* toggle state needed for bulk endpoints */
   3485  1.268     skrll 	upipe->nexttoggle = pipe->up_endpoint->ue_toggle;
   3486   1.92  augustss 
   3487  1.268     skrll 	if (pipe->up_dev->ud_addr == bus->ub_rhaddr) {
   3488    1.1  augustss 		switch (ed->bEndpointAddress) {
   3489    1.1  augustss 		case USB_CONTROL_ENDPOINT:
   3490  1.268     skrll 			pipe->up_methods = &roothub_ctrl_methods;
   3491    1.1  augustss 			break;
   3492  1.268     skrll 		case UE_DIR_IN | USBROOTHUB_INTR_ENDPT:
   3493  1.268     skrll 			pipe->up_methods = &uhci_root_intr_methods;
   3494    1.1  augustss 			break;
   3495    1.1  augustss 		default:
   3496  1.268     skrll 			return USBD_INVAL;
   3497    1.1  augustss 		}
   3498    1.1  augustss 	} else {
   3499    1.1  augustss 		switch (ed->bmAttributes & UE_XFERTYPE) {
   3500    1.1  augustss 		case UE_CONTROL:
   3501  1.268     skrll 			pipe->up_methods = &uhci_device_ctrl_methods;
   3502  1.268     skrll 			upipe->ctrl.sqh = uhci_alloc_sqh(sc);
   3503  1.268     skrll 			if (upipe->ctrl.sqh == NULL)
   3504    1.5  augustss 				goto bad;
   3505  1.268     skrll 			upipe->ctrl.setup = uhci_alloc_std(sc);
   3506  1.268     skrll 			if (upipe->ctrl.setup == NULL) {
   3507  1.268     skrll 				uhci_free_sqh(sc, upipe->ctrl.sqh);
   3508    1.5  augustss 				goto bad;
   3509    1.5  augustss 			}
   3510  1.268     skrll 			upipe->ctrl.stat = uhci_alloc_std(sc);
   3511  1.268     skrll 			if (upipe->ctrl.stat == NULL) {
   3512  1.268     skrll 				uhci_free_sqh(sc, upipe->ctrl.sqh);
   3513  1.268     skrll 				uhci_free_std(sc, upipe->ctrl.setup);
   3514    1.5  augustss 				goto bad;
   3515    1.5  augustss 			}
   3516  1.152  augustss 			err = usb_allocmem(&sc->sc_bus,
   3517  1.152  augustss 				  sizeof(usb_device_request_t),
   3518  1.268     skrll 				  0, &upipe->ctrl.reqdma);
   3519   1.63  augustss 			if (err) {
   3520  1.268     skrll 				uhci_free_sqh(sc, upipe->ctrl.sqh);
   3521  1.268     skrll 				uhci_free_std(sc, upipe->ctrl.setup);
   3522  1.268     skrll 				uhci_free_std(sc, upipe->ctrl.stat);
   3523    1.5  augustss 				goto bad;
   3524    1.5  augustss 			}
   3525    1.1  augustss 			break;
   3526    1.1  augustss 		case UE_INTERRUPT:
   3527  1.268     skrll 			pipe->up_methods = &uhci_device_intr_methods;
   3528  1.268     skrll 			ival = pipe->up_interval;
   3529   1.79  augustss 			if (ival == USBD_DEFAULT_INTERVAL)
   3530   1.79  augustss 				ival = ed->bInterval;
   3531  1.268     skrll 			return uhci_device_setintr(sc, upipe, ival);
   3532    1.1  augustss 		case UE_ISOCHRONOUS:
   3533  1.268     skrll 			pipe->up_serialise = false;
   3534  1.268     skrll 			pipe->up_methods = &uhci_device_isoc_methods;
   3535  1.268     skrll 			return uhci_setup_isoc(pipe);
   3536    1.1  augustss 		case UE_BULK:
   3537  1.268     skrll 			pipe->up_methods = &uhci_device_bulk_methods;
   3538  1.268     skrll 			upipe->bulk.sqh = uhci_alloc_sqh(sc);
   3539  1.268     skrll 			if (upipe->bulk.sqh == NULL)
   3540    1.5  augustss 				goto bad;
   3541    1.1  augustss 			break;
   3542    1.1  augustss 		}
   3543    1.1  augustss 	}
   3544  1.268     skrll 	return USBD_NORMAL_COMPLETION;
   3545    1.5  augustss 
   3546    1.5  augustss  bad:
   3547  1.248       mrg 	return USBD_NOMEM;
   3548    1.1  augustss }
   3549    1.1  augustss 
   3550    1.1  augustss /*
   3551    1.1  augustss  * Data structures and routines to emulate the root hub.
   3552    1.1  augustss  */
   3553    1.1  augustss /*
   3554  1.166   dsainty  * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also
   3555  1.166   dsainty  * enables the port, and also states that SET_FEATURE(PORT_ENABLE)
   3556  1.166   dsainty  * should not be used by the USB subsystem.  As we cannot issue a
   3557  1.166   dsainty  * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port
   3558  1.166   dsainty  * will be enabled as part of the reset.
   3559  1.166   dsainty  *
   3560  1.166   dsainty  * On the VT83C572, the port cannot be successfully enabled until the
   3561  1.166   dsainty  * outstanding "port enable change" and "connection status change"
   3562  1.166   dsainty  * events have been reset.
   3563  1.166   dsainty  */
   3564  1.166   dsainty Static usbd_status
   3565  1.166   dsainty uhci_portreset(uhci_softc_t *sc, int index)
   3566  1.166   dsainty {
   3567  1.166   dsainty 	int lim, port, x;
   3568  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3569  1.166   dsainty 
   3570  1.166   dsainty 	if (index == 1)
   3571  1.166   dsainty 		port = UHCI_PORTSC1;
   3572  1.166   dsainty 	else if (index == 2)
   3573  1.166   dsainty 		port = UHCI_PORTSC2;
   3574  1.166   dsainty 	else
   3575  1.268     skrll 		return USBD_IOERROR;
   3576  1.166   dsainty 
   3577  1.166   dsainty 	x = URWMASK(UREAD2(sc, port));
   3578  1.166   dsainty 	UWRITE2(sc, port, x | UHCI_PORTSC_PR);
   3579  1.166   dsainty 
   3580  1.166   dsainty 	usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY);
   3581  1.166   dsainty 
   3582  1.277  pgoyette 	DPRINTF("uhci port %jd reset, status0 = 0x%04jx", index,
   3583  1.268     skrll 	    UREAD2(sc, port), 0, 0);
   3584  1.166   dsainty 
   3585  1.166   dsainty 	x = URWMASK(UREAD2(sc, port));
   3586  1.222  drochner 	UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP));
   3587  1.166   dsainty 
   3588  1.166   dsainty 	delay(100);
   3589  1.166   dsainty 
   3590  1.277  pgoyette 	DPRINTF("uhci port %jd reset, status1 = 0x%04jx", index,
   3591  1.268     skrll 	    UREAD2(sc, port), 0, 0);
   3592  1.166   dsainty 
   3593  1.166   dsainty 	x = URWMASK(UREAD2(sc, port));
   3594  1.166   dsainty 	UWRITE2(sc, port, x  | UHCI_PORTSC_PE);
   3595  1.166   dsainty 
   3596  1.166   dsainty 	for (lim = 10; --lim > 0;) {
   3597  1.166   dsainty 		usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY);
   3598  1.166   dsainty 
   3599  1.166   dsainty 		x = UREAD2(sc, port);
   3600  1.277  pgoyette 		DPRINTF("uhci port %jd iteration %ju, status = 0x%04jx", index,
   3601  1.268     skrll 		    lim, x, 0);
   3602  1.166   dsainty 
   3603  1.166   dsainty 		if (!(x & UHCI_PORTSC_CCS)) {
   3604  1.166   dsainty 			/*
   3605  1.166   dsainty 			 * No device is connected (or was disconnected
   3606  1.166   dsainty 			 * during reset).  Consider the port reset.
   3607  1.166   dsainty 			 * The delay must be long enough to ensure on
   3608  1.166   dsainty 			 * the initial iteration that the device
   3609  1.166   dsainty 			 * connection will have been registered.  50ms
   3610  1.166   dsainty 			 * appears to be sufficient, but 20ms is not.
   3611  1.166   dsainty 			 */
   3612  1.277  pgoyette 			DPRINTFN(3, "uhci port %jd loop %ju, device detached",
   3613  1.268     skrll 			    index, lim, 0, 0);
   3614  1.166   dsainty 			break;
   3615  1.166   dsainty 		}
   3616  1.166   dsainty 
   3617  1.166   dsainty 		if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) {
   3618  1.166   dsainty 			/*
   3619  1.166   dsainty 			 * Port enabled changed and/or connection
   3620  1.166   dsainty 			 * status changed were set.  Reset either or
   3621  1.166   dsainty 			 * both raised flags (by writing a 1 to that
   3622  1.166   dsainty 			 * bit), and wait again for state to settle.
   3623  1.166   dsainty 			 */
   3624  1.166   dsainty 			UWRITE2(sc, port, URWMASK(x) |
   3625  1.166   dsainty 				(x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)));
   3626  1.166   dsainty 			continue;
   3627  1.166   dsainty 		}
   3628  1.166   dsainty 
   3629  1.166   dsainty 		if (x & UHCI_PORTSC_PE)
   3630  1.166   dsainty 			/* Port is enabled */
   3631  1.166   dsainty 			break;
   3632  1.166   dsainty 
   3633  1.166   dsainty 		UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE);
   3634  1.166   dsainty 	}
   3635  1.166   dsainty 
   3636  1.277  pgoyette 	DPRINTFN(3, "uhci port %jd reset, status2 = 0x%04jx", index,
   3637  1.268     skrll 	    UREAD2(sc, port), 0, 0);
   3638  1.166   dsainty 
   3639  1.166   dsainty 	if (lim <= 0) {
   3640  1.277  pgoyette 		DPRINTF("uhci port %jd reset timed out", index,
   3641  1.268     skrll 		    0, 0, 0);
   3642  1.268     skrll 		return USBD_TIMEOUT;
   3643  1.166   dsainty 	}
   3644  1.184     perry 
   3645  1.166   dsainty 	sc->sc_isreset = 1;
   3646  1.268     skrll 	return USBD_NORMAL_COMPLETION;
   3647  1.166   dsainty }
   3648  1.166   dsainty 
   3649  1.268     skrll Static int
   3650  1.268     skrll uhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req,
   3651  1.268     skrll     void *buf, int buflen)
   3652    1.1  augustss {
   3653  1.268     skrll 	uhci_softc_t *sc = UHCI_BUS2SC(bus);
   3654    1.1  augustss 	int port, x;
   3655  1.268     skrll 	int status, change, totlen = 0;
   3656  1.268     skrll 	uint16_t len, value, index;
   3657    1.1  augustss 	usb_port_status_t ps;
   3658   1.63  augustss 	usbd_status err;
   3659    1.1  augustss 
   3660  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3661  1.268     skrll 
   3662   1.82  augustss 	if (sc->sc_dying)
   3663  1.268     skrll 		return -1;
   3664    1.1  augustss 
   3665  1.277  pgoyette 	DPRINTF("type=0x%02jx request=%02jx", req->bmRequestType,
   3666  1.268     skrll 	    req->bRequest, 0, 0);
   3667    1.1  augustss 
   3668    1.1  augustss 	len = UGETW(req->wLength);
   3669    1.1  augustss 	value = UGETW(req->wValue);
   3670    1.1  augustss 	index = UGETW(req->wIndex);
   3671   1.49  augustss 
   3672    1.1  augustss #define C(x,y) ((x) | ((y) << 8))
   3673  1.268     skrll 	switch (C(req->bRequest, req->bmRequestType)) {
   3674    1.1  augustss 	case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
   3675  1.277  pgoyette 		DPRINTF("wValue=0x%04jx", value, 0, 0, 0);
   3676  1.195  christos 		if (len == 0)
   3677  1.195  christos 			break;
   3678  1.268     skrll 		switch (value) {
   3679  1.213  drochner #define sd ((usb_string_descriptor_t *)buf)
   3680  1.268     skrll 		case C(2, UDESC_STRING):
   3681  1.268     skrll 			/* Product */
   3682  1.268     skrll 			totlen = usb_makestrdesc(sd, len, "UHCI root hub");
   3683  1.268     skrll 			break;
   3684  1.213  drochner #undef sd
   3685    1.1  augustss 		default:
   3686  1.268     skrll 			/* default from usbroothub */
   3687  1.268     skrll 			return buflen;
   3688    1.1  augustss 		}
   3689    1.1  augustss 		break;
   3690  1.268     skrll 
   3691    1.1  augustss 	/* Hub requests */
   3692    1.1  augustss 	case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
   3693    1.1  augustss 		break;
   3694    1.1  augustss 	case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
   3695  1.277  pgoyette 		DPRINTF("UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", index,
   3696  1.268     skrll 		    value, 0, 0);
   3697    1.1  augustss 		if (index == 1)
   3698    1.1  augustss 			port = UHCI_PORTSC1;
   3699    1.1  augustss 		else if (index == 2)
   3700    1.1  augustss 			port = UHCI_PORTSC2;
   3701    1.1  augustss 		else {
   3702  1.268     skrll 			return -1;
   3703    1.1  augustss 		}
   3704    1.1  augustss 		switch(value) {
   3705    1.1  augustss 		case UHF_PORT_ENABLE:
   3706  1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3707    1.1  augustss 			UWRITE2(sc, port, x & ~UHCI_PORTSC_PE);
   3708    1.1  augustss 			break;
   3709    1.1  augustss 		case UHF_PORT_SUSPEND:
   3710  1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3711  1.222  drochner 			if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */
   3712  1.222  drochner 				break;
   3713  1.222  drochner 			UWRITE2(sc, port, x | UHCI_PORTSC_RD);
   3714  1.222  drochner 			/* see USB2 spec ch. 7.1.7.7 */
   3715  1.222  drochner 			usb_delay_ms(&sc->sc_bus, 20);
   3716    1.1  augustss 			UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP);
   3717  1.222  drochner 			/* 10ms resume delay must be provided by caller */
   3718    1.1  augustss 			break;
   3719    1.1  augustss 		case UHF_PORT_RESET:
   3720  1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3721    1.1  augustss 			UWRITE2(sc, port, x & ~UHCI_PORTSC_PR);
   3722    1.1  augustss 			break;
   3723    1.1  augustss 		case UHF_C_PORT_CONNECTION:
   3724  1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3725    1.1  augustss 			UWRITE2(sc, port, x | UHCI_PORTSC_CSC);
   3726    1.1  augustss 			break;
   3727    1.1  augustss 		case UHF_C_PORT_ENABLE:
   3728  1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3729    1.1  augustss 			UWRITE2(sc, port, x | UHCI_PORTSC_POEDC);
   3730    1.1  augustss 			break;
   3731    1.1  augustss 		case UHF_C_PORT_OVER_CURRENT:
   3732  1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3733    1.1  augustss 			UWRITE2(sc, port, x | UHCI_PORTSC_OCIC);
   3734    1.1  augustss 			break;
   3735    1.1  augustss 		case UHF_C_PORT_RESET:
   3736    1.1  augustss 			sc->sc_isreset = 0;
   3737  1.268     skrll 			break;
   3738    1.1  augustss 		case UHF_PORT_CONNECTION:
   3739    1.1  augustss 		case UHF_PORT_OVER_CURRENT:
   3740    1.1  augustss 		case UHF_PORT_POWER:
   3741    1.1  augustss 		case UHF_PORT_LOW_SPEED:
   3742    1.1  augustss 		case UHF_C_PORT_SUSPEND:
   3743    1.1  augustss 		default:
   3744  1.268     skrll 			return -1;
   3745    1.1  augustss 		}
   3746    1.1  augustss 		break;
   3747    1.1  augustss 	case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER):
   3748    1.1  augustss 		if (index == 1)
   3749    1.1  augustss 			port = UHCI_PORTSC1;
   3750    1.1  augustss 		else if (index == 2)
   3751    1.1  augustss 			port = UHCI_PORTSC2;
   3752    1.1  augustss 		else {
   3753  1.268     skrll 			return -1;
   3754    1.1  augustss 		}
   3755    1.1  augustss 		if (len > 0) {
   3756  1.268     skrll 			*(uint8_t *)buf =
   3757  1.268     skrll 			    UHCI_PORTSC_GET_LS(UREAD2(sc, port));
   3758    1.1  augustss 			totlen = 1;
   3759    1.1  augustss 		}
   3760    1.1  augustss 		break;
   3761    1.1  augustss 	case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
   3762  1.195  christos 		if (len == 0)
   3763  1.195  christos 			break;
   3764  1.177    toshii 		if ((value & 0xff) != 0) {
   3765  1.268     skrll 			return -1;
   3766    1.1  augustss 		}
   3767  1.268     skrll 		usb_hub_descriptor_t hubd;
   3768  1.268     skrll 
   3769  1.283  riastrad 		totlen = uimin(buflen, sizeof(hubd));
   3770  1.268     skrll 		memcpy(&hubd, buf, totlen);
   3771  1.268     skrll 		hubd.bNbrPorts = 2;
   3772  1.268     skrll 		memcpy(buf, &hubd, totlen);
   3773    1.1  augustss 		break;
   3774    1.1  augustss 	case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
   3775    1.1  augustss 		if (len != 4) {
   3776  1.268     skrll 			return -1;
   3777    1.1  augustss 		}
   3778    1.1  augustss 		memset(buf, 0, len);
   3779    1.1  augustss 		totlen = len;
   3780    1.1  augustss 		break;
   3781    1.1  augustss 	case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
   3782    1.1  augustss 		if (index == 1)
   3783    1.1  augustss 			port = UHCI_PORTSC1;
   3784    1.1  augustss 		else if (index == 2)
   3785    1.1  augustss 			port = UHCI_PORTSC2;
   3786    1.1  augustss 		else {
   3787  1.268     skrll 			return -1;
   3788    1.1  augustss 		}
   3789    1.1  augustss 		if (len != 4) {
   3790  1.268     skrll 			return -1;
   3791    1.1  augustss 		}
   3792    1.1  augustss 		x = UREAD2(sc, port);
   3793    1.1  augustss 		status = change = 0;
   3794  1.142  augustss 		if (x & UHCI_PORTSC_CCS)
   3795    1.1  augustss 			status |= UPS_CURRENT_CONNECT_STATUS;
   3796  1.152  augustss 		if (x & UHCI_PORTSC_CSC)
   3797    1.1  augustss 			change |= UPS_C_CONNECT_STATUS;
   3798  1.152  augustss 		if (x & UHCI_PORTSC_PE)
   3799    1.1  augustss 			status |= UPS_PORT_ENABLED;
   3800  1.152  augustss 		if (x & UHCI_PORTSC_POEDC)
   3801    1.1  augustss 			change |= UPS_C_PORT_ENABLED;
   3802  1.152  augustss 		if (x & UHCI_PORTSC_OCI)
   3803    1.1  augustss 			status |= UPS_OVERCURRENT_INDICATOR;
   3804  1.152  augustss 		if (x & UHCI_PORTSC_OCIC)
   3805    1.1  augustss 			change |= UPS_C_OVERCURRENT_INDICATOR;
   3806  1.152  augustss 		if (x & UHCI_PORTSC_SUSP)
   3807    1.1  augustss 			status |= UPS_SUSPEND;
   3808  1.152  augustss 		if (x & UHCI_PORTSC_LSDA)
   3809    1.1  augustss 			status |= UPS_LOW_SPEED;
   3810    1.1  augustss 		status |= UPS_PORT_POWER;
   3811    1.1  augustss 		if (sc->sc_isreset)
   3812    1.1  augustss 			change |= UPS_C_PORT_RESET;
   3813    1.1  augustss 		USETW(ps.wPortStatus, status);
   3814    1.1  augustss 		USETW(ps.wPortChange, change);
   3815  1.283  riastrad 		totlen = uimin(len, sizeof(ps));
   3816  1.268     skrll 		memcpy(buf, &ps, totlen);
   3817    1.1  augustss 		break;
   3818    1.1  augustss 	case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
   3819  1.268     skrll 		return -1;
   3820    1.1  augustss 	case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
   3821    1.1  augustss 		break;
   3822    1.1  augustss 	case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
   3823    1.1  augustss 		if (index == 1)
   3824    1.1  augustss 			port = UHCI_PORTSC1;
   3825    1.1  augustss 		else if (index == 2)
   3826    1.1  augustss 			port = UHCI_PORTSC2;
   3827    1.1  augustss 		else {
   3828  1.268     skrll 			return -1;
   3829    1.1  augustss 		}
   3830    1.1  augustss 		switch(value) {
   3831    1.1  augustss 		case UHF_PORT_ENABLE:
   3832  1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3833    1.1  augustss 			UWRITE2(sc, port, x | UHCI_PORTSC_PE);
   3834    1.1  augustss 			break;
   3835    1.1  augustss 		case UHF_PORT_SUSPEND:
   3836  1.137  augustss 			x = URWMASK(UREAD2(sc, port));
   3837    1.1  augustss 			UWRITE2(sc, port, x | UHCI_PORTSC_SUSP);
   3838    1.1  augustss 			break;
   3839    1.1  augustss 		case UHF_PORT_RESET:
   3840  1.166   dsainty 			err = uhci_portreset(sc, index);
   3841  1.268     skrll 			if (err != USBD_NORMAL_COMPLETION)
   3842  1.268     skrll 				return -1;
   3843  1.268     skrll 			return 0;
   3844  1.111  augustss 		case UHF_PORT_POWER:
   3845  1.111  augustss 			/* Pretend we turned on power */
   3846  1.268     skrll 			return 0;
   3847    1.1  augustss 		case UHF_C_PORT_CONNECTION:
   3848    1.1  augustss 		case UHF_C_PORT_ENABLE:
   3849    1.1  augustss 		case UHF_C_PORT_OVER_CURRENT:
   3850    1.1  augustss 		case UHF_PORT_CONNECTION:
   3851    1.1  augustss 		case UHF_PORT_OVER_CURRENT:
   3852    1.1  augustss 		case UHF_PORT_LOW_SPEED:
   3853    1.1  augustss 		case UHF_C_PORT_SUSPEND:
   3854    1.1  augustss 		case UHF_C_PORT_RESET:
   3855    1.1  augustss 		default:
   3856  1.268     skrll 			return -1;
   3857    1.1  augustss 		}
   3858    1.1  augustss 		break;
   3859    1.1  augustss 	default:
   3860  1.268     skrll 		/* default from usbroothub */
   3861  1.277  pgoyette 		DPRINTF("returning %jd (usbroothub default)",
   3862  1.268     skrll 		    buflen, 0, 0, 0);
   3863  1.268     skrll 		return buflen;
   3864    1.1  augustss 	}
   3865    1.1  augustss 
   3866  1.277  pgoyette 	DPRINTF("returning %jd", totlen, 0, 0, 0);
   3867    1.1  augustss 
   3868  1.268     skrll 	return totlen;
   3869    1.1  augustss }
   3870    1.1  augustss 
   3871    1.1  augustss /* Abort a root interrupt request. */
   3872    1.1  augustss void
   3873  1.268     skrll uhci_root_intr_abort(struct usbd_xfer *xfer)
   3874    1.1  augustss {
   3875  1.268     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   3876   1.30  augustss 
   3877  1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   3878  1.268     skrll 	KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
   3879  1.248       mrg 
   3880  1.234    dyoung 	callout_stop(&sc->sc_poll_handle);
   3881   1.96  augustss 	sc->sc_intr_xfer = NULL;
   3882   1.58  augustss 
   3883  1.268     skrll 	xfer->ux_status = USBD_CANCELLED;
   3884   1.96  augustss #ifdef DIAGNOSTIC
   3885  1.268     skrll 	UHCI_XFER2UXFER(xfer)->ux_isdone = true;
   3886   1.96  augustss #endif
   3887   1.63  augustss 	usb_transfer_complete(xfer);
   3888    1.1  augustss }
   3889    1.1  augustss 
   3890   1.16  augustss usbd_status
   3891  1.268     skrll uhci_root_intr_transfer(struct usbd_xfer *xfer)
   3892   1.16  augustss {
   3893  1.268     skrll 	uhci_softc_t *sc = UHCI_XFER2SC(xfer);
   3894   1.63  augustss 	usbd_status err;
   3895   1.16  augustss 
   3896   1.52  augustss 	/* Insert last in queue. */
   3897  1.248       mrg 	mutex_enter(&sc->sc_lock);
   3898   1.63  augustss 	err = usb_insert_transfer(xfer);
   3899  1.248       mrg 	mutex_exit(&sc->sc_lock);
   3900   1.63  augustss 	if (err)
   3901  1.268     skrll 		return err;
   3902   1.52  augustss 
   3903  1.186     skrll 	/*
   3904  1.186     skrll 	 * Pipe isn't running (otherwise err would be USBD_INPROG),
   3905   1.67  augustss 	 * start first
   3906   1.67  augustss 	 */
   3907  1.268     skrll 	return uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
   3908   1.16  augustss }
   3909   1.16  augustss 
   3910    1.1  augustss /* Start a transfer on the root interrupt pipe */
   3911    1.1  augustss usbd_status
   3912  1.268     skrll uhci_root_intr_start(struct usbd_xfer *xfer)
   3913    1.1  augustss {
   3914  1.268     skrll 	struct usbd_pipe *pipe = xfer->ux_pipe;
   3915  1.268     skrll 	uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
   3916  1.174  drochner 	unsigned int ival;
   3917    1.1  augustss 
   3918  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3919  1.277  pgoyette 	DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length,
   3920  1.268     skrll 	    xfer->ux_flags, 0);
   3921   1.82  augustss 
   3922   1.82  augustss 	if (sc->sc_dying)
   3923  1.268     skrll 		return USBD_IOERROR;
   3924    1.1  augustss 
   3925  1.174  drochner 	/* XXX temporary variable needed to avoid gcc3 warning */
   3926  1.268     skrll 	ival = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval;
   3927  1.174  drochner 	sc->sc_ival = mstohz(ival);
   3928  1.234    dyoung 	callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer);
   3929   1.96  augustss 	sc->sc_intr_xfer = xfer;
   3930  1.268     skrll 	return USBD_IN_PROGRESS;
   3931    1.1  augustss }
   3932    1.1  augustss 
   3933    1.1  augustss /* Close the root interrupt pipe. */
   3934    1.1  augustss void
   3935  1.268     skrll uhci_root_intr_close(struct usbd_pipe *pipe)
   3936    1.1  augustss {
   3937  1.268     skrll 	uhci_softc_t *sc = UHCI_PIPE2SC(pipe);
   3938  1.268     skrll 	UHCIHIST_FUNC(); UHCIHIST_CALLED();
   3939   1.30  augustss 
   3940  1.248       mrg 	KASSERT(mutex_owned(&sc->sc_lock));
   3941  1.248       mrg 
   3942  1.234    dyoung 	callout_stop(&sc->sc_poll_handle);
   3943   1.96  augustss 	sc->sc_intr_xfer = NULL;
   3944    1.1  augustss }
   3945