uhci.c revision 1.205.2.2
1 /* $NetBSD: uhci.c,v 1.205.2.2 2008/08/31 16:48:29 jdc Exp $ */ 2 /* $FreeBSD: src/sys/dev/usb/uhci.c,v 1.33 1999/11/17 22:33:41 n_hibma Exp $ */ 3 4 /* 5 * Copyright (c) 1998, 2004 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Lennart Augustsson (lennart (at) augustsson.net) at 10 * Carlstedt Research & Technology. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the NetBSD 23 * Foundation, Inc. and its contributors. 24 * 4. Neither the name of The NetBSD Foundation nor the names of its 25 * contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 41 /* 42 * USB Universal Host Controller driver. 43 * Handles e.g. PIIX3 and PIIX4. 44 * 45 * UHCI spec: http://developer.intel.com/design/USB/UHCI11D.htm 46 * USB spec: http://www.usb.org/developers/docs/usbspec.zip 47 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 48 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 49 */ 50 51 #include <sys/cdefs.h> 52 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.205.2.2 2008/08/31 16:48:29 jdc Exp $"); 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/kernel.h> 57 #include <sys/malloc.h> 58 #if defined(__NetBSD__) || defined(__OpenBSD__) 59 #include <sys/device.h> 60 #include <sys/select.h> 61 #include <sys/extent.h> 62 #include <uvm/uvm_extern.h> 63 #elif defined(__FreeBSD__) 64 #include <sys/module.h> 65 #include <sys/bus.h> 66 #include <machine/bus_pio.h> 67 #if defined(DIAGNOSTIC) && defined(__i386__) 68 #include <machine/cpu.h> 69 #endif 70 #endif 71 #include <sys/proc.h> 72 #include <sys/queue.h> 73 74 #include <machine/bus.h> 75 #include <machine/endian.h> 76 77 #include <dev/usb/usb.h> 78 #include <dev/usb/usbdi.h> 79 #include <dev/usb/usbdivar.h> 80 #include <dev/usb/usb_mem.h> 81 #include <dev/usb/usb_quirks.h> 82 83 #include <dev/usb/uhcireg.h> 84 #include <dev/usb/uhcivar.h> 85 86 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 87 /*#define UHCI_CTL_LOOP */ 88 89 #if defined(__FreeBSD__) 90 #include <machine/clock.h> 91 92 #define delay(d) DELAY(d) 93 #endif 94 95 #if defined(__OpenBSD__) 96 struct cfdriver uhci_cd = { 97 NULL, "uhci", DV_DULL 98 }; 99 #endif 100 101 #ifdef UHCI_DEBUG 102 uhci_softc_t *thesc; 103 #define DPRINTF(x) if (uhcidebug) printf x 104 #define DPRINTFN(n,x) if (uhcidebug>(n)) printf x 105 int uhcidebug = 0; 106 int uhcinoloop = 0; 107 #ifndef __NetBSD__ 108 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f)) 109 #endif 110 #else 111 #define DPRINTF(x) 112 #define DPRINTFN(n,x) 113 #endif 114 115 /* 116 * The UHCI controller is little endian, so on big endian machines 117 * the data stored in memory needs to be swapped. 118 */ 119 #if defined(__FreeBSD__) || defined(__OpenBSD__) 120 #if BYTE_ORDER == BIG_ENDIAN 121 #define htole32(x) (bswap32(x)) 122 #define le32toh(x) (bswap32(x)) 123 #else 124 #define htole32(x) (x) 125 #define le32toh(x) (x) 126 #endif 127 #endif 128 129 struct uhci_pipe { 130 struct usbd_pipe pipe; 131 int nexttoggle; 132 133 u_char aborting; 134 usbd_xfer_handle abortstart, abortend; 135 136 /* Info needed for different pipe kinds. */ 137 union { 138 /* Control pipe */ 139 struct { 140 uhci_soft_qh_t *sqh; 141 usb_dma_t reqdma; 142 uhci_soft_td_t *setup, *stat; 143 u_int length; 144 } ctl; 145 /* Interrupt pipe */ 146 struct { 147 int npoll; 148 int isread; 149 uhci_soft_qh_t **qhs; 150 } intr; 151 /* Bulk pipe */ 152 struct { 153 uhci_soft_qh_t *sqh; 154 u_int length; 155 int isread; 156 } bulk; 157 /* Iso pipe */ 158 struct iso { 159 uhci_soft_td_t **stds; 160 int next, inuse; 161 } iso; 162 } u; 163 }; 164 165 Static void uhci_globalreset(uhci_softc_t *); 166 Static usbd_status uhci_portreset(uhci_softc_t*, int); 167 Static void uhci_reset(uhci_softc_t *); 168 Static void uhci_shutdown(void *v); 169 Static void uhci_power(int, void *); 170 Static usbd_status uhci_run(uhci_softc_t *, int run); 171 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 172 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 173 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 174 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 175 #if 0 176 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 177 uhci_intr_info_t *); 178 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 179 #endif 180 181 Static void uhci_free_std_chain(uhci_softc_t *, 182 uhci_soft_td_t *, uhci_soft_td_t *); 183 Static usbd_status uhci_alloc_std_chain(struct uhci_pipe *, 184 uhci_softc_t *, int, int, u_int16_t, usb_dma_t *, 185 uhci_soft_td_t **, uhci_soft_td_t **); 186 Static void uhci_poll_hub(void *); 187 Static void uhci_waitintr(uhci_softc_t *, usbd_xfer_handle); 188 Static void uhci_check_intr(uhci_softc_t *, uhci_intr_info_t *); 189 Static void uhci_idone(uhci_intr_info_t *); 190 191 Static void uhci_abort_xfer(usbd_xfer_handle, usbd_status status); 192 193 Static void uhci_timeout(void *); 194 Static void uhci_timeout_task(void *); 195 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 196 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 197 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 198 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 199 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 200 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 201 Static int uhci_str(usb_string_descriptor_t *, int, const char *); 202 Static void uhci_add_loop(uhci_softc_t *sc); 203 Static void uhci_rem_loop(uhci_softc_t *sc); 204 205 Static usbd_status uhci_setup_isoc(usbd_pipe_handle pipe); 206 Static void uhci_device_isoc_enter(usbd_xfer_handle); 207 208 Static usbd_status uhci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 209 Static void uhci_freem(struct usbd_bus *, usb_dma_t *); 210 211 Static usbd_xfer_handle uhci_allocx(struct usbd_bus *); 212 Static void uhci_freex(struct usbd_bus *, usbd_xfer_handle); 213 214 Static usbd_status uhci_device_ctrl_transfer(usbd_xfer_handle); 215 Static usbd_status uhci_device_ctrl_start(usbd_xfer_handle); 216 Static void uhci_device_ctrl_abort(usbd_xfer_handle); 217 Static void uhci_device_ctrl_close(usbd_pipe_handle); 218 Static void uhci_device_ctrl_done(usbd_xfer_handle); 219 220 Static usbd_status uhci_device_intr_transfer(usbd_xfer_handle); 221 Static usbd_status uhci_device_intr_start(usbd_xfer_handle); 222 Static void uhci_device_intr_abort(usbd_xfer_handle); 223 Static void uhci_device_intr_close(usbd_pipe_handle); 224 Static void uhci_device_intr_done(usbd_xfer_handle); 225 226 Static usbd_status uhci_device_bulk_transfer(usbd_xfer_handle); 227 Static usbd_status uhci_device_bulk_start(usbd_xfer_handle); 228 Static void uhci_device_bulk_abort(usbd_xfer_handle); 229 Static void uhci_device_bulk_close(usbd_pipe_handle); 230 Static void uhci_device_bulk_done(usbd_xfer_handle); 231 232 Static usbd_status uhci_device_isoc_transfer(usbd_xfer_handle); 233 Static usbd_status uhci_device_isoc_start(usbd_xfer_handle); 234 Static void uhci_device_isoc_abort(usbd_xfer_handle); 235 Static void uhci_device_isoc_close(usbd_pipe_handle); 236 Static void uhci_device_isoc_done(usbd_xfer_handle); 237 238 Static usbd_status uhci_root_ctrl_transfer(usbd_xfer_handle); 239 Static usbd_status uhci_root_ctrl_start(usbd_xfer_handle); 240 Static void uhci_root_ctrl_abort(usbd_xfer_handle); 241 Static void uhci_root_ctrl_close(usbd_pipe_handle); 242 Static void uhci_root_ctrl_done(usbd_xfer_handle); 243 244 Static usbd_status uhci_root_intr_transfer(usbd_xfer_handle); 245 Static usbd_status uhci_root_intr_start(usbd_xfer_handle); 246 Static void uhci_root_intr_abort(usbd_xfer_handle); 247 Static void uhci_root_intr_close(usbd_pipe_handle); 248 Static void uhci_root_intr_done(usbd_xfer_handle); 249 250 Static usbd_status uhci_open(usbd_pipe_handle); 251 Static void uhci_poll(struct usbd_bus *); 252 Static void uhci_softintr(void *); 253 254 Static usbd_status uhci_device_request(usbd_xfer_handle xfer); 255 256 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 257 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 258 Static usbd_status uhci_device_setintr(uhci_softc_t *sc, 259 struct uhci_pipe *pipe, int ival); 260 261 Static void uhci_device_clear_toggle(usbd_pipe_handle pipe); 262 Static void uhci_noop(usbd_pipe_handle pipe); 263 264 Static inline uhci_soft_qh_t *uhci_find_prev_qh(uhci_soft_qh_t *, 265 uhci_soft_qh_t *); 266 267 #ifdef UHCI_DEBUG 268 Static void uhci_dump_all(uhci_softc_t *); 269 Static void uhci_dumpregs(uhci_softc_t *); 270 Static void uhci_dump_qhs(uhci_soft_qh_t *); 271 Static void uhci_dump_qh(uhci_soft_qh_t *); 272 Static void uhci_dump_tds(uhci_soft_td_t *); 273 Static void uhci_dump_td(uhci_soft_td_t *); 274 Static void uhci_dump_ii(uhci_intr_info_t *ii); 275 void uhci_dump(void); 276 #endif 277 278 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 279 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 280 #define UWRITE1(sc, r, x) \ 281 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 282 } while (/*CONSTCOND*/0) 283 #define UWRITE2(sc, r, x) \ 284 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 285 } while (/*CONSTCOND*/0) 286 #define UWRITE4(sc, r, x) \ 287 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 288 } while (/*CONSTCOND*/0) 289 static __inline uint8_t 290 UREAD1(uhci_softc_t *sc, bus_size_t r) 291 { 292 293 UBARR(sc); 294 return bus_space_read_1(sc->iot, sc->ioh, r); 295 } 296 297 static __inline uint16_t 298 UREAD2(uhci_softc_t *sc, bus_size_t r) 299 { 300 301 UBARR(sc); 302 return bus_space_read_2(sc->iot, sc->ioh, r); 303 } 304 305 static __inline uint32_t 306 UREAD4(uhci_softc_t *sc, bus_size_t r) 307 { 308 309 UBARR(sc); 310 return bus_space_read_4(sc->iot, sc->ioh, r); 311 } 312 313 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 314 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 315 316 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 317 318 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 319 320 #define UHCI_INTR_ENDPT 1 321 322 struct usbd_bus_methods uhci_bus_methods = { 323 uhci_open, 324 uhci_softintr, 325 uhci_poll, 326 uhci_allocm, 327 uhci_freem, 328 uhci_allocx, 329 uhci_freex, 330 }; 331 332 struct usbd_pipe_methods uhci_root_ctrl_methods = { 333 uhci_root_ctrl_transfer, 334 uhci_root_ctrl_start, 335 uhci_root_ctrl_abort, 336 uhci_root_ctrl_close, 337 uhci_noop, 338 uhci_root_ctrl_done, 339 }; 340 341 struct usbd_pipe_methods uhci_root_intr_methods = { 342 uhci_root_intr_transfer, 343 uhci_root_intr_start, 344 uhci_root_intr_abort, 345 uhci_root_intr_close, 346 uhci_noop, 347 uhci_root_intr_done, 348 }; 349 350 struct usbd_pipe_methods uhci_device_ctrl_methods = { 351 uhci_device_ctrl_transfer, 352 uhci_device_ctrl_start, 353 uhci_device_ctrl_abort, 354 uhci_device_ctrl_close, 355 uhci_noop, 356 uhci_device_ctrl_done, 357 }; 358 359 struct usbd_pipe_methods uhci_device_intr_methods = { 360 uhci_device_intr_transfer, 361 uhci_device_intr_start, 362 uhci_device_intr_abort, 363 uhci_device_intr_close, 364 uhci_device_clear_toggle, 365 uhci_device_intr_done, 366 }; 367 368 struct usbd_pipe_methods uhci_device_bulk_methods = { 369 uhci_device_bulk_transfer, 370 uhci_device_bulk_start, 371 uhci_device_bulk_abort, 372 uhci_device_bulk_close, 373 uhci_device_clear_toggle, 374 uhci_device_bulk_done, 375 }; 376 377 struct usbd_pipe_methods uhci_device_isoc_methods = { 378 uhci_device_isoc_transfer, 379 uhci_device_isoc_start, 380 uhci_device_isoc_abort, 381 uhci_device_isoc_close, 382 uhci_noop, 383 uhci_device_isoc_done, 384 }; 385 386 #define uhci_add_intr_info(sc, ii) \ 387 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ii), list) 388 #define uhci_del_intr_info(ii) \ 389 do { \ 390 LIST_REMOVE((ii), list); \ 391 (ii)->list.le_prev = NULL; \ 392 } while (0) 393 #define uhci_active_intr_info(ii) ((ii)->list.le_prev != NULL) 394 395 Static inline uhci_soft_qh_t * 396 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 397 { 398 DPRINTFN(15,("uhci_find_prev_qh: pqh=%p sqh=%p\n", pqh, sqh)); 399 400 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 401 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 402 usb_syncmem(&pqh->dma, 403 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 404 sizeof(pqh->qh.qh_hlink), 405 BUS_DMASYNC_POSTWRITE); 406 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 407 printf("uhci_find_prev_qh: QH not found\n"); 408 return (NULL); 409 } 410 #endif 411 } 412 return (pqh); 413 } 414 415 void 416 uhci_globalreset(uhci_softc_t *sc) 417 { 418 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 419 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 420 UHCICMD(sc, 0); /* do nothing */ 421 } 422 423 usbd_status 424 uhci_init(uhci_softc_t *sc) 425 { 426 usbd_status err; 427 int i, j; 428 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 429 uhci_soft_td_t *std; 430 431 DPRINTFN(1,("uhci_init: start\n")); 432 433 #ifdef UHCI_DEBUG 434 thesc = sc; 435 436 if (uhcidebug > 2) 437 uhci_dumpregs(sc); 438 #endif 439 440 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 441 uhci_globalreset(sc); /* reset the controller */ 442 uhci_reset(sc); 443 444 #ifdef __NetBSD__ 445 usb_setup_reserve(sc, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 446 USB_MEM_RESERVE); 447 #endif 448 449 /* Allocate and initialize real frame array. */ 450 err = usb_allocmem(&sc->sc_bus, 451 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 452 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 453 if (err) 454 return (err); 455 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 456 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 457 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 458 459 /* 460 * Allocate a TD, inactive, that hangs from the last QH. 461 * This is to avoid a bug in the PIIX that makes it run berserk 462 * otherwise. 463 */ 464 std = uhci_alloc_std(sc); 465 if (std == NULL) 466 return (USBD_NOMEM); 467 std->link.std = NULL; 468 std->td.td_link = htole32(UHCI_PTR_T); 469 std->td.td_status = htole32(0); /* inactive */ 470 std->td.td_token = htole32(0); 471 std->td.td_buffer = htole32(0); 472 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 473 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 474 475 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 476 lsqh = uhci_alloc_sqh(sc); 477 if (lsqh == NULL) 478 return (USBD_NOMEM); 479 lsqh->hlink = NULL; 480 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 481 lsqh->elink = std; 482 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 483 sc->sc_last_qh = lsqh; 484 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 485 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 486 487 /* Allocate the dummy QH where bulk traffic will be queued. */ 488 bsqh = uhci_alloc_sqh(sc); 489 if (bsqh == NULL) 490 return (USBD_NOMEM); 491 bsqh->hlink = lsqh; 492 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 493 bsqh->elink = NULL; 494 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 495 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 496 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 497 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 498 499 /* Allocate dummy QH where high speed control traffic will be queued. */ 500 chsqh = uhci_alloc_sqh(sc); 501 if (chsqh == NULL) 502 return (USBD_NOMEM); 503 chsqh->hlink = bsqh; 504 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 505 chsqh->elink = NULL; 506 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 507 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 508 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 509 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 510 511 /* Allocate dummy QH where control traffic will be queued. */ 512 clsqh = uhci_alloc_sqh(sc); 513 if (clsqh == NULL) 514 return (USBD_NOMEM); 515 clsqh->hlink = bsqh; 516 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 517 clsqh->elink = NULL; 518 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 519 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 520 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 521 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 522 523 /* 524 * Make all (virtual) frame list pointers point to the interrupt 525 * queue heads and the interrupt queue heads at the control 526 * queue head and point the physical frame list to the virtual. 527 */ 528 for(i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 529 std = uhci_alloc_std(sc); 530 sqh = uhci_alloc_sqh(sc); 531 if (std == NULL || sqh == NULL) 532 return (USBD_NOMEM); 533 std->link.sqh = sqh; 534 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 535 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 536 std->td.td_token = htole32(0); 537 std->td.td_buffer = htole32(0); 538 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 539 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 540 sqh->hlink = clsqh; 541 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 542 sqh->elink = NULL; 543 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 544 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 545 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 546 sc->sc_vframes[i].htd = std; 547 sc->sc_vframes[i].etd = std; 548 sc->sc_vframes[i].hqh = sqh; 549 sc->sc_vframes[i].eqh = sqh; 550 for (j = i; 551 j < UHCI_FRAMELIST_COUNT; 552 j += UHCI_VFRAMELIST_COUNT) 553 sc->sc_pframes[j] = htole32(std->physaddr); 554 } 555 usb_syncmem(&sc->sc_dma, 0, 556 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 557 BUS_DMASYNC_PREWRITE); 558 559 560 LIST_INIT(&sc->sc_intrhead); 561 562 SIMPLEQ_INIT(&sc->sc_free_xfers); 563 564 usb_callout_init(sc->sc_poll_handle); 565 566 /* Set up the bus struct. */ 567 sc->sc_bus.methods = &uhci_bus_methods; 568 sc->sc_bus.pipe_size = sizeof(struct uhci_pipe); 569 570 #if defined(__NetBSD__) || defined(__OpenBSD__) 571 sc->sc_suspend = PWR_RESUME; 572 sc->sc_powerhook = powerhook_establish(USBDEVNAME(sc->sc_bus.bdev), 573 uhci_power, sc); 574 sc->sc_shutdownhook = shutdownhook_establish(uhci_shutdown, sc); 575 #endif 576 577 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 578 579 DPRINTFN(1,("uhci_init: enabling\n")); 580 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 581 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 582 583 return (uhci_run(sc, 1)); /* and here we go... */ 584 } 585 586 #if defined(__NetBSD__) || defined(__OpenBSD__) 587 int 588 uhci_activate(device_ptr_t self, enum devact act) 589 { 590 struct uhci_softc *sc = (struct uhci_softc *)self; 591 int rv = 0; 592 593 switch (act) { 594 case DVACT_ACTIVATE: 595 return (EOPNOTSUPP); 596 597 case DVACT_DEACTIVATE: 598 if (sc->sc_child != NULL) 599 rv = config_deactivate(sc->sc_child); 600 break; 601 } 602 return (rv); 603 } 604 605 int 606 uhci_detach(struct uhci_softc *sc, int flags) 607 { 608 usbd_xfer_handle xfer; 609 int rv = 0; 610 611 if (sc->sc_child != NULL) 612 rv = config_detach(sc->sc_child, flags); 613 614 if (rv != 0) 615 return (rv); 616 617 #if defined(__NetBSD__) || defined(__OpenBSD__) 618 powerhook_disestablish(sc->sc_powerhook); 619 shutdownhook_disestablish(sc->sc_shutdownhook); 620 #endif 621 622 /* Free all xfers associated with this HC. */ 623 for (;;) { 624 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 625 if (xfer == NULL) 626 break; 627 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 628 free(xfer, M_USB); 629 } 630 631 /* XXX free other data structures XXX */ 632 633 return (rv); 634 } 635 #endif 636 637 usbd_status 638 uhci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 639 { 640 struct uhci_softc *sc = (struct uhci_softc *)bus; 641 usbd_status status; 642 u_int32_t n; 643 644 /* 645 * XXX 646 * Since we are allocating a buffer we can assume that we will 647 * need TDs for it. Since we don't want to allocate those from 648 * an interrupt context, we allocate them here and free them again. 649 * This is no guarantee that we'll get the TDs next time... 650 */ 651 n = size / 8; 652 if (n > 16) { 653 u_int32_t i; 654 uhci_soft_td_t **stds; 655 DPRINTF(("uhci_allocm: get %d TDs\n", n)); 656 stds = malloc(sizeof(uhci_soft_td_t *) * n, M_TEMP, 657 M_WAITOK|M_ZERO); 658 for(i=0; i < n; i++) 659 stds[i] = uhci_alloc_std(sc); 660 for(i=0; i < n; i++) 661 if (stds[i] != NULL) 662 uhci_free_std(sc, stds[i]); 663 free(stds, M_TEMP); 664 } 665 666 667 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 668 #ifdef __NetBSD__ 669 if (status == USBD_NOMEM) 670 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 671 #endif 672 return status; 673 } 674 675 void 676 uhci_freem(struct usbd_bus *bus, usb_dma_t *dma) 677 { 678 #ifdef __NetBSD__ 679 if (dma->block->flags & USB_DMA_RESERVE) { 680 usb_reserve_freem(&((struct uhci_softc *)bus)->sc_dma_reserve, 681 dma); 682 return; 683 } 684 #endif 685 usb_freemem(&((struct uhci_softc *)bus)->sc_bus, dma); 686 } 687 688 usbd_xfer_handle 689 uhci_allocx(struct usbd_bus *bus) 690 { 691 struct uhci_softc *sc = (struct uhci_softc *)bus; 692 usbd_xfer_handle xfer; 693 694 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 695 if (xfer != NULL) { 696 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 697 #ifdef DIAGNOSTIC 698 if (xfer->busy_free != XFER_FREE) { 699 printf("uhci_allocx: xfer=%p not free, 0x%08x\n", xfer, 700 xfer->busy_free); 701 } 702 #endif 703 } else { 704 xfer = malloc(sizeof(struct uhci_xfer), M_USB, M_NOWAIT); 705 } 706 if (xfer != NULL) { 707 memset(xfer, 0, sizeof (struct uhci_xfer)); 708 UXFER(xfer)->iinfo.sc = sc; 709 #ifdef DIAGNOSTIC 710 UXFER(xfer)->iinfo.isdone = 1; 711 xfer->busy_free = XFER_BUSY; 712 #endif 713 } 714 return (xfer); 715 } 716 717 void 718 uhci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 719 { 720 struct uhci_softc *sc = (struct uhci_softc *)bus; 721 722 #ifdef DIAGNOSTIC 723 if (xfer->busy_free != XFER_BUSY) { 724 printf("uhci_freex: xfer=%p not busy, 0x%08x\n", xfer, 725 xfer->busy_free); 726 } 727 xfer->busy_free = XFER_FREE; 728 if (!UXFER(xfer)->iinfo.isdone) { 729 printf("uhci_freex: !isdone\n"); 730 } 731 #endif 732 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 733 } 734 735 /* 736 * Shut down the controller when the system is going down. 737 */ 738 void 739 uhci_shutdown(void *v) 740 { 741 uhci_softc_t *sc = v; 742 int s; 743 744 DPRINTF(("uhci_shutdown: stopping the HC\n")); 745 746 /* 747 * Use polling mode to prevent the interrupts shutting 748 * us down before we shut them down. 749 */ 750 s = splhardusb(); 751 sc->sc_bus.use_polling++; 752 uhci_run(sc, 0); /* stop the controller */ 753 sc->sc_bus.use_polling--; 754 splx(s); 755 } 756 757 /* 758 * Handle suspend/resume. 759 * 760 * We need to switch to polling mode here, because this routine is 761 * called from an interrupt context. This is all right since we 762 * are almost suspended anyway. 763 */ 764 void 765 uhci_power(int why, void *v) 766 { 767 uhci_softc_t *sc = v; 768 int cmd; 769 int s; 770 771 s = splhardusb(); 772 cmd = UREAD2(sc, UHCI_CMD); 773 774 DPRINTF(("uhci_power: sc=%p, why=%d (was %d), cmd=0x%x\n", 775 sc, why, sc->sc_suspend, cmd)); 776 777 switch (why) { 778 case PWR_SUSPEND: 779 case PWR_STANDBY: 780 #ifdef UHCI_DEBUG 781 if (uhcidebug > 2) 782 uhci_dumpregs(sc); 783 #endif 784 if (sc->sc_intr_xfer != NULL) 785 usb_uncallout(sc->sc_poll_handle, uhci_poll_hub, 786 sc->sc_intr_xfer); 787 sc->sc_bus.use_polling++; 788 uhci_run(sc, 0); /* stop the controller */ 789 790 /* save some state if BIOS doesn't */ 791 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 792 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 793 794 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 795 796 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter global suspend */ 797 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 798 sc->sc_suspend = why; 799 sc->sc_bus.use_polling--; 800 DPRINTF(("uhci_power: cmd=0x%x\n", UREAD2(sc, UHCI_CMD))); 801 break; 802 case PWR_RESUME: 803 #ifdef DIAGNOSTIC 804 if (sc->sc_suspend == PWR_RESUME) 805 printf("uhci_power: weird, resume without suspend.\n"); 806 #endif 807 sc->sc_bus.use_polling++; 808 sc->sc_suspend = why; 809 if (cmd & UHCI_CMD_RS) 810 uhci_run(sc, 0); /* in case BIOS has started it */ 811 812 /* restore saved state */ 813 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 814 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 815 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 816 817 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force global resume */ 818 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 819 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 820 UHCICMD(sc, UHCI_CMD_MAXP); 821 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 822 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* re-enable intrs */ 823 uhci_run(sc, 1); /* and start traffic again */ 824 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 825 sc->sc_bus.use_polling--; 826 if (sc->sc_intr_xfer != NULL) 827 usb_callout(sc->sc_poll_handle, sc->sc_ival, 828 uhci_poll_hub, sc->sc_intr_xfer); 829 #ifdef UHCI_DEBUG 830 if (uhcidebug > 2) 831 uhci_dumpregs(sc); 832 #endif 833 break; 834 case PWR_SOFTSUSPEND: 835 case PWR_SOFTSTANDBY: 836 case PWR_SOFTRESUME: 837 break; 838 } 839 splx(s); 840 } 841 842 #ifdef UHCI_DEBUG 843 Static void 844 uhci_dumpregs(uhci_softc_t *sc) 845 { 846 DPRINTFN(-1,("%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, " 847 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 848 USBDEVNAME(sc->sc_bus.bdev), 849 UREAD2(sc, UHCI_CMD), 850 UREAD2(sc, UHCI_STS), 851 UREAD2(sc, UHCI_INTR), 852 UREAD2(sc, UHCI_FRNUM), 853 UREAD4(sc, UHCI_FLBASEADDR), 854 UREAD1(sc, UHCI_SOF), 855 UREAD2(sc, UHCI_PORTSC1), 856 UREAD2(sc, UHCI_PORTSC2))); 857 } 858 859 void 860 uhci_dump_td(uhci_soft_td_t *p) 861 { 862 char sbuf[128], sbuf2[128]; 863 864 865 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 866 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 867 DPRINTFN(-1,("TD(%p) at %08lx = link=0x%08lx status=0x%08lx " 868 "token=0x%08lx buffer=0x%08lx\n", 869 p, (long)p->physaddr, 870 (long)le32toh(p->td.td_link), 871 (long)le32toh(p->td.td_status), 872 (long)le32toh(p->td.td_token), 873 (long)le32toh(p->td.td_buffer))); 874 875 bitmask_snprintf((u_int32_t)le32toh(p->td.td_link), "\20\1T\2Q\3VF", 876 sbuf, sizeof(sbuf)); 877 bitmask_snprintf((u_int32_t)le32toh(p->td.td_status), 878 "\20\22BITSTUFF\23CRCTO\24NAK\25BABBLE\26DBUFFER\27" 879 "STALLED\30ACTIVE\31IOC\32ISO\33LS\36SPD", 880 sbuf2, sizeof(sbuf2)); 881 882 DPRINTFN(-1,(" %s %s,errcnt=%d,actlen=%d pid=%02x,addr=%d,endpt=%d," 883 "D=%d,maxlen=%d\n", sbuf, sbuf2, 884 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 885 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 886 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 887 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 888 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 889 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 890 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token)))); 891 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 892 BUS_DMASYNC_PREREAD); 893 } 894 895 void 896 uhci_dump_qh(uhci_soft_qh_t *sqh) 897 { 898 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 899 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 900 DPRINTFN(-1,("QH(%p) at %08x: hlink=%08x elink=%08x\n", sqh, 901 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 902 le32toh(sqh->qh.qh_elink))); 903 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 904 } 905 906 907 #if 1 908 void 909 uhci_dump(void) 910 { 911 uhci_dump_all(thesc); 912 } 913 #endif 914 915 void 916 uhci_dump_all(uhci_softc_t *sc) 917 { 918 uhci_dumpregs(sc); 919 printf("intrs=%d\n", sc->sc_bus.no_intrs); 920 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 921 uhci_dump_qh(sc->sc_lctl_start); 922 } 923 924 925 void 926 uhci_dump_qhs(uhci_soft_qh_t *sqh) 927 { 928 uhci_dump_qh(sqh); 929 930 /* uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 931 * Traverses sideways first, then down. 932 * 933 * QH1 934 * QH2 935 * No QH 936 * TD2.1 937 * TD2.2 938 * TD1.1 939 * etc. 940 * 941 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 942 */ 943 944 945 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 946 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 947 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 948 uhci_dump_qhs(sqh->hlink); 949 else 950 DPRINTF(("No QH\n")); 951 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 952 953 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 954 uhci_dump_tds(sqh->elink); 955 else 956 DPRINTF(("No TD\n")); 957 } 958 959 void 960 uhci_dump_tds(uhci_soft_td_t *std) 961 { 962 uhci_soft_td_t *td; 963 int stop; 964 965 for(td = std; td != NULL; td = td->link.std) { 966 uhci_dump_td(td); 967 968 /* Check whether the link pointer in this TD marks 969 * the link pointer as end of queue. This avoids 970 * printing the free list in case the queue/TD has 971 * already been moved there (seatbelt). 972 */ 973 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 974 sizeof(td->td.td_link), 975 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 976 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 977 le32toh(td->td.td_link) == 0); 978 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 979 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 980 if (stop) 981 break; 982 } 983 } 984 985 Static void 986 uhci_dump_ii(uhci_intr_info_t *ii) 987 { 988 usbd_pipe_handle pipe; 989 usb_endpoint_descriptor_t *ed; 990 usbd_device_handle dev; 991 992 #ifdef DIAGNOSTIC 993 #define DONE ii->isdone 994 #else 995 #define DONE 0 996 #endif 997 if (ii == NULL) { 998 printf("ii NULL\n"); 999 return; 1000 } 1001 if (ii->xfer == NULL) { 1002 printf("ii %p: done=%d xfer=NULL\n", 1003 ii, DONE); 1004 return; 1005 } 1006 pipe = ii->xfer->pipe; 1007 if (pipe == NULL) { 1008 printf("ii %p: done=%d xfer=%p pipe=NULL\n", 1009 ii, DONE, ii->xfer); 1010 return; 1011 } 1012 if (pipe->endpoint == NULL) { 1013 printf("ii %p: done=%d xfer=%p pipe=%p pipe->endpoint=NULL\n", 1014 ii, DONE, ii->xfer, pipe); 1015 return; 1016 } 1017 if (pipe->device == NULL) { 1018 printf("ii %p: done=%d xfer=%p pipe=%p pipe->device=NULL\n", 1019 ii, DONE, ii->xfer, pipe); 1020 return; 1021 } 1022 ed = pipe->endpoint->edesc; 1023 dev = pipe->device; 1024 printf("ii %p: done=%d xfer=%p dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 1025 ii, DONE, ii->xfer, dev, 1026 UGETW(dev->ddesc.idVendor), 1027 UGETW(dev->ddesc.idProduct), 1028 dev->address, pipe, 1029 ed->bEndpointAddress, ed->bmAttributes); 1030 #undef DONE 1031 } 1032 1033 void uhci_dump_iis(struct uhci_softc *sc); 1034 void 1035 uhci_dump_iis(struct uhci_softc *sc) 1036 { 1037 uhci_intr_info_t *ii; 1038 1039 printf("intr_info list:\n"); 1040 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = LIST_NEXT(ii, list)) 1041 uhci_dump_ii(ii); 1042 } 1043 1044 void iidump(void); 1045 void iidump(void) { uhci_dump_iis(thesc); } 1046 1047 #endif 1048 1049 /* 1050 * This routine is executed periodically and simulates interrupts 1051 * from the root controller interrupt pipe for port status change. 1052 */ 1053 void 1054 uhci_poll_hub(void *addr) 1055 { 1056 usbd_xfer_handle xfer = addr; 1057 usbd_pipe_handle pipe = xfer->pipe; 1058 uhci_softc_t *sc = (uhci_softc_t *)pipe->device->bus; 1059 int s; 1060 u_char *p; 1061 1062 DPRINTFN(20, ("uhci_poll_hub\n")); 1063 1064 usb_callout(sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 1065 1066 p = KERNADDR(&xfer->dmabuf, 0); 1067 p[0] = 0; 1068 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1069 p[0] |= 1<<1; 1070 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1071 p[0] |= 1<<2; 1072 if (p[0] == 0) 1073 /* No change, try again in a while */ 1074 return; 1075 1076 xfer->actlen = 1; 1077 xfer->status = USBD_NORMAL_COMPLETION; 1078 s = splusb(); 1079 xfer->device->bus->intr_context++; 1080 usb_transfer_complete(xfer); 1081 xfer->device->bus->intr_context--; 1082 splx(s); 1083 } 1084 1085 void 1086 uhci_root_intr_done(usbd_xfer_handle xfer) 1087 { 1088 } 1089 1090 void 1091 uhci_root_ctrl_done(usbd_xfer_handle xfer) 1092 { 1093 } 1094 1095 /* 1096 * Let the last QH loop back to the high speed control transfer QH. 1097 * This is what intel calls "bandwidth reclamation" and improves 1098 * USB performance a lot for some devices. 1099 * If we are already looping, just count it. 1100 */ 1101 void 1102 uhci_add_loop(uhci_softc_t *sc) { 1103 #ifdef UHCI_DEBUG 1104 if (uhcinoloop) 1105 return; 1106 #endif 1107 if (++sc->sc_loops == 1) { 1108 DPRINTFN(5,("uhci_start_loop: add\n")); 1109 /* Note, we don't loop back the soft pointer. */ 1110 sc->sc_last_qh->qh.qh_hlink = 1111 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 1112 usb_syncmem(&sc->sc_last_qh->dma, 1113 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1114 sizeof(sc->sc_last_qh->qh.qh_hlink), 1115 BUS_DMASYNC_PREWRITE); 1116 } 1117 } 1118 1119 void 1120 uhci_rem_loop(uhci_softc_t *sc) { 1121 #ifdef UHCI_DEBUG 1122 if (uhcinoloop) 1123 return; 1124 #endif 1125 if (--sc->sc_loops == 0) { 1126 DPRINTFN(5,("uhci_end_loop: remove\n")); 1127 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 1128 usb_syncmem(&sc->sc_last_qh->dma, 1129 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1130 sizeof(sc->sc_last_qh->qh.qh_hlink), 1131 BUS_DMASYNC_PREWRITE); 1132 } 1133 } 1134 1135 /* Add high speed control QH, called at splusb(). */ 1136 void 1137 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1138 { 1139 uhci_soft_qh_t *eqh; 1140 1141 SPLUSBCHECK; 1142 1143 DPRINTFN(10, ("uhci_add_ctrl: sqh=%p\n", sqh)); 1144 eqh = sc->sc_hctl_end; 1145 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1146 sizeof(eqh->qh.qh_hlink), 1147 BUS_DMASYNC_POSTWRITE); 1148 sqh->hlink = eqh->hlink; 1149 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1150 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1151 BUS_DMASYNC_PREWRITE); 1152 eqh->hlink = sqh; 1153 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1154 sc->sc_hctl_end = sqh; 1155 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1156 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1157 #ifdef UHCI_CTL_LOOP 1158 uhci_add_loop(sc); 1159 #endif 1160 } 1161 1162 /* Remove high speed control QH, called at splusb(). */ 1163 void 1164 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1165 { 1166 uhci_soft_qh_t *pqh; 1167 1168 SPLUSBCHECK; 1169 1170 DPRINTFN(10, ("uhci_remove_hs_ctrl: sqh=%p\n", sqh)); 1171 #ifdef UHCI_CTL_LOOP 1172 uhci_rem_loop(sc); 1173 #endif 1174 /* 1175 * The T bit should be set in the elink of the QH so that the HC 1176 * doesn't follow the pointer. This condition may fail if the 1177 * the transferred packet was short so that the QH still points 1178 * at the last used TD. 1179 * In this case we set the T bit and wait a little for the HC 1180 * to stop looking at the TD. 1181 * Note that if the TD chain is large enough, the controller 1182 * may still be looking at the chain at the end of this function. 1183 * uhci_free_std_chain() will make sure the controller stops 1184 * looking at it quickly, but until then we should not change 1185 * sqh->hlink. 1186 */ 1187 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1188 sizeof(sqh->qh.qh_elink), 1189 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1190 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1191 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1192 usb_syncmem(&sqh->dma, 1193 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1194 sizeof(sqh->qh.qh_elink), 1195 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1196 delay(UHCI_QH_REMOVE_DELAY); 1197 } 1198 1199 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1200 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1201 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1202 pqh->hlink = sqh->hlink; 1203 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1204 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1205 sizeof(pqh->qh.qh_hlink), 1206 BUS_DMASYNC_PREWRITE); 1207 delay(UHCI_QH_REMOVE_DELAY); 1208 if (sc->sc_hctl_end == sqh) 1209 sc->sc_hctl_end = pqh; 1210 } 1211 1212 /* Add low speed control QH, called at splusb(). */ 1213 void 1214 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1215 { 1216 uhci_soft_qh_t *eqh; 1217 1218 SPLUSBCHECK; 1219 1220 DPRINTFN(10, ("uhci_add_ls_ctrl: sqh=%p\n", sqh)); 1221 eqh = sc->sc_lctl_end; 1222 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1223 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1224 sqh->hlink = eqh->hlink; 1225 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1226 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1227 BUS_DMASYNC_PREWRITE); 1228 eqh->hlink = sqh; 1229 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1230 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1231 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1232 sc->sc_lctl_end = sqh; 1233 } 1234 1235 /* Remove low speed control QH, called at splusb(). */ 1236 void 1237 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1238 { 1239 uhci_soft_qh_t *pqh; 1240 1241 SPLUSBCHECK; 1242 1243 DPRINTFN(10, ("uhci_remove_ls_ctrl: sqh=%p\n", sqh)); 1244 /* See comment in uhci_remove_hs_ctrl() */ 1245 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1246 sizeof(sqh->qh.qh_elink), 1247 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1248 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1249 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1250 usb_syncmem(&sqh->dma, 1251 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1252 sizeof(sqh->qh.qh_elink), 1253 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1254 delay(UHCI_QH_REMOVE_DELAY); 1255 } 1256 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1257 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1258 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1259 pqh->hlink = sqh->hlink; 1260 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1261 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1262 sizeof(pqh->qh.qh_hlink), 1263 BUS_DMASYNC_PREWRITE); 1264 delay(UHCI_QH_REMOVE_DELAY); 1265 if (sc->sc_lctl_end == sqh) 1266 sc->sc_lctl_end = pqh; 1267 } 1268 1269 /* Add bulk QH, called at splusb(). */ 1270 void 1271 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1272 { 1273 uhci_soft_qh_t *eqh; 1274 1275 SPLUSBCHECK; 1276 1277 DPRINTFN(10, ("uhci_add_bulk: sqh=%p\n", sqh)); 1278 eqh = sc->sc_bulk_end; 1279 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1280 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1281 sqh->hlink = eqh->hlink; 1282 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1283 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1284 BUS_DMASYNC_PREWRITE); 1285 eqh->hlink = sqh; 1286 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1287 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1288 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1289 sc->sc_bulk_end = sqh; 1290 uhci_add_loop(sc); 1291 } 1292 1293 /* Remove bulk QH, called at splusb(). */ 1294 void 1295 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1296 { 1297 uhci_soft_qh_t *pqh; 1298 1299 SPLUSBCHECK; 1300 1301 DPRINTFN(10, ("uhci_remove_bulk: sqh=%p\n", sqh)); 1302 uhci_rem_loop(sc); 1303 /* See comment in uhci_remove_hs_ctrl() */ 1304 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1305 sizeof(sqh->qh.qh_elink), 1306 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1307 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1308 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1309 usb_syncmem(&sqh->dma, 1310 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1311 sizeof(sqh->qh.qh_elink), 1312 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1313 delay(UHCI_QH_REMOVE_DELAY); 1314 } 1315 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1316 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1317 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1318 pqh->hlink = sqh->hlink; 1319 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1320 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1321 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1322 delay(UHCI_QH_REMOVE_DELAY); 1323 if (sc->sc_bulk_end == sqh) 1324 sc->sc_bulk_end = pqh; 1325 } 1326 1327 Static int uhci_intr1(uhci_softc_t *); 1328 1329 int 1330 uhci_intr(void *arg) 1331 { 1332 uhci_softc_t *sc = arg; 1333 1334 if (sc->sc_dying) 1335 return (0); 1336 1337 if (sc->sc_bus.use_polling) { 1338 #ifdef DIAGNOSTIC 1339 DPRINTFN(16, ("uhci_intr: ignored interrupt while polling\n")); 1340 #endif 1341 return (0); 1342 } 1343 1344 return (uhci_intr1(sc)); 1345 } 1346 1347 int 1348 uhci_intr1(uhci_softc_t *sc) 1349 { 1350 int status; 1351 int ack; 1352 1353 #ifdef UHCI_DEBUG 1354 if (uhcidebug > 15) { 1355 DPRINTF(("%s: uhci_intr1\n", USBDEVNAME(sc->sc_bus.bdev))); 1356 uhci_dumpregs(sc); 1357 } 1358 #endif 1359 1360 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1361 if (status == 0) /* The interrupt was not for us. */ 1362 return (0); 1363 1364 if (sc->sc_suspend != PWR_RESUME) { 1365 #ifdef DIAGNOSTIC 1366 printf("%s: interrupt while not operating ignored\n", 1367 USBDEVNAME(sc->sc_bus.bdev)); 1368 #endif 1369 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1370 return (0); 1371 } 1372 1373 ack = 0; 1374 if (status & UHCI_STS_USBINT) 1375 ack |= UHCI_STS_USBINT; 1376 if (status & UHCI_STS_USBEI) 1377 ack |= UHCI_STS_USBEI; 1378 if (status & UHCI_STS_RD) { 1379 ack |= UHCI_STS_RD; 1380 #ifdef UHCI_DEBUG 1381 printf("%s: resume detect\n", USBDEVNAME(sc->sc_bus.bdev)); 1382 #endif 1383 } 1384 if (status & UHCI_STS_HSE) { 1385 ack |= UHCI_STS_HSE; 1386 printf("%s: host system error\n", USBDEVNAME(sc->sc_bus.bdev)); 1387 } 1388 if (status & UHCI_STS_HCPE) { 1389 ack |= UHCI_STS_HCPE; 1390 printf("%s: host controller process error\n", 1391 USBDEVNAME(sc->sc_bus.bdev)); 1392 } 1393 if (status & UHCI_STS_HCH) { 1394 /* no acknowledge needed */ 1395 if (!sc->sc_dying) { 1396 printf("%s: host controller halted\n", 1397 USBDEVNAME(sc->sc_bus.bdev)); 1398 #ifdef UHCI_DEBUG 1399 uhci_dump_all(sc); 1400 #endif 1401 } 1402 sc->sc_dying = 1; 1403 } 1404 1405 if (!ack) 1406 return (0); /* nothing to acknowledge */ 1407 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1408 1409 sc->sc_bus.no_intrs++; 1410 usb_schedsoftintr(&sc->sc_bus); 1411 1412 DPRINTFN(15, ("%s: uhci_intr: exit\n", USBDEVNAME(sc->sc_bus.bdev))); 1413 1414 return (1); 1415 } 1416 1417 void 1418 uhci_softintr(void *v) 1419 { 1420 uhci_softc_t *sc = v; 1421 uhci_intr_info_t *ii, *nextii; 1422 1423 DPRINTFN(10,("%s: uhci_softintr (%d)\n", USBDEVNAME(sc->sc_bus.bdev), 1424 sc->sc_bus.intr_context)); 1425 1426 sc->sc_bus.intr_context++; 1427 1428 /* 1429 * Interrupts on UHCI really suck. When the host controller 1430 * interrupts because a transfer is completed there is no 1431 * way of knowing which transfer it was. You can scan down 1432 * the TDs and QHs of the previous frame to limit the search, 1433 * but that assumes that the interrupt was not delayed by more 1434 * than 1 ms, which may not always be true (e.g. after debug 1435 * output on a slow console). 1436 * We scan all interrupt descriptors to see if any have 1437 * completed. 1438 */ 1439 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = nextii) { 1440 nextii = LIST_NEXT(ii, list); 1441 uhci_check_intr(sc, ii); 1442 } 1443 1444 #ifdef USB_USE_SOFTINTR 1445 if (sc->sc_softwake) { 1446 sc->sc_softwake = 0; 1447 wakeup(&sc->sc_softwake); 1448 } 1449 #endif /* USB_USE_SOFTINTR */ 1450 1451 sc->sc_bus.intr_context--; 1452 } 1453 1454 /* Check for an interrupt. */ 1455 void 1456 uhci_check_intr(uhci_softc_t *sc, uhci_intr_info_t *ii) 1457 { 1458 uhci_soft_td_t *std, *lstd; 1459 u_int32_t status; 1460 1461 DPRINTFN(15, ("uhci_check_intr: ii=%p\n", ii)); 1462 #ifdef DIAGNOSTIC 1463 if (ii == NULL) { 1464 printf("uhci_check_intr: no ii? %p\n", ii); 1465 return; 1466 } 1467 #endif 1468 if (ii->xfer->status == USBD_CANCELLED || 1469 ii->xfer->status == USBD_TIMEOUT) { 1470 DPRINTF(("uhci_check_intr: aborted xfer=%p\n", ii->xfer)); 1471 return; 1472 } 1473 1474 if (ii->stdstart == NULL) 1475 return; 1476 lstd = ii->stdend; 1477 #ifdef DIAGNOSTIC 1478 if (lstd == NULL) { 1479 printf("uhci_check_intr: std==0\n"); 1480 return; 1481 } 1482 #endif 1483 /* 1484 * If the last TD is still active we need to check whether there 1485 * is an error somewhere in the middle, or whether there was a 1486 * short packet (SPD and not ACTIVE). 1487 */ 1488 usb_syncmem(&lstd->dma, 1489 lstd->offs + offsetof(uhci_td_t, td_status), 1490 sizeof(lstd->td.td_status), 1491 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1492 if (le32toh(lstd->td.td_status) & UHCI_TD_ACTIVE) { 1493 DPRINTFN(12, ("uhci_check_intr: active ii=%p\n", ii)); 1494 for (std = ii->stdstart; std != lstd; std = std->link.std) { 1495 usb_syncmem(&std->dma, 1496 std->offs + offsetof(uhci_td_t, td_status), 1497 sizeof(std->td.td_status), 1498 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1499 status = le32toh(std->td.td_status); 1500 usb_syncmem(&std->dma, 1501 std->offs + offsetof(uhci_td_t, td_status), 1502 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1503 /* If there's an active TD the xfer isn't done. */ 1504 if (status & UHCI_TD_ACTIVE) 1505 break; 1506 /* Any kind of error makes the xfer done. */ 1507 if (status & UHCI_TD_STALLED) 1508 goto done; 1509 /* We want short packets, and it is short: it's done */ 1510 usb_syncmem(&std->dma, 1511 std->offs + offsetof(uhci_td_t, td_token), 1512 sizeof(std->td.td_token), 1513 BUS_DMASYNC_POSTWRITE); 1514 if ((status & UHCI_TD_SPD) && 1515 UHCI_TD_GET_ACTLEN(status) < 1516 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) 1517 goto done; 1518 } 1519 DPRINTFN(12, ("uhci_check_intr: ii=%p std=%p still active\n", 1520 ii, ii->stdstart)); 1521 usb_syncmem(&lstd->dma, 1522 lstd->offs + offsetof(uhci_td_t, td_status), 1523 sizeof(lstd->td.td_status), 1524 BUS_DMASYNC_PREREAD); 1525 return; 1526 } 1527 done: 1528 DPRINTFN(12, ("uhci_check_intr: ii=%p done\n", ii)); 1529 usb_uncallout(ii->xfer->timeout_handle, uhci_timeout, ii); 1530 uhci_idone(ii); 1531 } 1532 1533 /* Called at splusb() */ 1534 void 1535 uhci_idone(uhci_intr_info_t *ii) 1536 { 1537 usbd_xfer_handle xfer = ii->xfer; 1538 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 1539 uhci_soft_td_t *std; 1540 u_int32_t status = 0, nstatus; 1541 int actlen; 1542 1543 DPRINTFN(12, ("uhci_idone: ii=%p\n", ii)); 1544 #ifdef DIAGNOSTIC 1545 { 1546 int s = splhigh(); 1547 if (ii->isdone) { 1548 splx(s); 1549 #ifdef UHCI_DEBUG 1550 printf("uhci_idone: ii is done!\n "); 1551 uhci_dump_ii(ii); 1552 #else 1553 printf("uhci_idone: ii=%p is done!\n", ii); 1554 #endif 1555 return; 1556 } 1557 ii->isdone = 1; 1558 splx(s); 1559 } 1560 #endif 1561 1562 if (xfer->nframes != 0) { 1563 /* Isoc transfer, do things differently. */ 1564 uhci_soft_td_t **stds = upipe->u.iso.stds; 1565 int i, n, nframes, len; 1566 1567 DPRINTFN(5,("uhci_idone: ii=%p isoc ready\n", ii)); 1568 1569 nframes = xfer->nframes; 1570 actlen = 0; 1571 n = UXFER(xfer)->curframe; 1572 for (i = 0; i < nframes; i++) { 1573 std = stds[n]; 1574 #ifdef UHCI_DEBUG 1575 if (uhcidebug > 5) { 1576 DPRINTFN(-1,("uhci_idone: isoc TD %d\n", i)); 1577 uhci_dump_td(std); 1578 } 1579 #endif 1580 if (++n >= UHCI_VFRAMELIST_COUNT) 1581 n = 0; 1582 usb_syncmem(&std->dma, 1583 std->offs + offsetof(uhci_td_t, td_status), 1584 sizeof(std->td.td_status), 1585 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1586 status = le32toh(std->td.td_status); 1587 len = UHCI_TD_GET_ACTLEN(status); 1588 xfer->frlengths[i] = len; 1589 actlen += len; 1590 } 1591 upipe->u.iso.inuse -= nframes; 1592 xfer->actlen = actlen; 1593 xfer->status = USBD_NORMAL_COMPLETION; 1594 goto end; 1595 } 1596 1597 #ifdef UHCI_DEBUG 1598 DPRINTFN(10, ("uhci_idone: ii=%p, xfer=%p, pipe=%p ready\n", 1599 ii, xfer, upipe)); 1600 if (uhcidebug > 10) 1601 uhci_dump_tds(ii->stdstart); 1602 #endif 1603 1604 /* The transfer is done, compute actual length and status. */ 1605 actlen = 0; 1606 for (std = ii->stdstart; std != NULL; std = std->link.std) { 1607 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1608 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1609 nstatus = le32toh(std->td.td_status); 1610 if (nstatus & UHCI_TD_ACTIVE) 1611 break; 1612 1613 status = nstatus; 1614 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1615 UHCI_TD_PID_SETUP) 1616 actlen += UHCI_TD_GET_ACTLEN(status); 1617 else { 1618 /* 1619 * UHCI will report CRCTO in addition to a STALL or NAK 1620 * for a SETUP transaction. See section 3.2.2, "TD 1621 * CONTROL AND STATUS". 1622 */ 1623 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1624 status &= ~UHCI_TD_CRCTO; 1625 } 1626 } 1627 /* If there are left over TDs we need to update the toggle. */ 1628 if (std != NULL) 1629 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1630 1631 status &= UHCI_TD_ERROR; 1632 DPRINTFN(10, ("uhci_idone: actlen=%d, status=0x%x\n", 1633 actlen, status)); 1634 xfer->actlen = actlen; 1635 if (status != 0) { 1636 #ifdef UHCI_DEBUG 1637 char sbuf[128]; 1638 1639 bitmask_snprintf((u_int32_t)status, 1640 "\20\22BITSTUFF\23CRCTO\24NAK\25" 1641 "BABBLE\26DBUFFER\27STALLED\30ACTIVE", 1642 sbuf, sizeof(sbuf)); 1643 1644 DPRINTFN((status == UHCI_TD_STALLED)*10, 1645 ("uhci_idone: error, addr=%d, endpt=0x%02x, " 1646 "status 0x%s\n", 1647 xfer->pipe->device->address, 1648 xfer->pipe->endpoint->edesc->bEndpointAddress, 1649 sbuf)); 1650 #endif 1651 1652 if (status == UHCI_TD_STALLED) 1653 xfer->status = USBD_STALLED; 1654 else 1655 xfer->status = USBD_IOERROR; /* more info XXX */ 1656 } else { 1657 xfer->status = USBD_NORMAL_COMPLETION; 1658 } 1659 1660 end: 1661 usb_transfer_complete(xfer); 1662 DPRINTFN(12, ("uhci_idone: ii=%p done\n", ii)); 1663 } 1664 1665 /* 1666 * Called when a request does not complete. 1667 */ 1668 void 1669 uhci_timeout(void *addr) 1670 { 1671 uhci_intr_info_t *ii = addr; 1672 struct uhci_xfer *uxfer = UXFER(ii->xfer); 1673 struct uhci_pipe *upipe = (struct uhci_pipe *)uxfer->xfer.pipe; 1674 uhci_softc_t *sc = (uhci_softc_t *)upipe->pipe.device->bus; 1675 1676 DPRINTF(("uhci_timeout: uxfer=%p\n", uxfer)); 1677 1678 if (sc->sc_dying) { 1679 uhci_abort_xfer(&uxfer->xfer, USBD_TIMEOUT); 1680 return; 1681 } 1682 1683 /* Execute the abort in a process context. */ 1684 usb_init_task(&uxfer->abort_task, uhci_timeout_task, ii->xfer); 1685 usb_add_task(uxfer->xfer.pipe->device, &uxfer->abort_task, 1686 USB_TASKQ_HC); 1687 } 1688 1689 void 1690 uhci_timeout_task(void *addr) 1691 { 1692 usbd_xfer_handle xfer = addr; 1693 int s; 1694 1695 DPRINTF(("uhci_timeout_task: xfer=%p\n", xfer)); 1696 1697 s = splusb(); 1698 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1699 splx(s); 1700 } 1701 1702 /* 1703 * Wait here until controller claims to have an interrupt. 1704 * Then call uhci_intr and return. Use timeout to avoid waiting 1705 * too long. 1706 * Only used during boot when interrupts are not enabled yet. 1707 */ 1708 void 1709 uhci_waitintr(uhci_softc_t *sc, usbd_xfer_handle xfer) 1710 { 1711 int timo = xfer->timeout; 1712 uhci_intr_info_t *ii; 1713 1714 DPRINTFN(10,("uhci_waitintr: timeout = %dms\n", timo)); 1715 1716 xfer->status = USBD_IN_PROGRESS; 1717 for (; timo >= 0; timo--) { 1718 usb_delay_ms(&sc->sc_bus, 1); 1719 DPRINTFN(20,("uhci_waitintr: 0x%04x\n", UREAD2(sc, UHCI_STS))); 1720 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1721 uhci_intr1(sc); 1722 if (xfer->status != USBD_IN_PROGRESS) 1723 return; 1724 } 1725 } 1726 1727 /* Timeout */ 1728 DPRINTF(("uhci_waitintr: timeout\n")); 1729 for (ii = LIST_FIRST(&sc->sc_intrhead); 1730 ii != NULL && ii->xfer != xfer; 1731 ii = LIST_NEXT(ii, list)) 1732 ; 1733 #ifdef DIAGNOSTIC 1734 if (ii == NULL) 1735 panic("uhci_waitintr: lost intr_info"); 1736 #endif 1737 uhci_idone(ii); 1738 } 1739 1740 void 1741 uhci_poll(struct usbd_bus *bus) 1742 { 1743 uhci_softc_t *sc = (uhci_softc_t *)bus; 1744 1745 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) 1746 uhci_intr1(sc); 1747 } 1748 1749 void 1750 uhci_reset(uhci_softc_t *sc) 1751 { 1752 int n; 1753 1754 UHCICMD(sc, UHCI_CMD_HCRESET); 1755 /* The reset bit goes low when the controller is done. */ 1756 for (n = 0; n < UHCI_RESET_TIMEOUT && 1757 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1758 usb_delay_ms(&sc->sc_bus, 1); 1759 if (n >= UHCI_RESET_TIMEOUT) 1760 printf("%s: controller did not reset\n", 1761 USBDEVNAME(sc->sc_bus.bdev)); 1762 } 1763 1764 usbd_status 1765 uhci_run(uhci_softc_t *sc, int run) 1766 { 1767 int s, n, running; 1768 u_int16_t cmd; 1769 1770 run = run != 0; 1771 s = splhardusb(); 1772 DPRINTF(("uhci_run: setting run=%d\n", run)); 1773 cmd = UREAD2(sc, UHCI_CMD); 1774 if (run) 1775 cmd |= UHCI_CMD_RS; 1776 else 1777 cmd &= ~UHCI_CMD_RS; 1778 UHCICMD(sc, cmd); 1779 for(n = 0; n < 10; n++) { 1780 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1781 /* return when we've entered the state we want */ 1782 if (run == running) { 1783 splx(s); 1784 DPRINTF(("uhci_run: done cmd=0x%x sts=0x%x\n", 1785 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS))); 1786 return (USBD_NORMAL_COMPLETION); 1787 } 1788 usb_delay_ms(&sc->sc_bus, 1); 1789 } 1790 splx(s); 1791 printf("%s: cannot %s\n", USBDEVNAME(sc->sc_bus.bdev), 1792 run ? "start" : "stop"); 1793 return (USBD_IOERROR); 1794 } 1795 1796 /* 1797 * Memory management routines. 1798 * uhci_alloc_std allocates TDs 1799 * uhci_alloc_sqh allocates QHs 1800 * These two routines do their own free list management, 1801 * partly for speed, partly because allocating DMAable memory 1802 * has page size granularaity so much memory would be wasted if 1803 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1804 */ 1805 1806 uhci_soft_td_t * 1807 uhci_alloc_std(uhci_softc_t *sc) 1808 { 1809 uhci_soft_td_t *std; 1810 usbd_status err; 1811 int i, offs; 1812 usb_dma_t dma; 1813 1814 if (sc->sc_freetds == NULL) { 1815 DPRINTFN(2,("uhci_alloc_std: allocating chunk\n")); 1816 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1817 UHCI_TD_ALIGN, &dma); 1818 if (err) 1819 return (0); 1820 for(i = 0; i < UHCI_STD_CHUNK; i++) { 1821 offs = i * UHCI_STD_SIZE; 1822 std = KERNADDR(&dma, offs); 1823 std->physaddr = DMAADDR(&dma, offs); 1824 std->dma = dma; 1825 std->offs = offs; 1826 std->link.std = sc->sc_freetds; 1827 sc->sc_freetds = std; 1828 } 1829 } 1830 std = sc->sc_freetds; 1831 sc->sc_freetds = std->link.std; 1832 memset(&std->td, 0, sizeof(uhci_td_t)); 1833 return std; 1834 } 1835 1836 void 1837 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1838 { 1839 #ifdef DIAGNOSTIC 1840 #define TD_IS_FREE 0x12345678 1841 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1842 printf("uhci_free_std: freeing free TD %p\n", std); 1843 return; 1844 } 1845 std->td.td_token = htole32(TD_IS_FREE); 1846 #endif 1847 std->link.std = sc->sc_freetds; 1848 sc->sc_freetds = std; 1849 } 1850 1851 uhci_soft_qh_t * 1852 uhci_alloc_sqh(uhci_softc_t *sc) 1853 { 1854 uhci_soft_qh_t *sqh; 1855 usbd_status err; 1856 int i, offs; 1857 usb_dma_t dma; 1858 1859 if (sc->sc_freeqhs == NULL) { 1860 DPRINTFN(2, ("uhci_alloc_sqh: allocating chunk\n")); 1861 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1862 UHCI_QH_ALIGN, &dma); 1863 if (err) 1864 return (0); 1865 for(i = 0; i < UHCI_SQH_CHUNK; i++) { 1866 offs = i * UHCI_SQH_SIZE; 1867 sqh = KERNADDR(&dma, offs); 1868 sqh->physaddr = DMAADDR(&dma, offs); 1869 sqh->dma = dma; 1870 sqh->offs = offs; 1871 sqh->hlink = sc->sc_freeqhs; 1872 sc->sc_freeqhs = sqh; 1873 } 1874 } 1875 sqh = sc->sc_freeqhs; 1876 sc->sc_freeqhs = sqh->hlink; 1877 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1878 return (sqh); 1879 } 1880 1881 void 1882 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1883 { 1884 sqh->hlink = sc->sc_freeqhs; 1885 sc->sc_freeqhs = sqh; 1886 } 1887 1888 void 1889 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1890 uhci_soft_td_t *stdend) 1891 { 1892 uhci_soft_td_t *p; 1893 1894 /* 1895 * to avoid race condition with the controller which may be looking 1896 * at this chain, we need to first invalidate all links, and 1897 * then wait for the controller to move to another queue 1898 */ 1899 for (p = std; p != stdend; p = p->link.std) { 1900 usb_syncmem(&p->dma, 1901 p->offs + offsetof(uhci_td_t, td_link), 1902 sizeof(p->td.td_link), 1903 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1904 if ((p->td.td_link & UHCI_PTR_T) == 0) { 1905 p->td.td_link = UHCI_PTR_T; 1906 usb_syncmem(&p->dma, 1907 p->offs + offsetof(uhci_td_t, td_link), 1908 sizeof(p->td.td_link), 1909 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1910 } 1911 } 1912 delay(UHCI_QH_REMOVE_DELAY); 1913 1914 for (; std != stdend; std = p) { 1915 p = std->link.std; 1916 uhci_free_std(sc, std); 1917 } 1918 } 1919 1920 usbd_status 1921 uhci_alloc_std_chain(struct uhci_pipe *upipe, uhci_softc_t *sc, int len, 1922 int rd, u_int16_t flags, usb_dma_t *dma, 1923 uhci_soft_td_t **sp, uhci_soft_td_t **ep) 1924 { 1925 uhci_soft_td_t *p, *lastp; 1926 uhci_physaddr_t lastlink; 1927 int i, ntd, l, tog, maxp; 1928 u_int32_t status; 1929 int addr = upipe->pipe.device->address; 1930 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 1931 1932 DPRINTFN(8, ("uhci_alloc_std_chain: addr=%d endpt=%d len=%d speed=%d " 1933 "flags=0x%x\n", addr, UE_GET_ADDR(endpt), len, 1934 upipe->pipe.device->speed, flags)); 1935 maxp = UGETW(upipe->pipe.endpoint->edesc->wMaxPacketSize); 1936 if (maxp == 0) { 1937 printf("uhci_alloc_std_chain: maxp=0\n"); 1938 return (USBD_INVAL); 1939 } 1940 ntd = (len + maxp - 1) / maxp; 1941 if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0) 1942 ntd++; 1943 DPRINTFN(10, ("uhci_alloc_std_chain: maxp=%d ntd=%d\n", maxp, ntd)); 1944 if (ntd == 0) { 1945 *sp = *ep = 0; 1946 DPRINTFN(-1,("uhci_alloc_std_chain: ntd=0\n")); 1947 return (USBD_NORMAL_COMPLETION); 1948 } 1949 tog = upipe->nexttoggle; 1950 if (ntd % 2 == 0) 1951 tog ^= 1; 1952 upipe->nexttoggle = tog ^ 1; 1953 lastp = NULL; 1954 lastlink = UHCI_PTR_T; 1955 ntd--; 1956 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 1957 if (upipe->pipe.device->speed == USB_SPEED_LOW) 1958 status |= UHCI_TD_LS; 1959 if (flags & USBD_SHORT_XFER_OK) 1960 status |= UHCI_TD_SPD; 1961 usb_syncmem(dma, 0, len, 1962 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1963 for (i = ntd; i >= 0; i--) { 1964 p = uhci_alloc_std(sc); 1965 if (p == NULL) { 1966 KASSERT(lastp != NULL); 1967 uhci_free_std_chain(sc, lastp, NULL); 1968 return (USBD_NOMEM); 1969 } 1970 p->link.std = lastp; 1971 p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD); 1972 lastp = p; 1973 lastlink = p->physaddr; 1974 p->td.td_status = htole32(status); 1975 if (i == ntd) { 1976 /* last TD */ 1977 l = len % maxp; 1978 if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER)) 1979 l = maxp; 1980 *ep = p; 1981 } else 1982 l = maxp; 1983 p->td.td_token = 1984 htole32(rd ? UHCI_TD_IN (l, endpt, addr, tog) : 1985 UHCI_TD_OUT(l, endpt, addr, tog)); 1986 p->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 1987 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 1988 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1989 tog ^= 1; 1990 } 1991 *sp = lastp; 1992 DPRINTFN(10, ("uhci_alloc_std_chain: nexttog=%d\n", 1993 upipe->nexttoggle)); 1994 return (USBD_NORMAL_COMPLETION); 1995 } 1996 1997 void 1998 uhci_device_clear_toggle(usbd_pipe_handle pipe) 1999 { 2000 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2001 upipe->nexttoggle = 0; 2002 } 2003 2004 void 2005 uhci_noop(usbd_pipe_handle pipe) 2006 { 2007 } 2008 2009 usbd_status 2010 uhci_device_bulk_transfer(usbd_xfer_handle xfer) 2011 { 2012 usbd_status err; 2013 2014 /* Insert last in queue. */ 2015 err = usb_insert_transfer(xfer); 2016 if (err) 2017 return (err); 2018 2019 /* 2020 * Pipe isn't running (otherwise err would be USBD_INPROG), 2021 * so start it first. 2022 */ 2023 return (uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2024 } 2025 2026 usbd_status 2027 uhci_device_bulk_start(usbd_xfer_handle xfer) 2028 { 2029 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2030 usbd_device_handle dev = upipe->pipe.device; 2031 uhci_softc_t *sc = (uhci_softc_t *)dev->bus; 2032 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2033 uhci_soft_td_t *data, *dataend; 2034 uhci_soft_qh_t *sqh; 2035 usbd_status err; 2036 int len, isread, endpt; 2037 int s; 2038 2039 DPRINTFN(3, ("uhci_device_bulk_start: xfer=%p len=%d flags=%d ii=%p\n", 2040 xfer, xfer->length, xfer->flags, ii)); 2041 2042 if (sc->sc_dying) 2043 return (USBD_IOERROR); 2044 2045 #ifdef DIAGNOSTIC 2046 if (xfer->rqflags & URQ_REQUEST) 2047 panic("uhci_device_bulk_transfer: a request"); 2048 #endif 2049 2050 len = xfer->length; 2051 endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2052 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2053 sqh = upipe->u.bulk.sqh; 2054 2055 upipe->u.bulk.isread = isread; 2056 upipe->u.bulk.length = len; 2057 2058 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->flags, 2059 &xfer->dmabuf, &data, &dataend); 2060 if (err) 2061 return (err); 2062 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2063 usb_syncmem(&dataend->dma, 2064 dataend->offs + offsetof(uhci_td_t, td_status), 2065 sizeof(dataend->td.td_status), 2066 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2067 2068 2069 #ifdef UHCI_DEBUG 2070 if (uhcidebug > 8) { 2071 DPRINTF(("uhci_device_bulk_transfer: data(1)\n")); 2072 uhci_dump_tds(data); 2073 } 2074 #endif 2075 2076 /* Set up interrupt info. */ 2077 ii->xfer = xfer; 2078 ii->stdstart = data; 2079 ii->stdend = dataend; 2080 #ifdef DIAGNOSTIC 2081 if (!ii->isdone) { 2082 printf("uhci_device_bulk_transfer: not done, ii=%p\n", ii); 2083 } 2084 ii->isdone = 0; 2085 #endif 2086 2087 sqh->elink = data; 2088 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2089 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2090 2091 s = splusb(); 2092 uhci_add_bulk(sc, sqh); 2093 uhci_add_intr_info(sc, ii); 2094 2095 if (xfer->timeout && !sc->sc_bus.use_polling) { 2096 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 2097 uhci_timeout, ii); 2098 } 2099 xfer->status = USBD_IN_PROGRESS; 2100 splx(s); 2101 2102 #ifdef UHCI_DEBUG 2103 if (uhcidebug > 10) { 2104 DPRINTF(("uhci_device_bulk_transfer: data(2)\n")); 2105 uhci_dump_tds(data); 2106 } 2107 #endif 2108 2109 if (sc->sc_bus.use_polling) 2110 uhci_waitintr(sc, xfer); 2111 2112 return (USBD_IN_PROGRESS); 2113 } 2114 2115 /* Abort a device bulk request. */ 2116 void 2117 uhci_device_bulk_abort(usbd_xfer_handle xfer) 2118 { 2119 DPRINTF(("uhci_device_bulk_abort:\n")); 2120 uhci_abort_xfer(xfer, USBD_CANCELLED); 2121 } 2122 2123 /* 2124 * Abort a device request. 2125 * If this routine is called at splusb() it guarantees that the request 2126 * will be removed from the hardware scheduling and that the callback 2127 * for it will be called with USBD_CANCELLED status. 2128 * It's impossible to guarantee that the requested transfer will not 2129 * have happened since the hardware runs concurrently. 2130 * If the transaction has already happened we rely on the ordinary 2131 * interrupt processing to process it. 2132 */ 2133 void 2134 uhci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2135 { 2136 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2137 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2138 uhci_softc_t *sc = (uhci_softc_t *)upipe->pipe.device->bus; 2139 uhci_soft_td_t *std; 2140 int s; 2141 int wake; 2142 2143 DPRINTFN(1,("uhci_abort_xfer: xfer=%p, status=%d\n", xfer, status)); 2144 2145 if (sc->sc_dying) { 2146 /* If we're dying, just do the software part. */ 2147 s = splusb(); 2148 xfer->status = status; /* make software ignore it */ 2149 usb_uncallout(xfer->timeout_handle, uhci_timeout, xfer); 2150 usb_transfer_complete(xfer); 2151 splx(s); 2152 return; 2153 } 2154 2155 if (xfer->device->bus->intr_context || !curproc) 2156 panic("uhci_abort_xfer: not in process context"); 2157 2158 /* 2159 * If an abort is already in progress then just wait for it to 2160 * complete and return. 2161 */ 2162 if (xfer->hcflags & UXFER_ABORTING) { 2163 DPRINTFN(2, ("uhci_abort_xfer: already aborting\n")); 2164 #ifdef DIAGNOSTIC 2165 if (status == USBD_TIMEOUT) 2166 printf("uhci_abort_xfer: TIMEOUT while aborting\n"); 2167 #endif 2168 /* Override the status which might be USBD_TIMEOUT. */ 2169 xfer->status = status; 2170 DPRINTFN(2, ("uhci_abort_xfer: waiting for abort to finish\n")); 2171 xfer->hcflags |= UXFER_ABORTWAIT; 2172 while (xfer->hcflags & UXFER_ABORTING) 2173 tsleep(&xfer->hcflags, PZERO, "uhciaw", 0); 2174 return; 2175 } 2176 xfer->hcflags |= UXFER_ABORTING; 2177 2178 /* 2179 * Step 1: Make interrupt routine and hardware ignore xfer. 2180 */ 2181 s = splusb(); 2182 xfer->status = status; /* make software ignore it */ 2183 usb_uncallout(xfer->timeout_handle, uhci_timeout, ii); 2184 DPRINTFN(1,("uhci_abort_xfer: stop ii=%p\n", ii)); 2185 for (std = ii->stdstart; std != NULL; std = std->link.std) { 2186 usb_syncmem(&std->dma, 2187 std->offs + offsetof(uhci_td_t, td_status), 2188 sizeof(std->td.td_status), 2189 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2190 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2191 usb_syncmem(&std->dma, 2192 std->offs + offsetof(uhci_td_t, td_status), 2193 sizeof(std->td.td_status), 2194 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2195 } 2196 splx(s); 2197 2198 /* 2199 * Step 2: Wait until we know hardware has finished any possible 2200 * use of the xfer. Also make sure the soft interrupt routine 2201 * has run. 2202 */ 2203 usb_delay_ms(upipe->pipe.device->bus, 2); /* Hardware finishes in 1ms */ 2204 s = splusb(); 2205 #ifdef USB_USE_SOFTINTR 2206 sc->sc_softwake = 1; 2207 #endif /* USB_USE_SOFTINTR */ 2208 usb_schedsoftintr(&sc->sc_bus); 2209 #ifdef USB_USE_SOFTINTR 2210 DPRINTFN(1,("uhci_abort_xfer: tsleep\n")); 2211 tsleep(&sc->sc_softwake, PZERO, "uhciab", 0); 2212 #endif /* USB_USE_SOFTINTR */ 2213 splx(s); 2214 2215 /* 2216 * Step 3: Execute callback. 2217 */ 2218 DPRINTFN(1,("uhci_abort_xfer: callback\n")); 2219 s = splusb(); 2220 #ifdef DIAGNOSTIC 2221 ii->isdone = 1; 2222 #endif 2223 wake = xfer->hcflags & UXFER_ABORTWAIT; 2224 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2225 usb_transfer_complete(xfer); 2226 if (wake) 2227 wakeup(&xfer->hcflags); 2228 splx(s); 2229 } 2230 2231 /* Close a device bulk pipe. */ 2232 void 2233 uhci_device_bulk_close(usbd_pipe_handle pipe) 2234 { 2235 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2236 usbd_device_handle dev = upipe->pipe.device; 2237 uhci_softc_t *sc = (uhci_softc_t *)dev->bus; 2238 2239 uhci_free_sqh(sc, upipe->u.bulk.sqh); 2240 } 2241 2242 usbd_status 2243 uhci_device_ctrl_transfer(usbd_xfer_handle xfer) 2244 { 2245 usbd_status err; 2246 2247 /* Insert last in queue. */ 2248 err = usb_insert_transfer(xfer); 2249 if (err) 2250 return (err); 2251 2252 /* 2253 * Pipe isn't running (otherwise err would be USBD_INPROG), 2254 * so start it first. 2255 */ 2256 return (uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2257 } 2258 2259 usbd_status 2260 uhci_device_ctrl_start(usbd_xfer_handle xfer) 2261 { 2262 uhci_softc_t *sc = (uhci_softc_t *)xfer->pipe->device->bus; 2263 usbd_status err; 2264 2265 if (sc->sc_dying) 2266 return (USBD_IOERROR); 2267 2268 #ifdef DIAGNOSTIC 2269 if (!(xfer->rqflags & URQ_REQUEST)) 2270 panic("uhci_device_ctrl_transfer: not a request"); 2271 #endif 2272 2273 err = uhci_device_request(xfer); 2274 if (err) 2275 return (err); 2276 2277 if (sc->sc_bus.use_polling) 2278 uhci_waitintr(sc, xfer); 2279 return (USBD_IN_PROGRESS); 2280 } 2281 2282 usbd_status 2283 uhci_device_intr_transfer(usbd_xfer_handle xfer) 2284 { 2285 usbd_status err; 2286 2287 /* Insert last in queue. */ 2288 err = usb_insert_transfer(xfer); 2289 if (err) 2290 return (err); 2291 2292 /* 2293 * Pipe isn't running (otherwise err would be USBD_INPROG), 2294 * so start it first. 2295 */ 2296 return (uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2297 } 2298 2299 usbd_status 2300 uhci_device_intr_start(usbd_xfer_handle xfer) 2301 { 2302 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2303 usbd_device_handle dev = upipe->pipe.device; 2304 uhci_softc_t *sc = (uhci_softc_t *)dev->bus; 2305 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2306 uhci_soft_td_t *data, *dataend; 2307 uhci_soft_qh_t *sqh; 2308 usbd_status err; 2309 int isread, endpt; 2310 int i, s; 2311 2312 if (sc->sc_dying) 2313 return (USBD_IOERROR); 2314 2315 DPRINTFN(3,("uhci_device_intr_transfer: xfer=%p len=%d flags=%d\n", 2316 xfer, xfer->length, xfer->flags)); 2317 2318 #ifdef DIAGNOSTIC 2319 if (xfer->rqflags & URQ_REQUEST) 2320 panic("uhci_device_intr_transfer: a request"); 2321 #endif 2322 2323 endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2324 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2325 2326 upipe->u.intr.isread = isread; 2327 2328 err = uhci_alloc_std_chain(upipe, sc, xfer->length, isread, 2329 xfer->flags, &xfer->dmabuf, &data, 2330 &dataend); 2331 if (err) 2332 return (err); 2333 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2334 usb_syncmem(&dataend->dma, 2335 dataend->offs + offsetof(uhci_td_t, td_status), 2336 sizeof(dataend->td.td_status), 2337 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2338 2339 #ifdef UHCI_DEBUG 2340 if (uhcidebug > 10) { 2341 DPRINTF(("uhci_device_intr_transfer: data(1)\n")); 2342 uhci_dump_tds(data); 2343 uhci_dump_qh(upipe->u.intr.qhs[0]); 2344 } 2345 #endif 2346 2347 s = splusb(); 2348 /* Set up interrupt info. */ 2349 ii->xfer = xfer; 2350 ii->stdstart = data; 2351 ii->stdend = dataend; 2352 #ifdef DIAGNOSTIC 2353 if (!ii->isdone) { 2354 printf("uhci_device_intr_transfer: not done, ii=%p\n", ii); 2355 } 2356 ii->isdone = 0; 2357 #endif 2358 2359 DPRINTFN(10,("uhci_device_intr_transfer: qhs[0]=%p\n", 2360 upipe->u.intr.qhs[0])); 2361 for (i = 0; i < upipe->u.intr.npoll; i++) { 2362 sqh = upipe->u.intr.qhs[i]; 2363 sqh->elink = data; 2364 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2365 usb_syncmem(&sqh->dma, 2366 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2367 sizeof(sqh->qh.qh_elink), 2368 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2369 } 2370 uhci_add_intr_info(sc, ii); 2371 xfer->status = USBD_IN_PROGRESS; 2372 splx(s); 2373 2374 #ifdef UHCI_DEBUG 2375 if (uhcidebug > 10) { 2376 DPRINTF(("uhci_device_intr_transfer: data(2)\n")); 2377 uhci_dump_tds(data); 2378 uhci_dump_qh(upipe->u.intr.qhs[0]); 2379 } 2380 #endif 2381 2382 return (USBD_IN_PROGRESS); 2383 } 2384 2385 /* Abort a device control request. */ 2386 void 2387 uhci_device_ctrl_abort(usbd_xfer_handle xfer) 2388 { 2389 DPRINTF(("uhci_device_ctrl_abort:\n")); 2390 uhci_abort_xfer(xfer, USBD_CANCELLED); 2391 } 2392 2393 /* Close a device control pipe. */ 2394 void 2395 uhci_device_ctrl_close(usbd_pipe_handle pipe) 2396 { 2397 } 2398 2399 /* Abort a device interrupt request. */ 2400 void 2401 uhci_device_intr_abort(usbd_xfer_handle xfer) 2402 { 2403 DPRINTFN(1,("uhci_device_intr_abort: xfer=%p\n", xfer)); 2404 if (xfer->pipe->intrxfer == xfer) { 2405 DPRINTFN(1,("uhci_device_intr_abort: remove\n")); 2406 xfer->pipe->intrxfer = NULL; 2407 } 2408 uhci_abort_xfer(xfer, USBD_CANCELLED); 2409 } 2410 2411 /* Close a device interrupt pipe. */ 2412 void 2413 uhci_device_intr_close(usbd_pipe_handle pipe) 2414 { 2415 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2416 uhci_softc_t *sc = (uhci_softc_t *)pipe->device->bus; 2417 int i, npoll; 2418 int s; 2419 2420 /* Unlink descriptors from controller data structures. */ 2421 npoll = upipe->u.intr.npoll; 2422 s = splusb(); 2423 for (i = 0; i < npoll; i++) 2424 uhci_remove_intr(sc, upipe->u.intr.qhs[i]); 2425 splx(s); 2426 2427 /* 2428 * We now have to wait for any activity on the physical 2429 * descriptors to stop. 2430 */ 2431 usb_delay_ms(&sc->sc_bus, 2); 2432 2433 for(i = 0; i < npoll; i++) 2434 uhci_free_sqh(sc, upipe->u.intr.qhs[i]); 2435 free(upipe->u.intr.qhs, M_USBHC); 2436 2437 /* XXX free other resources */ 2438 } 2439 2440 usbd_status 2441 uhci_device_request(usbd_xfer_handle xfer) 2442 { 2443 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2444 usb_device_request_t *req = &xfer->request; 2445 usbd_device_handle dev = upipe->pipe.device; 2446 uhci_softc_t *sc = (uhci_softc_t *)dev->bus; 2447 int addr = dev->address; 2448 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2449 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2450 uhci_soft_td_t *setup, *data, *stat, *next, *dataend; 2451 uhci_soft_qh_t *sqh; 2452 int len; 2453 u_int32_t ls; 2454 usbd_status err; 2455 int isread; 2456 int s; 2457 2458 DPRINTFN(3,("uhci_device_control type=0x%02x, request=0x%02x, " 2459 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 2460 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2461 UGETW(req->wIndex), UGETW(req->wLength), 2462 addr, endpt)); 2463 2464 ls = dev->speed == USB_SPEED_LOW ? UHCI_TD_LS : 0; 2465 isread = req->bmRequestType & UT_READ; 2466 len = UGETW(req->wLength); 2467 2468 setup = upipe->u.ctl.setup; 2469 stat = upipe->u.ctl.stat; 2470 sqh = upipe->u.ctl.sqh; 2471 2472 /* Set up data transaction */ 2473 if (len != 0) { 2474 upipe->nexttoggle = 1; 2475 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->flags, 2476 &xfer->dmabuf, &data, &dataend); 2477 if (err) 2478 return (err); 2479 next = data; 2480 dataend->link.std = stat; 2481 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_VF | UHCI_PTR_TD); 2482 usb_syncmem(&dataend->dma, 2483 dataend->offs + offsetof(uhci_td_t, td_link), 2484 sizeof(dataend->td.td_link), 2485 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2486 } else { 2487 next = stat; 2488 } 2489 upipe->u.ctl.length = len; 2490 2491 memcpy(KERNADDR(&upipe->u.ctl.reqdma, 0), req, sizeof *req); 2492 usb_syncmem(&upipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 2493 2494 setup->link.std = next; 2495 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_VF | UHCI_PTR_TD); 2496 setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2497 UHCI_TD_ACTIVE); 2498 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof *req, endpt, addr)); 2499 setup->td.td_buffer = htole32(DMAADDR(&upipe->u.ctl.reqdma, 0)); 2500 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2501 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2502 2503 stat->link.std = NULL; 2504 stat->td.td_link = htole32(UHCI_PTR_T); 2505 stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2506 UHCI_TD_ACTIVE | UHCI_TD_IOC); 2507 stat->td.td_token = 2508 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2509 UHCI_TD_IN (0, endpt, addr, 1)); 2510 stat->td.td_buffer = htole32(0); 2511 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2512 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2513 2514 #ifdef UHCI_DEBUG 2515 if (uhcidebug > 10) { 2516 DPRINTF(("uhci_device_request: before transfer\n")); 2517 uhci_dump_tds(setup); 2518 } 2519 #endif 2520 2521 /* Set up interrupt info. */ 2522 ii->xfer = xfer; 2523 ii->stdstart = setup; 2524 ii->stdend = stat; 2525 #ifdef DIAGNOSTIC 2526 if (!ii->isdone) { 2527 printf("uhci_device_request: not done, ii=%p\n", ii); 2528 } 2529 ii->isdone = 0; 2530 #endif 2531 2532 sqh->elink = setup; 2533 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2534 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2535 2536 s = splusb(); 2537 if (dev->speed == USB_SPEED_LOW) 2538 uhci_add_ls_ctrl(sc, sqh); 2539 else 2540 uhci_add_hs_ctrl(sc, sqh); 2541 uhci_add_intr_info(sc, ii); 2542 #ifdef UHCI_DEBUG 2543 if (uhcidebug > 12) { 2544 uhci_soft_td_t *std; 2545 uhci_soft_qh_t *xqh; 2546 uhci_soft_qh_t *sxqh; 2547 int maxqh = 0; 2548 uhci_physaddr_t link; 2549 DPRINTF(("uhci_enter_ctl_q: follow from [0]\n")); 2550 for (std = sc->sc_vframes[0].htd, link = 0; 2551 (link & UHCI_PTR_QH) == 0; 2552 std = std->link.std) { 2553 link = le32toh(std->td.td_link); 2554 uhci_dump_td(std); 2555 } 2556 sxqh = (uhci_soft_qh_t *)std; 2557 uhci_dump_qh(sxqh); 2558 for (xqh = sxqh; 2559 xqh != NULL; 2560 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2561 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2562 uhci_dump_qh(xqh); 2563 } 2564 DPRINTF(("Enqueued QH:\n")); 2565 uhci_dump_qh(sqh); 2566 uhci_dump_tds(sqh->elink); 2567 } 2568 #endif 2569 if (xfer->timeout && !sc->sc_bus.use_polling) { 2570 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 2571 uhci_timeout, ii); 2572 } 2573 xfer->status = USBD_IN_PROGRESS; 2574 splx(s); 2575 2576 return (USBD_NORMAL_COMPLETION); 2577 } 2578 2579 usbd_status 2580 uhci_device_isoc_transfer(usbd_xfer_handle xfer) 2581 { 2582 usbd_status err; 2583 2584 DPRINTFN(5,("uhci_device_isoc_transfer: xfer=%p\n", xfer)); 2585 2586 /* Put it on our queue, */ 2587 err = usb_insert_transfer(xfer); 2588 2589 /* bail out on error, */ 2590 if (err && err != USBD_IN_PROGRESS) 2591 return (err); 2592 2593 /* XXX should check inuse here */ 2594 2595 /* insert into schedule, */ 2596 uhci_device_isoc_enter(xfer); 2597 2598 /* and start if the pipe wasn't running */ 2599 if (!err) 2600 uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 2601 2602 return (err); 2603 } 2604 2605 void 2606 uhci_device_isoc_enter(usbd_xfer_handle xfer) 2607 { 2608 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2609 usbd_device_handle dev = upipe->pipe.device; 2610 uhci_softc_t *sc = (uhci_softc_t *)dev->bus; 2611 struct iso *iso = &upipe->u.iso; 2612 uhci_soft_td_t *std; 2613 u_int32_t buf, len, status, offs; 2614 int s, i, next, nframes; 2615 int rd = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2616 2617 DPRINTFN(5,("uhci_device_isoc_enter: used=%d next=%d xfer=%p " 2618 "nframes=%d\n", 2619 iso->inuse, iso->next, xfer, xfer->nframes)); 2620 2621 if (sc->sc_dying) 2622 return; 2623 2624 if (xfer->status == USBD_IN_PROGRESS) { 2625 /* This request has already been entered into the frame list */ 2626 printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer); 2627 /* XXX */ 2628 } 2629 2630 #ifdef DIAGNOSTIC 2631 if (iso->inuse >= UHCI_VFRAMELIST_COUNT) 2632 printf("uhci_device_isoc_enter: overflow!\n"); 2633 #endif 2634 2635 next = iso->next; 2636 if (next == -1) { 2637 /* Not in use yet, schedule it a few frames ahead. */ 2638 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 2639 DPRINTFN(2,("uhci_device_isoc_enter: start next=%d\n", next)); 2640 } 2641 2642 xfer->status = USBD_IN_PROGRESS; 2643 UXFER(xfer)->curframe = next; 2644 2645 buf = DMAADDR(&xfer->dmabuf, 0); 2646 offs = 0; 2647 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 2648 UHCI_TD_ACTIVE | 2649 UHCI_TD_IOS); 2650 nframes = xfer->nframes; 2651 s = splusb(); 2652 for (i = 0; i < nframes; i++) { 2653 std = iso->stds[next]; 2654 if (++next >= UHCI_VFRAMELIST_COUNT) 2655 next = 0; 2656 len = xfer->frlengths[i]; 2657 std->td.td_buffer = htole32(buf); 2658 usb_syncmem(&xfer->dmabuf, offs, len, 2659 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2660 if (i == nframes - 1) 2661 status |= UHCI_TD_IOC; 2662 std->td.td_status = htole32(status); 2663 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2664 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 2665 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2666 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2667 #ifdef UHCI_DEBUG 2668 if (uhcidebug > 5) { 2669 DPRINTFN(5,("uhci_device_isoc_enter: TD %d\n", i)); 2670 uhci_dump_td(std); 2671 } 2672 #endif 2673 buf += len; 2674 offs += len; 2675 } 2676 iso->next = next; 2677 iso->inuse += xfer->nframes; 2678 2679 splx(s); 2680 } 2681 2682 usbd_status 2683 uhci_device_isoc_start(usbd_xfer_handle xfer) 2684 { 2685 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2686 uhci_softc_t *sc = (uhci_softc_t *)upipe->pipe.device->bus; 2687 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2688 uhci_soft_td_t *end; 2689 int s, i; 2690 2691 DPRINTFN(5,("uhci_device_isoc_start: xfer=%p\n", xfer)); 2692 2693 if (sc->sc_dying) 2694 return (USBD_IOERROR); 2695 2696 #ifdef DIAGNOSTIC 2697 if (xfer->status != USBD_IN_PROGRESS) 2698 printf("uhci_device_isoc_start: not in progress %p\n", xfer); 2699 #endif 2700 2701 /* Find the last TD */ 2702 i = UXFER(xfer)->curframe + xfer->nframes; 2703 if (i >= UHCI_VFRAMELIST_COUNT) 2704 i -= UHCI_VFRAMELIST_COUNT; 2705 end = upipe->u.iso.stds[i]; 2706 2707 #ifdef DIAGNOSTIC 2708 if (end == NULL) { 2709 printf("uhci_device_isoc_start: end == NULL\n"); 2710 return (USBD_INVAL); 2711 } 2712 #endif 2713 2714 s = splusb(); 2715 2716 /* Set up interrupt info. */ 2717 ii->xfer = xfer; 2718 ii->stdstart = end; 2719 ii->stdend = end; 2720 #ifdef DIAGNOSTIC 2721 if (!ii->isdone) 2722 printf("uhci_device_isoc_start: not done, ii=%p\n", ii); 2723 ii->isdone = 0; 2724 #endif 2725 uhci_add_intr_info(sc, ii); 2726 2727 splx(s); 2728 2729 return (USBD_IN_PROGRESS); 2730 } 2731 2732 void 2733 uhci_device_isoc_abort(usbd_xfer_handle xfer) 2734 { 2735 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2736 uhci_soft_td_t **stds = upipe->u.iso.stds; 2737 uhci_soft_td_t *std; 2738 int i, n, s, nframes, maxlen, len; 2739 2740 s = splusb(); 2741 2742 /* Transfer is already done. */ 2743 if (xfer->status != USBD_NOT_STARTED && 2744 xfer->status != USBD_IN_PROGRESS) { 2745 splx(s); 2746 return; 2747 } 2748 2749 /* Give xfer the requested abort code. */ 2750 xfer->status = USBD_CANCELLED; 2751 2752 /* make hardware ignore it, */ 2753 nframes = xfer->nframes; 2754 n = UXFER(xfer)->curframe; 2755 maxlen = 0; 2756 for (i = 0; i < nframes; i++) { 2757 std = stds[n]; 2758 usb_syncmem(&std->dma, 2759 std->offs + offsetof(uhci_td_t, td_status), 2760 sizeof(std->td.td_status), 2761 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2762 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2763 usb_syncmem(&std->dma, 2764 std->offs + offsetof(uhci_td_t, td_status), 2765 sizeof(std->td.td_status), 2766 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2767 usb_syncmem(&std->dma, 2768 std->offs + offsetof(uhci_td_t, td_token), 2769 sizeof(std->td.td_token), 2770 BUS_DMASYNC_POSTWRITE); 2771 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 2772 if (len > maxlen) 2773 maxlen = len; 2774 if (++n >= UHCI_VFRAMELIST_COUNT) 2775 n = 0; 2776 } 2777 2778 /* and wait until we are sure the hardware has finished. */ 2779 delay(maxlen); 2780 2781 #ifdef DIAGNOSTIC 2782 UXFER(xfer)->iinfo.isdone = 1; 2783 #endif 2784 /* Run callback and remove from interrupt list. */ 2785 usb_transfer_complete(xfer); 2786 2787 splx(s); 2788 } 2789 2790 void 2791 uhci_device_isoc_close(usbd_pipe_handle pipe) 2792 { 2793 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2794 usbd_device_handle dev = upipe->pipe.device; 2795 uhci_softc_t *sc = (uhci_softc_t *)dev->bus; 2796 uhci_soft_td_t *std, *vstd; 2797 struct iso *iso; 2798 int i, s; 2799 2800 /* 2801 * Make sure all TDs are marked as inactive. 2802 * Wait for completion. 2803 * Unschedule. 2804 * Deallocate. 2805 */ 2806 iso = &upipe->u.iso; 2807 2808 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2809 std = iso->stds[i]; 2810 usb_syncmem(&std->dma, 2811 std->offs + offsetof(uhci_td_t, td_status), 2812 sizeof(std->td.td_status), 2813 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2814 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 2815 usb_syncmem(&std->dma, 2816 std->offs + offsetof(uhci_td_t, td_status), 2817 sizeof(std->td.td_status), 2818 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2819 } 2820 usb_delay_ms(&sc->sc_bus, 2); /* wait for completion */ 2821 2822 s = splusb(); 2823 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2824 std = iso->stds[i]; 2825 for (vstd = sc->sc_vframes[i].htd; 2826 vstd != NULL && vstd->link.std != std; 2827 vstd = vstd->link.std) 2828 ; 2829 if (vstd == NULL) { 2830 /*panic*/ 2831 printf("uhci_device_isoc_close: %p not found\n", std); 2832 splx(s); 2833 return; 2834 } 2835 vstd->link = std->link; 2836 usb_syncmem(&std->dma, 2837 std->offs + offsetof(uhci_td_t, td_link), 2838 sizeof(std->td.td_link), 2839 BUS_DMASYNC_POSTWRITE); 2840 vstd->td.td_link = std->td.td_link; 2841 usb_syncmem(&vstd->dma, 2842 vstd->offs + offsetof(uhci_td_t, td_link), 2843 sizeof(vstd->td.td_link), 2844 BUS_DMASYNC_PREWRITE); 2845 uhci_free_std(sc, std); 2846 } 2847 splx(s); 2848 2849 free(iso->stds, M_USBHC); 2850 } 2851 2852 usbd_status 2853 uhci_setup_isoc(usbd_pipe_handle pipe) 2854 { 2855 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2856 usbd_device_handle dev = upipe->pipe.device; 2857 uhci_softc_t *sc = (uhci_softc_t *)dev->bus; 2858 int addr = upipe->pipe.device->address; 2859 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2860 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 2861 uhci_soft_td_t *std, *vstd; 2862 u_int32_t token; 2863 struct iso *iso; 2864 int i, s; 2865 2866 iso = &upipe->u.iso; 2867 iso->stds = malloc(UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *), 2868 M_USBHC, M_WAITOK); 2869 2870 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 2871 UHCI_TD_OUT(0, endpt, addr, 0); 2872 2873 /* Allocate the TDs and mark as inactive; */ 2874 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2875 std = uhci_alloc_std(sc); 2876 if (std == 0) 2877 goto bad; 2878 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 2879 std->td.td_token = htole32(token); 2880 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2881 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2882 iso->stds[i] = std; 2883 } 2884 2885 /* Insert TDs into schedule. */ 2886 s = splusb(); 2887 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2888 std = iso->stds[i]; 2889 vstd = sc->sc_vframes[i].htd; 2890 usb_syncmem(&vstd->dma, 2891 vstd->offs + offsetof(uhci_td_t, td_link), 2892 sizeof(vstd->td.td_link), 2893 BUS_DMASYNC_POSTWRITE); 2894 std->link = vstd->link; 2895 std->td.td_link = vstd->td.td_link; 2896 usb_syncmem(&std->dma, 2897 std->offs + offsetof(uhci_td_t, td_link), 2898 sizeof(std->td.td_link), 2899 BUS_DMASYNC_PREWRITE); 2900 vstd->link.std = std; 2901 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 2902 usb_syncmem(&vstd->dma, 2903 vstd->offs + offsetof(uhci_td_t, td_link), 2904 sizeof(vstd->td.td_link), 2905 BUS_DMASYNC_PREWRITE); 2906 } 2907 splx(s); 2908 2909 iso->next = -1; 2910 iso->inuse = 0; 2911 2912 return (USBD_NORMAL_COMPLETION); 2913 2914 bad: 2915 while (--i >= 0) 2916 uhci_free_std(sc, iso->stds[i]); 2917 free(iso->stds, M_USBHC); 2918 return (USBD_NOMEM); 2919 } 2920 2921 void 2922 uhci_device_isoc_done(usbd_xfer_handle xfer) 2923 { 2924 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2925 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2926 int i, offs; 2927 int rd = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2928 2929 2930 DPRINTFN(4, ("uhci_isoc_done: length=%d, busy_free=0x%08x\n", 2931 xfer->actlen, xfer->busy_free)); 2932 2933 if (ii->xfer != xfer) 2934 /* Not on interrupt list, ignore it. */ 2935 return; 2936 2937 if (!uhci_active_intr_info(ii)) 2938 return; 2939 2940 #ifdef DIAGNOSTIC 2941 if (ii->stdend == NULL) { 2942 printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer); 2943 #ifdef UHCI_DEBUG 2944 uhci_dump_ii(ii); 2945 #endif 2946 return; 2947 } 2948 #endif 2949 2950 /* Turn off the interrupt since it is active even if the TD is not. */ 2951 usb_syncmem(&ii->stdend->dma, 2952 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2953 sizeof(ii->stdend->td.td_status), 2954 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2955 ii->stdend->td.td_status &= htole32(~UHCI_TD_IOC); 2956 usb_syncmem(&ii->stdend->dma, 2957 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2958 sizeof(ii->stdend->td.td_status), 2959 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2960 2961 uhci_del_intr_info(ii); /* remove from active list */ 2962 2963 offs = 0; 2964 for (i = 0; i < xfer->nframes; i++) { 2965 usb_syncmem(&xfer->dmabuf, offs, xfer->frlengths[i], 2966 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2967 offs += xfer->frlengths[i]; 2968 } 2969 } 2970 2971 void 2972 uhci_device_intr_done(usbd_xfer_handle xfer) 2973 { 2974 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2975 uhci_softc_t *sc = ii->sc; 2976 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2977 uhci_soft_qh_t *sqh; 2978 int i, npoll, isread; 2979 2980 DPRINTFN(5, ("uhci_device_intr_done: length=%d\n", xfer->actlen)); 2981 2982 npoll = upipe->u.intr.npoll; 2983 for(i = 0; i < npoll; i++) { 2984 sqh = upipe->u.intr.qhs[i]; 2985 sqh->elink = NULL; 2986 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 2987 usb_syncmem(&sqh->dma, 2988 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2989 sizeof(sqh->qh.qh_elink), 2990 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2991 } 2992 uhci_free_std_chain(sc, ii->stdstart, NULL); 2993 2994 isread = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2995 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 2996 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2997 2998 /* XXX Wasteful. */ 2999 if (xfer->pipe->repeat) { 3000 uhci_soft_td_t *data, *dataend; 3001 3002 DPRINTFN(5,("uhci_device_intr_done: requeing\n")); 3003 3004 /* This alloc cannot fail since we freed the chain above. */ 3005 uhci_alloc_std_chain(upipe, sc, xfer->length, 1, xfer->flags, 3006 &xfer->dmabuf, &data, &dataend); 3007 dataend->td.td_status |= htole32(UHCI_TD_IOC); 3008 usb_syncmem(&dataend->dma, 3009 dataend->offs + offsetof(uhci_td_t, td_status), 3010 sizeof(dataend->td.td_status), 3011 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3012 3013 #ifdef UHCI_DEBUG 3014 if (uhcidebug > 10) { 3015 DPRINTF(("uhci_device_intr_done: data(1)\n")); 3016 uhci_dump_tds(data); 3017 uhci_dump_qh(upipe->u.intr.qhs[0]); 3018 } 3019 #endif 3020 3021 ii->stdstart = data; 3022 ii->stdend = dataend; 3023 #ifdef DIAGNOSTIC 3024 if (!ii->isdone) { 3025 printf("uhci_device_intr_done: not done, ii=%p\n", ii); 3026 } 3027 ii->isdone = 0; 3028 #endif 3029 for (i = 0; i < npoll; i++) { 3030 sqh = upipe->u.intr.qhs[i]; 3031 sqh->elink = data; 3032 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 3033 usb_syncmem(&sqh->dma, 3034 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3035 sizeof(sqh->qh.qh_elink), 3036 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3037 } 3038 xfer->status = USBD_IN_PROGRESS; 3039 /* The ii is already on the examined list, just leave it. */ 3040 } else { 3041 DPRINTFN(5,("uhci_device_intr_done: removing\n")); 3042 if (uhci_active_intr_info(ii)) 3043 uhci_del_intr_info(ii); 3044 } 3045 } 3046 3047 /* Deallocate request data structures */ 3048 void 3049 uhci_device_ctrl_done(usbd_xfer_handle xfer) 3050 { 3051 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3052 uhci_softc_t *sc = ii->sc; 3053 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 3054 int len = UGETW(xfer->request.wLength); 3055 int isread = (xfer->request.bmRequestType & UT_READ); 3056 3057 #ifdef DIAGNOSTIC 3058 if (!(xfer->rqflags & URQ_REQUEST)) 3059 panic("uhci_device_ctrl_done: not a request"); 3060 #endif 3061 3062 if (!uhci_active_intr_info(ii)) 3063 return; 3064 3065 uhci_del_intr_info(ii); /* remove from active list */ 3066 3067 if (upipe->pipe.device->speed == USB_SPEED_LOW) 3068 uhci_remove_ls_ctrl(sc, upipe->u.ctl.sqh); 3069 else 3070 uhci_remove_hs_ctrl(sc, upipe->u.ctl.sqh); 3071 3072 if (upipe->u.ctl.length != 0) 3073 uhci_free_std_chain(sc, ii->stdstart->link.std, ii->stdend); 3074 3075 if (len) { 3076 usb_syncmem(&xfer->dmabuf, 0, len, 3077 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3078 } 3079 usb_syncmem(&upipe->u.ctl.reqdma, 0, 3080 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3081 3082 DPRINTFN(5, ("uhci_device_ctrl_done: length=%d\n", xfer->actlen)); 3083 } 3084 3085 /* Deallocate request data structures */ 3086 void 3087 uhci_device_bulk_done(usbd_xfer_handle xfer) 3088 { 3089 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3090 uhci_softc_t *sc = ii->sc; 3091 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 3092 3093 DPRINTFN(5,("uhci_device_bulk_done: xfer=%p ii=%p sc=%p upipe=%p\n", 3094 xfer, ii, sc, upipe)); 3095 3096 if (!uhci_active_intr_info(ii)) 3097 return; 3098 3099 uhci_del_intr_info(ii); /* remove from active list */ 3100 3101 uhci_remove_bulk(sc, upipe->u.bulk.sqh); 3102 3103 uhci_free_std_chain(sc, ii->stdstart, NULL); 3104 3105 DPRINTFN(5, ("uhci_device_bulk_done: length=%d\n", xfer->actlen)); 3106 } 3107 3108 /* Add interrupt QH, called with vflock. */ 3109 void 3110 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3111 { 3112 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3113 uhci_soft_qh_t *eqh; 3114 3115 DPRINTFN(4, ("uhci_add_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3116 3117 eqh = vf->eqh; 3118 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3119 sizeof(eqh->qh.qh_hlink), 3120 BUS_DMASYNC_POSTWRITE); 3121 sqh->hlink = eqh->hlink; 3122 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3123 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3124 sizeof(sqh->qh.qh_hlink), 3125 BUS_DMASYNC_PREWRITE); 3126 eqh->hlink = sqh; 3127 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3128 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3129 sizeof(eqh->qh.qh_hlink), 3130 BUS_DMASYNC_PREWRITE); 3131 vf->eqh = sqh; 3132 vf->bandwidth++; 3133 } 3134 3135 /* Remove interrupt QH. */ 3136 void 3137 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3138 { 3139 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3140 uhci_soft_qh_t *pqh; 3141 3142 DPRINTFN(4, ("uhci_remove_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3143 3144 /* See comment in uhci_remove_ctrl() */ 3145 3146 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3147 sizeof(sqh->qh.qh_elink), 3148 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3149 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3150 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3151 usb_syncmem(&sqh->dma, 3152 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3153 sizeof(sqh->qh.qh_elink), 3154 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3155 delay(UHCI_QH_REMOVE_DELAY); 3156 } 3157 3158 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3159 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3160 sizeof(sqh->qh.qh_hlink), 3161 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3162 pqh->hlink = sqh->hlink; 3163 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3164 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3165 sizeof(pqh->qh.qh_hlink), 3166 BUS_DMASYNC_PREWRITE); 3167 delay(UHCI_QH_REMOVE_DELAY); 3168 if (vf->eqh == sqh) 3169 vf->eqh = pqh; 3170 vf->bandwidth--; 3171 } 3172 3173 usbd_status 3174 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3175 { 3176 uhci_soft_qh_t *sqh; 3177 int i, npoll, s; 3178 u_int bestbw, bw, bestoffs, offs; 3179 3180 DPRINTFN(2, ("uhci_device_setintr: pipe=%p\n", upipe)); 3181 if (ival == 0) { 3182 printf("uhci_device_setintr: 0 interval\n"); 3183 return (USBD_INVAL); 3184 } 3185 3186 if (ival > UHCI_VFRAMELIST_COUNT) 3187 ival = UHCI_VFRAMELIST_COUNT; 3188 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3189 DPRINTFN(2, ("uhci_device_setintr: ival=%d npoll=%d\n", ival, npoll)); 3190 3191 upipe->u.intr.npoll = npoll; 3192 upipe->u.intr.qhs = 3193 malloc(npoll * sizeof(uhci_soft_qh_t *), M_USBHC, M_WAITOK); 3194 3195 /* 3196 * Figure out which offset in the schedule that has most 3197 * bandwidth left over. 3198 */ 3199 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3200 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3201 for (bw = i = 0; i < npoll; i++) 3202 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3203 if (bw < bestbw) { 3204 bestbw = bw; 3205 bestoffs = offs; 3206 } 3207 } 3208 DPRINTFN(1, ("uhci_device_setintr: bw=%d offs=%d\n", bestbw, bestoffs)); 3209 3210 for(i = 0; i < npoll; i++) { 3211 upipe->u.intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3212 sqh->elink = NULL; 3213 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3214 usb_syncmem(&sqh->dma, 3215 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3216 sizeof(sqh->qh.qh_elink), 3217 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3218 sqh->pos = MOD(i * ival + bestoffs); 3219 } 3220 #undef MOD 3221 3222 s = splusb(); 3223 /* Enter QHs into the controller data structures. */ 3224 for(i = 0; i < npoll; i++) 3225 uhci_add_intr(sc, upipe->u.intr.qhs[i]); 3226 splx(s); 3227 3228 DPRINTFN(5, ("uhci_device_setintr: returns %p\n", upipe)); 3229 return (USBD_NORMAL_COMPLETION); 3230 } 3231 3232 /* Open a new pipe. */ 3233 usbd_status 3234 uhci_open(usbd_pipe_handle pipe) 3235 { 3236 uhci_softc_t *sc = (uhci_softc_t *)pipe->device->bus; 3237 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 3238 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 3239 usbd_status err; 3240 int ival; 3241 3242 DPRINTFN(1, ("uhci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 3243 pipe, pipe->device->address, 3244 ed->bEndpointAddress, sc->sc_addr)); 3245 3246 upipe->aborting = 0; 3247 upipe->nexttoggle = 0; 3248 3249 if (pipe->device->address == sc->sc_addr) { 3250 switch (ed->bEndpointAddress) { 3251 case USB_CONTROL_ENDPOINT: 3252 pipe->methods = &uhci_root_ctrl_methods; 3253 break; 3254 case UE_DIR_IN | UHCI_INTR_ENDPT: 3255 pipe->methods = &uhci_root_intr_methods; 3256 break; 3257 default: 3258 return (USBD_INVAL); 3259 } 3260 } else { 3261 switch (ed->bmAttributes & UE_XFERTYPE) { 3262 case UE_CONTROL: 3263 pipe->methods = &uhci_device_ctrl_methods; 3264 upipe->u.ctl.sqh = uhci_alloc_sqh(sc); 3265 if (upipe->u.ctl.sqh == NULL) 3266 goto bad; 3267 upipe->u.ctl.setup = uhci_alloc_std(sc); 3268 if (upipe->u.ctl.setup == NULL) { 3269 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3270 goto bad; 3271 } 3272 upipe->u.ctl.stat = uhci_alloc_std(sc); 3273 if (upipe->u.ctl.stat == NULL) { 3274 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3275 uhci_free_std(sc, upipe->u.ctl.setup); 3276 goto bad; 3277 } 3278 err = usb_allocmem(&sc->sc_bus, 3279 sizeof(usb_device_request_t), 3280 0, &upipe->u.ctl.reqdma); 3281 if (err) { 3282 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3283 uhci_free_std(sc, upipe->u.ctl.setup); 3284 uhci_free_std(sc, upipe->u.ctl.stat); 3285 goto bad; 3286 } 3287 break; 3288 case UE_INTERRUPT: 3289 pipe->methods = &uhci_device_intr_methods; 3290 ival = pipe->interval; 3291 if (ival == USBD_DEFAULT_INTERVAL) 3292 ival = ed->bInterval; 3293 return (uhci_device_setintr(sc, upipe, ival)); 3294 case UE_ISOCHRONOUS: 3295 pipe->methods = &uhci_device_isoc_methods; 3296 return (uhci_setup_isoc(pipe)); 3297 case UE_BULK: 3298 pipe->methods = &uhci_device_bulk_methods; 3299 upipe->u.bulk.sqh = uhci_alloc_sqh(sc); 3300 if (upipe->u.bulk.sqh == NULL) 3301 goto bad; 3302 break; 3303 } 3304 } 3305 return (USBD_NORMAL_COMPLETION); 3306 3307 bad: 3308 return (USBD_NOMEM); 3309 } 3310 3311 /* 3312 * Data structures and routines to emulate the root hub. 3313 */ 3314 usb_device_descriptor_t uhci_devd = { 3315 USB_DEVICE_DESCRIPTOR_SIZE, 3316 UDESC_DEVICE, /* type */ 3317 {0x00, 0x01}, /* USB version */ 3318 UDCLASS_HUB, /* class */ 3319 UDSUBCLASS_HUB, /* subclass */ 3320 UDPROTO_FSHUB, /* protocol */ 3321 64, /* max packet */ 3322 {0},{0},{0x00,0x01}, /* device id */ 3323 1,2,0, /* string indicies */ 3324 1 /* # of configurations */ 3325 }; 3326 3327 usb_config_descriptor_t uhci_confd = { 3328 USB_CONFIG_DESCRIPTOR_SIZE, 3329 UDESC_CONFIG, 3330 {USB_CONFIG_DESCRIPTOR_SIZE + 3331 USB_INTERFACE_DESCRIPTOR_SIZE + 3332 USB_ENDPOINT_DESCRIPTOR_SIZE}, 3333 1, 3334 1, 3335 0, 3336 UC_SELF_POWERED, 3337 0 /* max power */ 3338 }; 3339 3340 usb_interface_descriptor_t uhci_ifcd = { 3341 USB_INTERFACE_DESCRIPTOR_SIZE, 3342 UDESC_INTERFACE, 3343 0, 3344 0, 3345 1, 3346 UICLASS_HUB, 3347 UISUBCLASS_HUB, 3348 UIPROTO_FSHUB, 3349 0 3350 }; 3351 3352 usb_endpoint_descriptor_t uhci_endpd = { 3353 USB_ENDPOINT_DESCRIPTOR_SIZE, 3354 UDESC_ENDPOINT, 3355 UE_DIR_IN | UHCI_INTR_ENDPT, 3356 UE_INTERRUPT, 3357 {8}, 3358 255 3359 }; 3360 3361 usb_hub_descriptor_t uhci_hubd_piix = { 3362 USB_HUB_DESCRIPTOR_SIZE, 3363 UDESC_HUB, 3364 2, 3365 { UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0 }, 3366 50, /* power on to power good */ 3367 0, 3368 { 0x00 }, /* both ports are removable */ 3369 { 0 }, 3370 }; 3371 3372 int 3373 uhci_str(usb_string_descriptor_t *p, int l, const char *s) 3374 { 3375 int i; 3376 3377 if (l == 0) 3378 return (0); 3379 p->bLength = 2 * strlen(s) + 2; 3380 if (l == 1) 3381 return (1); 3382 p->bDescriptorType = UDESC_STRING; 3383 l -= 2; 3384 for (i = 0; s[i] && l > 1; i++, l -= 2) 3385 USETW2(p->bString[i], 0, s[i]); 3386 return (2*i+2); 3387 } 3388 3389 /* 3390 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3391 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3392 * should not be used by the USB subsystem. As we cannot issue a 3393 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3394 * will be enabled as part of the reset. 3395 * 3396 * On the VT83C572, the port cannot be successfully enabled until the 3397 * outstanding "port enable change" and "connection status change" 3398 * events have been reset. 3399 */ 3400 Static usbd_status 3401 uhci_portreset(uhci_softc_t *sc, int index) 3402 { 3403 int lim, port, x; 3404 3405 if (index == 1) 3406 port = UHCI_PORTSC1; 3407 else if (index == 2) 3408 port = UHCI_PORTSC2; 3409 else 3410 return (USBD_IOERROR); 3411 3412 x = URWMASK(UREAD2(sc, port)); 3413 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3414 3415 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3416 3417 DPRINTFN(3,("uhci port %d reset, status0 = 0x%04x\n", 3418 index, UREAD2(sc, port))); 3419 3420 x = URWMASK(UREAD2(sc, port)); 3421 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3422 3423 delay(100); 3424 3425 DPRINTFN(3,("uhci port %d reset, status1 = 0x%04x\n", 3426 index, UREAD2(sc, port))); 3427 3428 x = URWMASK(UREAD2(sc, port)); 3429 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3430 3431 for (lim = 10; --lim > 0;) { 3432 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3433 3434 x = UREAD2(sc, port); 3435 3436 DPRINTFN(3,("uhci port %d iteration %u, status = 0x%04x\n", 3437 index, lim, x)); 3438 3439 if (!(x & UHCI_PORTSC_CCS)) { 3440 /* 3441 * No device is connected (or was disconnected 3442 * during reset). Consider the port reset. 3443 * The delay must be long enough to ensure on 3444 * the initial iteration that the device 3445 * connection will have been registered. 50ms 3446 * appears to be sufficient, but 20ms is not. 3447 */ 3448 DPRINTFN(3,("uhci port %d loop %u, device detached\n", 3449 index, lim)); 3450 break; 3451 } 3452 3453 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3454 /* 3455 * Port enabled changed and/or connection 3456 * status changed were set. Reset either or 3457 * both raised flags (by writing a 1 to that 3458 * bit), and wait again for state to settle. 3459 */ 3460 UWRITE2(sc, port, URWMASK(x) | 3461 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3462 continue; 3463 } 3464 3465 if (x & UHCI_PORTSC_PE) 3466 /* Port is enabled */ 3467 break; 3468 3469 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3470 } 3471 3472 DPRINTFN(3,("uhci port %d reset, status2 = 0x%04x\n", 3473 index, UREAD2(sc, port))); 3474 3475 if (lim <= 0) { 3476 DPRINTFN(1,("uhci port %d reset timed out\n", index)); 3477 return (USBD_TIMEOUT); 3478 } 3479 3480 sc->sc_isreset = 1; 3481 return (USBD_NORMAL_COMPLETION); 3482 } 3483 3484 /* 3485 * Simulate a hardware hub by handling all the necessary requests. 3486 */ 3487 usbd_status 3488 uhci_root_ctrl_transfer(usbd_xfer_handle xfer) 3489 { 3490 usbd_status err; 3491 3492 /* Insert last in queue. */ 3493 err = usb_insert_transfer(xfer); 3494 if (err) 3495 return (err); 3496 3497 /* 3498 * Pipe isn't running (otherwise err would be USBD_INPROG), 3499 * so start it first. 3500 */ 3501 return (uhci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3502 } 3503 3504 usbd_status 3505 uhci_root_ctrl_start(usbd_xfer_handle xfer) 3506 { 3507 uhci_softc_t *sc = (uhci_softc_t *)xfer->pipe->device->bus; 3508 usb_device_request_t *req; 3509 void *buf = NULL; 3510 int port, x; 3511 int s, len, value, index, status, change, l, totlen = 0; 3512 usb_port_status_t ps; 3513 usbd_status err; 3514 3515 if (sc->sc_dying) 3516 return (USBD_IOERROR); 3517 3518 #ifdef DIAGNOSTIC 3519 if (!(xfer->rqflags & URQ_REQUEST)) 3520 panic("uhci_root_ctrl_transfer: not a request"); 3521 #endif 3522 req = &xfer->request; 3523 3524 DPRINTFN(2,("uhci_root_ctrl_control type=0x%02x request=%02x\n", 3525 req->bmRequestType, req->bRequest)); 3526 3527 len = UGETW(req->wLength); 3528 value = UGETW(req->wValue); 3529 index = UGETW(req->wIndex); 3530 3531 if (len != 0) 3532 buf = KERNADDR(&xfer->dmabuf, 0); 3533 3534 #define C(x,y) ((x) | ((y) << 8)) 3535 switch(C(req->bRequest, req->bmRequestType)) { 3536 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3537 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3538 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3539 /* 3540 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3541 * for the integrated root hub. 3542 */ 3543 break; 3544 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3545 if (len > 0) { 3546 *(u_int8_t *)buf = sc->sc_conf; 3547 totlen = 1; 3548 } 3549 break; 3550 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3551 DPRINTFN(2,("uhci_root_ctrl_control wValue=0x%04x\n", value)); 3552 if (len == 0) 3553 break; 3554 switch(value >> 8) { 3555 case UDESC_DEVICE: 3556 if ((value & 0xff) != 0) { 3557 err = USBD_IOERROR; 3558 goto ret; 3559 } 3560 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 3561 USETW(uhci_devd.idVendor, sc->sc_id_vendor); 3562 memcpy(buf, &uhci_devd, l); 3563 break; 3564 case UDESC_CONFIG: 3565 if ((value & 0xff) != 0) { 3566 err = USBD_IOERROR; 3567 goto ret; 3568 } 3569 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 3570 memcpy(buf, &uhci_confd, l); 3571 buf = (char *)buf + l; 3572 len -= l; 3573 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 3574 totlen += l; 3575 memcpy(buf, &uhci_ifcd, l); 3576 buf = (char *)buf + l; 3577 len -= l; 3578 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 3579 totlen += l; 3580 memcpy(buf, &uhci_endpd, l); 3581 break; 3582 case UDESC_STRING: 3583 *(u_int8_t *)buf = 0; 3584 totlen = 1; 3585 switch (value & 0xff) { 3586 case 0: /* Language table */ 3587 totlen = uhci_str(buf, len, "\001"); 3588 break; 3589 case 1: /* Vendor */ 3590 totlen = uhci_str(buf, len, sc->sc_vendor); 3591 break; 3592 case 2: /* Product */ 3593 totlen = uhci_str(buf, len, "UHCI root hub"); 3594 break; 3595 } 3596 break; 3597 default: 3598 err = USBD_IOERROR; 3599 goto ret; 3600 } 3601 break; 3602 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3603 if (len > 0) { 3604 *(u_int8_t *)buf = 0; 3605 totlen = 1; 3606 } 3607 break; 3608 case C(UR_GET_STATUS, UT_READ_DEVICE): 3609 if (len > 1) { 3610 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 3611 totlen = 2; 3612 } 3613 break; 3614 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3615 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3616 if (len > 1) { 3617 USETW(((usb_status_t *)buf)->wStatus, 0); 3618 totlen = 2; 3619 } 3620 break; 3621 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3622 if (value >= USB_MAX_DEVICES) { 3623 err = USBD_IOERROR; 3624 goto ret; 3625 } 3626 sc->sc_addr = value; 3627 break; 3628 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3629 if (value != 0 && value != 1) { 3630 err = USBD_IOERROR; 3631 goto ret; 3632 } 3633 sc->sc_conf = value; 3634 break; 3635 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3636 break; 3637 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3638 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3639 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3640 err = USBD_IOERROR; 3641 goto ret; 3642 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3643 break; 3644 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3645 break; 3646 /* Hub requests */ 3647 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3648 break; 3649 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3650 DPRINTFN(3, ("uhci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 3651 "port=%d feature=%d\n", 3652 index, value)); 3653 if (index == 1) 3654 port = UHCI_PORTSC1; 3655 else if (index == 2) 3656 port = UHCI_PORTSC2; 3657 else { 3658 err = USBD_IOERROR; 3659 goto ret; 3660 } 3661 switch(value) { 3662 case UHF_PORT_ENABLE: 3663 x = URWMASK(UREAD2(sc, port)); 3664 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3665 break; 3666 case UHF_PORT_SUSPEND: 3667 x = URWMASK(UREAD2(sc, port)); 3668 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3669 break; 3670 case UHF_PORT_RESET: 3671 x = URWMASK(UREAD2(sc, port)); 3672 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3673 break; 3674 case UHF_C_PORT_CONNECTION: 3675 x = URWMASK(UREAD2(sc, port)); 3676 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3677 break; 3678 case UHF_C_PORT_ENABLE: 3679 x = URWMASK(UREAD2(sc, port)); 3680 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3681 break; 3682 case UHF_C_PORT_OVER_CURRENT: 3683 x = URWMASK(UREAD2(sc, port)); 3684 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3685 break; 3686 case UHF_C_PORT_RESET: 3687 sc->sc_isreset = 0; 3688 err = USBD_NORMAL_COMPLETION; 3689 goto ret; 3690 case UHF_PORT_CONNECTION: 3691 case UHF_PORT_OVER_CURRENT: 3692 case UHF_PORT_POWER: 3693 case UHF_PORT_LOW_SPEED: 3694 case UHF_C_PORT_SUSPEND: 3695 default: 3696 err = USBD_IOERROR; 3697 goto ret; 3698 } 3699 break; 3700 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3701 if (index == 1) 3702 port = UHCI_PORTSC1; 3703 else if (index == 2) 3704 port = UHCI_PORTSC2; 3705 else { 3706 err = USBD_IOERROR; 3707 goto ret; 3708 } 3709 if (len > 0) { 3710 *(u_int8_t *)buf = 3711 (UREAD2(sc, port) & UHCI_PORTSC_LS) >> 3712 UHCI_PORTSC_LS_SHIFT; 3713 totlen = 1; 3714 } 3715 break; 3716 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3717 if (len == 0) 3718 break; 3719 if ((value & 0xff) != 0) { 3720 err = USBD_IOERROR; 3721 goto ret; 3722 } 3723 l = min(len, USB_HUB_DESCRIPTOR_SIZE); 3724 totlen = l; 3725 memcpy(buf, &uhci_hubd_piix, l); 3726 break; 3727 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3728 if (len != 4) { 3729 err = USBD_IOERROR; 3730 goto ret; 3731 } 3732 memset(buf, 0, len); 3733 totlen = len; 3734 break; 3735 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3736 if (index == 1) 3737 port = UHCI_PORTSC1; 3738 else if (index == 2) 3739 port = UHCI_PORTSC2; 3740 else { 3741 err = USBD_IOERROR; 3742 goto ret; 3743 } 3744 if (len != 4) { 3745 err = USBD_IOERROR; 3746 goto ret; 3747 } 3748 x = UREAD2(sc, port); 3749 status = change = 0; 3750 if (x & UHCI_PORTSC_CCS) 3751 status |= UPS_CURRENT_CONNECT_STATUS; 3752 if (x & UHCI_PORTSC_CSC) 3753 change |= UPS_C_CONNECT_STATUS; 3754 if (x & UHCI_PORTSC_PE) 3755 status |= UPS_PORT_ENABLED; 3756 if (x & UHCI_PORTSC_POEDC) 3757 change |= UPS_C_PORT_ENABLED; 3758 if (x & UHCI_PORTSC_OCI) 3759 status |= UPS_OVERCURRENT_INDICATOR; 3760 if (x & UHCI_PORTSC_OCIC) 3761 change |= UPS_C_OVERCURRENT_INDICATOR; 3762 if (x & UHCI_PORTSC_SUSP) 3763 status |= UPS_SUSPEND; 3764 if (x & UHCI_PORTSC_LSDA) 3765 status |= UPS_LOW_SPEED; 3766 status |= UPS_PORT_POWER; 3767 if (sc->sc_isreset) 3768 change |= UPS_C_PORT_RESET; 3769 USETW(ps.wPortStatus, status); 3770 USETW(ps.wPortChange, change); 3771 l = min(len, sizeof ps); 3772 memcpy(buf, &ps, l); 3773 totlen = l; 3774 break; 3775 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3776 err = USBD_IOERROR; 3777 goto ret; 3778 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3779 break; 3780 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3781 if (index == 1) 3782 port = UHCI_PORTSC1; 3783 else if (index == 2) 3784 port = UHCI_PORTSC2; 3785 else { 3786 err = USBD_IOERROR; 3787 goto ret; 3788 } 3789 switch(value) { 3790 case UHF_PORT_ENABLE: 3791 x = URWMASK(UREAD2(sc, port)); 3792 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3793 break; 3794 case UHF_PORT_SUSPEND: 3795 x = URWMASK(UREAD2(sc, port)); 3796 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 3797 break; 3798 case UHF_PORT_RESET: 3799 err = uhci_portreset(sc, index); 3800 goto ret; 3801 case UHF_PORT_POWER: 3802 /* Pretend we turned on power */ 3803 err = USBD_NORMAL_COMPLETION; 3804 goto ret; 3805 case UHF_C_PORT_CONNECTION: 3806 case UHF_C_PORT_ENABLE: 3807 case UHF_C_PORT_OVER_CURRENT: 3808 case UHF_PORT_CONNECTION: 3809 case UHF_PORT_OVER_CURRENT: 3810 case UHF_PORT_LOW_SPEED: 3811 case UHF_C_PORT_SUSPEND: 3812 case UHF_C_PORT_RESET: 3813 default: 3814 err = USBD_IOERROR; 3815 goto ret; 3816 } 3817 break; 3818 default: 3819 err = USBD_IOERROR; 3820 goto ret; 3821 } 3822 xfer->actlen = totlen; 3823 err = USBD_NORMAL_COMPLETION; 3824 ret: 3825 xfer->status = err; 3826 s = splusb(); 3827 usb_transfer_complete(xfer); 3828 splx(s); 3829 return (USBD_IN_PROGRESS); 3830 } 3831 3832 /* Abort a root control request. */ 3833 void 3834 uhci_root_ctrl_abort(usbd_xfer_handle xfer) 3835 { 3836 /* Nothing to do, all transfers are synchronous. */ 3837 } 3838 3839 /* Close the root pipe. */ 3840 void 3841 uhci_root_ctrl_close(usbd_pipe_handle pipe) 3842 { 3843 DPRINTF(("uhci_root_ctrl_close\n")); 3844 } 3845 3846 /* Abort a root interrupt request. */ 3847 void 3848 uhci_root_intr_abort(usbd_xfer_handle xfer) 3849 { 3850 uhci_softc_t *sc = (uhci_softc_t *)xfer->pipe->device->bus; 3851 3852 usb_uncallout(sc->sc_poll_handle, uhci_poll_hub, xfer); 3853 sc->sc_intr_xfer = NULL; 3854 3855 if (xfer->pipe->intrxfer == xfer) { 3856 DPRINTF(("uhci_root_intr_abort: remove\n")); 3857 xfer->pipe->intrxfer = 0; 3858 } 3859 xfer->status = USBD_CANCELLED; 3860 #ifdef DIAGNOSTIC 3861 UXFER(xfer)->iinfo.isdone = 1; 3862 #endif 3863 usb_transfer_complete(xfer); 3864 } 3865 3866 usbd_status 3867 uhci_root_intr_transfer(usbd_xfer_handle xfer) 3868 { 3869 usbd_status err; 3870 3871 /* Insert last in queue. */ 3872 err = usb_insert_transfer(xfer); 3873 if (err) 3874 return (err); 3875 3876 /* 3877 * Pipe isn't running (otherwise err would be USBD_INPROG), 3878 * start first 3879 */ 3880 return (uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3881 } 3882 3883 /* Start a transfer on the root interrupt pipe */ 3884 usbd_status 3885 uhci_root_intr_start(usbd_xfer_handle xfer) 3886 { 3887 usbd_pipe_handle pipe = xfer->pipe; 3888 uhci_softc_t *sc = (uhci_softc_t *)pipe->device->bus; 3889 unsigned int ival; 3890 3891 DPRINTFN(3, ("uhci_root_intr_start: xfer=%p len=%d flags=%d\n", 3892 xfer, xfer->length, xfer->flags)); 3893 3894 if (sc->sc_dying) 3895 return (USBD_IOERROR); 3896 3897 /* XXX temporary variable needed to avoid gcc3 warning */ 3898 ival = xfer->pipe->endpoint->edesc->bInterval; 3899 sc->sc_ival = mstohz(ival); 3900 usb_callout(sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 3901 sc->sc_intr_xfer = xfer; 3902 return (USBD_IN_PROGRESS); 3903 } 3904 3905 /* Close the root interrupt pipe. */ 3906 void 3907 uhci_root_intr_close(usbd_pipe_handle pipe) 3908 { 3909 uhci_softc_t *sc = (uhci_softc_t *)pipe->device->bus; 3910 3911 usb_uncallout(sc->sc_poll_handle, uhci_poll_hub, sc->sc_intr_xfer); 3912 sc->sc_intr_xfer = NULL; 3913 DPRINTF(("uhci_root_intr_close\n")); 3914 } 3915
Indexes created Tue Sep 30 20:09:53 GMT 2025