uhci.c revision 1.216.4.2
1 /* $NetBSD: uhci.c,v 1.216.4.2 2009/05/04 08:13:21 yamt Exp $ */ 2 /* $FreeBSD: src/sys/dev/usb/uhci.c,v 1.33 1999/11/17 22:33:41 n_hibma Exp $ */ 3 4 /* 5 * Copyright (c) 1998, 2004 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Lennart Augustsson (lennart (at) augustsson.net) at 10 * Carlstedt Research & Technology. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Universal Host Controller driver. 36 * Handles e.g. PIIX3 and PIIX4. 37 * 38 * UHCI spec: http://developer.intel.com/design/USB/UHCI11D.htm 39 * USB spec: http://www.usb.org/developers/docs/usbspec.zip 40 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 41 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.216.4.2 2009/05/04 08:13:21 yamt Exp $"); 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/malloc.h> 51 #if defined(__NetBSD__) || defined(__OpenBSD__) 52 #include <sys/device.h> 53 #include <sys/select.h> 54 #include <sys/extent.h> 55 #include <uvm/uvm_extern.h> 56 #elif defined(__FreeBSD__) 57 #include <sys/module.h> 58 #include <sys/bus.h> 59 #include <machine/bus_pio.h> 60 #if defined(DIAGNOSTIC) && defined(__i386__) 61 #include <sys/cpu.h> 62 #endif 63 #endif 64 #include <sys/proc.h> 65 #include <sys/queue.h> 66 #include <sys/bus.h> 67 68 #include <machine/endian.h> 69 70 #include <dev/usb/usb.h> 71 #include <dev/usb/usbdi.h> 72 #include <dev/usb/usbdivar.h> 73 #include <dev/usb/usb_mem.h> 74 #include <dev/usb/usb_quirks.h> 75 76 #include <dev/usb/uhcireg.h> 77 #include <dev/usb/uhcivar.h> 78 #include <dev/usb/usbroothub_subr.h> 79 80 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 81 /*#define UHCI_CTL_LOOP */ 82 83 #if defined(__FreeBSD__) 84 #include <machine/clock.h> 85 86 #define delay(d) DELAY(d) 87 #endif 88 89 #if defined(__OpenBSD__) 90 struct cfdriver uhci_cd = { 91 NULL, "uhci", DV_DULL 92 }; 93 #endif 94 95 #ifdef UHCI_DEBUG 96 uhci_softc_t *thesc; 97 #define DPRINTF(x) if (uhcidebug) printf x 98 #define DPRINTFN(n,x) if (uhcidebug>(n)) printf x 99 int uhcidebug = 0; 100 int uhcinoloop = 0; 101 #ifndef __NetBSD__ 102 #define snprintb((q), (f), "%b", q,f,b,l) snprintf((b), (l)) 103 #endif 104 #else 105 #define DPRINTF(x) 106 #define DPRINTFN(n,x) 107 #endif 108 109 /* 110 * The UHCI controller is little endian, so on big endian machines 111 * the data stored in memory needs to be swapped. 112 */ 113 #if defined(__FreeBSD__) || defined(__OpenBSD__) 114 #if BYTE_ORDER == BIG_ENDIAN 115 #define htole32(x) (bswap32(x)) 116 #define le32toh(x) (bswap32(x)) 117 #else 118 #define htole32(x) (x) 119 #define le32toh(x) (x) 120 #endif 121 #endif 122 123 struct uhci_pipe { 124 struct usbd_pipe pipe; 125 int nexttoggle; 126 127 u_char aborting; 128 usbd_xfer_handle abortstart, abortend; 129 130 /* Info needed for different pipe kinds. */ 131 union { 132 /* Control pipe */ 133 struct { 134 uhci_soft_qh_t *sqh; 135 usb_dma_t reqdma; 136 uhci_soft_td_t *setup, *stat; 137 u_int length; 138 } ctl; 139 /* Interrupt pipe */ 140 struct { 141 int npoll; 142 int isread; 143 uhci_soft_qh_t **qhs; 144 } intr; 145 /* Bulk pipe */ 146 struct { 147 uhci_soft_qh_t *sqh; 148 u_int length; 149 int isread; 150 } bulk; 151 /* Iso pipe */ 152 struct iso { 153 uhci_soft_td_t **stds; 154 int next, inuse; 155 } iso; 156 } u; 157 }; 158 159 Static void uhci_globalreset(uhci_softc_t *); 160 Static usbd_status uhci_portreset(uhci_softc_t*, int); 161 Static void uhci_reset(uhci_softc_t *); 162 Static usbd_status uhci_run(uhci_softc_t *, int run); 163 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 164 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 165 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 166 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 167 #if 0 168 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 169 uhci_intr_info_t *); 170 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 171 #endif 172 173 Static void uhci_free_std_chain(uhci_softc_t *, 174 uhci_soft_td_t *, uhci_soft_td_t *); 175 Static usbd_status uhci_alloc_std_chain(struct uhci_pipe *, 176 uhci_softc_t *, int, int, u_int16_t, usb_dma_t *, 177 uhci_soft_td_t **, uhci_soft_td_t **); 178 Static void uhci_poll_hub(void *); 179 Static void uhci_waitintr(uhci_softc_t *, usbd_xfer_handle); 180 Static void uhci_check_intr(uhci_softc_t *, uhci_intr_info_t *); 181 Static void uhci_idone(uhci_intr_info_t *); 182 183 Static void uhci_abort_xfer(usbd_xfer_handle, usbd_status status); 184 185 Static void uhci_timeout(void *); 186 Static void uhci_timeout_task(void *); 187 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 188 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 189 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 190 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 191 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 192 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 193 Static void uhci_add_loop(uhci_softc_t *sc); 194 Static void uhci_rem_loop(uhci_softc_t *sc); 195 196 Static usbd_status uhci_setup_isoc(usbd_pipe_handle pipe); 197 Static void uhci_device_isoc_enter(usbd_xfer_handle); 198 199 Static usbd_status uhci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 200 Static void uhci_freem(struct usbd_bus *, usb_dma_t *); 201 202 Static usbd_xfer_handle uhci_allocx(struct usbd_bus *); 203 Static void uhci_freex(struct usbd_bus *, usbd_xfer_handle); 204 205 Static usbd_status uhci_device_ctrl_transfer(usbd_xfer_handle); 206 Static usbd_status uhci_device_ctrl_start(usbd_xfer_handle); 207 Static void uhci_device_ctrl_abort(usbd_xfer_handle); 208 Static void uhci_device_ctrl_close(usbd_pipe_handle); 209 Static void uhci_device_ctrl_done(usbd_xfer_handle); 210 211 Static usbd_status uhci_device_intr_transfer(usbd_xfer_handle); 212 Static usbd_status uhci_device_intr_start(usbd_xfer_handle); 213 Static void uhci_device_intr_abort(usbd_xfer_handle); 214 Static void uhci_device_intr_close(usbd_pipe_handle); 215 Static void uhci_device_intr_done(usbd_xfer_handle); 216 217 Static usbd_status uhci_device_bulk_transfer(usbd_xfer_handle); 218 Static usbd_status uhci_device_bulk_start(usbd_xfer_handle); 219 Static void uhci_device_bulk_abort(usbd_xfer_handle); 220 Static void uhci_device_bulk_close(usbd_pipe_handle); 221 Static void uhci_device_bulk_done(usbd_xfer_handle); 222 223 Static usbd_status uhci_device_isoc_transfer(usbd_xfer_handle); 224 Static usbd_status uhci_device_isoc_start(usbd_xfer_handle); 225 Static void uhci_device_isoc_abort(usbd_xfer_handle); 226 Static void uhci_device_isoc_close(usbd_pipe_handle); 227 Static void uhci_device_isoc_done(usbd_xfer_handle); 228 229 Static usbd_status uhci_root_ctrl_transfer(usbd_xfer_handle); 230 Static usbd_status uhci_root_ctrl_start(usbd_xfer_handle); 231 Static void uhci_root_ctrl_abort(usbd_xfer_handle); 232 Static void uhci_root_ctrl_close(usbd_pipe_handle); 233 Static void uhci_root_ctrl_done(usbd_xfer_handle); 234 235 Static usbd_status uhci_root_intr_transfer(usbd_xfer_handle); 236 Static usbd_status uhci_root_intr_start(usbd_xfer_handle); 237 Static void uhci_root_intr_abort(usbd_xfer_handle); 238 Static void uhci_root_intr_close(usbd_pipe_handle); 239 Static void uhci_root_intr_done(usbd_xfer_handle); 240 241 Static usbd_status uhci_open(usbd_pipe_handle); 242 Static void uhci_poll(struct usbd_bus *); 243 Static void uhci_softintr(void *); 244 245 Static usbd_status uhci_device_request(usbd_xfer_handle xfer); 246 247 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 248 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 249 Static usbd_status uhci_device_setintr(uhci_softc_t *sc, 250 struct uhci_pipe *pipe, int ival); 251 252 Static void uhci_device_clear_toggle(usbd_pipe_handle pipe); 253 Static void uhci_noop(usbd_pipe_handle pipe); 254 255 Static inline uhci_soft_qh_t *uhci_find_prev_qh(uhci_soft_qh_t *, 256 uhci_soft_qh_t *); 257 258 #ifdef UHCI_DEBUG 259 Static void uhci_dump_all(uhci_softc_t *); 260 Static void uhci_dumpregs(uhci_softc_t *); 261 Static void uhci_dump_qhs(uhci_soft_qh_t *); 262 Static void uhci_dump_qh(uhci_soft_qh_t *); 263 Static void uhci_dump_tds(uhci_soft_td_t *); 264 Static void uhci_dump_td(uhci_soft_td_t *); 265 Static void uhci_dump_ii(uhci_intr_info_t *ii); 266 void uhci_dump(void); 267 #endif 268 269 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 270 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 271 #define UWRITE1(sc, r, x) \ 272 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 273 } while (/*CONSTCOND*/0) 274 #define UWRITE2(sc, r, x) \ 275 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 276 } while (/*CONSTCOND*/0) 277 #define UWRITE4(sc, r, x) \ 278 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 279 } while (/*CONSTCOND*/0) 280 static __inline uint8_t 281 UREAD1(uhci_softc_t *sc, bus_size_t r) 282 { 283 284 UBARR(sc); 285 return bus_space_read_1(sc->iot, sc->ioh, r); 286 } 287 288 static __inline uint16_t 289 UREAD2(uhci_softc_t *sc, bus_size_t r) 290 { 291 292 UBARR(sc); 293 return bus_space_read_2(sc->iot, sc->ioh, r); 294 } 295 296 static __inline uint32_t 297 UREAD4(uhci_softc_t *sc, bus_size_t r) 298 { 299 300 UBARR(sc); 301 return bus_space_read_4(sc->iot, sc->ioh, r); 302 } 303 304 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 305 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 306 307 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 308 309 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 310 311 #define UHCI_INTR_ENDPT 1 312 313 const struct usbd_bus_methods uhci_bus_methods = { 314 uhci_open, 315 uhci_softintr, 316 uhci_poll, 317 uhci_allocm, 318 uhci_freem, 319 uhci_allocx, 320 uhci_freex, 321 }; 322 323 const struct usbd_pipe_methods uhci_root_ctrl_methods = { 324 uhci_root_ctrl_transfer, 325 uhci_root_ctrl_start, 326 uhci_root_ctrl_abort, 327 uhci_root_ctrl_close, 328 uhci_noop, 329 uhci_root_ctrl_done, 330 }; 331 332 const struct usbd_pipe_methods uhci_root_intr_methods = { 333 uhci_root_intr_transfer, 334 uhci_root_intr_start, 335 uhci_root_intr_abort, 336 uhci_root_intr_close, 337 uhci_noop, 338 uhci_root_intr_done, 339 }; 340 341 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 342 uhci_device_ctrl_transfer, 343 uhci_device_ctrl_start, 344 uhci_device_ctrl_abort, 345 uhci_device_ctrl_close, 346 uhci_noop, 347 uhci_device_ctrl_done, 348 }; 349 350 const struct usbd_pipe_methods uhci_device_intr_methods = { 351 uhci_device_intr_transfer, 352 uhci_device_intr_start, 353 uhci_device_intr_abort, 354 uhci_device_intr_close, 355 uhci_device_clear_toggle, 356 uhci_device_intr_done, 357 }; 358 359 const struct usbd_pipe_methods uhci_device_bulk_methods = { 360 uhci_device_bulk_transfer, 361 uhci_device_bulk_start, 362 uhci_device_bulk_abort, 363 uhci_device_bulk_close, 364 uhci_device_clear_toggle, 365 uhci_device_bulk_done, 366 }; 367 368 const struct usbd_pipe_methods uhci_device_isoc_methods = { 369 uhci_device_isoc_transfer, 370 uhci_device_isoc_start, 371 uhci_device_isoc_abort, 372 uhci_device_isoc_close, 373 uhci_noop, 374 uhci_device_isoc_done, 375 }; 376 377 #define uhci_add_intr_info(sc, ii) \ 378 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ii), list) 379 #define uhci_del_intr_info(ii) \ 380 do { \ 381 LIST_REMOVE((ii), list); \ 382 (ii)->list.le_prev = NULL; \ 383 } while (0) 384 #define uhci_active_intr_info(ii) ((ii)->list.le_prev != NULL) 385 386 Static inline uhci_soft_qh_t * 387 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 388 { 389 DPRINTFN(15,("uhci_find_prev_qh: pqh=%p sqh=%p\n", pqh, sqh)); 390 391 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 392 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 393 usb_syncmem(&pqh->dma, 394 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 395 sizeof(pqh->qh.qh_hlink), 396 BUS_DMASYNC_POSTWRITE); 397 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 398 printf("uhci_find_prev_qh: QH not found\n"); 399 return (NULL); 400 } 401 #endif 402 } 403 return (pqh); 404 } 405 406 void 407 uhci_globalreset(uhci_softc_t *sc) 408 { 409 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 410 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 411 UHCICMD(sc, 0); /* do nothing */ 412 } 413 414 usbd_status 415 uhci_init(uhci_softc_t *sc) 416 { 417 usbd_status err; 418 int i, j; 419 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 420 uhci_soft_td_t *std; 421 422 DPRINTFN(1,("uhci_init: start\n")); 423 424 #ifdef UHCI_DEBUG 425 thesc = sc; 426 427 if (uhcidebug > 2) 428 uhci_dumpregs(sc); 429 #endif 430 431 sc->sc_suspend = PWR_RESUME; 432 433 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 434 uhci_globalreset(sc); /* reset the controller */ 435 uhci_reset(sc); 436 437 #ifdef __NetBSD__ 438 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 439 USB_MEM_RESERVE); 440 #endif 441 442 /* Allocate and initialize real frame array. */ 443 err = usb_allocmem(&sc->sc_bus, 444 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 445 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 446 if (err) 447 return (err); 448 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 449 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 450 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 451 452 /* 453 * Allocate a TD, inactive, that hangs from the last QH. 454 * This is to avoid a bug in the PIIX that makes it run berserk 455 * otherwise. 456 */ 457 std = uhci_alloc_std(sc); 458 if (std == NULL) 459 return (USBD_NOMEM); 460 std->link.std = NULL; 461 std->td.td_link = htole32(UHCI_PTR_T); 462 std->td.td_status = htole32(0); /* inactive */ 463 std->td.td_token = htole32(0); 464 std->td.td_buffer = htole32(0); 465 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 466 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 467 468 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 469 lsqh = uhci_alloc_sqh(sc); 470 if (lsqh == NULL) 471 return (USBD_NOMEM); 472 lsqh->hlink = NULL; 473 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 474 lsqh->elink = std; 475 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 476 sc->sc_last_qh = lsqh; 477 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 478 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 479 480 /* Allocate the dummy QH where bulk traffic will be queued. */ 481 bsqh = uhci_alloc_sqh(sc); 482 if (bsqh == NULL) 483 return (USBD_NOMEM); 484 bsqh->hlink = lsqh; 485 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 486 bsqh->elink = NULL; 487 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 488 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 489 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 490 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 491 492 /* Allocate dummy QH where high speed control traffic will be queued. */ 493 chsqh = uhci_alloc_sqh(sc); 494 if (chsqh == NULL) 495 return (USBD_NOMEM); 496 chsqh->hlink = bsqh; 497 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 498 chsqh->elink = NULL; 499 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 500 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 501 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 502 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 503 504 /* Allocate dummy QH where control traffic will be queued. */ 505 clsqh = uhci_alloc_sqh(sc); 506 if (clsqh == NULL) 507 return (USBD_NOMEM); 508 clsqh->hlink = chsqh; 509 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 510 clsqh->elink = NULL; 511 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 512 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 513 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 514 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 515 516 /* 517 * Make all (virtual) frame list pointers point to the interrupt 518 * queue heads and the interrupt queue heads at the control 519 * queue head and point the physical frame list to the virtual. 520 */ 521 for(i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 522 std = uhci_alloc_std(sc); 523 sqh = uhci_alloc_sqh(sc); 524 if (std == NULL || sqh == NULL) 525 return (USBD_NOMEM); 526 std->link.sqh = sqh; 527 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 528 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 529 std->td.td_token = htole32(0); 530 std->td.td_buffer = htole32(0); 531 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 532 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 533 sqh->hlink = clsqh; 534 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 535 sqh->elink = NULL; 536 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 537 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 538 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 539 sc->sc_vframes[i].htd = std; 540 sc->sc_vframes[i].etd = std; 541 sc->sc_vframes[i].hqh = sqh; 542 sc->sc_vframes[i].eqh = sqh; 543 for (j = i; 544 j < UHCI_FRAMELIST_COUNT; 545 j += UHCI_VFRAMELIST_COUNT) 546 sc->sc_pframes[j] = htole32(std->physaddr); 547 } 548 usb_syncmem(&sc->sc_dma, 0, 549 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 550 BUS_DMASYNC_PREWRITE); 551 552 553 LIST_INIT(&sc->sc_intrhead); 554 555 SIMPLEQ_INIT(&sc->sc_free_xfers); 556 557 usb_callout_init(sc->sc_poll_handle); 558 559 /* Set up the bus struct. */ 560 sc->sc_bus.methods = &uhci_bus_methods; 561 sc->sc_bus.pipe_size = sizeof(struct uhci_pipe); 562 563 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 564 565 DPRINTFN(1,("uhci_init: enabling\n")); 566 567 err = uhci_run(sc, 1); /* and here we go... */ 568 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 569 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 570 return err; 571 } 572 573 #if defined(__NetBSD__) || defined(__OpenBSD__) 574 int 575 uhci_activate(device_t self, enum devact act) 576 { 577 struct uhci_softc *sc = device_private(self); 578 int rv = 0; 579 580 switch (act) { 581 case DVACT_ACTIVATE: 582 return (EOPNOTSUPP); 583 584 case DVACT_DEACTIVATE: 585 sc->sc_dying = 1; 586 if (sc->sc_child != NULL) 587 rv = config_deactivate(sc->sc_child); 588 break; 589 } 590 return (rv); 591 } 592 593 void 594 uhci_childdet(device_t self, device_t child) 595 { 596 struct uhci_softc *sc = device_private(self); 597 598 KASSERT(sc->sc_child == child); 599 sc->sc_child = NULL; 600 } 601 602 int 603 uhci_detach(struct uhci_softc *sc, int flags) 604 { 605 usbd_xfer_handle xfer; 606 int rv = 0; 607 608 if (sc->sc_child != NULL) 609 rv = config_detach(sc->sc_child, flags); 610 611 if (rv != 0) 612 return (rv); 613 614 /* Free all xfers associated with this HC. */ 615 for (;;) { 616 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 617 if (xfer == NULL) 618 break; 619 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 620 free(xfer, M_USB); 621 } 622 623 callout_halt(&sc->sc_poll_handle, NULL); 624 callout_destroy(&sc->sc_poll_handle); 625 626 /* XXX free other data structures XXX */ 627 628 return (rv); 629 } 630 #endif 631 632 usbd_status 633 uhci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 634 { 635 struct uhci_softc *sc = bus->hci_private; 636 usbd_status status; 637 u_int32_t n; 638 639 /* 640 * XXX 641 * Since we are allocating a buffer we can assume that we will 642 * need TDs for it. Since we don't want to allocate those from 643 * an interrupt context, we allocate them here and free them again. 644 * This is no guarantee that we'll get the TDs next time... 645 */ 646 n = size / 8; 647 if (n > 16) { 648 u_int32_t i; 649 uhci_soft_td_t **stds; 650 DPRINTF(("uhci_allocm: get %d TDs\n", n)); 651 stds = malloc(sizeof(uhci_soft_td_t *) * n, M_TEMP, 652 M_WAITOK|M_ZERO); 653 for(i=0; i < n; i++) 654 stds[i] = uhci_alloc_std(sc); 655 for(i=0; i < n; i++) 656 if (stds[i] != NULL) 657 uhci_free_std(sc, stds[i]); 658 free(stds, M_TEMP); 659 } 660 661 662 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 663 #ifdef __NetBSD__ 664 if (status == USBD_NOMEM) 665 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 666 #endif 667 return status; 668 } 669 670 void 671 uhci_freem(struct usbd_bus *bus, usb_dma_t *dma) 672 { 673 #ifdef __NetBSD__ 674 if (dma->block->flags & USB_DMA_RESERVE) { 675 usb_reserve_freem(&((struct uhci_softc *)bus)->sc_dma_reserve, 676 dma); 677 return; 678 } 679 #endif 680 usb_freemem(&((struct uhci_softc *)bus)->sc_bus, dma); 681 } 682 683 usbd_xfer_handle 684 uhci_allocx(struct usbd_bus *bus) 685 { 686 struct uhci_softc *sc = bus->hci_private; 687 usbd_xfer_handle xfer; 688 689 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 690 if (xfer != NULL) { 691 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 692 #ifdef DIAGNOSTIC 693 if (xfer->busy_free != XFER_FREE) { 694 printf("uhci_allocx: xfer=%p not free, 0x%08x\n", xfer, 695 xfer->busy_free); 696 } 697 #endif 698 } else { 699 xfer = malloc(sizeof(struct uhci_xfer), M_USB, M_NOWAIT); 700 } 701 if (xfer != NULL) { 702 memset(xfer, 0, sizeof (struct uhci_xfer)); 703 UXFER(xfer)->iinfo.sc = sc; 704 #ifdef DIAGNOSTIC 705 UXFER(xfer)->iinfo.isdone = 1; 706 xfer->busy_free = XFER_BUSY; 707 #endif 708 } 709 return (xfer); 710 } 711 712 void 713 uhci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 714 { 715 struct uhci_softc *sc = bus->hci_private; 716 717 #ifdef DIAGNOSTIC 718 if (xfer->busy_free != XFER_BUSY) { 719 printf("uhci_freex: xfer=%p not busy, 0x%08x\n", xfer, 720 xfer->busy_free); 721 } 722 xfer->busy_free = XFER_FREE; 723 if (!UXFER(xfer)->iinfo.isdone) { 724 printf("uhci_freex: !isdone\n"); 725 } 726 #endif 727 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 728 } 729 730 /* 731 * Handle suspend/resume. 732 * 733 * We need to switch to polling mode here, because this routine is 734 * called from an interrupt context. This is all right since we 735 * are almost suspended anyway. 736 */ 737 bool 738 uhci_resume(device_t dv PMF_FN_ARGS) 739 { 740 uhci_softc_t *sc = device_private(dv); 741 int cmd; 742 int s; 743 744 s = splhardusb(); 745 746 cmd = UREAD2(sc, UHCI_CMD); 747 sc->sc_bus.use_polling++; 748 UWRITE2(sc, UHCI_INTR, 0); 749 uhci_globalreset(sc); 750 uhci_reset(sc); 751 if (cmd & UHCI_CMD_RS) 752 uhci_run(sc, 0); 753 754 /* restore saved state */ 755 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 756 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 757 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 758 759 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 760 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 761 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 762 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 763 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 764 UHCICMD(sc, UHCI_CMD_MAXP); 765 uhci_run(sc, 1); /* and start traffic again */ 766 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 767 sc->sc_bus.use_polling--; 768 if (sc->sc_intr_xfer != NULL) 769 usb_callout(sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, 770 sc->sc_intr_xfer); 771 #ifdef UHCI_DEBUG 772 if (uhcidebug > 2) 773 uhci_dumpregs(sc); 774 #endif 775 776 sc->sc_suspend = PWR_RESUME; 777 splx(s); 778 779 return true; 780 } 781 782 bool 783 uhci_suspend(device_t dv PMF_FN_ARGS) 784 { 785 uhci_softc_t *sc = device_private(dv); 786 int cmd; 787 int s; 788 789 s = splhardusb(); 790 791 cmd = UREAD2(sc, UHCI_CMD); 792 793 #ifdef UHCI_DEBUG 794 if (uhcidebug > 2) 795 uhci_dumpregs(sc); 796 #endif 797 if (sc->sc_intr_xfer != NULL) 798 usb_uncallout(sc->sc_poll_handle, uhci_poll_hub, 799 sc->sc_intr_xfer); 800 sc->sc_suspend = PWR_SUSPEND; 801 sc->sc_bus.use_polling++; 802 803 uhci_run(sc, 0); /* stop the controller */ 804 cmd &= ~UHCI_CMD_RS; 805 806 /* save some state if BIOS doesn't */ 807 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 808 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 809 810 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 811 812 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 813 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 814 sc->sc_bus.use_polling--; 815 816 splx(s); 817 818 return true; 819 } 820 821 #ifdef UHCI_DEBUG 822 Static void 823 uhci_dumpregs(uhci_softc_t *sc) 824 { 825 DPRINTFN(-1,("%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, " 826 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 827 device_xname(sc->sc_dev), 828 UREAD2(sc, UHCI_CMD), 829 UREAD2(sc, UHCI_STS), 830 UREAD2(sc, UHCI_INTR), 831 UREAD2(sc, UHCI_FRNUM), 832 UREAD4(sc, UHCI_FLBASEADDR), 833 UREAD1(sc, UHCI_SOF), 834 UREAD2(sc, UHCI_PORTSC1), 835 UREAD2(sc, UHCI_PORTSC2))); 836 } 837 838 void 839 uhci_dump_td(uhci_soft_td_t *p) 840 { 841 char sbuf[128], sbuf2[128]; 842 843 844 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 845 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 846 DPRINTFN(-1,("TD(%p) at %08lx = link=0x%08lx status=0x%08lx " 847 "token=0x%08lx buffer=0x%08lx\n", 848 p, (long)p->physaddr, 849 (long)le32toh(p->td.td_link), 850 (long)le32toh(p->td.td_status), 851 (long)le32toh(p->td.td_token), 852 (long)le32toh(p->td.td_buffer))); 853 854 snprintb(sbuf, sizeof(sbuf), "\20\1T\2Q\3VF", 855 (u_int32_t)le32toh(p->td.td_link)); 856 snprintb(sbuf2, sizeof(sbuf2), 857 "\20\22BITSTUFF\23CRCTO\24NAK\25BABBLE\26DBUFFER\27" 858 "STALLED\30ACTIVE\31IOC\32ISO\33LS\36SPD", 859 (u_int32_t)le32toh(p->td.td_status)); 860 861 DPRINTFN(-1,(" %s %s,errcnt=%d,actlen=%d pid=%02x,addr=%d,endpt=%d," 862 "D=%d,maxlen=%d\n", sbuf, sbuf2, 863 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 864 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 865 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 866 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 867 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 868 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 869 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token)))); 870 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 871 BUS_DMASYNC_PREREAD); 872 } 873 874 void 875 uhci_dump_qh(uhci_soft_qh_t *sqh) 876 { 877 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 878 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 879 DPRINTFN(-1,("QH(%p) at %08x: hlink=%08x elink=%08x\n", sqh, 880 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 881 le32toh(sqh->qh.qh_elink))); 882 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 883 } 884 885 886 #if 1 887 void 888 uhci_dump(void) 889 { 890 uhci_dump_all(thesc); 891 } 892 #endif 893 894 void 895 uhci_dump_all(uhci_softc_t *sc) 896 { 897 uhci_dumpregs(sc); 898 printf("intrs=%d\n", sc->sc_bus.no_intrs); 899 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 900 uhci_dump_qh(sc->sc_lctl_start); 901 } 902 903 904 void 905 uhci_dump_qhs(uhci_soft_qh_t *sqh) 906 { 907 uhci_dump_qh(sqh); 908 909 /* uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 910 * Traverses sideways first, then down. 911 * 912 * QH1 913 * QH2 914 * No QH 915 * TD2.1 916 * TD2.2 917 * TD1.1 918 * etc. 919 * 920 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 921 */ 922 923 924 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 925 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 926 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 927 uhci_dump_qhs(sqh->hlink); 928 else 929 DPRINTF(("No QH\n")); 930 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 931 932 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 933 uhci_dump_tds(sqh->elink); 934 else 935 DPRINTF(("No TD\n")); 936 } 937 938 void 939 uhci_dump_tds(uhci_soft_td_t *std) 940 { 941 uhci_soft_td_t *td; 942 int stop; 943 944 for(td = std; td != NULL; td = td->link.std) { 945 uhci_dump_td(td); 946 947 /* Check whether the link pointer in this TD marks 948 * the link pointer as end of queue. This avoids 949 * printing the free list in case the queue/TD has 950 * already been moved there (seatbelt). 951 */ 952 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 953 sizeof(td->td.td_link), 954 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 955 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 956 le32toh(td->td.td_link) == 0); 957 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 958 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 959 if (stop) 960 break; 961 } 962 } 963 964 Static void 965 uhci_dump_ii(uhci_intr_info_t *ii) 966 { 967 usbd_pipe_handle pipe; 968 usb_endpoint_descriptor_t *ed; 969 usbd_device_handle dev; 970 971 #ifdef DIAGNOSTIC 972 #define DONE ii->isdone 973 #else 974 #define DONE 0 975 #endif 976 if (ii == NULL) { 977 printf("ii NULL\n"); 978 return; 979 } 980 if (ii->xfer == NULL) { 981 printf("ii %p: done=%d xfer=NULL\n", 982 ii, DONE); 983 return; 984 } 985 pipe = ii->xfer->pipe; 986 if (pipe == NULL) { 987 printf("ii %p: done=%d xfer=%p pipe=NULL\n", 988 ii, DONE, ii->xfer); 989 return; 990 } 991 if (pipe->endpoint == NULL) { 992 printf("ii %p: done=%d xfer=%p pipe=%p pipe->endpoint=NULL\n", 993 ii, DONE, ii->xfer, pipe); 994 return; 995 } 996 if (pipe->device == NULL) { 997 printf("ii %p: done=%d xfer=%p pipe=%p pipe->device=NULL\n", 998 ii, DONE, ii->xfer, pipe); 999 return; 1000 } 1001 ed = pipe->endpoint->edesc; 1002 dev = pipe->device; 1003 printf("ii %p: done=%d xfer=%p dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 1004 ii, DONE, ii->xfer, dev, 1005 UGETW(dev->ddesc.idVendor), 1006 UGETW(dev->ddesc.idProduct), 1007 dev->address, pipe, 1008 ed->bEndpointAddress, ed->bmAttributes); 1009 #undef DONE 1010 } 1011 1012 void uhci_dump_iis(struct uhci_softc *sc); 1013 void 1014 uhci_dump_iis(struct uhci_softc *sc) 1015 { 1016 uhci_intr_info_t *ii; 1017 1018 printf("intr_info list:\n"); 1019 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = LIST_NEXT(ii, list)) 1020 uhci_dump_ii(ii); 1021 } 1022 1023 void iidump(void); 1024 void iidump(void) { uhci_dump_iis(thesc); } 1025 1026 #endif 1027 1028 /* 1029 * This routine is executed periodically and simulates interrupts 1030 * from the root controller interrupt pipe for port status change. 1031 */ 1032 void 1033 uhci_poll_hub(void *addr) 1034 { 1035 usbd_xfer_handle xfer = addr; 1036 usbd_pipe_handle pipe = xfer->pipe; 1037 uhci_softc_t *sc; 1038 int s; 1039 u_char *p; 1040 1041 DPRINTFN(20, ("uhci_poll_hub\n")); 1042 1043 if (__predict_false(pipe->device == NULL || pipe->device->bus == NULL)) 1044 return; /* device has detached */ 1045 sc = pipe->device->bus->hci_private; 1046 usb_callout(sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 1047 1048 p = KERNADDR(&xfer->dmabuf, 0); 1049 p[0] = 0; 1050 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1051 p[0] |= 1<<1; 1052 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1053 p[0] |= 1<<2; 1054 if (p[0] == 0) 1055 /* No change, try again in a while */ 1056 return; 1057 1058 xfer->actlen = 1; 1059 xfer->status = USBD_NORMAL_COMPLETION; 1060 s = splusb(); 1061 xfer->device->bus->intr_context++; 1062 usb_transfer_complete(xfer); 1063 xfer->device->bus->intr_context--; 1064 splx(s); 1065 } 1066 1067 void 1068 uhci_root_intr_done(usbd_xfer_handle xfer) 1069 { 1070 } 1071 1072 void 1073 uhci_root_ctrl_done(usbd_xfer_handle xfer) 1074 { 1075 } 1076 1077 /* 1078 * Let the last QH loop back to the high speed control transfer QH. 1079 * This is what intel calls "bandwidth reclamation" and improves 1080 * USB performance a lot for some devices. 1081 * If we are already looping, just count it. 1082 */ 1083 void 1084 uhci_add_loop(uhci_softc_t *sc) { 1085 #ifdef UHCI_DEBUG 1086 if (uhcinoloop) 1087 return; 1088 #endif 1089 if (++sc->sc_loops == 1) { 1090 DPRINTFN(5,("uhci_start_loop: add\n")); 1091 /* Note, we don't loop back the soft pointer. */ 1092 sc->sc_last_qh->qh.qh_hlink = 1093 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 1094 usb_syncmem(&sc->sc_last_qh->dma, 1095 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1096 sizeof(sc->sc_last_qh->qh.qh_hlink), 1097 BUS_DMASYNC_PREWRITE); 1098 } 1099 } 1100 1101 void 1102 uhci_rem_loop(uhci_softc_t *sc) { 1103 #ifdef UHCI_DEBUG 1104 if (uhcinoloop) 1105 return; 1106 #endif 1107 if (--sc->sc_loops == 0) { 1108 DPRINTFN(5,("uhci_end_loop: remove\n")); 1109 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 1110 usb_syncmem(&sc->sc_last_qh->dma, 1111 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1112 sizeof(sc->sc_last_qh->qh.qh_hlink), 1113 BUS_DMASYNC_PREWRITE); 1114 } 1115 } 1116 1117 /* Add high speed control QH, called at splusb(). */ 1118 void 1119 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1120 { 1121 uhci_soft_qh_t *eqh; 1122 1123 SPLUSBCHECK; 1124 1125 DPRINTFN(10, ("uhci_add_ctrl: sqh=%p\n", sqh)); 1126 eqh = sc->sc_hctl_end; 1127 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1128 sizeof(eqh->qh.qh_hlink), 1129 BUS_DMASYNC_POSTWRITE); 1130 sqh->hlink = eqh->hlink; 1131 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1132 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1133 BUS_DMASYNC_PREWRITE); 1134 eqh->hlink = sqh; 1135 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1136 sc->sc_hctl_end = sqh; 1137 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1138 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1139 #ifdef UHCI_CTL_LOOP 1140 uhci_add_loop(sc); 1141 #endif 1142 } 1143 1144 /* Remove high speed control QH, called at splusb(). */ 1145 void 1146 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1147 { 1148 uhci_soft_qh_t *pqh; 1149 1150 SPLUSBCHECK; 1151 1152 DPRINTFN(10, ("uhci_remove_hs_ctrl: sqh=%p\n", sqh)); 1153 #ifdef UHCI_CTL_LOOP 1154 uhci_rem_loop(sc); 1155 #endif 1156 /* 1157 * The T bit should be set in the elink of the QH so that the HC 1158 * doesn't follow the pointer. This condition may fail if the 1159 * the transferred packet was short so that the QH still points 1160 * at the last used TD. 1161 * In this case we set the T bit and wait a little for the HC 1162 * to stop looking at the TD. 1163 * Note that if the TD chain is large enough, the controller 1164 * may still be looking at the chain at the end of this function. 1165 * uhci_free_std_chain() will make sure the controller stops 1166 * looking at it quickly, but until then we should not change 1167 * sqh->hlink. 1168 */ 1169 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1170 sizeof(sqh->qh.qh_elink), 1171 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1172 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1173 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1174 usb_syncmem(&sqh->dma, 1175 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1176 sizeof(sqh->qh.qh_elink), 1177 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1178 delay(UHCI_QH_REMOVE_DELAY); 1179 } 1180 1181 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1182 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1183 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1184 pqh->hlink = sqh->hlink; 1185 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1186 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1187 sizeof(pqh->qh.qh_hlink), 1188 BUS_DMASYNC_PREWRITE); 1189 delay(UHCI_QH_REMOVE_DELAY); 1190 if (sc->sc_hctl_end == sqh) 1191 sc->sc_hctl_end = pqh; 1192 } 1193 1194 /* Add low speed control QH, called at splusb(). */ 1195 void 1196 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1197 { 1198 uhci_soft_qh_t *eqh; 1199 1200 SPLUSBCHECK; 1201 1202 DPRINTFN(10, ("uhci_add_ls_ctrl: sqh=%p\n", sqh)); 1203 eqh = sc->sc_lctl_end; 1204 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1205 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1206 sqh->hlink = eqh->hlink; 1207 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1208 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1209 BUS_DMASYNC_PREWRITE); 1210 eqh->hlink = sqh; 1211 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1212 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1213 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1214 sc->sc_lctl_end = sqh; 1215 } 1216 1217 /* Remove low speed control QH, called at splusb(). */ 1218 void 1219 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1220 { 1221 uhci_soft_qh_t *pqh; 1222 1223 SPLUSBCHECK; 1224 1225 DPRINTFN(10, ("uhci_remove_ls_ctrl: sqh=%p\n", sqh)); 1226 /* See comment in uhci_remove_hs_ctrl() */ 1227 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1228 sizeof(sqh->qh.qh_elink), 1229 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1230 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1231 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1232 usb_syncmem(&sqh->dma, 1233 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1234 sizeof(sqh->qh.qh_elink), 1235 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1236 delay(UHCI_QH_REMOVE_DELAY); 1237 } 1238 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1239 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1240 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1241 pqh->hlink = sqh->hlink; 1242 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1243 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1244 sizeof(pqh->qh.qh_hlink), 1245 BUS_DMASYNC_PREWRITE); 1246 delay(UHCI_QH_REMOVE_DELAY); 1247 if (sc->sc_lctl_end == sqh) 1248 sc->sc_lctl_end = pqh; 1249 } 1250 1251 /* Add bulk QH, called at splusb(). */ 1252 void 1253 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1254 { 1255 uhci_soft_qh_t *eqh; 1256 1257 SPLUSBCHECK; 1258 1259 DPRINTFN(10, ("uhci_add_bulk: sqh=%p\n", sqh)); 1260 eqh = sc->sc_bulk_end; 1261 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1262 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1263 sqh->hlink = eqh->hlink; 1264 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1265 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1266 BUS_DMASYNC_PREWRITE); 1267 eqh->hlink = sqh; 1268 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1269 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1270 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1271 sc->sc_bulk_end = sqh; 1272 uhci_add_loop(sc); 1273 } 1274 1275 /* Remove bulk QH, called at splusb(). */ 1276 void 1277 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1278 { 1279 uhci_soft_qh_t *pqh; 1280 1281 SPLUSBCHECK; 1282 1283 DPRINTFN(10, ("uhci_remove_bulk: sqh=%p\n", sqh)); 1284 uhci_rem_loop(sc); 1285 /* See comment in uhci_remove_hs_ctrl() */ 1286 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1287 sizeof(sqh->qh.qh_elink), 1288 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1289 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1290 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1291 usb_syncmem(&sqh->dma, 1292 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1293 sizeof(sqh->qh.qh_elink), 1294 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1295 delay(UHCI_QH_REMOVE_DELAY); 1296 } 1297 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1298 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1299 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1300 pqh->hlink = sqh->hlink; 1301 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1302 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1303 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1304 delay(UHCI_QH_REMOVE_DELAY); 1305 if (sc->sc_bulk_end == sqh) 1306 sc->sc_bulk_end = pqh; 1307 } 1308 1309 Static int uhci_intr1(uhci_softc_t *); 1310 1311 int 1312 uhci_intr(void *arg) 1313 { 1314 uhci_softc_t *sc = arg; 1315 1316 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1317 return (0); 1318 1319 if (sc->sc_bus.use_polling || UREAD2(sc, UHCI_INTR) == 0) { 1320 #ifdef DIAGNOSTIC 1321 DPRINTFN(16, ("uhci_intr: ignored interrupt while polling\n")); 1322 #endif 1323 return (0); 1324 } 1325 1326 return (uhci_intr1(sc)); 1327 } 1328 1329 int 1330 uhci_intr1(uhci_softc_t *sc) 1331 { 1332 int status; 1333 int ack; 1334 1335 #ifdef UHCI_DEBUG 1336 if (uhcidebug > 15) { 1337 DPRINTF(("%s: uhci_intr1\n", device_xname(sc->sc_dev))); 1338 uhci_dumpregs(sc); 1339 } 1340 #endif 1341 1342 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1343 if (status == 0) /* The interrupt was not for us. */ 1344 return (0); 1345 1346 if (sc->sc_suspend != PWR_RESUME) { 1347 #ifdef DIAGNOSTIC 1348 printf("%s: interrupt while not operating ignored\n", 1349 device_xname(sc->sc_dev)); 1350 #endif 1351 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1352 return (0); 1353 } 1354 1355 ack = 0; 1356 if (status & UHCI_STS_USBINT) 1357 ack |= UHCI_STS_USBINT; 1358 if (status & UHCI_STS_USBEI) 1359 ack |= UHCI_STS_USBEI; 1360 if (status & UHCI_STS_RD) { 1361 ack |= UHCI_STS_RD; 1362 #ifdef UHCI_DEBUG 1363 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1364 #endif 1365 } 1366 if (status & UHCI_STS_HSE) { 1367 ack |= UHCI_STS_HSE; 1368 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1369 } 1370 if (status & UHCI_STS_HCPE) { 1371 ack |= UHCI_STS_HCPE; 1372 printf("%s: host controller process error\n", 1373 device_xname(sc->sc_dev)); 1374 } 1375 if (status & UHCI_STS_HCH) { 1376 /* no acknowledge needed */ 1377 if (!sc->sc_dying) { 1378 printf("%s: host controller halted\n", 1379 device_xname(sc->sc_dev)); 1380 #ifdef UHCI_DEBUG 1381 uhci_dump_all(sc); 1382 #endif 1383 } 1384 sc->sc_dying = 1; 1385 } 1386 1387 if (!ack) 1388 return (0); /* nothing to acknowledge */ 1389 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1390 1391 sc->sc_bus.no_intrs++; 1392 usb_schedsoftintr(&sc->sc_bus); 1393 1394 DPRINTFN(15, ("%s: uhci_intr: exit\n", device_xname(sc->sc_dev))); 1395 1396 return (1); 1397 } 1398 1399 void 1400 uhci_softintr(void *v) 1401 { 1402 struct usbd_bus *bus = v; 1403 uhci_softc_t *sc = bus->hci_private; 1404 uhci_intr_info_t *ii, *nextii; 1405 1406 DPRINTFN(10,("%s: uhci_softintr (%d)\n", device_xname(sc->sc_dev), 1407 sc->sc_bus.intr_context)); 1408 1409 sc->sc_bus.intr_context++; 1410 1411 /* 1412 * Interrupts on UHCI really suck. When the host controller 1413 * interrupts because a transfer is completed there is no 1414 * way of knowing which transfer it was. You can scan down 1415 * the TDs and QHs of the previous frame to limit the search, 1416 * but that assumes that the interrupt was not delayed by more 1417 * than 1 ms, which may not always be true (e.g. after debug 1418 * output on a slow console). 1419 * We scan all interrupt descriptors to see if any have 1420 * completed. 1421 */ 1422 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = nextii) { 1423 nextii = LIST_NEXT(ii, list); 1424 uhci_check_intr(sc, ii); 1425 } 1426 1427 #ifdef USB_USE_SOFTINTR 1428 if (sc->sc_softwake) { 1429 sc->sc_softwake = 0; 1430 wakeup(&sc->sc_softwake); 1431 } 1432 #endif /* USB_USE_SOFTINTR */ 1433 1434 sc->sc_bus.intr_context--; 1435 } 1436 1437 /* Check for an interrupt. */ 1438 void 1439 uhci_check_intr(uhci_softc_t *sc, uhci_intr_info_t *ii) 1440 { 1441 uhci_soft_td_t *std, *lstd; 1442 u_int32_t status; 1443 1444 DPRINTFN(15, ("uhci_check_intr: ii=%p\n", ii)); 1445 #ifdef DIAGNOSTIC 1446 if (ii == NULL) { 1447 printf("uhci_check_intr: no ii? %p\n", ii); 1448 return; 1449 } 1450 #endif 1451 if (ii->xfer->status == USBD_CANCELLED || 1452 ii->xfer->status == USBD_TIMEOUT) { 1453 DPRINTF(("uhci_check_intr: aborted xfer=%p\n", ii->xfer)); 1454 return; 1455 } 1456 1457 if (ii->stdstart == NULL) 1458 return; 1459 lstd = ii->stdend; 1460 #ifdef DIAGNOSTIC 1461 if (lstd == NULL) { 1462 printf("uhci_check_intr: std==0\n"); 1463 return; 1464 } 1465 #endif 1466 /* 1467 * If the last TD is still active we need to check whether there 1468 * is an error somewhere in the middle, or whether there was a 1469 * short packet (SPD and not ACTIVE). 1470 */ 1471 usb_syncmem(&lstd->dma, 1472 lstd->offs + offsetof(uhci_td_t, td_status), 1473 sizeof(lstd->td.td_status), 1474 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1475 if (le32toh(lstd->td.td_status) & UHCI_TD_ACTIVE) { 1476 DPRINTFN(12, ("uhci_check_intr: active ii=%p\n", ii)); 1477 for (std = ii->stdstart; std != lstd; std = std->link.std) { 1478 usb_syncmem(&std->dma, 1479 std->offs + offsetof(uhci_td_t, td_status), 1480 sizeof(std->td.td_status), 1481 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1482 status = le32toh(std->td.td_status); 1483 usb_syncmem(&std->dma, 1484 std->offs + offsetof(uhci_td_t, td_status), 1485 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1486 /* If there's an active TD the xfer isn't done. */ 1487 if (status & UHCI_TD_ACTIVE) 1488 break; 1489 /* Any kind of error makes the xfer done. */ 1490 if (status & UHCI_TD_STALLED) 1491 goto done; 1492 /* We want short packets, and it is short: it's done */ 1493 usb_syncmem(&std->dma, 1494 std->offs + offsetof(uhci_td_t, td_token), 1495 sizeof(std->td.td_token), 1496 BUS_DMASYNC_POSTWRITE); 1497 if ((status & UHCI_TD_SPD) && 1498 UHCI_TD_GET_ACTLEN(status) < 1499 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) 1500 goto done; 1501 } 1502 DPRINTFN(12, ("uhci_check_intr: ii=%p std=%p still active\n", 1503 ii, ii->stdstart)); 1504 usb_syncmem(&lstd->dma, 1505 lstd->offs + offsetof(uhci_td_t, td_status), 1506 sizeof(lstd->td.td_status), 1507 BUS_DMASYNC_PREREAD); 1508 return; 1509 } 1510 done: 1511 DPRINTFN(12, ("uhci_check_intr: ii=%p done\n", ii)); 1512 usb_uncallout(ii->xfer->timeout_handle, uhci_timeout, ii); 1513 uhci_idone(ii); 1514 } 1515 1516 /* Called at splusb() */ 1517 void 1518 uhci_idone(uhci_intr_info_t *ii) 1519 { 1520 usbd_xfer_handle xfer = ii->xfer; 1521 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 1522 uhci_soft_td_t *std; 1523 u_int32_t status = 0, nstatus; 1524 int actlen; 1525 1526 DPRINTFN(12, ("uhci_idone: ii=%p\n", ii)); 1527 #ifdef DIAGNOSTIC 1528 { 1529 int s = splhigh(); 1530 if (ii->isdone) { 1531 splx(s); 1532 #ifdef UHCI_DEBUG 1533 printf("uhci_idone: ii is done!\n "); 1534 uhci_dump_ii(ii); 1535 #else 1536 printf("uhci_idone: ii=%p is done!\n", ii); 1537 #endif 1538 return; 1539 } 1540 ii->isdone = 1; 1541 splx(s); 1542 } 1543 #endif 1544 1545 if (xfer->nframes != 0) { 1546 /* Isoc transfer, do things differently. */ 1547 uhci_soft_td_t **stds = upipe->u.iso.stds; 1548 int i, n, nframes, len; 1549 1550 DPRINTFN(5,("uhci_idone: ii=%p isoc ready\n", ii)); 1551 1552 nframes = xfer->nframes; 1553 actlen = 0; 1554 n = UXFER(xfer)->curframe; 1555 for (i = 0; i < nframes; i++) { 1556 std = stds[n]; 1557 #ifdef UHCI_DEBUG 1558 if (uhcidebug > 5) { 1559 DPRINTFN(-1,("uhci_idone: isoc TD %d\n", i)); 1560 uhci_dump_td(std); 1561 } 1562 #endif 1563 if (++n >= UHCI_VFRAMELIST_COUNT) 1564 n = 0; 1565 usb_syncmem(&std->dma, 1566 std->offs + offsetof(uhci_td_t, td_status), 1567 sizeof(std->td.td_status), 1568 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1569 status = le32toh(std->td.td_status); 1570 len = UHCI_TD_GET_ACTLEN(status); 1571 xfer->frlengths[i] = len; 1572 actlen += len; 1573 } 1574 upipe->u.iso.inuse -= nframes; 1575 xfer->actlen = actlen; 1576 xfer->status = USBD_NORMAL_COMPLETION; 1577 goto end; 1578 } 1579 1580 #ifdef UHCI_DEBUG 1581 DPRINTFN(10, ("uhci_idone: ii=%p, xfer=%p, pipe=%p ready\n", 1582 ii, xfer, upipe)); 1583 if (uhcidebug > 10) 1584 uhci_dump_tds(ii->stdstart); 1585 #endif 1586 1587 /* The transfer is done, compute actual length and status. */ 1588 actlen = 0; 1589 for (std = ii->stdstart; std != NULL; std = std->link.std) { 1590 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1591 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1592 nstatus = le32toh(std->td.td_status); 1593 if (nstatus & UHCI_TD_ACTIVE) 1594 break; 1595 1596 status = nstatus; 1597 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1598 UHCI_TD_PID_SETUP) 1599 actlen += UHCI_TD_GET_ACTLEN(status); 1600 else { 1601 /* 1602 * UHCI will report CRCTO in addition to a STALL or NAK 1603 * for a SETUP transaction. See section 3.2.2, "TD 1604 * CONTROL AND STATUS". 1605 */ 1606 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1607 status &= ~UHCI_TD_CRCTO; 1608 } 1609 } 1610 /* If there are left over TDs we need to update the toggle. */ 1611 if (std != NULL) 1612 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1613 1614 status &= UHCI_TD_ERROR; 1615 DPRINTFN(10, ("uhci_idone: actlen=%d, status=0x%x\n", 1616 actlen, status)); 1617 xfer->actlen = actlen; 1618 if (status != 0) { 1619 #ifdef UHCI_DEBUG 1620 char sbuf[128]; 1621 1622 snprintb(sbuf, sizeof(sbuf), 1623 "\20\22BITSTUFF\23CRCTO\24NAK\25" 1624 "BABBLE\26DBUFFER\27STALLED\30ACTIVE",(u_int32_t)status); 1625 1626 DPRINTFN((status == UHCI_TD_STALLED)*10, 1627 ("uhci_idone: error, addr=%d, endpt=0x%02x, " 1628 "status 0x%s\n", 1629 xfer->pipe->device->address, 1630 xfer->pipe->endpoint->edesc->bEndpointAddress, 1631 sbuf)); 1632 #endif 1633 1634 if (status == UHCI_TD_STALLED) 1635 xfer->status = USBD_STALLED; 1636 else 1637 xfer->status = USBD_IOERROR; /* more info XXX */ 1638 } else { 1639 xfer->status = USBD_NORMAL_COMPLETION; 1640 } 1641 1642 end: 1643 usb_transfer_complete(xfer); 1644 DPRINTFN(12, ("uhci_idone: ii=%p done\n", ii)); 1645 } 1646 1647 /* 1648 * Called when a request does not complete. 1649 */ 1650 void 1651 uhci_timeout(void *addr) 1652 { 1653 uhci_intr_info_t *ii = addr; 1654 struct uhci_xfer *uxfer = UXFER(ii->xfer); 1655 struct uhci_pipe *upipe = (struct uhci_pipe *)uxfer->xfer.pipe; 1656 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 1657 1658 DPRINTF(("uhci_timeout: uxfer=%p\n", uxfer)); 1659 1660 if (sc->sc_dying) { 1661 uhci_abort_xfer(&uxfer->xfer, USBD_TIMEOUT); 1662 return; 1663 } 1664 1665 /* Execute the abort in a process context. */ 1666 usb_init_task(&uxfer->abort_task, uhci_timeout_task, ii->xfer); 1667 usb_add_task(uxfer->xfer.pipe->device, &uxfer->abort_task, 1668 USB_TASKQ_HC); 1669 } 1670 1671 void 1672 uhci_timeout_task(void *addr) 1673 { 1674 usbd_xfer_handle xfer = addr; 1675 int s; 1676 1677 DPRINTF(("uhci_timeout_task: xfer=%p\n", xfer)); 1678 1679 s = splusb(); 1680 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1681 splx(s); 1682 } 1683 1684 /* 1685 * Wait here until controller claims to have an interrupt. 1686 * Then call uhci_intr and return. Use timeout to avoid waiting 1687 * too long. 1688 * Only used during boot when interrupts are not enabled yet. 1689 */ 1690 void 1691 uhci_waitintr(uhci_softc_t *sc, usbd_xfer_handle xfer) 1692 { 1693 int timo = xfer->timeout; 1694 uhci_intr_info_t *ii; 1695 1696 DPRINTFN(10,("uhci_waitintr: timeout = %dms\n", timo)); 1697 1698 xfer->status = USBD_IN_PROGRESS; 1699 for (; timo >= 0; timo--) { 1700 usb_delay_ms(&sc->sc_bus, 1); 1701 DPRINTFN(20,("uhci_waitintr: 0x%04x\n", UREAD2(sc, UHCI_STS))); 1702 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1703 uhci_intr1(sc); 1704 if (xfer->status != USBD_IN_PROGRESS) 1705 return; 1706 } 1707 } 1708 1709 /* Timeout */ 1710 DPRINTF(("uhci_waitintr: timeout\n")); 1711 for (ii = LIST_FIRST(&sc->sc_intrhead); 1712 ii != NULL && ii->xfer != xfer; 1713 ii = LIST_NEXT(ii, list)) 1714 ; 1715 #ifdef DIAGNOSTIC 1716 if (ii == NULL) 1717 panic("uhci_waitintr: lost intr_info"); 1718 #endif 1719 uhci_idone(ii); 1720 } 1721 1722 void 1723 uhci_poll(struct usbd_bus *bus) 1724 { 1725 uhci_softc_t *sc = bus->hci_private; 1726 1727 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) 1728 uhci_intr1(sc); 1729 } 1730 1731 void 1732 uhci_reset(uhci_softc_t *sc) 1733 { 1734 int n; 1735 1736 UHCICMD(sc, UHCI_CMD_HCRESET); 1737 /* The reset bit goes low when the controller is done. */ 1738 for (n = 0; n < UHCI_RESET_TIMEOUT && 1739 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1740 usb_delay_ms(&sc->sc_bus, 1); 1741 if (n >= UHCI_RESET_TIMEOUT) 1742 printf("%s: controller did not reset\n", 1743 device_xname(sc->sc_dev)); 1744 } 1745 1746 usbd_status 1747 uhci_run(uhci_softc_t *sc, int run) 1748 { 1749 int s, n, running; 1750 u_int16_t cmd; 1751 1752 run = run != 0; 1753 s = splhardusb(); 1754 DPRINTF(("uhci_run: setting run=%d\n", run)); 1755 cmd = UREAD2(sc, UHCI_CMD); 1756 if (run) 1757 cmd |= UHCI_CMD_RS; 1758 else 1759 cmd &= ~UHCI_CMD_RS; 1760 UHCICMD(sc, cmd); 1761 for(n = 0; n < 10; n++) { 1762 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1763 /* return when we've entered the state we want */ 1764 if (run == running) { 1765 splx(s); 1766 DPRINTF(("uhci_run: done cmd=0x%x sts=0x%x\n", 1767 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS))); 1768 return (USBD_NORMAL_COMPLETION); 1769 } 1770 usb_delay_ms(&sc->sc_bus, 1); 1771 } 1772 splx(s); 1773 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1774 run ? "start" : "stop"); 1775 return (USBD_IOERROR); 1776 } 1777 1778 /* 1779 * Memory management routines. 1780 * uhci_alloc_std allocates TDs 1781 * uhci_alloc_sqh allocates QHs 1782 * These two routines do their own free list management, 1783 * partly for speed, partly because allocating DMAable memory 1784 * has page size granularaity so much memory would be wasted if 1785 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1786 */ 1787 1788 uhci_soft_td_t * 1789 uhci_alloc_std(uhci_softc_t *sc) 1790 { 1791 uhci_soft_td_t *std; 1792 usbd_status err; 1793 int i, offs; 1794 usb_dma_t dma; 1795 1796 if (sc->sc_freetds == NULL) { 1797 DPRINTFN(2,("uhci_alloc_std: allocating chunk\n")); 1798 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1799 UHCI_TD_ALIGN, &dma); 1800 if (err) 1801 return (0); 1802 for(i = 0; i < UHCI_STD_CHUNK; i++) { 1803 offs = i * UHCI_STD_SIZE; 1804 std = KERNADDR(&dma, offs); 1805 std->physaddr = DMAADDR(&dma, offs); 1806 std->dma = dma; 1807 std->offs = offs; 1808 std->link.std = sc->sc_freetds; 1809 sc->sc_freetds = std; 1810 } 1811 } 1812 std = sc->sc_freetds; 1813 sc->sc_freetds = std->link.std; 1814 memset(&std->td, 0, sizeof(uhci_td_t)); 1815 return std; 1816 } 1817 1818 void 1819 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1820 { 1821 #ifdef DIAGNOSTIC 1822 #define TD_IS_FREE 0x12345678 1823 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1824 printf("uhci_free_std: freeing free TD %p\n", std); 1825 return; 1826 } 1827 std->td.td_token = htole32(TD_IS_FREE); 1828 #endif 1829 std->link.std = sc->sc_freetds; 1830 sc->sc_freetds = std; 1831 } 1832 1833 uhci_soft_qh_t * 1834 uhci_alloc_sqh(uhci_softc_t *sc) 1835 { 1836 uhci_soft_qh_t *sqh; 1837 usbd_status err; 1838 int i, offs; 1839 usb_dma_t dma; 1840 1841 if (sc->sc_freeqhs == NULL) { 1842 DPRINTFN(2, ("uhci_alloc_sqh: allocating chunk\n")); 1843 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1844 UHCI_QH_ALIGN, &dma); 1845 if (err) 1846 return (0); 1847 for(i = 0; i < UHCI_SQH_CHUNK; i++) { 1848 offs = i * UHCI_SQH_SIZE; 1849 sqh = KERNADDR(&dma, offs); 1850 sqh->physaddr = DMAADDR(&dma, offs); 1851 sqh->dma = dma; 1852 sqh->offs = offs; 1853 sqh->hlink = sc->sc_freeqhs; 1854 sc->sc_freeqhs = sqh; 1855 } 1856 } 1857 sqh = sc->sc_freeqhs; 1858 sc->sc_freeqhs = sqh->hlink; 1859 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1860 return (sqh); 1861 } 1862 1863 void 1864 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1865 { 1866 sqh->hlink = sc->sc_freeqhs; 1867 sc->sc_freeqhs = sqh; 1868 } 1869 1870 void 1871 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1872 uhci_soft_td_t *stdend) 1873 { 1874 uhci_soft_td_t *p; 1875 1876 /* 1877 * to avoid race condition with the controller which may be looking 1878 * at this chain, we need to first invalidate all links, and 1879 * then wait for the controller to move to another queue 1880 */ 1881 for (p = std; p != stdend; p = p->link.std) { 1882 usb_syncmem(&p->dma, 1883 p->offs + offsetof(uhci_td_t, td_link), 1884 sizeof(p->td.td_link), 1885 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1886 if ((p->td.td_link & UHCI_PTR_T) == 0) { 1887 p->td.td_link = UHCI_PTR_T; 1888 usb_syncmem(&p->dma, 1889 p->offs + offsetof(uhci_td_t, td_link), 1890 sizeof(p->td.td_link), 1891 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1892 } 1893 } 1894 delay(UHCI_QH_REMOVE_DELAY); 1895 1896 for (; std != stdend; std = p) { 1897 p = std->link.std; 1898 uhci_free_std(sc, std); 1899 } 1900 } 1901 1902 usbd_status 1903 uhci_alloc_std_chain(struct uhci_pipe *upipe, uhci_softc_t *sc, int len, 1904 int rd, u_int16_t flags, usb_dma_t *dma, 1905 uhci_soft_td_t **sp, uhci_soft_td_t **ep) 1906 { 1907 uhci_soft_td_t *p, *lastp; 1908 uhci_physaddr_t lastlink; 1909 int i, ntd, l, tog, maxp; 1910 u_int32_t status; 1911 int addr = upipe->pipe.device->address; 1912 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 1913 1914 DPRINTFN(8, ("uhci_alloc_std_chain: addr=%d endpt=%d len=%d speed=%d " 1915 "flags=0x%x\n", addr, UE_GET_ADDR(endpt), len, 1916 upipe->pipe.device->speed, flags)); 1917 maxp = UGETW(upipe->pipe.endpoint->edesc->wMaxPacketSize); 1918 if (maxp == 0) { 1919 printf("uhci_alloc_std_chain: maxp=0\n"); 1920 return (USBD_INVAL); 1921 } 1922 ntd = (len + maxp - 1) / maxp; 1923 if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0) 1924 ntd++; 1925 DPRINTFN(10, ("uhci_alloc_std_chain: maxp=%d ntd=%d\n", maxp, ntd)); 1926 if (ntd == 0) { 1927 *sp = *ep = 0; 1928 DPRINTFN(-1,("uhci_alloc_std_chain: ntd=0\n")); 1929 return (USBD_NORMAL_COMPLETION); 1930 } 1931 tog = upipe->nexttoggle; 1932 if (ntd % 2 == 0) 1933 tog ^= 1; 1934 upipe->nexttoggle = tog ^ 1; 1935 lastp = NULL; 1936 lastlink = UHCI_PTR_T; 1937 ntd--; 1938 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 1939 if (upipe->pipe.device->speed == USB_SPEED_LOW) 1940 status |= UHCI_TD_LS; 1941 if (flags & USBD_SHORT_XFER_OK) 1942 status |= UHCI_TD_SPD; 1943 usb_syncmem(dma, 0, len, 1944 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1945 for (i = ntd; i >= 0; i--) { 1946 p = uhci_alloc_std(sc); 1947 if (p == NULL) { 1948 KASSERT(lastp != NULL); 1949 uhci_free_std_chain(sc, lastp, NULL); 1950 return (USBD_NOMEM); 1951 } 1952 p->link.std = lastp; 1953 p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD); 1954 lastp = p; 1955 lastlink = p->physaddr; 1956 p->td.td_status = htole32(status); 1957 if (i == ntd) { 1958 /* last TD */ 1959 l = len % maxp; 1960 if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER)) 1961 l = maxp; 1962 *ep = p; 1963 } else 1964 l = maxp; 1965 p->td.td_token = 1966 htole32(rd ? UHCI_TD_IN (l, endpt, addr, tog) : 1967 UHCI_TD_OUT(l, endpt, addr, tog)); 1968 p->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 1969 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 1970 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1971 tog ^= 1; 1972 } 1973 *sp = lastp; 1974 DPRINTFN(10, ("uhci_alloc_std_chain: nexttog=%d\n", 1975 upipe->nexttoggle)); 1976 return (USBD_NORMAL_COMPLETION); 1977 } 1978 1979 void 1980 uhci_device_clear_toggle(usbd_pipe_handle pipe) 1981 { 1982 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 1983 upipe->nexttoggle = 0; 1984 } 1985 1986 void 1987 uhci_noop(usbd_pipe_handle pipe) 1988 { 1989 } 1990 1991 usbd_status 1992 uhci_device_bulk_transfer(usbd_xfer_handle xfer) 1993 { 1994 usbd_status err; 1995 1996 /* Insert last in queue. */ 1997 err = usb_insert_transfer(xfer); 1998 if (err) 1999 return (err); 2000 2001 /* 2002 * Pipe isn't running (otherwise err would be USBD_INPROG), 2003 * so start it first. 2004 */ 2005 return (uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2006 } 2007 2008 usbd_status 2009 uhci_device_bulk_start(usbd_xfer_handle xfer) 2010 { 2011 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2012 usbd_device_handle dev = upipe->pipe.device; 2013 uhci_softc_t *sc = dev->bus->hci_private; 2014 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2015 uhci_soft_td_t *data, *dataend; 2016 uhci_soft_qh_t *sqh; 2017 usbd_status err; 2018 int len, isread, endpt; 2019 int s; 2020 2021 DPRINTFN(3, ("uhci_device_bulk_start: xfer=%p len=%d flags=%d ii=%p\n", 2022 xfer, xfer->length, xfer->flags, ii)); 2023 2024 if (sc->sc_dying) 2025 return (USBD_IOERROR); 2026 2027 #ifdef DIAGNOSTIC 2028 if (xfer->rqflags & URQ_REQUEST) 2029 panic("uhci_device_bulk_transfer: a request"); 2030 #endif 2031 2032 len = xfer->length; 2033 endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2034 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2035 sqh = upipe->u.bulk.sqh; 2036 2037 upipe->u.bulk.isread = isread; 2038 upipe->u.bulk.length = len; 2039 2040 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->flags, 2041 &xfer->dmabuf, &data, &dataend); 2042 if (err) 2043 return (err); 2044 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2045 usb_syncmem(&dataend->dma, 2046 dataend->offs + offsetof(uhci_td_t, td_status), 2047 sizeof(dataend->td.td_status), 2048 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2049 2050 2051 #ifdef UHCI_DEBUG 2052 if (uhcidebug > 8) { 2053 DPRINTF(("uhci_device_bulk_transfer: data(1)\n")); 2054 uhci_dump_tds(data); 2055 } 2056 #endif 2057 2058 /* Set up interrupt info. */ 2059 ii->xfer = xfer; 2060 ii->stdstart = data; 2061 ii->stdend = dataend; 2062 #ifdef DIAGNOSTIC 2063 if (!ii->isdone) { 2064 printf("uhci_device_bulk_transfer: not done, ii=%p\n", ii); 2065 } 2066 ii->isdone = 0; 2067 #endif 2068 2069 sqh->elink = data; 2070 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2071 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2072 2073 s = splusb(); 2074 uhci_add_bulk(sc, sqh); 2075 uhci_add_intr_info(sc, ii); 2076 2077 if (xfer->timeout && !sc->sc_bus.use_polling) { 2078 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 2079 uhci_timeout, ii); 2080 } 2081 xfer->status = USBD_IN_PROGRESS; 2082 splx(s); 2083 2084 #ifdef UHCI_DEBUG 2085 if (uhcidebug > 10) { 2086 DPRINTF(("uhci_device_bulk_transfer: data(2)\n")); 2087 uhci_dump_tds(data); 2088 } 2089 #endif 2090 2091 if (sc->sc_bus.use_polling) 2092 uhci_waitintr(sc, xfer); 2093 2094 return (USBD_IN_PROGRESS); 2095 } 2096 2097 /* Abort a device bulk request. */ 2098 void 2099 uhci_device_bulk_abort(usbd_xfer_handle xfer) 2100 { 2101 DPRINTF(("uhci_device_bulk_abort:\n")); 2102 uhci_abort_xfer(xfer, USBD_CANCELLED); 2103 } 2104 2105 /* 2106 * Abort a device request. 2107 * If this routine is called at splusb() it guarantees that the request 2108 * will be removed from the hardware scheduling and that the callback 2109 * for it will be called with USBD_CANCELLED status. 2110 * It's impossible to guarantee that the requested transfer will not 2111 * have happened since the hardware runs concurrently. 2112 * If the transaction has already happened we rely on the ordinary 2113 * interrupt processing to process it. 2114 */ 2115 void 2116 uhci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2117 { 2118 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2119 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2120 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 2121 uhci_soft_td_t *std; 2122 int s; 2123 int wake; 2124 2125 DPRINTFN(1,("uhci_abort_xfer: xfer=%p, status=%d\n", xfer, status)); 2126 2127 if (sc->sc_dying) { 2128 /* If we're dying, just do the software part. */ 2129 s = splusb(); 2130 xfer->status = status; /* make software ignore it */ 2131 usb_uncallout(xfer->timeout_handle, uhci_timeout, xfer); 2132 usb_transfer_complete(xfer); 2133 splx(s); 2134 return; 2135 } 2136 2137 if (xfer->device->bus->intr_context || !curproc) 2138 panic("uhci_abort_xfer: not in process context"); 2139 2140 /* 2141 * If an abort is already in progress then just wait for it to 2142 * complete and return. 2143 */ 2144 if (xfer->hcflags & UXFER_ABORTING) { 2145 DPRINTFN(2, ("uhci_abort_xfer: already aborting\n")); 2146 #ifdef DIAGNOSTIC 2147 if (status == USBD_TIMEOUT) 2148 printf("uhci_abort_xfer: TIMEOUT while aborting\n"); 2149 #endif 2150 /* Override the status which might be USBD_TIMEOUT. */ 2151 xfer->status = status; 2152 DPRINTFN(2, ("uhci_abort_xfer: waiting for abort to finish\n")); 2153 xfer->hcflags |= UXFER_ABORTWAIT; 2154 while (xfer->hcflags & UXFER_ABORTING) 2155 tsleep(&xfer->hcflags, PZERO, "uhciaw", 0); 2156 return; 2157 } 2158 xfer->hcflags |= UXFER_ABORTING; 2159 2160 /* 2161 * Step 1: Make interrupt routine and hardware ignore xfer. 2162 */ 2163 s = splusb(); 2164 xfer->status = status; /* make software ignore it */ 2165 usb_uncallout(xfer->timeout_handle, uhci_timeout, ii); 2166 DPRINTFN(1,("uhci_abort_xfer: stop ii=%p\n", ii)); 2167 for (std = ii->stdstart; std != NULL; std = std->link.std) { 2168 usb_syncmem(&std->dma, 2169 std->offs + offsetof(uhci_td_t, td_status), 2170 sizeof(std->td.td_status), 2171 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2172 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2173 usb_syncmem(&std->dma, 2174 std->offs + offsetof(uhci_td_t, td_status), 2175 sizeof(std->td.td_status), 2176 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2177 } 2178 splx(s); 2179 2180 /* 2181 * Step 2: Wait until we know hardware has finished any possible 2182 * use of the xfer. Also make sure the soft interrupt routine 2183 * has run. 2184 */ 2185 usb_delay_ms(upipe->pipe.device->bus, 2); /* Hardware finishes in 1ms */ 2186 s = splusb(); 2187 #ifdef USB_USE_SOFTINTR 2188 sc->sc_softwake = 1; 2189 #endif /* USB_USE_SOFTINTR */ 2190 usb_schedsoftintr(&sc->sc_bus); 2191 #ifdef USB_USE_SOFTINTR 2192 DPRINTFN(1,("uhci_abort_xfer: tsleep\n")); 2193 tsleep(&sc->sc_softwake, PZERO, "uhciab", 0); 2194 #endif /* USB_USE_SOFTINTR */ 2195 splx(s); 2196 2197 /* 2198 * Step 3: Execute callback. 2199 */ 2200 DPRINTFN(1,("uhci_abort_xfer: callback\n")); 2201 s = splusb(); 2202 #ifdef DIAGNOSTIC 2203 ii->isdone = 1; 2204 #endif 2205 wake = xfer->hcflags & UXFER_ABORTWAIT; 2206 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2207 usb_transfer_complete(xfer); 2208 if (wake) 2209 wakeup(&xfer->hcflags); 2210 splx(s); 2211 } 2212 2213 /* Close a device bulk pipe. */ 2214 void 2215 uhci_device_bulk_close(usbd_pipe_handle pipe) 2216 { 2217 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2218 usbd_device_handle dev = upipe->pipe.device; 2219 uhci_softc_t *sc = dev->bus->hci_private; 2220 2221 uhci_free_sqh(sc, upipe->u.bulk.sqh); 2222 } 2223 2224 usbd_status 2225 uhci_device_ctrl_transfer(usbd_xfer_handle xfer) 2226 { 2227 usbd_status err; 2228 2229 /* Insert last in queue. */ 2230 err = usb_insert_transfer(xfer); 2231 if (err) 2232 return (err); 2233 2234 /* 2235 * Pipe isn't running (otherwise err would be USBD_INPROG), 2236 * so start it first. 2237 */ 2238 return (uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2239 } 2240 2241 usbd_status 2242 uhci_device_ctrl_start(usbd_xfer_handle xfer) 2243 { 2244 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2245 usbd_status err; 2246 2247 if (sc->sc_dying) 2248 return (USBD_IOERROR); 2249 2250 #ifdef DIAGNOSTIC 2251 if (!(xfer->rqflags & URQ_REQUEST)) 2252 panic("uhci_device_ctrl_transfer: not a request"); 2253 #endif 2254 2255 err = uhci_device_request(xfer); 2256 if (err) 2257 return (err); 2258 2259 if (sc->sc_bus.use_polling) 2260 uhci_waitintr(sc, xfer); 2261 return (USBD_IN_PROGRESS); 2262 } 2263 2264 usbd_status 2265 uhci_device_intr_transfer(usbd_xfer_handle xfer) 2266 { 2267 usbd_status err; 2268 2269 /* Insert last in queue. */ 2270 err = usb_insert_transfer(xfer); 2271 if (err) 2272 return (err); 2273 2274 /* 2275 * Pipe isn't running (otherwise err would be USBD_INPROG), 2276 * so start it first. 2277 */ 2278 return (uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2279 } 2280 2281 usbd_status 2282 uhci_device_intr_start(usbd_xfer_handle xfer) 2283 { 2284 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2285 usbd_device_handle dev = upipe->pipe.device; 2286 uhci_softc_t *sc = dev->bus->hci_private; 2287 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2288 uhci_soft_td_t *data, *dataend; 2289 uhci_soft_qh_t *sqh; 2290 usbd_status err; 2291 int isread, endpt; 2292 int i, s; 2293 2294 if (sc->sc_dying) 2295 return (USBD_IOERROR); 2296 2297 DPRINTFN(3,("uhci_device_intr_transfer: xfer=%p len=%d flags=%d\n", 2298 xfer, xfer->length, xfer->flags)); 2299 2300 #ifdef DIAGNOSTIC 2301 if (xfer->rqflags & URQ_REQUEST) 2302 panic("uhci_device_intr_transfer: a request"); 2303 #endif 2304 2305 endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2306 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2307 2308 upipe->u.intr.isread = isread; 2309 2310 err = uhci_alloc_std_chain(upipe, sc, xfer->length, isread, 2311 xfer->flags, &xfer->dmabuf, &data, 2312 &dataend); 2313 if (err) 2314 return (err); 2315 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2316 usb_syncmem(&dataend->dma, 2317 dataend->offs + offsetof(uhci_td_t, td_status), 2318 sizeof(dataend->td.td_status), 2319 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2320 2321 #ifdef UHCI_DEBUG 2322 if (uhcidebug > 10) { 2323 DPRINTF(("uhci_device_intr_transfer: data(1)\n")); 2324 uhci_dump_tds(data); 2325 uhci_dump_qh(upipe->u.intr.qhs[0]); 2326 } 2327 #endif 2328 2329 s = splusb(); 2330 /* Set up interrupt info. */ 2331 ii->xfer = xfer; 2332 ii->stdstart = data; 2333 ii->stdend = dataend; 2334 #ifdef DIAGNOSTIC 2335 if (!ii->isdone) { 2336 printf("uhci_device_intr_transfer: not done, ii=%p\n", ii); 2337 } 2338 ii->isdone = 0; 2339 #endif 2340 2341 DPRINTFN(10,("uhci_device_intr_transfer: qhs[0]=%p\n", 2342 upipe->u.intr.qhs[0])); 2343 for (i = 0; i < upipe->u.intr.npoll; i++) { 2344 sqh = upipe->u.intr.qhs[i]; 2345 sqh->elink = data; 2346 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2347 usb_syncmem(&sqh->dma, 2348 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2349 sizeof(sqh->qh.qh_elink), 2350 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2351 } 2352 uhci_add_intr_info(sc, ii); 2353 xfer->status = USBD_IN_PROGRESS; 2354 splx(s); 2355 2356 #ifdef UHCI_DEBUG 2357 if (uhcidebug > 10) { 2358 DPRINTF(("uhci_device_intr_transfer: data(2)\n")); 2359 uhci_dump_tds(data); 2360 uhci_dump_qh(upipe->u.intr.qhs[0]); 2361 } 2362 #endif 2363 2364 return (USBD_IN_PROGRESS); 2365 } 2366 2367 /* Abort a device control request. */ 2368 void 2369 uhci_device_ctrl_abort(usbd_xfer_handle xfer) 2370 { 2371 DPRINTF(("uhci_device_ctrl_abort:\n")); 2372 uhci_abort_xfer(xfer, USBD_CANCELLED); 2373 } 2374 2375 /* Close a device control pipe. */ 2376 void 2377 uhci_device_ctrl_close(usbd_pipe_handle pipe) 2378 { 2379 } 2380 2381 /* Abort a device interrupt request. */ 2382 void 2383 uhci_device_intr_abort(usbd_xfer_handle xfer) 2384 { 2385 DPRINTFN(1,("uhci_device_intr_abort: xfer=%p\n", xfer)); 2386 if (xfer->pipe->intrxfer == xfer) { 2387 DPRINTFN(1,("uhci_device_intr_abort: remove\n")); 2388 xfer->pipe->intrxfer = NULL; 2389 } 2390 uhci_abort_xfer(xfer, USBD_CANCELLED); 2391 } 2392 2393 /* Close a device interrupt pipe. */ 2394 void 2395 uhci_device_intr_close(usbd_pipe_handle pipe) 2396 { 2397 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2398 uhci_softc_t *sc = pipe->device->bus->hci_private; 2399 int i, npoll; 2400 int s; 2401 2402 /* Unlink descriptors from controller data structures. */ 2403 npoll = upipe->u.intr.npoll; 2404 s = splusb(); 2405 for (i = 0; i < npoll; i++) 2406 uhci_remove_intr(sc, upipe->u.intr.qhs[i]); 2407 splx(s); 2408 2409 /* 2410 * We now have to wait for any activity on the physical 2411 * descriptors to stop. 2412 */ 2413 usb_delay_ms(&sc->sc_bus, 2); 2414 2415 for(i = 0; i < npoll; i++) 2416 uhci_free_sqh(sc, upipe->u.intr.qhs[i]); 2417 free(upipe->u.intr.qhs, M_USBHC); 2418 2419 /* XXX free other resources */ 2420 } 2421 2422 usbd_status 2423 uhci_device_request(usbd_xfer_handle xfer) 2424 { 2425 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2426 usb_device_request_t *req = &xfer->request; 2427 usbd_device_handle dev = upipe->pipe.device; 2428 uhci_softc_t *sc = dev->bus->hci_private; 2429 int addr = dev->address; 2430 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2431 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2432 uhci_soft_td_t *setup, *data, *stat, *next, *dataend; 2433 uhci_soft_qh_t *sqh; 2434 int len; 2435 u_int32_t ls; 2436 usbd_status err; 2437 int isread; 2438 int s; 2439 2440 DPRINTFN(3,("uhci_device_control type=0x%02x, request=0x%02x, " 2441 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 2442 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2443 UGETW(req->wIndex), UGETW(req->wLength), 2444 addr, endpt)); 2445 2446 ls = dev->speed == USB_SPEED_LOW ? UHCI_TD_LS : 0; 2447 isread = req->bmRequestType & UT_READ; 2448 len = UGETW(req->wLength); 2449 2450 setup = upipe->u.ctl.setup; 2451 stat = upipe->u.ctl.stat; 2452 sqh = upipe->u.ctl.sqh; 2453 2454 /* Set up data transaction */ 2455 if (len != 0) { 2456 upipe->nexttoggle = 1; 2457 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->flags, 2458 &xfer->dmabuf, &data, &dataend); 2459 if (err) 2460 return (err); 2461 next = data; 2462 dataend->link.std = stat; 2463 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_VF | UHCI_PTR_TD); 2464 usb_syncmem(&dataend->dma, 2465 dataend->offs + offsetof(uhci_td_t, td_link), 2466 sizeof(dataend->td.td_link), 2467 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2468 } else { 2469 next = stat; 2470 } 2471 upipe->u.ctl.length = len; 2472 2473 memcpy(KERNADDR(&upipe->u.ctl.reqdma, 0), req, sizeof *req); 2474 usb_syncmem(&upipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 2475 2476 setup->link.std = next; 2477 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_VF | UHCI_PTR_TD); 2478 setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2479 UHCI_TD_ACTIVE); 2480 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof *req, endpt, addr)); 2481 setup->td.td_buffer = htole32(DMAADDR(&upipe->u.ctl.reqdma, 0)); 2482 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2483 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2484 2485 stat->link.std = NULL; 2486 stat->td.td_link = htole32(UHCI_PTR_T); 2487 stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2488 UHCI_TD_ACTIVE | UHCI_TD_IOC); 2489 stat->td.td_token = 2490 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2491 UHCI_TD_IN (0, endpt, addr, 1)); 2492 stat->td.td_buffer = htole32(0); 2493 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2494 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2495 2496 #ifdef UHCI_DEBUG 2497 if (uhcidebug > 10) { 2498 DPRINTF(("uhci_device_request: before transfer\n")); 2499 uhci_dump_tds(setup); 2500 } 2501 #endif 2502 2503 /* Set up interrupt info. */ 2504 ii->xfer = xfer; 2505 ii->stdstart = setup; 2506 ii->stdend = stat; 2507 #ifdef DIAGNOSTIC 2508 if (!ii->isdone) { 2509 printf("uhci_device_request: not done, ii=%p\n", ii); 2510 } 2511 ii->isdone = 0; 2512 #endif 2513 2514 sqh->elink = setup; 2515 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2516 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2517 2518 s = splusb(); 2519 if (dev->speed == USB_SPEED_LOW) 2520 uhci_add_ls_ctrl(sc, sqh); 2521 else 2522 uhci_add_hs_ctrl(sc, sqh); 2523 uhci_add_intr_info(sc, ii); 2524 #ifdef UHCI_DEBUG 2525 if (uhcidebug > 12) { 2526 uhci_soft_td_t *std; 2527 uhci_soft_qh_t *xqh; 2528 uhci_soft_qh_t *sxqh; 2529 int maxqh = 0; 2530 uhci_physaddr_t link; 2531 DPRINTF(("uhci_enter_ctl_q: follow from [0]\n")); 2532 for (std = sc->sc_vframes[0].htd, link = 0; 2533 (link & UHCI_PTR_QH) == 0; 2534 std = std->link.std) { 2535 link = le32toh(std->td.td_link); 2536 uhci_dump_td(std); 2537 } 2538 sxqh = (uhci_soft_qh_t *)std; 2539 uhci_dump_qh(sxqh); 2540 for (xqh = sxqh; 2541 xqh != NULL; 2542 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2543 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2544 uhci_dump_qh(xqh); 2545 } 2546 DPRINTF(("Enqueued QH:\n")); 2547 uhci_dump_qh(sqh); 2548 uhci_dump_tds(sqh->elink); 2549 } 2550 #endif 2551 if (xfer->timeout && !sc->sc_bus.use_polling) { 2552 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 2553 uhci_timeout, ii); 2554 } 2555 xfer->status = USBD_IN_PROGRESS; 2556 splx(s); 2557 2558 return (USBD_NORMAL_COMPLETION); 2559 } 2560 2561 usbd_status 2562 uhci_device_isoc_transfer(usbd_xfer_handle xfer) 2563 { 2564 usbd_status err; 2565 2566 DPRINTFN(5,("uhci_device_isoc_transfer: xfer=%p\n", xfer)); 2567 2568 /* Put it on our queue, */ 2569 err = usb_insert_transfer(xfer); 2570 2571 /* bail out on error, */ 2572 if (err && err != USBD_IN_PROGRESS) 2573 return (err); 2574 2575 /* XXX should check inuse here */ 2576 2577 /* insert into schedule, */ 2578 uhci_device_isoc_enter(xfer); 2579 2580 /* and start if the pipe wasn't running */ 2581 if (!err) 2582 uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 2583 2584 return (err); 2585 } 2586 2587 void 2588 uhci_device_isoc_enter(usbd_xfer_handle xfer) 2589 { 2590 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2591 usbd_device_handle dev = upipe->pipe.device; 2592 uhci_softc_t *sc = dev->bus->hci_private; 2593 struct iso *iso = &upipe->u.iso; 2594 uhci_soft_td_t *std; 2595 u_int32_t buf, len, status, offs; 2596 int s, i, next, nframes; 2597 int rd = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2598 2599 DPRINTFN(5,("uhci_device_isoc_enter: used=%d next=%d xfer=%p " 2600 "nframes=%d\n", 2601 iso->inuse, iso->next, xfer, xfer->nframes)); 2602 2603 if (sc->sc_dying) 2604 return; 2605 2606 if (xfer->status == USBD_IN_PROGRESS) { 2607 /* This request has already been entered into the frame list */ 2608 printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer); 2609 /* XXX */ 2610 } 2611 2612 #ifdef DIAGNOSTIC 2613 if (iso->inuse >= UHCI_VFRAMELIST_COUNT) 2614 printf("uhci_device_isoc_enter: overflow!\n"); 2615 #endif 2616 2617 next = iso->next; 2618 if (next == -1) { 2619 /* Not in use yet, schedule it a few frames ahead. */ 2620 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 2621 DPRINTFN(2,("uhci_device_isoc_enter: start next=%d\n", next)); 2622 } 2623 2624 xfer->status = USBD_IN_PROGRESS; 2625 UXFER(xfer)->curframe = next; 2626 2627 buf = DMAADDR(&xfer->dmabuf, 0); 2628 offs = 0; 2629 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 2630 UHCI_TD_ACTIVE | 2631 UHCI_TD_IOS); 2632 nframes = xfer->nframes; 2633 s = splusb(); 2634 for (i = 0; i < nframes; i++) { 2635 std = iso->stds[next]; 2636 if (++next >= UHCI_VFRAMELIST_COUNT) 2637 next = 0; 2638 len = xfer->frlengths[i]; 2639 std->td.td_buffer = htole32(buf); 2640 usb_syncmem(&xfer->dmabuf, offs, len, 2641 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2642 if (i == nframes - 1) 2643 status |= UHCI_TD_IOC; 2644 std->td.td_status = htole32(status); 2645 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2646 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 2647 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2648 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2649 #ifdef UHCI_DEBUG 2650 if (uhcidebug > 5) { 2651 DPRINTFN(5,("uhci_device_isoc_enter: TD %d\n", i)); 2652 uhci_dump_td(std); 2653 } 2654 #endif 2655 buf += len; 2656 offs += len; 2657 } 2658 iso->next = next; 2659 iso->inuse += xfer->nframes; 2660 2661 splx(s); 2662 } 2663 2664 usbd_status 2665 uhci_device_isoc_start(usbd_xfer_handle xfer) 2666 { 2667 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2668 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 2669 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2670 uhci_soft_td_t *end; 2671 int s, i; 2672 2673 DPRINTFN(5,("uhci_device_isoc_start: xfer=%p\n", xfer)); 2674 2675 if (sc->sc_dying) 2676 return (USBD_IOERROR); 2677 2678 #ifdef DIAGNOSTIC 2679 if (xfer->status != USBD_IN_PROGRESS) 2680 printf("uhci_device_isoc_start: not in progress %p\n", xfer); 2681 #endif 2682 2683 /* Find the last TD */ 2684 i = UXFER(xfer)->curframe + xfer->nframes; 2685 if (i >= UHCI_VFRAMELIST_COUNT) 2686 i -= UHCI_VFRAMELIST_COUNT; 2687 end = upipe->u.iso.stds[i]; 2688 2689 #ifdef DIAGNOSTIC 2690 if (end == NULL) { 2691 printf("uhci_device_isoc_start: end == NULL\n"); 2692 return (USBD_INVAL); 2693 } 2694 #endif 2695 2696 s = splusb(); 2697 2698 /* Set up interrupt info. */ 2699 ii->xfer = xfer; 2700 ii->stdstart = end; 2701 ii->stdend = end; 2702 #ifdef DIAGNOSTIC 2703 if (!ii->isdone) 2704 printf("uhci_device_isoc_start: not done, ii=%p\n", ii); 2705 ii->isdone = 0; 2706 #endif 2707 uhci_add_intr_info(sc, ii); 2708 2709 splx(s); 2710 2711 return (USBD_IN_PROGRESS); 2712 } 2713 2714 void 2715 uhci_device_isoc_abort(usbd_xfer_handle xfer) 2716 { 2717 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2718 uhci_soft_td_t **stds = upipe->u.iso.stds; 2719 uhci_soft_td_t *std; 2720 int i, n, s, nframes, maxlen, len; 2721 2722 s = splusb(); 2723 2724 /* Transfer is already done. */ 2725 if (xfer->status != USBD_NOT_STARTED && 2726 xfer->status != USBD_IN_PROGRESS) { 2727 splx(s); 2728 return; 2729 } 2730 2731 /* Give xfer the requested abort code. */ 2732 xfer->status = USBD_CANCELLED; 2733 2734 /* make hardware ignore it, */ 2735 nframes = xfer->nframes; 2736 n = UXFER(xfer)->curframe; 2737 maxlen = 0; 2738 for (i = 0; i < nframes; i++) { 2739 std = stds[n]; 2740 usb_syncmem(&std->dma, 2741 std->offs + offsetof(uhci_td_t, td_status), 2742 sizeof(std->td.td_status), 2743 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2744 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2745 usb_syncmem(&std->dma, 2746 std->offs + offsetof(uhci_td_t, td_status), 2747 sizeof(std->td.td_status), 2748 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2749 usb_syncmem(&std->dma, 2750 std->offs + offsetof(uhci_td_t, td_token), 2751 sizeof(std->td.td_token), 2752 BUS_DMASYNC_POSTWRITE); 2753 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 2754 if (len > maxlen) 2755 maxlen = len; 2756 if (++n >= UHCI_VFRAMELIST_COUNT) 2757 n = 0; 2758 } 2759 2760 /* and wait until we are sure the hardware has finished. */ 2761 delay(maxlen); 2762 2763 #ifdef DIAGNOSTIC 2764 UXFER(xfer)->iinfo.isdone = 1; 2765 #endif 2766 /* Run callback and remove from interrupt list. */ 2767 usb_transfer_complete(xfer); 2768 2769 splx(s); 2770 } 2771 2772 void 2773 uhci_device_isoc_close(usbd_pipe_handle pipe) 2774 { 2775 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2776 usbd_device_handle dev = upipe->pipe.device; 2777 uhci_softc_t *sc = dev->bus->hci_private; 2778 uhci_soft_td_t *std, *vstd; 2779 struct iso *iso; 2780 int i, s; 2781 2782 /* 2783 * Make sure all TDs are marked as inactive. 2784 * Wait for completion. 2785 * Unschedule. 2786 * Deallocate. 2787 */ 2788 iso = &upipe->u.iso; 2789 2790 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2791 std = iso->stds[i]; 2792 usb_syncmem(&std->dma, 2793 std->offs + offsetof(uhci_td_t, td_status), 2794 sizeof(std->td.td_status), 2795 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2796 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 2797 usb_syncmem(&std->dma, 2798 std->offs + offsetof(uhci_td_t, td_status), 2799 sizeof(std->td.td_status), 2800 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2801 } 2802 usb_delay_ms(&sc->sc_bus, 2); /* wait for completion */ 2803 2804 s = splusb(); 2805 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2806 std = iso->stds[i]; 2807 for (vstd = sc->sc_vframes[i].htd; 2808 vstd != NULL && vstd->link.std != std; 2809 vstd = vstd->link.std) 2810 ; 2811 if (vstd == NULL) { 2812 /*panic*/ 2813 printf("uhci_device_isoc_close: %p not found\n", std); 2814 splx(s); 2815 return; 2816 } 2817 vstd->link = std->link; 2818 usb_syncmem(&std->dma, 2819 std->offs + offsetof(uhci_td_t, td_link), 2820 sizeof(std->td.td_link), 2821 BUS_DMASYNC_POSTWRITE); 2822 vstd->td.td_link = std->td.td_link; 2823 usb_syncmem(&vstd->dma, 2824 vstd->offs + offsetof(uhci_td_t, td_link), 2825 sizeof(vstd->td.td_link), 2826 BUS_DMASYNC_PREWRITE); 2827 uhci_free_std(sc, std); 2828 } 2829 splx(s); 2830 2831 free(iso->stds, M_USBHC); 2832 } 2833 2834 usbd_status 2835 uhci_setup_isoc(usbd_pipe_handle pipe) 2836 { 2837 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2838 usbd_device_handle dev = upipe->pipe.device; 2839 uhci_softc_t *sc = dev->bus->hci_private; 2840 int addr = upipe->pipe.device->address; 2841 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2842 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 2843 uhci_soft_td_t *std, *vstd; 2844 u_int32_t token; 2845 struct iso *iso; 2846 int i, s; 2847 2848 iso = &upipe->u.iso; 2849 iso->stds = malloc(UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *), 2850 M_USBHC, M_WAITOK); 2851 2852 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 2853 UHCI_TD_OUT(0, endpt, addr, 0); 2854 2855 /* Allocate the TDs and mark as inactive; */ 2856 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2857 std = uhci_alloc_std(sc); 2858 if (std == 0) 2859 goto bad; 2860 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 2861 std->td.td_token = htole32(token); 2862 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2863 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2864 iso->stds[i] = std; 2865 } 2866 2867 /* Insert TDs into schedule. */ 2868 s = splusb(); 2869 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2870 std = iso->stds[i]; 2871 vstd = sc->sc_vframes[i].htd; 2872 usb_syncmem(&vstd->dma, 2873 vstd->offs + offsetof(uhci_td_t, td_link), 2874 sizeof(vstd->td.td_link), 2875 BUS_DMASYNC_POSTWRITE); 2876 std->link = vstd->link; 2877 std->td.td_link = vstd->td.td_link; 2878 usb_syncmem(&std->dma, 2879 std->offs + offsetof(uhci_td_t, td_link), 2880 sizeof(std->td.td_link), 2881 BUS_DMASYNC_PREWRITE); 2882 vstd->link.std = std; 2883 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 2884 usb_syncmem(&vstd->dma, 2885 vstd->offs + offsetof(uhci_td_t, td_link), 2886 sizeof(vstd->td.td_link), 2887 BUS_DMASYNC_PREWRITE); 2888 } 2889 splx(s); 2890 2891 iso->next = -1; 2892 iso->inuse = 0; 2893 2894 return (USBD_NORMAL_COMPLETION); 2895 2896 bad: 2897 while (--i >= 0) 2898 uhci_free_std(sc, iso->stds[i]); 2899 free(iso->stds, M_USBHC); 2900 return (USBD_NOMEM); 2901 } 2902 2903 void 2904 uhci_device_isoc_done(usbd_xfer_handle xfer) 2905 { 2906 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2907 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2908 int i, offs; 2909 int rd = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2910 2911 2912 DPRINTFN(4, ("uhci_isoc_done: length=%d, busy_free=0x%08x\n", 2913 xfer->actlen, xfer->busy_free)); 2914 2915 if (ii->xfer != xfer) 2916 /* Not on interrupt list, ignore it. */ 2917 return; 2918 2919 if (!uhci_active_intr_info(ii)) 2920 return; 2921 2922 #ifdef DIAGNOSTIC 2923 if (ii->stdend == NULL) { 2924 printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer); 2925 #ifdef UHCI_DEBUG 2926 uhci_dump_ii(ii); 2927 #endif 2928 return; 2929 } 2930 #endif 2931 2932 /* Turn off the interrupt since it is active even if the TD is not. */ 2933 usb_syncmem(&ii->stdend->dma, 2934 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2935 sizeof(ii->stdend->td.td_status), 2936 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2937 ii->stdend->td.td_status &= htole32(~UHCI_TD_IOC); 2938 usb_syncmem(&ii->stdend->dma, 2939 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2940 sizeof(ii->stdend->td.td_status), 2941 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2942 2943 uhci_del_intr_info(ii); /* remove from active list */ 2944 2945 offs = 0; 2946 for (i = 0; i < xfer->nframes; i++) { 2947 usb_syncmem(&xfer->dmabuf, offs, xfer->frlengths[i], 2948 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2949 offs += xfer->frlengths[i]; 2950 } 2951 } 2952 2953 void 2954 uhci_device_intr_done(usbd_xfer_handle xfer) 2955 { 2956 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2957 uhci_softc_t *sc = ii->sc; 2958 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2959 uhci_soft_qh_t *sqh; 2960 int i, npoll, isread; 2961 2962 DPRINTFN(5, ("uhci_device_intr_done: length=%d\n", xfer->actlen)); 2963 2964 npoll = upipe->u.intr.npoll; 2965 for(i = 0; i < npoll; i++) { 2966 sqh = upipe->u.intr.qhs[i]; 2967 sqh->elink = NULL; 2968 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 2969 usb_syncmem(&sqh->dma, 2970 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2971 sizeof(sqh->qh.qh_elink), 2972 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2973 } 2974 uhci_free_std_chain(sc, ii->stdstart, NULL); 2975 2976 isread = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2977 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 2978 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2979 2980 /* XXX Wasteful. */ 2981 if (xfer->pipe->repeat) { 2982 uhci_soft_td_t *data, *dataend; 2983 2984 DPRINTFN(5,("uhci_device_intr_done: requeing\n")); 2985 2986 /* This alloc cannot fail since we freed the chain above. */ 2987 uhci_alloc_std_chain(upipe, sc, xfer->length, 2988 upipe->u.intr.isread, xfer->flags, 2989 &xfer->dmabuf, &data, &dataend); 2990 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2991 usb_syncmem(&dataend->dma, 2992 dataend->offs + offsetof(uhci_td_t, td_status), 2993 sizeof(dataend->td.td_status), 2994 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2995 2996 #ifdef UHCI_DEBUG 2997 if (uhcidebug > 10) { 2998 DPRINTF(("uhci_device_intr_done: data(1)\n")); 2999 uhci_dump_tds(data); 3000 uhci_dump_qh(upipe->u.intr.qhs[0]); 3001 } 3002 #endif 3003 3004 ii->stdstart = data; 3005 ii->stdend = dataend; 3006 #ifdef DIAGNOSTIC 3007 if (!ii->isdone) { 3008 printf("uhci_device_intr_done: not done, ii=%p\n", ii); 3009 } 3010 ii->isdone = 0; 3011 #endif 3012 for (i = 0; i < npoll; i++) { 3013 sqh = upipe->u.intr.qhs[i]; 3014 sqh->elink = data; 3015 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 3016 usb_syncmem(&sqh->dma, 3017 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3018 sizeof(sqh->qh.qh_elink), 3019 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3020 } 3021 xfer->status = USBD_IN_PROGRESS; 3022 /* The ii is already on the examined list, just leave it. */ 3023 } else { 3024 DPRINTFN(5,("uhci_device_intr_done: removing\n")); 3025 if (uhci_active_intr_info(ii)) 3026 uhci_del_intr_info(ii); 3027 } 3028 } 3029 3030 /* Deallocate request data structures */ 3031 void 3032 uhci_device_ctrl_done(usbd_xfer_handle xfer) 3033 { 3034 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3035 uhci_softc_t *sc = ii->sc; 3036 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 3037 int len = UGETW(xfer->request.wLength); 3038 int isread = (xfer->request.bmRequestType & UT_READ); 3039 3040 #ifdef DIAGNOSTIC 3041 if (!(xfer->rqflags & URQ_REQUEST)) 3042 panic("uhci_device_ctrl_done: not a request"); 3043 #endif 3044 3045 if (!uhci_active_intr_info(ii)) 3046 return; 3047 3048 uhci_del_intr_info(ii); /* remove from active list */ 3049 3050 if (upipe->pipe.device->speed == USB_SPEED_LOW) 3051 uhci_remove_ls_ctrl(sc, upipe->u.ctl.sqh); 3052 else 3053 uhci_remove_hs_ctrl(sc, upipe->u.ctl.sqh); 3054 3055 if (upipe->u.ctl.length != 0) 3056 uhci_free_std_chain(sc, ii->stdstart->link.std, ii->stdend); 3057 3058 if (len) { 3059 usb_syncmem(&xfer->dmabuf, 0, len, 3060 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3061 } 3062 usb_syncmem(&upipe->u.ctl.reqdma, 0, 3063 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3064 3065 DPRINTFN(5, ("uhci_device_ctrl_done: length=%d\n", xfer->actlen)); 3066 } 3067 3068 /* Deallocate request data structures */ 3069 void 3070 uhci_device_bulk_done(usbd_xfer_handle xfer) 3071 { 3072 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3073 uhci_softc_t *sc = ii->sc; 3074 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 3075 3076 DPRINTFN(5,("uhci_device_bulk_done: xfer=%p ii=%p sc=%p upipe=%p\n", 3077 xfer, ii, sc, upipe)); 3078 3079 if (!uhci_active_intr_info(ii)) 3080 return; 3081 3082 uhci_del_intr_info(ii); /* remove from active list */ 3083 3084 uhci_remove_bulk(sc, upipe->u.bulk.sqh); 3085 3086 uhci_free_std_chain(sc, ii->stdstart, NULL); 3087 3088 DPRINTFN(5, ("uhci_device_bulk_done: length=%d\n", xfer->actlen)); 3089 } 3090 3091 /* Add interrupt QH, called with vflock. */ 3092 void 3093 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3094 { 3095 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3096 uhci_soft_qh_t *eqh; 3097 3098 DPRINTFN(4, ("uhci_add_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3099 3100 eqh = vf->eqh; 3101 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3102 sizeof(eqh->qh.qh_hlink), 3103 BUS_DMASYNC_POSTWRITE); 3104 sqh->hlink = eqh->hlink; 3105 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3106 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3107 sizeof(sqh->qh.qh_hlink), 3108 BUS_DMASYNC_PREWRITE); 3109 eqh->hlink = sqh; 3110 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3111 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3112 sizeof(eqh->qh.qh_hlink), 3113 BUS_DMASYNC_PREWRITE); 3114 vf->eqh = sqh; 3115 vf->bandwidth++; 3116 } 3117 3118 /* Remove interrupt QH. */ 3119 void 3120 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3121 { 3122 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3123 uhci_soft_qh_t *pqh; 3124 3125 DPRINTFN(4, ("uhci_remove_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3126 3127 /* See comment in uhci_remove_ctrl() */ 3128 3129 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3130 sizeof(sqh->qh.qh_elink), 3131 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3132 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3133 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3134 usb_syncmem(&sqh->dma, 3135 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3136 sizeof(sqh->qh.qh_elink), 3137 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3138 delay(UHCI_QH_REMOVE_DELAY); 3139 } 3140 3141 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3142 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3143 sizeof(sqh->qh.qh_hlink), 3144 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3145 pqh->hlink = sqh->hlink; 3146 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3147 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3148 sizeof(pqh->qh.qh_hlink), 3149 BUS_DMASYNC_PREWRITE); 3150 delay(UHCI_QH_REMOVE_DELAY); 3151 if (vf->eqh == sqh) 3152 vf->eqh = pqh; 3153 vf->bandwidth--; 3154 } 3155 3156 usbd_status 3157 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3158 { 3159 uhci_soft_qh_t *sqh; 3160 int i, npoll, s; 3161 u_int bestbw, bw, bestoffs, offs; 3162 3163 DPRINTFN(2, ("uhci_device_setintr: pipe=%p\n", upipe)); 3164 if (ival == 0) { 3165 printf("uhci_device_setintr: 0 interval\n"); 3166 return (USBD_INVAL); 3167 } 3168 3169 if (ival > UHCI_VFRAMELIST_COUNT) 3170 ival = UHCI_VFRAMELIST_COUNT; 3171 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3172 DPRINTFN(2, ("uhci_device_setintr: ival=%d npoll=%d\n", ival, npoll)); 3173 3174 upipe->u.intr.npoll = npoll; 3175 upipe->u.intr.qhs = 3176 malloc(npoll * sizeof(uhci_soft_qh_t *), M_USBHC, M_WAITOK); 3177 3178 /* 3179 * Figure out which offset in the schedule that has most 3180 * bandwidth left over. 3181 */ 3182 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3183 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3184 for (bw = i = 0; i < npoll; i++) 3185 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3186 if (bw < bestbw) { 3187 bestbw = bw; 3188 bestoffs = offs; 3189 } 3190 } 3191 DPRINTFN(1, ("uhci_device_setintr: bw=%d offs=%d\n", bestbw, bestoffs)); 3192 3193 for(i = 0; i < npoll; i++) { 3194 upipe->u.intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3195 sqh->elink = NULL; 3196 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3197 usb_syncmem(&sqh->dma, 3198 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3199 sizeof(sqh->qh.qh_elink), 3200 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3201 sqh->pos = MOD(i * ival + bestoffs); 3202 } 3203 #undef MOD 3204 3205 s = splusb(); 3206 /* Enter QHs into the controller data structures. */ 3207 for(i = 0; i < npoll; i++) 3208 uhci_add_intr(sc, upipe->u.intr.qhs[i]); 3209 splx(s); 3210 3211 DPRINTFN(5, ("uhci_device_setintr: returns %p\n", upipe)); 3212 return (USBD_NORMAL_COMPLETION); 3213 } 3214 3215 /* Open a new pipe. */ 3216 usbd_status 3217 uhci_open(usbd_pipe_handle pipe) 3218 { 3219 uhci_softc_t *sc = pipe->device->bus->hci_private; 3220 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 3221 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 3222 usbd_status err; 3223 int ival; 3224 3225 DPRINTFN(1, ("uhci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 3226 pipe, pipe->device->address, 3227 ed->bEndpointAddress, sc->sc_addr)); 3228 3229 upipe->aborting = 0; 3230 upipe->nexttoggle = 0; 3231 3232 if (pipe->device->address == sc->sc_addr) { 3233 switch (ed->bEndpointAddress) { 3234 case USB_CONTROL_ENDPOINT: 3235 pipe->methods = &uhci_root_ctrl_methods; 3236 break; 3237 case UE_DIR_IN | UHCI_INTR_ENDPT: 3238 pipe->methods = &uhci_root_intr_methods; 3239 break; 3240 default: 3241 return (USBD_INVAL); 3242 } 3243 } else { 3244 switch (ed->bmAttributes & UE_XFERTYPE) { 3245 case UE_CONTROL: 3246 pipe->methods = &uhci_device_ctrl_methods; 3247 upipe->u.ctl.sqh = uhci_alloc_sqh(sc); 3248 if (upipe->u.ctl.sqh == NULL) 3249 goto bad; 3250 upipe->u.ctl.setup = uhci_alloc_std(sc); 3251 if (upipe->u.ctl.setup == NULL) { 3252 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3253 goto bad; 3254 } 3255 upipe->u.ctl.stat = uhci_alloc_std(sc); 3256 if (upipe->u.ctl.stat == NULL) { 3257 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3258 uhci_free_std(sc, upipe->u.ctl.setup); 3259 goto bad; 3260 } 3261 err = usb_allocmem(&sc->sc_bus, 3262 sizeof(usb_device_request_t), 3263 0, &upipe->u.ctl.reqdma); 3264 if (err) { 3265 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3266 uhci_free_std(sc, upipe->u.ctl.setup); 3267 uhci_free_std(sc, upipe->u.ctl.stat); 3268 goto bad; 3269 } 3270 break; 3271 case UE_INTERRUPT: 3272 pipe->methods = &uhci_device_intr_methods; 3273 ival = pipe->interval; 3274 if (ival == USBD_DEFAULT_INTERVAL) 3275 ival = ed->bInterval; 3276 return (uhci_device_setintr(sc, upipe, ival)); 3277 case UE_ISOCHRONOUS: 3278 pipe->methods = &uhci_device_isoc_methods; 3279 return (uhci_setup_isoc(pipe)); 3280 case UE_BULK: 3281 pipe->methods = &uhci_device_bulk_methods; 3282 upipe->u.bulk.sqh = uhci_alloc_sqh(sc); 3283 if (upipe->u.bulk.sqh == NULL) 3284 goto bad; 3285 break; 3286 } 3287 } 3288 return (USBD_NORMAL_COMPLETION); 3289 3290 bad: 3291 return (USBD_NOMEM); 3292 } 3293 3294 /* 3295 * Data structures and routines to emulate the root hub. 3296 */ 3297 usb_device_descriptor_t uhci_devd = { 3298 USB_DEVICE_DESCRIPTOR_SIZE, 3299 UDESC_DEVICE, /* type */ 3300 {0x00, 0x01}, /* USB version */ 3301 UDCLASS_HUB, /* class */ 3302 UDSUBCLASS_HUB, /* subclass */ 3303 UDPROTO_FSHUB, /* protocol */ 3304 64, /* max packet */ 3305 {0},{0},{0x00,0x01}, /* device id */ 3306 1,2,0, /* string indicies */ 3307 1 /* # of configurations */ 3308 }; 3309 3310 const usb_config_descriptor_t uhci_confd = { 3311 USB_CONFIG_DESCRIPTOR_SIZE, 3312 UDESC_CONFIG, 3313 {USB_CONFIG_DESCRIPTOR_SIZE + 3314 USB_INTERFACE_DESCRIPTOR_SIZE + 3315 USB_ENDPOINT_DESCRIPTOR_SIZE}, 3316 1, 3317 1, 3318 0, 3319 UC_ATTR_MBO | UC_SELF_POWERED, 3320 0 /* max power */ 3321 }; 3322 3323 const usb_interface_descriptor_t uhci_ifcd = { 3324 USB_INTERFACE_DESCRIPTOR_SIZE, 3325 UDESC_INTERFACE, 3326 0, 3327 0, 3328 1, 3329 UICLASS_HUB, 3330 UISUBCLASS_HUB, 3331 UIPROTO_FSHUB, 3332 0 3333 }; 3334 3335 const usb_endpoint_descriptor_t uhci_endpd = { 3336 USB_ENDPOINT_DESCRIPTOR_SIZE, 3337 UDESC_ENDPOINT, 3338 UE_DIR_IN | UHCI_INTR_ENDPT, 3339 UE_INTERRUPT, 3340 {8}, 3341 255 3342 }; 3343 3344 const usb_hub_descriptor_t uhci_hubd_piix = { 3345 USB_HUB_DESCRIPTOR_SIZE, 3346 UDESC_HUB, 3347 2, 3348 { UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0 }, 3349 50, /* power on to power good */ 3350 0, 3351 { 0x00 }, /* both ports are removable */ 3352 { 0 }, 3353 }; 3354 3355 /* 3356 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3357 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3358 * should not be used by the USB subsystem. As we cannot issue a 3359 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3360 * will be enabled as part of the reset. 3361 * 3362 * On the VT83C572, the port cannot be successfully enabled until the 3363 * outstanding "port enable change" and "connection status change" 3364 * events have been reset. 3365 */ 3366 Static usbd_status 3367 uhci_portreset(uhci_softc_t *sc, int index) 3368 { 3369 int lim, port, x; 3370 3371 if (index == 1) 3372 port = UHCI_PORTSC1; 3373 else if (index == 2) 3374 port = UHCI_PORTSC2; 3375 else 3376 return (USBD_IOERROR); 3377 3378 x = URWMASK(UREAD2(sc, port)); 3379 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3380 3381 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3382 3383 DPRINTFN(3,("uhci port %d reset, status0 = 0x%04x\n", 3384 index, UREAD2(sc, port))); 3385 3386 x = URWMASK(UREAD2(sc, port)); 3387 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3388 3389 delay(100); 3390 3391 DPRINTFN(3,("uhci port %d reset, status1 = 0x%04x\n", 3392 index, UREAD2(sc, port))); 3393 3394 x = URWMASK(UREAD2(sc, port)); 3395 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3396 3397 for (lim = 10; --lim > 0;) { 3398 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3399 3400 x = UREAD2(sc, port); 3401 3402 DPRINTFN(3,("uhci port %d iteration %u, status = 0x%04x\n", 3403 index, lim, x)); 3404 3405 if (!(x & UHCI_PORTSC_CCS)) { 3406 /* 3407 * No device is connected (or was disconnected 3408 * during reset). Consider the port reset. 3409 * The delay must be long enough to ensure on 3410 * the initial iteration that the device 3411 * connection will have been registered. 50ms 3412 * appears to be sufficient, but 20ms is not. 3413 */ 3414 DPRINTFN(3,("uhci port %d loop %u, device detached\n", 3415 index, lim)); 3416 break; 3417 } 3418 3419 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3420 /* 3421 * Port enabled changed and/or connection 3422 * status changed were set. Reset either or 3423 * both raised flags (by writing a 1 to that 3424 * bit), and wait again for state to settle. 3425 */ 3426 UWRITE2(sc, port, URWMASK(x) | 3427 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3428 continue; 3429 } 3430 3431 if (x & UHCI_PORTSC_PE) 3432 /* Port is enabled */ 3433 break; 3434 3435 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3436 } 3437 3438 DPRINTFN(3,("uhci port %d reset, status2 = 0x%04x\n", 3439 index, UREAD2(sc, port))); 3440 3441 if (lim <= 0) { 3442 DPRINTFN(1,("uhci port %d reset timed out\n", index)); 3443 return (USBD_TIMEOUT); 3444 } 3445 3446 sc->sc_isreset = 1; 3447 return (USBD_NORMAL_COMPLETION); 3448 } 3449 3450 /* 3451 * Simulate a hardware hub by handling all the necessary requests. 3452 */ 3453 usbd_status 3454 uhci_root_ctrl_transfer(usbd_xfer_handle xfer) 3455 { 3456 usbd_status err; 3457 3458 /* Insert last in queue. */ 3459 err = usb_insert_transfer(xfer); 3460 if (err) 3461 return (err); 3462 3463 /* 3464 * Pipe isn't running (otherwise err would be USBD_INPROG), 3465 * so start it first. 3466 */ 3467 return (uhci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3468 } 3469 3470 usbd_status 3471 uhci_root_ctrl_start(usbd_xfer_handle xfer) 3472 { 3473 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3474 usb_device_request_t *req; 3475 void *buf = NULL; 3476 int port, x; 3477 int s, len, value, index, status, change, l, totlen = 0; 3478 usb_port_status_t ps; 3479 usbd_status err; 3480 3481 if (sc->sc_dying) 3482 return (USBD_IOERROR); 3483 3484 #ifdef DIAGNOSTIC 3485 if (!(xfer->rqflags & URQ_REQUEST)) 3486 panic("uhci_root_ctrl_transfer: not a request"); 3487 #endif 3488 req = &xfer->request; 3489 3490 DPRINTFN(2,("uhci_root_ctrl_control type=0x%02x request=%02x\n", 3491 req->bmRequestType, req->bRequest)); 3492 3493 len = UGETW(req->wLength); 3494 value = UGETW(req->wValue); 3495 index = UGETW(req->wIndex); 3496 3497 if (len != 0) 3498 buf = KERNADDR(&xfer->dmabuf, 0); 3499 3500 #define C(x,y) ((x) | ((y) << 8)) 3501 switch(C(req->bRequest, req->bmRequestType)) { 3502 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3503 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3504 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3505 /* 3506 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3507 * for the integrated root hub. 3508 */ 3509 break; 3510 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3511 if (len > 0) { 3512 *(u_int8_t *)buf = sc->sc_conf; 3513 totlen = 1; 3514 } 3515 break; 3516 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3517 DPRINTFN(2,("uhci_root_ctrl_control wValue=0x%04x\n", value)); 3518 if (len == 0) 3519 break; 3520 switch(value >> 8) { 3521 case UDESC_DEVICE: 3522 if ((value & 0xff) != 0) { 3523 err = USBD_IOERROR; 3524 goto ret; 3525 } 3526 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 3527 USETW(uhci_devd.idVendor, sc->sc_id_vendor); 3528 memcpy(buf, &uhci_devd, l); 3529 break; 3530 case UDESC_CONFIG: 3531 if ((value & 0xff) != 0) { 3532 err = USBD_IOERROR; 3533 goto ret; 3534 } 3535 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 3536 memcpy(buf, &uhci_confd, l); 3537 buf = (char *)buf + l; 3538 len -= l; 3539 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 3540 totlen += l; 3541 memcpy(buf, &uhci_ifcd, l); 3542 buf = (char *)buf + l; 3543 len -= l; 3544 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 3545 totlen += l; 3546 memcpy(buf, &uhci_endpd, l); 3547 break; 3548 case UDESC_STRING: 3549 #define sd ((usb_string_descriptor_t *)buf) 3550 switch (value & 0xff) { 3551 case 0: /* Language table */ 3552 totlen = usb_makelangtbl(sd, len); 3553 break; 3554 case 1: /* Vendor */ 3555 totlen = usb_makestrdesc(sd, len, 3556 sc->sc_vendor); 3557 break; 3558 case 2: /* Product */ 3559 totlen = usb_makestrdesc(sd, len, 3560 "UHCI root hub"); 3561 break; 3562 } 3563 #undef sd 3564 break; 3565 default: 3566 err = USBD_IOERROR; 3567 goto ret; 3568 } 3569 break; 3570 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3571 if (len > 0) { 3572 *(u_int8_t *)buf = 0; 3573 totlen = 1; 3574 } 3575 break; 3576 case C(UR_GET_STATUS, UT_READ_DEVICE): 3577 if (len > 1) { 3578 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 3579 totlen = 2; 3580 } 3581 break; 3582 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3583 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3584 if (len > 1) { 3585 USETW(((usb_status_t *)buf)->wStatus, 0); 3586 totlen = 2; 3587 } 3588 break; 3589 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3590 if (value >= USB_MAX_DEVICES) { 3591 err = USBD_IOERROR; 3592 goto ret; 3593 } 3594 sc->sc_addr = value; 3595 break; 3596 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3597 if (value != 0 && value != 1) { 3598 err = USBD_IOERROR; 3599 goto ret; 3600 } 3601 sc->sc_conf = value; 3602 break; 3603 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3604 break; 3605 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3606 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3607 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3608 err = USBD_IOERROR; 3609 goto ret; 3610 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3611 break; 3612 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3613 break; 3614 /* Hub requests */ 3615 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3616 break; 3617 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3618 DPRINTFN(3, ("uhci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 3619 "port=%d feature=%d\n", 3620 index, value)); 3621 if (index == 1) 3622 port = UHCI_PORTSC1; 3623 else if (index == 2) 3624 port = UHCI_PORTSC2; 3625 else { 3626 err = USBD_IOERROR; 3627 goto ret; 3628 } 3629 switch(value) { 3630 case UHF_PORT_ENABLE: 3631 x = URWMASK(UREAD2(sc, port)); 3632 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3633 break; 3634 case UHF_PORT_SUSPEND: 3635 x = URWMASK(UREAD2(sc, port)); 3636 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3637 break; 3638 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3639 /* see USB2 spec ch. 7.1.7.7 */ 3640 usb_delay_ms(&sc->sc_bus, 20); 3641 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3642 /* 10ms resume delay must be provided by caller */ 3643 break; 3644 case UHF_PORT_RESET: 3645 x = URWMASK(UREAD2(sc, port)); 3646 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3647 break; 3648 case UHF_C_PORT_CONNECTION: 3649 x = URWMASK(UREAD2(sc, port)); 3650 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3651 break; 3652 case UHF_C_PORT_ENABLE: 3653 x = URWMASK(UREAD2(sc, port)); 3654 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3655 break; 3656 case UHF_C_PORT_OVER_CURRENT: 3657 x = URWMASK(UREAD2(sc, port)); 3658 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3659 break; 3660 case UHF_C_PORT_RESET: 3661 sc->sc_isreset = 0; 3662 err = USBD_NORMAL_COMPLETION; 3663 goto ret; 3664 case UHF_PORT_CONNECTION: 3665 case UHF_PORT_OVER_CURRENT: 3666 case UHF_PORT_POWER: 3667 case UHF_PORT_LOW_SPEED: 3668 case UHF_C_PORT_SUSPEND: 3669 default: 3670 err = USBD_IOERROR; 3671 goto ret; 3672 } 3673 break; 3674 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3675 if (index == 1) 3676 port = UHCI_PORTSC1; 3677 else if (index == 2) 3678 port = UHCI_PORTSC2; 3679 else { 3680 err = USBD_IOERROR; 3681 goto ret; 3682 } 3683 if (len > 0) { 3684 *(u_int8_t *)buf = 3685 (UREAD2(sc, port) & UHCI_PORTSC_LS) >> 3686 UHCI_PORTSC_LS_SHIFT; 3687 totlen = 1; 3688 } 3689 break; 3690 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3691 if (len == 0) 3692 break; 3693 if ((value & 0xff) != 0) { 3694 err = USBD_IOERROR; 3695 goto ret; 3696 } 3697 l = min(len, USB_HUB_DESCRIPTOR_SIZE); 3698 totlen = l; 3699 memcpy(buf, &uhci_hubd_piix, l); 3700 break; 3701 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3702 if (len != 4) { 3703 err = USBD_IOERROR; 3704 goto ret; 3705 } 3706 memset(buf, 0, len); 3707 totlen = len; 3708 break; 3709 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3710 if (index == 1) 3711 port = UHCI_PORTSC1; 3712 else if (index == 2) 3713 port = UHCI_PORTSC2; 3714 else { 3715 err = USBD_IOERROR; 3716 goto ret; 3717 } 3718 if (len != 4) { 3719 err = USBD_IOERROR; 3720 goto ret; 3721 } 3722 x = UREAD2(sc, port); 3723 status = change = 0; 3724 if (x & UHCI_PORTSC_CCS) 3725 status |= UPS_CURRENT_CONNECT_STATUS; 3726 if (x & UHCI_PORTSC_CSC) 3727 change |= UPS_C_CONNECT_STATUS; 3728 if (x & UHCI_PORTSC_PE) 3729 status |= UPS_PORT_ENABLED; 3730 if (x & UHCI_PORTSC_POEDC) 3731 change |= UPS_C_PORT_ENABLED; 3732 if (x & UHCI_PORTSC_OCI) 3733 status |= UPS_OVERCURRENT_INDICATOR; 3734 if (x & UHCI_PORTSC_OCIC) 3735 change |= UPS_C_OVERCURRENT_INDICATOR; 3736 if (x & UHCI_PORTSC_SUSP) 3737 status |= UPS_SUSPEND; 3738 if (x & UHCI_PORTSC_LSDA) 3739 status |= UPS_LOW_SPEED; 3740 status |= UPS_PORT_POWER; 3741 if (sc->sc_isreset) 3742 change |= UPS_C_PORT_RESET; 3743 USETW(ps.wPortStatus, status); 3744 USETW(ps.wPortChange, change); 3745 l = min(len, sizeof ps); 3746 memcpy(buf, &ps, l); 3747 totlen = l; 3748 break; 3749 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3750 err = USBD_IOERROR; 3751 goto ret; 3752 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3753 break; 3754 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3755 if (index == 1) 3756 port = UHCI_PORTSC1; 3757 else if (index == 2) 3758 port = UHCI_PORTSC2; 3759 else { 3760 err = USBD_IOERROR; 3761 goto ret; 3762 } 3763 switch(value) { 3764 case UHF_PORT_ENABLE: 3765 x = URWMASK(UREAD2(sc, port)); 3766 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3767 break; 3768 case UHF_PORT_SUSPEND: 3769 x = URWMASK(UREAD2(sc, port)); 3770 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 3771 break; 3772 case UHF_PORT_RESET: 3773 err = uhci_portreset(sc, index); 3774 goto ret; 3775 case UHF_PORT_POWER: 3776 /* Pretend we turned on power */ 3777 err = USBD_NORMAL_COMPLETION; 3778 goto ret; 3779 case UHF_C_PORT_CONNECTION: 3780 case UHF_C_PORT_ENABLE: 3781 case UHF_C_PORT_OVER_CURRENT: 3782 case UHF_PORT_CONNECTION: 3783 case UHF_PORT_OVER_CURRENT: 3784 case UHF_PORT_LOW_SPEED: 3785 case UHF_C_PORT_SUSPEND: 3786 case UHF_C_PORT_RESET: 3787 default: 3788 err = USBD_IOERROR; 3789 goto ret; 3790 } 3791 break; 3792 default: 3793 err = USBD_IOERROR; 3794 goto ret; 3795 } 3796 xfer->actlen = totlen; 3797 err = USBD_NORMAL_COMPLETION; 3798 ret: 3799 xfer->status = err; 3800 s = splusb(); 3801 usb_transfer_complete(xfer); 3802 splx(s); 3803 return (USBD_IN_PROGRESS); 3804 } 3805 3806 /* Abort a root control request. */ 3807 void 3808 uhci_root_ctrl_abort(usbd_xfer_handle xfer) 3809 { 3810 /* Nothing to do, all transfers are synchronous. */ 3811 } 3812 3813 /* Close the root pipe. */ 3814 void 3815 uhci_root_ctrl_close(usbd_pipe_handle pipe) 3816 { 3817 DPRINTF(("uhci_root_ctrl_close\n")); 3818 } 3819 3820 /* Abort a root interrupt request. */ 3821 void 3822 uhci_root_intr_abort(usbd_xfer_handle xfer) 3823 { 3824 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3825 3826 usb_uncallout(sc->sc_poll_handle, uhci_poll_hub, xfer); 3827 sc->sc_intr_xfer = NULL; 3828 3829 if (xfer->pipe->intrxfer == xfer) { 3830 DPRINTF(("uhci_root_intr_abort: remove\n")); 3831 xfer->pipe->intrxfer = 0; 3832 } 3833 xfer->status = USBD_CANCELLED; 3834 #ifdef DIAGNOSTIC 3835 UXFER(xfer)->iinfo.isdone = 1; 3836 #endif 3837 usb_transfer_complete(xfer); 3838 } 3839 3840 usbd_status 3841 uhci_root_intr_transfer(usbd_xfer_handle xfer) 3842 { 3843 usbd_status err; 3844 3845 /* Insert last in queue. */ 3846 err = usb_insert_transfer(xfer); 3847 if (err) 3848 return (err); 3849 3850 /* 3851 * Pipe isn't running (otherwise err would be USBD_INPROG), 3852 * start first 3853 */ 3854 return (uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3855 } 3856 3857 /* Start a transfer on the root interrupt pipe */ 3858 usbd_status 3859 uhci_root_intr_start(usbd_xfer_handle xfer) 3860 { 3861 usbd_pipe_handle pipe = xfer->pipe; 3862 uhci_softc_t *sc = pipe->device->bus->hci_private; 3863 unsigned int ival; 3864 3865 DPRINTFN(3, ("uhci_root_intr_start: xfer=%p len=%d flags=%d\n", 3866 xfer, xfer->length, xfer->flags)); 3867 3868 if (sc->sc_dying) 3869 return (USBD_IOERROR); 3870 3871 /* XXX temporary variable needed to avoid gcc3 warning */ 3872 ival = xfer->pipe->endpoint->edesc->bInterval; 3873 sc->sc_ival = mstohz(ival); 3874 usb_callout(sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 3875 sc->sc_intr_xfer = xfer; 3876 return (USBD_IN_PROGRESS); 3877 } 3878 3879 /* Close the root interrupt pipe. */ 3880 void 3881 uhci_root_intr_close(usbd_pipe_handle pipe) 3882 { 3883 uhci_softc_t *sc = pipe->device->bus->hci_private; 3884 3885 usb_uncallout(sc->sc_poll_handle, uhci_poll_hub, sc->sc_intr_xfer); 3886 sc->sc_intr_xfer = NULL; 3887 DPRINTF(("uhci_root_intr_close\n")); 3888 } 3889
Indexes created Tue Sep 30 20:09:53 GMT 2025