uhci.c revision 1.232.2.1
1 /* $NetBSD: uhci.c,v 1.232.2.1 2010/07/03 01:19:41 rmind Exp $ */ 2 /* $FreeBSD: src/sys/dev/usb/uhci.c,v 1.33 1999/11/17 22:33:41 n_hibma Exp $ */ 3 4 /* 5 * Copyright (c) 1998, 2004 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Lennart Augustsson (lennart (at) augustsson.net) at 10 * Carlstedt Research & Technology. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Universal Host Controller driver. 36 * Handles e.g. PIIX3 and PIIX4. 37 * 38 * UHCI spec: http://www.intel.com/technology/usb/spec.htm 39 * USB spec: http://www.usb.org/developers/docs/ 40 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 41 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.232.2.1 2010/07/03 01:19:41 rmind Exp $"); 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/malloc.h> 51 #include <sys/device.h> 52 #include <sys/select.h> 53 #include <sys/extent.h> 54 #include <uvm/uvm_extern.h> 55 #include <sys/proc.h> 56 #include <sys/queue.h> 57 #include <sys/bus.h> 58 59 #include <machine/endian.h> 60 61 #include <dev/usb/usb.h> 62 #include <dev/usb/usbdi.h> 63 #include <dev/usb/usbdivar.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/uhcireg.h> 68 #include <dev/usb/uhcivar.h> 69 #include <dev/usb/usbroothub_subr.h> 70 71 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 72 /*#define UHCI_CTL_LOOP */ 73 74 75 76 #ifdef UHCI_DEBUG 77 uhci_softc_t *thesc; 78 #define DPRINTF(x) if (uhcidebug) printf x 79 #define DPRINTFN(n,x) if (uhcidebug>(n)) printf x 80 int uhcidebug = 0; 81 int uhcinoloop = 0; 82 #else 83 #define DPRINTF(x) 84 #define DPRINTFN(n,x) 85 #endif 86 87 /* 88 * The UHCI controller is little endian, so on big endian machines 89 * the data stored in memory needs to be swapped. 90 */ 91 92 struct uhci_pipe { 93 struct usbd_pipe pipe; 94 int nexttoggle; 95 96 u_char aborting; 97 usbd_xfer_handle abortstart, abortend; 98 99 /* Info needed for different pipe kinds. */ 100 union { 101 /* Control pipe */ 102 struct { 103 uhci_soft_qh_t *sqh; 104 usb_dma_t reqdma; 105 uhci_soft_td_t *setup, *stat; 106 u_int length; 107 } ctl; 108 /* Interrupt pipe */ 109 struct { 110 int npoll; 111 int isread; 112 uhci_soft_qh_t **qhs; 113 } intr; 114 /* Bulk pipe */ 115 struct { 116 uhci_soft_qh_t *sqh; 117 u_int length; 118 int isread; 119 } bulk; 120 /* Iso pipe */ 121 struct iso { 122 uhci_soft_td_t **stds; 123 int next, inuse; 124 } iso; 125 } u; 126 }; 127 128 Static void uhci_globalreset(uhci_softc_t *); 129 Static usbd_status uhci_portreset(uhci_softc_t*, int); 130 Static void uhci_reset(uhci_softc_t *); 131 Static usbd_status uhci_run(uhci_softc_t *, int run); 132 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 133 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 134 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 135 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 136 #if 0 137 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 138 uhci_intr_info_t *); 139 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 140 #endif 141 142 Static void uhci_free_std_chain(uhci_softc_t *, 143 uhci_soft_td_t *, uhci_soft_td_t *); 144 Static usbd_status uhci_alloc_std_chain(struct uhci_pipe *, 145 uhci_softc_t *, int, int, u_int16_t, usb_dma_t *, 146 uhci_soft_td_t **, uhci_soft_td_t **); 147 Static void uhci_poll_hub(void *); 148 Static void uhci_waitintr(uhci_softc_t *, usbd_xfer_handle); 149 Static void uhci_check_intr(uhci_softc_t *, uhci_intr_info_t *); 150 Static void uhci_idone(uhci_intr_info_t *); 151 152 Static void uhci_abort_xfer(usbd_xfer_handle, usbd_status status); 153 154 Static void uhci_timeout(void *); 155 Static void uhci_timeout_task(void *); 156 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 157 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 158 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 159 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 160 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 161 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 162 Static void uhci_add_loop(uhci_softc_t *sc); 163 Static void uhci_rem_loop(uhci_softc_t *sc); 164 165 Static usbd_status uhci_setup_isoc(usbd_pipe_handle pipe); 166 Static void uhci_device_isoc_enter(usbd_xfer_handle); 167 168 Static usbd_status uhci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 169 Static void uhci_freem(struct usbd_bus *, usb_dma_t *); 170 171 Static usbd_xfer_handle uhci_allocx(struct usbd_bus *); 172 Static void uhci_freex(struct usbd_bus *, usbd_xfer_handle); 173 174 Static usbd_status uhci_device_ctrl_transfer(usbd_xfer_handle); 175 Static usbd_status uhci_device_ctrl_start(usbd_xfer_handle); 176 Static void uhci_device_ctrl_abort(usbd_xfer_handle); 177 Static void uhci_device_ctrl_close(usbd_pipe_handle); 178 Static void uhci_device_ctrl_done(usbd_xfer_handle); 179 180 Static usbd_status uhci_device_intr_transfer(usbd_xfer_handle); 181 Static usbd_status uhci_device_intr_start(usbd_xfer_handle); 182 Static void uhci_device_intr_abort(usbd_xfer_handle); 183 Static void uhci_device_intr_close(usbd_pipe_handle); 184 Static void uhci_device_intr_done(usbd_xfer_handle); 185 186 Static usbd_status uhci_device_bulk_transfer(usbd_xfer_handle); 187 Static usbd_status uhci_device_bulk_start(usbd_xfer_handle); 188 Static void uhci_device_bulk_abort(usbd_xfer_handle); 189 Static void uhci_device_bulk_close(usbd_pipe_handle); 190 Static void uhci_device_bulk_done(usbd_xfer_handle); 191 192 Static usbd_status uhci_device_isoc_transfer(usbd_xfer_handle); 193 Static usbd_status uhci_device_isoc_start(usbd_xfer_handle); 194 Static void uhci_device_isoc_abort(usbd_xfer_handle); 195 Static void uhci_device_isoc_close(usbd_pipe_handle); 196 Static void uhci_device_isoc_done(usbd_xfer_handle); 197 198 Static usbd_status uhci_root_ctrl_transfer(usbd_xfer_handle); 199 Static usbd_status uhci_root_ctrl_start(usbd_xfer_handle); 200 Static void uhci_root_ctrl_abort(usbd_xfer_handle); 201 Static void uhci_root_ctrl_close(usbd_pipe_handle); 202 Static void uhci_root_ctrl_done(usbd_xfer_handle); 203 204 Static usbd_status uhci_root_intr_transfer(usbd_xfer_handle); 205 Static usbd_status uhci_root_intr_start(usbd_xfer_handle); 206 Static void uhci_root_intr_abort(usbd_xfer_handle); 207 Static void uhci_root_intr_close(usbd_pipe_handle); 208 Static void uhci_root_intr_done(usbd_xfer_handle); 209 210 Static usbd_status uhci_open(usbd_pipe_handle); 211 Static void uhci_poll(struct usbd_bus *); 212 Static void uhci_softintr(void *); 213 214 Static usbd_status uhci_device_request(usbd_xfer_handle xfer); 215 216 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 217 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 218 Static usbd_status uhci_device_setintr(uhci_softc_t *sc, 219 struct uhci_pipe *pipe, int ival); 220 221 Static void uhci_device_clear_toggle(usbd_pipe_handle pipe); 222 Static void uhci_noop(usbd_pipe_handle pipe); 223 224 Static inline uhci_soft_qh_t *uhci_find_prev_qh(uhci_soft_qh_t *, 225 uhci_soft_qh_t *); 226 227 #ifdef UHCI_DEBUG 228 Static void uhci_dump_all(uhci_softc_t *); 229 Static void uhci_dumpregs(uhci_softc_t *); 230 Static void uhci_dump_qhs(uhci_soft_qh_t *); 231 Static void uhci_dump_qh(uhci_soft_qh_t *); 232 Static void uhci_dump_tds(uhci_soft_td_t *); 233 Static void uhci_dump_td(uhci_soft_td_t *); 234 Static void uhci_dump_ii(uhci_intr_info_t *ii); 235 void uhci_dump(void); 236 #endif 237 238 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 239 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 240 #define UWRITE1(sc, r, x) \ 241 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 242 } while (/*CONSTCOND*/0) 243 #define UWRITE2(sc, r, x) \ 244 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 245 } while (/*CONSTCOND*/0) 246 #define UWRITE4(sc, r, x) \ 247 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 248 } while (/*CONSTCOND*/0) 249 static __inline uint8_t 250 UREAD1(uhci_softc_t *sc, bus_size_t r) 251 { 252 253 UBARR(sc); 254 return bus_space_read_1(sc->iot, sc->ioh, r); 255 } 256 257 static __inline uint16_t 258 UREAD2(uhci_softc_t *sc, bus_size_t r) 259 { 260 261 UBARR(sc); 262 return bus_space_read_2(sc->iot, sc->ioh, r); 263 } 264 265 static __inline uint32_t 266 UREAD4(uhci_softc_t *sc, bus_size_t r) 267 { 268 269 UBARR(sc); 270 return bus_space_read_4(sc->iot, sc->ioh, r); 271 } 272 273 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 274 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 275 276 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 277 278 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 279 280 #define UHCI_INTR_ENDPT 1 281 282 const struct usbd_bus_methods uhci_bus_methods = { 283 uhci_open, 284 uhci_softintr, 285 uhci_poll, 286 uhci_allocm, 287 uhci_freem, 288 uhci_allocx, 289 uhci_freex, 290 }; 291 292 const struct usbd_pipe_methods uhci_root_ctrl_methods = { 293 uhci_root_ctrl_transfer, 294 uhci_root_ctrl_start, 295 uhci_root_ctrl_abort, 296 uhci_root_ctrl_close, 297 uhci_noop, 298 uhci_root_ctrl_done, 299 }; 300 301 const struct usbd_pipe_methods uhci_root_intr_methods = { 302 uhci_root_intr_transfer, 303 uhci_root_intr_start, 304 uhci_root_intr_abort, 305 uhci_root_intr_close, 306 uhci_noop, 307 uhci_root_intr_done, 308 }; 309 310 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 311 uhci_device_ctrl_transfer, 312 uhci_device_ctrl_start, 313 uhci_device_ctrl_abort, 314 uhci_device_ctrl_close, 315 uhci_noop, 316 uhci_device_ctrl_done, 317 }; 318 319 const struct usbd_pipe_methods uhci_device_intr_methods = { 320 uhci_device_intr_transfer, 321 uhci_device_intr_start, 322 uhci_device_intr_abort, 323 uhci_device_intr_close, 324 uhci_device_clear_toggle, 325 uhci_device_intr_done, 326 }; 327 328 const struct usbd_pipe_methods uhci_device_bulk_methods = { 329 uhci_device_bulk_transfer, 330 uhci_device_bulk_start, 331 uhci_device_bulk_abort, 332 uhci_device_bulk_close, 333 uhci_device_clear_toggle, 334 uhci_device_bulk_done, 335 }; 336 337 const struct usbd_pipe_methods uhci_device_isoc_methods = { 338 uhci_device_isoc_transfer, 339 uhci_device_isoc_start, 340 uhci_device_isoc_abort, 341 uhci_device_isoc_close, 342 uhci_noop, 343 uhci_device_isoc_done, 344 }; 345 346 #define uhci_add_intr_info(sc, ii) \ 347 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ii), list) 348 #define uhci_del_intr_info(ii) \ 349 do { \ 350 LIST_REMOVE((ii), list); \ 351 (ii)->list.le_prev = NULL; \ 352 } while (0) 353 #define uhci_active_intr_info(ii) ((ii)->list.le_prev != NULL) 354 355 Static inline uhci_soft_qh_t * 356 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 357 { 358 DPRINTFN(15,("uhci_find_prev_qh: pqh=%p sqh=%p\n", pqh, sqh)); 359 360 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 361 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 362 usb_syncmem(&pqh->dma, 363 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 364 sizeof(pqh->qh.qh_hlink), 365 BUS_DMASYNC_POSTWRITE); 366 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 367 printf("uhci_find_prev_qh: QH not found\n"); 368 return (NULL); 369 } 370 #endif 371 } 372 return (pqh); 373 } 374 375 void 376 uhci_globalreset(uhci_softc_t *sc) 377 { 378 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 379 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 380 UHCICMD(sc, 0); /* do nothing */ 381 } 382 383 usbd_status 384 uhci_init(uhci_softc_t *sc) 385 { 386 usbd_status err; 387 int i, j; 388 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 389 uhci_soft_td_t *std; 390 391 DPRINTFN(1,("uhci_init: start\n")); 392 393 #ifdef UHCI_DEBUG 394 thesc = sc; 395 396 if (uhcidebug > 2) 397 uhci_dumpregs(sc); 398 #endif 399 400 sc->sc_suspend = PWR_RESUME; 401 402 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 403 uhci_globalreset(sc); /* reset the controller */ 404 uhci_reset(sc); 405 406 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 407 USB_MEM_RESERVE); 408 409 /* Allocate and initialize real frame array. */ 410 err = usb_allocmem(&sc->sc_bus, 411 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 412 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 413 if (err) 414 return (err); 415 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 416 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 417 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 418 419 /* 420 * Allocate a TD, inactive, that hangs from the last QH. 421 * This is to avoid a bug in the PIIX that makes it run berserk 422 * otherwise. 423 */ 424 std = uhci_alloc_std(sc); 425 if (std == NULL) 426 return (USBD_NOMEM); 427 std->link.std = NULL; 428 std->td.td_link = htole32(UHCI_PTR_T); 429 std->td.td_status = htole32(0); /* inactive */ 430 std->td.td_token = htole32(0); 431 std->td.td_buffer = htole32(0); 432 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 433 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 434 435 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 436 lsqh = uhci_alloc_sqh(sc); 437 if (lsqh == NULL) 438 return (USBD_NOMEM); 439 lsqh->hlink = NULL; 440 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 441 lsqh->elink = std; 442 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 443 sc->sc_last_qh = lsqh; 444 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 445 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 446 447 /* Allocate the dummy QH where bulk traffic will be queued. */ 448 bsqh = uhci_alloc_sqh(sc); 449 if (bsqh == NULL) 450 return (USBD_NOMEM); 451 bsqh->hlink = lsqh; 452 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 453 bsqh->elink = NULL; 454 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 455 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 456 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 457 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 458 459 /* Allocate dummy QH where high speed control traffic will be queued. */ 460 chsqh = uhci_alloc_sqh(sc); 461 if (chsqh == NULL) 462 return (USBD_NOMEM); 463 chsqh->hlink = bsqh; 464 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 465 chsqh->elink = NULL; 466 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 467 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 468 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 469 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 470 471 /* Allocate dummy QH where control traffic will be queued. */ 472 clsqh = uhci_alloc_sqh(sc); 473 if (clsqh == NULL) 474 return (USBD_NOMEM); 475 clsqh->hlink = chsqh; 476 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 477 clsqh->elink = NULL; 478 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 479 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 480 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 481 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 482 483 /* 484 * Make all (virtual) frame list pointers point to the interrupt 485 * queue heads and the interrupt queue heads at the control 486 * queue head and point the physical frame list to the virtual. 487 */ 488 for(i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 489 std = uhci_alloc_std(sc); 490 sqh = uhci_alloc_sqh(sc); 491 if (std == NULL || sqh == NULL) 492 return (USBD_NOMEM); 493 std->link.sqh = sqh; 494 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 495 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 496 std->td.td_token = htole32(0); 497 std->td.td_buffer = htole32(0); 498 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 499 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 500 sqh->hlink = clsqh; 501 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 502 sqh->elink = NULL; 503 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 504 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 505 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 506 sc->sc_vframes[i].htd = std; 507 sc->sc_vframes[i].etd = std; 508 sc->sc_vframes[i].hqh = sqh; 509 sc->sc_vframes[i].eqh = sqh; 510 for (j = i; 511 j < UHCI_FRAMELIST_COUNT; 512 j += UHCI_VFRAMELIST_COUNT) 513 sc->sc_pframes[j] = htole32(std->physaddr); 514 } 515 usb_syncmem(&sc->sc_dma, 0, 516 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 517 BUS_DMASYNC_PREWRITE); 518 519 520 LIST_INIT(&sc->sc_intrhead); 521 522 SIMPLEQ_INIT(&sc->sc_free_xfers); 523 524 usb_callout_init(sc->sc_poll_handle); 525 526 /* Set up the bus struct. */ 527 sc->sc_bus.methods = &uhci_bus_methods; 528 sc->sc_bus.pipe_size = sizeof(struct uhci_pipe); 529 530 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 531 532 DPRINTFN(1,("uhci_init: enabling\n")); 533 534 err = uhci_run(sc, 1); /* and here we go... */ 535 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 536 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 537 return err; 538 } 539 540 int 541 uhci_activate(device_t self, enum devact act) 542 { 543 struct uhci_softc *sc = device_private(self); 544 545 switch (act) { 546 case DVACT_DEACTIVATE: 547 sc->sc_dying = 1; 548 return 0; 549 default: 550 return EOPNOTSUPP; 551 } 552 } 553 554 void 555 uhci_childdet(device_t self, device_t child) 556 { 557 struct uhci_softc *sc = device_private(self); 558 559 KASSERT(sc->sc_child == child); 560 sc->sc_child = NULL; 561 } 562 563 int 564 uhci_detach(struct uhci_softc *sc, int flags) 565 { 566 usbd_xfer_handle xfer; 567 int rv = 0; 568 569 if (sc->sc_child != NULL) 570 rv = config_detach(sc->sc_child, flags); 571 572 if (rv != 0) 573 return (rv); 574 575 /* Free all xfers associated with this HC. */ 576 for (;;) { 577 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 578 if (xfer == NULL) 579 break; 580 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 581 free(xfer, M_USB); 582 } 583 584 callout_halt(&sc->sc_poll_handle, NULL); 585 callout_destroy(&sc->sc_poll_handle); 586 587 /* XXX free other data structures XXX */ 588 589 return (rv); 590 } 591 592 usbd_status 593 uhci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 594 { 595 struct uhci_softc *sc = bus->hci_private; 596 usbd_status status; 597 u_int32_t n; 598 599 /* 600 * XXX 601 * Since we are allocating a buffer we can assume that we will 602 * need TDs for it. Since we don't want to allocate those from 603 * an interrupt context, we allocate them here and free them again. 604 * This is no guarantee that we'll get the TDs next time... 605 */ 606 n = size / 8; 607 if (n > 16) { 608 u_int32_t i; 609 uhci_soft_td_t **stds; 610 DPRINTF(("uhci_allocm: get %d TDs\n", n)); 611 stds = malloc(sizeof(uhci_soft_td_t *) * n, M_TEMP, 612 M_WAITOK|M_ZERO); 613 for(i=0; i < n; i++) 614 stds[i] = uhci_alloc_std(sc); 615 for(i=0; i < n; i++) 616 if (stds[i] != NULL) 617 uhci_free_std(sc, stds[i]); 618 free(stds, M_TEMP); 619 } 620 621 622 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 623 if (status == USBD_NOMEM) 624 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 625 return status; 626 } 627 628 void 629 uhci_freem(struct usbd_bus *bus, usb_dma_t *dma) 630 { 631 if (dma->block->flags & USB_DMA_RESERVE) { 632 usb_reserve_freem(&((struct uhci_softc *)bus)->sc_dma_reserve, 633 dma); 634 return; 635 } 636 usb_freemem(&((struct uhci_softc *)bus)->sc_bus, dma); 637 } 638 639 usbd_xfer_handle 640 uhci_allocx(struct usbd_bus *bus) 641 { 642 struct uhci_softc *sc = bus->hci_private; 643 usbd_xfer_handle xfer; 644 645 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 646 if (xfer != NULL) { 647 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 648 #ifdef DIAGNOSTIC 649 if (xfer->busy_free != XFER_FREE) { 650 printf("uhci_allocx: xfer=%p not free, 0x%08x\n", xfer, 651 xfer->busy_free); 652 } 653 #endif 654 } else { 655 xfer = malloc(sizeof(struct uhci_xfer), M_USB, M_NOWAIT); 656 } 657 if (xfer != NULL) { 658 memset(xfer, 0, sizeof (struct uhci_xfer)); 659 UXFER(xfer)->iinfo.sc = sc; 660 #ifdef DIAGNOSTIC 661 UXFER(xfer)->iinfo.isdone = 1; 662 xfer->busy_free = XFER_BUSY; 663 #endif 664 } 665 return (xfer); 666 } 667 668 void 669 uhci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 670 { 671 struct uhci_softc *sc = bus->hci_private; 672 673 #ifdef DIAGNOSTIC 674 if (xfer->busy_free != XFER_BUSY) { 675 printf("uhci_freex: xfer=%p not busy, 0x%08x\n", xfer, 676 xfer->busy_free); 677 } 678 xfer->busy_free = XFER_FREE; 679 if (!UXFER(xfer)->iinfo.isdone) { 680 printf("uhci_freex: !isdone\n"); 681 } 682 #endif 683 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 684 } 685 686 /* 687 * Handle suspend/resume. 688 * 689 * We need to switch to polling mode here, because this routine is 690 * called from an interrupt context. This is all right since we 691 * are almost suspended anyway. 692 */ 693 bool 694 uhci_resume(device_t dv, const pmf_qual_t *qual) 695 { 696 uhci_softc_t *sc = device_private(dv); 697 int cmd; 698 int s; 699 700 s = splhardusb(); 701 702 cmd = UREAD2(sc, UHCI_CMD); 703 sc->sc_bus.use_polling++; 704 UWRITE2(sc, UHCI_INTR, 0); 705 uhci_globalreset(sc); 706 uhci_reset(sc); 707 if (cmd & UHCI_CMD_RS) 708 uhci_run(sc, 0); 709 710 /* restore saved state */ 711 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 712 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 713 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 714 715 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 716 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 717 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 718 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 719 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 720 UHCICMD(sc, UHCI_CMD_MAXP); 721 uhci_run(sc, 1); /* and start traffic again */ 722 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 723 sc->sc_bus.use_polling--; 724 if (sc->sc_intr_xfer != NULL) 725 usb_callout(sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, 726 sc->sc_intr_xfer); 727 #ifdef UHCI_DEBUG 728 if (uhcidebug > 2) 729 uhci_dumpregs(sc); 730 #endif 731 732 sc->sc_suspend = PWR_RESUME; 733 splx(s); 734 735 return true; 736 } 737 738 bool 739 uhci_suspend(device_t dv, const pmf_qual_t *qual) 740 { 741 uhci_softc_t *sc = device_private(dv); 742 int cmd; 743 int s; 744 745 s = splhardusb(); 746 747 cmd = UREAD2(sc, UHCI_CMD); 748 749 #ifdef UHCI_DEBUG 750 if (uhcidebug > 2) 751 uhci_dumpregs(sc); 752 #endif 753 if (sc->sc_intr_xfer != NULL) 754 usb_uncallout(sc->sc_poll_handle, uhci_poll_hub, 755 sc->sc_intr_xfer); 756 sc->sc_suspend = PWR_SUSPEND; 757 sc->sc_bus.use_polling++; 758 759 uhci_run(sc, 0); /* stop the controller */ 760 cmd &= ~UHCI_CMD_RS; 761 762 /* save some state if BIOS doesn't */ 763 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 764 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 765 766 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 767 768 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 769 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 770 sc->sc_bus.use_polling--; 771 772 splx(s); 773 774 return true; 775 } 776 777 #ifdef UHCI_DEBUG 778 Static void 779 uhci_dumpregs(uhci_softc_t *sc) 780 { 781 DPRINTFN(-1,("%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, " 782 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 783 device_xname(sc->sc_dev), 784 UREAD2(sc, UHCI_CMD), 785 UREAD2(sc, UHCI_STS), 786 UREAD2(sc, UHCI_INTR), 787 UREAD2(sc, UHCI_FRNUM), 788 UREAD4(sc, UHCI_FLBASEADDR), 789 UREAD1(sc, UHCI_SOF), 790 UREAD2(sc, UHCI_PORTSC1), 791 UREAD2(sc, UHCI_PORTSC2))); 792 } 793 794 void 795 uhci_dump_td(uhci_soft_td_t *p) 796 { 797 char sbuf[128], sbuf2[128]; 798 799 800 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 801 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 802 DPRINTFN(-1,("TD(%p) at %08lx = link=0x%08lx status=0x%08lx " 803 "token=0x%08lx buffer=0x%08lx\n", 804 p, (long)p->physaddr, 805 (long)le32toh(p->td.td_link), 806 (long)le32toh(p->td.td_status), 807 (long)le32toh(p->td.td_token), 808 (long)le32toh(p->td.td_buffer))); 809 810 snprintb(sbuf, sizeof(sbuf), "\20\1T\2Q\3VF", 811 (u_int32_t)le32toh(p->td.td_link)); 812 snprintb(sbuf2, sizeof(sbuf2), 813 "\20\22BITSTUFF\23CRCTO\24NAK\25BABBLE\26DBUFFER\27" 814 "STALLED\30ACTIVE\31IOC\32ISO\33LS\36SPD", 815 (u_int32_t)le32toh(p->td.td_status)); 816 817 DPRINTFN(-1,(" %s %s,errcnt=%d,actlen=%d pid=%02x,addr=%d,endpt=%d," 818 "D=%d,maxlen=%d\n", sbuf, sbuf2, 819 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 820 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 821 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 822 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 823 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 824 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 825 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token)))); 826 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 827 BUS_DMASYNC_PREREAD); 828 } 829 830 void 831 uhci_dump_qh(uhci_soft_qh_t *sqh) 832 { 833 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 834 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 835 DPRINTFN(-1,("QH(%p) at %08x: hlink=%08x elink=%08x\n", sqh, 836 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 837 le32toh(sqh->qh.qh_elink))); 838 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 839 } 840 841 842 #if 1 843 void 844 uhci_dump(void) 845 { 846 uhci_dump_all(thesc); 847 } 848 #endif 849 850 void 851 uhci_dump_all(uhci_softc_t *sc) 852 { 853 uhci_dumpregs(sc); 854 printf("intrs=%d\n", sc->sc_bus.no_intrs); 855 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 856 uhci_dump_qh(sc->sc_lctl_start); 857 } 858 859 860 void 861 uhci_dump_qhs(uhci_soft_qh_t *sqh) 862 { 863 uhci_dump_qh(sqh); 864 865 /* uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 866 * Traverses sideways first, then down. 867 * 868 * QH1 869 * QH2 870 * No QH 871 * TD2.1 872 * TD2.2 873 * TD1.1 874 * etc. 875 * 876 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 877 */ 878 879 880 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 881 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 882 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 883 uhci_dump_qhs(sqh->hlink); 884 else 885 DPRINTF(("No QH\n")); 886 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 887 888 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 889 uhci_dump_tds(sqh->elink); 890 else 891 DPRINTF(("No TD\n")); 892 } 893 894 void 895 uhci_dump_tds(uhci_soft_td_t *std) 896 { 897 uhci_soft_td_t *td; 898 int stop; 899 900 for(td = std; td != NULL; td = td->link.std) { 901 uhci_dump_td(td); 902 903 /* Check whether the link pointer in this TD marks 904 * the link pointer as end of queue. This avoids 905 * printing the free list in case the queue/TD has 906 * already been moved there (seatbelt). 907 */ 908 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 909 sizeof(td->td.td_link), 910 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 911 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 912 le32toh(td->td.td_link) == 0); 913 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 914 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 915 if (stop) 916 break; 917 } 918 } 919 920 Static void 921 uhci_dump_ii(uhci_intr_info_t *ii) 922 { 923 usbd_pipe_handle pipe; 924 usb_endpoint_descriptor_t *ed; 925 usbd_device_handle dev; 926 927 #ifdef DIAGNOSTIC 928 #define DONE ii->isdone 929 #else 930 #define DONE 0 931 #endif 932 if (ii == NULL) { 933 printf("ii NULL\n"); 934 return; 935 } 936 if (ii->xfer == NULL) { 937 printf("ii %p: done=%d xfer=NULL\n", 938 ii, DONE); 939 return; 940 } 941 pipe = ii->xfer->pipe; 942 if (pipe == NULL) { 943 printf("ii %p: done=%d xfer=%p pipe=NULL\n", 944 ii, DONE, ii->xfer); 945 return; 946 } 947 if (pipe->endpoint == NULL) { 948 printf("ii %p: done=%d xfer=%p pipe=%p pipe->endpoint=NULL\n", 949 ii, DONE, ii->xfer, pipe); 950 return; 951 } 952 if (pipe->device == NULL) { 953 printf("ii %p: done=%d xfer=%p pipe=%p pipe->device=NULL\n", 954 ii, DONE, ii->xfer, pipe); 955 return; 956 } 957 ed = pipe->endpoint->edesc; 958 dev = pipe->device; 959 printf("ii %p: done=%d xfer=%p dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 960 ii, DONE, ii->xfer, dev, 961 UGETW(dev->ddesc.idVendor), 962 UGETW(dev->ddesc.idProduct), 963 dev->address, pipe, 964 ed->bEndpointAddress, ed->bmAttributes); 965 #undef DONE 966 } 967 968 void uhci_dump_iis(struct uhci_softc *sc); 969 void 970 uhci_dump_iis(struct uhci_softc *sc) 971 { 972 uhci_intr_info_t *ii; 973 974 printf("intr_info list:\n"); 975 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = LIST_NEXT(ii, list)) 976 uhci_dump_ii(ii); 977 } 978 979 void iidump(void); 980 void iidump(void) { uhci_dump_iis(thesc); } 981 982 #endif 983 984 /* 985 * This routine is executed periodically and simulates interrupts 986 * from the root controller interrupt pipe for port status change. 987 */ 988 void 989 uhci_poll_hub(void *addr) 990 { 991 usbd_xfer_handle xfer = addr; 992 usbd_pipe_handle pipe = xfer->pipe; 993 uhci_softc_t *sc; 994 int s; 995 u_char *p; 996 997 DPRINTFN(20, ("uhci_poll_hub\n")); 998 999 if (__predict_false(pipe->device == NULL || pipe->device->bus == NULL)) 1000 return; /* device has detached */ 1001 sc = pipe->device->bus->hci_private; 1002 usb_callout(sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 1003 1004 p = KERNADDR(&xfer->dmabuf, 0); 1005 p[0] = 0; 1006 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1007 p[0] |= 1<<1; 1008 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1009 p[0] |= 1<<2; 1010 if (p[0] == 0) 1011 /* No change, try again in a while */ 1012 return; 1013 1014 xfer->actlen = 1; 1015 xfer->status = USBD_NORMAL_COMPLETION; 1016 s = splusb(); 1017 xfer->device->bus->intr_context++; 1018 usb_transfer_complete(xfer); 1019 xfer->device->bus->intr_context--; 1020 splx(s); 1021 } 1022 1023 void 1024 uhci_root_intr_done(usbd_xfer_handle xfer) 1025 { 1026 } 1027 1028 void 1029 uhci_root_ctrl_done(usbd_xfer_handle xfer) 1030 { 1031 } 1032 1033 /* 1034 * Let the last QH loop back to the high speed control transfer QH. 1035 * This is what intel calls "bandwidth reclamation" and improves 1036 * USB performance a lot for some devices. 1037 * If we are already looping, just count it. 1038 */ 1039 void 1040 uhci_add_loop(uhci_softc_t *sc) { 1041 #ifdef UHCI_DEBUG 1042 if (uhcinoloop) 1043 return; 1044 #endif 1045 if (++sc->sc_loops == 1) { 1046 DPRINTFN(5,("uhci_start_loop: add\n")); 1047 /* Note, we don't loop back the soft pointer. */ 1048 sc->sc_last_qh->qh.qh_hlink = 1049 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 1050 usb_syncmem(&sc->sc_last_qh->dma, 1051 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1052 sizeof(sc->sc_last_qh->qh.qh_hlink), 1053 BUS_DMASYNC_PREWRITE); 1054 } 1055 } 1056 1057 void 1058 uhci_rem_loop(uhci_softc_t *sc) { 1059 #ifdef UHCI_DEBUG 1060 if (uhcinoloop) 1061 return; 1062 #endif 1063 if (--sc->sc_loops == 0) { 1064 DPRINTFN(5,("uhci_end_loop: remove\n")); 1065 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 1066 usb_syncmem(&sc->sc_last_qh->dma, 1067 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1068 sizeof(sc->sc_last_qh->qh.qh_hlink), 1069 BUS_DMASYNC_PREWRITE); 1070 } 1071 } 1072 1073 /* Add high speed control QH, called at splusb(). */ 1074 void 1075 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1076 { 1077 uhci_soft_qh_t *eqh; 1078 1079 SPLUSBCHECK; 1080 1081 DPRINTFN(10, ("uhci_add_ctrl: sqh=%p\n", sqh)); 1082 eqh = sc->sc_hctl_end; 1083 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1084 sizeof(eqh->qh.qh_hlink), 1085 BUS_DMASYNC_POSTWRITE); 1086 sqh->hlink = eqh->hlink; 1087 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1088 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1089 BUS_DMASYNC_PREWRITE); 1090 eqh->hlink = sqh; 1091 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1092 sc->sc_hctl_end = sqh; 1093 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1094 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1095 #ifdef UHCI_CTL_LOOP 1096 uhci_add_loop(sc); 1097 #endif 1098 } 1099 1100 /* Remove high speed control QH, called at splusb(). */ 1101 void 1102 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1103 { 1104 uhci_soft_qh_t *pqh; 1105 1106 SPLUSBCHECK; 1107 1108 DPRINTFN(10, ("uhci_remove_hs_ctrl: sqh=%p\n", sqh)); 1109 #ifdef UHCI_CTL_LOOP 1110 uhci_rem_loop(sc); 1111 #endif 1112 /* 1113 * The T bit should be set in the elink of the QH so that the HC 1114 * doesn't follow the pointer. This condition may fail if the 1115 * the transferred packet was short so that the QH still points 1116 * at the last used TD. 1117 * In this case we set the T bit and wait a little for the HC 1118 * to stop looking at the TD. 1119 * Note that if the TD chain is large enough, the controller 1120 * may still be looking at the chain at the end of this function. 1121 * uhci_free_std_chain() will make sure the controller stops 1122 * looking at it quickly, but until then we should not change 1123 * sqh->hlink. 1124 */ 1125 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1126 sizeof(sqh->qh.qh_elink), 1127 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1128 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1129 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1130 usb_syncmem(&sqh->dma, 1131 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1132 sizeof(sqh->qh.qh_elink), 1133 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1134 delay(UHCI_QH_REMOVE_DELAY); 1135 } 1136 1137 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1138 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1139 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1140 pqh->hlink = sqh->hlink; 1141 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1142 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1143 sizeof(pqh->qh.qh_hlink), 1144 BUS_DMASYNC_PREWRITE); 1145 delay(UHCI_QH_REMOVE_DELAY); 1146 if (sc->sc_hctl_end == sqh) 1147 sc->sc_hctl_end = pqh; 1148 } 1149 1150 /* Add low speed control QH, called at splusb(). */ 1151 void 1152 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1153 { 1154 uhci_soft_qh_t *eqh; 1155 1156 SPLUSBCHECK; 1157 1158 DPRINTFN(10, ("uhci_add_ls_ctrl: sqh=%p\n", sqh)); 1159 eqh = sc->sc_lctl_end; 1160 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1161 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1162 sqh->hlink = eqh->hlink; 1163 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1164 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1165 BUS_DMASYNC_PREWRITE); 1166 eqh->hlink = sqh; 1167 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1168 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1169 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1170 sc->sc_lctl_end = sqh; 1171 } 1172 1173 /* Remove low speed control QH, called at splusb(). */ 1174 void 1175 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1176 { 1177 uhci_soft_qh_t *pqh; 1178 1179 SPLUSBCHECK; 1180 1181 DPRINTFN(10, ("uhci_remove_ls_ctrl: sqh=%p\n", sqh)); 1182 /* See comment in uhci_remove_hs_ctrl() */ 1183 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1184 sizeof(sqh->qh.qh_elink), 1185 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1186 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1187 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1188 usb_syncmem(&sqh->dma, 1189 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1190 sizeof(sqh->qh.qh_elink), 1191 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1192 delay(UHCI_QH_REMOVE_DELAY); 1193 } 1194 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1195 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1196 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1197 pqh->hlink = sqh->hlink; 1198 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1199 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1200 sizeof(pqh->qh.qh_hlink), 1201 BUS_DMASYNC_PREWRITE); 1202 delay(UHCI_QH_REMOVE_DELAY); 1203 if (sc->sc_lctl_end == sqh) 1204 sc->sc_lctl_end = pqh; 1205 } 1206 1207 /* Add bulk QH, called at splusb(). */ 1208 void 1209 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1210 { 1211 uhci_soft_qh_t *eqh; 1212 1213 SPLUSBCHECK; 1214 1215 DPRINTFN(10, ("uhci_add_bulk: sqh=%p\n", sqh)); 1216 eqh = sc->sc_bulk_end; 1217 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1218 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1219 sqh->hlink = eqh->hlink; 1220 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1221 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1222 BUS_DMASYNC_PREWRITE); 1223 eqh->hlink = sqh; 1224 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1225 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1226 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1227 sc->sc_bulk_end = sqh; 1228 uhci_add_loop(sc); 1229 } 1230 1231 /* Remove bulk QH, called at splusb(). */ 1232 void 1233 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1234 { 1235 uhci_soft_qh_t *pqh; 1236 1237 SPLUSBCHECK; 1238 1239 DPRINTFN(10, ("uhci_remove_bulk: sqh=%p\n", sqh)); 1240 uhci_rem_loop(sc); 1241 /* See comment in uhci_remove_hs_ctrl() */ 1242 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1243 sizeof(sqh->qh.qh_elink), 1244 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1245 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1246 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1247 usb_syncmem(&sqh->dma, 1248 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1249 sizeof(sqh->qh.qh_elink), 1250 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1251 delay(UHCI_QH_REMOVE_DELAY); 1252 } 1253 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1254 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1255 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1256 pqh->hlink = sqh->hlink; 1257 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1258 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1259 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1260 delay(UHCI_QH_REMOVE_DELAY); 1261 if (sc->sc_bulk_end == sqh) 1262 sc->sc_bulk_end = pqh; 1263 } 1264 1265 Static int uhci_intr1(uhci_softc_t *); 1266 1267 int 1268 uhci_intr(void *arg) 1269 { 1270 uhci_softc_t *sc = arg; 1271 1272 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1273 return (0); 1274 1275 if (sc->sc_bus.use_polling || UREAD2(sc, UHCI_INTR) == 0) { 1276 #ifdef DIAGNOSTIC 1277 DPRINTFN(16, ("uhci_intr: ignored interrupt while polling\n")); 1278 #endif 1279 return (0); 1280 } 1281 1282 return (uhci_intr1(sc)); 1283 } 1284 1285 int 1286 uhci_intr1(uhci_softc_t *sc) 1287 { 1288 int status; 1289 int ack; 1290 1291 #ifdef UHCI_DEBUG 1292 if (uhcidebug > 15) { 1293 DPRINTF(("%s: uhci_intr1\n", device_xname(sc->sc_dev))); 1294 uhci_dumpregs(sc); 1295 } 1296 #endif 1297 1298 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1299 if (status == 0) /* The interrupt was not for us. */ 1300 return (0); 1301 1302 if (sc->sc_suspend != PWR_RESUME) { 1303 #ifdef DIAGNOSTIC 1304 printf("%s: interrupt while not operating ignored\n", 1305 device_xname(sc->sc_dev)); 1306 #endif 1307 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1308 return (0); 1309 } 1310 1311 ack = 0; 1312 if (status & UHCI_STS_USBINT) 1313 ack |= UHCI_STS_USBINT; 1314 if (status & UHCI_STS_USBEI) 1315 ack |= UHCI_STS_USBEI; 1316 if (status & UHCI_STS_RD) { 1317 ack |= UHCI_STS_RD; 1318 #ifdef UHCI_DEBUG 1319 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1320 #endif 1321 } 1322 if (status & UHCI_STS_HSE) { 1323 ack |= UHCI_STS_HSE; 1324 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1325 } 1326 if (status & UHCI_STS_HCPE) { 1327 ack |= UHCI_STS_HCPE; 1328 printf("%s: host controller process error\n", 1329 device_xname(sc->sc_dev)); 1330 } 1331 1332 /* When HCHalted=1 and Run/Stop=0 , it is normal */ 1333 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 1334 /* no acknowledge needed */ 1335 if (!sc->sc_dying) { 1336 printf("%s: host controller halted\n", 1337 device_xname(sc->sc_dev)); 1338 #ifdef UHCI_DEBUG 1339 uhci_dump_all(sc); 1340 #endif 1341 } 1342 sc->sc_dying = 1; 1343 } 1344 1345 if (!ack) 1346 return (0); /* nothing to acknowledge */ 1347 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1348 1349 sc->sc_bus.no_intrs++; 1350 usb_schedsoftintr(&sc->sc_bus); 1351 1352 DPRINTFN(15, ("%s: uhci_intr: exit\n", device_xname(sc->sc_dev))); 1353 1354 return (1); 1355 } 1356 1357 void 1358 uhci_softintr(void *v) 1359 { 1360 struct usbd_bus *bus = v; 1361 uhci_softc_t *sc = bus->hci_private; 1362 uhci_intr_info_t *ii, *nextii; 1363 1364 DPRINTFN(10,("%s: uhci_softintr (%d)\n", device_xname(sc->sc_dev), 1365 sc->sc_bus.intr_context)); 1366 1367 sc->sc_bus.intr_context++; 1368 1369 /* 1370 * Interrupts on UHCI really suck. When the host controller 1371 * interrupts because a transfer is completed there is no 1372 * way of knowing which transfer it was. You can scan down 1373 * the TDs and QHs of the previous frame to limit the search, 1374 * but that assumes that the interrupt was not delayed by more 1375 * than 1 ms, which may not always be true (e.g. after debug 1376 * output on a slow console). 1377 * We scan all interrupt descriptors to see if any have 1378 * completed. 1379 */ 1380 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = nextii) { 1381 nextii = LIST_NEXT(ii, list); 1382 uhci_check_intr(sc, ii); 1383 } 1384 1385 #ifdef USB_USE_SOFTINTR 1386 if (sc->sc_softwake) { 1387 sc->sc_softwake = 0; 1388 wakeup(&sc->sc_softwake); 1389 } 1390 #endif /* USB_USE_SOFTINTR */ 1391 1392 sc->sc_bus.intr_context--; 1393 } 1394 1395 /* Check for an interrupt. */ 1396 void 1397 uhci_check_intr(uhci_softc_t *sc, uhci_intr_info_t *ii) 1398 { 1399 uhci_soft_td_t *std, *lstd; 1400 u_int32_t status; 1401 1402 DPRINTFN(15, ("uhci_check_intr: ii=%p\n", ii)); 1403 #ifdef DIAGNOSTIC 1404 if (ii == NULL) { 1405 printf("uhci_check_intr: no ii? %p\n", ii); 1406 return; 1407 } 1408 #endif 1409 if (ii->xfer->status == USBD_CANCELLED || 1410 ii->xfer->status == USBD_TIMEOUT) { 1411 DPRINTF(("uhci_check_intr: aborted xfer=%p\n", ii->xfer)); 1412 return; 1413 } 1414 1415 if (ii->stdstart == NULL) 1416 return; 1417 lstd = ii->stdend; 1418 #ifdef DIAGNOSTIC 1419 if (lstd == NULL) { 1420 printf("uhci_check_intr: std==0\n"); 1421 return; 1422 } 1423 #endif 1424 /* 1425 * If the last TD is still active we need to check whether there 1426 * is an error somewhere in the middle, or whether there was a 1427 * short packet (SPD and not ACTIVE). 1428 */ 1429 usb_syncmem(&lstd->dma, 1430 lstd->offs + offsetof(uhci_td_t, td_status), 1431 sizeof(lstd->td.td_status), 1432 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1433 if (le32toh(lstd->td.td_status) & UHCI_TD_ACTIVE) { 1434 DPRINTFN(12, ("uhci_check_intr: active ii=%p\n", ii)); 1435 for (std = ii->stdstart; std != lstd; std = std->link.std) { 1436 usb_syncmem(&std->dma, 1437 std->offs + offsetof(uhci_td_t, td_status), 1438 sizeof(std->td.td_status), 1439 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1440 status = le32toh(std->td.td_status); 1441 usb_syncmem(&std->dma, 1442 std->offs + offsetof(uhci_td_t, td_status), 1443 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1444 /* If there's an active TD the xfer isn't done. */ 1445 if (status & UHCI_TD_ACTIVE) 1446 break; 1447 /* Any kind of error makes the xfer done. */ 1448 if (status & UHCI_TD_STALLED) 1449 goto done; 1450 /* We want short packets, and it is short: it's done */ 1451 usb_syncmem(&std->dma, 1452 std->offs + offsetof(uhci_td_t, td_token), 1453 sizeof(std->td.td_token), 1454 BUS_DMASYNC_POSTWRITE); 1455 if ((status & UHCI_TD_SPD) && 1456 UHCI_TD_GET_ACTLEN(status) < 1457 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) 1458 goto done; 1459 } 1460 DPRINTFN(12, ("uhci_check_intr: ii=%p std=%p still active\n", 1461 ii, ii->stdstart)); 1462 usb_syncmem(&lstd->dma, 1463 lstd->offs + offsetof(uhci_td_t, td_status), 1464 sizeof(lstd->td.td_status), 1465 BUS_DMASYNC_PREREAD); 1466 return; 1467 } 1468 done: 1469 DPRINTFN(12, ("uhci_check_intr: ii=%p done\n", ii)); 1470 usb_uncallout(ii->xfer->timeout_handle, uhci_timeout, ii); 1471 uhci_idone(ii); 1472 } 1473 1474 /* Called at splusb() */ 1475 void 1476 uhci_idone(uhci_intr_info_t *ii) 1477 { 1478 usbd_xfer_handle xfer = ii->xfer; 1479 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 1480 uhci_soft_td_t *std; 1481 u_int32_t status = 0, nstatus; 1482 int actlen; 1483 1484 DPRINTFN(12, ("uhci_idone: ii=%p\n", ii)); 1485 #ifdef DIAGNOSTIC 1486 { 1487 int s = splhigh(); 1488 if (ii->isdone) { 1489 splx(s); 1490 #ifdef UHCI_DEBUG 1491 printf("uhci_idone: ii is done!\n "); 1492 uhci_dump_ii(ii); 1493 #else 1494 printf("uhci_idone: ii=%p is done!\n", ii); 1495 #endif 1496 return; 1497 } 1498 ii->isdone = 1; 1499 splx(s); 1500 } 1501 #endif 1502 1503 if (xfer->nframes != 0) { 1504 /* Isoc transfer, do things differently. */ 1505 uhci_soft_td_t **stds = upipe->u.iso.stds; 1506 int i, n, nframes, len; 1507 1508 DPRINTFN(5,("uhci_idone: ii=%p isoc ready\n", ii)); 1509 1510 nframes = xfer->nframes; 1511 actlen = 0; 1512 n = UXFER(xfer)->curframe; 1513 for (i = 0; i < nframes; i++) { 1514 std = stds[n]; 1515 #ifdef UHCI_DEBUG 1516 if (uhcidebug > 5) { 1517 DPRINTFN(-1,("uhci_idone: isoc TD %d\n", i)); 1518 uhci_dump_td(std); 1519 } 1520 #endif 1521 if (++n >= UHCI_VFRAMELIST_COUNT) 1522 n = 0; 1523 usb_syncmem(&std->dma, 1524 std->offs + offsetof(uhci_td_t, td_status), 1525 sizeof(std->td.td_status), 1526 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1527 status = le32toh(std->td.td_status); 1528 len = UHCI_TD_GET_ACTLEN(status); 1529 xfer->frlengths[i] = len; 1530 actlen += len; 1531 } 1532 upipe->u.iso.inuse -= nframes; 1533 xfer->actlen = actlen; 1534 xfer->status = USBD_NORMAL_COMPLETION; 1535 goto end; 1536 } 1537 1538 #ifdef UHCI_DEBUG 1539 DPRINTFN(10, ("uhci_idone: ii=%p, xfer=%p, pipe=%p ready\n", 1540 ii, xfer, upipe)); 1541 if (uhcidebug > 10) 1542 uhci_dump_tds(ii->stdstart); 1543 #endif 1544 1545 /* The transfer is done, compute actual length and status. */ 1546 actlen = 0; 1547 for (std = ii->stdstart; std != NULL; std = std->link.std) { 1548 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1549 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1550 nstatus = le32toh(std->td.td_status); 1551 if (nstatus & UHCI_TD_ACTIVE) 1552 break; 1553 1554 status = nstatus; 1555 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1556 UHCI_TD_PID_SETUP) 1557 actlen += UHCI_TD_GET_ACTLEN(status); 1558 else { 1559 /* 1560 * UHCI will report CRCTO in addition to a STALL or NAK 1561 * for a SETUP transaction. See section 3.2.2, "TD 1562 * CONTROL AND STATUS". 1563 */ 1564 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1565 status &= ~UHCI_TD_CRCTO; 1566 } 1567 } 1568 /* If there are left over TDs we need to update the toggle. */ 1569 if (std != NULL) 1570 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1571 1572 status &= UHCI_TD_ERROR; 1573 DPRINTFN(10, ("uhci_idone: actlen=%d, status=0x%x\n", 1574 actlen, status)); 1575 xfer->actlen = actlen; 1576 if (status != 0) { 1577 #ifdef UHCI_DEBUG 1578 char sbuf[128]; 1579 1580 snprintb(sbuf, sizeof(sbuf), 1581 "\20\22BITSTUFF\23CRCTO\24NAK\25" 1582 "BABBLE\26DBUFFER\27STALLED\30ACTIVE",(u_int32_t)status); 1583 1584 DPRINTFN((status == UHCI_TD_STALLED)*10, 1585 ("uhci_idone: error, addr=%d, endpt=0x%02x, " 1586 "status 0x%s\n", 1587 xfer->pipe->device->address, 1588 xfer->pipe->endpoint->edesc->bEndpointAddress, 1589 sbuf)); 1590 #endif 1591 1592 if (status == UHCI_TD_STALLED) 1593 xfer->status = USBD_STALLED; 1594 else 1595 xfer->status = USBD_IOERROR; /* more info XXX */ 1596 } else { 1597 xfer->status = USBD_NORMAL_COMPLETION; 1598 } 1599 1600 end: 1601 usb_transfer_complete(xfer); 1602 DPRINTFN(12, ("uhci_idone: ii=%p done\n", ii)); 1603 } 1604 1605 /* 1606 * Called when a request does not complete. 1607 */ 1608 void 1609 uhci_timeout(void *addr) 1610 { 1611 uhci_intr_info_t *ii = addr; 1612 struct uhci_xfer *uxfer = UXFER(ii->xfer); 1613 struct uhci_pipe *upipe = (struct uhci_pipe *)uxfer->xfer.pipe; 1614 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 1615 1616 DPRINTF(("uhci_timeout: uxfer=%p\n", uxfer)); 1617 1618 if (sc->sc_dying) { 1619 uhci_abort_xfer(&uxfer->xfer, USBD_TIMEOUT); 1620 return; 1621 } 1622 1623 /* Execute the abort in a process context. */ 1624 usb_init_task(&uxfer->abort_task, uhci_timeout_task, ii->xfer); 1625 usb_add_task(uxfer->xfer.pipe->device, &uxfer->abort_task, 1626 USB_TASKQ_HC); 1627 } 1628 1629 void 1630 uhci_timeout_task(void *addr) 1631 { 1632 usbd_xfer_handle xfer = addr; 1633 int s; 1634 1635 DPRINTF(("uhci_timeout_task: xfer=%p\n", xfer)); 1636 1637 s = splusb(); 1638 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1639 splx(s); 1640 } 1641 1642 /* 1643 * Wait here until controller claims to have an interrupt. 1644 * Then call uhci_intr and return. Use timeout to avoid waiting 1645 * too long. 1646 * Only used during boot when interrupts are not enabled yet. 1647 */ 1648 void 1649 uhci_waitintr(uhci_softc_t *sc, usbd_xfer_handle xfer) 1650 { 1651 int timo = xfer->timeout; 1652 uhci_intr_info_t *ii; 1653 1654 DPRINTFN(10,("uhci_waitintr: timeout = %dms\n", timo)); 1655 1656 xfer->status = USBD_IN_PROGRESS; 1657 for (; timo >= 0; timo--) { 1658 usb_delay_ms(&sc->sc_bus, 1); 1659 DPRINTFN(20,("uhci_waitintr: 0x%04x\n", UREAD2(sc, UHCI_STS))); 1660 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1661 uhci_intr1(sc); 1662 if (xfer->status != USBD_IN_PROGRESS) 1663 return; 1664 } 1665 } 1666 1667 /* Timeout */ 1668 DPRINTF(("uhci_waitintr: timeout\n")); 1669 for (ii = LIST_FIRST(&sc->sc_intrhead); 1670 ii != NULL && ii->xfer != xfer; 1671 ii = LIST_NEXT(ii, list)) 1672 ; 1673 #ifdef DIAGNOSTIC 1674 if (ii == NULL) 1675 panic("uhci_waitintr: lost intr_info"); 1676 #endif 1677 uhci_idone(ii); 1678 } 1679 1680 void 1681 uhci_poll(struct usbd_bus *bus) 1682 { 1683 uhci_softc_t *sc = bus->hci_private; 1684 1685 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) 1686 uhci_intr1(sc); 1687 } 1688 1689 void 1690 uhci_reset(uhci_softc_t *sc) 1691 { 1692 int n; 1693 1694 UHCICMD(sc, UHCI_CMD_HCRESET); 1695 /* The reset bit goes low when the controller is done. */ 1696 for (n = 0; n < UHCI_RESET_TIMEOUT && 1697 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1698 usb_delay_ms(&sc->sc_bus, 1); 1699 if (n >= UHCI_RESET_TIMEOUT) 1700 printf("%s: controller did not reset\n", 1701 device_xname(sc->sc_dev)); 1702 } 1703 1704 usbd_status 1705 uhci_run(uhci_softc_t *sc, int run) 1706 { 1707 int s, n, running; 1708 u_int16_t cmd; 1709 1710 run = run != 0; 1711 s = splhardusb(); 1712 DPRINTF(("uhci_run: setting run=%d\n", run)); 1713 cmd = UREAD2(sc, UHCI_CMD); 1714 if (run) 1715 cmd |= UHCI_CMD_RS; 1716 else 1717 cmd &= ~UHCI_CMD_RS; 1718 UHCICMD(sc, cmd); 1719 for(n = 0; n < 10; n++) { 1720 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1721 /* return when we've entered the state we want */ 1722 if (run == running) { 1723 splx(s); 1724 DPRINTF(("uhci_run: done cmd=0x%x sts=0x%x\n", 1725 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS))); 1726 return (USBD_NORMAL_COMPLETION); 1727 } 1728 usb_delay_ms(&sc->sc_bus, 1); 1729 } 1730 splx(s); 1731 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1732 run ? "start" : "stop"); 1733 return (USBD_IOERROR); 1734 } 1735 1736 /* 1737 * Memory management routines. 1738 * uhci_alloc_std allocates TDs 1739 * uhci_alloc_sqh allocates QHs 1740 * These two routines do their own free list management, 1741 * partly for speed, partly because allocating DMAable memory 1742 * has page size granularaity so much memory would be wasted if 1743 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1744 */ 1745 1746 uhci_soft_td_t * 1747 uhci_alloc_std(uhci_softc_t *sc) 1748 { 1749 uhci_soft_td_t *std; 1750 usbd_status err; 1751 int i, offs; 1752 usb_dma_t dma; 1753 1754 if (sc->sc_freetds == NULL) { 1755 DPRINTFN(2,("uhci_alloc_std: allocating chunk\n")); 1756 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1757 UHCI_TD_ALIGN, &dma); 1758 if (err) 1759 return (0); 1760 for(i = 0; i < UHCI_STD_CHUNK; i++) { 1761 offs = i * UHCI_STD_SIZE; 1762 std = KERNADDR(&dma, offs); 1763 std->physaddr = DMAADDR(&dma, offs); 1764 std->dma = dma; 1765 std->offs = offs; 1766 std->link.std = sc->sc_freetds; 1767 sc->sc_freetds = std; 1768 } 1769 } 1770 std = sc->sc_freetds; 1771 sc->sc_freetds = std->link.std; 1772 memset(&std->td, 0, sizeof(uhci_td_t)); 1773 return std; 1774 } 1775 1776 void 1777 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1778 { 1779 #ifdef DIAGNOSTIC 1780 #define TD_IS_FREE 0x12345678 1781 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1782 printf("uhci_free_std: freeing free TD %p\n", std); 1783 return; 1784 } 1785 std->td.td_token = htole32(TD_IS_FREE); 1786 #endif 1787 std->link.std = sc->sc_freetds; 1788 sc->sc_freetds = std; 1789 } 1790 1791 uhci_soft_qh_t * 1792 uhci_alloc_sqh(uhci_softc_t *sc) 1793 { 1794 uhci_soft_qh_t *sqh; 1795 usbd_status err; 1796 int i, offs; 1797 usb_dma_t dma; 1798 1799 if (sc->sc_freeqhs == NULL) { 1800 DPRINTFN(2, ("uhci_alloc_sqh: allocating chunk\n")); 1801 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1802 UHCI_QH_ALIGN, &dma); 1803 if (err) 1804 return (0); 1805 for(i = 0; i < UHCI_SQH_CHUNK; i++) { 1806 offs = i * UHCI_SQH_SIZE; 1807 sqh = KERNADDR(&dma, offs); 1808 sqh->physaddr = DMAADDR(&dma, offs); 1809 sqh->dma = dma; 1810 sqh->offs = offs; 1811 sqh->hlink = sc->sc_freeqhs; 1812 sc->sc_freeqhs = sqh; 1813 } 1814 } 1815 sqh = sc->sc_freeqhs; 1816 sc->sc_freeqhs = sqh->hlink; 1817 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1818 return (sqh); 1819 } 1820 1821 void 1822 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1823 { 1824 sqh->hlink = sc->sc_freeqhs; 1825 sc->sc_freeqhs = sqh; 1826 } 1827 1828 void 1829 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1830 uhci_soft_td_t *stdend) 1831 { 1832 uhci_soft_td_t *p; 1833 1834 /* 1835 * to avoid race condition with the controller which may be looking 1836 * at this chain, we need to first invalidate all links, and 1837 * then wait for the controller to move to another queue 1838 */ 1839 for (p = std; p != stdend; p = p->link.std) { 1840 usb_syncmem(&p->dma, 1841 p->offs + offsetof(uhci_td_t, td_link), 1842 sizeof(p->td.td_link), 1843 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1844 if ((p->td.td_link & UHCI_PTR_T) == 0) { 1845 p->td.td_link = UHCI_PTR_T; 1846 usb_syncmem(&p->dma, 1847 p->offs + offsetof(uhci_td_t, td_link), 1848 sizeof(p->td.td_link), 1849 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1850 } 1851 } 1852 delay(UHCI_QH_REMOVE_DELAY); 1853 1854 for (; std != stdend; std = p) { 1855 p = std->link.std; 1856 uhci_free_std(sc, std); 1857 } 1858 } 1859 1860 usbd_status 1861 uhci_alloc_std_chain(struct uhci_pipe *upipe, uhci_softc_t *sc, int len, 1862 int rd, u_int16_t flags, usb_dma_t *dma, 1863 uhci_soft_td_t **sp, uhci_soft_td_t **ep) 1864 { 1865 uhci_soft_td_t *p, *lastp; 1866 uhci_physaddr_t lastlink; 1867 int i, ntd, l, tog, maxp; 1868 u_int32_t status; 1869 int addr = upipe->pipe.device->address; 1870 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 1871 1872 DPRINTFN(8, ("uhci_alloc_std_chain: addr=%d endpt=%d len=%d speed=%d " 1873 "flags=0x%x\n", addr, UE_GET_ADDR(endpt), len, 1874 upipe->pipe.device->speed, flags)); 1875 maxp = UGETW(upipe->pipe.endpoint->edesc->wMaxPacketSize); 1876 if (maxp == 0) { 1877 printf("uhci_alloc_std_chain: maxp=0\n"); 1878 return (USBD_INVAL); 1879 } 1880 ntd = (len + maxp - 1) / maxp; 1881 if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0) 1882 ntd++; 1883 DPRINTFN(10, ("uhci_alloc_std_chain: maxp=%d ntd=%d\n", maxp, ntd)); 1884 if (ntd == 0) { 1885 *sp = *ep = 0; 1886 DPRINTFN(-1,("uhci_alloc_std_chain: ntd=0\n")); 1887 return (USBD_NORMAL_COMPLETION); 1888 } 1889 tog = upipe->nexttoggle; 1890 if (ntd % 2 == 0) 1891 tog ^= 1; 1892 upipe->nexttoggle = tog ^ 1; 1893 lastp = NULL; 1894 lastlink = UHCI_PTR_T; 1895 ntd--; 1896 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 1897 if (upipe->pipe.device->speed == USB_SPEED_LOW) 1898 status |= UHCI_TD_LS; 1899 if (flags & USBD_SHORT_XFER_OK) 1900 status |= UHCI_TD_SPD; 1901 usb_syncmem(dma, 0, len, 1902 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1903 for (i = ntd; i >= 0; i--) { 1904 p = uhci_alloc_std(sc); 1905 if (p == NULL) { 1906 KASSERT(lastp != NULL); 1907 uhci_free_std_chain(sc, lastp, NULL); 1908 return (USBD_NOMEM); 1909 } 1910 p->link.std = lastp; 1911 p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD); 1912 lastp = p; 1913 lastlink = p->physaddr; 1914 p->td.td_status = htole32(status); 1915 if (i == ntd) { 1916 /* last TD */ 1917 l = len % maxp; 1918 if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER)) 1919 l = maxp; 1920 *ep = p; 1921 } else 1922 l = maxp; 1923 p->td.td_token = 1924 htole32(rd ? UHCI_TD_IN (l, endpt, addr, tog) : 1925 UHCI_TD_OUT(l, endpt, addr, tog)); 1926 p->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 1927 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 1928 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1929 tog ^= 1; 1930 } 1931 *sp = lastp; 1932 DPRINTFN(10, ("uhci_alloc_std_chain: nexttog=%d\n", 1933 upipe->nexttoggle)); 1934 return (USBD_NORMAL_COMPLETION); 1935 } 1936 1937 void 1938 uhci_device_clear_toggle(usbd_pipe_handle pipe) 1939 { 1940 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 1941 upipe->nexttoggle = 0; 1942 } 1943 1944 void 1945 uhci_noop(usbd_pipe_handle pipe) 1946 { 1947 } 1948 1949 usbd_status 1950 uhci_device_bulk_transfer(usbd_xfer_handle xfer) 1951 { 1952 usbd_status err; 1953 1954 /* Insert last in queue. */ 1955 err = usb_insert_transfer(xfer); 1956 if (err) 1957 return (err); 1958 1959 /* 1960 * Pipe isn't running (otherwise err would be USBD_INPROG), 1961 * so start it first. 1962 */ 1963 return (uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1964 } 1965 1966 usbd_status 1967 uhci_device_bulk_start(usbd_xfer_handle xfer) 1968 { 1969 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 1970 usbd_device_handle dev = upipe->pipe.device; 1971 uhci_softc_t *sc = dev->bus->hci_private; 1972 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 1973 uhci_soft_td_t *data, *dataend; 1974 uhci_soft_qh_t *sqh; 1975 usbd_status err; 1976 int len, isread, endpt; 1977 int s; 1978 1979 DPRINTFN(3, ("uhci_device_bulk_start: xfer=%p len=%d flags=%d ii=%p\n", 1980 xfer, xfer->length, xfer->flags, ii)); 1981 1982 if (sc->sc_dying) 1983 return (USBD_IOERROR); 1984 1985 #ifdef DIAGNOSTIC 1986 if (xfer->rqflags & URQ_REQUEST) 1987 panic("uhci_device_bulk_transfer: a request"); 1988 #endif 1989 1990 len = xfer->length; 1991 endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 1992 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 1993 sqh = upipe->u.bulk.sqh; 1994 1995 upipe->u.bulk.isread = isread; 1996 upipe->u.bulk.length = len; 1997 1998 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->flags, 1999 &xfer->dmabuf, &data, &dataend); 2000 if (err) 2001 return (err); 2002 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2003 usb_syncmem(&dataend->dma, 2004 dataend->offs + offsetof(uhci_td_t, td_status), 2005 sizeof(dataend->td.td_status), 2006 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2007 2008 2009 #ifdef UHCI_DEBUG 2010 if (uhcidebug > 8) { 2011 DPRINTF(("uhci_device_bulk_transfer: data(1)\n")); 2012 uhci_dump_tds(data); 2013 } 2014 #endif 2015 2016 /* Set up interrupt info. */ 2017 ii->xfer = xfer; 2018 ii->stdstart = data; 2019 ii->stdend = dataend; 2020 #ifdef DIAGNOSTIC 2021 if (!ii->isdone) { 2022 printf("uhci_device_bulk_transfer: not done, ii=%p\n", ii); 2023 } 2024 ii->isdone = 0; 2025 #endif 2026 2027 sqh->elink = data; 2028 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2029 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2030 2031 s = splusb(); 2032 uhci_add_bulk(sc, sqh); 2033 uhci_add_intr_info(sc, ii); 2034 2035 if (xfer->timeout && !sc->sc_bus.use_polling) { 2036 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 2037 uhci_timeout, ii); 2038 } 2039 xfer->status = USBD_IN_PROGRESS; 2040 splx(s); 2041 2042 #ifdef UHCI_DEBUG 2043 if (uhcidebug > 10) { 2044 DPRINTF(("uhci_device_bulk_transfer: data(2)\n")); 2045 uhci_dump_tds(data); 2046 } 2047 #endif 2048 2049 if (sc->sc_bus.use_polling) 2050 uhci_waitintr(sc, xfer); 2051 2052 return (USBD_IN_PROGRESS); 2053 } 2054 2055 /* Abort a device bulk request. */ 2056 void 2057 uhci_device_bulk_abort(usbd_xfer_handle xfer) 2058 { 2059 DPRINTF(("uhci_device_bulk_abort:\n")); 2060 uhci_abort_xfer(xfer, USBD_CANCELLED); 2061 } 2062 2063 /* 2064 * Abort a device request. 2065 * If this routine is called at splusb() it guarantees that the request 2066 * will be removed from the hardware scheduling and that the callback 2067 * for it will be called with USBD_CANCELLED status. 2068 * It's impossible to guarantee that the requested transfer will not 2069 * have happened since the hardware runs concurrently. 2070 * If the transaction has already happened we rely on the ordinary 2071 * interrupt processing to process it. 2072 */ 2073 void 2074 uhci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2075 { 2076 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2077 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2078 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 2079 uhci_soft_td_t *std; 2080 int s; 2081 int wake; 2082 2083 DPRINTFN(1,("uhci_abort_xfer: xfer=%p, status=%d\n", xfer, status)); 2084 2085 if (sc->sc_dying) { 2086 /* If we're dying, just do the software part. */ 2087 s = splusb(); 2088 xfer->status = status; /* make software ignore it */ 2089 usb_uncallout(xfer->timeout_handle, uhci_timeout, xfer); 2090 usb_transfer_complete(xfer); 2091 splx(s); 2092 return; 2093 } 2094 2095 if (xfer->device->bus->intr_context || !curproc) 2096 panic("uhci_abort_xfer: not in process context"); 2097 2098 /* 2099 * If an abort is already in progress then just wait for it to 2100 * complete and return. 2101 */ 2102 if (xfer->hcflags & UXFER_ABORTING) { 2103 DPRINTFN(2, ("uhci_abort_xfer: already aborting\n")); 2104 #ifdef DIAGNOSTIC 2105 if (status == USBD_TIMEOUT) 2106 printf("uhci_abort_xfer: TIMEOUT while aborting\n"); 2107 #endif 2108 /* Override the status which might be USBD_TIMEOUT. */ 2109 xfer->status = status; 2110 DPRINTFN(2, ("uhci_abort_xfer: waiting for abort to finish\n")); 2111 xfer->hcflags |= UXFER_ABORTWAIT; 2112 while (xfer->hcflags & UXFER_ABORTING) 2113 tsleep(&xfer->hcflags, PZERO, "uhciaw", 0); 2114 return; 2115 } 2116 xfer->hcflags |= UXFER_ABORTING; 2117 2118 /* 2119 * Step 1: Make interrupt routine and hardware ignore xfer. 2120 */ 2121 s = splusb(); 2122 xfer->status = status; /* make software ignore it */ 2123 usb_uncallout(xfer->timeout_handle, uhci_timeout, ii); 2124 DPRINTFN(1,("uhci_abort_xfer: stop ii=%p\n", ii)); 2125 for (std = ii->stdstart; std != NULL; std = std->link.std) { 2126 usb_syncmem(&std->dma, 2127 std->offs + offsetof(uhci_td_t, td_status), 2128 sizeof(std->td.td_status), 2129 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2130 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2131 usb_syncmem(&std->dma, 2132 std->offs + offsetof(uhci_td_t, td_status), 2133 sizeof(std->td.td_status), 2134 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2135 } 2136 splx(s); 2137 2138 /* 2139 * Step 2: Wait until we know hardware has finished any possible 2140 * use of the xfer. Also make sure the soft interrupt routine 2141 * has run. 2142 */ 2143 usb_delay_ms(upipe->pipe.device->bus, 2); /* Hardware finishes in 1ms */ 2144 s = splusb(); 2145 #ifdef USB_USE_SOFTINTR 2146 sc->sc_softwake = 1; 2147 #endif /* USB_USE_SOFTINTR */ 2148 usb_schedsoftintr(&sc->sc_bus); 2149 #ifdef USB_USE_SOFTINTR 2150 DPRINTFN(1,("uhci_abort_xfer: tsleep\n")); 2151 tsleep(&sc->sc_softwake, PZERO, "uhciab", 0); 2152 #endif /* USB_USE_SOFTINTR */ 2153 splx(s); 2154 2155 /* 2156 * Step 3: Execute callback. 2157 */ 2158 DPRINTFN(1,("uhci_abort_xfer: callback\n")); 2159 s = splusb(); 2160 #ifdef DIAGNOSTIC 2161 ii->isdone = 1; 2162 #endif 2163 wake = xfer->hcflags & UXFER_ABORTWAIT; 2164 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2165 usb_transfer_complete(xfer); 2166 if (wake) 2167 wakeup(&xfer->hcflags); 2168 splx(s); 2169 } 2170 2171 /* Close a device bulk pipe. */ 2172 void 2173 uhci_device_bulk_close(usbd_pipe_handle pipe) 2174 { 2175 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2176 usbd_device_handle dev = upipe->pipe.device; 2177 uhci_softc_t *sc = dev->bus->hci_private; 2178 2179 uhci_free_sqh(sc, upipe->u.bulk.sqh); 2180 } 2181 2182 usbd_status 2183 uhci_device_ctrl_transfer(usbd_xfer_handle xfer) 2184 { 2185 usbd_status err; 2186 2187 /* Insert last in queue. */ 2188 err = usb_insert_transfer(xfer); 2189 if (err) 2190 return (err); 2191 2192 /* 2193 * Pipe isn't running (otherwise err would be USBD_INPROG), 2194 * so start it first. 2195 */ 2196 return (uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2197 } 2198 2199 usbd_status 2200 uhci_device_ctrl_start(usbd_xfer_handle xfer) 2201 { 2202 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2203 usbd_status err; 2204 2205 if (sc->sc_dying) 2206 return (USBD_IOERROR); 2207 2208 #ifdef DIAGNOSTIC 2209 if (!(xfer->rqflags & URQ_REQUEST)) 2210 panic("uhci_device_ctrl_transfer: not a request"); 2211 #endif 2212 2213 err = uhci_device_request(xfer); 2214 if (err) 2215 return (err); 2216 2217 if (sc->sc_bus.use_polling) 2218 uhci_waitintr(sc, xfer); 2219 return (USBD_IN_PROGRESS); 2220 } 2221 2222 usbd_status 2223 uhci_device_intr_transfer(usbd_xfer_handle xfer) 2224 { 2225 usbd_status err; 2226 2227 /* Insert last in queue. */ 2228 err = usb_insert_transfer(xfer); 2229 if (err) 2230 return (err); 2231 2232 /* 2233 * Pipe isn't running (otherwise err would be USBD_INPROG), 2234 * so start it first. 2235 */ 2236 return (uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2237 } 2238 2239 usbd_status 2240 uhci_device_intr_start(usbd_xfer_handle xfer) 2241 { 2242 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2243 usbd_device_handle dev = upipe->pipe.device; 2244 uhci_softc_t *sc = dev->bus->hci_private; 2245 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2246 uhci_soft_td_t *data, *dataend; 2247 uhci_soft_qh_t *sqh; 2248 usbd_status err; 2249 int isread, endpt; 2250 int i, s; 2251 2252 if (sc->sc_dying) 2253 return (USBD_IOERROR); 2254 2255 DPRINTFN(3,("uhci_device_intr_transfer: xfer=%p len=%d flags=%d\n", 2256 xfer, xfer->length, xfer->flags)); 2257 2258 #ifdef DIAGNOSTIC 2259 if (xfer->rqflags & URQ_REQUEST) 2260 panic("uhci_device_intr_transfer: a request"); 2261 #endif 2262 2263 endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2264 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2265 2266 upipe->u.intr.isread = isread; 2267 2268 err = uhci_alloc_std_chain(upipe, sc, xfer->length, isread, 2269 xfer->flags, &xfer->dmabuf, &data, 2270 &dataend); 2271 if (err) 2272 return (err); 2273 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2274 usb_syncmem(&dataend->dma, 2275 dataend->offs + offsetof(uhci_td_t, td_status), 2276 sizeof(dataend->td.td_status), 2277 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2278 2279 #ifdef UHCI_DEBUG 2280 if (uhcidebug > 10) { 2281 DPRINTF(("uhci_device_intr_transfer: data(1)\n")); 2282 uhci_dump_tds(data); 2283 uhci_dump_qh(upipe->u.intr.qhs[0]); 2284 } 2285 #endif 2286 2287 s = splusb(); 2288 /* Set up interrupt info. */ 2289 ii->xfer = xfer; 2290 ii->stdstart = data; 2291 ii->stdend = dataend; 2292 #ifdef DIAGNOSTIC 2293 if (!ii->isdone) { 2294 printf("uhci_device_intr_transfer: not done, ii=%p\n", ii); 2295 } 2296 ii->isdone = 0; 2297 #endif 2298 2299 DPRINTFN(10,("uhci_device_intr_transfer: qhs[0]=%p\n", 2300 upipe->u.intr.qhs[0])); 2301 for (i = 0; i < upipe->u.intr.npoll; i++) { 2302 sqh = upipe->u.intr.qhs[i]; 2303 sqh->elink = data; 2304 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2305 usb_syncmem(&sqh->dma, 2306 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2307 sizeof(sqh->qh.qh_elink), 2308 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2309 } 2310 uhci_add_intr_info(sc, ii); 2311 xfer->status = USBD_IN_PROGRESS; 2312 splx(s); 2313 2314 #ifdef UHCI_DEBUG 2315 if (uhcidebug > 10) { 2316 DPRINTF(("uhci_device_intr_transfer: data(2)\n")); 2317 uhci_dump_tds(data); 2318 uhci_dump_qh(upipe->u.intr.qhs[0]); 2319 } 2320 #endif 2321 2322 return (USBD_IN_PROGRESS); 2323 } 2324 2325 /* Abort a device control request. */ 2326 void 2327 uhci_device_ctrl_abort(usbd_xfer_handle xfer) 2328 { 2329 DPRINTF(("uhci_device_ctrl_abort:\n")); 2330 uhci_abort_xfer(xfer, USBD_CANCELLED); 2331 } 2332 2333 /* Close a device control pipe. */ 2334 void 2335 uhci_device_ctrl_close(usbd_pipe_handle pipe) 2336 { 2337 } 2338 2339 /* Abort a device interrupt request. */ 2340 void 2341 uhci_device_intr_abort(usbd_xfer_handle xfer) 2342 { 2343 DPRINTFN(1,("uhci_device_intr_abort: xfer=%p\n", xfer)); 2344 if (xfer->pipe->intrxfer == xfer) { 2345 DPRINTFN(1,("uhci_device_intr_abort: remove\n")); 2346 xfer->pipe->intrxfer = NULL; 2347 } 2348 uhci_abort_xfer(xfer, USBD_CANCELLED); 2349 } 2350 2351 /* Close a device interrupt pipe. */ 2352 void 2353 uhci_device_intr_close(usbd_pipe_handle pipe) 2354 { 2355 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2356 uhci_softc_t *sc = pipe->device->bus->hci_private; 2357 int i, npoll; 2358 int s; 2359 2360 /* Unlink descriptors from controller data structures. */ 2361 npoll = upipe->u.intr.npoll; 2362 s = splusb(); 2363 for (i = 0; i < npoll; i++) 2364 uhci_remove_intr(sc, upipe->u.intr.qhs[i]); 2365 splx(s); 2366 2367 /* 2368 * We now have to wait for any activity on the physical 2369 * descriptors to stop. 2370 */ 2371 usb_delay_ms(&sc->sc_bus, 2); 2372 2373 for(i = 0; i < npoll; i++) 2374 uhci_free_sqh(sc, upipe->u.intr.qhs[i]); 2375 free(upipe->u.intr.qhs, M_USBHC); 2376 2377 /* XXX free other resources */ 2378 } 2379 2380 usbd_status 2381 uhci_device_request(usbd_xfer_handle xfer) 2382 { 2383 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2384 usb_device_request_t *req = &xfer->request; 2385 usbd_device_handle dev = upipe->pipe.device; 2386 uhci_softc_t *sc = dev->bus->hci_private; 2387 int addr = dev->address; 2388 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2389 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2390 uhci_soft_td_t *setup, *data, *stat, *next, *dataend; 2391 uhci_soft_qh_t *sqh; 2392 int len; 2393 u_int32_t ls; 2394 usbd_status err; 2395 int isread; 2396 int s; 2397 2398 DPRINTFN(3,("uhci_device_control type=0x%02x, request=0x%02x, " 2399 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 2400 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2401 UGETW(req->wIndex), UGETW(req->wLength), 2402 addr, endpt)); 2403 2404 ls = dev->speed == USB_SPEED_LOW ? UHCI_TD_LS : 0; 2405 isread = req->bmRequestType & UT_READ; 2406 len = UGETW(req->wLength); 2407 2408 setup = upipe->u.ctl.setup; 2409 stat = upipe->u.ctl.stat; 2410 sqh = upipe->u.ctl.sqh; 2411 2412 /* Set up data transaction */ 2413 if (len != 0) { 2414 upipe->nexttoggle = 1; 2415 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->flags, 2416 &xfer->dmabuf, &data, &dataend); 2417 if (err) 2418 return (err); 2419 next = data; 2420 dataend->link.std = stat; 2421 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_VF | UHCI_PTR_TD); 2422 usb_syncmem(&dataend->dma, 2423 dataend->offs + offsetof(uhci_td_t, td_link), 2424 sizeof(dataend->td.td_link), 2425 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2426 } else { 2427 next = stat; 2428 } 2429 upipe->u.ctl.length = len; 2430 2431 memcpy(KERNADDR(&upipe->u.ctl.reqdma, 0), req, sizeof *req); 2432 usb_syncmem(&upipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 2433 2434 setup->link.std = next; 2435 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_VF | UHCI_PTR_TD); 2436 setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2437 UHCI_TD_ACTIVE); 2438 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof *req, endpt, addr)); 2439 setup->td.td_buffer = htole32(DMAADDR(&upipe->u.ctl.reqdma, 0)); 2440 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2441 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2442 2443 stat->link.std = NULL; 2444 stat->td.td_link = htole32(UHCI_PTR_T); 2445 stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2446 UHCI_TD_ACTIVE | UHCI_TD_IOC); 2447 stat->td.td_token = 2448 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2449 UHCI_TD_IN (0, endpt, addr, 1)); 2450 stat->td.td_buffer = htole32(0); 2451 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2452 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2453 2454 #ifdef UHCI_DEBUG 2455 if (uhcidebug > 10) { 2456 DPRINTF(("uhci_device_request: before transfer\n")); 2457 uhci_dump_tds(setup); 2458 } 2459 #endif 2460 2461 /* Set up interrupt info. */ 2462 ii->xfer = xfer; 2463 ii->stdstart = setup; 2464 ii->stdend = stat; 2465 #ifdef DIAGNOSTIC 2466 if (!ii->isdone) { 2467 printf("uhci_device_request: not done, ii=%p\n", ii); 2468 } 2469 ii->isdone = 0; 2470 #endif 2471 2472 sqh->elink = setup; 2473 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2474 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2475 2476 s = splusb(); 2477 if (dev->speed == USB_SPEED_LOW) 2478 uhci_add_ls_ctrl(sc, sqh); 2479 else 2480 uhci_add_hs_ctrl(sc, sqh); 2481 uhci_add_intr_info(sc, ii); 2482 #ifdef UHCI_DEBUG 2483 if (uhcidebug > 12) { 2484 uhci_soft_td_t *std; 2485 uhci_soft_qh_t *xqh; 2486 uhci_soft_qh_t *sxqh; 2487 int maxqh = 0; 2488 uhci_physaddr_t link; 2489 DPRINTF(("uhci_enter_ctl_q: follow from [0]\n")); 2490 for (std = sc->sc_vframes[0].htd, link = 0; 2491 (link & UHCI_PTR_QH) == 0; 2492 std = std->link.std) { 2493 link = le32toh(std->td.td_link); 2494 uhci_dump_td(std); 2495 } 2496 sxqh = (uhci_soft_qh_t *)std; 2497 uhci_dump_qh(sxqh); 2498 for (xqh = sxqh; 2499 xqh != NULL; 2500 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2501 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2502 uhci_dump_qh(xqh); 2503 } 2504 DPRINTF(("Enqueued QH:\n")); 2505 uhci_dump_qh(sqh); 2506 uhci_dump_tds(sqh->elink); 2507 } 2508 #endif 2509 if (xfer->timeout && !sc->sc_bus.use_polling) { 2510 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 2511 uhci_timeout, ii); 2512 } 2513 xfer->status = USBD_IN_PROGRESS; 2514 splx(s); 2515 2516 return (USBD_NORMAL_COMPLETION); 2517 } 2518 2519 usbd_status 2520 uhci_device_isoc_transfer(usbd_xfer_handle xfer) 2521 { 2522 usbd_status err; 2523 2524 DPRINTFN(5,("uhci_device_isoc_transfer: xfer=%p\n", xfer)); 2525 2526 /* Put it on our queue, */ 2527 err = usb_insert_transfer(xfer); 2528 2529 /* bail out on error, */ 2530 if (err && err != USBD_IN_PROGRESS) 2531 return (err); 2532 2533 /* XXX should check inuse here */ 2534 2535 /* insert into schedule, */ 2536 uhci_device_isoc_enter(xfer); 2537 2538 /* and start if the pipe wasn't running */ 2539 if (!err) 2540 uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 2541 2542 return (err); 2543 } 2544 2545 void 2546 uhci_device_isoc_enter(usbd_xfer_handle xfer) 2547 { 2548 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2549 usbd_device_handle dev = upipe->pipe.device; 2550 uhci_softc_t *sc = dev->bus->hci_private; 2551 struct iso *iso = &upipe->u.iso; 2552 uhci_soft_td_t *std; 2553 u_int32_t buf, len, status, offs; 2554 int s, i, next, nframes; 2555 int rd = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2556 2557 DPRINTFN(5,("uhci_device_isoc_enter: used=%d next=%d xfer=%p " 2558 "nframes=%d\n", 2559 iso->inuse, iso->next, xfer, xfer->nframes)); 2560 2561 if (sc->sc_dying) 2562 return; 2563 2564 if (xfer->status == USBD_IN_PROGRESS) { 2565 /* This request has already been entered into the frame list */ 2566 printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer); 2567 /* XXX */ 2568 } 2569 2570 #ifdef DIAGNOSTIC 2571 if (iso->inuse >= UHCI_VFRAMELIST_COUNT) 2572 printf("uhci_device_isoc_enter: overflow!\n"); 2573 #endif 2574 2575 next = iso->next; 2576 if (next == -1) { 2577 /* Not in use yet, schedule it a few frames ahead. */ 2578 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 2579 DPRINTFN(2,("uhci_device_isoc_enter: start next=%d\n", next)); 2580 } 2581 2582 xfer->status = USBD_IN_PROGRESS; 2583 UXFER(xfer)->curframe = next; 2584 2585 buf = DMAADDR(&xfer->dmabuf, 0); 2586 offs = 0; 2587 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 2588 UHCI_TD_ACTIVE | 2589 UHCI_TD_IOS); 2590 nframes = xfer->nframes; 2591 s = splusb(); 2592 for (i = 0; i < nframes; i++) { 2593 std = iso->stds[next]; 2594 if (++next >= UHCI_VFRAMELIST_COUNT) 2595 next = 0; 2596 len = xfer->frlengths[i]; 2597 std->td.td_buffer = htole32(buf); 2598 usb_syncmem(&xfer->dmabuf, offs, len, 2599 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2600 if (i == nframes - 1) 2601 status |= UHCI_TD_IOC; 2602 std->td.td_status = htole32(status); 2603 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2604 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 2605 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2606 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2607 #ifdef UHCI_DEBUG 2608 if (uhcidebug > 5) { 2609 DPRINTFN(5,("uhci_device_isoc_enter: TD %d\n", i)); 2610 uhci_dump_td(std); 2611 } 2612 #endif 2613 buf += len; 2614 offs += len; 2615 } 2616 iso->next = next; 2617 iso->inuse += xfer->nframes; 2618 2619 splx(s); 2620 } 2621 2622 usbd_status 2623 uhci_device_isoc_start(usbd_xfer_handle xfer) 2624 { 2625 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2626 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 2627 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2628 uhci_soft_td_t *end; 2629 int s, i; 2630 2631 DPRINTFN(5,("uhci_device_isoc_start: xfer=%p\n", xfer)); 2632 2633 if (sc->sc_dying) 2634 return (USBD_IOERROR); 2635 2636 #ifdef DIAGNOSTIC 2637 if (xfer->status != USBD_IN_PROGRESS) 2638 printf("uhci_device_isoc_start: not in progress %p\n", xfer); 2639 #endif 2640 2641 /* Find the last TD */ 2642 i = UXFER(xfer)->curframe + xfer->nframes; 2643 if (i >= UHCI_VFRAMELIST_COUNT) 2644 i -= UHCI_VFRAMELIST_COUNT; 2645 end = upipe->u.iso.stds[i]; 2646 2647 #ifdef DIAGNOSTIC 2648 if (end == NULL) { 2649 printf("uhci_device_isoc_start: end == NULL\n"); 2650 return (USBD_INVAL); 2651 } 2652 #endif 2653 2654 s = splusb(); 2655 2656 /* Set up interrupt info. */ 2657 ii->xfer = xfer; 2658 ii->stdstart = end; 2659 ii->stdend = end; 2660 #ifdef DIAGNOSTIC 2661 if (!ii->isdone) 2662 printf("uhci_device_isoc_start: not done, ii=%p\n", ii); 2663 ii->isdone = 0; 2664 #endif 2665 uhci_add_intr_info(sc, ii); 2666 2667 splx(s); 2668 2669 return (USBD_IN_PROGRESS); 2670 } 2671 2672 void 2673 uhci_device_isoc_abort(usbd_xfer_handle xfer) 2674 { 2675 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2676 uhci_soft_td_t **stds = upipe->u.iso.stds; 2677 uhci_soft_td_t *std; 2678 int i, n, s, nframes, maxlen, len; 2679 2680 s = splusb(); 2681 2682 /* Transfer is already done. */ 2683 if (xfer->status != USBD_NOT_STARTED && 2684 xfer->status != USBD_IN_PROGRESS) { 2685 splx(s); 2686 return; 2687 } 2688 2689 /* Give xfer the requested abort code. */ 2690 xfer->status = USBD_CANCELLED; 2691 2692 /* make hardware ignore it, */ 2693 nframes = xfer->nframes; 2694 n = UXFER(xfer)->curframe; 2695 maxlen = 0; 2696 for (i = 0; i < nframes; i++) { 2697 std = stds[n]; 2698 usb_syncmem(&std->dma, 2699 std->offs + offsetof(uhci_td_t, td_status), 2700 sizeof(std->td.td_status), 2701 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2702 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2703 usb_syncmem(&std->dma, 2704 std->offs + offsetof(uhci_td_t, td_status), 2705 sizeof(std->td.td_status), 2706 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2707 usb_syncmem(&std->dma, 2708 std->offs + offsetof(uhci_td_t, td_token), 2709 sizeof(std->td.td_token), 2710 BUS_DMASYNC_POSTWRITE); 2711 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 2712 if (len > maxlen) 2713 maxlen = len; 2714 if (++n >= UHCI_VFRAMELIST_COUNT) 2715 n = 0; 2716 } 2717 2718 /* and wait until we are sure the hardware has finished. */ 2719 delay(maxlen); 2720 2721 #ifdef DIAGNOSTIC 2722 UXFER(xfer)->iinfo.isdone = 1; 2723 #endif 2724 /* Run callback and remove from interrupt list. */ 2725 usb_transfer_complete(xfer); 2726 2727 splx(s); 2728 } 2729 2730 void 2731 uhci_device_isoc_close(usbd_pipe_handle pipe) 2732 { 2733 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2734 usbd_device_handle dev = upipe->pipe.device; 2735 uhci_softc_t *sc = dev->bus->hci_private; 2736 uhci_soft_td_t *std, *vstd; 2737 struct iso *iso; 2738 int i, s; 2739 2740 /* 2741 * Make sure all TDs are marked as inactive. 2742 * Wait for completion. 2743 * Unschedule. 2744 * Deallocate. 2745 */ 2746 iso = &upipe->u.iso; 2747 2748 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2749 std = iso->stds[i]; 2750 usb_syncmem(&std->dma, 2751 std->offs + offsetof(uhci_td_t, td_status), 2752 sizeof(std->td.td_status), 2753 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2754 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 2755 usb_syncmem(&std->dma, 2756 std->offs + offsetof(uhci_td_t, td_status), 2757 sizeof(std->td.td_status), 2758 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2759 } 2760 usb_delay_ms(&sc->sc_bus, 2); /* wait for completion */ 2761 2762 s = splusb(); 2763 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2764 std = iso->stds[i]; 2765 for (vstd = sc->sc_vframes[i].htd; 2766 vstd != NULL && vstd->link.std != std; 2767 vstd = vstd->link.std) 2768 ; 2769 if (vstd == NULL) { 2770 /*panic*/ 2771 printf("uhci_device_isoc_close: %p not found\n", std); 2772 splx(s); 2773 return; 2774 } 2775 vstd->link = std->link; 2776 usb_syncmem(&std->dma, 2777 std->offs + offsetof(uhci_td_t, td_link), 2778 sizeof(std->td.td_link), 2779 BUS_DMASYNC_POSTWRITE); 2780 vstd->td.td_link = std->td.td_link; 2781 usb_syncmem(&vstd->dma, 2782 vstd->offs + offsetof(uhci_td_t, td_link), 2783 sizeof(vstd->td.td_link), 2784 BUS_DMASYNC_PREWRITE); 2785 uhci_free_std(sc, std); 2786 } 2787 splx(s); 2788 2789 free(iso->stds, M_USBHC); 2790 } 2791 2792 usbd_status 2793 uhci_setup_isoc(usbd_pipe_handle pipe) 2794 { 2795 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2796 usbd_device_handle dev = upipe->pipe.device; 2797 uhci_softc_t *sc = dev->bus->hci_private; 2798 int addr = upipe->pipe.device->address; 2799 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2800 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 2801 uhci_soft_td_t *std, *vstd; 2802 u_int32_t token; 2803 struct iso *iso; 2804 int i, s; 2805 2806 iso = &upipe->u.iso; 2807 iso->stds = malloc(UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *), 2808 M_USBHC, M_WAITOK); 2809 2810 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 2811 UHCI_TD_OUT(0, endpt, addr, 0); 2812 2813 /* Allocate the TDs and mark as inactive; */ 2814 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2815 std = uhci_alloc_std(sc); 2816 if (std == 0) 2817 goto bad; 2818 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 2819 std->td.td_token = htole32(token); 2820 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2821 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2822 iso->stds[i] = std; 2823 } 2824 2825 /* Insert TDs into schedule. */ 2826 s = splusb(); 2827 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2828 std = iso->stds[i]; 2829 vstd = sc->sc_vframes[i].htd; 2830 usb_syncmem(&vstd->dma, 2831 vstd->offs + offsetof(uhci_td_t, td_link), 2832 sizeof(vstd->td.td_link), 2833 BUS_DMASYNC_POSTWRITE); 2834 std->link = vstd->link; 2835 std->td.td_link = vstd->td.td_link; 2836 usb_syncmem(&std->dma, 2837 std->offs + offsetof(uhci_td_t, td_link), 2838 sizeof(std->td.td_link), 2839 BUS_DMASYNC_PREWRITE); 2840 vstd->link.std = std; 2841 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 2842 usb_syncmem(&vstd->dma, 2843 vstd->offs + offsetof(uhci_td_t, td_link), 2844 sizeof(vstd->td.td_link), 2845 BUS_DMASYNC_PREWRITE); 2846 } 2847 splx(s); 2848 2849 iso->next = -1; 2850 iso->inuse = 0; 2851 2852 return (USBD_NORMAL_COMPLETION); 2853 2854 bad: 2855 while (--i >= 0) 2856 uhci_free_std(sc, iso->stds[i]); 2857 free(iso->stds, M_USBHC); 2858 return (USBD_NOMEM); 2859 } 2860 2861 void 2862 uhci_device_isoc_done(usbd_xfer_handle xfer) 2863 { 2864 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2865 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2866 int i, offs; 2867 int rd = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2868 2869 2870 DPRINTFN(4, ("uhci_isoc_done: length=%d, busy_free=0x%08x\n", 2871 xfer->actlen, xfer->busy_free)); 2872 2873 if (ii->xfer != xfer) 2874 /* Not on interrupt list, ignore it. */ 2875 return; 2876 2877 if (!uhci_active_intr_info(ii)) 2878 return; 2879 2880 #ifdef DIAGNOSTIC 2881 if (ii->stdend == NULL) { 2882 printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer); 2883 #ifdef UHCI_DEBUG 2884 uhci_dump_ii(ii); 2885 #endif 2886 return; 2887 } 2888 #endif 2889 2890 /* Turn off the interrupt since it is active even if the TD is not. */ 2891 usb_syncmem(&ii->stdend->dma, 2892 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2893 sizeof(ii->stdend->td.td_status), 2894 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2895 ii->stdend->td.td_status &= htole32(~UHCI_TD_IOC); 2896 usb_syncmem(&ii->stdend->dma, 2897 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2898 sizeof(ii->stdend->td.td_status), 2899 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2900 2901 uhci_del_intr_info(ii); /* remove from active list */ 2902 2903 offs = 0; 2904 for (i = 0; i < xfer->nframes; i++) { 2905 usb_syncmem(&xfer->dmabuf, offs, xfer->frlengths[i], 2906 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2907 offs += xfer->frlengths[i]; 2908 } 2909 } 2910 2911 void 2912 uhci_device_intr_done(usbd_xfer_handle xfer) 2913 { 2914 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2915 uhci_softc_t *sc = ii->sc; 2916 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2917 uhci_soft_qh_t *sqh; 2918 int i, npoll, isread; 2919 2920 DPRINTFN(5, ("uhci_device_intr_done: length=%d\n", xfer->actlen)); 2921 2922 npoll = upipe->u.intr.npoll; 2923 for(i = 0; i < npoll; i++) { 2924 sqh = upipe->u.intr.qhs[i]; 2925 sqh->elink = NULL; 2926 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 2927 usb_syncmem(&sqh->dma, 2928 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2929 sizeof(sqh->qh.qh_elink), 2930 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2931 } 2932 uhci_free_std_chain(sc, ii->stdstart, NULL); 2933 2934 isread = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2935 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 2936 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2937 2938 /* XXX Wasteful. */ 2939 if (xfer->pipe->repeat) { 2940 uhci_soft_td_t *data, *dataend; 2941 2942 DPRINTFN(5,("uhci_device_intr_done: requeing\n")); 2943 2944 /* This alloc cannot fail since we freed the chain above. */ 2945 uhci_alloc_std_chain(upipe, sc, xfer->length, 2946 upipe->u.intr.isread, xfer->flags, 2947 &xfer->dmabuf, &data, &dataend); 2948 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2949 usb_syncmem(&dataend->dma, 2950 dataend->offs + offsetof(uhci_td_t, td_status), 2951 sizeof(dataend->td.td_status), 2952 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2953 2954 #ifdef UHCI_DEBUG 2955 if (uhcidebug > 10) { 2956 DPRINTF(("uhci_device_intr_done: data(1)\n")); 2957 uhci_dump_tds(data); 2958 uhci_dump_qh(upipe->u.intr.qhs[0]); 2959 } 2960 #endif 2961 2962 ii->stdstart = data; 2963 ii->stdend = dataend; 2964 #ifdef DIAGNOSTIC 2965 if (!ii->isdone) { 2966 printf("uhci_device_intr_done: not done, ii=%p\n", ii); 2967 } 2968 ii->isdone = 0; 2969 #endif 2970 for (i = 0; i < npoll; i++) { 2971 sqh = upipe->u.intr.qhs[i]; 2972 sqh->elink = data; 2973 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2974 usb_syncmem(&sqh->dma, 2975 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2976 sizeof(sqh->qh.qh_elink), 2977 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2978 } 2979 xfer->status = USBD_IN_PROGRESS; 2980 /* The ii is already on the examined list, just leave it. */ 2981 } else { 2982 DPRINTFN(5,("uhci_device_intr_done: removing\n")); 2983 if (uhci_active_intr_info(ii)) 2984 uhci_del_intr_info(ii); 2985 } 2986 } 2987 2988 /* Deallocate request data structures */ 2989 void 2990 uhci_device_ctrl_done(usbd_xfer_handle xfer) 2991 { 2992 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2993 uhci_softc_t *sc = ii->sc; 2994 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2995 int len = UGETW(xfer->request.wLength); 2996 int isread = (xfer->request.bmRequestType & UT_READ); 2997 2998 #ifdef DIAGNOSTIC 2999 if (!(xfer->rqflags & URQ_REQUEST)) 3000 panic("uhci_device_ctrl_done: not a request"); 3001 #endif 3002 3003 if (!uhci_active_intr_info(ii)) 3004 return; 3005 3006 uhci_del_intr_info(ii); /* remove from active list */ 3007 3008 if (upipe->pipe.device->speed == USB_SPEED_LOW) 3009 uhci_remove_ls_ctrl(sc, upipe->u.ctl.sqh); 3010 else 3011 uhci_remove_hs_ctrl(sc, upipe->u.ctl.sqh); 3012 3013 if (upipe->u.ctl.length != 0) 3014 uhci_free_std_chain(sc, ii->stdstart->link.std, ii->stdend); 3015 3016 if (len) { 3017 usb_syncmem(&xfer->dmabuf, 0, len, 3018 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3019 } 3020 usb_syncmem(&upipe->u.ctl.reqdma, 0, 3021 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3022 3023 DPRINTFN(5, ("uhci_device_ctrl_done: length=%d\n", xfer->actlen)); 3024 } 3025 3026 /* Deallocate request data structures */ 3027 void 3028 uhci_device_bulk_done(usbd_xfer_handle xfer) 3029 { 3030 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3031 uhci_softc_t *sc = ii->sc; 3032 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 3033 3034 DPRINTFN(5,("uhci_device_bulk_done: xfer=%p ii=%p sc=%p upipe=%p\n", 3035 xfer, ii, sc, upipe)); 3036 3037 if (!uhci_active_intr_info(ii)) 3038 return; 3039 3040 uhci_del_intr_info(ii); /* remove from active list */ 3041 3042 uhci_remove_bulk(sc, upipe->u.bulk.sqh); 3043 3044 uhci_free_std_chain(sc, ii->stdstart, NULL); 3045 3046 DPRINTFN(5, ("uhci_device_bulk_done: length=%d\n", xfer->actlen)); 3047 } 3048 3049 /* Add interrupt QH, called with vflock. */ 3050 void 3051 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3052 { 3053 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3054 uhci_soft_qh_t *eqh; 3055 3056 DPRINTFN(4, ("uhci_add_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3057 3058 eqh = vf->eqh; 3059 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3060 sizeof(eqh->qh.qh_hlink), 3061 BUS_DMASYNC_POSTWRITE); 3062 sqh->hlink = eqh->hlink; 3063 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3064 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3065 sizeof(sqh->qh.qh_hlink), 3066 BUS_DMASYNC_PREWRITE); 3067 eqh->hlink = sqh; 3068 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3069 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3070 sizeof(eqh->qh.qh_hlink), 3071 BUS_DMASYNC_PREWRITE); 3072 vf->eqh = sqh; 3073 vf->bandwidth++; 3074 } 3075 3076 /* Remove interrupt QH. */ 3077 void 3078 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3079 { 3080 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3081 uhci_soft_qh_t *pqh; 3082 3083 DPRINTFN(4, ("uhci_remove_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3084 3085 /* See comment in uhci_remove_ctrl() */ 3086 3087 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3088 sizeof(sqh->qh.qh_elink), 3089 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3090 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3091 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3092 usb_syncmem(&sqh->dma, 3093 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3094 sizeof(sqh->qh.qh_elink), 3095 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3096 delay(UHCI_QH_REMOVE_DELAY); 3097 } 3098 3099 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3100 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3101 sizeof(sqh->qh.qh_hlink), 3102 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3103 pqh->hlink = sqh->hlink; 3104 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3105 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3106 sizeof(pqh->qh.qh_hlink), 3107 BUS_DMASYNC_PREWRITE); 3108 delay(UHCI_QH_REMOVE_DELAY); 3109 if (vf->eqh == sqh) 3110 vf->eqh = pqh; 3111 vf->bandwidth--; 3112 } 3113 3114 usbd_status 3115 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3116 { 3117 uhci_soft_qh_t *sqh; 3118 int i, npoll, s; 3119 u_int bestbw, bw, bestoffs, offs; 3120 3121 DPRINTFN(2, ("uhci_device_setintr: pipe=%p\n", upipe)); 3122 if (ival == 0) { 3123 printf("uhci_device_setintr: 0 interval\n"); 3124 return (USBD_INVAL); 3125 } 3126 3127 if (ival > UHCI_VFRAMELIST_COUNT) 3128 ival = UHCI_VFRAMELIST_COUNT; 3129 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3130 DPRINTFN(2, ("uhci_device_setintr: ival=%d npoll=%d\n", ival, npoll)); 3131 3132 upipe->u.intr.npoll = npoll; 3133 upipe->u.intr.qhs = 3134 malloc(npoll * sizeof(uhci_soft_qh_t *), M_USBHC, M_WAITOK); 3135 3136 /* 3137 * Figure out which offset in the schedule that has most 3138 * bandwidth left over. 3139 */ 3140 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3141 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3142 for (bw = i = 0; i < npoll; i++) 3143 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3144 if (bw < bestbw) { 3145 bestbw = bw; 3146 bestoffs = offs; 3147 } 3148 } 3149 DPRINTFN(1, ("uhci_device_setintr: bw=%d offs=%d\n", bestbw, bestoffs)); 3150 3151 for(i = 0; i < npoll; i++) { 3152 upipe->u.intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3153 sqh->elink = NULL; 3154 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3155 usb_syncmem(&sqh->dma, 3156 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3157 sizeof(sqh->qh.qh_elink), 3158 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3159 sqh->pos = MOD(i * ival + bestoffs); 3160 } 3161 #undef MOD 3162 3163 s = splusb(); 3164 /* Enter QHs into the controller data structures. */ 3165 for(i = 0; i < npoll; i++) 3166 uhci_add_intr(sc, upipe->u.intr.qhs[i]); 3167 splx(s); 3168 3169 DPRINTFN(5, ("uhci_device_setintr: returns %p\n", upipe)); 3170 return (USBD_NORMAL_COMPLETION); 3171 } 3172 3173 /* Open a new pipe. */ 3174 usbd_status 3175 uhci_open(usbd_pipe_handle pipe) 3176 { 3177 uhci_softc_t *sc = pipe->device->bus->hci_private; 3178 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 3179 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 3180 usbd_status err; 3181 int ival; 3182 3183 DPRINTFN(1, ("uhci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 3184 pipe, pipe->device->address, 3185 ed->bEndpointAddress, sc->sc_addr)); 3186 3187 upipe->aborting = 0; 3188 upipe->nexttoggle = 0; 3189 3190 if (pipe->device->address == sc->sc_addr) { 3191 switch (ed->bEndpointAddress) { 3192 case USB_CONTROL_ENDPOINT: 3193 pipe->methods = &uhci_root_ctrl_methods; 3194 break; 3195 case UE_DIR_IN | UHCI_INTR_ENDPT: 3196 pipe->methods = &uhci_root_intr_methods; 3197 break; 3198 default: 3199 return (USBD_INVAL); 3200 } 3201 } else { 3202 switch (ed->bmAttributes & UE_XFERTYPE) { 3203 case UE_CONTROL: 3204 pipe->methods = &uhci_device_ctrl_methods; 3205 upipe->u.ctl.sqh = uhci_alloc_sqh(sc); 3206 if (upipe->u.ctl.sqh == NULL) 3207 goto bad; 3208 upipe->u.ctl.setup = uhci_alloc_std(sc); 3209 if (upipe->u.ctl.setup == NULL) { 3210 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3211 goto bad; 3212 } 3213 upipe->u.ctl.stat = uhci_alloc_std(sc); 3214 if (upipe->u.ctl.stat == NULL) { 3215 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3216 uhci_free_std(sc, upipe->u.ctl.setup); 3217 goto bad; 3218 } 3219 err = usb_allocmem(&sc->sc_bus, 3220 sizeof(usb_device_request_t), 3221 0, &upipe->u.ctl.reqdma); 3222 if (err) { 3223 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3224 uhci_free_std(sc, upipe->u.ctl.setup); 3225 uhci_free_std(sc, upipe->u.ctl.stat); 3226 goto bad; 3227 } 3228 break; 3229 case UE_INTERRUPT: 3230 pipe->methods = &uhci_device_intr_methods; 3231 ival = pipe->interval; 3232 if (ival == USBD_DEFAULT_INTERVAL) 3233 ival = ed->bInterval; 3234 return (uhci_device_setintr(sc, upipe, ival)); 3235 case UE_ISOCHRONOUS: 3236 pipe->methods = &uhci_device_isoc_methods; 3237 return (uhci_setup_isoc(pipe)); 3238 case UE_BULK: 3239 pipe->methods = &uhci_device_bulk_methods; 3240 upipe->u.bulk.sqh = uhci_alloc_sqh(sc); 3241 if (upipe->u.bulk.sqh == NULL) 3242 goto bad; 3243 break; 3244 } 3245 } 3246 return (USBD_NORMAL_COMPLETION); 3247 3248 bad: 3249 return (USBD_NOMEM); 3250 } 3251 3252 /* 3253 * Data structures and routines to emulate the root hub. 3254 */ 3255 usb_device_descriptor_t uhci_devd = { 3256 USB_DEVICE_DESCRIPTOR_SIZE, 3257 UDESC_DEVICE, /* type */ 3258 {0x00, 0x01}, /* USB version */ 3259 UDCLASS_HUB, /* class */ 3260 UDSUBCLASS_HUB, /* subclass */ 3261 UDPROTO_FSHUB, /* protocol */ 3262 64, /* max packet */ 3263 {0},{0},{0x00,0x01}, /* device id */ 3264 1,2,0, /* string indicies */ 3265 1 /* # of configurations */ 3266 }; 3267 3268 const usb_config_descriptor_t uhci_confd = { 3269 USB_CONFIG_DESCRIPTOR_SIZE, 3270 UDESC_CONFIG, 3271 {USB_CONFIG_DESCRIPTOR_SIZE + 3272 USB_INTERFACE_DESCRIPTOR_SIZE + 3273 USB_ENDPOINT_DESCRIPTOR_SIZE}, 3274 1, 3275 1, 3276 0, 3277 UC_ATTR_MBO | UC_SELF_POWERED, 3278 0 /* max power */ 3279 }; 3280 3281 const usb_interface_descriptor_t uhci_ifcd = { 3282 USB_INTERFACE_DESCRIPTOR_SIZE, 3283 UDESC_INTERFACE, 3284 0, 3285 0, 3286 1, 3287 UICLASS_HUB, 3288 UISUBCLASS_HUB, 3289 UIPROTO_FSHUB, 3290 0 3291 }; 3292 3293 const usb_endpoint_descriptor_t uhci_endpd = { 3294 USB_ENDPOINT_DESCRIPTOR_SIZE, 3295 UDESC_ENDPOINT, 3296 UE_DIR_IN | UHCI_INTR_ENDPT, 3297 UE_INTERRUPT, 3298 {8}, 3299 255 3300 }; 3301 3302 const usb_hub_descriptor_t uhci_hubd_piix = { 3303 USB_HUB_DESCRIPTOR_SIZE, 3304 UDESC_HUB, 3305 2, 3306 { UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0 }, 3307 50, /* power on to power good */ 3308 0, 3309 { 0x00 }, /* both ports are removable */ 3310 { 0 }, 3311 }; 3312 3313 /* 3314 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3315 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3316 * should not be used by the USB subsystem. As we cannot issue a 3317 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3318 * will be enabled as part of the reset. 3319 * 3320 * On the VT83C572, the port cannot be successfully enabled until the 3321 * outstanding "port enable change" and "connection status change" 3322 * events have been reset. 3323 */ 3324 Static usbd_status 3325 uhci_portreset(uhci_softc_t *sc, int index) 3326 { 3327 int lim, port, x; 3328 3329 if (index == 1) 3330 port = UHCI_PORTSC1; 3331 else if (index == 2) 3332 port = UHCI_PORTSC2; 3333 else 3334 return (USBD_IOERROR); 3335 3336 x = URWMASK(UREAD2(sc, port)); 3337 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3338 3339 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3340 3341 DPRINTFN(3,("uhci port %d reset, status0 = 0x%04x\n", 3342 index, UREAD2(sc, port))); 3343 3344 x = URWMASK(UREAD2(sc, port)); 3345 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3346 3347 delay(100); 3348 3349 DPRINTFN(3,("uhci port %d reset, status1 = 0x%04x\n", 3350 index, UREAD2(sc, port))); 3351 3352 x = URWMASK(UREAD2(sc, port)); 3353 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3354 3355 for (lim = 10; --lim > 0;) { 3356 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3357 3358 x = UREAD2(sc, port); 3359 3360 DPRINTFN(3,("uhci port %d iteration %u, status = 0x%04x\n", 3361 index, lim, x)); 3362 3363 if (!(x & UHCI_PORTSC_CCS)) { 3364 /* 3365 * No device is connected (or was disconnected 3366 * during reset). Consider the port reset. 3367 * The delay must be long enough to ensure on 3368 * the initial iteration that the device 3369 * connection will have been registered. 50ms 3370 * appears to be sufficient, but 20ms is not. 3371 */ 3372 DPRINTFN(3,("uhci port %d loop %u, device detached\n", 3373 index, lim)); 3374 break; 3375 } 3376 3377 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3378 /* 3379 * Port enabled changed and/or connection 3380 * status changed were set. Reset either or 3381 * both raised flags (by writing a 1 to that 3382 * bit), and wait again for state to settle. 3383 */ 3384 UWRITE2(sc, port, URWMASK(x) | 3385 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3386 continue; 3387 } 3388 3389 if (x & UHCI_PORTSC_PE) 3390 /* Port is enabled */ 3391 break; 3392 3393 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3394 } 3395 3396 DPRINTFN(3,("uhci port %d reset, status2 = 0x%04x\n", 3397 index, UREAD2(sc, port))); 3398 3399 if (lim <= 0) { 3400 DPRINTFN(1,("uhci port %d reset timed out\n", index)); 3401 return (USBD_TIMEOUT); 3402 } 3403 3404 sc->sc_isreset = 1; 3405 return (USBD_NORMAL_COMPLETION); 3406 } 3407 3408 /* 3409 * Simulate a hardware hub by handling all the necessary requests. 3410 */ 3411 usbd_status 3412 uhci_root_ctrl_transfer(usbd_xfer_handle xfer) 3413 { 3414 usbd_status err; 3415 3416 /* Insert last in queue. */ 3417 err = usb_insert_transfer(xfer); 3418 if (err) 3419 return (err); 3420 3421 /* 3422 * Pipe isn't running (otherwise err would be USBD_INPROG), 3423 * so start it first. 3424 */ 3425 return (uhci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3426 } 3427 3428 usbd_status 3429 uhci_root_ctrl_start(usbd_xfer_handle xfer) 3430 { 3431 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3432 usb_device_request_t *req; 3433 void *buf = NULL; 3434 int port, x; 3435 int s, len, value, index, status, change, l, totlen = 0; 3436 usb_port_status_t ps; 3437 usbd_status err; 3438 3439 if (sc->sc_dying) 3440 return (USBD_IOERROR); 3441 3442 #ifdef DIAGNOSTIC 3443 if (!(xfer->rqflags & URQ_REQUEST)) 3444 panic("uhci_root_ctrl_transfer: not a request"); 3445 #endif 3446 req = &xfer->request; 3447 3448 DPRINTFN(2,("uhci_root_ctrl_control type=0x%02x request=%02x\n", 3449 req->bmRequestType, req->bRequest)); 3450 3451 len = UGETW(req->wLength); 3452 value = UGETW(req->wValue); 3453 index = UGETW(req->wIndex); 3454 3455 if (len != 0) 3456 buf = KERNADDR(&xfer->dmabuf, 0); 3457 3458 #define C(x,y) ((x) | ((y) << 8)) 3459 switch(C(req->bRequest, req->bmRequestType)) { 3460 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3461 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3462 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3463 /* 3464 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3465 * for the integrated root hub. 3466 */ 3467 break; 3468 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3469 if (len > 0) { 3470 *(u_int8_t *)buf = sc->sc_conf; 3471 totlen = 1; 3472 } 3473 break; 3474 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3475 DPRINTFN(2,("uhci_root_ctrl_control wValue=0x%04x\n", value)); 3476 if (len == 0) 3477 break; 3478 switch(value >> 8) { 3479 case UDESC_DEVICE: 3480 if ((value & 0xff) != 0) { 3481 err = USBD_IOERROR; 3482 goto ret; 3483 } 3484 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 3485 USETW(uhci_devd.idVendor, sc->sc_id_vendor); 3486 memcpy(buf, &uhci_devd, l); 3487 break; 3488 case UDESC_CONFIG: 3489 if ((value & 0xff) != 0) { 3490 err = USBD_IOERROR; 3491 goto ret; 3492 } 3493 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 3494 memcpy(buf, &uhci_confd, l); 3495 buf = (char *)buf + l; 3496 len -= l; 3497 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 3498 totlen += l; 3499 memcpy(buf, &uhci_ifcd, l); 3500 buf = (char *)buf + l; 3501 len -= l; 3502 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 3503 totlen += l; 3504 memcpy(buf, &uhci_endpd, l); 3505 break; 3506 case UDESC_STRING: 3507 #define sd ((usb_string_descriptor_t *)buf) 3508 switch (value & 0xff) { 3509 case 0: /* Language table */ 3510 totlen = usb_makelangtbl(sd, len); 3511 break; 3512 case 1: /* Vendor */ 3513 totlen = usb_makestrdesc(sd, len, 3514 sc->sc_vendor); 3515 break; 3516 case 2: /* Product */ 3517 totlen = usb_makestrdesc(sd, len, 3518 "UHCI root hub"); 3519 break; 3520 } 3521 #undef sd 3522 break; 3523 default: 3524 err = USBD_IOERROR; 3525 goto ret; 3526 } 3527 break; 3528 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3529 if (len > 0) { 3530 *(u_int8_t *)buf = 0; 3531 totlen = 1; 3532 } 3533 break; 3534 case C(UR_GET_STATUS, UT_READ_DEVICE): 3535 if (len > 1) { 3536 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 3537 totlen = 2; 3538 } 3539 break; 3540 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3541 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3542 if (len > 1) { 3543 USETW(((usb_status_t *)buf)->wStatus, 0); 3544 totlen = 2; 3545 } 3546 break; 3547 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3548 if (value >= USB_MAX_DEVICES) { 3549 err = USBD_IOERROR; 3550 goto ret; 3551 } 3552 sc->sc_addr = value; 3553 break; 3554 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3555 if (value != 0 && value != 1) { 3556 err = USBD_IOERROR; 3557 goto ret; 3558 } 3559 sc->sc_conf = value; 3560 break; 3561 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3562 break; 3563 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3564 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3565 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3566 err = USBD_IOERROR; 3567 goto ret; 3568 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3569 break; 3570 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3571 break; 3572 /* Hub requests */ 3573 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3574 break; 3575 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3576 DPRINTFN(3, ("uhci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 3577 "port=%d feature=%d\n", 3578 index, value)); 3579 if (index == 1) 3580 port = UHCI_PORTSC1; 3581 else if (index == 2) 3582 port = UHCI_PORTSC2; 3583 else { 3584 err = USBD_IOERROR; 3585 goto ret; 3586 } 3587 switch(value) { 3588 case UHF_PORT_ENABLE: 3589 x = URWMASK(UREAD2(sc, port)); 3590 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3591 break; 3592 case UHF_PORT_SUSPEND: 3593 x = URWMASK(UREAD2(sc, port)); 3594 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3595 break; 3596 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3597 /* see USB2 spec ch. 7.1.7.7 */ 3598 usb_delay_ms(&sc->sc_bus, 20); 3599 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3600 /* 10ms resume delay must be provided by caller */ 3601 break; 3602 case UHF_PORT_RESET: 3603 x = URWMASK(UREAD2(sc, port)); 3604 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3605 break; 3606 case UHF_C_PORT_CONNECTION: 3607 x = URWMASK(UREAD2(sc, port)); 3608 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3609 break; 3610 case UHF_C_PORT_ENABLE: 3611 x = URWMASK(UREAD2(sc, port)); 3612 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3613 break; 3614 case UHF_C_PORT_OVER_CURRENT: 3615 x = URWMASK(UREAD2(sc, port)); 3616 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3617 break; 3618 case UHF_C_PORT_RESET: 3619 sc->sc_isreset = 0; 3620 err = USBD_NORMAL_COMPLETION; 3621 goto ret; 3622 case UHF_PORT_CONNECTION: 3623 case UHF_PORT_OVER_CURRENT: 3624 case UHF_PORT_POWER: 3625 case UHF_PORT_LOW_SPEED: 3626 case UHF_C_PORT_SUSPEND: 3627 default: 3628 err = USBD_IOERROR; 3629 goto ret; 3630 } 3631 break; 3632 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3633 if (index == 1) 3634 port = UHCI_PORTSC1; 3635 else if (index == 2) 3636 port = UHCI_PORTSC2; 3637 else { 3638 err = USBD_IOERROR; 3639 goto ret; 3640 } 3641 if (len > 0) { 3642 *(u_int8_t *)buf = 3643 (UREAD2(sc, port) & UHCI_PORTSC_LS) >> 3644 UHCI_PORTSC_LS_SHIFT; 3645 totlen = 1; 3646 } 3647 break; 3648 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3649 if (len == 0) 3650 break; 3651 if ((value & 0xff) != 0) { 3652 err = USBD_IOERROR; 3653 goto ret; 3654 } 3655 l = min(len, USB_HUB_DESCRIPTOR_SIZE); 3656 totlen = l; 3657 memcpy(buf, &uhci_hubd_piix, l); 3658 break; 3659 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3660 if (len != 4) { 3661 err = USBD_IOERROR; 3662 goto ret; 3663 } 3664 memset(buf, 0, len); 3665 totlen = len; 3666 break; 3667 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3668 if (index == 1) 3669 port = UHCI_PORTSC1; 3670 else if (index == 2) 3671 port = UHCI_PORTSC2; 3672 else { 3673 err = USBD_IOERROR; 3674 goto ret; 3675 } 3676 if (len != 4) { 3677 err = USBD_IOERROR; 3678 goto ret; 3679 } 3680 x = UREAD2(sc, port); 3681 status = change = 0; 3682 if (x & UHCI_PORTSC_CCS) 3683 status |= UPS_CURRENT_CONNECT_STATUS; 3684 if (x & UHCI_PORTSC_CSC) 3685 change |= UPS_C_CONNECT_STATUS; 3686 if (x & UHCI_PORTSC_PE) 3687 status |= UPS_PORT_ENABLED; 3688 if (x & UHCI_PORTSC_POEDC) 3689 change |= UPS_C_PORT_ENABLED; 3690 if (x & UHCI_PORTSC_OCI) 3691 status |= UPS_OVERCURRENT_INDICATOR; 3692 if (x & UHCI_PORTSC_OCIC) 3693 change |= UPS_C_OVERCURRENT_INDICATOR; 3694 if (x & UHCI_PORTSC_SUSP) 3695 status |= UPS_SUSPEND; 3696 if (x & UHCI_PORTSC_LSDA) 3697 status |= UPS_LOW_SPEED; 3698 status |= UPS_PORT_POWER; 3699 if (sc->sc_isreset) 3700 change |= UPS_C_PORT_RESET; 3701 USETW(ps.wPortStatus, status); 3702 USETW(ps.wPortChange, change); 3703 l = min(len, sizeof ps); 3704 memcpy(buf, &ps, l); 3705 totlen = l; 3706 break; 3707 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3708 err = USBD_IOERROR; 3709 goto ret; 3710 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3711 break; 3712 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3713 if (index == 1) 3714 port = UHCI_PORTSC1; 3715 else if (index == 2) 3716 port = UHCI_PORTSC2; 3717 else { 3718 err = USBD_IOERROR; 3719 goto ret; 3720 } 3721 switch(value) { 3722 case UHF_PORT_ENABLE: 3723 x = URWMASK(UREAD2(sc, port)); 3724 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3725 break; 3726 case UHF_PORT_SUSPEND: 3727 x = URWMASK(UREAD2(sc, port)); 3728 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 3729 break; 3730 case UHF_PORT_RESET: 3731 err = uhci_portreset(sc, index); 3732 goto ret; 3733 case UHF_PORT_POWER: 3734 /* Pretend we turned on power */ 3735 err = USBD_NORMAL_COMPLETION; 3736 goto ret; 3737 case UHF_C_PORT_CONNECTION: 3738 case UHF_C_PORT_ENABLE: 3739 case UHF_C_PORT_OVER_CURRENT: 3740 case UHF_PORT_CONNECTION: 3741 case UHF_PORT_OVER_CURRENT: 3742 case UHF_PORT_LOW_SPEED: 3743 case UHF_C_PORT_SUSPEND: 3744 case UHF_C_PORT_RESET: 3745 default: 3746 err = USBD_IOERROR; 3747 goto ret; 3748 } 3749 break; 3750 default: 3751 err = USBD_IOERROR; 3752 goto ret; 3753 } 3754 xfer->actlen = totlen; 3755 err = USBD_NORMAL_COMPLETION; 3756 ret: 3757 xfer->status = err; 3758 s = splusb(); 3759 usb_transfer_complete(xfer); 3760 splx(s); 3761 return (USBD_IN_PROGRESS); 3762 } 3763 3764 /* Abort a root control request. */ 3765 void 3766 uhci_root_ctrl_abort(usbd_xfer_handle xfer) 3767 { 3768 /* Nothing to do, all transfers are synchronous. */ 3769 } 3770 3771 /* Close the root pipe. */ 3772 void 3773 uhci_root_ctrl_close(usbd_pipe_handle pipe) 3774 { 3775 DPRINTF(("uhci_root_ctrl_close\n")); 3776 } 3777 3778 /* Abort a root interrupt request. */ 3779 void 3780 uhci_root_intr_abort(usbd_xfer_handle xfer) 3781 { 3782 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3783 3784 usb_uncallout(sc->sc_poll_handle, uhci_poll_hub, xfer); 3785 sc->sc_intr_xfer = NULL; 3786 3787 if (xfer->pipe->intrxfer == xfer) { 3788 DPRINTF(("uhci_root_intr_abort: remove\n")); 3789 xfer->pipe->intrxfer = 0; 3790 } 3791 xfer->status = USBD_CANCELLED; 3792 #ifdef DIAGNOSTIC 3793 UXFER(xfer)->iinfo.isdone = 1; 3794 #endif 3795 usb_transfer_complete(xfer); 3796 } 3797 3798 usbd_status 3799 uhci_root_intr_transfer(usbd_xfer_handle xfer) 3800 { 3801 usbd_status err; 3802 3803 /* Insert last in queue. */ 3804 err = usb_insert_transfer(xfer); 3805 if (err) 3806 return (err); 3807 3808 /* 3809 * Pipe isn't running (otherwise err would be USBD_INPROG), 3810 * start first 3811 */ 3812 return (uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3813 } 3814 3815 /* Start a transfer on the root interrupt pipe */ 3816 usbd_status 3817 uhci_root_intr_start(usbd_xfer_handle xfer) 3818 { 3819 usbd_pipe_handle pipe = xfer->pipe; 3820 uhci_softc_t *sc = pipe->device->bus->hci_private; 3821 unsigned int ival; 3822 3823 DPRINTFN(3, ("uhci_root_intr_start: xfer=%p len=%d flags=%d\n", 3824 xfer, xfer->length, xfer->flags)); 3825 3826 if (sc->sc_dying) 3827 return (USBD_IOERROR); 3828 3829 /* XXX temporary variable needed to avoid gcc3 warning */ 3830 ival = xfer->pipe->endpoint->edesc->bInterval; 3831 sc->sc_ival = mstohz(ival); 3832 usb_callout(sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 3833 sc->sc_intr_xfer = xfer; 3834 return (USBD_IN_PROGRESS); 3835 } 3836 3837 /* Close the root interrupt pipe. */ 3838 void 3839 uhci_root_intr_close(usbd_pipe_handle pipe) 3840 { 3841 uhci_softc_t *sc = pipe->device->bus->hci_private; 3842 3843 usb_uncallout(sc->sc_poll_handle, uhci_poll_hub, sc->sc_intr_xfer); 3844 sc->sc_intr_xfer = NULL; 3845 DPRINTF(("uhci_root_intr_close\n")); 3846 } 3847
Indexes created Tue Sep 30 20:09:53 GMT 2025