uhci.c revision 1.232.2.3
1 /* $NetBSD: uhci.c,v 1.232.2.3 2011/05/31 03:04:56 rmind Exp $ */ 2 /* $FreeBSD: src/sys/dev/usb/uhci.c,v 1.33 1999/11/17 22:33:41 n_hibma Exp $ */ 3 4 /* 5 * Copyright (c) 1998, 2004 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Lennart Augustsson (lennart (at) augustsson.net) at 10 * Carlstedt Research & Technology. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Universal Host Controller driver. 36 * Handles e.g. PIIX3 and PIIX4. 37 * 38 * UHCI spec: http://www.intel.com/technology/usb/spec.htm 39 * USB spec: http://www.usb.org/developers/docs/ 40 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 41 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.232.2.3 2011/05/31 03:04:56 rmind Exp $"); 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/malloc.h> 51 #include <sys/device.h> 52 #include <sys/select.h> 53 #include <sys/extent.h> 54 #include <sys/proc.h> 55 #include <sys/queue.h> 56 #include <sys/bus.h> 57 58 #include <machine/endian.h> 59 60 #include <dev/usb/usb.h> 61 #include <dev/usb/usbdi.h> 62 #include <dev/usb/usbdivar.h> 63 #include <dev/usb/usb_mem.h> 64 #include <dev/usb/usb_quirks.h> 65 66 #include <dev/usb/uhcireg.h> 67 #include <dev/usb/uhcivar.h> 68 #include <dev/usb/usbroothub_subr.h> 69 70 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 71 /*#define UHCI_CTL_LOOP */ 72 73 74 75 #ifdef UHCI_DEBUG 76 uhci_softc_t *thesc; 77 #define DPRINTF(x) if (uhcidebug) printf x 78 #define DPRINTFN(n,x) if (uhcidebug>(n)) printf x 79 int uhcidebug = 0; 80 int uhcinoloop = 0; 81 #else 82 #define DPRINTF(x) 83 #define DPRINTFN(n,x) 84 #endif 85 86 /* 87 * The UHCI controller is little endian, so on big endian machines 88 * the data stored in memory needs to be swapped. 89 */ 90 91 struct uhci_pipe { 92 struct usbd_pipe pipe; 93 int nexttoggle; 94 95 u_char aborting; 96 usbd_xfer_handle abortstart, abortend; 97 98 /* Info needed for different pipe kinds. */ 99 union { 100 /* Control pipe */ 101 struct { 102 uhci_soft_qh_t *sqh; 103 usb_dma_t reqdma; 104 uhci_soft_td_t *setup, *stat; 105 u_int length; 106 } ctl; 107 /* Interrupt pipe */ 108 struct { 109 int npoll; 110 int isread; 111 uhci_soft_qh_t **qhs; 112 } intr; 113 /* Bulk pipe */ 114 struct { 115 uhci_soft_qh_t *sqh; 116 u_int length; 117 int isread; 118 } bulk; 119 /* Iso pipe */ 120 struct iso { 121 uhci_soft_td_t **stds; 122 int next, inuse; 123 } iso; 124 } u; 125 }; 126 127 Static void uhci_globalreset(uhci_softc_t *); 128 Static usbd_status uhci_portreset(uhci_softc_t*, int); 129 Static void uhci_reset(uhci_softc_t *); 130 Static usbd_status uhci_run(uhci_softc_t *, int run); 131 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 132 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 133 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 134 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 135 #if 0 136 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 137 uhci_intr_info_t *); 138 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 139 #endif 140 141 Static void uhci_free_std_chain(uhci_softc_t *, 142 uhci_soft_td_t *, uhci_soft_td_t *); 143 Static usbd_status uhci_alloc_std_chain(struct uhci_pipe *, 144 uhci_softc_t *, int, int, u_int16_t, usb_dma_t *, 145 uhci_soft_td_t **, uhci_soft_td_t **); 146 Static void uhci_poll_hub(void *); 147 Static void uhci_waitintr(uhci_softc_t *, usbd_xfer_handle); 148 Static void uhci_check_intr(uhci_softc_t *, uhci_intr_info_t *); 149 Static void uhci_idone(uhci_intr_info_t *); 150 151 Static void uhci_abort_xfer(usbd_xfer_handle, usbd_status status); 152 153 Static void uhci_timeout(void *); 154 Static void uhci_timeout_task(void *); 155 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 156 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 157 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 158 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 159 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 160 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 161 Static void uhci_add_loop(uhci_softc_t *sc); 162 Static void uhci_rem_loop(uhci_softc_t *sc); 163 164 Static usbd_status uhci_setup_isoc(usbd_pipe_handle pipe); 165 Static void uhci_device_isoc_enter(usbd_xfer_handle); 166 167 Static usbd_status uhci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 168 Static void uhci_freem(struct usbd_bus *, usb_dma_t *); 169 170 Static usbd_xfer_handle uhci_allocx(struct usbd_bus *); 171 Static void uhci_freex(struct usbd_bus *, usbd_xfer_handle); 172 173 Static usbd_status uhci_device_ctrl_transfer(usbd_xfer_handle); 174 Static usbd_status uhci_device_ctrl_start(usbd_xfer_handle); 175 Static void uhci_device_ctrl_abort(usbd_xfer_handle); 176 Static void uhci_device_ctrl_close(usbd_pipe_handle); 177 Static void uhci_device_ctrl_done(usbd_xfer_handle); 178 179 Static usbd_status uhci_device_intr_transfer(usbd_xfer_handle); 180 Static usbd_status uhci_device_intr_start(usbd_xfer_handle); 181 Static void uhci_device_intr_abort(usbd_xfer_handle); 182 Static void uhci_device_intr_close(usbd_pipe_handle); 183 Static void uhci_device_intr_done(usbd_xfer_handle); 184 185 Static usbd_status uhci_device_bulk_transfer(usbd_xfer_handle); 186 Static usbd_status uhci_device_bulk_start(usbd_xfer_handle); 187 Static void uhci_device_bulk_abort(usbd_xfer_handle); 188 Static void uhci_device_bulk_close(usbd_pipe_handle); 189 Static void uhci_device_bulk_done(usbd_xfer_handle); 190 191 Static usbd_status uhci_device_isoc_transfer(usbd_xfer_handle); 192 Static usbd_status uhci_device_isoc_start(usbd_xfer_handle); 193 Static void uhci_device_isoc_abort(usbd_xfer_handle); 194 Static void uhci_device_isoc_close(usbd_pipe_handle); 195 Static void uhci_device_isoc_done(usbd_xfer_handle); 196 197 Static usbd_status uhci_root_ctrl_transfer(usbd_xfer_handle); 198 Static usbd_status uhci_root_ctrl_start(usbd_xfer_handle); 199 Static void uhci_root_ctrl_abort(usbd_xfer_handle); 200 Static void uhci_root_ctrl_close(usbd_pipe_handle); 201 Static void uhci_root_ctrl_done(usbd_xfer_handle); 202 203 Static usbd_status uhci_root_intr_transfer(usbd_xfer_handle); 204 Static usbd_status uhci_root_intr_start(usbd_xfer_handle); 205 Static void uhci_root_intr_abort(usbd_xfer_handle); 206 Static void uhci_root_intr_close(usbd_pipe_handle); 207 Static void uhci_root_intr_done(usbd_xfer_handle); 208 209 Static usbd_status uhci_open(usbd_pipe_handle); 210 Static void uhci_poll(struct usbd_bus *); 211 Static void uhci_softintr(void *); 212 213 Static usbd_status uhci_device_request(usbd_xfer_handle xfer); 214 215 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 216 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 217 Static usbd_status uhci_device_setintr(uhci_softc_t *sc, 218 struct uhci_pipe *pipe, int ival); 219 220 Static void uhci_device_clear_toggle(usbd_pipe_handle pipe); 221 Static void uhci_noop(usbd_pipe_handle pipe); 222 223 Static inline uhci_soft_qh_t *uhci_find_prev_qh(uhci_soft_qh_t *, 224 uhci_soft_qh_t *); 225 226 #ifdef UHCI_DEBUG 227 Static void uhci_dump_all(uhci_softc_t *); 228 Static void uhci_dumpregs(uhci_softc_t *); 229 Static void uhci_dump_qhs(uhci_soft_qh_t *); 230 Static void uhci_dump_qh(uhci_soft_qh_t *); 231 Static void uhci_dump_tds(uhci_soft_td_t *); 232 Static void uhci_dump_td(uhci_soft_td_t *); 233 Static void uhci_dump_ii(uhci_intr_info_t *ii); 234 void uhci_dump(void); 235 #endif 236 237 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 238 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 239 #define UWRITE1(sc, r, x) \ 240 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 241 } while (/*CONSTCOND*/0) 242 #define UWRITE2(sc, r, x) \ 243 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 244 } while (/*CONSTCOND*/0) 245 #define UWRITE4(sc, r, x) \ 246 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 247 } while (/*CONSTCOND*/0) 248 static __inline uint8_t 249 UREAD1(uhci_softc_t *sc, bus_size_t r) 250 { 251 252 UBARR(sc); 253 return bus_space_read_1(sc->iot, sc->ioh, r); 254 } 255 256 static __inline uint16_t 257 UREAD2(uhci_softc_t *sc, bus_size_t r) 258 { 259 260 UBARR(sc); 261 return bus_space_read_2(sc->iot, sc->ioh, r); 262 } 263 264 static __inline uint32_t 265 UREAD4(uhci_softc_t *sc, bus_size_t r) 266 { 267 268 UBARR(sc); 269 return bus_space_read_4(sc->iot, sc->ioh, r); 270 } 271 272 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 273 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 274 275 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 276 277 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 278 279 #define UHCI_INTR_ENDPT 1 280 281 const struct usbd_bus_methods uhci_bus_methods = { 282 uhci_open, 283 uhci_softintr, 284 uhci_poll, 285 uhci_allocm, 286 uhci_freem, 287 uhci_allocx, 288 uhci_freex, 289 }; 290 291 const struct usbd_pipe_methods uhci_root_ctrl_methods = { 292 uhci_root_ctrl_transfer, 293 uhci_root_ctrl_start, 294 uhci_root_ctrl_abort, 295 uhci_root_ctrl_close, 296 uhci_noop, 297 uhci_root_ctrl_done, 298 }; 299 300 const struct usbd_pipe_methods uhci_root_intr_methods = { 301 uhci_root_intr_transfer, 302 uhci_root_intr_start, 303 uhci_root_intr_abort, 304 uhci_root_intr_close, 305 uhci_noop, 306 uhci_root_intr_done, 307 }; 308 309 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 310 uhci_device_ctrl_transfer, 311 uhci_device_ctrl_start, 312 uhci_device_ctrl_abort, 313 uhci_device_ctrl_close, 314 uhci_noop, 315 uhci_device_ctrl_done, 316 }; 317 318 const struct usbd_pipe_methods uhci_device_intr_methods = { 319 uhci_device_intr_transfer, 320 uhci_device_intr_start, 321 uhci_device_intr_abort, 322 uhci_device_intr_close, 323 uhci_device_clear_toggle, 324 uhci_device_intr_done, 325 }; 326 327 const struct usbd_pipe_methods uhci_device_bulk_methods = { 328 uhci_device_bulk_transfer, 329 uhci_device_bulk_start, 330 uhci_device_bulk_abort, 331 uhci_device_bulk_close, 332 uhci_device_clear_toggle, 333 uhci_device_bulk_done, 334 }; 335 336 const struct usbd_pipe_methods uhci_device_isoc_methods = { 337 uhci_device_isoc_transfer, 338 uhci_device_isoc_start, 339 uhci_device_isoc_abort, 340 uhci_device_isoc_close, 341 uhci_noop, 342 uhci_device_isoc_done, 343 }; 344 345 #define uhci_add_intr_info(sc, ii) \ 346 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ii), list) 347 #define uhci_del_intr_info(ii) \ 348 do { \ 349 LIST_REMOVE((ii), list); \ 350 (ii)->list.le_prev = NULL; \ 351 } while (0) 352 #define uhci_active_intr_info(ii) ((ii)->list.le_prev != NULL) 353 354 Static inline uhci_soft_qh_t * 355 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 356 { 357 DPRINTFN(15,("uhci_find_prev_qh: pqh=%p sqh=%p\n", pqh, sqh)); 358 359 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 360 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 361 usb_syncmem(&pqh->dma, 362 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 363 sizeof(pqh->qh.qh_hlink), 364 BUS_DMASYNC_POSTWRITE); 365 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 366 printf("uhci_find_prev_qh: QH not found\n"); 367 return (NULL); 368 } 369 #endif 370 } 371 return (pqh); 372 } 373 374 void 375 uhci_globalreset(uhci_softc_t *sc) 376 { 377 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 378 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 379 UHCICMD(sc, 0); /* do nothing */ 380 } 381 382 usbd_status 383 uhci_init(uhci_softc_t *sc) 384 { 385 usbd_status err; 386 int i, j; 387 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 388 uhci_soft_td_t *std; 389 390 DPRINTFN(1,("uhci_init: start\n")); 391 392 #ifdef UHCI_DEBUG 393 thesc = sc; 394 395 if (uhcidebug > 2) 396 uhci_dumpregs(sc); 397 #endif 398 399 sc->sc_suspend = PWR_RESUME; 400 401 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 402 uhci_globalreset(sc); /* reset the controller */ 403 uhci_reset(sc); 404 405 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 406 USB_MEM_RESERVE); 407 408 /* Allocate and initialize real frame array. */ 409 err = usb_allocmem(&sc->sc_bus, 410 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 411 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 412 if (err) 413 return (err); 414 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 415 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 416 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 417 418 /* 419 * Allocate a TD, inactive, that hangs from the last QH. 420 * This is to avoid a bug in the PIIX that makes it run berserk 421 * otherwise. 422 */ 423 std = uhci_alloc_std(sc); 424 if (std == NULL) 425 return (USBD_NOMEM); 426 std->link.std = NULL; 427 std->td.td_link = htole32(UHCI_PTR_T); 428 std->td.td_status = htole32(0); /* inactive */ 429 std->td.td_token = htole32(0); 430 std->td.td_buffer = htole32(0); 431 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 432 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 433 434 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 435 lsqh = uhci_alloc_sqh(sc); 436 if (lsqh == NULL) 437 return (USBD_NOMEM); 438 lsqh->hlink = NULL; 439 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 440 lsqh->elink = std; 441 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 442 sc->sc_last_qh = lsqh; 443 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 444 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 445 446 /* Allocate the dummy QH where bulk traffic will be queued. */ 447 bsqh = uhci_alloc_sqh(sc); 448 if (bsqh == NULL) 449 return (USBD_NOMEM); 450 bsqh->hlink = lsqh; 451 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 452 bsqh->elink = NULL; 453 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 454 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 455 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 456 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 457 458 /* Allocate dummy QH where high speed control traffic will be queued. */ 459 chsqh = uhci_alloc_sqh(sc); 460 if (chsqh == NULL) 461 return (USBD_NOMEM); 462 chsqh->hlink = bsqh; 463 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 464 chsqh->elink = NULL; 465 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 466 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 467 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 468 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 469 470 /* Allocate dummy QH where control traffic will be queued. */ 471 clsqh = uhci_alloc_sqh(sc); 472 if (clsqh == NULL) 473 return (USBD_NOMEM); 474 clsqh->hlink = chsqh; 475 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 476 clsqh->elink = NULL; 477 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 478 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 479 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 480 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 481 482 /* 483 * Make all (virtual) frame list pointers point to the interrupt 484 * queue heads and the interrupt queue heads at the control 485 * queue head and point the physical frame list to the virtual. 486 */ 487 for(i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 488 std = uhci_alloc_std(sc); 489 sqh = uhci_alloc_sqh(sc); 490 if (std == NULL || sqh == NULL) 491 return (USBD_NOMEM); 492 std->link.sqh = sqh; 493 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 494 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 495 std->td.td_token = htole32(0); 496 std->td.td_buffer = htole32(0); 497 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 498 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 499 sqh->hlink = clsqh; 500 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 501 sqh->elink = NULL; 502 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 503 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 504 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 505 sc->sc_vframes[i].htd = std; 506 sc->sc_vframes[i].etd = std; 507 sc->sc_vframes[i].hqh = sqh; 508 sc->sc_vframes[i].eqh = sqh; 509 for (j = i; 510 j < UHCI_FRAMELIST_COUNT; 511 j += UHCI_VFRAMELIST_COUNT) 512 sc->sc_pframes[j] = htole32(std->physaddr); 513 } 514 usb_syncmem(&sc->sc_dma, 0, 515 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 516 BUS_DMASYNC_PREWRITE); 517 518 519 LIST_INIT(&sc->sc_intrhead); 520 521 SIMPLEQ_INIT(&sc->sc_free_xfers); 522 523 callout_init(&sc->sc_poll_handle, 0); 524 525 /* Set up the bus struct. */ 526 sc->sc_bus.methods = &uhci_bus_methods; 527 sc->sc_bus.pipe_size = sizeof(struct uhci_pipe); 528 529 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 530 531 DPRINTFN(1,("uhci_init: enabling\n")); 532 533 err = uhci_run(sc, 1); /* and here we go... */ 534 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 535 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 536 return err; 537 } 538 539 int 540 uhci_activate(device_t self, enum devact act) 541 { 542 struct uhci_softc *sc = device_private(self); 543 544 switch (act) { 545 case DVACT_DEACTIVATE: 546 sc->sc_dying = 1; 547 return 0; 548 default: 549 return EOPNOTSUPP; 550 } 551 } 552 553 void 554 uhci_childdet(device_t self, device_t child) 555 { 556 struct uhci_softc *sc = device_private(self); 557 558 KASSERT(sc->sc_child == child); 559 sc->sc_child = NULL; 560 } 561 562 int 563 uhci_detach(struct uhci_softc *sc, int flags) 564 { 565 usbd_xfer_handle xfer; 566 int rv = 0; 567 568 if (sc->sc_child != NULL) 569 rv = config_detach(sc->sc_child, flags); 570 571 if (rv != 0) 572 return (rv); 573 574 /* Free all xfers associated with this HC. */ 575 for (;;) { 576 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 577 if (xfer == NULL) 578 break; 579 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 580 free(xfer, M_USB); 581 } 582 583 callout_halt(&sc->sc_poll_handle, NULL); 584 callout_destroy(&sc->sc_poll_handle); 585 586 /* XXX free other data structures XXX */ 587 588 return (rv); 589 } 590 591 usbd_status 592 uhci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 593 { 594 struct uhci_softc *sc = bus->hci_private; 595 usbd_status status; 596 u_int32_t n; 597 598 /* 599 * XXX 600 * Since we are allocating a buffer we can assume that we will 601 * need TDs for it. Since we don't want to allocate those from 602 * an interrupt context, we allocate them here and free them again. 603 * This is no guarantee that we'll get the TDs next time... 604 */ 605 n = size / 8; 606 if (n > 16) { 607 u_int32_t i; 608 uhci_soft_td_t **stds; 609 DPRINTF(("uhci_allocm: get %d TDs\n", n)); 610 stds = malloc(sizeof(uhci_soft_td_t *) * n, M_TEMP, 611 M_WAITOK|M_ZERO); 612 for(i=0; i < n; i++) 613 stds[i] = uhci_alloc_std(sc); 614 for(i=0; i < n; i++) 615 if (stds[i] != NULL) 616 uhci_free_std(sc, stds[i]); 617 free(stds, M_TEMP); 618 } 619 620 621 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 622 if (status == USBD_NOMEM) 623 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 624 return status; 625 } 626 627 void 628 uhci_freem(struct usbd_bus *bus, usb_dma_t *dma) 629 { 630 if (dma->block->flags & USB_DMA_RESERVE) { 631 usb_reserve_freem(&((struct uhci_softc *)bus)->sc_dma_reserve, 632 dma); 633 return; 634 } 635 usb_freemem(&((struct uhci_softc *)bus)->sc_bus, dma); 636 } 637 638 usbd_xfer_handle 639 uhci_allocx(struct usbd_bus *bus) 640 { 641 struct uhci_softc *sc = bus->hci_private; 642 usbd_xfer_handle xfer; 643 644 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 645 if (xfer != NULL) { 646 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 647 #ifdef DIAGNOSTIC 648 if (xfer->busy_free != XFER_FREE) { 649 printf("uhci_allocx: xfer=%p not free, 0x%08x\n", xfer, 650 xfer->busy_free); 651 } 652 #endif 653 } else { 654 xfer = malloc(sizeof(struct uhci_xfer), M_USB, M_NOWAIT); 655 } 656 if (xfer != NULL) { 657 memset(xfer, 0, sizeof (struct uhci_xfer)); 658 UXFER(xfer)->iinfo.sc = sc; 659 #ifdef DIAGNOSTIC 660 UXFER(xfer)->iinfo.isdone = 1; 661 xfer->busy_free = XFER_BUSY; 662 #endif 663 } 664 return (xfer); 665 } 666 667 void 668 uhci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 669 { 670 struct uhci_softc *sc = bus->hci_private; 671 672 #ifdef DIAGNOSTIC 673 if (xfer->busy_free != XFER_BUSY) { 674 printf("uhci_freex: xfer=%p not busy, 0x%08x\n", xfer, 675 xfer->busy_free); 676 } 677 xfer->busy_free = XFER_FREE; 678 if (!UXFER(xfer)->iinfo.isdone) { 679 printf("uhci_freex: !isdone\n"); 680 } 681 #endif 682 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 683 } 684 685 /* 686 * Handle suspend/resume. 687 * 688 * We need to switch to polling mode here, because this routine is 689 * called from an interrupt context. This is all right since we 690 * are almost suspended anyway. 691 */ 692 bool 693 uhci_resume(device_t dv, const pmf_qual_t *qual) 694 { 695 uhci_softc_t *sc = device_private(dv); 696 int cmd; 697 int s; 698 699 s = splhardusb(); 700 701 cmd = UREAD2(sc, UHCI_CMD); 702 sc->sc_bus.use_polling++; 703 UWRITE2(sc, UHCI_INTR, 0); 704 uhci_globalreset(sc); 705 uhci_reset(sc); 706 if (cmd & UHCI_CMD_RS) 707 uhci_run(sc, 0); 708 709 /* restore saved state */ 710 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 711 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 712 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 713 714 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 715 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 716 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 717 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 718 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 719 UHCICMD(sc, UHCI_CMD_MAXP); 720 uhci_run(sc, 1); /* and start traffic again */ 721 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 722 sc->sc_bus.use_polling--; 723 if (sc->sc_intr_xfer != NULL) 724 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, 725 sc->sc_intr_xfer); 726 #ifdef UHCI_DEBUG 727 if (uhcidebug > 2) 728 uhci_dumpregs(sc); 729 #endif 730 731 sc->sc_suspend = PWR_RESUME; 732 splx(s); 733 734 return true; 735 } 736 737 bool 738 uhci_suspend(device_t dv, const pmf_qual_t *qual) 739 { 740 uhci_softc_t *sc = device_private(dv); 741 int cmd; 742 int s; 743 744 s = splhardusb(); 745 746 cmd = UREAD2(sc, UHCI_CMD); 747 748 #ifdef UHCI_DEBUG 749 if (uhcidebug > 2) 750 uhci_dumpregs(sc); 751 #endif 752 if (sc->sc_intr_xfer != NULL) 753 callout_stop(&sc->sc_poll_handle); 754 sc->sc_suspend = PWR_SUSPEND; 755 sc->sc_bus.use_polling++; 756 757 uhci_run(sc, 0); /* stop the controller */ 758 cmd &= ~UHCI_CMD_RS; 759 760 /* save some state if BIOS doesn't */ 761 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 762 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 763 764 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 765 766 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 767 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 768 sc->sc_bus.use_polling--; 769 770 splx(s); 771 772 return true; 773 } 774 775 #ifdef UHCI_DEBUG 776 Static void 777 uhci_dumpregs(uhci_softc_t *sc) 778 { 779 DPRINTFN(-1,("%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, " 780 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 781 device_xname(sc->sc_dev), 782 UREAD2(sc, UHCI_CMD), 783 UREAD2(sc, UHCI_STS), 784 UREAD2(sc, UHCI_INTR), 785 UREAD2(sc, UHCI_FRNUM), 786 UREAD4(sc, UHCI_FLBASEADDR), 787 UREAD1(sc, UHCI_SOF), 788 UREAD2(sc, UHCI_PORTSC1), 789 UREAD2(sc, UHCI_PORTSC2))); 790 } 791 792 void 793 uhci_dump_td(uhci_soft_td_t *p) 794 { 795 char sbuf[128], sbuf2[128]; 796 797 798 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 799 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 800 DPRINTFN(-1,("TD(%p) at %08lx = link=0x%08lx status=0x%08lx " 801 "token=0x%08lx buffer=0x%08lx\n", 802 p, (long)p->physaddr, 803 (long)le32toh(p->td.td_link), 804 (long)le32toh(p->td.td_status), 805 (long)le32toh(p->td.td_token), 806 (long)le32toh(p->td.td_buffer))); 807 808 snprintb(sbuf, sizeof(sbuf), "\20\1T\2Q\3VF", 809 (u_int32_t)le32toh(p->td.td_link)); 810 snprintb(sbuf2, sizeof(sbuf2), 811 "\20\22BITSTUFF\23CRCTO\24NAK\25BABBLE\26DBUFFER\27" 812 "STALLED\30ACTIVE\31IOC\32ISO\33LS\36SPD", 813 (u_int32_t)le32toh(p->td.td_status)); 814 815 DPRINTFN(-1,(" %s %s,errcnt=%d,actlen=%d pid=%02x,addr=%d,endpt=%d," 816 "D=%d,maxlen=%d\n", sbuf, sbuf2, 817 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 818 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 819 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 820 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 821 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 822 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 823 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token)))); 824 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 825 BUS_DMASYNC_PREREAD); 826 } 827 828 void 829 uhci_dump_qh(uhci_soft_qh_t *sqh) 830 { 831 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 832 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 833 DPRINTFN(-1,("QH(%p) at %08x: hlink=%08x elink=%08x\n", sqh, 834 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 835 le32toh(sqh->qh.qh_elink))); 836 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 837 } 838 839 840 #if 1 841 void 842 uhci_dump(void) 843 { 844 uhci_dump_all(thesc); 845 } 846 #endif 847 848 void 849 uhci_dump_all(uhci_softc_t *sc) 850 { 851 uhci_dumpregs(sc); 852 printf("intrs=%d\n", sc->sc_bus.no_intrs); 853 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 854 uhci_dump_qh(sc->sc_lctl_start); 855 } 856 857 858 void 859 uhci_dump_qhs(uhci_soft_qh_t *sqh) 860 { 861 uhci_dump_qh(sqh); 862 863 /* uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 864 * Traverses sideways first, then down. 865 * 866 * QH1 867 * QH2 868 * No QH 869 * TD2.1 870 * TD2.2 871 * TD1.1 872 * etc. 873 * 874 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 875 */ 876 877 878 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 879 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 880 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 881 uhci_dump_qhs(sqh->hlink); 882 else 883 DPRINTF(("No QH\n")); 884 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 885 886 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 887 uhci_dump_tds(sqh->elink); 888 else 889 DPRINTF(("No TD\n")); 890 } 891 892 void 893 uhci_dump_tds(uhci_soft_td_t *std) 894 { 895 uhci_soft_td_t *td; 896 int stop; 897 898 for(td = std; td != NULL; td = td->link.std) { 899 uhci_dump_td(td); 900 901 /* Check whether the link pointer in this TD marks 902 * the link pointer as end of queue. This avoids 903 * printing the free list in case the queue/TD has 904 * already been moved there (seatbelt). 905 */ 906 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 907 sizeof(td->td.td_link), 908 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 909 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 910 le32toh(td->td.td_link) == 0); 911 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 912 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 913 if (stop) 914 break; 915 } 916 } 917 918 Static void 919 uhci_dump_ii(uhci_intr_info_t *ii) 920 { 921 usbd_pipe_handle pipe; 922 usb_endpoint_descriptor_t *ed; 923 usbd_device_handle dev; 924 925 #ifdef DIAGNOSTIC 926 #define DONE ii->isdone 927 #else 928 #define DONE 0 929 #endif 930 if (ii == NULL) { 931 printf("ii NULL\n"); 932 return; 933 } 934 if (ii->xfer == NULL) { 935 printf("ii %p: done=%d xfer=NULL\n", 936 ii, DONE); 937 return; 938 } 939 pipe = ii->xfer->pipe; 940 if (pipe == NULL) { 941 printf("ii %p: done=%d xfer=%p pipe=NULL\n", 942 ii, DONE, ii->xfer); 943 return; 944 } 945 if (pipe->endpoint == NULL) { 946 printf("ii %p: done=%d xfer=%p pipe=%p pipe->endpoint=NULL\n", 947 ii, DONE, ii->xfer, pipe); 948 return; 949 } 950 if (pipe->device == NULL) { 951 printf("ii %p: done=%d xfer=%p pipe=%p pipe->device=NULL\n", 952 ii, DONE, ii->xfer, pipe); 953 return; 954 } 955 ed = pipe->endpoint->edesc; 956 dev = pipe->device; 957 printf("ii %p: done=%d xfer=%p dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 958 ii, DONE, ii->xfer, dev, 959 UGETW(dev->ddesc.idVendor), 960 UGETW(dev->ddesc.idProduct), 961 dev->address, pipe, 962 ed->bEndpointAddress, ed->bmAttributes); 963 #undef DONE 964 } 965 966 void uhci_dump_iis(struct uhci_softc *sc); 967 void 968 uhci_dump_iis(struct uhci_softc *sc) 969 { 970 uhci_intr_info_t *ii; 971 972 printf("intr_info list:\n"); 973 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = LIST_NEXT(ii, list)) 974 uhci_dump_ii(ii); 975 } 976 977 void iidump(void); 978 void iidump(void) { uhci_dump_iis(thesc); } 979 980 #endif 981 982 /* 983 * This routine is executed periodically and simulates interrupts 984 * from the root controller interrupt pipe for port status change. 985 */ 986 void 987 uhci_poll_hub(void *addr) 988 { 989 usbd_xfer_handle xfer = addr; 990 usbd_pipe_handle pipe = xfer->pipe; 991 uhci_softc_t *sc; 992 int s; 993 u_char *p; 994 995 DPRINTFN(20, ("uhci_poll_hub\n")); 996 997 if (__predict_false(pipe->device == NULL || pipe->device->bus == NULL)) 998 return; /* device has detached */ 999 sc = pipe->device->bus->hci_private; 1000 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 1001 1002 p = KERNADDR(&xfer->dmabuf, 0); 1003 p[0] = 0; 1004 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1005 p[0] |= 1<<1; 1006 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1007 p[0] |= 1<<2; 1008 if (p[0] == 0) 1009 /* No change, try again in a while */ 1010 return; 1011 1012 xfer->actlen = 1; 1013 xfer->status = USBD_NORMAL_COMPLETION; 1014 s = splusb(); 1015 xfer->device->bus->intr_context++; 1016 usb_transfer_complete(xfer); 1017 xfer->device->bus->intr_context--; 1018 splx(s); 1019 } 1020 1021 void 1022 uhci_root_intr_done(usbd_xfer_handle xfer) 1023 { 1024 } 1025 1026 void 1027 uhci_root_ctrl_done(usbd_xfer_handle xfer) 1028 { 1029 } 1030 1031 /* 1032 * Let the last QH loop back to the high speed control transfer QH. 1033 * This is what intel calls "bandwidth reclamation" and improves 1034 * USB performance a lot for some devices. 1035 * If we are already looping, just count it. 1036 */ 1037 void 1038 uhci_add_loop(uhci_softc_t *sc) { 1039 #ifdef UHCI_DEBUG 1040 if (uhcinoloop) 1041 return; 1042 #endif 1043 if (++sc->sc_loops == 1) { 1044 DPRINTFN(5,("uhci_start_loop: add\n")); 1045 /* Note, we don't loop back the soft pointer. */ 1046 sc->sc_last_qh->qh.qh_hlink = 1047 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 1048 usb_syncmem(&sc->sc_last_qh->dma, 1049 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1050 sizeof(sc->sc_last_qh->qh.qh_hlink), 1051 BUS_DMASYNC_PREWRITE); 1052 } 1053 } 1054 1055 void 1056 uhci_rem_loop(uhci_softc_t *sc) { 1057 #ifdef UHCI_DEBUG 1058 if (uhcinoloop) 1059 return; 1060 #endif 1061 if (--sc->sc_loops == 0) { 1062 DPRINTFN(5,("uhci_end_loop: remove\n")); 1063 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 1064 usb_syncmem(&sc->sc_last_qh->dma, 1065 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1066 sizeof(sc->sc_last_qh->qh.qh_hlink), 1067 BUS_DMASYNC_PREWRITE); 1068 } 1069 } 1070 1071 /* Add high speed control QH, called at splusb(). */ 1072 void 1073 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1074 { 1075 uhci_soft_qh_t *eqh; 1076 1077 SPLUSBCHECK; 1078 1079 DPRINTFN(10, ("uhci_add_ctrl: sqh=%p\n", sqh)); 1080 eqh = sc->sc_hctl_end; 1081 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1082 sizeof(eqh->qh.qh_hlink), 1083 BUS_DMASYNC_POSTWRITE); 1084 sqh->hlink = eqh->hlink; 1085 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1086 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1087 BUS_DMASYNC_PREWRITE); 1088 eqh->hlink = sqh; 1089 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1090 sc->sc_hctl_end = sqh; 1091 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1092 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1093 #ifdef UHCI_CTL_LOOP 1094 uhci_add_loop(sc); 1095 #endif 1096 } 1097 1098 /* Remove high speed control QH, called at splusb(). */ 1099 void 1100 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1101 { 1102 uhci_soft_qh_t *pqh; 1103 1104 SPLUSBCHECK; 1105 1106 DPRINTFN(10, ("uhci_remove_hs_ctrl: sqh=%p\n", sqh)); 1107 #ifdef UHCI_CTL_LOOP 1108 uhci_rem_loop(sc); 1109 #endif 1110 /* 1111 * The T bit should be set in the elink of the QH so that the HC 1112 * doesn't follow the pointer. This condition may fail if the 1113 * the transferred packet was short so that the QH still points 1114 * at the last used TD. 1115 * In this case we set the T bit and wait a little for the HC 1116 * to stop looking at the TD. 1117 * Note that if the TD chain is large enough, the controller 1118 * may still be looking at the chain at the end of this function. 1119 * uhci_free_std_chain() will make sure the controller stops 1120 * looking at it quickly, but until then we should not change 1121 * sqh->hlink. 1122 */ 1123 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1124 sizeof(sqh->qh.qh_elink), 1125 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1126 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1127 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1128 usb_syncmem(&sqh->dma, 1129 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1130 sizeof(sqh->qh.qh_elink), 1131 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1132 delay(UHCI_QH_REMOVE_DELAY); 1133 } 1134 1135 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1136 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1137 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1138 pqh->hlink = sqh->hlink; 1139 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1140 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1141 sizeof(pqh->qh.qh_hlink), 1142 BUS_DMASYNC_PREWRITE); 1143 delay(UHCI_QH_REMOVE_DELAY); 1144 if (sc->sc_hctl_end == sqh) 1145 sc->sc_hctl_end = pqh; 1146 } 1147 1148 /* Add low speed control QH, called at splusb(). */ 1149 void 1150 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1151 { 1152 uhci_soft_qh_t *eqh; 1153 1154 SPLUSBCHECK; 1155 1156 DPRINTFN(10, ("uhci_add_ls_ctrl: sqh=%p\n", sqh)); 1157 eqh = sc->sc_lctl_end; 1158 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1159 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1160 sqh->hlink = eqh->hlink; 1161 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1162 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1163 BUS_DMASYNC_PREWRITE); 1164 eqh->hlink = sqh; 1165 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1166 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1167 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1168 sc->sc_lctl_end = sqh; 1169 } 1170 1171 /* Remove low speed control QH, called at splusb(). */ 1172 void 1173 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1174 { 1175 uhci_soft_qh_t *pqh; 1176 1177 SPLUSBCHECK; 1178 1179 DPRINTFN(10, ("uhci_remove_ls_ctrl: sqh=%p\n", sqh)); 1180 /* See comment in uhci_remove_hs_ctrl() */ 1181 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1182 sizeof(sqh->qh.qh_elink), 1183 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1184 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1185 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1186 usb_syncmem(&sqh->dma, 1187 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1188 sizeof(sqh->qh.qh_elink), 1189 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1190 delay(UHCI_QH_REMOVE_DELAY); 1191 } 1192 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1193 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1194 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1195 pqh->hlink = sqh->hlink; 1196 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1197 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1198 sizeof(pqh->qh.qh_hlink), 1199 BUS_DMASYNC_PREWRITE); 1200 delay(UHCI_QH_REMOVE_DELAY); 1201 if (sc->sc_lctl_end == sqh) 1202 sc->sc_lctl_end = pqh; 1203 } 1204 1205 /* Add bulk QH, called at splusb(). */ 1206 void 1207 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1208 { 1209 uhci_soft_qh_t *eqh; 1210 1211 SPLUSBCHECK; 1212 1213 DPRINTFN(10, ("uhci_add_bulk: sqh=%p\n", sqh)); 1214 eqh = sc->sc_bulk_end; 1215 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1216 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1217 sqh->hlink = eqh->hlink; 1218 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1219 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1220 BUS_DMASYNC_PREWRITE); 1221 eqh->hlink = sqh; 1222 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1223 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1224 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1225 sc->sc_bulk_end = sqh; 1226 uhci_add_loop(sc); 1227 } 1228 1229 /* Remove bulk QH, called at splusb(). */ 1230 void 1231 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1232 { 1233 uhci_soft_qh_t *pqh; 1234 1235 SPLUSBCHECK; 1236 1237 DPRINTFN(10, ("uhci_remove_bulk: sqh=%p\n", sqh)); 1238 uhci_rem_loop(sc); 1239 /* See comment in uhci_remove_hs_ctrl() */ 1240 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1241 sizeof(sqh->qh.qh_elink), 1242 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1243 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1244 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1245 usb_syncmem(&sqh->dma, 1246 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1247 sizeof(sqh->qh.qh_elink), 1248 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1249 delay(UHCI_QH_REMOVE_DELAY); 1250 } 1251 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1252 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1253 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1254 pqh->hlink = sqh->hlink; 1255 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1256 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1257 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1258 delay(UHCI_QH_REMOVE_DELAY); 1259 if (sc->sc_bulk_end == sqh) 1260 sc->sc_bulk_end = pqh; 1261 } 1262 1263 Static int uhci_intr1(uhci_softc_t *); 1264 1265 int 1266 uhci_intr(void *arg) 1267 { 1268 uhci_softc_t *sc = arg; 1269 1270 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1271 return (0); 1272 1273 if (sc->sc_bus.use_polling || UREAD2(sc, UHCI_INTR) == 0) { 1274 #ifdef DIAGNOSTIC 1275 DPRINTFN(16, ("uhci_intr: ignored interrupt while polling\n")); 1276 #endif 1277 return (0); 1278 } 1279 1280 return (uhci_intr1(sc)); 1281 } 1282 1283 int 1284 uhci_intr1(uhci_softc_t *sc) 1285 { 1286 int status; 1287 int ack; 1288 1289 #ifdef UHCI_DEBUG 1290 if (uhcidebug > 15) { 1291 DPRINTF(("%s: uhci_intr1\n", device_xname(sc->sc_dev))); 1292 uhci_dumpregs(sc); 1293 } 1294 #endif 1295 1296 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1297 if (status == 0) /* The interrupt was not for us. */ 1298 return (0); 1299 1300 if (sc->sc_suspend != PWR_RESUME) { 1301 #ifdef DIAGNOSTIC 1302 printf("%s: interrupt while not operating ignored\n", 1303 device_xname(sc->sc_dev)); 1304 #endif 1305 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1306 return (0); 1307 } 1308 1309 ack = 0; 1310 if (status & UHCI_STS_USBINT) 1311 ack |= UHCI_STS_USBINT; 1312 if (status & UHCI_STS_USBEI) 1313 ack |= UHCI_STS_USBEI; 1314 if (status & UHCI_STS_RD) { 1315 ack |= UHCI_STS_RD; 1316 #ifdef UHCI_DEBUG 1317 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1318 #endif 1319 } 1320 if (status & UHCI_STS_HSE) { 1321 ack |= UHCI_STS_HSE; 1322 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1323 } 1324 if (status & UHCI_STS_HCPE) { 1325 ack |= UHCI_STS_HCPE; 1326 printf("%s: host controller process error\n", 1327 device_xname(sc->sc_dev)); 1328 } 1329 1330 /* When HCHalted=1 and Run/Stop=0 , it is normal */ 1331 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 1332 /* no acknowledge needed */ 1333 if (!sc->sc_dying) { 1334 printf("%s: host controller halted\n", 1335 device_xname(sc->sc_dev)); 1336 #ifdef UHCI_DEBUG 1337 uhci_dump_all(sc); 1338 #endif 1339 } 1340 sc->sc_dying = 1; 1341 } 1342 1343 if (!ack) 1344 return (0); /* nothing to acknowledge */ 1345 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1346 1347 sc->sc_bus.no_intrs++; 1348 usb_schedsoftintr(&sc->sc_bus); 1349 1350 DPRINTFN(15, ("%s: uhci_intr: exit\n", device_xname(sc->sc_dev))); 1351 1352 return (1); 1353 } 1354 1355 void 1356 uhci_softintr(void *v) 1357 { 1358 struct usbd_bus *bus = v; 1359 uhci_softc_t *sc = bus->hci_private; 1360 uhci_intr_info_t *ii, *nextii; 1361 1362 DPRINTFN(10,("%s: uhci_softintr (%d)\n", device_xname(sc->sc_dev), 1363 sc->sc_bus.intr_context)); 1364 1365 sc->sc_bus.intr_context++; 1366 1367 /* 1368 * Interrupts on UHCI really suck. When the host controller 1369 * interrupts because a transfer is completed there is no 1370 * way of knowing which transfer it was. You can scan down 1371 * the TDs and QHs of the previous frame to limit the search, 1372 * but that assumes that the interrupt was not delayed by more 1373 * than 1 ms, which may not always be true (e.g. after debug 1374 * output on a slow console). 1375 * We scan all interrupt descriptors to see if any have 1376 * completed. 1377 */ 1378 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = nextii) { 1379 nextii = LIST_NEXT(ii, list); 1380 uhci_check_intr(sc, ii); 1381 } 1382 1383 #ifdef USB_USE_SOFTINTR 1384 if (sc->sc_softwake) { 1385 sc->sc_softwake = 0; 1386 wakeup(&sc->sc_softwake); 1387 } 1388 #endif /* USB_USE_SOFTINTR */ 1389 1390 sc->sc_bus.intr_context--; 1391 } 1392 1393 /* Check for an interrupt. */ 1394 void 1395 uhci_check_intr(uhci_softc_t *sc, uhci_intr_info_t *ii) 1396 { 1397 uhci_soft_td_t *std, *lstd; 1398 u_int32_t status; 1399 1400 DPRINTFN(15, ("uhci_check_intr: ii=%p\n", ii)); 1401 #ifdef DIAGNOSTIC 1402 if (ii == NULL) { 1403 printf("uhci_check_intr: no ii? %p\n", ii); 1404 return; 1405 } 1406 #endif 1407 if (ii->xfer->status == USBD_CANCELLED || 1408 ii->xfer->status == USBD_TIMEOUT) { 1409 DPRINTF(("uhci_check_intr: aborted xfer=%p\n", ii->xfer)); 1410 return; 1411 } 1412 1413 if (ii->stdstart == NULL) 1414 return; 1415 lstd = ii->stdend; 1416 #ifdef DIAGNOSTIC 1417 if (lstd == NULL) { 1418 printf("uhci_check_intr: std==0\n"); 1419 return; 1420 } 1421 #endif 1422 /* 1423 * If the last TD is still active we need to check whether there 1424 * is an error somewhere in the middle, or whether there was a 1425 * short packet (SPD and not ACTIVE). 1426 */ 1427 usb_syncmem(&lstd->dma, 1428 lstd->offs + offsetof(uhci_td_t, td_status), 1429 sizeof(lstd->td.td_status), 1430 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1431 if (le32toh(lstd->td.td_status) & UHCI_TD_ACTIVE) { 1432 DPRINTFN(12, ("uhci_check_intr: active ii=%p\n", ii)); 1433 for (std = ii->stdstart; std != lstd; std = std->link.std) { 1434 usb_syncmem(&std->dma, 1435 std->offs + offsetof(uhci_td_t, td_status), 1436 sizeof(std->td.td_status), 1437 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1438 status = le32toh(std->td.td_status); 1439 usb_syncmem(&std->dma, 1440 std->offs + offsetof(uhci_td_t, td_status), 1441 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1442 /* If there's an active TD the xfer isn't done. */ 1443 if (status & UHCI_TD_ACTIVE) 1444 break; 1445 /* Any kind of error makes the xfer done. */ 1446 if (status & UHCI_TD_STALLED) 1447 goto done; 1448 /* We want short packets, and it is short: it's done */ 1449 usb_syncmem(&std->dma, 1450 std->offs + offsetof(uhci_td_t, td_token), 1451 sizeof(std->td.td_token), 1452 BUS_DMASYNC_POSTWRITE); 1453 if ((status & UHCI_TD_SPD) && 1454 UHCI_TD_GET_ACTLEN(status) < 1455 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) 1456 goto done; 1457 } 1458 DPRINTFN(12, ("uhci_check_intr: ii=%p std=%p still active\n", 1459 ii, ii->stdstart)); 1460 usb_syncmem(&lstd->dma, 1461 lstd->offs + offsetof(uhci_td_t, td_status), 1462 sizeof(lstd->td.td_status), 1463 BUS_DMASYNC_PREREAD); 1464 return; 1465 } 1466 done: 1467 DPRINTFN(12, ("uhci_check_intr: ii=%p done\n", ii)); 1468 callout_stop(&ii->xfer->timeout_handle); 1469 uhci_idone(ii); 1470 } 1471 1472 /* Called at splusb() */ 1473 void 1474 uhci_idone(uhci_intr_info_t *ii) 1475 { 1476 usbd_xfer_handle xfer = ii->xfer; 1477 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 1478 uhci_soft_td_t *std; 1479 u_int32_t status = 0, nstatus; 1480 int actlen; 1481 1482 DPRINTFN(12, ("uhci_idone: ii=%p\n", ii)); 1483 #ifdef DIAGNOSTIC 1484 { 1485 int s = splhigh(); 1486 if (ii->isdone) { 1487 splx(s); 1488 #ifdef UHCI_DEBUG 1489 printf("uhci_idone: ii is done!\n "); 1490 uhci_dump_ii(ii); 1491 #else 1492 printf("uhci_idone: ii=%p is done!\n", ii); 1493 #endif 1494 return; 1495 } 1496 ii->isdone = 1; 1497 splx(s); 1498 } 1499 #endif 1500 1501 if (xfer->nframes != 0) { 1502 /* Isoc transfer, do things differently. */ 1503 uhci_soft_td_t **stds = upipe->u.iso.stds; 1504 int i, n, nframes, len; 1505 1506 DPRINTFN(5,("uhci_idone: ii=%p isoc ready\n", ii)); 1507 1508 nframes = xfer->nframes; 1509 actlen = 0; 1510 n = UXFER(xfer)->curframe; 1511 for (i = 0; i < nframes; i++) { 1512 std = stds[n]; 1513 #ifdef UHCI_DEBUG 1514 if (uhcidebug > 5) { 1515 DPRINTFN(-1,("uhci_idone: isoc TD %d\n", i)); 1516 uhci_dump_td(std); 1517 } 1518 #endif 1519 if (++n >= UHCI_VFRAMELIST_COUNT) 1520 n = 0; 1521 usb_syncmem(&std->dma, 1522 std->offs + offsetof(uhci_td_t, td_status), 1523 sizeof(std->td.td_status), 1524 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1525 status = le32toh(std->td.td_status); 1526 len = UHCI_TD_GET_ACTLEN(status); 1527 xfer->frlengths[i] = len; 1528 actlen += len; 1529 } 1530 upipe->u.iso.inuse -= nframes; 1531 xfer->actlen = actlen; 1532 xfer->status = USBD_NORMAL_COMPLETION; 1533 goto end; 1534 } 1535 1536 #ifdef UHCI_DEBUG 1537 DPRINTFN(10, ("uhci_idone: ii=%p, xfer=%p, pipe=%p ready\n", 1538 ii, xfer, upipe)); 1539 if (uhcidebug > 10) 1540 uhci_dump_tds(ii->stdstart); 1541 #endif 1542 1543 /* The transfer is done, compute actual length and status. */ 1544 actlen = 0; 1545 for (std = ii->stdstart; std != NULL; std = std->link.std) { 1546 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1547 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1548 nstatus = le32toh(std->td.td_status); 1549 if (nstatus & UHCI_TD_ACTIVE) 1550 break; 1551 1552 status = nstatus; 1553 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1554 UHCI_TD_PID_SETUP) 1555 actlen += UHCI_TD_GET_ACTLEN(status); 1556 else { 1557 /* 1558 * UHCI will report CRCTO in addition to a STALL or NAK 1559 * for a SETUP transaction. See section 3.2.2, "TD 1560 * CONTROL AND STATUS". 1561 */ 1562 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1563 status &= ~UHCI_TD_CRCTO; 1564 } 1565 } 1566 /* If there are left over TDs we need to update the toggle. */ 1567 if (std != NULL) 1568 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1569 1570 status &= UHCI_TD_ERROR; 1571 DPRINTFN(10, ("uhci_idone: actlen=%d, status=0x%x\n", 1572 actlen, status)); 1573 xfer->actlen = actlen; 1574 if (status != 0) { 1575 #ifdef UHCI_DEBUG 1576 char sbuf[128]; 1577 1578 snprintb(sbuf, sizeof(sbuf), 1579 "\20\22BITSTUFF\23CRCTO\24NAK\25" 1580 "BABBLE\26DBUFFER\27STALLED\30ACTIVE",(u_int32_t)status); 1581 1582 DPRINTFN((status == UHCI_TD_STALLED)*10, 1583 ("uhci_idone: error, addr=%d, endpt=0x%02x, " 1584 "status 0x%s\n", 1585 xfer->pipe->device->address, 1586 xfer->pipe->endpoint->edesc->bEndpointAddress, 1587 sbuf)); 1588 #endif 1589 1590 if (status == UHCI_TD_STALLED) 1591 xfer->status = USBD_STALLED; 1592 else 1593 xfer->status = USBD_IOERROR; /* more info XXX */ 1594 } else { 1595 xfer->status = USBD_NORMAL_COMPLETION; 1596 } 1597 1598 end: 1599 usb_transfer_complete(xfer); 1600 DPRINTFN(12, ("uhci_idone: ii=%p done\n", ii)); 1601 } 1602 1603 /* 1604 * Called when a request does not complete. 1605 */ 1606 void 1607 uhci_timeout(void *addr) 1608 { 1609 uhci_intr_info_t *ii = addr; 1610 struct uhci_xfer *uxfer = UXFER(ii->xfer); 1611 struct uhci_pipe *upipe = (struct uhci_pipe *)uxfer->xfer.pipe; 1612 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 1613 1614 DPRINTF(("uhci_timeout: uxfer=%p\n", uxfer)); 1615 1616 if (sc->sc_dying) { 1617 uhci_abort_xfer(&uxfer->xfer, USBD_TIMEOUT); 1618 return; 1619 } 1620 1621 /* Execute the abort in a process context. */ 1622 usb_init_task(&uxfer->abort_task, uhci_timeout_task, ii->xfer); 1623 usb_add_task(uxfer->xfer.pipe->device, &uxfer->abort_task, 1624 USB_TASKQ_HC); 1625 } 1626 1627 void 1628 uhci_timeout_task(void *addr) 1629 { 1630 usbd_xfer_handle xfer = addr; 1631 int s; 1632 1633 DPRINTF(("uhci_timeout_task: xfer=%p\n", xfer)); 1634 1635 s = splusb(); 1636 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1637 splx(s); 1638 } 1639 1640 /* 1641 * Wait here until controller claims to have an interrupt. 1642 * Then call uhci_intr and return. Use timeout to avoid waiting 1643 * too long. 1644 * Only used during boot when interrupts are not enabled yet. 1645 */ 1646 void 1647 uhci_waitintr(uhci_softc_t *sc, usbd_xfer_handle xfer) 1648 { 1649 int timo = xfer->timeout; 1650 uhci_intr_info_t *ii; 1651 1652 DPRINTFN(10,("uhci_waitintr: timeout = %dms\n", timo)); 1653 1654 xfer->status = USBD_IN_PROGRESS; 1655 for (; timo >= 0; timo--) { 1656 usb_delay_ms(&sc->sc_bus, 1); 1657 DPRINTFN(20,("uhci_waitintr: 0x%04x\n", UREAD2(sc, UHCI_STS))); 1658 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1659 uhci_intr1(sc); 1660 if (xfer->status != USBD_IN_PROGRESS) 1661 return; 1662 } 1663 } 1664 1665 /* Timeout */ 1666 DPRINTF(("uhci_waitintr: timeout\n")); 1667 for (ii = LIST_FIRST(&sc->sc_intrhead); 1668 ii != NULL && ii->xfer != xfer; 1669 ii = LIST_NEXT(ii, list)) 1670 ; 1671 #ifdef DIAGNOSTIC 1672 if (ii == NULL) 1673 panic("uhci_waitintr: lost intr_info"); 1674 #endif 1675 uhci_idone(ii); 1676 } 1677 1678 void 1679 uhci_poll(struct usbd_bus *bus) 1680 { 1681 uhci_softc_t *sc = bus->hci_private; 1682 1683 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) 1684 uhci_intr1(sc); 1685 } 1686 1687 void 1688 uhci_reset(uhci_softc_t *sc) 1689 { 1690 int n; 1691 1692 UHCICMD(sc, UHCI_CMD_HCRESET); 1693 /* The reset bit goes low when the controller is done. */ 1694 for (n = 0; n < UHCI_RESET_TIMEOUT && 1695 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1696 usb_delay_ms(&sc->sc_bus, 1); 1697 if (n >= UHCI_RESET_TIMEOUT) 1698 printf("%s: controller did not reset\n", 1699 device_xname(sc->sc_dev)); 1700 } 1701 1702 usbd_status 1703 uhci_run(uhci_softc_t *sc, int run) 1704 { 1705 int s, n, running; 1706 u_int16_t cmd; 1707 1708 run = run != 0; 1709 s = splhardusb(); 1710 DPRINTF(("uhci_run: setting run=%d\n", run)); 1711 cmd = UREAD2(sc, UHCI_CMD); 1712 if (run) 1713 cmd |= UHCI_CMD_RS; 1714 else 1715 cmd &= ~UHCI_CMD_RS; 1716 UHCICMD(sc, cmd); 1717 for(n = 0; n < 10; n++) { 1718 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1719 /* return when we've entered the state we want */ 1720 if (run == running) { 1721 splx(s); 1722 DPRINTF(("uhci_run: done cmd=0x%x sts=0x%x\n", 1723 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS))); 1724 return (USBD_NORMAL_COMPLETION); 1725 } 1726 usb_delay_ms(&sc->sc_bus, 1); 1727 } 1728 splx(s); 1729 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1730 run ? "start" : "stop"); 1731 return (USBD_IOERROR); 1732 } 1733 1734 /* 1735 * Memory management routines. 1736 * uhci_alloc_std allocates TDs 1737 * uhci_alloc_sqh allocates QHs 1738 * These two routines do their own free list management, 1739 * partly for speed, partly because allocating DMAable memory 1740 * has page size granularaity so much memory would be wasted if 1741 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1742 */ 1743 1744 uhci_soft_td_t * 1745 uhci_alloc_std(uhci_softc_t *sc) 1746 { 1747 uhci_soft_td_t *std; 1748 usbd_status err; 1749 int i, offs; 1750 usb_dma_t dma; 1751 1752 if (sc->sc_freetds == NULL) { 1753 DPRINTFN(2,("uhci_alloc_std: allocating chunk\n")); 1754 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1755 UHCI_TD_ALIGN, &dma); 1756 if (err) 1757 return (0); 1758 for(i = 0; i < UHCI_STD_CHUNK; i++) { 1759 offs = i * UHCI_STD_SIZE; 1760 std = KERNADDR(&dma, offs); 1761 std->physaddr = DMAADDR(&dma, offs); 1762 std->dma = dma; 1763 std->offs = offs; 1764 std->link.std = sc->sc_freetds; 1765 sc->sc_freetds = std; 1766 } 1767 } 1768 std = sc->sc_freetds; 1769 sc->sc_freetds = std->link.std; 1770 memset(&std->td, 0, sizeof(uhci_td_t)); 1771 return std; 1772 } 1773 1774 void 1775 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1776 { 1777 #ifdef DIAGNOSTIC 1778 #define TD_IS_FREE 0x12345678 1779 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1780 printf("uhci_free_std: freeing free TD %p\n", std); 1781 return; 1782 } 1783 std->td.td_token = htole32(TD_IS_FREE); 1784 #endif 1785 std->link.std = sc->sc_freetds; 1786 sc->sc_freetds = std; 1787 } 1788 1789 uhci_soft_qh_t * 1790 uhci_alloc_sqh(uhci_softc_t *sc) 1791 { 1792 uhci_soft_qh_t *sqh; 1793 usbd_status err; 1794 int i, offs; 1795 usb_dma_t dma; 1796 1797 if (sc->sc_freeqhs == NULL) { 1798 DPRINTFN(2, ("uhci_alloc_sqh: allocating chunk\n")); 1799 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1800 UHCI_QH_ALIGN, &dma); 1801 if (err) 1802 return (0); 1803 for(i = 0; i < UHCI_SQH_CHUNK; i++) { 1804 offs = i * UHCI_SQH_SIZE; 1805 sqh = KERNADDR(&dma, offs); 1806 sqh->physaddr = DMAADDR(&dma, offs); 1807 sqh->dma = dma; 1808 sqh->offs = offs; 1809 sqh->hlink = sc->sc_freeqhs; 1810 sc->sc_freeqhs = sqh; 1811 } 1812 } 1813 sqh = sc->sc_freeqhs; 1814 sc->sc_freeqhs = sqh->hlink; 1815 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1816 return (sqh); 1817 } 1818 1819 void 1820 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1821 { 1822 sqh->hlink = sc->sc_freeqhs; 1823 sc->sc_freeqhs = sqh; 1824 } 1825 1826 void 1827 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1828 uhci_soft_td_t *stdend) 1829 { 1830 uhci_soft_td_t *p; 1831 1832 /* 1833 * to avoid race condition with the controller which may be looking 1834 * at this chain, we need to first invalidate all links, and 1835 * then wait for the controller to move to another queue 1836 */ 1837 for (p = std; p != stdend; p = p->link.std) { 1838 usb_syncmem(&p->dma, 1839 p->offs + offsetof(uhci_td_t, td_link), 1840 sizeof(p->td.td_link), 1841 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1842 if ((p->td.td_link & UHCI_PTR_T) == 0) { 1843 p->td.td_link = UHCI_PTR_T; 1844 usb_syncmem(&p->dma, 1845 p->offs + offsetof(uhci_td_t, td_link), 1846 sizeof(p->td.td_link), 1847 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1848 } 1849 } 1850 delay(UHCI_QH_REMOVE_DELAY); 1851 1852 for (; std != stdend; std = p) { 1853 p = std->link.std; 1854 uhci_free_std(sc, std); 1855 } 1856 } 1857 1858 usbd_status 1859 uhci_alloc_std_chain(struct uhci_pipe *upipe, uhci_softc_t *sc, int len, 1860 int rd, u_int16_t flags, usb_dma_t *dma, 1861 uhci_soft_td_t **sp, uhci_soft_td_t **ep) 1862 { 1863 uhci_soft_td_t *p, *lastp; 1864 uhci_physaddr_t lastlink; 1865 int i, ntd, l, tog, maxp; 1866 u_int32_t status; 1867 int addr = upipe->pipe.device->address; 1868 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 1869 1870 DPRINTFN(8, ("uhci_alloc_std_chain: addr=%d endpt=%d len=%d speed=%d " 1871 "flags=0x%x\n", addr, UE_GET_ADDR(endpt), len, 1872 upipe->pipe.device->speed, flags)); 1873 maxp = UGETW(upipe->pipe.endpoint->edesc->wMaxPacketSize); 1874 if (maxp == 0) { 1875 printf("uhci_alloc_std_chain: maxp=0\n"); 1876 return (USBD_INVAL); 1877 } 1878 ntd = (len + maxp - 1) / maxp; 1879 if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0) 1880 ntd++; 1881 DPRINTFN(10, ("uhci_alloc_std_chain: maxp=%d ntd=%d\n", maxp, ntd)); 1882 if (ntd == 0) { 1883 *sp = *ep = 0; 1884 DPRINTFN(-1,("uhci_alloc_std_chain: ntd=0\n")); 1885 return (USBD_NORMAL_COMPLETION); 1886 } 1887 tog = upipe->nexttoggle; 1888 if (ntd % 2 == 0) 1889 tog ^= 1; 1890 upipe->nexttoggle = tog ^ 1; 1891 lastp = NULL; 1892 lastlink = UHCI_PTR_T; 1893 ntd--; 1894 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 1895 if (upipe->pipe.device->speed == USB_SPEED_LOW) 1896 status |= UHCI_TD_LS; 1897 if (flags & USBD_SHORT_XFER_OK) 1898 status |= UHCI_TD_SPD; 1899 usb_syncmem(dma, 0, len, 1900 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1901 for (i = ntd; i >= 0; i--) { 1902 p = uhci_alloc_std(sc); 1903 if (p == NULL) { 1904 KASSERT(lastp != NULL); 1905 uhci_free_std_chain(sc, lastp, NULL); 1906 return (USBD_NOMEM); 1907 } 1908 p->link.std = lastp; 1909 p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD); 1910 lastp = p; 1911 lastlink = p->physaddr; 1912 p->td.td_status = htole32(status); 1913 if (i == ntd) { 1914 /* last TD */ 1915 l = len % maxp; 1916 if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER)) 1917 l = maxp; 1918 *ep = p; 1919 } else 1920 l = maxp; 1921 p->td.td_token = 1922 htole32(rd ? UHCI_TD_IN (l, endpt, addr, tog) : 1923 UHCI_TD_OUT(l, endpt, addr, tog)); 1924 p->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 1925 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 1926 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1927 tog ^= 1; 1928 } 1929 *sp = lastp; 1930 DPRINTFN(10, ("uhci_alloc_std_chain: nexttog=%d\n", 1931 upipe->nexttoggle)); 1932 return (USBD_NORMAL_COMPLETION); 1933 } 1934 1935 void 1936 uhci_device_clear_toggle(usbd_pipe_handle pipe) 1937 { 1938 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 1939 upipe->nexttoggle = 0; 1940 } 1941 1942 void 1943 uhci_noop(usbd_pipe_handle pipe) 1944 { 1945 } 1946 1947 usbd_status 1948 uhci_device_bulk_transfer(usbd_xfer_handle xfer) 1949 { 1950 usbd_status err; 1951 1952 /* Insert last in queue. */ 1953 err = usb_insert_transfer(xfer); 1954 if (err) 1955 return (err); 1956 1957 /* 1958 * Pipe isn't running (otherwise err would be USBD_INPROG), 1959 * so start it first. 1960 */ 1961 return (uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1962 } 1963 1964 usbd_status 1965 uhci_device_bulk_start(usbd_xfer_handle xfer) 1966 { 1967 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 1968 usbd_device_handle dev = upipe->pipe.device; 1969 uhci_softc_t *sc = dev->bus->hci_private; 1970 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 1971 uhci_soft_td_t *data, *dataend; 1972 uhci_soft_qh_t *sqh; 1973 usbd_status err; 1974 int len, isread, endpt; 1975 int s; 1976 1977 DPRINTFN(3, ("uhci_device_bulk_start: xfer=%p len=%d flags=%d ii=%p\n", 1978 xfer, xfer->length, xfer->flags, ii)); 1979 1980 if (sc->sc_dying) 1981 return (USBD_IOERROR); 1982 1983 #ifdef DIAGNOSTIC 1984 if (xfer->rqflags & URQ_REQUEST) 1985 panic("uhci_device_bulk_transfer: a request"); 1986 #endif 1987 1988 len = xfer->length; 1989 endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 1990 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 1991 sqh = upipe->u.bulk.sqh; 1992 1993 upipe->u.bulk.isread = isread; 1994 upipe->u.bulk.length = len; 1995 1996 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->flags, 1997 &xfer->dmabuf, &data, &dataend); 1998 if (err) 1999 return (err); 2000 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2001 usb_syncmem(&dataend->dma, 2002 dataend->offs + offsetof(uhci_td_t, td_status), 2003 sizeof(dataend->td.td_status), 2004 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2005 2006 2007 #ifdef UHCI_DEBUG 2008 if (uhcidebug > 8) { 2009 DPRINTF(("uhci_device_bulk_transfer: data(1)\n")); 2010 uhci_dump_tds(data); 2011 } 2012 #endif 2013 2014 /* Set up interrupt info. */ 2015 ii->xfer = xfer; 2016 ii->stdstart = data; 2017 ii->stdend = dataend; 2018 #ifdef DIAGNOSTIC 2019 if (!ii->isdone) { 2020 printf("uhci_device_bulk_transfer: not done, ii=%p\n", ii); 2021 } 2022 ii->isdone = 0; 2023 #endif 2024 2025 sqh->elink = data; 2026 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2027 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2028 2029 s = splusb(); 2030 uhci_add_bulk(sc, sqh); 2031 uhci_add_intr_info(sc, ii); 2032 2033 if (xfer->timeout && !sc->sc_bus.use_polling) { 2034 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 2035 uhci_timeout, ii); 2036 } 2037 xfer->status = USBD_IN_PROGRESS; 2038 splx(s); 2039 2040 #ifdef UHCI_DEBUG 2041 if (uhcidebug > 10) { 2042 DPRINTF(("uhci_device_bulk_transfer: data(2)\n")); 2043 uhci_dump_tds(data); 2044 } 2045 #endif 2046 2047 if (sc->sc_bus.use_polling) 2048 uhci_waitintr(sc, xfer); 2049 2050 return (USBD_IN_PROGRESS); 2051 } 2052 2053 /* Abort a device bulk request. */ 2054 void 2055 uhci_device_bulk_abort(usbd_xfer_handle xfer) 2056 { 2057 DPRINTF(("uhci_device_bulk_abort:\n")); 2058 uhci_abort_xfer(xfer, USBD_CANCELLED); 2059 } 2060 2061 /* 2062 * Abort a device request. 2063 * If this routine is called at splusb() it guarantees that the request 2064 * will be removed from the hardware scheduling and that the callback 2065 * for it will be called with USBD_CANCELLED status. 2066 * It's impossible to guarantee that the requested transfer will not 2067 * have happened since the hardware runs concurrently. 2068 * If the transaction has already happened we rely on the ordinary 2069 * interrupt processing to process it. 2070 */ 2071 void 2072 uhci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2073 { 2074 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2075 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2076 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 2077 uhci_soft_td_t *std; 2078 int s; 2079 int wake; 2080 2081 DPRINTFN(1,("uhci_abort_xfer: xfer=%p, status=%d\n", xfer, status)); 2082 2083 if (sc->sc_dying) { 2084 /* If we're dying, just do the software part. */ 2085 s = splusb(); 2086 xfer->status = status; /* make software ignore it */ 2087 callout_stop(&xfer->timeout_handle); 2088 usb_transfer_complete(xfer); 2089 splx(s); 2090 return; 2091 } 2092 2093 if (xfer->device->bus->intr_context || !curproc) 2094 panic("uhci_abort_xfer: not in process context"); 2095 2096 /* 2097 * If an abort is already in progress then just wait for it to 2098 * complete and return. 2099 */ 2100 if (xfer->hcflags & UXFER_ABORTING) { 2101 DPRINTFN(2, ("uhci_abort_xfer: already aborting\n")); 2102 #ifdef DIAGNOSTIC 2103 if (status == USBD_TIMEOUT) 2104 printf("uhci_abort_xfer: TIMEOUT while aborting\n"); 2105 #endif 2106 /* Override the status which might be USBD_TIMEOUT. */ 2107 xfer->status = status; 2108 DPRINTFN(2, ("uhci_abort_xfer: waiting for abort to finish\n")); 2109 xfer->hcflags |= UXFER_ABORTWAIT; 2110 while (xfer->hcflags & UXFER_ABORTING) 2111 tsleep(&xfer->hcflags, PZERO, "uhciaw", 0); 2112 return; 2113 } 2114 xfer->hcflags |= UXFER_ABORTING; 2115 2116 /* 2117 * Step 1: Make interrupt routine and hardware ignore xfer. 2118 */ 2119 s = splusb(); 2120 xfer->status = status; /* make software ignore it */ 2121 callout_stop(&xfer->timeout_handle); 2122 DPRINTFN(1,("uhci_abort_xfer: stop ii=%p\n", ii)); 2123 for (std = ii->stdstart; std != NULL; std = std->link.std) { 2124 usb_syncmem(&std->dma, 2125 std->offs + offsetof(uhci_td_t, td_status), 2126 sizeof(std->td.td_status), 2127 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2128 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2129 usb_syncmem(&std->dma, 2130 std->offs + offsetof(uhci_td_t, td_status), 2131 sizeof(std->td.td_status), 2132 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2133 } 2134 splx(s); 2135 2136 /* 2137 * Step 2: Wait until we know hardware has finished any possible 2138 * use of the xfer. Also make sure the soft interrupt routine 2139 * has run. 2140 */ 2141 usb_delay_ms(upipe->pipe.device->bus, 2); /* Hardware finishes in 1ms */ 2142 s = splusb(); 2143 #ifdef USB_USE_SOFTINTR 2144 sc->sc_softwake = 1; 2145 #endif /* USB_USE_SOFTINTR */ 2146 usb_schedsoftintr(&sc->sc_bus); 2147 #ifdef USB_USE_SOFTINTR 2148 DPRINTFN(1,("uhci_abort_xfer: tsleep\n")); 2149 tsleep(&sc->sc_softwake, PZERO, "uhciab", 0); 2150 #endif /* USB_USE_SOFTINTR */ 2151 splx(s); 2152 2153 /* 2154 * Step 3: Execute callback. 2155 */ 2156 DPRINTFN(1,("uhci_abort_xfer: callback\n")); 2157 s = splusb(); 2158 #ifdef DIAGNOSTIC 2159 ii->isdone = 1; 2160 #endif 2161 wake = xfer->hcflags & UXFER_ABORTWAIT; 2162 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2163 usb_transfer_complete(xfer); 2164 if (wake) 2165 wakeup(&xfer->hcflags); 2166 splx(s); 2167 } 2168 2169 /* Close a device bulk pipe. */ 2170 void 2171 uhci_device_bulk_close(usbd_pipe_handle pipe) 2172 { 2173 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2174 usbd_device_handle dev = upipe->pipe.device; 2175 uhci_softc_t *sc = dev->bus->hci_private; 2176 2177 uhci_free_sqh(sc, upipe->u.bulk.sqh); 2178 2179 pipe->endpoint->datatoggle = upipe->nexttoggle; 2180 } 2181 2182 usbd_status 2183 uhci_device_ctrl_transfer(usbd_xfer_handle xfer) 2184 { 2185 usbd_status err; 2186 2187 /* Insert last in queue. */ 2188 err = usb_insert_transfer(xfer); 2189 if (err) 2190 return (err); 2191 2192 /* 2193 * Pipe isn't running (otherwise err would be USBD_INPROG), 2194 * so start it first. 2195 */ 2196 return (uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2197 } 2198 2199 usbd_status 2200 uhci_device_ctrl_start(usbd_xfer_handle xfer) 2201 { 2202 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2203 usbd_status err; 2204 2205 if (sc->sc_dying) 2206 return (USBD_IOERROR); 2207 2208 #ifdef DIAGNOSTIC 2209 if (!(xfer->rqflags & URQ_REQUEST)) 2210 panic("uhci_device_ctrl_transfer: not a request"); 2211 #endif 2212 2213 err = uhci_device_request(xfer); 2214 if (err) 2215 return (err); 2216 2217 if (sc->sc_bus.use_polling) 2218 uhci_waitintr(sc, xfer); 2219 return (USBD_IN_PROGRESS); 2220 } 2221 2222 usbd_status 2223 uhci_device_intr_transfer(usbd_xfer_handle xfer) 2224 { 2225 usbd_status err; 2226 2227 /* Insert last in queue. */ 2228 err = usb_insert_transfer(xfer); 2229 if (err) 2230 return (err); 2231 2232 /* 2233 * Pipe isn't running (otherwise err would be USBD_INPROG), 2234 * so start it first. 2235 */ 2236 return (uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2237 } 2238 2239 usbd_status 2240 uhci_device_intr_start(usbd_xfer_handle xfer) 2241 { 2242 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2243 usbd_device_handle dev = upipe->pipe.device; 2244 uhci_softc_t *sc = dev->bus->hci_private; 2245 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2246 uhci_soft_td_t *data, *dataend; 2247 uhci_soft_qh_t *sqh; 2248 usbd_status err; 2249 int isread, endpt; 2250 int i, s; 2251 2252 if (sc->sc_dying) 2253 return (USBD_IOERROR); 2254 2255 DPRINTFN(3,("uhci_device_intr_transfer: xfer=%p len=%d flags=%d\n", 2256 xfer, xfer->length, xfer->flags)); 2257 2258 #ifdef DIAGNOSTIC 2259 if (xfer->rqflags & URQ_REQUEST) 2260 panic("uhci_device_intr_transfer: a request"); 2261 #endif 2262 2263 endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2264 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2265 2266 upipe->u.intr.isread = isread; 2267 2268 err = uhci_alloc_std_chain(upipe, sc, xfer->length, isread, 2269 xfer->flags, &xfer->dmabuf, &data, 2270 &dataend); 2271 if (err) 2272 return (err); 2273 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2274 usb_syncmem(&dataend->dma, 2275 dataend->offs + offsetof(uhci_td_t, td_status), 2276 sizeof(dataend->td.td_status), 2277 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2278 2279 #ifdef UHCI_DEBUG 2280 if (uhcidebug > 10) { 2281 DPRINTF(("uhci_device_intr_transfer: data(1)\n")); 2282 uhci_dump_tds(data); 2283 uhci_dump_qh(upipe->u.intr.qhs[0]); 2284 } 2285 #endif 2286 2287 s = splusb(); 2288 /* Set up interrupt info. */ 2289 ii->xfer = xfer; 2290 ii->stdstart = data; 2291 ii->stdend = dataend; 2292 #ifdef DIAGNOSTIC 2293 if (!ii->isdone) { 2294 printf("uhci_device_intr_transfer: not done, ii=%p\n", ii); 2295 } 2296 ii->isdone = 0; 2297 #endif 2298 2299 DPRINTFN(10,("uhci_device_intr_transfer: qhs[0]=%p\n", 2300 upipe->u.intr.qhs[0])); 2301 for (i = 0; i < upipe->u.intr.npoll; i++) { 2302 sqh = upipe->u.intr.qhs[i]; 2303 sqh->elink = data; 2304 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2305 usb_syncmem(&sqh->dma, 2306 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2307 sizeof(sqh->qh.qh_elink), 2308 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2309 } 2310 uhci_add_intr_info(sc, ii); 2311 xfer->status = USBD_IN_PROGRESS; 2312 splx(s); 2313 2314 #ifdef UHCI_DEBUG 2315 if (uhcidebug > 10) { 2316 DPRINTF(("uhci_device_intr_transfer: data(2)\n")); 2317 uhci_dump_tds(data); 2318 uhci_dump_qh(upipe->u.intr.qhs[0]); 2319 } 2320 #endif 2321 2322 return (USBD_IN_PROGRESS); 2323 } 2324 2325 /* Abort a device control request. */ 2326 void 2327 uhci_device_ctrl_abort(usbd_xfer_handle xfer) 2328 { 2329 DPRINTF(("uhci_device_ctrl_abort:\n")); 2330 uhci_abort_xfer(xfer, USBD_CANCELLED); 2331 } 2332 2333 /* Close a device control pipe. */ 2334 void 2335 uhci_device_ctrl_close(usbd_pipe_handle pipe) 2336 { 2337 } 2338 2339 /* Abort a device interrupt request. */ 2340 void 2341 uhci_device_intr_abort(usbd_xfer_handle xfer) 2342 { 2343 DPRINTFN(1,("uhci_device_intr_abort: xfer=%p\n", xfer)); 2344 if (xfer->pipe->intrxfer == xfer) { 2345 DPRINTFN(1,("uhci_device_intr_abort: remove\n")); 2346 xfer->pipe->intrxfer = NULL; 2347 } 2348 uhci_abort_xfer(xfer, USBD_CANCELLED); 2349 } 2350 2351 /* Close a device interrupt pipe. */ 2352 void 2353 uhci_device_intr_close(usbd_pipe_handle pipe) 2354 { 2355 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2356 uhci_softc_t *sc = pipe->device->bus->hci_private; 2357 int i, npoll; 2358 int s; 2359 2360 /* Unlink descriptors from controller data structures. */ 2361 npoll = upipe->u.intr.npoll; 2362 s = splusb(); 2363 for (i = 0; i < npoll; i++) 2364 uhci_remove_intr(sc, upipe->u.intr.qhs[i]); 2365 splx(s); 2366 2367 /* 2368 * We now have to wait for any activity on the physical 2369 * descriptors to stop. 2370 */ 2371 usb_delay_ms(&sc->sc_bus, 2); 2372 2373 for(i = 0; i < npoll; i++) 2374 uhci_free_sqh(sc, upipe->u.intr.qhs[i]); 2375 free(upipe->u.intr.qhs, M_USBHC); 2376 2377 /* XXX free other resources */ 2378 } 2379 2380 usbd_status 2381 uhci_device_request(usbd_xfer_handle xfer) 2382 { 2383 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2384 usb_device_request_t *req = &xfer->request; 2385 usbd_device_handle dev = upipe->pipe.device; 2386 uhci_softc_t *sc = dev->bus->hci_private; 2387 int addr = dev->address; 2388 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2389 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2390 uhci_soft_td_t *setup, *data, *stat, *next, *dataend; 2391 uhci_soft_qh_t *sqh; 2392 int len; 2393 u_int32_t ls; 2394 usbd_status err; 2395 int isread; 2396 int s; 2397 2398 DPRINTFN(3,("uhci_device_control type=0x%02x, request=0x%02x, " 2399 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 2400 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2401 UGETW(req->wIndex), UGETW(req->wLength), 2402 addr, endpt)); 2403 2404 ls = dev->speed == USB_SPEED_LOW ? UHCI_TD_LS : 0; 2405 isread = req->bmRequestType & UT_READ; 2406 len = UGETW(req->wLength); 2407 2408 setup = upipe->u.ctl.setup; 2409 stat = upipe->u.ctl.stat; 2410 sqh = upipe->u.ctl.sqh; 2411 2412 /* Set up data transaction */ 2413 if (len != 0) { 2414 upipe->nexttoggle = 1; 2415 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->flags, 2416 &xfer->dmabuf, &data, &dataend); 2417 if (err) 2418 return (err); 2419 next = data; 2420 dataend->link.std = stat; 2421 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_VF | UHCI_PTR_TD); 2422 usb_syncmem(&dataend->dma, 2423 dataend->offs + offsetof(uhci_td_t, td_link), 2424 sizeof(dataend->td.td_link), 2425 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2426 } else { 2427 next = stat; 2428 } 2429 upipe->u.ctl.length = len; 2430 2431 memcpy(KERNADDR(&upipe->u.ctl.reqdma, 0), req, sizeof *req); 2432 usb_syncmem(&upipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 2433 2434 setup->link.std = next; 2435 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_VF | UHCI_PTR_TD); 2436 setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2437 UHCI_TD_ACTIVE); 2438 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof *req, endpt, addr)); 2439 setup->td.td_buffer = htole32(DMAADDR(&upipe->u.ctl.reqdma, 0)); 2440 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2441 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2442 2443 stat->link.std = NULL; 2444 stat->td.td_link = htole32(UHCI_PTR_T); 2445 stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2446 UHCI_TD_ACTIVE | UHCI_TD_IOC); 2447 stat->td.td_token = 2448 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2449 UHCI_TD_IN (0, endpt, addr, 1)); 2450 stat->td.td_buffer = htole32(0); 2451 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2452 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2453 2454 #ifdef UHCI_DEBUG 2455 if (uhcidebug > 10) { 2456 DPRINTF(("uhci_device_request: before transfer\n")); 2457 uhci_dump_tds(setup); 2458 } 2459 #endif 2460 2461 /* Set up interrupt info. */ 2462 ii->xfer = xfer; 2463 ii->stdstart = setup; 2464 ii->stdend = stat; 2465 #ifdef DIAGNOSTIC 2466 if (!ii->isdone) { 2467 printf("uhci_device_request: not done, ii=%p\n", ii); 2468 } 2469 ii->isdone = 0; 2470 #endif 2471 2472 sqh->elink = setup; 2473 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2474 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2475 2476 s = splusb(); 2477 if (dev->speed == USB_SPEED_LOW) 2478 uhci_add_ls_ctrl(sc, sqh); 2479 else 2480 uhci_add_hs_ctrl(sc, sqh); 2481 uhci_add_intr_info(sc, ii); 2482 #ifdef UHCI_DEBUG 2483 if (uhcidebug > 12) { 2484 uhci_soft_td_t *std; 2485 uhci_soft_qh_t *xqh; 2486 uhci_soft_qh_t *sxqh; 2487 int maxqh = 0; 2488 uhci_physaddr_t link; 2489 DPRINTF(("uhci_enter_ctl_q: follow from [0]\n")); 2490 for (std = sc->sc_vframes[0].htd, link = 0; 2491 (link & UHCI_PTR_QH) == 0; 2492 std = std->link.std) { 2493 link = le32toh(std->td.td_link); 2494 uhci_dump_td(std); 2495 } 2496 sxqh = (uhci_soft_qh_t *)std; 2497 uhci_dump_qh(sxqh); 2498 for (xqh = sxqh; 2499 xqh != NULL; 2500 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2501 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2502 uhci_dump_qh(xqh); 2503 } 2504 DPRINTF(("Enqueued QH:\n")); 2505 uhci_dump_qh(sqh); 2506 uhci_dump_tds(sqh->elink); 2507 } 2508 #endif 2509 if (xfer->timeout && !sc->sc_bus.use_polling) { 2510 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 2511 uhci_timeout, ii); 2512 } 2513 xfer->status = USBD_IN_PROGRESS; 2514 splx(s); 2515 2516 return (USBD_NORMAL_COMPLETION); 2517 } 2518 2519 usbd_status 2520 uhci_device_isoc_transfer(usbd_xfer_handle xfer) 2521 { 2522 usbd_status err; 2523 2524 DPRINTFN(5,("uhci_device_isoc_transfer: xfer=%p\n", xfer)); 2525 2526 /* Put it on our queue, */ 2527 err = usb_insert_transfer(xfer); 2528 2529 /* bail out on error, */ 2530 if (err && err != USBD_IN_PROGRESS) 2531 return (err); 2532 2533 /* XXX should check inuse here */ 2534 2535 /* insert into schedule, */ 2536 uhci_device_isoc_enter(xfer); 2537 2538 /* and start if the pipe wasn't running */ 2539 if (!err) 2540 uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 2541 2542 return (err); 2543 } 2544 2545 void 2546 uhci_device_isoc_enter(usbd_xfer_handle xfer) 2547 { 2548 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2549 usbd_device_handle dev = upipe->pipe.device; 2550 uhci_softc_t *sc = dev->bus->hci_private; 2551 struct iso *iso = &upipe->u.iso; 2552 uhci_soft_td_t *std; 2553 u_int32_t buf, len, status, offs; 2554 int s, i, next, nframes; 2555 int rd = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2556 2557 DPRINTFN(5,("uhci_device_isoc_enter: used=%d next=%d xfer=%p " 2558 "nframes=%d\n", 2559 iso->inuse, iso->next, xfer, xfer->nframes)); 2560 2561 if (sc->sc_dying) 2562 return; 2563 2564 if (xfer->status == USBD_IN_PROGRESS) { 2565 /* This request has already been entered into the frame list */ 2566 printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer); 2567 /* XXX */ 2568 } 2569 2570 #ifdef DIAGNOSTIC 2571 if (iso->inuse >= UHCI_VFRAMELIST_COUNT) 2572 printf("uhci_device_isoc_enter: overflow!\n"); 2573 #endif 2574 2575 next = iso->next; 2576 if (next == -1) { 2577 /* Not in use yet, schedule it a few frames ahead. */ 2578 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 2579 DPRINTFN(2,("uhci_device_isoc_enter: start next=%d\n", next)); 2580 } 2581 2582 xfer->status = USBD_IN_PROGRESS; 2583 UXFER(xfer)->curframe = next; 2584 2585 buf = DMAADDR(&xfer->dmabuf, 0); 2586 offs = 0; 2587 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 2588 UHCI_TD_ACTIVE | 2589 UHCI_TD_IOS); 2590 nframes = xfer->nframes; 2591 s = splusb(); 2592 for (i = 0; i < nframes; i++) { 2593 std = iso->stds[next]; 2594 if (++next >= UHCI_VFRAMELIST_COUNT) 2595 next = 0; 2596 len = xfer->frlengths[i]; 2597 std->td.td_buffer = htole32(buf); 2598 usb_syncmem(&xfer->dmabuf, offs, len, 2599 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2600 if (i == nframes - 1) 2601 status |= UHCI_TD_IOC; 2602 std->td.td_status = htole32(status); 2603 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2604 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 2605 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2606 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2607 #ifdef UHCI_DEBUG 2608 if (uhcidebug > 5) { 2609 DPRINTFN(5,("uhci_device_isoc_enter: TD %d\n", i)); 2610 uhci_dump_td(std); 2611 } 2612 #endif 2613 buf += len; 2614 offs += len; 2615 } 2616 iso->next = next; 2617 iso->inuse += xfer->nframes; 2618 2619 splx(s); 2620 } 2621 2622 usbd_status 2623 uhci_device_isoc_start(usbd_xfer_handle xfer) 2624 { 2625 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2626 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 2627 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2628 uhci_soft_td_t *end; 2629 int s, i; 2630 2631 DPRINTFN(5,("uhci_device_isoc_start: xfer=%p\n", xfer)); 2632 2633 if (sc->sc_dying) 2634 return (USBD_IOERROR); 2635 2636 #ifdef DIAGNOSTIC 2637 if (xfer->status != USBD_IN_PROGRESS) 2638 printf("uhci_device_isoc_start: not in progress %p\n", xfer); 2639 #endif 2640 2641 /* Find the last TD */ 2642 i = UXFER(xfer)->curframe + xfer->nframes; 2643 if (i >= UHCI_VFRAMELIST_COUNT) 2644 i -= UHCI_VFRAMELIST_COUNT; 2645 end = upipe->u.iso.stds[i]; 2646 2647 #ifdef DIAGNOSTIC 2648 if (end == NULL) { 2649 printf("uhci_device_isoc_start: end == NULL\n"); 2650 return (USBD_INVAL); 2651 } 2652 #endif 2653 2654 s = splusb(); 2655 2656 /* Set up interrupt info. */ 2657 ii->xfer = xfer; 2658 ii->stdstart = end; 2659 ii->stdend = end; 2660 #ifdef DIAGNOSTIC 2661 if (!ii->isdone) 2662 printf("uhci_device_isoc_start: not done, ii=%p\n", ii); 2663 ii->isdone = 0; 2664 #endif 2665 uhci_add_intr_info(sc, ii); 2666 2667 splx(s); 2668 2669 return (USBD_IN_PROGRESS); 2670 } 2671 2672 void 2673 uhci_device_isoc_abort(usbd_xfer_handle xfer) 2674 { 2675 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2676 uhci_soft_td_t **stds = upipe->u.iso.stds; 2677 uhci_soft_td_t *std; 2678 int i, n, s, nframes, maxlen, len; 2679 2680 s = splusb(); 2681 2682 /* Transfer is already done. */ 2683 if (xfer->status != USBD_NOT_STARTED && 2684 xfer->status != USBD_IN_PROGRESS) { 2685 splx(s); 2686 return; 2687 } 2688 2689 /* Give xfer the requested abort code. */ 2690 xfer->status = USBD_CANCELLED; 2691 2692 /* make hardware ignore it, */ 2693 nframes = xfer->nframes; 2694 n = UXFER(xfer)->curframe; 2695 maxlen = 0; 2696 for (i = 0; i < nframes; i++) { 2697 std = stds[n]; 2698 usb_syncmem(&std->dma, 2699 std->offs + offsetof(uhci_td_t, td_status), 2700 sizeof(std->td.td_status), 2701 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2702 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2703 usb_syncmem(&std->dma, 2704 std->offs + offsetof(uhci_td_t, td_status), 2705 sizeof(std->td.td_status), 2706 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2707 usb_syncmem(&std->dma, 2708 std->offs + offsetof(uhci_td_t, td_token), 2709 sizeof(std->td.td_token), 2710 BUS_DMASYNC_POSTWRITE); 2711 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 2712 if (len > maxlen) 2713 maxlen = len; 2714 if (++n >= UHCI_VFRAMELIST_COUNT) 2715 n = 0; 2716 } 2717 2718 /* and wait until we are sure the hardware has finished. */ 2719 delay(maxlen); 2720 2721 #ifdef DIAGNOSTIC 2722 UXFER(xfer)->iinfo.isdone = 1; 2723 #endif 2724 /* Run callback and remove from interrupt list. */ 2725 usb_transfer_complete(xfer); 2726 2727 splx(s); 2728 } 2729 2730 void 2731 uhci_device_isoc_close(usbd_pipe_handle pipe) 2732 { 2733 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2734 usbd_device_handle dev = upipe->pipe.device; 2735 uhci_softc_t *sc = dev->bus->hci_private; 2736 uhci_soft_td_t *std, *vstd; 2737 struct iso *iso; 2738 int i, s; 2739 2740 /* 2741 * Make sure all TDs are marked as inactive. 2742 * Wait for completion. 2743 * Unschedule. 2744 * Deallocate. 2745 */ 2746 iso = &upipe->u.iso; 2747 2748 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2749 std = iso->stds[i]; 2750 usb_syncmem(&std->dma, 2751 std->offs + offsetof(uhci_td_t, td_status), 2752 sizeof(std->td.td_status), 2753 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2754 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 2755 usb_syncmem(&std->dma, 2756 std->offs + offsetof(uhci_td_t, td_status), 2757 sizeof(std->td.td_status), 2758 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2759 } 2760 usb_delay_ms(&sc->sc_bus, 2); /* wait for completion */ 2761 2762 s = splusb(); 2763 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2764 std = iso->stds[i]; 2765 for (vstd = sc->sc_vframes[i].htd; 2766 vstd != NULL && vstd->link.std != std; 2767 vstd = vstd->link.std) 2768 ; 2769 if (vstd == NULL) { 2770 /*panic*/ 2771 printf("uhci_device_isoc_close: %p not found\n", std); 2772 splx(s); 2773 return; 2774 } 2775 vstd->link = std->link; 2776 usb_syncmem(&std->dma, 2777 std->offs + offsetof(uhci_td_t, td_link), 2778 sizeof(std->td.td_link), 2779 BUS_DMASYNC_POSTWRITE); 2780 vstd->td.td_link = std->td.td_link; 2781 usb_syncmem(&vstd->dma, 2782 vstd->offs + offsetof(uhci_td_t, td_link), 2783 sizeof(vstd->td.td_link), 2784 BUS_DMASYNC_PREWRITE); 2785 uhci_free_std(sc, std); 2786 } 2787 splx(s); 2788 2789 free(iso->stds, M_USBHC); 2790 } 2791 2792 usbd_status 2793 uhci_setup_isoc(usbd_pipe_handle pipe) 2794 { 2795 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2796 usbd_device_handle dev = upipe->pipe.device; 2797 uhci_softc_t *sc = dev->bus->hci_private; 2798 int addr = upipe->pipe.device->address; 2799 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2800 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 2801 uhci_soft_td_t *std, *vstd; 2802 u_int32_t token; 2803 struct iso *iso; 2804 int i, s; 2805 2806 iso = &upipe->u.iso; 2807 iso->stds = malloc(UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *), 2808 M_USBHC, M_WAITOK); 2809 2810 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 2811 UHCI_TD_OUT(0, endpt, addr, 0); 2812 2813 /* Allocate the TDs and mark as inactive; */ 2814 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2815 std = uhci_alloc_std(sc); 2816 if (std == 0) 2817 goto bad; 2818 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 2819 std->td.td_token = htole32(token); 2820 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2821 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2822 iso->stds[i] = std; 2823 } 2824 2825 /* Insert TDs into schedule. */ 2826 s = splusb(); 2827 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2828 std = iso->stds[i]; 2829 vstd = sc->sc_vframes[i].htd; 2830 usb_syncmem(&vstd->dma, 2831 vstd->offs + offsetof(uhci_td_t, td_link), 2832 sizeof(vstd->td.td_link), 2833 BUS_DMASYNC_POSTWRITE); 2834 std->link = vstd->link; 2835 std->td.td_link = vstd->td.td_link; 2836 usb_syncmem(&std->dma, 2837 std->offs + offsetof(uhci_td_t, td_link), 2838 sizeof(std->td.td_link), 2839 BUS_DMASYNC_PREWRITE); 2840 vstd->link.std = std; 2841 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 2842 usb_syncmem(&vstd->dma, 2843 vstd->offs + offsetof(uhci_td_t, td_link), 2844 sizeof(vstd->td.td_link), 2845 BUS_DMASYNC_PREWRITE); 2846 } 2847 splx(s); 2848 2849 iso->next = -1; 2850 iso->inuse = 0; 2851 2852 return (USBD_NORMAL_COMPLETION); 2853 2854 bad: 2855 while (--i >= 0) 2856 uhci_free_std(sc, iso->stds[i]); 2857 free(iso->stds, M_USBHC); 2858 return (USBD_NOMEM); 2859 } 2860 2861 void 2862 uhci_device_isoc_done(usbd_xfer_handle xfer) 2863 { 2864 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2865 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2866 int i, offs; 2867 int rd = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2868 2869 2870 DPRINTFN(4, ("uhci_isoc_done: length=%d, busy_free=0x%08x\n", 2871 xfer->actlen, xfer->busy_free)); 2872 2873 if (ii->xfer != xfer) 2874 /* Not on interrupt list, ignore it. */ 2875 return; 2876 2877 if (!uhci_active_intr_info(ii)) 2878 return; 2879 2880 #ifdef DIAGNOSTIC 2881 if (ii->stdend == NULL) { 2882 printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer); 2883 #ifdef UHCI_DEBUG 2884 uhci_dump_ii(ii); 2885 #endif 2886 return; 2887 } 2888 #endif 2889 2890 /* Turn off the interrupt since it is active even if the TD is not. */ 2891 usb_syncmem(&ii->stdend->dma, 2892 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2893 sizeof(ii->stdend->td.td_status), 2894 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2895 ii->stdend->td.td_status &= htole32(~UHCI_TD_IOC); 2896 usb_syncmem(&ii->stdend->dma, 2897 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2898 sizeof(ii->stdend->td.td_status), 2899 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2900 2901 uhci_del_intr_info(ii); /* remove from active list */ 2902 2903 offs = 0; 2904 for (i = 0; i < xfer->nframes; i++) { 2905 usb_syncmem(&xfer->dmabuf, offs, xfer->frlengths[i], 2906 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2907 offs += xfer->frlengths[i]; 2908 } 2909 } 2910 2911 void 2912 uhci_device_intr_done(usbd_xfer_handle xfer) 2913 { 2914 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2915 uhci_softc_t *sc = ii->sc; 2916 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2917 uhci_soft_qh_t *sqh; 2918 int i, npoll, isread; 2919 2920 DPRINTFN(5, ("uhci_device_intr_done: length=%d\n", xfer->actlen)); 2921 2922 npoll = upipe->u.intr.npoll; 2923 for(i = 0; i < npoll; i++) { 2924 sqh = upipe->u.intr.qhs[i]; 2925 sqh->elink = NULL; 2926 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 2927 usb_syncmem(&sqh->dma, 2928 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2929 sizeof(sqh->qh.qh_elink), 2930 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2931 } 2932 uhci_free_std_chain(sc, ii->stdstart, NULL); 2933 2934 isread = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2935 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 2936 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2937 2938 /* XXX Wasteful. */ 2939 if (xfer->pipe->repeat) { 2940 uhci_soft_td_t *data, *dataend; 2941 2942 DPRINTFN(5,("uhci_device_intr_done: requeing\n")); 2943 2944 /* This alloc cannot fail since we freed the chain above. */ 2945 uhci_alloc_std_chain(upipe, sc, xfer->length, 2946 upipe->u.intr.isread, xfer->flags, 2947 &xfer->dmabuf, &data, &dataend); 2948 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2949 usb_syncmem(&dataend->dma, 2950 dataend->offs + offsetof(uhci_td_t, td_status), 2951 sizeof(dataend->td.td_status), 2952 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2953 2954 #ifdef UHCI_DEBUG 2955 if (uhcidebug > 10) { 2956 DPRINTF(("uhci_device_intr_done: data(1)\n")); 2957 uhci_dump_tds(data); 2958 uhci_dump_qh(upipe->u.intr.qhs[0]); 2959 } 2960 #endif 2961 2962 ii->stdstart = data; 2963 ii->stdend = dataend; 2964 #ifdef DIAGNOSTIC 2965 if (!ii->isdone) { 2966 printf("uhci_device_intr_done: not done, ii=%p\n", ii); 2967 } 2968 ii->isdone = 0; 2969 #endif 2970 for (i = 0; i < npoll; i++) { 2971 sqh = upipe->u.intr.qhs[i]; 2972 sqh->elink = data; 2973 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2974 usb_syncmem(&sqh->dma, 2975 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2976 sizeof(sqh->qh.qh_elink), 2977 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2978 } 2979 xfer->status = USBD_IN_PROGRESS; 2980 /* The ii is already on the examined list, just leave it. */ 2981 } else { 2982 DPRINTFN(5,("uhci_device_intr_done: removing\n")); 2983 if (uhci_active_intr_info(ii)) 2984 uhci_del_intr_info(ii); 2985 } 2986 } 2987 2988 /* Deallocate request data structures */ 2989 void 2990 uhci_device_ctrl_done(usbd_xfer_handle xfer) 2991 { 2992 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2993 uhci_softc_t *sc = ii->sc; 2994 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2995 int len = UGETW(xfer->request.wLength); 2996 int isread = (xfer->request.bmRequestType & UT_READ); 2997 2998 #ifdef DIAGNOSTIC 2999 if (!(xfer->rqflags & URQ_REQUEST)) 3000 panic("uhci_device_ctrl_done: not a request"); 3001 #endif 3002 3003 if (!uhci_active_intr_info(ii)) 3004 return; 3005 3006 uhci_del_intr_info(ii); /* remove from active list */ 3007 3008 if (upipe->pipe.device->speed == USB_SPEED_LOW) 3009 uhci_remove_ls_ctrl(sc, upipe->u.ctl.sqh); 3010 else 3011 uhci_remove_hs_ctrl(sc, upipe->u.ctl.sqh); 3012 3013 if (upipe->u.ctl.length != 0) 3014 uhci_free_std_chain(sc, ii->stdstart->link.std, ii->stdend); 3015 3016 if (len) { 3017 usb_syncmem(&xfer->dmabuf, 0, len, 3018 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3019 } 3020 usb_syncmem(&upipe->u.ctl.reqdma, 0, 3021 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3022 3023 DPRINTFN(5, ("uhci_device_ctrl_done: length=%d\n", xfer->actlen)); 3024 } 3025 3026 /* Deallocate request data structures */ 3027 void 3028 uhci_device_bulk_done(usbd_xfer_handle xfer) 3029 { 3030 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3031 uhci_softc_t *sc = ii->sc; 3032 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 3033 3034 DPRINTFN(5,("uhci_device_bulk_done: xfer=%p ii=%p sc=%p upipe=%p\n", 3035 xfer, ii, sc, upipe)); 3036 3037 if (!uhci_active_intr_info(ii)) 3038 return; 3039 3040 uhci_del_intr_info(ii); /* remove from active list */ 3041 3042 uhci_remove_bulk(sc, upipe->u.bulk.sqh); 3043 3044 uhci_free_std_chain(sc, ii->stdstart, NULL); 3045 3046 DPRINTFN(5, ("uhci_device_bulk_done: length=%d\n", xfer->actlen)); 3047 } 3048 3049 /* Add interrupt QH, called with vflock. */ 3050 void 3051 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3052 { 3053 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3054 uhci_soft_qh_t *eqh; 3055 3056 DPRINTFN(4, ("uhci_add_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3057 3058 eqh = vf->eqh; 3059 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3060 sizeof(eqh->qh.qh_hlink), 3061 BUS_DMASYNC_POSTWRITE); 3062 sqh->hlink = eqh->hlink; 3063 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3064 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3065 sizeof(sqh->qh.qh_hlink), 3066 BUS_DMASYNC_PREWRITE); 3067 eqh->hlink = sqh; 3068 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3069 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3070 sizeof(eqh->qh.qh_hlink), 3071 BUS_DMASYNC_PREWRITE); 3072 vf->eqh = sqh; 3073 vf->bandwidth++; 3074 } 3075 3076 /* Remove interrupt QH. */ 3077 void 3078 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3079 { 3080 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3081 uhci_soft_qh_t *pqh; 3082 3083 DPRINTFN(4, ("uhci_remove_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3084 3085 /* See comment in uhci_remove_ctrl() */ 3086 3087 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3088 sizeof(sqh->qh.qh_elink), 3089 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3090 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3091 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3092 usb_syncmem(&sqh->dma, 3093 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3094 sizeof(sqh->qh.qh_elink), 3095 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3096 delay(UHCI_QH_REMOVE_DELAY); 3097 } 3098 3099 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3100 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3101 sizeof(sqh->qh.qh_hlink), 3102 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3103 pqh->hlink = sqh->hlink; 3104 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3105 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3106 sizeof(pqh->qh.qh_hlink), 3107 BUS_DMASYNC_PREWRITE); 3108 delay(UHCI_QH_REMOVE_DELAY); 3109 if (vf->eqh == sqh) 3110 vf->eqh = pqh; 3111 vf->bandwidth--; 3112 } 3113 3114 usbd_status 3115 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3116 { 3117 uhci_soft_qh_t *sqh; 3118 int i, npoll, s; 3119 u_int bestbw, bw, bestoffs, offs; 3120 3121 DPRINTFN(2, ("uhci_device_setintr: pipe=%p\n", upipe)); 3122 if (ival == 0) { 3123 printf("uhci_device_setintr: 0 interval\n"); 3124 return (USBD_INVAL); 3125 } 3126 3127 if (ival > UHCI_VFRAMELIST_COUNT) 3128 ival = UHCI_VFRAMELIST_COUNT; 3129 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3130 DPRINTFN(2, ("uhci_device_setintr: ival=%d npoll=%d\n", ival, npoll)); 3131 3132 upipe->u.intr.npoll = npoll; 3133 upipe->u.intr.qhs = 3134 malloc(npoll * sizeof(uhci_soft_qh_t *), M_USBHC, M_WAITOK); 3135 3136 /* 3137 * Figure out which offset in the schedule that has most 3138 * bandwidth left over. 3139 */ 3140 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3141 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3142 for (bw = i = 0; i < npoll; i++) 3143 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3144 if (bw < bestbw) { 3145 bestbw = bw; 3146 bestoffs = offs; 3147 } 3148 } 3149 DPRINTFN(1, ("uhci_device_setintr: bw=%d offs=%d\n", bestbw, bestoffs)); 3150 3151 for(i = 0; i < npoll; i++) { 3152 upipe->u.intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3153 sqh->elink = NULL; 3154 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3155 usb_syncmem(&sqh->dma, 3156 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3157 sizeof(sqh->qh.qh_elink), 3158 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3159 sqh->pos = MOD(i * ival + bestoffs); 3160 } 3161 #undef MOD 3162 3163 s = splusb(); 3164 /* Enter QHs into the controller data structures. */ 3165 for(i = 0; i < npoll; i++) 3166 uhci_add_intr(sc, upipe->u.intr.qhs[i]); 3167 splx(s); 3168 3169 DPRINTFN(5, ("uhci_device_setintr: returns %p\n", upipe)); 3170 return (USBD_NORMAL_COMPLETION); 3171 } 3172 3173 /* Open a new pipe. */ 3174 usbd_status 3175 uhci_open(usbd_pipe_handle pipe) 3176 { 3177 uhci_softc_t *sc = pipe->device->bus->hci_private; 3178 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 3179 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 3180 usbd_status err; 3181 int ival; 3182 3183 DPRINTFN(1, ("uhci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 3184 pipe, pipe->device->address, 3185 ed->bEndpointAddress, sc->sc_addr)); 3186 3187 upipe->aborting = 0; 3188 /* toggle state needed for bulk endpoints */ 3189 upipe->nexttoggle = pipe->endpoint->datatoggle; 3190 3191 if (pipe->device->address == sc->sc_addr) { 3192 switch (ed->bEndpointAddress) { 3193 case USB_CONTROL_ENDPOINT: 3194 pipe->methods = &uhci_root_ctrl_methods; 3195 break; 3196 case UE_DIR_IN | UHCI_INTR_ENDPT: 3197 pipe->methods = &uhci_root_intr_methods; 3198 break; 3199 default: 3200 return (USBD_INVAL); 3201 } 3202 } else { 3203 switch (ed->bmAttributes & UE_XFERTYPE) { 3204 case UE_CONTROL: 3205 pipe->methods = &uhci_device_ctrl_methods; 3206 upipe->u.ctl.sqh = uhci_alloc_sqh(sc); 3207 if (upipe->u.ctl.sqh == NULL) 3208 goto bad; 3209 upipe->u.ctl.setup = uhci_alloc_std(sc); 3210 if (upipe->u.ctl.setup == NULL) { 3211 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3212 goto bad; 3213 } 3214 upipe->u.ctl.stat = uhci_alloc_std(sc); 3215 if (upipe->u.ctl.stat == NULL) { 3216 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3217 uhci_free_std(sc, upipe->u.ctl.setup); 3218 goto bad; 3219 } 3220 err = usb_allocmem(&sc->sc_bus, 3221 sizeof(usb_device_request_t), 3222 0, &upipe->u.ctl.reqdma); 3223 if (err) { 3224 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3225 uhci_free_std(sc, upipe->u.ctl.setup); 3226 uhci_free_std(sc, upipe->u.ctl.stat); 3227 goto bad; 3228 } 3229 break; 3230 case UE_INTERRUPT: 3231 pipe->methods = &uhci_device_intr_methods; 3232 ival = pipe->interval; 3233 if (ival == USBD_DEFAULT_INTERVAL) 3234 ival = ed->bInterval; 3235 return (uhci_device_setintr(sc, upipe, ival)); 3236 case UE_ISOCHRONOUS: 3237 pipe->methods = &uhci_device_isoc_methods; 3238 return (uhci_setup_isoc(pipe)); 3239 case UE_BULK: 3240 pipe->methods = &uhci_device_bulk_methods; 3241 upipe->u.bulk.sqh = uhci_alloc_sqh(sc); 3242 if (upipe->u.bulk.sqh == NULL) 3243 goto bad; 3244 break; 3245 } 3246 } 3247 return (USBD_NORMAL_COMPLETION); 3248 3249 bad: 3250 return (USBD_NOMEM); 3251 } 3252 3253 /* 3254 * Data structures and routines to emulate the root hub. 3255 */ 3256 usb_device_descriptor_t uhci_devd = { 3257 USB_DEVICE_DESCRIPTOR_SIZE, 3258 UDESC_DEVICE, /* type */ 3259 {0x00, 0x01}, /* USB version */ 3260 UDCLASS_HUB, /* class */ 3261 UDSUBCLASS_HUB, /* subclass */ 3262 UDPROTO_FSHUB, /* protocol */ 3263 64, /* max packet */ 3264 {0},{0},{0x00,0x01}, /* device id */ 3265 1,2,0, /* string indicies */ 3266 1 /* # of configurations */ 3267 }; 3268 3269 const usb_config_descriptor_t uhci_confd = { 3270 USB_CONFIG_DESCRIPTOR_SIZE, 3271 UDESC_CONFIG, 3272 {USB_CONFIG_DESCRIPTOR_SIZE + 3273 USB_INTERFACE_DESCRIPTOR_SIZE + 3274 USB_ENDPOINT_DESCRIPTOR_SIZE}, 3275 1, 3276 1, 3277 0, 3278 UC_ATTR_MBO | UC_SELF_POWERED, 3279 0 /* max power */ 3280 }; 3281 3282 const usb_interface_descriptor_t uhci_ifcd = { 3283 USB_INTERFACE_DESCRIPTOR_SIZE, 3284 UDESC_INTERFACE, 3285 0, 3286 0, 3287 1, 3288 UICLASS_HUB, 3289 UISUBCLASS_HUB, 3290 UIPROTO_FSHUB, 3291 0 3292 }; 3293 3294 const usb_endpoint_descriptor_t uhci_endpd = { 3295 USB_ENDPOINT_DESCRIPTOR_SIZE, 3296 UDESC_ENDPOINT, 3297 UE_DIR_IN | UHCI_INTR_ENDPT, 3298 UE_INTERRUPT, 3299 {8}, 3300 255 3301 }; 3302 3303 const usb_hub_descriptor_t uhci_hubd_piix = { 3304 USB_HUB_DESCRIPTOR_SIZE, 3305 UDESC_HUB, 3306 2, 3307 { UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0 }, 3308 50, /* power on to power good */ 3309 0, 3310 { 0x00 }, /* both ports are removable */ 3311 { 0 }, 3312 }; 3313 3314 /* 3315 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3316 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3317 * should not be used by the USB subsystem. As we cannot issue a 3318 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3319 * will be enabled as part of the reset. 3320 * 3321 * On the VT83C572, the port cannot be successfully enabled until the 3322 * outstanding "port enable change" and "connection status change" 3323 * events have been reset. 3324 */ 3325 Static usbd_status 3326 uhci_portreset(uhci_softc_t *sc, int index) 3327 { 3328 int lim, port, x; 3329 3330 if (index == 1) 3331 port = UHCI_PORTSC1; 3332 else if (index == 2) 3333 port = UHCI_PORTSC2; 3334 else 3335 return (USBD_IOERROR); 3336 3337 x = URWMASK(UREAD2(sc, port)); 3338 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3339 3340 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3341 3342 DPRINTFN(3,("uhci port %d reset, status0 = 0x%04x\n", 3343 index, UREAD2(sc, port))); 3344 3345 x = URWMASK(UREAD2(sc, port)); 3346 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3347 3348 delay(100); 3349 3350 DPRINTFN(3,("uhci port %d reset, status1 = 0x%04x\n", 3351 index, UREAD2(sc, port))); 3352 3353 x = URWMASK(UREAD2(sc, port)); 3354 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3355 3356 for (lim = 10; --lim > 0;) { 3357 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3358 3359 x = UREAD2(sc, port); 3360 3361 DPRINTFN(3,("uhci port %d iteration %u, status = 0x%04x\n", 3362 index, lim, x)); 3363 3364 if (!(x & UHCI_PORTSC_CCS)) { 3365 /* 3366 * No device is connected (or was disconnected 3367 * during reset). Consider the port reset. 3368 * The delay must be long enough to ensure on 3369 * the initial iteration that the device 3370 * connection will have been registered. 50ms 3371 * appears to be sufficient, but 20ms is not. 3372 */ 3373 DPRINTFN(3,("uhci port %d loop %u, device detached\n", 3374 index, lim)); 3375 break; 3376 } 3377 3378 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3379 /* 3380 * Port enabled changed and/or connection 3381 * status changed were set. Reset either or 3382 * both raised flags (by writing a 1 to that 3383 * bit), and wait again for state to settle. 3384 */ 3385 UWRITE2(sc, port, URWMASK(x) | 3386 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3387 continue; 3388 } 3389 3390 if (x & UHCI_PORTSC_PE) 3391 /* Port is enabled */ 3392 break; 3393 3394 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3395 } 3396 3397 DPRINTFN(3,("uhci port %d reset, status2 = 0x%04x\n", 3398 index, UREAD2(sc, port))); 3399 3400 if (lim <= 0) { 3401 DPRINTFN(1,("uhci port %d reset timed out\n", index)); 3402 return (USBD_TIMEOUT); 3403 } 3404 3405 sc->sc_isreset = 1; 3406 return (USBD_NORMAL_COMPLETION); 3407 } 3408 3409 /* 3410 * Simulate a hardware hub by handling all the necessary requests. 3411 */ 3412 usbd_status 3413 uhci_root_ctrl_transfer(usbd_xfer_handle xfer) 3414 { 3415 usbd_status err; 3416 3417 /* Insert last in queue. */ 3418 err = usb_insert_transfer(xfer); 3419 if (err) 3420 return (err); 3421 3422 /* 3423 * Pipe isn't running (otherwise err would be USBD_INPROG), 3424 * so start it first. 3425 */ 3426 return (uhci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3427 } 3428 3429 usbd_status 3430 uhci_root_ctrl_start(usbd_xfer_handle xfer) 3431 { 3432 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3433 usb_device_request_t *req; 3434 void *buf = NULL; 3435 int port, x; 3436 int s, len, value, index, status, change, l, totlen = 0; 3437 usb_port_status_t ps; 3438 usbd_status err; 3439 3440 if (sc->sc_dying) 3441 return (USBD_IOERROR); 3442 3443 #ifdef DIAGNOSTIC 3444 if (!(xfer->rqflags & URQ_REQUEST)) 3445 panic("uhci_root_ctrl_transfer: not a request"); 3446 #endif 3447 req = &xfer->request; 3448 3449 DPRINTFN(2,("uhci_root_ctrl_control type=0x%02x request=%02x\n", 3450 req->bmRequestType, req->bRequest)); 3451 3452 len = UGETW(req->wLength); 3453 value = UGETW(req->wValue); 3454 index = UGETW(req->wIndex); 3455 3456 if (len != 0) 3457 buf = KERNADDR(&xfer->dmabuf, 0); 3458 3459 #define C(x,y) ((x) | ((y) << 8)) 3460 switch(C(req->bRequest, req->bmRequestType)) { 3461 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3462 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3463 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3464 /* 3465 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3466 * for the integrated root hub. 3467 */ 3468 break; 3469 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3470 if (len > 0) { 3471 *(u_int8_t *)buf = sc->sc_conf; 3472 totlen = 1; 3473 } 3474 break; 3475 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3476 DPRINTFN(2,("uhci_root_ctrl_control wValue=0x%04x\n", value)); 3477 if (len == 0) 3478 break; 3479 switch(value >> 8) { 3480 case UDESC_DEVICE: 3481 if ((value & 0xff) != 0) { 3482 err = USBD_IOERROR; 3483 goto ret; 3484 } 3485 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 3486 USETW(uhci_devd.idVendor, sc->sc_id_vendor); 3487 memcpy(buf, &uhci_devd, l); 3488 break; 3489 case UDESC_CONFIG: 3490 if ((value & 0xff) != 0) { 3491 err = USBD_IOERROR; 3492 goto ret; 3493 } 3494 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 3495 memcpy(buf, &uhci_confd, l); 3496 buf = (char *)buf + l; 3497 len -= l; 3498 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 3499 totlen += l; 3500 memcpy(buf, &uhci_ifcd, l); 3501 buf = (char *)buf + l; 3502 len -= l; 3503 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 3504 totlen += l; 3505 memcpy(buf, &uhci_endpd, l); 3506 break; 3507 case UDESC_STRING: 3508 #define sd ((usb_string_descriptor_t *)buf) 3509 switch (value & 0xff) { 3510 case 0: /* Language table */ 3511 totlen = usb_makelangtbl(sd, len); 3512 break; 3513 case 1: /* Vendor */ 3514 totlen = usb_makestrdesc(sd, len, 3515 sc->sc_vendor); 3516 break; 3517 case 2: /* Product */ 3518 totlen = usb_makestrdesc(sd, len, 3519 "UHCI root hub"); 3520 break; 3521 } 3522 #undef sd 3523 break; 3524 default: 3525 err = USBD_IOERROR; 3526 goto ret; 3527 } 3528 break; 3529 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3530 if (len > 0) { 3531 *(u_int8_t *)buf = 0; 3532 totlen = 1; 3533 } 3534 break; 3535 case C(UR_GET_STATUS, UT_READ_DEVICE): 3536 if (len > 1) { 3537 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 3538 totlen = 2; 3539 } 3540 break; 3541 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3542 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3543 if (len > 1) { 3544 USETW(((usb_status_t *)buf)->wStatus, 0); 3545 totlen = 2; 3546 } 3547 break; 3548 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3549 if (value >= USB_MAX_DEVICES) { 3550 err = USBD_IOERROR; 3551 goto ret; 3552 } 3553 sc->sc_addr = value; 3554 break; 3555 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3556 if (value != 0 && value != 1) { 3557 err = USBD_IOERROR; 3558 goto ret; 3559 } 3560 sc->sc_conf = value; 3561 break; 3562 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3563 break; 3564 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3565 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3566 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3567 err = USBD_IOERROR; 3568 goto ret; 3569 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3570 break; 3571 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3572 break; 3573 /* Hub requests */ 3574 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3575 break; 3576 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3577 DPRINTFN(3, ("uhci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 3578 "port=%d feature=%d\n", 3579 index, value)); 3580 if (index == 1) 3581 port = UHCI_PORTSC1; 3582 else if (index == 2) 3583 port = UHCI_PORTSC2; 3584 else { 3585 err = USBD_IOERROR; 3586 goto ret; 3587 } 3588 switch(value) { 3589 case UHF_PORT_ENABLE: 3590 x = URWMASK(UREAD2(sc, port)); 3591 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3592 break; 3593 case UHF_PORT_SUSPEND: 3594 x = URWMASK(UREAD2(sc, port)); 3595 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3596 break; 3597 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3598 /* see USB2 spec ch. 7.1.7.7 */ 3599 usb_delay_ms(&sc->sc_bus, 20); 3600 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3601 /* 10ms resume delay must be provided by caller */ 3602 break; 3603 case UHF_PORT_RESET: 3604 x = URWMASK(UREAD2(sc, port)); 3605 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3606 break; 3607 case UHF_C_PORT_CONNECTION: 3608 x = URWMASK(UREAD2(sc, port)); 3609 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3610 break; 3611 case UHF_C_PORT_ENABLE: 3612 x = URWMASK(UREAD2(sc, port)); 3613 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3614 break; 3615 case UHF_C_PORT_OVER_CURRENT: 3616 x = URWMASK(UREAD2(sc, port)); 3617 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3618 break; 3619 case UHF_C_PORT_RESET: 3620 sc->sc_isreset = 0; 3621 err = USBD_NORMAL_COMPLETION; 3622 goto ret; 3623 case UHF_PORT_CONNECTION: 3624 case UHF_PORT_OVER_CURRENT: 3625 case UHF_PORT_POWER: 3626 case UHF_PORT_LOW_SPEED: 3627 case UHF_C_PORT_SUSPEND: 3628 default: 3629 err = USBD_IOERROR; 3630 goto ret; 3631 } 3632 break; 3633 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3634 if (index == 1) 3635 port = UHCI_PORTSC1; 3636 else if (index == 2) 3637 port = UHCI_PORTSC2; 3638 else { 3639 err = USBD_IOERROR; 3640 goto ret; 3641 } 3642 if (len > 0) { 3643 *(u_int8_t *)buf = 3644 (UREAD2(sc, port) & UHCI_PORTSC_LS) >> 3645 UHCI_PORTSC_LS_SHIFT; 3646 totlen = 1; 3647 } 3648 break; 3649 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3650 if (len == 0) 3651 break; 3652 if ((value & 0xff) != 0) { 3653 err = USBD_IOERROR; 3654 goto ret; 3655 } 3656 l = min(len, USB_HUB_DESCRIPTOR_SIZE); 3657 totlen = l; 3658 memcpy(buf, &uhci_hubd_piix, l); 3659 break; 3660 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3661 if (len != 4) { 3662 err = USBD_IOERROR; 3663 goto ret; 3664 } 3665 memset(buf, 0, len); 3666 totlen = len; 3667 break; 3668 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3669 if (index == 1) 3670 port = UHCI_PORTSC1; 3671 else if (index == 2) 3672 port = UHCI_PORTSC2; 3673 else { 3674 err = USBD_IOERROR; 3675 goto ret; 3676 } 3677 if (len != 4) { 3678 err = USBD_IOERROR; 3679 goto ret; 3680 } 3681 x = UREAD2(sc, port); 3682 status = change = 0; 3683 if (x & UHCI_PORTSC_CCS) 3684 status |= UPS_CURRENT_CONNECT_STATUS; 3685 if (x & UHCI_PORTSC_CSC) 3686 change |= UPS_C_CONNECT_STATUS; 3687 if (x & UHCI_PORTSC_PE) 3688 status |= UPS_PORT_ENABLED; 3689 if (x & UHCI_PORTSC_POEDC) 3690 change |= UPS_C_PORT_ENABLED; 3691 if (x & UHCI_PORTSC_OCI) 3692 status |= UPS_OVERCURRENT_INDICATOR; 3693 if (x & UHCI_PORTSC_OCIC) 3694 change |= UPS_C_OVERCURRENT_INDICATOR; 3695 if (x & UHCI_PORTSC_SUSP) 3696 status |= UPS_SUSPEND; 3697 if (x & UHCI_PORTSC_LSDA) 3698 status |= UPS_LOW_SPEED; 3699 status |= UPS_PORT_POWER; 3700 if (sc->sc_isreset) 3701 change |= UPS_C_PORT_RESET; 3702 USETW(ps.wPortStatus, status); 3703 USETW(ps.wPortChange, change); 3704 l = min(len, sizeof ps); 3705 memcpy(buf, &ps, l); 3706 totlen = l; 3707 break; 3708 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3709 err = USBD_IOERROR; 3710 goto ret; 3711 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3712 break; 3713 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3714 if (index == 1) 3715 port = UHCI_PORTSC1; 3716 else if (index == 2) 3717 port = UHCI_PORTSC2; 3718 else { 3719 err = USBD_IOERROR; 3720 goto ret; 3721 } 3722 switch(value) { 3723 case UHF_PORT_ENABLE: 3724 x = URWMASK(UREAD2(sc, port)); 3725 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3726 break; 3727 case UHF_PORT_SUSPEND: 3728 x = URWMASK(UREAD2(sc, port)); 3729 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 3730 break; 3731 case UHF_PORT_RESET: 3732 err = uhci_portreset(sc, index); 3733 goto ret; 3734 case UHF_PORT_POWER: 3735 /* Pretend we turned on power */ 3736 err = USBD_NORMAL_COMPLETION; 3737 goto ret; 3738 case UHF_C_PORT_CONNECTION: 3739 case UHF_C_PORT_ENABLE: 3740 case UHF_C_PORT_OVER_CURRENT: 3741 case UHF_PORT_CONNECTION: 3742 case UHF_PORT_OVER_CURRENT: 3743 case UHF_PORT_LOW_SPEED: 3744 case UHF_C_PORT_SUSPEND: 3745 case UHF_C_PORT_RESET: 3746 default: 3747 err = USBD_IOERROR; 3748 goto ret; 3749 } 3750 break; 3751 default: 3752 err = USBD_IOERROR; 3753 goto ret; 3754 } 3755 xfer->actlen = totlen; 3756 err = USBD_NORMAL_COMPLETION; 3757 ret: 3758 xfer->status = err; 3759 s = splusb(); 3760 usb_transfer_complete(xfer); 3761 splx(s); 3762 return (USBD_IN_PROGRESS); 3763 } 3764 3765 /* Abort a root control request. */ 3766 void 3767 uhci_root_ctrl_abort(usbd_xfer_handle xfer) 3768 { 3769 /* Nothing to do, all transfers are synchronous. */ 3770 } 3771 3772 /* Close the root pipe. */ 3773 void 3774 uhci_root_ctrl_close(usbd_pipe_handle pipe) 3775 { 3776 DPRINTF(("uhci_root_ctrl_close\n")); 3777 } 3778 3779 /* Abort a root interrupt request. */ 3780 void 3781 uhci_root_intr_abort(usbd_xfer_handle xfer) 3782 { 3783 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3784 3785 callout_stop(&sc->sc_poll_handle); 3786 sc->sc_intr_xfer = NULL; 3787 3788 if (xfer->pipe->intrxfer == xfer) { 3789 DPRINTF(("uhci_root_intr_abort: remove\n")); 3790 xfer->pipe->intrxfer = 0; 3791 } 3792 xfer->status = USBD_CANCELLED; 3793 #ifdef DIAGNOSTIC 3794 UXFER(xfer)->iinfo.isdone = 1; 3795 #endif 3796 usb_transfer_complete(xfer); 3797 } 3798 3799 usbd_status 3800 uhci_root_intr_transfer(usbd_xfer_handle xfer) 3801 { 3802 usbd_status err; 3803 3804 /* Insert last in queue. */ 3805 err = usb_insert_transfer(xfer); 3806 if (err) 3807 return (err); 3808 3809 /* 3810 * Pipe isn't running (otherwise err would be USBD_INPROG), 3811 * start first 3812 */ 3813 return (uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3814 } 3815 3816 /* Start a transfer on the root interrupt pipe */ 3817 usbd_status 3818 uhci_root_intr_start(usbd_xfer_handle xfer) 3819 { 3820 usbd_pipe_handle pipe = xfer->pipe; 3821 uhci_softc_t *sc = pipe->device->bus->hci_private; 3822 unsigned int ival; 3823 3824 DPRINTFN(3, ("uhci_root_intr_start: xfer=%p len=%d flags=%d\n", 3825 xfer, xfer->length, xfer->flags)); 3826 3827 if (sc->sc_dying) 3828 return (USBD_IOERROR); 3829 3830 /* XXX temporary variable needed to avoid gcc3 warning */ 3831 ival = xfer->pipe->endpoint->edesc->bInterval; 3832 sc->sc_ival = mstohz(ival); 3833 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 3834 sc->sc_intr_xfer = xfer; 3835 return (USBD_IN_PROGRESS); 3836 } 3837 3838 /* Close the root interrupt pipe. */ 3839 void 3840 uhci_root_intr_close(usbd_pipe_handle pipe) 3841 { 3842 uhci_softc_t *sc = pipe->device->bus->hci_private; 3843 3844 callout_stop(&sc->sc_poll_handle); 3845 sc->sc_intr_xfer = NULL; 3846 DPRINTF(("uhci_root_intr_close\n")); 3847 } 3848
Indexes created Tue Sep 30 20:09:53 GMT 2025