uhci.c revision 1.240.2.1 1 /* $NetBSD: uhci.c,v 1.240.2.1 2012/04/17 00:08:07 yamt Exp $ */
2 /* $FreeBSD: src/sys/dev/usb/uhci.c,v 1.33 1999/11/17 22:33:41 n_hibma Exp $ */
3
4 /*
5 * Copyright (c) 1998, 2004 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Lennart Augustsson (lennart (at) augustsson.net) at
10 * Carlstedt Research & Technology.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 /*
35 * USB Universal Host Controller driver.
36 * Handles e.g. PIIX3 and PIIX4.
37 *
38 * UHCI spec: http://www.intel.com/technology/usb/spec.htm
39 * USB spec: http://www.usb.org/developers/docs/
40 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf
41 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf
42 */
43
44 #include <sys/cdefs.h>
45 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.240.2.1 2012/04/17 00:08:07 yamt Exp $");
46
47 #include "opt_usb.h"
48
49 #include <sys/param.h>
50 #include <sys/systm.h>
51 #include <sys/kernel.h>
52 #include <sys/malloc.h>
53 #include <sys/device.h>
54 #include <sys/select.h>
55 #include <sys/extent.h>
56 #include <sys/proc.h>
57 #include <sys/queue.h>
58 #include <sys/bus.h>
59 #include <sys/cpu.h>
60
61 #include <machine/endian.h>
62
63 #include <dev/usb/usb.h>
64 #include <dev/usb/usbdi.h>
65 #include <dev/usb/usbdivar.h>
66 #include <dev/usb/usb_mem.h>
67 #include <dev/usb/usb_quirks.h>
68
69 #include <dev/usb/uhcireg.h>
70 #include <dev/usb/uhcivar.h>
71 #include <dev/usb/usbroothub_subr.h>
72
73 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */
74 /*#define UHCI_CTL_LOOP */
75
76
77
78 #ifdef UHCI_DEBUG
79 uhci_softc_t *thesc;
80 #define DPRINTF(x) if (uhcidebug) printf x
81 #define DPRINTFN(n,x) if (uhcidebug>(n)) printf x
82 int uhcidebug = 0;
83 int uhcinoloop = 0;
84 #else
85 #define DPRINTF(x)
86 #define DPRINTFN(n,x)
87 #endif
88
89 /*
90 * The UHCI controller is little endian, so on big endian machines
91 * the data stored in memory needs to be swapped.
92 */
93
94 struct uhci_pipe {
95 struct usbd_pipe pipe;
96 int nexttoggle;
97
98 u_char aborting;
99 usbd_xfer_handle abortstart, abortend;
100
101 /* Info needed for different pipe kinds. */
102 union {
103 /* Control pipe */
104 struct {
105 uhci_soft_qh_t *sqh;
106 usb_dma_t reqdma;
107 uhci_soft_td_t *setup, *stat;
108 u_int length;
109 } ctl;
110 /* Interrupt pipe */
111 struct {
112 int npoll;
113 int isread;
114 uhci_soft_qh_t **qhs;
115 } intr;
116 /* Bulk pipe */
117 struct {
118 uhci_soft_qh_t *sqh;
119 u_int length;
120 int isread;
121 } bulk;
122 /* Iso pipe */
123 struct iso {
124 uhci_soft_td_t **stds;
125 int next, inuse;
126 } iso;
127 } u;
128 };
129
130 Static void uhci_globalreset(uhci_softc_t *);
131 Static usbd_status uhci_portreset(uhci_softc_t*, int);
132 Static void uhci_reset(uhci_softc_t *);
133 Static usbd_status uhci_run(uhci_softc_t *, int run);
134 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *);
135 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *);
136 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *);
137 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *);
138 #if 0
139 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *,
140 uhci_intr_info_t *);
141 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *);
142 #endif
143
144 Static void uhci_free_std_chain(uhci_softc_t *,
145 uhci_soft_td_t *, uhci_soft_td_t *);
146 Static usbd_status uhci_alloc_std_chain(struct uhci_pipe *,
147 uhci_softc_t *, int, int, u_int16_t, usb_dma_t *,
148 uhci_soft_td_t **, uhci_soft_td_t **);
149 Static void uhci_poll_hub(void *);
150 Static void uhci_waitintr(uhci_softc_t *, usbd_xfer_handle);
151 Static void uhci_check_intr(uhci_softc_t *, uhci_intr_info_t *);
152 Static void uhci_idone(uhci_intr_info_t *);
153
154 Static void uhci_abort_xfer(usbd_xfer_handle, usbd_status status);
155
156 Static void uhci_timeout(void *);
157 Static void uhci_timeout_task(void *);
158 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *);
159 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *);
160 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *);
161 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *);
162 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *);
163 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *);
164 Static void uhci_add_loop(uhci_softc_t *sc);
165 Static void uhci_rem_loop(uhci_softc_t *sc);
166
167 Static usbd_status uhci_setup_isoc(usbd_pipe_handle pipe);
168 Static void uhci_device_isoc_enter(usbd_xfer_handle);
169
170 Static usbd_status uhci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t);
171 Static void uhci_freem(struct usbd_bus *, usb_dma_t *);
172
173 Static usbd_xfer_handle uhci_allocx(struct usbd_bus *);
174 Static void uhci_freex(struct usbd_bus *, usbd_xfer_handle);
175
176 Static usbd_status uhci_device_ctrl_transfer(usbd_xfer_handle);
177 Static usbd_status uhci_device_ctrl_start(usbd_xfer_handle);
178 Static void uhci_device_ctrl_abort(usbd_xfer_handle);
179 Static void uhci_device_ctrl_close(usbd_pipe_handle);
180 Static void uhci_device_ctrl_done(usbd_xfer_handle);
181
182 Static usbd_status uhci_device_intr_transfer(usbd_xfer_handle);
183 Static usbd_status uhci_device_intr_start(usbd_xfer_handle);
184 Static void uhci_device_intr_abort(usbd_xfer_handle);
185 Static void uhci_device_intr_close(usbd_pipe_handle);
186 Static void uhci_device_intr_done(usbd_xfer_handle);
187
188 Static usbd_status uhci_device_bulk_transfer(usbd_xfer_handle);
189 Static usbd_status uhci_device_bulk_start(usbd_xfer_handle);
190 Static void uhci_device_bulk_abort(usbd_xfer_handle);
191 Static void uhci_device_bulk_close(usbd_pipe_handle);
192 Static void uhci_device_bulk_done(usbd_xfer_handle);
193
194 Static usbd_status uhci_device_isoc_transfer(usbd_xfer_handle);
195 Static usbd_status uhci_device_isoc_start(usbd_xfer_handle);
196 Static void uhci_device_isoc_abort(usbd_xfer_handle);
197 Static void uhci_device_isoc_close(usbd_pipe_handle);
198 Static void uhci_device_isoc_done(usbd_xfer_handle);
199
200 Static usbd_status uhci_root_ctrl_transfer(usbd_xfer_handle);
201 Static usbd_status uhci_root_ctrl_start(usbd_xfer_handle);
202 Static void uhci_root_ctrl_abort(usbd_xfer_handle);
203 Static void uhci_root_ctrl_close(usbd_pipe_handle);
204 Static void uhci_root_ctrl_done(usbd_xfer_handle);
205
206 Static usbd_status uhci_root_intr_transfer(usbd_xfer_handle);
207 Static usbd_status uhci_root_intr_start(usbd_xfer_handle);
208 Static void uhci_root_intr_abort(usbd_xfer_handle);
209 Static void uhci_root_intr_close(usbd_pipe_handle);
210 Static void uhci_root_intr_done(usbd_xfer_handle);
211
212 Static usbd_status uhci_open(usbd_pipe_handle);
213 Static void uhci_poll(struct usbd_bus *);
214 Static void uhci_softintr(void *);
215
216 Static usbd_status uhci_device_request(usbd_xfer_handle xfer);
217
218 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *);
219 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *);
220 Static usbd_status uhci_device_setintr(uhci_softc_t *sc,
221 struct uhci_pipe *pipe, int ival);
222
223 Static void uhci_device_clear_toggle(usbd_pipe_handle pipe);
224 Static void uhci_noop(usbd_pipe_handle pipe);
225
226 static inline uhci_soft_qh_t *uhci_find_prev_qh(uhci_soft_qh_t *,
227 uhci_soft_qh_t *);
228
229 #ifdef UHCI_DEBUG
230 Static void uhci_dump_all(uhci_softc_t *);
231 Static void uhci_dumpregs(uhci_softc_t *);
232 Static void uhci_dump_qhs(uhci_soft_qh_t *);
233 Static void uhci_dump_qh(uhci_soft_qh_t *);
234 Static void uhci_dump_tds(uhci_soft_td_t *);
235 Static void uhci_dump_td(uhci_soft_td_t *);
236 Static void uhci_dump_ii(uhci_intr_info_t *ii);
237 void uhci_dump(void);
238 #endif
239
240 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \
241 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
242 #define UWRITE1(sc, r, x) \
243 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \
244 } while (/*CONSTCOND*/0)
245 #define UWRITE2(sc, r, x) \
246 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \
247 } while (/*CONSTCOND*/0)
248 #define UWRITE4(sc, r, x) \
249 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \
250 } while (/*CONSTCOND*/0)
251 static __inline uint8_t
252 UREAD1(uhci_softc_t *sc, bus_size_t r)
253 {
254
255 UBARR(sc);
256 return bus_space_read_1(sc->iot, sc->ioh, r);
257 }
258
259 static __inline uint16_t
260 UREAD2(uhci_softc_t *sc, bus_size_t r)
261 {
262
263 UBARR(sc);
264 return bus_space_read_2(sc->iot, sc->ioh, r);
265 }
266
267 static __inline uint32_t
268 UREAD4(uhci_softc_t *sc, bus_size_t r)
269 {
270
271 UBARR(sc);
272 return bus_space_read_4(sc->iot, sc->ioh, r);
273 }
274
275 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd)
276 #define UHCISTS(sc) UREAD2(sc, UHCI_STS)
277
278 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */
279
280 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK)
281
282 #define UHCI_INTR_ENDPT 1
283
284 const struct usbd_bus_methods uhci_bus_methods = {
285 .open_pipe = uhci_open,
286 .soft_intr = uhci_softintr,
287 .do_poll = uhci_poll,
288 .allocm = uhci_allocm,
289 .freem = uhci_freem,
290 .allocx = uhci_allocx,
291 .freex = uhci_freex,
292 };
293
294 const struct usbd_pipe_methods uhci_root_ctrl_methods = {
295 .transfer = uhci_root_ctrl_transfer,
296 .start = uhci_root_ctrl_start,
297 .abort = uhci_root_ctrl_abort,
298 .close = uhci_root_ctrl_close,
299 .cleartoggle = uhci_noop,
300 .done = uhci_root_ctrl_done,
301 };
302
303 const struct usbd_pipe_methods uhci_root_intr_methods = {
304 .transfer = uhci_root_intr_transfer,
305 .start = uhci_root_intr_start,
306 .abort = uhci_root_intr_abort,
307 .close = uhci_root_intr_close,
308 .cleartoggle = uhci_noop,
309 .done = uhci_root_intr_done,
310 };
311
312 const struct usbd_pipe_methods uhci_device_ctrl_methods = {
313 .transfer = uhci_device_ctrl_transfer,
314 .start = uhci_device_ctrl_start,
315 .abort = uhci_device_ctrl_abort,
316 .close = uhci_device_ctrl_close,
317 .cleartoggle = uhci_noop,
318 .done = uhci_device_ctrl_done,
319 };
320
321 const struct usbd_pipe_methods uhci_device_intr_methods = {
322 .transfer = uhci_device_intr_transfer,
323 .start = uhci_device_intr_start,
324 .abort = uhci_device_intr_abort,
325 .close = uhci_device_intr_close,
326 .cleartoggle = uhci_device_clear_toggle,
327 .done = uhci_device_intr_done,
328 };
329
330 const struct usbd_pipe_methods uhci_device_bulk_methods = {
331 .transfer = uhci_device_bulk_transfer,
332 .start = uhci_device_bulk_start,
333 .abort = uhci_device_bulk_abort,
334 .close = uhci_device_bulk_close,
335 .cleartoggle = uhci_device_clear_toggle,
336 .done = uhci_device_bulk_done,
337 };
338
339 const struct usbd_pipe_methods uhci_device_isoc_methods = {
340 .transfer = uhci_device_isoc_transfer,
341 .start = uhci_device_isoc_start,
342 .abort = uhci_device_isoc_abort,
343 .close = uhci_device_isoc_close,
344 .cleartoggle = uhci_noop,
345 .done = uhci_device_isoc_done,
346 };
347
348 #define uhci_add_intr_info(sc, ii) \
349 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ii), list)
350 #define uhci_del_intr_info(ii) \
351 do { \
352 LIST_REMOVE((ii), list); \
353 (ii)->list.le_prev = NULL; \
354 } while (0)
355 #define uhci_active_intr_info(ii) ((ii)->list.le_prev != NULL)
356
357 static inline uhci_soft_qh_t *
358 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh)
359 {
360 DPRINTFN(15,("uhci_find_prev_qh: pqh=%p sqh=%p\n", pqh, sqh));
361
362 for (; pqh->hlink != sqh; pqh = pqh->hlink) {
363 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG)
364 usb_syncmem(&pqh->dma,
365 pqh->offs + offsetof(uhci_qh_t, qh_hlink),
366 sizeof(pqh->qh.qh_hlink),
367 BUS_DMASYNC_POSTWRITE);
368 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) {
369 printf("uhci_find_prev_qh: QH not found\n");
370 return (NULL);
371 }
372 #endif
373 }
374 return (pqh);
375 }
376
377 void
378 uhci_globalreset(uhci_softc_t *sc)
379 {
380 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */
381 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */
382 UHCICMD(sc, 0); /* do nothing */
383 }
384
385 usbd_status
386 uhci_init(uhci_softc_t *sc)
387 {
388 usbd_status err;
389 int i, j;
390 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh;
391 uhci_soft_td_t *std;
392
393 DPRINTFN(1,("uhci_init: start\n"));
394
395 #ifdef UHCI_DEBUG
396 thesc = sc;
397
398 if (uhcidebug > 2)
399 uhci_dumpregs(sc);
400 #endif
401
402 sc->sc_suspend = PWR_RESUME;
403
404 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */
405 uhci_globalreset(sc); /* reset the controller */
406 uhci_reset(sc);
407
408 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag,
409 USB_MEM_RESERVE);
410
411 /* Allocate and initialize real frame array. */
412 err = usb_allocmem(&sc->sc_bus,
413 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t),
414 UHCI_FRAMELIST_ALIGN, &sc->sc_dma);
415 if (err)
416 return (err);
417 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0);
418 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */
419 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/
420
421 /*
422 * Allocate a TD, inactive, that hangs from the last QH.
423 * This is to avoid a bug in the PIIX that makes it run berserk
424 * otherwise.
425 */
426 std = uhci_alloc_std(sc);
427 if (std == NULL)
428 return (USBD_NOMEM);
429 std->link.std = NULL;
430 std->td.td_link = htole32(UHCI_PTR_T);
431 std->td.td_status = htole32(0); /* inactive */
432 std->td.td_token = htole32(0);
433 std->td.td_buffer = htole32(0);
434 usb_syncmem(&std->dma, std->offs, sizeof(std->td),
435 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
436
437 /* Allocate the dummy QH marking the end and used for looping the QHs.*/
438 lsqh = uhci_alloc_sqh(sc);
439 if (lsqh == NULL)
440 return (USBD_NOMEM);
441 lsqh->hlink = NULL;
442 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */
443 lsqh->elink = std;
444 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD);
445 sc->sc_last_qh = lsqh;
446 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh),
447 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
448
449 /* Allocate the dummy QH where bulk traffic will be queued. */
450 bsqh = uhci_alloc_sqh(sc);
451 if (bsqh == NULL)
452 return (USBD_NOMEM);
453 bsqh->hlink = lsqh;
454 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH);
455 bsqh->elink = NULL;
456 bsqh->qh.qh_elink = htole32(UHCI_PTR_T);
457 sc->sc_bulk_start = sc->sc_bulk_end = bsqh;
458 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh),
459 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
460
461 /* Allocate dummy QH where high speed control traffic will be queued. */
462 chsqh = uhci_alloc_sqh(sc);
463 if (chsqh == NULL)
464 return (USBD_NOMEM);
465 chsqh->hlink = bsqh;
466 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH);
467 chsqh->elink = NULL;
468 chsqh->qh.qh_elink = htole32(UHCI_PTR_T);
469 sc->sc_hctl_start = sc->sc_hctl_end = chsqh;
470 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh),
471 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
472
473 /* Allocate dummy QH where control traffic will be queued. */
474 clsqh = uhci_alloc_sqh(sc);
475 if (clsqh == NULL)
476 return (USBD_NOMEM);
477 clsqh->hlink = chsqh;
478 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH);
479 clsqh->elink = NULL;
480 clsqh->qh.qh_elink = htole32(UHCI_PTR_T);
481 sc->sc_lctl_start = sc->sc_lctl_end = clsqh;
482 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh),
483 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
484
485 /*
486 * Make all (virtual) frame list pointers point to the interrupt
487 * queue heads and the interrupt queue heads at the control
488 * queue head and point the physical frame list to the virtual.
489 */
490 for(i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
491 std = uhci_alloc_std(sc);
492 sqh = uhci_alloc_sqh(sc);
493 if (std == NULL || sqh == NULL)
494 return (USBD_NOMEM);
495 std->link.sqh = sqh;
496 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH);
497 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */
498 std->td.td_token = htole32(0);
499 std->td.td_buffer = htole32(0);
500 usb_syncmem(&std->dma, std->offs, sizeof(std->td),
501 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
502 sqh->hlink = clsqh;
503 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH);
504 sqh->elink = NULL;
505 sqh->qh.qh_elink = htole32(UHCI_PTR_T);
506 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
507 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
508 sc->sc_vframes[i].htd = std;
509 sc->sc_vframes[i].etd = std;
510 sc->sc_vframes[i].hqh = sqh;
511 sc->sc_vframes[i].eqh = sqh;
512 for (j = i;
513 j < UHCI_FRAMELIST_COUNT;
514 j += UHCI_VFRAMELIST_COUNT)
515 sc->sc_pframes[j] = htole32(std->physaddr);
516 }
517 usb_syncmem(&sc->sc_dma, 0,
518 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t),
519 BUS_DMASYNC_PREWRITE);
520
521
522 LIST_INIT(&sc->sc_intrhead);
523
524 SIMPLEQ_INIT(&sc->sc_free_xfers);
525
526 callout_init(&sc->sc_poll_handle, 0);
527
528 /* Set up the bus struct. */
529 sc->sc_bus.methods = &uhci_bus_methods;
530 sc->sc_bus.pipe_size = sizeof(struct uhci_pipe);
531
532 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */
533
534 DPRINTFN(1,("uhci_init: enabling\n"));
535
536 err = uhci_run(sc, 1); /* and here we go... */
537 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE |
538 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */
539 return err;
540 }
541
542 int
543 uhci_activate(device_t self, enum devact act)
544 {
545 struct uhci_softc *sc = device_private(self);
546
547 switch (act) {
548 case DVACT_DEACTIVATE:
549 sc->sc_dying = 1;
550 return 0;
551 default:
552 return EOPNOTSUPP;
553 }
554 }
555
556 void
557 uhci_childdet(device_t self, device_t child)
558 {
559 struct uhci_softc *sc = device_private(self);
560
561 KASSERT(sc->sc_child == child);
562 sc->sc_child = NULL;
563 }
564
565 int
566 uhci_detach(struct uhci_softc *sc, int flags)
567 {
568 usbd_xfer_handle xfer;
569 int rv = 0;
570
571 if (sc->sc_child != NULL)
572 rv = config_detach(sc->sc_child, flags);
573
574 if (rv != 0)
575 return (rv);
576
577 /* Free all xfers associated with this HC. */
578 for (;;) {
579 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers);
580 if (xfer == NULL)
581 break;
582 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next);
583 free(xfer, M_USB);
584 }
585
586 callout_halt(&sc->sc_poll_handle, NULL);
587 callout_destroy(&sc->sc_poll_handle);
588
589 /* XXX free other data structures XXX */
590
591 return (rv);
592 }
593
594 usbd_status
595 uhci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size)
596 {
597 struct uhci_softc *sc = bus->hci_private;
598 usbd_status status;
599 u_int32_t n;
600
601 /*
602 * XXX
603 * Since we are allocating a buffer we can assume that we will
604 * need TDs for it. Since we don't want to allocate those from
605 * an interrupt context, we allocate them here and free them again.
606 * This is no guarantee that we'll get the TDs next time...
607 */
608 n = size / 8;
609 if (n > 16) {
610 u_int32_t i;
611 uhci_soft_td_t **stds;
612 DPRINTF(("uhci_allocm: get %d TDs\n", n));
613 stds = malloc(sizeof(uhci_soft_td_t *) * n, M_TEMP,
614 M_WAITOK|M_ZERO);
615 for(i=0; i < n; i++)
616 stds[i] = uhci_alloc_std(sc);
617 for(i=0; i < n; i++)
618 if (stds[i] != NULL)
619 uhci_free_std(sc, stds[i]);
620 free(stds, M_TEMP);
621 }
622
623
624 status = usb_allocmem(&sc->sc_bus, size, 0, dma);
625 if (status == USBD_NOMEM)
626 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size);
627 return status;
628 }
629
630 void
631 uhci_freem(struct usbd_bus *bus, usb_dma_t *dma)
632 {
633 if (dma->block->flags & USB_DMA_RESERVE) {
634 usb_reserve_freem(&((struct uhci_softc *)bus)->sc_dma_reserve,
635 dma);
636 return;
637 }
638 usb_freemem(&((struct uhci_softc *)bus)->sc_bus, dma);
639 }
640
641 usbd_xfer_handle
642 uhci_allocx(struct usbd_bus *bus)
643 {
644 struct uhci_softc *sc = bus->hci_private;
645 usbd_xfer_handle xfer;
646
647 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers);
648 if (xfer != NULL) {
649 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next);
650 #ifdef DIAGNOSTIC
651 if (xfer->busy_free != XFER_FREE) {
652 printf("uhci_allocx: xfer=%p not free, 0x%08x\n", xfer,
653 xfer->busy_free);
654 }
655 #endif
656 } else {
657 xfer = malloc(sizeof(struct uhci_xfer), M_USB, M_NOWAIT);
658 }
659 if (xfer != NULL) {
660 memset(xfer, 0, sizeof (struct uhci_xfer));
661 UXFER(xfer)->iinfo.sc = sc;
662 #ifdef DIAGNOSTIC
663 UXFER(xfer)->iinfo.isdone = 1;
664 xfer->busy_free = XFER_BUSY;
665 #endif
666 }
667 return (xfer);
668 }
669
670 void
671 uhci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer)
672 {
673 struct uhci_softc *sc = bus->hci_private;
674
675 #ifdef DIAGNOSTIC
676 if (xfer->busy_free != XFER_BUSY) {
677 printf("uhci_freex: xfer=%p not busy, 0x%08x\n", xfer,
678 xfer->busy_free);
679 }
680 xfer->busy_free = XFER_FREE;
681 if (!UXFER(xfer)->iinfo.isdone) {
682 printf("uhci_freex: !isdone\n");
683 }
684 #endif
685 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next);
686 }
687
688 /*
689 * Handle suspend/resume.
690 *
691 * We need to switch to polling mode here, because this routine is
692 * called from an interrupt context. This is all right since we
693 * are almost suspended anyway.
694 */
695 bool
696 uhci_resume(device_t dv, const pmf_qual_t *qual)
697 {
698 uhci_softc_t *sc = device_private(dv);
699 int cmd;
700 int s;
701
702 s = splhardusb();
703
704 cmd = UREAD2(sc, UHCI_CMD);
705 sc->sc_bus.use_polling++;
706 UWRITE2(sc, UHCI_INTR, 0);
707 uhci_globalreset(sc);
708 uhci_reset(sc);
709 if (cmd & UHCI_CMD_RS)
710 uhci_run(sc, 0);
711
712 /* restore saved state */
713 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0));
714 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum);
715 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof);
716
717 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */
718 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY);
719 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */
720 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE |
721 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE);
722 UHCICMD(sc, UHCI_CMD_MAXP);
723 uhci_run(sc, 1); /* and start traffic again */
724 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY);
725 sc->sc_bus.use_polling--;
726 if (sc->sc_intr_xfer != NULL)
727 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub,
728 sc->sc_intr_xfer);
729 #ifdef UHCI_DEBUG
730 if (uhcidebug > 2)
731 uhci_dumpregs(sc);
732 #endif
733
734 sc->sc_suspend = PWR_RESUME;
735 splx(s);
736
737 return true;
738 }
739
740 bool
741 uhci_suspend(device_t dv, const pmf_qual_t *qual)
742 {
743 uhci_softc_t *sc = device_private(dv);
744 int cmd;
745 int s;
746
747 s = splhardusb();
748
749 cmd = UREAD2(sc, UHCI_CMD);
750
751 #ifdef UHCI_DEBUG
752 if (uhcidebug > 2)
753 uhci_dumpregs(sc);
754 #endif
755 if (sc->sc_intr_xfer != NULL)
756 callout_stop(&sc->sc_poll_handle);
757 sc->sc_suspend = PWR_SUSPEND;
758 sc->sc_bus.use_polling++;
759
760 uhci_run(sc, 0); /* stop the controller */
761 cmd &= ~UHCI_CMD_RS;
762
763 /* save some state if BIOS doesn't */
764 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM);
765 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF);
766
767 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */
768
769 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */
770 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT);
771 sc->sc_bus.use_polling--;
772
773 splx(s);
774
775 return true;
776 }
777
778 #ifdef UHCI_DEBUG
779 Static void
780 uhci_dumpregs(uhci_softc_t *sc)
781 {
782 DPRINTFN(-1,("%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, "
783 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n",
784 device_xname(sc->sc_dev),
785 UREAD2(sc, UHCI_CMD),
786 UREAD2(sc, UHCI_STS),
787 UREAD2(sc, UHCI_INTR),
788 UREAD2(sc, UHCI_FRNUM),
789 UREAD4(sc, UHCI_FLBASEADDR),
790 UREAD1(sc, UHCI_SOF),
791 UREAD2(sc, UHCI_PORTSC1),
792 UREAD2(sc, UHCI_PORTSC2)));
793 }
794
795 void
796 uhci_dump_td(uhci_soft_td_t *p)
797 {
798 char sbuf[128], sbuf2[128];
799
800
801 usb_syncmem(&p->dma, p->offs, sizeof(p->td),
802 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
803 DPRINTFN(-1,("TD(%p) at %08lx = link=0x%08lx status=0x%08lx "
804 "token=0x%08lx buffer=0x%08lx\n",
805 p, (long)p->physaddr,
806 (long)le32toh(p->td.td_link),
807 (long)le32toh(p->td.td_status),
808 (long)le32toh(p->td.td_token),
809 (long)le32toh(p->td.td_buffer)));
810
811 snprintb(sbuf, sizeof(sbuf), "\20\1T\2Q\3VF",
812 (u_int32_t)le32toh(p->td.td_link));
813 snprintb(sbuf2, sizeof(sbuf2),
814 "\20\22BITSTUFF\23CRCTO\24NAK\25BABBLE\26DBUFFER\27"
815 "STALLED\30ACTIVE\31IOC\32ISO\33LS\36SPD",
816 (u_int32_t)le32toh(p->td.td_status));
817
818 DPRINTFN(-1,(" %s %s,errcnt=%d,actlen=%d pid=%02x,addr=%d,endpt=%d,"
819 "D=%d,maxlen=%d\n", sbuf, sbuf2,
820 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)),
821 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)),
822 UHCI_TD_GET_PID(le32toh(p->td.td_token)),
823 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)),
824 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)),
825 UHCI_TD_GET_DT(le32toh(p->td.td_token)),
826 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token))));
827 usb_syncmem(&p->dma, p->offs, sizeof(p->td),
828 BUS_DMASYNC_PREREAD);
829 }
830
831 void
832 uhci_dump_qh(uhci_soft_qh_t *sqh)
833 {
834 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
835 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
836 DPRINTFN(-1,("QH(%p) at %08x: hlink=%08x elink=%08x\n", sqh,
837 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink),
838 le32toh(sqh->qh.qh_elink)));
839 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD);
840 }
841
842
843 #if 1
844 void
845 uhci_dump(void)
846 {
847 uhci_dump_all(thesc);
848 }
849 #endif
850
851 void
852 uhci_dump_all(uhci_softc_t *sc)
853 {
854 uhci_dumpregs(sc);
855 printf("intrs=%d\n", sc->sc_bus.no_intrs);
856 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/
857 uhci_dump_qh(sc->sc_lctl_start);
858 }
859
860
861 void
862 uhci_dump_qhs(uhci_soft_qh_t *sqh)
863 {
864 uhci_dump_qh(sqh);
865
866 /* uhci_dump_qhs displays all the QHs and TDs from the given QH onwards
867 * Traverses sideways first, then down.
868 *
869 * QH1
870 * QH2
871 * No QH
872 * TD2.1
873 * TD2.2
874 * TD1.1
875 * etc.
876 *
877 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1.
878 */
879
880
881 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
882 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
883 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T))
884 uhci_dump_qhs(sqh->hlink);
885 else
886 DPRINTF(("No QH\n"));
887 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD);
888
889 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T))
890 uhci_dump_tds(sqh->elink);
891 else
892 DPRINTF(("No TD\n"));
893 }
894
895 void
896 uhci_dump_tds(uhci_soft_td_t *std)
897 {
898 uhci_soft_td_t *td;
899 int stop;
900
901 for(td = std; td != NULL; td = td->link.std) {
902 uhci_dump_td(td);
903
904 /* Check whether the link pointer in this TD marks
905 * the link pointer as end of queue. This avoids
906 * printing the free list in case the queue/TD has
907 * already been moved there (seatbelt).
908 */
909 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link),
910 sizeof(td->td.td_link),
911 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
912 stop = (le32toh(td->td.td_link) & UHCI_PTR_T ||
913 le32toh(td->td.td_link) == 0);
914 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link),
915 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD);
916 if (stop)
917 break;
918 }
919 }
920
921 Static void
922 uhci_dump_ii(uhci_intr_info_t *ii)
923 {
924 usbd_pipe_handle pipe;
925 usb_endpoint_descriptor_t *ed;
926 usbd_device_handle dev;
927
928 #ifdef DIAGNOSTIC
929 #define DONE ii->isdone
930 #else
931 #define DONE 0
932 #endif
933 if (ii == NULL) {
934 printf("ii NULL\n");
935 return;
936 }
937 if (ii->xfer == NULL) {
938 printf("ii %p: done=%d xfer=NULL\n",
939 ii, DONE);
940 return;
941 }
942 pipe = ii->xfer->pipe;
943 if (pipe == NULL) {
944 printf("ii %p: done=%d xfer=%p pipe=NULL\n",
945 ii, DONE, ii->xfer);
946 return;
947 }
948 if (pipe->endpoint == NULL) {
949 printf("ii %p: done=%d xfer=%p pipe=%p pipe->endpoint=NULL\n",
950 ii, DONE, ii->xfer, pipe);
951 return;
952 }
953 if (pipe->device == NULL) {
954 printf("ii %p: done=%d xfer=%p pipe=%p pipe->device=NULL\n",
955 ii, DONE, ii->xfer, pipe);
956 return;
957 }
958 ed = pipe->endpoint->edesc;
959 dev = pipe->device;
960 printf("ii %p: done=%d xfer=%p dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n",
961 ii, DONE, ii->xfer, dev,
962 UGETW(dev->ddesc.idVendor),
963 UGETW(dev->ddesc.idProduct),
964 dev->address, pipe,
965 ed->bEndpointAddress, ed->bmAttributes);
966 #undef DONE
967 }
968
969 void uhci_dump_iis(struct uhci_softc *sc);
970 void
971 uhci_dump_iis(struct uhci_softc *sc)
972 {
973 uhci_intr_info_t *ii;
974
975 printf("intr_info list:\n");
976 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = LIST_NEXT(ii, list))
977 uhci_dump_ii(ii);
978 }
979
980 void iidump(void);
981 void iidump(void) { uhci_dump_iis(thesc); }
982
983 #endif
984
985 /*
986 * This routine is executed periodically and simulates interrupts
987 * from the root controller interrupt pipe for port status change.
988 */
989 void
990 uhci_poll_hub(void *addr)
991 {
992 usbd_xfer_handle xfer = addr;
993 usbd_pipe_handle pipe = xfer->pipe;
994 uhci_softc_t *sc;
995 int s;
996 u_char *p;
997
998 DPRINTFN(20, ("uhci_poll_hub\n"));
999
1000 if (__predict_false(pipe->device == NULL || pipe->device->bus == NULL))
1001 return; /* device has detached */
1002 sc = pipe->device->bus->hci_private;
1003 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer);
1004
1005 p = KERNADDR(&xfer->dmabuf, 0);
1006 p[0] = 0;
1007 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC))
1008 p[0] |= 1<<1;
1009 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC))
1010 p[0] |= 1<<2;
1011 if (p[0] == 0)
1012 /* No change, try again in a while */
1013 return;
1014
1015 xfer->actlen = 1;
1016 xfer->status = USBD_NORMAL_COMPLETION;
1017 s = splusb();
1018 usb_transfer_complete(xfer);
1019 splx(s);
1020 }
1021
1022 void
1023 uhci_root_intr_done(usbd_xfer_handle xfer)
1024 {
1025 }
1026
1027 void
1028 uhci_root_ctrl_done(usbd_xfer_handle xfer)
1029 {
1030 }
1031
1032 /*
1033 * Let the last QH loop back to the high speed control transfer QH.
1034 * This is what intel calls "bandwidth reclamation" and improves
1035 * USB performance a lot for some devices.
1036 * If we are already looping, just count it.
1037 */
1038 void
1039 uhci_add_loop(uhci_softc_t *sc) {
1040 #ifdef UHCI_DEBUG
1041 if (uhcinoloop)
1042 return;
1043 #endif
1044 if (++sc->sc_loops == 1) {
1045 DPRINTFN(5,("uhci_start_loop: add\n"));
1046 /* Note, we don't loop back the soft pointer. */
1047 sc->sc_last_qh->qh.qh_hlink =
1048 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH);
1049 usb_syncmem(&sc->sc_last_qh->dma,
1050 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink),
1051 sizeof(sc->sc_last_qh->qh.qh_hlink),
1052 BUS_DMASYNC_PREWRITE);
1053 }
1054 }
1055
1056 void
1057 uhci_rem_loop(uhci_softc_t *sc) {
1058 #ifdef UHCI_DEBUG
1059 if (uhcinoloop)
1060 return;
1061 #endif
1062 if (--sc->sc_loops == 0) {
1063 DPRINTFN(5,("uhci_end_loop: remove\n"));
1064 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T);
1065 usb_syncmem(&sc->sc_last_qh->dma,
1066 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink),
1067 sizeof(sc->sc_last_qh->qh.qh_hlink),
1068 BUS_DMASYNC_PREWRITE);
1069 }
1070 }
1071
1072 /* Add high speed control QH, called at splusb(). */
1073 void
1074 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1075 {
1076 uhci_soft_qh_t *eqh;
1077
1078 DPRINTFN(10, ("uhci_add_ctrl: sqh=%p\n", sqh));
1079 eqh = sc->sc_hctl_end;
1080 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1081 sizeof(eqh->qh.qh_hlink),
1082 BUS_DMASYNC_POSTWRITE);
1083 sqh->hlink = eqh->hlink;
1084 sqh->qh.qh_hlink = eqh->qh.qh_hlink;
1085 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1086 BUS_DMASYNC_PREWRITE);
1087 eqh->hlink = sqh;
1088 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
1089 sc->sc_hctl_end = sqh;
1090 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1091 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
1092 #ifdef UHCI_CTL_LOOP
1093 uhci_add_loop(sc);
1094 #endif
1095 }
1096
1097 /* Remove high speed control QH, called at splusb(). */
1098 void
1099 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1100 {
1101 uhci_soft_qh_t *pqh;
1102
1103 DPRINTFN(10, ("uhci_remove_hs_ctrl: sqh=%p\n", sqh));
1104 #ifdef UHCI_CTL_LOOP
1105 uhci_rem_loop(sc);
1106 #endif
1107 /*
1108 * The T bit should be set in the elink of the QH so that the HC
1109 * doesn't follow the pointer. This condition may fail if the
1110 * the transferred packet was short so that the QH still points
1111 * at the last used TD.
1112 * In this case we set the T bit and wait a little for the HC
1113 * to stop looking at the TD.
1114 * Note that if the TD chain is large enough, the controller
1115 * may still be looking at the chain at the end of this function.
1116 * uhci_free_std_chain() will make sure the controller stops
1117 * looking at it quickly, but until then we should not change
1118 * sqh->hlink.
1119 */
1120 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
1121 sizeof(sqh->qh.qh_elink),
1122 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1123 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) {
1124 sqh->qh.qh_elink = htole32(UHCI_PTR_T);
1125 usb_syncmem(&sqh->dma,
1126 sqh->offs + offsetof(uhci_qh_t, qh_elink),
1127 sizeof(sqh->qh.qh_elink),
1128 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1129 delay(UHCI_QH_REMOVE_DELAY);
1130 }
1131
1132 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh);
1133 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
1134 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
1135 pqh->hlink = sqh->hlink;
1136 pqh->qh.qh_hlink = sqh->qh.qh_hlink;
1137 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
1138 sizeof(pqh->qh.qh_hlink),
1139 BUS_DMASYNC_PREWRITE);
1140 delay(UHCI_QH_REMOVE_DELAY);
1141 if (sc->sc_hctl_end == sqh)
1142 sc->sc_hctl_end = pqh;
1143 }
1144
1145 /* Add low speed control QH, called at splusb(). */
1146 void
1147 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1148 {
1149 uhci_soft_qh_t *eqh;
1150
1151 DPRINTFN(10, ("uhci_add_ls_ctrl: sqh=%p\n", sqh));
1152 eqh = sc->sc_lctl_end;
1153 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1154 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
1155 sqh->hlink = eqh->hlink;
1156 sqh->qh.qh_hlink = eqh->qh.qh_hlink;
1157 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1158 BUS_DMASYNC_PREWRITE);
1159 eqh->hlink = sqh;
1160 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
1161 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1162 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
1163 sc->sc_lctl_end = sqh;
1164 }
1165
1166 /* Remove low speed control QH, called at splusb(). */
1167 void
1168 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1169 {
1170 uhci_soft_qh_t *pqh;
1171
1172 DPRINTFN(10, ("uhci_remove_ls_ctrl: sqh=%p\n", sqh));
1173 /* See comment in uhci_remove_hs_ctrl() */
1174 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
1175 sizeof(sqh->qh.qh_elink),
1176 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1177 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) {
1178 sqh->qh.qh_elink = htole32(UHCI_PTR_T);
1179 usb_syncmem(&sqh->dma,
1180 sqh->offs + offsetof(uhci_qh_t, qh_elink),
1181 sizeof(sqh->qh.qh_elink),
1182 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1183 delay(UHCI_QH_REMOVE_DELAY);
1184 }
1185 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh);
1186 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
1187 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
1188 pqh->hlink = sqh->hlink;
1189 pqh->qh.qh_hlink = sqh->qh.qh_hlink;
1190 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
1191 sizeof(pqh->qh.qh_hlink),
1192 BUS_DMASYNC_PREWRITE);
1193 delay(UHCI_QH_REMOVE_DELAY);
1194 if (sc->sc_lctl_end == sqh)
1195 sc->sc_lctl_end = pqh;
1196 }
1197
1198 /* Add bulk QH, called at splusb(). */
1199 void
1200 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1201 {
1202 uhci_soft_qh_t *eqh;
1203
1204 DPRINTFN(10, ("uhci_add_bulk: sqh=%p\n", sqh));
1205 eqh = sc->sc_bulk_end;
1206 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1207 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
1208 sqh->hlink = eqh->hlink;
1209 sqh->qh.qh_hlink = eqh->qh.qh_hlink;
1210 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1211 BUS_DMASYNC_PREWRITE);
1212 eqh->hlink = sqh;
1213 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
1214 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
1215 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
1216 sc->sc_bulk_end = sqh;
1217 uhci_add_loop(sc);
1218 }
1219
1220 /* Remove bulk QH, called at splusb(). */
1221 void
1222 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1223 {
1224 uhci_soft_qh_t *pqh;
1225
1226 DPRINTFN(10, ("uhci_remove_bulk: sqh=%p\n", sqh));
1227 uhci_rem_loop(sc);
1228 /* See comment in uhci_remove_hs_ctrl() */
1229 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
1230 sizeof(sqh->qh.qh_elink),
1231 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1232 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) {
1233 sqh->qh.qh_elink = htole32(UHCI_PTR_T);
1234 usb_syncmem(&sqh->dma,
1235 sqh->offs + offsetof(uhci_qh_t, qh_elink),
1236 sizeof(sqh->qh.qh_elink),
1237 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1238 delay(UHCI_QH_REMOVE_DELAY);
1239 }
1240 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh);
1241 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
1242 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE);
1243 pqh->hlink = sqh->hlink;
1244 pqh->qh.qh_hlink = sqh->qh.qh_hlink;
1245 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
1246 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE);
1247 delay(UHCI_QH_REMOVE_DELAY);
1248 if (sc->sc_bulk_end == sqh)
1249 sc->sc_bulk_end = pqh;
1250 }
1251
1252 Static int uhci_intr1(uhci_softc_t *);
1253
1254 int
1255 uhci_intr(void *arg)
1256 {
1257 uhci_softc_t *sc = arg;
1258
1259 if (sc->sc_dying || !device_has_power(sc->sc_dev))
1260 return (0);
1261
1262 if (sc->sc_bus.use_polling || UREAD2(sc, UHCI_INTR) == 0) {
1263 #ifdef DIAGNOSTIC
1264 DPRINTFN(16, ("uhci_intr: ignored interrupt while polling\n"));
1265 #endif
1266 return (0);
1267 }
1268
1269 return (uhci_intr1(sc));
1270 }
1271
1272 int
1273 uhci_intr1(uhci_softc_t *sc)
1274 {
1275 int status;
1276 int ack;
1277
1278 #ifdef UHCI_DEBUG
1279 if (uhcidebug > 15) {
1280 DPRINTF(("%s: uhci_intr1\n", device_xname(sc->sc_dev)));
1281 uhci_dumpregs(sc);
1282 }
1283 #endif
1284
1285 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS;
1286 if (status == 0) /* The interrupt was not for us. */
1287 return (0);
1288
1289 if (sc->sc_suspend != PWR_RESUME) {
1290 #ifdef DIAGNOSTIC
1291 printf("%s: interrupt while not operating ignored\n",
1292 device_xname(sc->sc_dev));
1293 #endif
1294 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */
1295 return (0);
1296 }
1297
1298 ack = 0;
1299 if (status & UHCI_STS_USBINT)
1300 ack |= UHCI_STS_USBINT;
1301 if (status & UHCI_STS_USBEI)
1302 ack |= UHCI_STS_USBEI;
1303 if (status & UHCI_STS_RD) {
1304 ack |= UHCI_STS_RD;
1305 #ifdef UHCI_DEBUG
1306 printf("%s: resume detect\n", device_xname(sc->sc_dev));
1307 #endif
1308 }
1309 if (status & UHCI_STS_HSE) {
1310 ack |= UHCI_STS_HSE;
1311 printf("%s: host system error\n", device_xname(sc->sc_dev));
1312 }
1313 if (status & UHCI_STS_HCPE) {
1314 ack |= UHCI_STS_HCPE;
1315 printf("%s: host controller process error\n",
1316 device_xname(sc->sc_dev));
1317 }
1318
1319 /* When HCHalted=1 and Run/Stop=0 , it is normal */
1320 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) {
1321 /* no acknowledge needed */
1322 if (!sc->sc_dying) {
1323 printf("%s: host controller halted\n",
1324 device_xname(sc->sc_dev));
1325 #ifdef UHCI_DEBUG
1326 uhci_dump_all(sc);
1327 #endif
1328 }
1329 sc->sc_dying = 1;
1330 }
1331
1332 if (!ack)
1333 return (0); /* nothing to acknowledge */
1334 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */
1335
1336 sc->sc_bus.no_intrs++;
1337 usb_schedsoftintr(&sc->sc_bus);
1338
1339 DPRINTFN(15, ("%s: uhci_intr: exit\n", device_xname(sc->sc_dev)));
1340
1341 return (1);
1342 }
1343
1344 void
1345 uhci_softintr(void *v)
1346 {
1347 struct usbd_bus *bus = v;
1348 uhci_softc_t *sc = bus->hci_private;
1349 uhci_intr_info_t *ii, *nextii;
1350
1351 DPRINTFN(10,("%s: uhci_softintr\n", device_xname(sc->sc_dev)));
1352
1353 /*
1354 * Interrupts on UHCI really suck. When the host controller
1355 * interrupts because a transfer is completed there is no
1356 * way of knowing which transfer it was. You can scan down
1357 * the TDs and QHs of the previous frame to limit the search,
1358 * but that assumes that the interrupt was not delayed by more
1359 * than 1 ms, which may not always be true (e.g. after debug
1360 * output on a slow console).
1361 * We scan all interrupt descriptors to see if any have
1362 * completed.
1363 */
1364 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = nextii) {
1365 nextii = LIST_NEXT(ii, list);
1366 uhci_check_intr(sc, ii);
1367 }
1368
1369 if (sc->sc_softwake) {
1370 sc->sc_softwake = 0;
1371 wakeup(&sc->sc_softwake);
1372 }
1373 }
1374
1375 /* Check for an interrupt. */
1376 void
1377 uhci_check_intr(uhci_softc_t *sc, uhci_intr_info_t *ii)
1378 {
1379 uhci_soft_td_t *std, *lstd;
1380 u_int32_t status;
1381
1382 DPRINTFN(15, ("uhci_check_intr: ii=%p\n", ii));
1383 #ifdef DIAGNOSTIC
1384 if (ii == NULL) {
1385 printf("uhci_check_intr: no ii? %p\n", ii);
1386 return;
1387 }
1388 #endif
1389 if (ii->xfer->status == USBD_CANCELLED ||
1390 ii->xfer->status == USBD_TIMEOUT) {
1391 DPRINTF(("uhci_check_intr: aborted xfer=%p\n", ii->xfer));
1392 return;
1393 }
1394
1395 if (ii->stdstart == NULL)
1396 return;
1397 lstd = ii->stdend;
1398 #ifdef DIAGNOSTIC
1399 if (lstd == NULL) {
1400 printf("uhci_check_intr: std==0\n");
1401 return;
1402 }
1403 #endif
1404 /*
1405 * If the last TD is still active we need to check whether there
1406 * is an error somewhere in the middle, or whether there was a
1407 * short packet (SPD and not ACTIVE).
1408 */
1409 usb_syncmem(&lstd->dma,
1410 lstd->offs + offsetof(uhci_td_t, td_status),
1411 sizeof(lstd->td.td_status),
1412 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1413 if (le32toh(lstd->td.td_status) & UHCI_TD_ACTIVE) {
1414 DPRINTFN(12, ("uhci_check_intr: active ii=%p\n", ii));
1415 for (std = ii->stdstart; std != lstd; std = std->link.std) {
1416 usb_syncmem(&std->dma,
1417 std->offs + offsetof(uhci_td_t, td_status),
1418 sizeof(std->td.td_status),
1419 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1420 status = le32toh(std->td.td_status);
1421 usb_syncmem(&std->dma,
1422 std->offs + offsetof(uhci_td_t, td_status),
1423 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD);
1424 /* If there's an active TD the xfer isn't done. */
1425 if (status & UHCI_TD_ACTIVE)
1426 break;
1427 /* Any kind of error makes the xfer done. */
1428 if (status & UHCI_TD_STALLED)
1429 goto done;
1430 /* We want short packets, and it is short: it's done */
1431 usb_syncmem(&std->dma,
1432 std->offs + offsetof(uhci_td_t, td_token),
1433 sizeof(std->td.td_token),
1434 BUS_DMASYNC_POSTWRITE);
1435 if ((status & UHCI_TD_SPD) &&
1436 UHCI_TD_GET_ACTLEN(status) <
1437 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)))
1438 goto done;
1439 }
1440 DPRINTFN(12, ("uhci_check_intr: ii=%p std=%p still active\n",
1441 ii, ii->stdstart));
1442 usb_syncmem(&lstd->dma,
1443 lstd->offs + offsetof(uhci_td_t, td_status),
1444 sizeof(lstd->td.td_status),
1445 BUS_DMASYNC_PREREAD);
1446 return;
1447 }
1448 done:
1449 DPRINTFN(12, ("uhci_check_intr: ii=%p done\n", ii));
1450 callout_stop(&ii->xfer->timeout_handle);
1451 uhci_idone(ii);
1452 }
1453
1454 /* Called at splusb() */
1455 void
1456 uhci_idone(uhci_intr_info_t *ii)
1457 {
1458 usbd_xfer_handle xfer = ii->xfer;
1459 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe;
1460 uhci_soft_td_t *std;
1461 u_int32_t status = 0, nstatus;
1462 int actlen;
1463
1464 DPRINTFN(12, ("uhci_idone: ii=%p\n", ii));
1465 #ifdef DIAGNOSTIC
1466 {
1467 int s = splhigh();
1468 if (ii->isdone) {
1469 splx(s);
1470 #ifdef UHCI_DEBUG
1471 printf("uhci_idone: ii is done!\n ");
1472 uhci_dump_ii(ii);
1473 #else
1474 printf("uhci_idone: ii=%p is done!\n", ii);
1475 #endif
1476 return;
1477 }
1478 ii->isdone = 1;
1479 splx(s);
1480 }
1481 #endif
1482
1483 if (xfer->nframes != 0) {
1484 /* Isoc transfer, do things differently. */
1485 uhci_soft_td_t **stds = upipe->u.iso.stds;
1486 int i, n, nframes, len;
1487
1488 DPRINTFN(5,("uhci_idone: ii=%p isoc ready\n", ii));
1489
1490 nframes = xfer->nframes;
1491 actlen = 0;
1492 n = UXFER(xfer)->curframe;
1493 for (i = 0; i < nframes; i++) {
1494 std = stds[n];
1495 #ifdef UHCI_DEBUG
1496 if (uhcidebug > 5) {
1497 DPRINTFN(-1,("uhci_idone: isoc TD %d\n", i));
1498 uhci_dump_td(std);
1499 }
1500 #endif
1501 if (++n >= UHCI_VFRAMELIST_COUNT)
1502 n = 0;
1503 usb_syncmem(&std->dma,
1504 std->offs + offsetof(uhci_td_t, td_status),
1505 sizeof(std->td.td_status),
1506 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1507 status = le32toh(std->td.td_status);
1508 len = UHCI_TD_GET_ACTLEN(status);
1509 xfer->frlengths[i] = len;
1510 actlen += len;
1511 }
1512 upipe->u.iso.inuse -= nframes;
1513 xfer->actlen = actlen;
1514 xfer->status = USBD_NORMAL_COMPLETION;
1515 goto end;
1516 }
1517
1518 #ifdef UHCI_DEBUG
1519 DPRINTFN(10, ("uhci_idone: ii=%p, xfer=%p, pipe=%p ready\n",
1520 ii, xfer, upipe));
1521 if (uhcidebug > 10)
1522 uhci_dump_tds(ii->stdstart);
1523 #endif
1524
1525 /* The transfer is done, compute actual length and status. */
1526 actlen = 0;
1527 for (std = ii->stdstart; std != NULL; std = std->link.std) {
1528 usb_syncmem(&std->dma, std->offs, sizeof(std->td),
1529 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1530 nstatus = le32toh(std->td.td_status);
1531 if (nstatus & UHCI_TD_ACTIVE)
1532 break;
1533
1534 status = nstatus;
1535 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) !=
1536 UHCI_TD_PID_SETUP)
1537 actlen += UHCI_TD_GET_ACTLEN(status);
1538 else {
1539 /*
1540 * UHCI will report CRCTO in addition to a STALL or NAK
1541 * for a SETUP transaction. See section 3.2.2, "TD
1542 * CONTROL AND STATUS".
1543 */
1544 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK))
1545 status &= ~UHCI_TD_CRCTO;
1546 }
1547 }
1548 /* If there are left over TDs we need to update the toggle. */
1549 if (std != NULL)
1550 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token));
1551
1552 status &= UHCI_TD_ERROR;
1553 DPRINTFN(10, ("uhci_idone: actlen=%d, status=0x%x\n",
1554 actlen, status));
1555 xfer->actlen = actlen;
1556 if (status != 0) {
1557 #ifdef UHCI_DEBUG
1558 char sbuf[128];
1559
1560 snprintb(sbuf, sizeof(sbuf),
1561 "\20\22BITSTUFF\23CRCTO\24NAK\25"
1562 "BABBLE\26DBUFFER\27STALLED\30ACTIVE",(u_int32_t)status);
1563
1564 DPRINTFN((status == UHCI_TD_STALLED)*10,
1565 ("uhci_idone: error, addr=%d, endpt=0x%02x, "
1566 "status 0x%s\n",
1567 xfer->pipe->device->address,
1568 xfer->pipe->endpoint->edesc->bEndpointAddress,
1569 sbuf));
1570 #endif
1571
1572 if (status == UHCI_TD_STALLED)
1573 xfer->status = USBD_STALLED;
1574 else
1575 xfer->status = USBD_IOERROR; /* more info XXX */
1576 } else {
1577 xfer->status = USBD_NORMAL_COMPLETION;
1578 }
1579
1580 end:
1581 usb_transfer_complete(xfer);
1582 DPRINTFN(12, ("uhci_idone: ii=%p done\n", ii));
1583 }
1584
1585 /*
1586 * Called when a request does not complete.
1587 */
1588 void
1589 uhci_timeout(void *addr)
1590 {
1591 uhci_intr_info_t *ii = addr;
1592 struct uhci_xfer *uxfer = UXFER(ii->xfer);
1593 struct uhci_pipe *upipe = (struct uhci_pipe *)uxfer->xfer.pipe;
1594 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private;
1595
1596 DPRINTF(("uhci_timeout: uxfer=%p\n", uxfer));
1597
1598 if (sc->sc_dying) {
1599 uhci_abort_xfer(&uxfer->xfer, USBD_TIMEOUT);
1600 return;
1601 }
1602
1603 /* Execute the abort in a process context. */
1604 usb_init_task(&uxfer->abort_task, uhci_timeout_task, ii->xfer);
1605 usb_add_task(uxfer->xfer.pipe->device, &uxfer->abort_task,
1606 USB_TASKQ_HC);
1607 }
1608
1609 void
1610 uhci_timeout_task(void *addr)
1611 {
1612 usbd_xfer_handle xfer = addr;
1613 int s;
1614
1615 DPRINTF(("uhci_timeout_task: xfer=%p\n", xfer));
1616
1617 s = splusb();
1618 uhci_abort_xfer(xfer, USBD_TIMEOUT);
1619 splx(s);
1620 }
1621
1622 /*
1623 * Wait here until controller claims to have an interrupt.
1624 * Then call uhci_intr and return. Use timeout to avoid waiting
1625 * too long.
1626 * Only used during boot when interrupts are not enabled yet.
1627 */
1628 void
1629 uhci_waitintr(uhci_softc_t *sc, usbd_xfer_handle xfer)
1630 {
1631 int timo = xfer->timeout;
1632 uhci_intr_info_t *ii;
1633
1634 DPRINTFN(10,("uhci_waitintr: timeout = %dms\n", timo));
1635
1636 xfer->status = USBD_IN_PROGRESS;
1637 for (; timo >= 0; timo--) {
1638 usb_delay_ms(&sc->sc_bus, 1);
1639 DPRINTFN(20,("uhci_waitintr: 0x%04x\n", UREAD2(sc, UHCI_STS)));
1640 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) {
1641 uhci_intr1(sc);
1642 if (xfer->status != USBD_IN_PROGRESS)
1643 return;
1644 }
1645 }
1646
1647 /* Timeout */
1648 DPRINTF(("uhci_waitintr: timeout\n"));
1649 for (ii = LIST_FIRST(&sc->sc_intrhead);
1650 ii != NULL && ii->xfer != xfer;
1651 ii = LIST_NEXT(ii, list))
1652 ;
1653 #ifdef DIAGNOSTIC
1654 if (ii == NULL)
1655 panic("uhci_waitintr: lost intr_info");
1656 #endif
1657 uhci_idone(ii);
1658 }
1659
1660 void
1661 uhci_poll(struct usbd_bus *bus)
1662 {
1663 uhci_softc_t *sc = bus->hci_private;
1664
1665 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT)
1666 uhci_intr1(sc);
1667 }
1668
1669 void
1670 uhci_reset(uhci_softc_t *sc)
1671 {
1672 int n;
1673
1674 UHCICMD(sc, UHCI_CMD_HCRESET);
1675 /* The reset bit goes low when the controller is done. */
1676 for (n = 0; n < UHCI_RESET_TIMEOUT &&
1677 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++)
1678 usb_delay_ms(&sc->sc_bus, 1);
1679 if (n >= UHCI_RESET_TIMEOUT)
1680 printf("%s: controller did not reset\n",
1681 device_xname(sc->sc_dev));
1682 }
1683
1684 usbd_status
1685 uhci_run(uhci_softc_t *sc, int run)
1686 {
1687 int s, n, running;
1688 u_int16_t cmd;
1689
1690 run = run != 0;
1691 s = splhardusb();
1692 DPRINTF(("uhci_run: setting run=%d\n", run));
1693 cmd = UREAD2(sc, UHCI_CMD);
1694 if (run)
1695 cmd |= UHCI_CMD_RS;
1696 else
1697 cmd &= ~UHCI_CMD_RS;
1698 UHCICMD(sc, cmd);
1699 for(n = 0; n < 10; n++) {
1700 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH);
1701 /* return when we've entered the state we want */
1702 if (run == running) {
1703 splx(s);
1704 DPRINTF(("uhci_run: done cmd=0x%x sts=0x%x\n",
1705 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS)));
1706 return (USBD_NORMAL_COMPLETION);
1707 }
1708 usb_delay_ms(&sc->sc_bus, 1);
1709 }
1710 splx(s);
1711 printf("%s: cannot %s\n", device_xname(sc->sc_dev),
1712 run ? "start" : "stop");
1713 return (USBD_IOERROR);
1714 }
1715
1716 /*
1717 * Memory management routines.
1718 * uhci_alloc_std allocates TDs
1719 * uhci_alloc_sqh allocates QHs
1720 * These two routines do their own free list management,
1721 * partly for speed, partly because allocating DMAable memory
1722 * has page size granularaity so much memory would be wasted if
1723 * only one TD/QH (32 bytes) was placed in each allocated chunk.
1724 */
1725
1726 uhci_soft_td_t *
1727 uhci_alloc_std(uhci_softc_t *sc)
1728 {
1729 uhci_soft_td_t *std;
1730 usbd_status err;
1731 int i, offs;
1732 usb_dma_t dma;
1733
1734 if (sc->sc_freetds == NULL) {
1735 DPRINTFN(2,("uhci_alloc_std: allocating chunk\n"));
1736 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK,
1737 UHCI_TD_ALIGN, &dma);
1738 if (err)
1739 return (0);
1740 for(i = 0; i < UHCI_STD_CHUNK; i++) {
1741 offs = i * UHCI_STD_SIZE;
1742 std = KERNADDR(&dma, offs);
1743 std->physaddr = DMAADDR(&dma, offs);
1744 std->dma = dma;
1745 std->offs = offs;
1746 std->link.std = sc->sc_freetds;
1747 sc->sc_freetds = std;
1748 }
1749 }
1750 std = sc->sc_freetds;
1751 sc->sc_freetds = std->link.std;
1752 memset(&std->td, 0, sizeof(uhci_td_t));
1753 return std;
1754 }
1755
1756 void
1757 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std)
1758 {
1759 #ifdef DIAGNOSTIC
1760 #define TD_IS_FREE 0x12345678
1761 if (le32toh(std->td.td_token) == TD_IS_FREE) {
1762 printf("uhci_free_std: freeing free TD %p\n", std);
1763 return;
1764 }
1765 std->td.td_token = htole32(TD_IS_FREE);
1766 #endif
1767 std->link.std = sc->sc_freetds;
1768 sc->sc_freetds = std;
1769 }
1770
1771 uhci_soft_qh_t *
1772 uhci_alloc_sqh(uhci_softc_t *sc)
1773 {
1774 uhci_soft_qh_t *sqh;
1775 usbd_status err;
1776 int i, offs;
1777 usb_dma_t dma;
1778
1779 if (sc->sc_freeqhs == NULL) {
1780 DPRINTFN(2, ("uhci_alloc_sqh: allocating chunk\n"));
1781 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK,
1782 UHCI_QH_ALIGN, &dma);
1783 if (err)
1784 return (0);
1785 for(i = 0; i < UHCI_SQH_CHUNK; i++) {
1786 offs = i * UHCI_SQH_SIZE;
1787 sqh = KERNADDR(&dma, offs);
1788 sqh->physaddr = DMAADDR(&dma, offs);
1789 sqh->dma = dma;
1790 sqh->offs = offs;
1791 sqh->hlink = sc->sc_freeqhs;
1792 sc->sc_freeqhs = sqh;
1793 }
1794 }
1795 sqh = sc->sc_freeqhs;
1796 sc->sc_freeqhs = sqh->hlink;
1797 memset(&sqh->qh, 0, sizeof(uhci_qh_t));
1798 return (sqh);
1799 }
1800
1801 void
1802 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
1803 {
1804 sqh->hlink = sc->sc_freeqhs;
1805 sc->sc_freeqhs = sqh;
1806 }
1807
1808 void
1809 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std,
1810 uhci_soft_td_t *stdend)
1811 {
1812 uhci_soft_td_t *p;
1813
1814 /*
1815 * to avoid race condition with the controller which may be looking
1816 * at this chain, we need to first invalidate all links, and
1817 * then wait for the controller to move to another queue
1818 */
1819 for (p = std; p != stdend; p = p->link.std) {
1820 usb_syncmem(&p->dma,
1821 p->offs + offsetof(uhci_td_t, td_link),
1822 sizeof(p->td.td_link),
1823 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1824 if ((p->td.td_link & UHCI_PTR_T) == 0) {
1825 p->td.td_link = UHCI_PTR_T;
1826 usb_syncmem(&p->dma,
1827 p->offs + offsetof(uhci_td_t, td_link),
1828 sizeof(p->td.td_link),
1829 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1830 }
1831 }
1832 delay(UHCI_QH_REMOVE_DELAY);
1833
1834 for (; std != stdend; std = p) {
1835 p = std->link.std;
1836 uhci_free_std(sc, std);
1837 }
1838 }
1839
1840 usbd_status
1841 uhci_alloc_std_chain(struct uhci_pipe *upipe, uhci_softc_t *sc, int len,
1842 int rd, u_int16_t flags, usb_dma_t *dma,
1843 uhci_soft_td_t **sp, uhci_soft_td_t **ep)
1844 {
1845 uhci_soft_td_t *p, *lastp;
1846 uhci_physaddr_t lastlink;
1847 int i, ntd, l, tog, maxp;
1848 u_int32_t status;
1849 int addr = upipe->pipe.device->address;
1850 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress;
1851
1852 DPRINTFN(8, ("uhci_alloc_std_chain: addr=%d endpt=%d len=%d speed=%d "
1853 "flags=0x%x\n", addr, UE_GET_ADDR(endpt), len,
1854 upipe->pipe.device->speed, flags));
1855 maxp = UGETW(upipe->pipe.endpoint->edesc->wMaxPacketSize);
1856 if (maxp == 0) {
1857 printf("uhci_alloc_std_chain: maxp=0\n");
1858 return (USBD_INVAL);
1859 }
1860 ntd = (len + maxp - 1) / maxp;
1861 if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0)
1862 ntd++;
1863 DPRINTFN(10, ("uhci_alloc_std_chain: maxp=%d ntd=%d\n", maxp, ntd));
1864 if (ntd == 0) {
1865 *sp = *ep = 0;
1866 DPRINTFN(-1,("uhci_alloc_std_chain: ntd=0\n"));
1867 return (USBD_NORMAL_COMPLETION);
1868 }
1869 tog = upipe->nexttoggle;
1870 if (ntd % 2 == 0)
1871 tog ^= 1;
1872 upipe->nexttoggle = tog ^ 1;
1873 lastp = NULL;
1874 lastlink = UHCI_PTR_T;
1875 ntd--;
1876 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE);
1877 if (upipe->pipe.device->speed == USB_SPEED_LOW)
1878 status |= UHCI_TD_LS;
1879 if (flags & USBD_SHORT_XFER_OK)
1880 status |= UHCI_TD_SPD;
1881 usb_syncmem(dma, 0, len,
1882 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
1883 for (i = ntd; i >= 0; i--) {
1884 p = uhci_alloc_std(sc);
1885 if (p == NULL) {
1886 KASSERT(lastp != NULL);
1887 uhci_free_std_chain(sc, lastp, NULL);
1888 return (USBD_NOMEM);
1889 }
1890 p->link.std = lastp;
1891 p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD);
1892 lastp = p;
1893 lastlink = p->physaddr;
1894 p->td.td_status = htole32(status);
1895 if (i == ntd) {
1896 /* last TD */
1897 l = len % maxp;
1898 if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER))
1899 l = maxp;
1900 *ep = p;
1901 } else
1902 l = maxp;
1903 p->td.td_token =
1904 htole32(rd ? UHCI_TD_IN (l, endpt, addr, tog) :
1905 UHCI_TD_OUT(l, endpt, addr, tog));
1906 p->td.td_buffer = htole32(DMAADDR(dma, i * maxp));
1907 usb_syncmem(&p->dma, p->offs, sizeof(p->td),
1908 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1909 tog ^= 1;
1910 }
1911 *sp = lastp;
1912 DPRINTFN(10, ("uhci_alloc_std_chain: nexttog=%d\n",
1913 upipe->nexttoggle));
1914 return (USBD_NORMAL_COMPLETION);
1915 }
1916
1917 void
1918 uhci_device_clear_toggle(usbd_pipe_handle pipe)
1919 {
1920 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;
1921 upipe->nexttoggle = 0;
1922 }
1923
1924 void
1925 uhci_noop(usbd_pipe_handle pipe)
1926 {
1927 }
1928
1929 usbd_status
1930 uhci_device_bulk_transfer(usbd_xfer_handle xfer)
1931 {
1932 usbd_status err;
1933
1934 /* Insert last in queue. */
1935 err = usb_insert_transfer(xfer);
1936 if (err)
1937 return (err);
1938
1939 /*
1940 * Pipe isn't running (otherwise err would be USBD_INPROG),
1941 * so start it first.
1942 */
1943 return (uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
1944 }
1945
1946 usbd_status
1947 uhci_device_bulk_start(usbd_xfer_handle xfer)
1948 {
1949 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe;
1950 usbd_device_handle dev = upipe->pipe.device;
1951 uhci_softc_t *sc = dev->bus->hci_private;
1952 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
1953 uhci_soft_td_t *data, *dataend;
1954 uhci_soft_qh_t *sqh;
1955 usbd_status err;
1956 int len, isread, endpt;
1957 int s;
1958
1959 DPRINTFN(3, ("uhci_device_bulk_start: xfer=%p len=%d flags=%d ii=%p\n",
1960 xfer, xfer->length, xfer->flags, ii));
1961
1962 if (sc->sc_dying)
1963 return (USBD_IOERROR);
1964
1965 #ifdef DIAGNOSTIC
1966 if (xfer->rqflags & URQ_REQUEST)
1967 panic("uhci_device_bulk_transfer: a request");
1968 #endif
1969
1970 len = xfer->length;
1971 endpt = upipe->pipe.endpoint->edesc->bEndpointAddress;
1972 isread = UE_GET_DIR(endpt) == UE_DIR_IN;
1973 sqh = upipe->u.bulk.sqh;
1974
1975 upipe->u.bulk.isread = isread;
1976 upipe->u.bulk.length = len;
1977
1978 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->flags,
1979 &xfer->dmabuf, &data, &dataend);
1980 if (err)
1981 return (err);
1982 dataend->td.td_status |= htole32(UHCI_TD_IOC);
1983 usb_syncmem(&dataend->dma,
1984 dataend->offs + offsetof(uhci_td_t, td_status),
1985 sizeof(dataend->td.td_status),
1986 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1987
1988
1989 #ifdef UHCI_DEBUG
1990 if (uhcidebug > 8) {
1991 DPRINTF(("uhci_device_bulk_transfer: data(1)\n"));
1992 uhci_dump_tds(data);
1993 }
1994 #endif
1995
1996 /* Set up interrupt info. */
1997 ii->xfer = xfer;
1998 ii->stdstart = data;
1999 ii->stdend = dataend;
2000 #ifdef DIAGNOSTIC
2001 if (!ii->isdone) {
2002 printf("uhci_device_bulk_transfer: not done, ii=%p\n", ii);
2003 }
2004 ii->isdone = 0;
2005 #endif
2006
2007 sqh->elink = data;
2008 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD);
2009 /* uhci_add_bulk() will do usb_syncmem(sqh) */
2010
2011 s = splusb();
2012 uhci_add_bulk(sc, sqh);
2013 uhci_add_intr_info(sc, ii);
2014
2015 if (xfer->timeout && !sc->sc_bus.use_polling) {
2016 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout),
2017 uhci_timeout, ii);
2018 }
2019 xfer->status = USBD_IN_PROGRESS;
2020 splx(s);
2021
2022 #ifdef UHCI_DEBUG
2023 if (uhcidebug > 10) {
2024 DPRINTF(("uhci_device_bulk_transfer: data(2)\n"));
2025 uhci_dump_tds(data);
2026 }
2027 #endif
2028
2029 if (sc->sc_bus.use_polling)
2030 uhci_waitintr(sc, xfer);
2031
2032 return (USBD_IN_PROGRESS);
2033 }
2034
2035 /* Abort a device bulk request. */
2036 void
2037 uhci_device_bulk_abort(usbd_xfer_handle xfer)
2038 {
2039 DPRINTF(("uhci_device_bulk_abort:\n"));
2040 uhci_abort_xfer(xfer, USBD_CANCELLED);
2041 }
2042
2043 /*
2044 * Abort a device request.
2045 * If this routine is called at splusb() it guarantees that the request
2046 * will be removed from the hardware scheduling and that the callback
2047 * for it will be called with USBD_CANCELLED status.
2048 * It's impossible to guarantee that the requested transfer will not
2049 * have happened since the hardware runs concurrently.
2050 * If the transaction has already happened we rely on the ordinary
2051 * interrupt processing to process it.
2052 */
2053 void
2054 uhci_abort_xfer(usbd_xfer_handle xfer, usbd_status status)
2055 {
2056 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
2057 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe;
2058 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private;
2059 uhci_soft_td_t *std;
2060 int s;
2061 int wake;
2062
2063 DPRINTFN(1,("uhci_abort_xfer: xfer=%p, status=%d\n", xfer, status));
2064
2065 if (sc->sc_dying) {
2066 /* If we're dying, just do the software part. */
2067 s = splusb();
2068 xfer->status = status; /* make software ignore it */
2069 callout_stop(&xfer->timeout_handle);
2070 usb_transfer_complete(xfer);
2071 splx(s);
2072 return;
2073 }
2074
2075 if (cpu_intr_p() || cpu_softintr_p())
2076 panic("uhci_abort_xfer: not in process context");
2077
2078 /*
2079 * If an abort is already in progress then just wait for it to
2080 * complete and return.
2081 */
2082 if (xfer->hcflags & UXFER_ABORTING) {
2083 DPRINTFN(2, ("uhci_abort_xfer: already aborting\n"));
2084 #ifdef DIAGNOSTIC
2085 if (status == USBD_TIMEOUT)
2086 printf("uhci_abort_xfer: TIMEOUT while aborting\n");
2087 #endif
2088 /* Override the status which might be USBD_TIMEOUT. */
2089 xfer->status = status;
2090 DPRINTFN(2, ("uhci_abort_xfer: waiting for abort to finish\n"));
2091 xfer->hcflags |= UXFER_ABORTWAIT;
2092 while (xfer->hcflags & UXFER_ABORTING)
2093 tsleep(&xfer->hcflags, PZERO, "uhciaw", 0);
2094 return;
2095 }
2096 xfer->hcflags |= UXFER_ABORTING;
2097
2098 /*
2099 * Step 1: Make interrupt routine and hardware ignore xfer.
2100 */
2101 s = splusb();
2102 xfer->status = status; /* make software ignore it */
2103 callout_stop(&xfer->timeout_handle);
2104 DPRINTFN(1,("uhci_abort_xfer: stop ii=%p\n", ii));
2105 for (std = ii->stdstart; std != NULL; std = std->link.std) {
2106 usb_syncmem(&std->dma,
2107 std->offs + offsetof(uhci_td_t, td_status),
2108 sizeof(std->td.td_status),
2109 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2110 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC));
2111 usb_syncmem(&std->dma,
2112 std->offs + offsetof(uhci_td_t, td_status),
2113 sizeof(std->td.td_status),
2114 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2115 }
2116 splx(s);
2117
2118 /*
2119 * Step 2: Wait until we know hardware has finished any possible
2120 * use of the xfer. Also make sure the soft interrupt routine
2121 * has run.
2122 */
2123 usb_delay_ms(upipe->pipe.device->bus, 2); /* Hardware finishes in 1ms */
2124 s = splusb();
2125 sc->sc_softwake = 1;
2126 usb_schedsoftintr(&sc->sc_bus);
2127 DPRINTFN(1,("uhci_abort_xfer: tsleep\n"));
2128 tsleep(&sc->sc_softwake, PZERO, "uhciab", 0);
2129 splx(s);
2130
2131 /*
2132 * Step 3: Execute callback.
2133 */
2134 DPRINTFN(1,("uhci_abort_xfer: callback\n"));
2135 s = splusb();
2136 #ifdef DIAGNOSTIC
2137 ii->isdone = 1;
2138 #endif
2139 wake = xfer->hcflags & UXFER_ABORTWAIT;
2140 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT);
2141 usb_transfer_complete(xfer);
2142 if (wake)
2143 wakeup(&xfer->hcflags);
2144 splx(s);
2145 }
2146
2147 /* Close a device bulk pipe. */
2148 void
2149 uhci_device_bulk_close(usbd_pipe_handle pipe)
2150 {
2151 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;
2152 usbd_device_handle dev = upipe->pipe.device;
2153 uhci_softc_t *sc = dev->bus->hci_private;
2154
2155 uhci_free_sqh(sc, upipe->u.bulk.sqh);
2156
2157 pipe->endpoint->datatoggle = upipe->nexttoggle;
2158 }
2159
2160 usbd_status
2161 uhci_device_ctrl_transfer(usbd_xfer_handle xfer)
2162 {
2163 usbd_status err;
2164
2165 /* Insert last in queue. */
2166 err = usb_insert_transfer(xfer);
2167 if (err)
2168 return (err);
2169
2170 /*
2171 * Pipe isn't running (otherwise err would be USBD_INPROG),
2172 * so start it first.
2173 */
2174 return (uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
2175 }
2176
2177 usbd_status
2178 uhci_device_ctrl_start(usbd_xfer_handle xfer)
2179 {
2180 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private;
2181 usbd_status err;
2182
2183 if (sc->sc_dying)
2184 return (USBD_IOERROR);
2185
2186 #ifdef DIAGNOSTIC
2187 if (!(xfer->rqflags & URQ_REQUEST))
2188 panic("uhci_device_ctrl_transfer: not a request");
2189 #endif
2190
2191 err = uhci_device_request(xfer);
2192 if (err)
2193 return (err);
2194
2195 if (sc->sc_bus.use_polling)
2196 uhci_waitintr(sc, xfer);
2197 return (USBD_IN_PROGRESS);
2198 }
2199
2200 usbd_status
2201 uhci_device_intr_transfer(usbd_xfer_handle xfer)
2202 {
2203 usbd_status err;
2204
2205 /* Insert last in queue. */
2206 err = usb_insert_transfer(xfer);
2207 if (err)
2208 return (err);
2209
2210 /*
2211 * Pipe isn't running (otherwise err would be USBD_INPROG),
2212 * so start it first.
2213 */
2214 return (uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
2215 }
2216
2217 usbd_status
2218 uhci_device_intr_start(usbd_xfer_handle xfer)
2219 {
2220 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe;
2221 usbd_device_handle dev = upipe->pipe.device;
2222 uhci_softc_t *sc = dev->bus->hci_private;
2223 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
2224 uhci_soft_td_t *data, *dataend;
2225 uhci_soft_qh_t *sqh;
2226 usbd_status err;
2227 int isread, endpt;
2228 int i, s;
2229
2230 if (sc->sc_dying)
2231 return (USBD_IOERROR);
2232
2233 DPRINTFN(3,("uhci_device_intr_transfer: xfer=%p len=%d flags=%d\n",
2234 xfer, xfer->length, xfer->flags));
2235
2236 #ifdef DIAGNOSTIC
2237 if (xfer->rqflags & URQ_REQUEST)
2238 panic("uhci_device_intr_transfer: a request");
2239 #endif
2240
2241 endpt = upipe->pipe.endpoint->edesc->bEndpointAddress;
2242 isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2243
2244 upipe->u.intr.isread = isread;
2245
2246 err = uhci_alloc_std_chain(upipe, sc, xfer->length, isread,
2247 xfer->flags, &xfer->dmabuf, &data,
2248 &dataend);
2249 if (err)
2250 return (err);
2251 dataend->td.td_status |= htole32(UHCI_TD_IOC);
2252 usb_syncmem(&dataend->dma,
2253 dataend->offs + offsetof(uhci_td_t, td_status),
2254 sizeof(dataend->td.td_status),
2255 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2256
2257 #ifdef UHCI_DEBUG
2258 if (uhcidebug > 10) {
2259 DPRINTF(("uhci_device_intr_transfer: data(1)\n"));
2260 uhci_dump_tds(data);
2261 uhci_dump_qh(upipe->u.intr.qhs[0]);
2262 }
2263 #endif
2264
2265 s = splusb();
2266 /* Set up interrupt info. */
2267 ii->xfer = xfer;
2268 ii->stdstart = data;
2269 ii->stdend = dataend;
2270 #ifdef DIAGNOSTIC
2271 if (!ii->isdone) {
2272 printf("uhci_device_intr_transfer: not done, ii=%p\n", ii);
2273 }
2274 ii->isdone = 0;
2275 #endif
2276
2277 DPRINTFN(10,("uhci_device_intr_transfer: qhs[0]=%p\n",
2278 upipe->u.intr.qhs[0]));
2279 for (i = 0; i < upipe->u.intr.npoll; i++) {
2280 sqh = upipe->u.intr.qhs[i];
2281 sqh->elink = data;
2282 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD);
2283 usb_syncmem(&sqh->dma,
2284 sqh->offs + offsetof(uhci_qh_t, qh_elink),
2285 sizeof(sqh->qh.qh_elink),
2286 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2287 }
2288 uhci_add_intr_info(sc, ii);
2289 xfer->status = USBD_IN_PROGRESS;
2290 splx(s);
2291
2292 #ifdef UHCI_DEBUG
2293 if (uhcidebug > 10) {
2294 DPRINTF(("uhci_device_intr_transfer: data(2)\n"));
2295 uhci_dump_tds(data);
2296 uhci_dump_qh(upipe->u.intr.qhs[0]);
2297 }
2298 #endif
2299
2300 return (USBD_IN_PROGRESS);
2301 }
2302
2303 /* Abort a device control request. */
2304 void
2305 uhci_device_ctrl_abort(usbd_xfer_handle xfer)
2306 {
2307 DPRINTF(("uhci_device_ctrl_abort:\n"));
2308 uhci_abort_xfer(xfer, USBD_CANCELLED);
2309 }
2310
2311 /* Close a device control pipe. */
2312 void
2313 uhci_device_ctrl_close(usbd_pipe_handle pipe)
2314 {
2315 }
2316
2317 /* Abort a device interrupt request. */
2318 void
2319 uhci_device_intr_abort(usbd_xfer_handle xfer)
2320 {
2321 DPRINTFN(1,("uhci_device_intr_abort: xfer=%p\n", xfer));
2322 if (xfer->pipe->intrxfer == xfer) {
2323 DPRINTFN(1,("uhci_device_intr_abort: remove\n"));
2324 xfer->pipe->intrxfer = NULL;
2325 }
2326 uhci_abort_xfer(xfer, USBD_CANCELLED);
2327 }
2328
2329 /* Close a device interrupt pipe. */
2330 void
2331 uhci_device_intr_close(usbd_pipe_handle pipe)
2332 {
2333 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;
2334 uhci_softc_t *sc = pipe->device->bus->hci_private;
2335 int i, npoll;
2336 int s;
2337
2338 /* Unlink descriptors from controller data structures. */
2339 npoll = upipe->u.intr.npoll;
2340 s = splusb();
2341 for (i = 0; i < npoll; i++)
2342 uhci_remove_intr(sc, upipe->u.intr.qhs[i]);
2343 splx(s);
2344
2345 /*
2346 * We now have to wait for any activity on the physical
2347 * descriptors to stop.
2348 */
2349 usb_delay_ms(&sc->sc_bus, 2);
2350
2351 for(i = 0; i < npoll; i++)
2352 uhci_free_sqh(sc, upipe->u.intr.qhs[i]);
2353 free(upipe->u.intr.qhs, M_USBHC);
2354
2355 /* XXX free other resources */
2356 }
2357
2358 usbd_status
2359 uhci_device_request(usbd_xfer_handle xfer)
2360 {
2361 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe;
2362 usb_device_request_t *req = &xfer->request;
2363 usbd_device_handle dev = upipe->pipe.device;
2364 uhci_softc_t *sc = dev->bus->hci_private;
2365 int addr = dev->address;
2366 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress;
2367 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
2368 uhci_soft_td_t *setup, *data, *stat, *next, *dataend;
2369 uhci_soft_qh_t *sqh;
2370 int len;
2371 u_int32_t ls;
2372 usbd_status err;
2373 int isread;
2374 int s;
2375
2376 DPRINTFN(3,("uhci_device_control type=0x%02x, request=0x%02x, "
2377 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n",
2378 req->bmRequestType, req->bRequest, UGETW(req->wValue),
2379 UGETW(req->wIndex), UGETW(req->wLength),
2380 addr, endpt));
2381
2382 ls = dev->speed == USB_SPEED_LOW ? UHCI_TD_LS : 0;
2383 isread = req->bmRequestType & UT_READ;
2384 len = UGETW(req->wLength);
2385
2386 setup = upipe->u.ctl.setup;
2387 stat = upipe->u.ctl.stat;
2388 sqh = upipe->u.ctl.sqh;
2389
2390 /* Set up data transaction */
2391 if (len != 0) {
2392 upipe->nexttoggle = 1;
2393 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->flags,
2394 &xfer->dmabuf, &data, &dataend);
2395 if (err)
2396 return (err);
2397 next = data;
2398 dataend->link.std = stat;
2399 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_VF | UHCI_PTR_TD);
2400 usb_syncmem(&dataend->dma,
2401 dataend->offs + offsetof(uhci_td_t, td_link),
2402 sizeof(dataend->td.td_link),
2403 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2404 } else {
2405 next = stat;
2406 }
2407 upipe->u.ctl.length = len;
2408
2409 memcpy(KERNADDR(&upipe->u.ctl.reqdma, 0), req, sizeof *req);
2410 usb_syncmem(&upipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE);
2411
2412 setup->link.std = next;
2413 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_VF | UHCI_PTR_TD);
2414 setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls |
2415 UHCI_TD_ACTIVE);
2416 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof *req, endpt, addr));
2417 setup->td.td_buffer = htole32(DMAADDR(&upipe->u.ctl.reqdma, 0));
2418 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td),
2419 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2420
2421 stat->link.std = NULL;
2422 stat->td.td_link = htole32(UHCI_PTR_T);
2423 stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls |
2424 UHCI_TD_ACTIVE | UHCI_TD_IOC);
2425 stat->td.td_token =
2426 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) :
2427 UHCI_TD_IN (0, endpt, addr, 1));
2428 stat->td.td_buffer = htole32(0);
2429 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td),
2430 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2431
2432 #ifdef UHCI_DEBUG
2433 if (uhcidebug > 10) {
2434 DPRINTF(("uhci_device_request: before transfer\n"));
2435 uhci_dump_tds(setup);
2436 }
2437 #endif
2438
2439 /* Set up interrupt info. */
2440 ii->xfer = xfer;
2441 ii->stdstart = setup;
2442 ii->stdend = stat;
2443 #ifdef DIAGNOSTIC
2444 if (!ii->isdone) {
2445 printf("uhci_device_request: not done, ii=%p\n", ii);
2446 }
2447 ii->isdone = 0;
2448 #endif
2449
2450 sqh->elink = setup;
2451 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD);
2452 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */
2453
2454 s = splusb();
2455 if (dev->speed == USB_SPEED_LOW)
2456 uhci_add_ls_ctrl(sc, sqh);
2457 else
2458 uhci_add_hs_ctrl(sc, sqh);
2459 uhci_add_intr_info(sc, ii);
2460 #ifdef UHCI_DEBUG
2461 if (uhcidebug > 12) {
2462 uhci_soft_td_t *std;
2463 uhci_soft_qh_t *xqh;
2464 uhci_soft_qh_t *sxqh;
2465 int maxqh = 0;
2466 uhci_physaddr_t link;
2467 DPRINTF(("uhci_enter_ctl_q: follow from [0]\n"));
2468 for (std = sc->sc_vframes[0].htd, link = 0;
2469 (link & UHCI_PTR_QH) == 0;
2470 std = std->link.std) {
2471 link = le32toh(std->td.td_link);
2472 uhci_dump_td(std);
2473 }
2474 sxqh = (uhci_soft_qh_t *)std;
2475 uhci_dump_qh(sxqh);
2476 for (xqh = sxqh;
2477 xqh != NULL;
2478 xqh = (maxqh++ == 5 || xqh->hlink == sxqh ||
2479 xqh->hlink == xqh ? NULL : xqh->hlink)) {
2480 uhci_dump_qh(xqh);
2481 }
2482 DPRINTF(("Enqueued QH:\n"));
2483 uhci_dump_qh(sqh);
2484 uhci_dump_tds(sqh->elink);
2485 }
2486 #endif
2487 if (xfer->timeout && !sc->sc_bus.use_polling) {
2488 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout),
2489 uhci_timeout, ii);
2490 }
2491 xfer->status = USBD_IN_PROGRESS;
2492 splx(s);
2493
2494 return (USBD_NORMAL_COMPLETION);
2495 }
2496
2497 usbd_status
2498 uhci_device_isoc_transfer(usbd_xfer_handle xfer)
2499 {
2500 usbd_status err;
2501
2502 DPRINTFN(5,("uhci_device_isoc_transfer: xfer=%p\n", xfer));
2503
2504 /* Put it on our queue, */
2505 err = usb_insert_transfer(xfer);
2506
2507 /* bail out on error, */
2508 if (err && err != USBD_IN_PROGRESS)
2509 return (err);
2510
2511 /* XXX should check inuse here */
2512
2513 /* insert into schedule, */
2514 uhci_device_isoc_enter(xfer);
2515
2516 /* and start if the pipe wasn't running */
2517 if (!err)
2518 uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue));
2519
2520 return (err);
2521 }
2522
2523 void
2524 uhci_device_isoc_enter(usbd_xfer_handle xfer)
2525 {
2526 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe;
2527 usbd_device_handle dev = upipe->pipe.device;
2528 uhci_softc_t *sc = dev->bus->hci_private;
2529 struct iso *iso = &upipe->u.iso;
2530 uhci_soft_td_t *std;
2531 u_int32_t buf, len, status, offs;
2532 int s, i, next, nframes;
2533 int rd = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN;
2534
2535 DPRINTFN(5,("uhci_device_isoc_enter: used=%d next=%d xfer=%p "
2536 "nframes=%d\n",
2537 iso->inuse, iso->next, xfer, xfer->nframes));
2538
2539 if (sc->sc_dying)
2540 return;
2541
2542 if (xfer->status == USBD_IN_PROGRESS) {
2543 /* This request has already been entered into the frame list */
2544 printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer);
2545 /* XXX */
2546 }
2547
2548 #ifdef DIAGNOSTIC
2549 if (iso->inuse >= UHCI_VFRAMELIST_COUNT)
2550 printf("uhci_device_isoc_enter: overflow!\n");
2551 #endif
2552
2553 next = iso->next;
2554 if (next == -1) {
2555 /* Not in use yet, schedule it a few frames ahead. */
2556 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT;
2557 DPRINTFN(2,("uhci_device_isoc_enter: start next=%d\n", next));
2558 }
2559
2560 xfer->status = USBD_IN_PROGRESS;
2561 UXFER(xfer)->curframe = next;
2562
2563 buf = DMAADDR(&xfer->dmabuf, 0);
2564 offs = 0;
2565 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) |
2566 UHCI_TD_ACTIVE |
2567 UHCI_TD_IOS);
2568 nframes = xfer->nframes;
2569 s = splusb();
2570 for (i = 0; i < nframes; i++) {
2571 std = iso->stds[next];
2572 if (++next >= UHCI_VFRAMELIST_COUNT)
2573 next = 0;
2574 len = xfer->frlengths[i];
2575 std->td.td_buffer = htole32(buf);
2576 usb_syncmem(&xfer->dmabuf, offs, len,
2577 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
2578 if (i == nframes - 1)
2579 status |= UHCI_TD_IOC;
2580 std->td.td_status = htole32(status);
2581 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK);
2582 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len));
2583 usb_syncmem(&std->dma, std->offs, sizeof(std->td),
2584 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2585 #ifdef UHCI_DEBUG
2586 if (uhcidebug > 5) {
2587 DPRINTFN(5,("uhci_device_isoc_enter: TD %d\n", i));
2588 uhci_dump_td(std);
2589 }
2590 #endif
2591 buf += len;
2592 offs += len;
2593 }
2594 iso->next = next;
2595 iso->inuse += xfer->nframes;
2596
2597 splx(s);
2598 }
2599
2600 usbd_status
2601 uhci_device_isoc_start(usbd_xfer_handle xfer)
2602 {
2603 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe;
2604 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private;
2605 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
2606 uhci_soft_td_t *end;
2607 int s, i;
2608
2609 DPRINTFN(5,("uhci_device_isoc_start: xfer=%p\n", xfer));
2610
2611 if (sc->sc_dying)
2612 return (USBD_IOERROR);
2613
2614 #ifdef DIAGNOSTIC
2615 if (xfer->status != USBD_IN_PROGRESS)
2616 printf("uhci_device_isoc_start: not in progress %p\n", xfer);
2617 #endif
2618
2619 /* Find the last TD */
2620 i = UXFER(xfer)->curframe + xfer->nframes;
2621 if (i >= UHCI_VFRAMELIST_COUNT)
2622 i -= UHCI_VFRAMELIST_COUNT;
2623 end = upipe->u.iso.stds[i];
2624
2625 #ifdef DIAGNOSTIC
2626 if (end == NULL) {
2627 printf("uhci_device_isoc_start: end == NULL\n");
2628 return (USBD_INVAL);
2629 }
2630 #endif
2631
2632 s = splusb();
2633
2634 /* Set up interrupt info. */
2635 ii->xfer = xfer;
2636 ii->stdstart = end;
2637 ii->stdend = end;
2638 #ifdef DIAGNOSTIC
2639 if (!ii->isdone)
2640 printf("uhci_device_isoc_start: not done, ii=%p\n", ii);
2641 ii->isdone = 0;
2642 #endif
2643 uhci_add_intr_info(sc, ii);
2644
2645 splx(s);
2646
2647 return (USBD_IN_PROGRESS);
2648 }
2649
2650 void
2651 uhci_device_isoc_abort(usbd_xfer_handle xfer)
2652 {
2653 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe;
2654 uhci_soft_td_t **stds = upipe->u.iso.stds;
2655 uhci_soft_td_t *std;
2656 int i, n, s, nframes, maxlen, len;
2657
2658 s = splusb();
2659
2660 /* Transfer is already done. */
2661 if (xfer->status != USBD_NOT_STARTED &&
2662 xfer->status != USBD_IN_PROGRESS) {
2663 splx(s);
2664 return;
2665 }
2666
2667 /* Give xfer the requested abort code. */
2668 xfer->status = USBD_CANCELLED;
2669
2670 /* make hardware ignore it, */
2671 nframes = xfer->nframes;
2672 n = UXFER(xfer)->curframe;
2673 maxlen = 0;
2674 for (i = 0; i < nframes; i++) {
2675 std = stds[n];
2676 usb_syncmem(&std->dma,
2677 std->offs + offsetof(uhci_td_t, td_status),
2678 sizeof(std->td.td_status),
2679 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2680 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC));
2681 usb_syncmem(&std->dma,
2682 std->offs + offsetof(uhci_td_t, td_status),
2683 sizeof(std->td.td_status),
2684 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2685 usb_syncmem(&std->dma,
2686 std->offs + offsetof(uhci_td_t, td_token),
2687 sizeof(std->td.td_token),
2688 BUS_DMASYNC_POSTWRITE);
2689 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token));
2690 if (len > maxlen)
2691 maxlen = len;
2692 if (++n >= UHCI_VFRAMELIST_COUNT)
2693 n = 0;
2694 }
2695
2696 /* and wait until we are sure the hardware has finished. */
2697 delay(maxlen);
2698
2699 #ifdef DIAGNOSTIC
2700 UXFER(xfer)->iinfo.isdone = 1;
2701 #endif
2702 /* Run callback and remove from interrupt list. */
2703 usb_transfer_complete(xfer);
2704
2705 splx(s);
2706 }
2707
2708 void
2709 uhci_device_isoc_close(usbd_pipe_handle pipe)
2710 {
2711 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;
2712 usbd_device_handle dev = upipe->pipe.device;
2713 uhci_softc_t *sc = dev->bus->hci_private;
2714 uhci_soft_td_t *std, *vstd;
2715 struct iso *iso;
2716 int i, s;
2717
2718 /*
2719 * Make sure all TDs are marked as inactive.
2720 * Wait for completion.
2721 * Unschedule.
2722 * Deallocate.
2723 */
2724 iso = &upipe->u.iso;
2725
2726 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
2727 std = iso->stds[i];
2728 usb_syncmem(&std->dma,
2729 std->offs + offsetof(uhci_td_t, td_status),
2730 sizeof(std->td.td_status),
2731 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2732 std->td.td_status &= htole32(~UHCI_TD_ACTIVE);
2733 usb_syncmem(&std->dma,
2734 std->offs + offsetof(uhci_td_t, td_status),
2735 sizeof(std->td.td_status),
2736 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2737 }
2738 usb_delay_ms(&sc->sc_bus, 2); /* wait for completion */
2739
2740 s = splusb();
2741 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
2742 std = iso->stds[i];
2743 for (vstd = sc->sc_vframes[i].htd;
2744 vstd != NULL && vstd->link.std != std;
2745 vstd = vstd->link.std)
2746 ;
2747 if (vstd == NULL) {
2748 /*panic*/
2749 printf("uhci_device_isoc_close: %p not found\n", std);
2750 splx(s);
2751 return;
2752 }
2753 vstd->link = std->link;
2754 usb_syncmem(&std->dma,
2755 std->offs + offsetof(uhci_td_t, td_link),
2756 sizeof(std->td.td_link),
2757 BUS_DMASYNC_POSTWRITE);
2758 vstd->td.td_link = std->td.td_link;
2759 usb_syncmem(&vstd->dma,
2760 vstd->offs + offsetof(uhci_td_t, td_link),
2761 sizeof(vstd->td.td_link),
2762 BUS_DMASYNC_PREWRITE);
2763 uhci_free_std(sc, std);
2764 }
2765 splx(s);
2766
2767 free(iso->stds, M_USBHC);
2768 }
2769
2770 usbd_status
2771 uhci_setup_isoc(usbd_pipe_handle pipe)
2772 {
2773 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;
2774 usbd_device_handle dev = upipe->pipe.device;
2775 uhci_softc_t *sc = dev->bus->hci_private;
2776 int addr = upipe->pipe.device->address;
2777 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress;
2778 int rd = UE_GET_DIR(endpt) == UE_DIR_IN;
2779 uhci_soft_td_t *std, *vstd;
2780 u_int32_t token;
2781 struct iso *iso;
2782 int i, s;
2783
2784 iso = &upipe->u.iso;
2785 iso->stds = malloc(UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *),
2786 M_USBHC, M_WAITOK);
2787
2788 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) :
2789 UHCI_TD_OUT(0, endpt, addr, 0);
2790
2791 /* Allocate the TDs and mark as inactive; */
2792 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
2793 std = uhci_alloc_std(sc);
2794 if (std == 0)
2795 goto bad;
2796 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */
2797 std->td.td_token = htole32(token);
2798 usb_syncmem(&std->dma, std->offs, sizeof(std->td),
2799 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2800 iso->stds[i] = std;
2801 }
2802
2803 /* Insert TDs into schedule. */
2804 s = splusb();
2805 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) {
2806 std = iso->stds[i];
2807 vstd = sc->sc_vframes[i].htd;
2808 usb_syncmem(&vstd->dma,
2809 vstd->offs + offsetof(uhci_td_t, td_link),
2810 sizeof(vstd->td.td_link),
2811 BUS_DMASYNC_POSTWRITE);
2812 std->link = vstd->link;
2813 std->td.td_link = vstd->td.td_link;
2814 usb_syncmem(&std->dma,
2815 std->offs + offsetof(uhci_td_t, td_link),
2816 sizeof(std->td.td_link),
2817 BUS_DMASYNC_PREWRITE);
2818 vstd->link.std = std;
2819 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD);
2820 usb_syncmem(&vstd->dma,
2821 vstd->offs + offsetof(uhci_td_t, td_link),
2822 sizeof(vstd->td.td_link),
2823 BUS_DMASYNC_PREWRITE);
2824 }
2825 splx(s);
2826
2827 iso->next = -1;
2828 iso->inuse = 0;
2829
2830 return (USBD_NORMAL_COMPLETION);
2831
2832 bad:
2833 while (--i >= 0)
2834 uhci_free_std(sc, iso->stds[i]);
2835 free(iso->stds, M_USBHC);
2836 return (USBD_NOMEM);
2837 }
2838
2839 void
2840 uhci_device_isoc_done(usbd_xfer_handle xfer)
2841 {
2842 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
2843 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe;
2844 int i, offs;
2845 int rd = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN;
2846
2847
2848 DPRINTFN(4, ("uhci_isoc_done: length=%d, busy_free=0x%08x\n",
2849 xfer->actlen, xfer->busy_free));
2850
2851 if (ii->xfer != xfer)
2852 /* Not on interrupt list, ignore it. */
2853 return;
2854
2855 if (!uhci_active_intr_info(ii))
2856 return;
2857
2858 #ifdef DIAGNOSTIC
2859 if (ii->stdend == NULL) {
2860 printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer);
2861 #ifdef UHCI_DEBUG
2862 uhci_dump_ii(ii);
2863 #endif
2864 return;
2865 }
2866 #endif
2867
2868 /* Turn off the interrupt since it is active even if the TD is not. */
2869 usb_syncmem(&ii->stdend->dma,
2870 ii->stdend->offs + offsetof(uhci_td_t, td_status),
2871 sizeof(ii->stdend->td.td_status),
2872 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2873 ii->stdend->td.td_status &= htole32(~UHCI_TD_IOC);
2874 usb_syncmem(&ii->stdend->dma,
2875 ii->stdend->offs + offsetof(uhci_td_t, td_status),
2876 sizeof(ii->stdend->td.td_status),
2877 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2878
2879 uhci_del_intr_info(ii); /* remove from active list */
2880
2881 offs = 0;
2882 for (i = 0; i < xfer->nframes; i++) {
2883 usb_syncmem(&xfer->dmabuf, offs, xfer->frlengths[i],
2884 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
2885 offs += xfer->frlengths[i];
2886 }
2887 }
2888
2889 void
2890 uhci_device_intr_done(usbd_xfer_handle xfer)
2891 {
2892 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
2893 uhci_softc_t *sc = ii->sc;
2894 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe;
2895 uhci_soft_qh_t *sqh;
2896 int i, npoll, isread;
2897
2898 DPRINTFN(5, ("uhci_device_intr_done: length=%d\n", xfer->actlen));
2899
2900 npoll = upipe->u.intr.npoll;
2901 for(i = 0; i < npoll; i++) {
2902 sqh = upipe->u.intr.qhs[i];
2903 sqh->elink = NULL;
2904 sqh->qh.qh_elink = htole32(UHCI_PTR_T);
2905 usb_syncmem(&sqh->dma,
2906 sqh->offs + offsetof(uhci_qh_t, qh_elink),
2907 sizeof(sqh->qh.qh_elink),
2908 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2909 }
2910 uhci_free_std_chain(sc, ii->stdstart, NULL);
2911
2912 isread = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN;
2913 usb_syncmem(&xfer->dmabuf, 0, xfer->length,
2914 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
2915
2916 /* XXX Wasteful. */
2917 if (xfer->pipe->repeat) {
2918 uhci_soft_td_t *data, *dataend;
2919
2920 DPRINTFN(5,("uhci_device_intr_done: requeing\n"));
2921
2922 /* This alloc cannot fail since we freed the chain above. */
2923 uhci_alloc_std_chain(upipe, sc, xfer->length,
2924 upipe->u.intr.isread, xfer->flags,
2925 &xfer->dmabuf, &data, &dataend);
2926 dataend->td.td_status |= htole32(UHCI_TD_IOC);
2927 usb_syncmem(&dataend->dma,
2928 dataend->offs + offsetof(uhci_td_t, td_status),
2929 sizeof(dataend->td.td_status),
2930 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2931
2932 #ifdef UHCI_DEBUG
2933 if (uhcidebug > 10) {
2934 DPRINTF(("uhci_device_intr_done: data(1)\n"));
2935 uhci_dump_tds(data);
2936 uhci_dump_qh(upipe->u.intr.qhs[0]);
2937 }
2938 #endif
2939
2940 ii->stdstart = data;
2941 ii->stdend = dataend;
2942 #ifdef DIAGNOSTIC
2943 if (!ii->isdone) {
2944 printf("uhci_device_intr_done: not done, ii=%p\n", ii);
2945 }
2946 ii->isdone = 0;
2947 #endif
2948 for (i = 0; i < npoll; i++) {
2949 sqh = upipe->u.intr.qhs[i];
2950 sqh->elink = data;
2951 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD);
2952 usb_syncmem(&sqh->dma,
2953 sqh->offs + offsetof(uhci_qh_t, qh_elink),
2954 sizeof(sqh->qh.qh_elink),
2955 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2956 }
2957 xfer->status = USBD_IN_PROGRESS;
2958 /* The ii is already on the examined list, just leave it. */
2959 } else {
2960 DPRINTFN(5,("uhci_device_intr_done: removing\n"));
2961 if (uhci_active_intr_info(ii))
2962 uhci_del_intr_info(ii);
2963 }
2964 }
2965
2966 /* Deallocate request data structures */
2967 void
2968 uhci_device_ctrl_done(usbd_xfer_handle xfer)
2969 {
2970 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
2971 uhci_softc_t *sc = ii->sc;
2972 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe;
2973 int len = UGETW(xfer->request.wLength);
2974 int isread = (xfer->request.bmRequestType & UT_READ);
2975
2976 #ifdef DIAGNOSTIC
2977 if (!(xfer->rqflags & URQ_REQUEST))
2978 panic("uhci_device_ctrl_done: not a request");
2979 #endif
2980
2981 if (!uhci_active_intr_info(ii))
2982 return;
2983
2984 uhci_del_intr_info(ii); /* remove from active list */
2985
2986 if (upipe->pipe.device->speed == USB_SPEED_LOW)
2987 uhci_remove_ls_ctrl(sc, upipe->u.ctl.sqh);
2988 else
2989 uhci_remove_hs_ctrl(sc, upipe->u.ctl.sqh);
2990
2991 if (upipe->u.ctl.length != 0)
2992 uhci_free_std_chain(sc, ii->stdstart->link.std, ii->stdend);
2993
2994 if (len) {
2995 usb_syncmem(&xfer->dmabuf, 0, len,
2996 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
2997 }
2998 usb_syncmem(&upipe->u.ctl.reqdma, 0,
2999 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE);
3000
3001 DPRINTFN(5, ("uhci_device_ctrl_done: length=%d\n", xfer->actlen));
3002 }
3003
3004 /* Deallocate request data structures */
3005 void
3006 uhci_device_bulk_done(usbd_xfer_handle xfer)
3007 {
3008 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo;
3009 uhci_softc_t *sc = ii->sc;
3010 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe;
3011
3012 DPRINTFN(5,("uhci_device_bulk_done: xfer=%p ii=%p sc=%p upipe=%p\n",
3013 xfer, ii, sc, upipe));
3014
3015 if (!uhci_active_intr_info(ii))
3016 return;
3017
3018 uhci_del_intr_info(ii); /* remove from active list */
3019
3020 uhci_remove_bulk(sc, upipe->u.bulk.sqh);
3021
3022 uhci_free_std_chain(sc, ii->stdstart, NULL);
3023
3024 DPRINTFN(5, ("uhci_device_bulk_done: length=%d\n", xfer->actlen));
3025 }
3026
3027 /* Add interrupt QH, called with vflock. */
3028 void
3029 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
3030 {
3031 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos];
3032 uhci_soft_qh_t *eqh;
3033
3034 DPRINTFN(4, ("uhci_add_intr: n=%d sqh=%p\n", sqh->pos, sqh));
3035
3036 eqh = vf->eqh;
3037 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
3038 sizeof(eqh->qh.qh_hlink),
3039 BUS_DMASYNC_POSTWRITE);
3040 sqh->hlink = eqh->hlink;
3041 sqh->qh.qh_hlink = eqh->qh.qh_hlink;
3042 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
3043 sizeof(sqh->qh.qh_hlink),
3044 BUS_DMASYNC_PREWRITE);
3045 eqh->hlink = sqh;
3046 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH);
3047 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink),
3048 sizeof(eqh->qh.qh_hlink),
3049 BUS_DMASYNC_PREWRITE);
3050 vf->eqh = sqh;
3051 vf->bandwidth++;
3052 }
3053
3054 /* Remove interrupt QH. */
3055 void
3056 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh)
3057 {
3058 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos];
3059 uhci_soft_qh_t *pqh;
3060
3061 DPRINTFN(4, ("uhci_remove_intr: n=%d sqh=%p\n", sqh->pos, sqh));
3062
3063 /* See comment in uhci_remove_ctrl() */
3064
3065 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink),
3066 sizeof(sqh->qh.qh_elink),
3067 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3068 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) {
3069 sqh->qh.qh_elink = htole32(UHCI_PTR_T);
3070 usb_syncmem(&sqh->dma,
3071 sqh->offs + offsetof(uhci_qh_t, qh_elink),
3072 sizeof(sqh->qh.qh_elink),
3073 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3074 delay(UHCI_QH_REMOVE_DELAY);
3075 }
3076
3077 pqh = uhci_find_prev_qh(vf->hqh, sqh);
3078 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink),
3079 sizeof(sqh->qh.qh_hlink),
3080 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3081 pqh->hlink = sqh->hlink;
3082 pqh->qh.qh_hlink = sqh->qh.qh_hlink;
3083 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink),
3084 sizeof(pqh->qh.qh_hlink),
3085 BUS_DMASYNC_PREWRITE);
3086 delay(UHCI_QH_REMOVE_DELAY);
3087 if (vf->eqh == sqh)
3088 vf->eqh = pqh;
3089 vf->bandwidth--;
3090 }
3091
3092 usbd_status
3093 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival)
3094 {
3095 uhci_soft_qh_t *sqh;
3096 int i, npoll, s;
3097 u_int bestbw, bw, bestoffs, offs;
3098
3099 DPRINTFN(2, ("uhci_device_setintr: pipe=%p\n", upipe));
3100 if (ival == 0) {
3101 printf("uhci_device_setintr: 0 interval\n");
3102 return (USBD_INVAL);
3103 }
3104
3105 if (ival > UHCI_VFRAMELIST_COUNT)
3106 ival = UHCI_VFRAMELIST_COUNT;
3107 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival;
3108 DPRINTFN(2, ("uhci_device_setintr: ival=%d npoll=%d\n", ival, npoll));
3109
3110 upipe->u.intr.npoll = npoll;
3111 upipe->u.intr.qhs =
3112 malloc(npoll * sizeof(uhci_soft_qh_t *), M_USBHC, M_WAITOK);
3113
3114 /*
3115 * Figure out which offset in the schedule that has most
3116 * bandwidth left over.
3117 */
3118 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1))
3119 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) {
3120 for (bw = i = 0; i < npoll; i++)
3121 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth;
3122 if (bw < bestbw) {
3123 bestbw = bw;
3124 bestoffs = offs;
3125 }
3126 }
3127 DPRINTFN(1, ("uhci_device_setintr: bw=%d offs=%d\n", bestbw, bestoffs));
3128
3129 for(i = 0; i < npoll; i++) {
3130 upipe->u.intr.qhs[i] = sqh = uhci_alloc_sqh(sc);
3131 sqh->elink = NULL;
3132 sqh->qh.qh_elink = htole32(UHCI_PTR_T);
3133 usb_syncmem(&sqh->dma,
3134 sqh->offs + offsetof(uhci_qh_t, qh_elink),
3135 sizeof(sqh->qh.qh_elink),
3136 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3137 sqh->pos = MOD(i * ival + bestoffs);
3138 }
3139 #undef MOD
3140
3141 s = splusb();
3142 /* Enter QHs into the controller data structures. */
3143 for(i = 0; i < npoll; i++)
3144 uhci_add_intr(sc, upipe->u.intr.qhs[i]);
3145 splx(s);
3146
3147 DPRINTFN(5, ("uhci_device_setintr: returns %p\n", upipe));
3148 return (USBD_NORMAL_COMPLETION);
3149 }
3150
3151 /* Open a new pipe. */
3152 usbd_status
3153 uhci_open(usbd_pipe_handle pipe)
3154 {
3155 uhci_softc_t *sc = pipe->device->bus->hci_private;
3156 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe;
3157 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc;
3158 usbd_status err;
3159 int ival;
3160
3161 DPRINTFN(1, ("uhci_open: pipe=%p, addr=%d, endpt=%d (%d)\n",
3162 pipe, pipe->device->address,
3163 ed->bEndpointAddress, sc->sc_addr));
3164
3165 upipe->aborting = 0;
3166 /* toggle state needed for bulk endpoints */
3167 upipe->nexttoggle = pipe->endpoint->datatoggle;
3168
3169 if (pipe->device->address == sc->sc_addr) {
3170 switch (ed->bEndpointAddress) {
3171 case USB_CONTROL_ENDPOINT:
3172 pipe->methods = &uhci_root_ctrl_methods;
3173 break;
3174 case UE_DIR_IN | UHCI_INTR_ENDPT:
3175 pipe->methods = &uhci_root_intr_methods;
3176 break;
3177 default:
3178 return (USBD_INVAL);
3179 }
3180 } else {
3181 switch (ed->bmAttributes & UE_XFERTYPE) {
3182 case UE_CONTROL:
3183 pipe->methods = &uhci_device_ctrl_methods;
3184 upipe->u.ctl.sqh = uhci_alloc_sqh(sc);
3185 if (upipe->u.ctl.sqh == NULL)
3186 goto bad;
3187 upipe->u.ctl.setup = uhci_alloc_std(sc);
3188 if (upipe->u.ctl.setup == NULL) {
3189 uhci_free_sqh(sc, upipe->u.ctl.sqh);
3190 goto bad;
3191 }
3192 upipe->u.ctl.stat = uhci_alloc_std(sc);
3193 if (upipe->u.ctl.stat == NULL) {
3194 uhci_free_sqh(sc, upipe->u.ctl.sqh);
3195 uhci_free_std(sc, upipe->u.ctl.setup);
3196 goto bad;
3197 }
3198 err = usb_allocmem(&sc->sc_bus,
3199 sizeof(usb_device_request_t),
3200 0, &upipe->u.ctl.reqdma);
3201 if (err) {
3202 uhci_free_sqh(sc, upipe->u.ctl.sqh);
3203 uhci_free_std(sc, upipe->u.ctl.setup);
3204 uhci_free_std(sc, upipe->u.ctl.stat);
3205 goto bad;
3206 }
3207 break;
3208 case UE_INTERRUPT:
3209 pipe->methods = &uhci_device_intr_methods;
3210 ival = pipe->interval;
3211 if (ival == USBD_DEFAULT_INTERVAL)
3212 ival = ed->bInterval;
3213 return (uhci_device_setintr(sc, upipe, ival));
3214 case UE_ISOCHRONOUS:
3215 pipe->methods = &uhci_device_isoc_methods;
3216 return (uhci_setup_isoc(pipe));
3217 case UE_BULK:
3218 pipe->methods = &uhci_device_bulk_methods;
3219 upipe->u.bulk.sqh = uhci_alloc_sqh(sc);
3220 if (upipe->u.bulk.sqh == NULL)
3221 goto bad;
3222 break;
3223 }
3224 }
3225 return (USBD_NORMAL_COMPLETION);
3226
3227 bad:
3228 return (USBD_NOMEM);
3229 }
3230
3231 /*
3232 * Data structures and routines to emulate the root hub.
3233 */
3234 usb_device_descriptor_t uhci_devd = {
3235 USB_DEVICE_DESCRIPTOR_SIZE,
3236 UDESC_DEVICE, /* type */
3237 {0x00, 0x01}, /* USB version */
3238 UDCLASS_HUB, /* class */
3239 UDSUBCLASS_HUB, /* subclass */
3240 UDPROTO_FSHUB, /* protocol */
3241 64, /* max packet */
3242 {0},{0},{0x00,0x01}, /* device id */
3243 1,2,0, /* string indicies */
3244 1 /* # of configurations */
3245 };
3246
3247 const usb_config_descriptor_t uhci_confd = {
3248 USB_CONFIG_DESCRIPTOR_SIZE,
3249 UDESC_CONFIG,
3250 {USB_CONFIG_DESCRIPTOR_SIZE +
3251 USB_INTERFACE_DESCRIPTOR_SIZE +
3252 USB_ENDPOINT_DESCRIPTOR_SIZE},
3253 1,
3254 1,
3255 0,
3256 UC_ATTR_MBO | UC_SELF_POWERED,
3257 0 /* max power */
3258 };
3259
3260 const usb_interface_descriptor_t uhci_ifcd = {
3261 USB_INTERFACE_DESCRIPTOR_SIZE,
3262 UDESC_INTERFACE,
3263 0,
3264 0,
3265 1,
3266 UICLASS_HUB,
3267 UISUBCLASS_HUB,
3268 UIPROTO_FSHUB,
3269 0
3270 };
3271
3272 const usb_endpoint_descriptor_t uhci_endpd = {
3273 USB_ENDPOINT_DESCRIPTOR_SIZE,
3274 UDESC_ENDPOINT,
3275 UE_DIR_IN | UHCI_INTR_ENDPT,
3276 UE_INTERRUPT,
3277 {8},
3278 255
3279 };
3280
3281 const usb_hub_descriptor_t uhci_hubd_piix = {
3282 USB_HUB_DESCRIPTOR_SIZE,
3283 UDESC_HUB,
3284 2,
3285 { UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0 },
3286 50, /* power on to power good */
3287 0,
3288 { 0x00 }, /* both ports are removable */
3289 { 0 },
3290 };
3291
3292 /*
3293 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also
3294 * enables the port, and also states that SET_FEATURE(PORT_ENABLE)
3295 * should not be used by the USB subsystem. As we cannot issue a
3296 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port
3297 * will be enabled as part of the reset.
3298 *
3299 * On the VT83C572, the port cannot be successfully enabled until the
3300 * outstanding "port enable change" and "connection status change"
3301 * events have been reset.
3302 */
3303 Static usbd_status
3304 uhci_portreset(uhci_softc_t *sc, int index)
3305 {
3306 int lim, port, x;
3307
3308 if (index == 1)
3309 port = UHCI_PORTSC1;
3310 else if (index == 2)
3311 port = UHCI_PORTSC2;
3312 else
3313 return (USBD_IOERROR);
3314
3315 x = URWMASK(UREAD2(sc, port));
3316 UWRITE2(sc, port, x | UHCI_PORTSC_PR);
3317
3318 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY);
3319
3320 DPRINTFN(3,("uhci port %d reset, status0 = 0x%04x\n",
3321 index, UREAD2(sc, port)));
3322
3323 x = URWMASK(UREAD2(sc, port));
3324 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP));
3325
3326 delay(100);
3327
3328 DPRINTFN(3,("uhci port %d reset, status1 = 0x%04x\n",
3329 index, UREAD2(sc, port)));
3330
3331 x = URWMASK(UREAD2(sc, port));
3332 UWRITE2(sc, port, x | UHCI_PORTSC_PE);
3333
3334 for (lim = 10; --lim > 0;) {
3335 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY);
3336
3337 x = UREAD2(sc, port);
3338
3339 DPRINTFN(3,("uhci port %d iteration %u, status = 0x%04x\n",
3340 index, lim, x));
3341
3342 if (!(x & UHCI_PORTSC_CCS)) {
3343 /*
3344 * No device is connected (or was disconnected
3345 * during reset). Consider the port reset.
3346 * The delay must be long enough to ensure on
3347 * the initial iteration that the device
3348 * connection will have been registered. 50ms
3349 * appears to be sufficient, but 20ms is not.
3350 */
3351 DPRINTFN(3,("uhci port %d loop %u, device detached\n",
3352 index, lim));
3353 break;
3354 }
3355
3356 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) {
3357 /*
3358 * Port enabled changed and/or connection
3359 * status changed were set. Reset either or
3360 * both raised flags (by writing a 1 to that
3361 * bit), and wait again for state to settle.
3362 */
3363 UWRITE2(sc, port, URWMASK(x) |
3364 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)));
3365 continue;
3366 }
3367
3368 if (x & UHCI_PORTSC_PE)
3369 /* Port is enabled */
3370 break;
3371
3372 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE);
3373 }
3374
3375 DPRINTFN(3,("uhci port %d reset, status2 = 0x%04x\n",
3376 index, UREAD2(sc, port)));
3377
3378 if (lim <= 0) {
3379 DPRINTFN(1,("uhci port %d reset timed out\n", index));
3380 return (USBD_TIMEOUT);
3381 }
3382
3383 sc->sc_isreset = 1;
3384 return (USBD_NORMAL_COMPLETION);
3385 }
3386
3387 /*
3388 * Simulate a hardware hub by handling all the necessary requests.
3389 */
3390 usbd_status
3391 uhci_root_ctrl_transfer(usbd_xfer_handle xfer)
3392 {
3393 usbd_status err;
3394
3395 /* Insert last in queue. */
3396 err = usb_insert_transfer(xfer);
3397 if (err)
3398 return (err);
3399
3400 /*
3401 * Pipe isn't running (otherwise err would be USBD_INPROG),
3402 * so start it first.
3403 */
3404 return (uhci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
3405 }
3406
3407 usbd_status
3408 uhci_root_ctrl_start(usbd_xfer_handle xfer)
3409 {
3410 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private;
3411 usb_device_request_t *req;
3412 void *buf = NULL;
3413 int port, x;
3414 int s, len, value, index, status, change, l, totlen = 0;
3415 usb_port_status_t ps;
3416 usbd_status err;
3417
3418 if (sc->sc_dying)
3419 return (USBD_IOERROR);
3420
3421 #ifdef DIAGNOSTIC
3422 if (!(xfer->rqflags & URQ_REQUEST))
3423 panic("uhci_root_ctrl_transfer: not a request");
3424 #endif
3425 req = &xfer->request;
3426
3427 DPRINTFN(2,("uhci_root_ctrl_control type=0x%02x request=%02x\n",
3428 req->bmRequestType, req->bRequest));
3429
3430 len = UGETW(req->wLength);
3431 value = UGETW(req->wValue);
3432 index = UGETW(req->wIndex);
3433
3434 if (len != 0)
3435 buf = KERNADDR(&xfer->dmabuf, 0);
3436
3437 #define C(x,y) ((x) | ((y) << 8))
3438 switch(C(req->bRequest, req->bmRequestType)) {
3439 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3440 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3441 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3442 /*
3443 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3444 * for the integrated root hub.
3445 */
3446 break;
3447 case C(UR_GET_CONFIG, UT_READ_DEVICE):
3448 if (len > 0) {
3449 *(u_int8_t *)buf = sc->sc_conf;
3450 totlen = 1;
3451 }
3452 break;
3453 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3454 DPRINTFN(2,("uhci_root_ctrl_control wValue=0x%04x\n", value));
3455 if (len == 0)
3456 break;
3457 switch(value >> 8) {
3458 case UDESC_DEVICE:
3459 if ((value & 0xff) != 0) {
3460 err = USBD_IOERROR;
3461 goto ret;
3462 }
3463 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE);
3464 USETW(uhci_devd.idVendor, sc->sc_id_vendor);
3465 memcpy(buf, &uhci_devd, l);
3466 break;
3467 case UDESC_CONFIG:
3468 if ((value & 0xff) != 0) {
3469 err = USBD_IOERROR;
3470 goto ret;
3471 }
3472 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE);
3473 memcpy(buf, &uhci_confd, l);
3474 buf = (char *)buf + l;
3475 len -= l;
3476 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE);
3477 totlen += l;
3478 memcpy(buf, &uhci_ifcd, l);
3479 buf = (char *)buf + l;
3480 len -= l;
3481 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE);
3482 totlen += l;
3483 memcpy(buf, &uhci_endpd, l);
3484 break;
3485 case UDESC_STRING:
3486 #define sd ((usb_string_descriptor_t *)buf)
3487 switch (value & 0xff) {
3488 case 0: /* Language table */
3489 totlen = usb_makelangtbl(sd, len);
3490 break;
3491 case 1: /* Vendor */
3492 totlen = usb_makestrdesc(sd, len,
3493 sc->sc_vendor);
3494 break;
3495 case 2: /* Product */
3496 totlen = usb_makestrdesc(sd, len,
3497 "UHCI root hub");
3498 break;
3499 }
3500 #undef sd
3501 break;
3502 default:
3503 err = USBD_IOERROR;
3504 goto ret;
3505 }
3506 break;
3507 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3508 if (len > 0) {
3509 *(u_int8_t *)buf = 0;
3510 totlen = 1;
3511 }
3512 break;
3513 case C(UR_GET_STATUS, UT_READ_DEVICE):
3514 if (len > 1) {
3515 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED);
3516 totlen = 2;
3517 }
3518 break;
3519 case C(UR_GET_STATUS, UT_READ_INTERFACE):
3520 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3521 if (len > 1) {
3522 USETW(((usb_status_t *)buf)->wStatus, 0);
3523 totlen = 2;
3524 }
3525 break;
3526 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3527 if (value >= USB_MAX_DEVICES) {
3528 err = USBD_IOERROR;
3529 goto ret;
3530 }
3531 sc->sc_addr = value;
3532 break;
3533 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3534 if (value != 0 && value != 1) {
3535 err = USBD_IOERROR;
3536 goto ret;
3537 }
3538 sc->sc_conf = value;
3539 break;
3540 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3541 break;
3542 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3543 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3544 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3545 err = USBD_IOERROR;
3546 goto ret;
3547 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3548 break;
3549 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3550 break;
3551 /* Hub requests */
3552 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3553 break;
3554 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3555 DPRINTFN(3, ("uhci_root_ctrl_control: UR_CLEAR_PORT_FEATURE "
3556 "port=%d feature=%d\n",
3557 index, value));
3558 if (index == 1)
3559 port = UHCI_PORTSC1;
3560 else if (index == 2)
3561 port = UHCI_PORTSC2;
3562 else {
3563 err = USBD_IOERROR;
3564 goto ret;
3565 }
3566 switch(value) {
3567 case UHF_PORT_ENABLE:
3568 x = URWMASK(UREAD2(sc, port));
3569 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE);
3570 break;
3571 case UHF_PORT_SUSPEND:
3572 x = URWMASK(UREAD2(sc, port));
3573 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */
3574 break;
3575 UWRITE2(sc, port, x | UHCI_PORTSC_RD);
3576 /* see USB2 spec ch. 7.1.7.7 */
3577 usb_delay_ms(&sc->sc_bus, 20);
3578 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP);
3579 /* 10ms resume delay must be provided by caller */
3580 break;
3581 case UHF_PORT_RESET:
3582 x = URWMASK(UREAD2(sc, port));
3583 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR);
3584 break;
3585 case UHF_C_PORT_CONNECTION:
3586 x = URWMASK(UREAD2(sc, port));
3587 UWRITE2(sc, port, x | UHCI_PORTSC_CSC);
3588 break;
3589 case UHF_C_PORT_ENABLE:
3590 x = URWMASK(UREAD2(sc, port));
3591 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC);
3592 break;
3593 case UHF_C_PORT_OVER_CURRENT:
3594 x = URWMASK(UREAD2(sc, port));
3595 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC);
3596 break;
3597 case UHF_C_PORT_RESET:
3598 sc->sc_isreset = 0;
3599 err = USBD_NORMAL_COMPLETION;
3600 goto ret;
3601 case UHF_PORT_CONNECTION:
3602 case UHF_PORT_OVER_CURRENT:
3603 case UHF_PORT_POWER:
3604 case UHF_PORT_LOW_SPEED:
3605 case UHF_C_PORT_SUSPEND:
3606 default:
3607 err = USBD_IOERROR;
3608 goto ret;
3609 }
3610 break;
3611 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER):
3612 if (index == 1)
3613 port = UHCI_PORTSC1;
3614 else if (index == 2)
3615 port = UHCI_PORTSC2;
3616 else {
3617 err = USBD_IOERROR;
3618 goto ret;
3619 }
3620 if (len > 0) {
3621 *(u_int8_t *)buf =
3622 (UREAD2(sc, port) & UHCI_PORTSC_LS) >>
3623 UHCI_PORTSC_LS_SHIFT;
3624 totlen = 1;
3625 }
3626 break;
3627 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3628 if (len == 0)
3629 break;
3630 if ((value & 0xff) != 0) {
3631 err = USBD_IOERROR;
3632 goto ret;
3633 }
3634 l = min(len, USB_HUB_DESCRIPTOR_SIZE);
3635 totlen = l;
3636 memcpy(buf, &uhci_hubd_piix, l);
3637 break;
3638 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3639 if (len != 4) {
3640 err = USBD_IOERROR;
3641 goto ret;
3642 }
3643 memset(buf, 0, len);
3644 totlen = len;
3645 break;
3646 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3647 if (index == 1)
3648 port = UHCI_PORTSC1;
3649 else if (index == 2)
3650 port = UHCI_PORTSC2;
3651 else {
3652 err = USBD_IOERROR;
3653 goto ret;
3654 }
3655 if (len != 4) {
3656 err = USBD_IOERROR;
3657 goto ret;
3658 }
3659 x = UREAD2(sc, port);
3660 status = change = 0;
3661 if (x & UHCI_PORTSC_CCS)
3662 status |= UPS_CURRENT_CONNECT_STATUS;
3663 if (x & UHCI_PORTSC_CSC)
3664 change |= UPS_C_CONNECT_STATUS;
3665 if (x & UHCI_PORTSC_PE)
3666 status |= UPS_PORT_ENABLED;
3667 if (x & UHCI_PORTSC_POEDC)
3668 change |= UPS_C_PORT_ENABLED;
3669 if (x & UHCI_PORTSC_OCI)
3670 status |= UPS_OVERCURRENT_INDICATOR;
3671 if (x & UHCI_PORTSC_OCIC)
3672 change |= UPS_C_OVERCURRENT_INDICATOR;
3673 if (x & UHCI_PORTSC_SUSP)
3674 status |= UPS_SUSPEND;
3675 if (x & UHCI_PORTSC_LSDA)
3676 status |= UPS_LOW_SPEED;
3677 status |= UPS_PORT_POWER;
3678 if (sc->sc_isreset)
3679 change |= UPS_C_PORT_RESET;
3680 USETW(ps.wPortStatus, status);
3681 USETW(ps.wPortChange, change);
3682 l = min(len, sizeof ps);
3683 memcpy(buf, &ps, l);
3684 totlen = l;
3685 break;
3686 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3687 err = USBD_IOERROR;
3688 goto ret;
3689 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3690 break;
3691 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3692 if (index == 1)
3693 port = UHCI_PORTSC1;
3694 else if (index == 2)
3695 port = UHCI_PORTSC2;
3696 else {
3697 err = USBD_IOERROR;
3698 goto ret;
3699 }
3700 switch(value) {
3701 case UHF_PORT_ENABLE:
3702 x = URWMASK(UREAD2(sc, port));
3703 UWRITE2(sc, port, x | UHCI_PORTSC_PE);
3704 break;
3705 case UHF_PORT_SUSPEND:
3706 x = URWMASK(UREAD2(sc, port));
3707 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP);
3708 break;
3709 case UHF_PORT_RESET:
3710 err = uhci_portreset(sc, index);
3711 goto ret;
3712 case UHF_PORT_POWER:
3713 /* Pretend we turned on power */
3714 err = USBD_NORMAL_COMPLETION;
3715 goto ret;
3716 case UHF_C_PORT_CONNECTION:
3717 case UHF_C_PORT_ENABLE:
3718 case UHF_C_PORT_OVER_CURRENT:
3719 case UHF_PORT_CONNECTION:
3720 case UHF_PORT_OVER_CURRENT:
3721 case UHF_PORT_LOW_SPEED:
3722 case UHF_C_PORT_SUSPEND:
3723 case UHF_C_PORT_RESET:
3724 default:
3725 err = USBD_IOERROR;
3726 goto ret;
3727 }
3728 break;
3729 default:
3730 err = USBD_IOERROR;
3731 goto ret;
3732 }
3733 xfer->actlen = totlen;
3734 err = USBD_NORMAL_COMPLETION;
3735 ret:
3736 xfer->status = err;
3737 s = splusb();
3738 usb_transfer_complete(xfer);
3739 splx(s);
3740 return (USBD_IN_PROGRESS);
3741 }
3742
3743 /* Abort a root control request. */
3744 void
3745 uhci_root_ctrl_abort(usbd_xfer_handle xfer)
3746 {
3747 /* Nothing to do, all transfers are synchronous. */
3748 }
3749
3750 /* Close the root pipe. */
3751 void
3752 uhci_root_ctrl_close(usbd_pipe_handle pipe)
3753 {
3754 DPRINTF(("uhci_root_ctrl_close\n"));
3755 }
3756
3757 /* Abort a root interrupt request. */
3758 void
3759 uhci_root_intr_abort(usbd_xfer_handle xfer)
3760 {
3761 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private;
3762
3763 callout_stop(&sc->sc_poll_handle);
3764 sc->sc_intr_xfer = NULL;
3765
3766 if (xfer->pipe->intrxfer == xfer) {
3767 DPRINTF(("uhci_root_intr_abort: remove\n"));
3768 xfer->pipe->intrxfer = 0;
3769 }
3770 xfer->status = USBD_CANCELLED;
3771 #ifdef DIAGNOSTIC
3772 UXFER(xfer)->iinfo.isdone = 1;
3773 #endif
3774 usb_transfer_complete(xfer);
3775 }
3776
3777 usbd_status
3778 uhci_root_intr_transfer(usbd_xfer_handle xfer)
3779 {
3780 usbd_status err;
3781
3782 /* Insert last in queue. */
3783 err = usb_insert_transfer(xfer);
3784 if (err)
3785 return (err);
3786
3787 /*
3788 * Pipe isn't running (otherwise err would be USBD_INPROG),
3789 * start first
3790 */
3791 return (uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
3792 }
3793
3794 /* Start a transfer on the root interrupt pipe */
3795 usbd_status
3796 uhci_root_intr_start(usbd_xfer_handle xfer)
3797 {
3798 usbd_pipe_handle pipe = xfer->pipe;
3799 uhci_softc_t *sc = pipe->device->bus->hci_private;
3800 unsigned int ival;
3801
3802 DPRINTFN(3, ("uhci_root_intr_start: xfer=%p len=%d flags=%d\n",
3803 xfer, xfer->length, xfer->flags));
3804
3805 if (sc->sc_dying)
3806 return (USBD_IOERROR);
3807
3808 /* XXX temporary variable needed to avoid gcc3 warning */
3809 ival = xfer->pipe->endpoint->edesc->bInterval;
3810 sc->sc_ival = mstohz(ival);
3811 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer);
3812 sc->sc_intr_xfer = xfer;
3813 return (USBD_IN_PROGRESS);
3814 }
3815
3816 /* Close the root interrupt pipe. */
3817 void
3818 uhci_root_intr_close(usbd_pipe_handle pipe)
3819 {
3820 uhci_softc_t *sc = pipe->device->bus->hci_private;
3821
3822 callout_stop(&sc->sc_poll_handle);
3823 sc->sc_intr_xfer = NULL;
3824 DPRINTF(("uhci_root_intr_close\n"));
3825 }
3826