uhci.c revision 1.240.2.3
1 /* $NetBSD: uhci.c,v 1.240.2.3 2013/01/23 00:06:13 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Universal Host Controller driver. 36 * Handles e.g. PIIX3 and PIIX4. 37 * 38 * UHCI spec: http://www.intel.com/technology/usb/spec.htm 39 * USB spec: http://www.usb.org/developers/docs/ 40 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 41 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.240.2.3 2013/01/23 00:06:13 yamt Exp $"); 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/kmem.h> 51 #include <sys/device.h> 52 #include <sys/select.h> 53 #include <sys/extent.h> 54 #include <sys/proc.h> 55 #include <sys/queue.h> 56 #include <sys/bus.h> 57 #include <sys/cpu.h> 58 59 #include <machine/endian.h> 60 61 #include <dev/usb/usb.h> 62 #include <dev/usb/usbdi.h> 63 #include <dev/usb/usbdivar.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/uhcireg.h> 68 #include <dev/usb/uhcivar.h> 69 #include <dev/usb/usbroothub_subr.h> 70 71 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 72 /*#define UHCI_CTL_LOOP */ 73 74 75 76 #ifdef UHCI_DEBUG 77 uhci_softc_t *thesc; 78 #define DPRINTF(x) if (uhcidebug) printf x 79 #define DPRINTFN(n,x) if (uhcidebug>(n)) printf x 80 int uhcidebug = 0; 81 int uhcinoloop = 0; 82 #else 83 #define DPRINTF(x) 84 #define DPRINTFN(n,x) 85 #endif 86 87 /* 88 * The UHCI controller is little endian, so on big endian machines 89 * the data stored in memory needs to be swapped. 90 */ 91 92 struct uhci_pipe { 93 struct usbd_pipe pipe; 94 int nexttoggle; 95 96 u_char aborting; 97 usbd_xfer_handle abortstart, abortend; 98 99 /* Info needed for different pipe kinds. */ 100 union { 101 /* Control pipe */ 102 struct { 103 uhci_soft_qh_t *sqh; 104 usb_dma_t reqdma; 105 uhci_soft_td_t *setup, *stat; 106 u_int length; 107 } ctl; 108 /* Interrupt pipe */ 109 struct { 110 int npoll; 111 int isread; 112 uhci_soft_qh_t **qhs; 113 } intr; 114 /* Bulk pipe */ 115 struct { 116 uhci_soft_qh_t *sqh; 117 u_int length; 118 int isread; 119 } bulk; 120 /* Iso pipe */ 121 struct iso { 122 uhci_soft_td_t **stds; 123 int next, inuse; 124 } iso; 125 } u; 126 }; 127 128 Static void uhci_globalreset(uhci_softc_t *); 129 Static usbd_status uhci_portreset(uhci_softc_t*, int); 130 Static void uhci_reset(uhci_softc_t *); 131 Static usbd_status uhci_run(uhci_softc_t *, int run, int locked); 132 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 133 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 134 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 135 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 136 #if 0 137 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 138 uhci_intr_info_t *); 139 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 140 #endif 141 142 Static void uhci_free_std_chain(uhci_softc_t *, 143 uhci_soft_td_t *, uhci_soft_td_t *); 144 Static usbd_status uhci_alloc_std_chain(struct uhci_pipe *, 145 uhci_softc_t *, int, int, u_int16_t, usb_dma_t *, 146 uhci_soft_td_t **, uhci_soft_td_t **); 147 Static void uhci_poll_hub(void *); 148 Static void uhci_waitintr(uhci_softc_t *, usbd_xfer_handle); 149 Static void uhci_check_intr(uhci_softc_t *, uhci_intr_info_t *); 150 Static void uhci_idone(uhci_intr_info_t *); 151 152 Static void uhci_abort_xfer(usbd_xfer_handle, usbd_status status); 153 154 Static void uhci_timeout(void *); 155 Static void uhci_timeout_task(void *); 156 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 157 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 158 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 159 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 160 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 161 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 162 Static void uhci_add_loop(uhci_softc_t *sc); 163 Static void uhci_rem_loop(uhci_softc_t *sc); 164 165 Static usbd_status uhci_setup_isoc(usbd_pipe_handle pipe); 166 Static void uhci_device_isoc_enter(usbd_xfer_handle); 167 168 Static usbd_status uhci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 169 Static void uhci_freem(struct usbd_bus *, usb_dma_t *); 170 171 Static usbd_xfer_handle uhci_allocx(struct usbd_bus *); 172 Static void uhci_freex(struct usbd_bus *, usbd_xfer_handle); 173 Static void uhci_get_lock(struct usbd_bus *, kmutex_t **); 174 175 Static usbd_status uhci_device_ctrl_transfer(usbd_xfer_handle); 176 Static usbd_status uhci_device_ctrl_start(usbd_xfer_handle); 177 Static void uhci_device_ctrl_abort(usbd_xfer_handle); 178 Static void uhci_device_ctrl_close(usbd_pipe_handle); 179 Static void uhci_device_ctrl_done(usbd_xfer_handle); 180 181 Static usbd_status uhci_device_intr_transfer(usbd_xfer_handle); 182 Static usbd_status uhci_device_intr_start(usbd_xfer_handle); 183 Static void uhci_device_intr_abort(usbd_xfer_handle); 184 Static void uhci_device_intr_close(usbd_pipe_handle); 185 Static void uhci_device_intr_done(usbd_xfer_handle); 186 187 Static usbd_status uhci_device_bulk_transfer(usbd_xfer_handle); 188 Static usbd_status uhci_device_bulk_start(usbd_xfer_handle); 189 Static void uhci_device_bulk_abort(usbd_xfer_handle); 190 Static void uhci_device_bulk_close(usbd_pipe_handle); 191 Static void uhci_device_bulk_done(usbd_xfer_handle); 192 193 Static usbd_status uhci_device_isoc_transfer(usbd_xfer_handle); 194 Static usbd_status uhci_device_isoc_start(usbd_xfer_handle); 195 Static void uhci_device_isoc_abort(usbd_xfer_handle); 196 Static void uhci_device_isoc_close(usbd_pipe_handle); 197 Static void uhci_device_isoc_done(usbd_xfer_handle); 198 199 Static usbd_status uhci_root_ctrl_transfer(usbd_xfer_handle); 200 Static usbd_status uhci_root_ctrl_start(usbd_xfer_handle); 201 Static void uhci_root_ctrl_abort(usbd_xfer_handle); 202 Static void uhci_root_ctrl_close(usbd_pipe_handle); 203 Static void uhci_root_ctrl_done(usbd_xfer_handle); 204 205 Static usbd_status uhci_root_intr_transfer(usbd_xfer_handle); 206 Static usbd_status uhci_root_intr_start(usbd_xfer_handle); 207 Static void uhci_root_intr_abort(usbd_xfer_handle); 208 Static void uhci_root_intr_close(usbd_pipe_handle); 209 Static void uhci_root_intr_done(usbd_xfer_handle); 210 211 Static usbd_status uhci_open(usbd_pipe_handle); 212 Static void uhci_poll(struct usbd_bus *); 213 Static void uhci_softintr(void *); 214 215 Static usbd_status uhci_device_request(usbd_xfer_handle xfer); 216 217 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 218 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 219 Static usbd_status uhci_device_setintr(uhci_softc_t *sc, 220 struct uhci_pipe *pipe, int ival); 221 222 Static void uhci_device_clear_toggle(usbd_pipe_handle pipe); 223 Static void uhci_noop(usbd_pipe_handle pipe); 224 225 static inline uhci_soft_qh_t *uhci_find_prev_qh(uhci_soft_qh_t *, 226 uhci_soft_qh_t *); 227 228 #ifdef UHCI_DEBUG 229 Static void uhci_dump_all(uhci_softc_t *); 230 Static void uhci_dumpregs(uhci_softc_t *); 231 Static void uhci_dump_qhs(uhci_soft_qh_t *); 232 Static void uhci_dump_qh(uhci_soft_qh_t *); 233 Static void uhci_dump_tds(uhci_soft_td_t *); 234 Static void uhci_dump_td(uhci_soft_td_t *); 235 Static void uhci_dump_ii(uhci_intr_info_t *ii); 236 void uhci_dump(void); 237 #endif 238 239 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 240 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 241 #define UWRITE1(sc, r, x) \ 242 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 243 } while (/*CONSTCOND*/0) 244 #define UWRITE2(sc, r, x) \ 245 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 246 } while (/*CONSTCOND*/0) 247 #define UWRITE4(sc, r, x) \ 248 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 249 } while (/*CONSTCOND*/0) 250 static __inline uint8_t 251 UREAD1(uhci_softc_t *sc, bus_size_t r) 252 { 253 254 UBARR(sc); 255 return bus_space_read_1(sc->iot, sc->ioh, r); 256 } 257 258 static __inline uint16_t 259 UREAD2(uhci_softc_t *sc, bus_size_t r) 260 { 261 262 UBARR(sc); 263 return bus_space_read_2(sc->iot, sc->ioh, r); 264 } 265 266 static __inline uint32_t 267 UREAD4(uhci_softc_t *sc, bus_size_t r) 268 { 269 270 UBARR(sc); 271 return bus_space_read_4(sc->iot, sc->ioh, r); 272 } 273 274 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 275 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 276 277 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 278 279 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 280 281 #define UHCI_INTR_ENDPT 1 282 283 const struct usbd_bus_methods uhci_bus_methods = { 284 .open_pipe = uhci_open, 285 .soft_intr = uhci_softintr, 286 .do_poll = uhci_poll, 287 .allocm = uhci_allocm, 288 .freem = uhci_freem, 289 .allocx = uhci_allocx, 290 .freex = uhci_freex, 291 .get_lock = uhci_get_lock, 292 }; 293 294 const struct usbd_pipe_methods uhci_root_ctrl_methods = { 295 .transfer = uhci_root_ctrl_transfer, 296 .start = uhci_root_ctrl_start, 297 .abort = uhci_root_ctrl_abort, 298 .close = uhci_root_ctrl_close, 299 .cleartoggle = uhci_noop, 300 .done = uhci_root_ctrl_done, 301 }; 302 303 const struct usbd_pipe_methods uhci_root_intr_methods = { 304 .transfer = uhci_root_intr_transfer, 305 .start = uhci_root_intr_start, 306 .abort = uhci_root_intr_abort, 307 .close = uhci_root_intr_close, 308 .cleartoggle = uhci_noop, 309 .done = uhci_root_intr_done, 310 }; 311 312 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 313 .transfer = uhci_device_ctrl_transfer, 314 .start = uhci_device_ctrl_start, 315 .abort = uhci_device_ctrl_abort, 316 .close = uhci_device_ctrl_close, 317 .cleartoggle = uhci_noop, 318 .done = uhci_device_ctrl_done, 319 }; 320 321 const struct usbd_pipe_methods uhci_device_intr_methods = { 322 .transfer = uhci_device_intr_transfer, 323 .start = uhci_device_intr_start, 324 .abort = uhci_device_intr_abort, 325 .close = uhci_device_intr_close, 326 .cleartoggle = uhci_device_clear_toggle, 327 .done = uhci_device_intr_done, 328 }; 329 330 const struct usbd_pipe_methods uhci_device_bulk_methods = { 331 .transfer = uhci_device_bulk_transfer, 332 .start = uhci_device_bulk_start, 333 .abort = uhci_device_bulk_abort, 334 .close = uhci_device_bulk_close, 335 .cleartoggle = uhci_device_clear_toggle, 336 .done = uhci_device_bulk_done, 337 }; 338 339 const struct usbd_pipe_methods uhci_device_isoc_methods = { 340 .transfer = uhci_device_isoc_transfer, 341 .start = uhci_device_isoc_start, 342 .abort = uhci_device_isoc_abort, 343 .close = uhci_device_isoc_close, 344 .cleartoggle = uhci_noop, 345 .done = uhci_device_isoc_done, 346 }; 347 348 #define uhci_add_intr_info(sc, ii) \ 349 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ii), list) 350 #define uhci_del_intr_info(ii) \ 351 do { \ 352 LIST_REMOVE((ii), list); \ 353 (ii)->list.le_prev = NULL; \ 354 } while (0) 355 #define uhci_active_intr_info(ii) ((ii)->list.le_prev != NULL) 356 357 static inline uhci_soft_qh_t * 358 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 359 { 360 DPRINTFN(15,("uhci_find_prev_qh: pqh=%p sqh=%p\n", pqh, sqh)); 361 362 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 363 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 364 usb_syncmem(&pqh->dma, 365 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 366 sizeof(pqh->qh.qh_hlink), 367 BUS_DMASYNC_POSTWRITE); 368 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 369 printf("uhci_find_prev_qh: QH not found\n"); 370 return (NULL); 371 } 372 #endif 373 } 374 return (pqh); 375 } 376 377 void 378 uhci_globalreset(uhci_softc_t *sc) 379 { 380 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 381 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 382 UHCICMD(sc, 0); /* do nothing */ 383 } 384 385 usbd_status 386 uhci_init(uhci_softc_t *sc) 387 { 388 usbd_status err; 389 int i, j; 390 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 391 uhci_soft_td_t *std; 392 393 DPRINTFN(1,("uhci_init: start\n")); 394 395 #ifdef UHCI_DEBUG 396 thesc = sc; 397 398 if (uhcidebug > 2) 399 uhci_dumpregs(sc); 400 #endif 401 402 sc->sc_suspend = PWR_RESUME; 403 404 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 405 uhci_globalreset(sc); /* reset the controller */ 406 uhci_reset(sc); 407 408 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 409 USB_MEM_RESERVE); 410 411 /* Allocate and initialize real frame array. */ 412 err = usb_allocmem(&sc->sc_bus, 413 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 414 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 415 if (err) 416 return (err); 417 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 418 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 419 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 420 421 /* 422 * Allocate a TD, inactive, that hangs from the last QH. 423 * This is to avoid a bug in the PIIX that makes it run berserk 424 * otherwise. 425 */ 426 std = uhci_alloc_std(sc); 427 if (std == NULL) 428 return (USBD_NOMEM); 429 std->link.std = NULL; 430 std->td.td_link = htole32(UHCI_PTR_T); 431 std->td.td_status = htole32(0); /* inactive */ 432 std->td.td_token = htole32(0); 433 std->td.td_buffer = htole32(0); 434 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 435 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 436 437 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 438 lsqh = uhci_alloc_sqh(sc); 439 if (lsqh == NULL) 440 return (USBD_NOMEM); 441 lsqh->hlink = NULL; 442 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 443 lsqh->elink = std; 444 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 445 sc->sc_last_qh = lsqh; 446 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 447 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 448 449 /* Allocate the dummy QH where bulk traffic will be queued. */ 450 bsqh = uhci_alloc_sqh(sc); 451 if (bsqh == NULL) 452 return (USBD_NOMEM); 453 bsqh->hlink = lsqh; 454 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 455 bsqh->elink = NULL; 456 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 457 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 458 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 459 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 460 461 /* Allocate dummy QH where high speed control traffic will be queued. */ 462 chsqh = uhci_alloc_sqh(sc); 463 if (chsqh == NULL) 464 return (USBD_NOMEM); 465 chsqh->hlink = bsqh; 466 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 467 chsqh->elink = NULL; 468 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 469 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 470 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 471 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 472 473 /* Allocate dummy QH where control traffic will be queued. */ 474 clsqh = uhci_alloc_sqh(sc); 475 if (clsqh == NULL) 476 return (USBD_NOMEM); 477 clsqh->hlink = chsqh; 478 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 479 clsqh->elink = NULL; 480 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 481 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 482 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 483 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 484 485 /* 486 * Make all (virtual) frame list pointers point to the interrupt 487 * queue heads and the interrupt queue heads at the control 488 * queue head and point the physical frame list to the virtual. 489 */ 490 for(i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 491 std = uhci_alloc_std(sc); 492 sqh = uhci_alloc_sqh(sc); 493 if (std == NULL || sqh == NULL) 494 return (USBD_NOMEM); 495 std->link.sqh = sqh; 496 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 497 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 498 std->td.td_token = htole32(0); 499 std->td.td_buffer = htole32(0); 500 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 501 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 502 sqh->hlink = clsqh; 503 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 504 sqh->elink = NULL; 505 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 506 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 507 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 508 sc->sc_vframes[i].htd = std; 509 sc->sc_vframes[i].etd = std; 510 sc->sc_vframes[i].hqh = sqh; 511 sc->sc_vframes[i].eqh = sqh; 512 for (j = i; 513 j < UHCI_FRAMELIST_COUNT; 514 j += UHCI_VFRAMELIST_COUNT) 515 sc->sc_pframes[j] = htole32(std->physaddr); 516 } 517 usb_syncmem(&sc->sc_dma, 0, 518 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 519 BUS_DMASYNC_PREWRITE); 520 521 522 LIST_INIT(&sc->sc_intrhead); 523 524 SIMPLEQ_INIT(&sc->sc_free_xfers); 525 526 callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE); 527 528 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 529 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 530 cv_init(&sc->sc_softwake_cv, "uhciab"); 531 532 /* Set up the bus struct. */ 533 sc->sc_bus.methods = &uhci_bus_methods; 534 sc->sc_bus.pipe_size = sizeof(struct uhci_pipe); 535 536 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 537 538 DPRINTFN(1,("uhci_init: enabling\n")); 539 540 err = uhci_run(sc, 1, 0); /* and here we go... */ 541 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 542 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 543 return err; 544 } 545 546 int 547 uhci_activate(device_t self, enum devact act) 548 { 549 struct uhci_softc *sc = device_private(self); 550 551 switch (act) { 552 case DVACT_DEACTIVATE: 553 sc->sc_dying = 1; 554 return 0; 555 default: 556 return EOPNOTSUPP; 557 } 558 } 559 560 void 561 uhci_childdet(device_t self, device_t child) 562 { 563 struct uhci_softc *sc = device_private(self); 564 565 KASSERT(sc->sc_child == child); 566 sc->sc_child = NULL; 567 } 568 569 int 570 uhci_detach(struct uhci_softc *sc, int flags) 571 { 572 usbd_xfer_handle xfer; 573 int rv = 0; 574 575 if (sc->sc_child != NULL) 576 rv = config_detach(sc->sc_child, flags); 577 578 if (rv != 0) 579 return (rv); 580 581 /* Free all xfers associated with this HC. */ 582 for (;;) { 583 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 584 if (xfer == NULL) 585 break; 586 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 587 kmem_free(xfer, sizeof(struct uhci_xfer)); 588 } 589 590 callout_halt(&sc->sc_poll_handle, NULL); 591 callout_destroy(&sc->sc_poll_handle); 592 593 cv_destroy(&sc->sc_softwake_cv); 594 595 mutex_destroy(&sc->sc_lock); 596 mutex_destroy(&sc->sc_intr_lock); 597 598 /* XXX free other data structures XXX */ 599 600 return (rv); 601 } 602 603 usbd_status 604 uhci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 605 { 606 struct uhci_softc *sc = bus->hci_private; 607 usbd_status status; 608 u_int32_t n; 609 610 /* 611 * XXX 612 * Since we are allocating a buffer we can assume that we will 613 * need TDs for it. Since we don't want to allocate those from 614 * an interrupt context, we allocate them here and free them again. 615 * This is no guarantee that we'll get the TDs next time... 616 */ 617 n = size / 8; 618 if (n > 16) { 619 u_int32_t i; 620 uhci_soft_td_t **stds; 621 622 DPRINTF(("uhci_allocm: get %d TDs\n", n)); 623 stds = kmem_alloc(sizeof(uhci_soft_td_t *) * n, KM_SLEEP); 624 if (!stds) 625 return USBD_NOMEM; 626 for(i = 0; i < n; i++) 627 stds[i] = uhci_alloc_std(sc); 628 for(i = 0; i < n; i++) 629 if (stds[i] != NULL) 630 uhci_free_std(sc, stds[i]); 631 kmem_free(stds, sizeof(uhci_soft_td_t *) * n); 632 } 633 634 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 635 if (status == USBD_NOMEM) 636 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 637 return status; 638 } 639 640 void 641 uhci_freem(struct usbd_bus *bus, usb_dma_t *dma) 642 { 643 if (dma->block->flags & USB_DMA_RESERVE) { 644 usb_reserve_freem(&((struct uhci_softc *)bus)->sc_dma_reserve, 645 dma); 646 return; 647 } 648 usb_freemem(&((struct uhci_softc *)bus)->sc_bus, dma); 649 } 650 651 usbd_xfer_handle 652 uhci_allocx(struct usbd_bus *bus) 653 { 654 struct uhci_softc *sc = bus->hci_private; 655 usbd_xfer_handle xfer; 656 657 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 658 if (xfer != NULL) { 659 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 660 #ifdef DIAGNOSTIC 661 if (xfer->busy_free != XFER_FREE) { 662 printf("uhci_allocx: xfer=%p not free, 0x%08x\n", xfer, 663 xfer->busy_free); 664 } 665 #endif 666 } else { 667 xfer = kmem_alloc(sizeof(struct uhci_xfer), KM_SLEEP); 668 } 669 if (xfer != NULL) { 670 memset(xfer, 0, sizeof (struct uhci_xfer)); 671 UXFER(xfer)->iinfo.sc = sc; 672 #ifdef DIAGNOSTIC 673 UXFER(xfer)->iinfo.isdone = 1; 674 xfer->busy_free = XFER_BUSY; 675 #endif 676 } 677 return (xfer); 678 } 679 680 void 681 uhci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 682 { 683 struct uhci_softc *sc = bus->hci_private; 684 685 #ifdef DIAGNOSTIC 686 if (xfer->busy_free != XFER_BUSY) { 687 printf("uhci_freex: xfer=%p not busy, 0x%08x\n", xfer, 688 xfer->busy_free); 689 } 690 xfer->busy_free = XFER_FREE; 691 if (!UXFER(xfer)->iinfo.isdone) { 692 printf("uhci_freex: !isdone\n"); 693 } 694 #endif 695 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 696 } 697 698 Static void 699 uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 700 { 701 struct uhci_softc *sc = bus->hci_private; 702 703 *lock = &sc->sc_lock; 704 } 705 706 707 /* 708 * Handle suspend/resume. 709 * 710 * We need to switch to polling mode here, because this routine is 711 * called from an interrupt context. This is all right since we 712 * are almost suspended anyway. 713 */ 714 bool 715 uhci_resume(device_t dv, const pmf_qual_t *qual) 716 { 717 uhci_softc_t *sc = device_private(dv); 718 int cmd; 719 720 mutex_spin_enter(&sc->sc_intr_lock); 721 722 cmd = UREAD2(sc, UHCI_CMD); 723 sc->sc_bus.use_polling++; 724 UWRITE2(sc, UHCI_INTR, 0); 725 uhci_globalreset(sc); 726 uhci_reset(sc); 727 if (cmd & UHCI_CMD_RS) 728 uhci_run(sc, 0, 1); 729 730 /* restore saved state */ 731 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 732 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 733 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 734 735 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 736 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock); 737 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 738 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 739 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 740 UHCICMD(sc, UHCI_CMD_MAXP); 741 uhci_run(sc, 1, 1); /* and start traffic again */ 742 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock); 743 sc->sc_bus.use_polling--; 744 if (sc->sc_intr_xfer != NULL) 745 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, 746 sc->sc_intr_xfer); 747 #ifdef UHCI_DEBUG 748 if (uhcidebug > 2) 749 uhci_dumpregs(sc); 750 #endif 751 752 sc->sc_suspend = PWR_RESUME; 753 mutex_spin_exit(&sc->sc_intr_lock); 754 755 return true; 756 } 757 758 bool 759 uhci_suspend(device_t dv, const pmf_qual_t *qual) 760 { 761 uhci_softc_t *sc = device_private(dv); 762 int cmd; 763 764 mutex_spin_enter(&sc->sc_intr_lock); 765 766 cmd = UREAD2(sc, UHCI_CMD); 767 768 #ifdef UHCI_DEBUG 769 if (uhcidebug > 2) 770 uhci_dumpregs(sc); 771 #endif 772 if (sc->sc_intr_xfer != NULL) 773 callout_stop(&sc->sc_poll_handle); 774 sc->sc_suspend = PWR_SUSPEND; 775 sc->sc_bus.use_polling++; 776 777 uhci_run(sc, 0, 1); /* stop the controller */ 778 cmd &= ~UHCI_CMD_RS; 779 780 /* save some state if BIOS doesn't */ 781 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 782 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 783 784 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 785 786 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 787 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock); 788 sc->sc_bus.use_polling--; 789 790 mutex_spin_exit(&sc->sc_intr_lock); 791 792 return true; 793 } 794 795 #ifdef UHCI_DEBUG 796 Static void 797 uhci_dumpregs(uhci_softc_t *sc) 798 { 799 DPRINTFN(-1,("%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, " 800 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 801 device_xname(sc->sc_dev), 802 UREAD2(sc, UHCI_CMD), 803 UREAD2(sc, UHCI_STS), 804 UREAD2(sc, UHCI_INTR), 805 UREAD2(sc, UHCI_FRNUM), 806 UREAD4(sc, UHCI_FLBASEADDR), 807 UREAD1(sc, UHCI_SOF), 808 UREAD2(sc, UHCI_PORTSC1), 809 UREAD2(sc, UHCI_PORTSC2))); 810 } 811 812 void 813 uhci_dump_td(uhci_soft_td_t *p) 814 { 815 char sbuf[128], sbuf2[128]; 816 817 818 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 819 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 820 DPRINTFN(-1,("TD(%p) at %08lx = link=0x%08lx status=0x%08lx " 821 "token=0x%08lx buffer=0x%08lx\n", 822 p, (long)p->physaddr, 823 (long)le32toh(p->td.td_link), 824 (long)le32toh(p->td.td_status), 825 (long)le32toh(p->td.td_token), 826 (long)le32toh(p->td.td_buffer))); 827 828 snprintb(sbuf, sizeof(sbuf), "\20\1T\2Q\3VF", 829 (u_int32_t)le32toh(p->td.td_link)); 830 snprintb(sbuf2, sizeof(sbuf2), 831 "\20\22BITSTUFF\23CRCTO\24NAK\25BABBLE\26DBUFFER\27" 832 "STALLED\30ACTIVE\31IOC\32ISO\33LS\36SPD", 833 (u_int32_t)le32toh(p->td.td_status)); 834 835 DPRINTFN(-1,(" %s %s,errcnt=%d,actlen=%d pid=%02x,addr=%d,endpt=%d," 836 "D=%d,maxlen=%d\n", sbuf, sbuf2, 837 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 838 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 839 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 840 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 841 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 842 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 843 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token)))); 844 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 845 BUS_DMASYNC_PREREAD); 846 } 847 848 void 849 uhci_dump_qh(uhci_soft_qh_t *sqh) 850 { 851 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 852 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 853 DPRINTFN(-1,("QH(%p) at %08x: hlink=%08x elink=%08x\n", sqh, 854 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 855 le32toh(sqh->qh.qh_elink))); 856 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 857 } 858 859 860 #if 1 861 void 862 uhci_dump(void) 863 { 864 uhci_dump_all(thesc); 865 } 866 #endif 867 868 void 869 uhci_dump_all(uhci_softc_t *sc) 870 { 871 uhci_dumpregs(sc); 872 printf("intrs=%d\n", sc->sc_bus.no_intrs); 873 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 874 uhci_dump_qh(sc->sc_lctl_start); 875 } 876 877 878 void 879 uhci_dump_qhs(uhci_soft_qh_t *sqh) 880 { 881 uhci_dump_qh(sqh); 882 883 /* uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 884 * Traverses sideways first, then down. 885 * 886 * QH1 887 * QH2 888 * No QH 889 * TD2.1 890 * TD2.2 891 * TD1.1 892 * etc. 893 * 894 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 895 */ 896 897 898 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 899 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 900 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 901 uhci_dump_qhs(sqh->hlink); 902 else 903 DPRINTF(("No QH\n")); 904 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 905 906 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 907 uhci_dump_tds(sqh->elink); 908 else 909 DPRINTF(("No TD\n")); 910 } 911 912 void 913 uhci_dump_tds(uhci_soft_td_t *std) 914 { 915 uhci_soft_td_t *td; 916 int stop; 917 918 for(td = std; td != NULL; td = td->link.std) { 919 uhci_dump_td(td); 920 921 /* Check whether the link pointer in this TD marks 922 * the link pointer as end of queue. This avoids 923 * printing the free list in case the queue/TD has 924 * already been moved there (seatbelt). 925 */ 926 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 927 sizeof(td->td.td_link), 928 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 929 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 930 le32toh(td->td.td_link) == 0); 931 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 932 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 933 if (stop) 934 break; 935 } 936 } 937 938 Static void 939 uhci_dump_ii(uhci_intr_info_t *ii) 940 { 941 usbd_pipe_handle pipe; 942 usb_endpoint_descriptor_t *ed; 943 usbd_device_handle dev; 944 945 #ifdef DIAGNOSTIC 946 #define DONE ii->isdone 947 #else 948 #define DONE 0 949 #endif 950 if (ii == NULL) { 951 printf("ii NULL\n"); 952 return; 953 } 954 if (ii->xfer == NULL) { 955 printf("ii %p: done=%d xfer=NULL\n", 956 ii, DONE); 957 return; 958 } 959 pipe = ii->xfer->pipe; 960 if (pipe == NULL) { 961 printf("ii %p: done=%d xfer=%p pipe=NULL\n", 962 ii, DONE, ii->xfer); 963 return; 964 } 965 if (pipe->endpoint == NULL) { 966 printf("ii %p: done=%d xfer=%p pipe=%p pipe->endpoint=NULL\n", 967 ii, DONE, ii->xfer, pipe); 968 return; 969 } 970 if (pipe->device == NULL) { 971 printf("ii %p: done=%d xfer=%p pipe=%p pipe->device=NULL\n", 972 ii, DONE, ii->xfer, pipe); 973 return; 974 } 975 ed = pipe->endpoint->edesc; 976 dev = pipe->device; 977 printf("ii %p: done=%d xfer=%p dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 978 ii, DONE, ii->xfer, dev, 979 UGETW(dev->ddesc.idVendor), 980 UGETW(dev->ddesc.idProduct), 981 dev->address, pipe, 982 ed->bEndpointAddress, ed->bmAttributes); 983 #undef DONE 984 } 985 986 void uhci_dump_iis(struct uhci_softc *sc); 987 void 988 uhci_dump_iis(struct uhci_softc *sc) 989 { 990 uhci_intr_info_t *ii; 991 992 printf("intr_info list:\n"); 993 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = LIST_NEXT(ii, list)) 994 uhci_dump_ii(ii); 995 } 996 997 void iidump(void); 998 void iidump(void) { uhci_dump_iis(thesc); } 999 1000 #endif 1001 1002 /* 1003 * This routine is executed periodically and simulates interrupts 1004 * from the root controller interrupt pipe for port status change. 1005 */ 1006 void 1007 uhci_poll_hub(void *addr) 1008 { 1009 usbd_xfer_handle xfer = addr; 1010 usbd_pipe_handle pipe = xfer->pipe; 1011 uhci_softc_t *sc; 1012 u_char *p; 1013 1014 DPRINTFN(20, ("uhci_poll_hub\n")); 1015 1016 if (__predict_false(pipe->device == NULL || pipe->device->bus == NULL)) 1017 return; /* device has detached */ 1018 sc = pipe->device->bus->hci_private; 1019 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 1020 1021 p = KERNADDR(&xfer->dmabuf, 0); 1022 p[0] = 0; 1023 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1024 p[0] |= 1<<1; 1025 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1026 p[0] |= 1<<2; 1027 if (p[0] == 0) 1028 /* No change, try again in a while */ 1029 return; 1030 1031 xfer->actlen = 1; 1032 xfer->status = USBD_NORMAL_COMPLETION; 1033 mutex_enter(&sc->sc_lock); 1034 usb_transfer_complete(xfer); 1035 mutex_exit(&sc->sc_lock); 1036 } 1037 1038 void 1039 uhci_root_intr_done(usbd_xfer_handle xfer) 1040 { 1041 } 1042 1043 void 1044 uhci_root_ctrl_done(usbd_xfer_handle xfer) 1045 { 1046 } 1047 1048 /* 1049 * Let the last QH loop back to the high speed control transfer QH. 1050 * This is what intel calls "bandwidth reclamation" and improves 1051 * USB performance a lot for some devices. 1052 * If we are already looping, just count it. 1053 */ 1054 void 1055 uhci_add_loop(uhci_softc_t *sc) { 1056 #ifdef UHCI_DEBUG 1057 if (uhcinoloop) 1058 return; 1059 #endif 1060 if (++sc->sc_loops == 1) { 1061 DPRINTFN(5,("uhci_start_loop: add\n")); 1062 /* Note, we don't loop back the soft pointer. */ 1063 sc->sc_last_qh->qh.qh_hlink = 1064 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 1065 usb_syncmem(&sc->sc_last_qh->dma, 1066 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1067 sizeof(sc->sc_last_qh->qh.qh_hlink), 1068 BUS_DMASYNC_PREWRITE); 1069 } 1070 } 1071 1072 void 1073 uhci_rem_loop(uhci_softc_t *sc) { 1074 #ifdef UHCI_DEBUG 1075 if (uhcinoloop) 1076 return; 1077 #endif 1078 if (--sc->sc_loops == 0) { 1079 DPRINTFN(5,("uhci_end_loop: remove\n")); 1080 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 1081 usb_syncmem(&sc->sc_last_qh->dma, 1082 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1083 sizeof(sc->sc_last_qh->qh.qh_hlink), 1084 BUS_DMASYNC_PREWRITE); 1085 } 1086 } 1087 1088 /* Add high speed control QH, called with lock held. */ 1089 void 1090 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1091 { 1092 uhci_soft_qh_t *eqh; 1093 1094 KASSERT(mutex_owned(&sc->sc_lock)); 1095 1096 DPRINTFN(10, ("uhci_add_ctrl: sqh=%p\n", sqh)); 1097 eqh = sc->sc_hctl_end; 1098 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1099 sizeof(eqh->qh.qh_hlink), 1100 BUS_DMASYNC_POSTWRITE); 1101 sqh->hlink = eqh->hlink; 1102 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1103 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1104 BUS_DMASYNC_PREWRITE); 1105 eqh->hlink = sqh; 1106 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1107 sc->sc_hctl_end = sqh; 1108 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1109 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1110 #ifdef UHCI_CTL_LOOP 1111 uhci_add_loop(sc); 1112 #endif 1113 } 1114 1115 /* Remove high speed control QH, called with lock held. */ 1116 void 1117 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1118 { 1119 uhci_soft_qh_t *pqh; 1120 1121 KASSERT(mutex_owned(&sc->sc_lock)); 1122 1123 DPRINTFN(10, ("uhci_remove_hs_ctrl: sqh=%p\n", sqh)); 1124 #ifdef UHCI_CTL_LOOP 1125 uhci_rem_loop(sc); 1126 #endif 1127 /* 1128 * The T bit should be set in the elink of the QH so that the HC 1129 * doesn't follow the pointer. This condition may fail if the 1130 * the transferred packet was short so that the QH still points 1131 * at the last used TD. 1132 * In this case we set the T bit and wait a little for the HC 1133 * to stop looking at the TD. 1134 * Note that if the TD chain is large enough, the controller 1135 * may still be looking at the chain at the end of this function. 1136 * uhci_free_std_chain() will make sure the controller stops 1137 * looking at it quickly, but until then we should not change 1138 * sqh->hlink. 1139 */ 1140 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1141 sizeof(sqh->qh.qh_elink), 1142 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1143 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1144 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1145 usb_syncmem(&sqh->dma, 1146 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1147 sizeof(sqh->qh.qh_elink), 1148 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1149 delay(UHCI_QH_REMOVE_DELAY); 1150 } 1151 1152 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1153 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1154 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1155 pqh->hlink = sqh->hlink; 1156 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1157 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1158 sizeof(pqh->qh.qh_hlink), 1159 BUS_DMASYNC_PREWRITE); 1160 delay(UHCI_QH_REMOVE_DELAY); 1161 if (sc->sc_hctl_end == sqh) 1162 sc->sc_hctl_end = pqh; 1163 } 1164 1165 /* Add low speed control QH, called with lock held. */ 1166 void 1167 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1168 { 1169 uhci_soft_qh_t *eqh; 1170 1171 KASSERT(mutex_owned(&sc->sc_lock)); 1172 1173 DPRINTFN(10, ("uhci_add_ls_ctrl: sqh=%p\n", sqh)); 1174 eqh = sc->sc_lctl_end; 1175 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1176 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1177 sqh->hlink = eqh->hlink; 1178 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1179 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1180 BUS_DMASYNC_PREWRITE); 1181 eqh->hlink = sqh; 1182 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1183 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1184 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1185 sc->sc_lctl_end = sqh; 1186 } 1187 1188 /* Remove low speed control QH, called with lock held. */ 1189 void 1190 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1191 { 1192 uhci_soft_qh_t *pqh; 1193 1194 KASSERT(mutex_owned(&sc->sc_lock)); 1195 1196 DPRINTFN(10, ("uhci_remove_ls_ctrl: sqh=%p\n", sqh)); 1197 /* See comment in uhci_remove_hs_ctrl() */ 1198 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1199 sizeof(sqh->qh.qh_elink), 1200 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1201 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1202 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1203 usb_syncmem(&sqh->dma, 1204 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1205 sizeof(sqh->qh.qh_elink), 1206 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1207 delay(UHCI_QH_REMOVE_DELAY); 1208 } 1209 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1210 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1211 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1212 pqh->hlink = sqh->hlink; 1213 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1214 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1215 sizeof(pqh->qh.qh_hlink), 1216 BUS_DMASYNC_PREWRITE); 1217 delay(UHCI_QH_REMOVE_DELAY); 1218 if (sc->sc_lctl_end == sqh) 1219 sc->sc_lctl_end = pqh; 1220 } 1221 1222 /* Add bulk QH, called with lock held. */ 1223 void 1224 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1225 { 1226 uhci_soft_qh_t *eqh; 1227 1228 KASSERT(mutex_owned(&sc->sc_lock)); 1229 1230 DPRINTFN(10, ("uhci_add_bulk: sqh=%p\n", sqh)); 1231 eqh = sc->sc_bulk_end; 1232 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1233 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1234 sqh->hlink = eqh->hlink; 1235 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1236 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1237 BUS_DMASYNC_PREWRITE); 1238 eqh->hlink = sqh; 1239 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1240 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1241 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1242 sc->sc_bulk_end = sqh; 1243 uhci_add_loop(sc); 1244 } 1245 1246 /* Remove bulk QH, called with lock held. */ 1247 void 1248 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1249 { 1250 uhci_soft_qh_t *pqh; 1251 1252 KASSERT(mutex_owned(&sc->sc_lock)); 1253 1254 DPRINTFN(10, ("uhci_remove_bulk: sqh=%p\n", sqh)); 1255 uhci_rem_loop(sc); 1256 /* See comment in uhci_remove_hs_ctrl() */ 1257 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1258 sizeof(sqh->qh.qh_elink), 1259 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1260 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1261 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1262 usb_syncmem(&sqh->dma, 1263 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1264 sizeof(sqh->qh.qh_elink), 1265 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1266 delay(UHCI_QH_REMOVE_DELAY); 1267 } 1268 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1269 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1270 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1271 pqh->hlink = sqh->hlink; 1272 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1273 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1274 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1275 delay(UHCI_QH_REMOVE_DELAY); 1276 if (sc->sc_bulk_end == sqh) 1277 sc->sc_bulk_end = pqh; 1278 } 1279 1280 Static int uhci_intr1(uhci_softc_t *); 1281 1282 int 1283 uhci_intr(void *arg) 1284 { 1285 uhci_softc_t *sc = arg; 1286 int ret = 0; 1287 1288 mutex_spin_enter(&sc->sc_intr_lock); 1289 1290 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1291 goto done; 1292 1293 if (sc->sc_bus.use_polling || UREAD2(sc, UHCI_INTR) == 0) { 1294 #ifdef DIAGNOSTIC 1295 DPRINTFN(16, ("uhci_intr: ignored interrupt while polling\n")); 1296 #endif 1297 goto done; 1298 } 1299 1300 ret = uhci_intr1(sc); 1301 1302 done: 1303 mutex_spin_exit(&sc->sc_intr_lock); 1304 return ret; 1305 } 1306 1307 int 1308 uhci_intr1(uhci_softc_t *sc) 1309 { 1310 int status; 1311 int ack; 1312 1313 #ifdef UHCI_DEBUG 1314 if (uhcidebug > 15) { 1315 DPRINTF(("%s: uhci_intr1\n", device_xname(sc->sc_dev))); 1316 uhci_dumpregs(sc); 1317 } 1318 #endif 1319 1320 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1321 1322 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1323 if (status == 0) /* The interrupt was not for us. */ 1324 return (0); 1325 1326 if (sc->sc_suspend != PWR_RESUME) { 1327 #ifdef DIAGNOSTIC 1328 printf("%s: interrupt while not operating ignored\n", 1329 device_xname(sc->sc_dev)); 1330 #endif 1331 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1332 return (0); 1333 } 1334 1335 ack = 0; 1336 if (status & UHCI_STS_USBINT) 1337 ack |= UHCI_STS_USBINT; 1338 if (status & UHCI_STS_USBEI) 1339 ack |= UHCI_STS_USBEI; 1340 if (status & UHCI_STS_RD) { 1341 ack |= UHCI_STS_RD; 1342 #ifdef UHCI_DEBUG 1343 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1344 #endif 1345 } 1346 if (status & UHCI_STS_HSE) { 1347 ack |= UHCI_STS_HSE; 1348 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1349 } 1350 if (status & UHCI_STS_HCPE) { 1351 ack |= UHCI_STS_HCPE; 1352 printf("%s: host controller process error\n", 1353 device_xname(sc->sc_dev)); 1354 } 1355 1356 /* When HCHalted=1 and Run/Stop=0 , it is normal */ 1357 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 1358 /* no acknowledge needed */ 1359 if (!sc->sc_dying) { 1360 printf("%s: host controller halted\n", 1361 device_xname(sc->sc_dev)); 1362 #ifdef UHCI_DEBUG 1363 uhci_dump_all(sc); 1364 #endif 1365 } 1366 sc->sc_dying = 1; 1367 } 1368 1369 if (!ack) 1370 return (0); /* nothing to acknowledge */ 1371 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1372 1373 sc->sc_bus.no_intrs++; 1374 usb_schedsoftintr(&sc->sc_bus); 1375 1376 DPRINTFN(15, ("%s: uhci_intr: exit\n", device_xname(sc->sc_dev))); 1377 1378 return (1); 1379 } 1380 1381 void 1382 uhci_softintr(void *v) 1383 { 1384 struct usbd_bus *bus = v; 1385 uhci_softc_t *sc = bus->hci_private; 1386 uhci_intr_info_t *ii, *nextii; 1387 1388 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1389 1390 DPRINTFN(10,("%s: uhci_softintr\n", device_xname(sc->sc_dev))); 1391 1392 /* 1393 * Interrupts on UHCI really suck. When the host controller 1394 * interrupts because a transfer is completed there is no 1395 * way of knowing which transfer it was. You can scan down 1396 * the TDs and QHs of the previous frame to limit the search, 1397 * but that assumes that the interrupt was not delayed by more 1398 * than 1 ms, which may not always be true (e.g. after debug 1399 * output on a slow console). 1400 * We scan all interrupt descriptors to see if any have 1401 * completed. 1402 */ 1403 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = nextii) { 1404 nextii = LIST_NEXT(ii, list); 1405 uhci_check_intr(sc, ii); 1406 } 1407 1408 if (sc->sc_softwake) { 1409 sc->sc_softwake = 0; 1410 cv_broadcast(&sc->sc_softwake_cv); 1411 } 1412 } 1413 1414 /* Check for an interrupt. */ 1415 void 1416 uhci_check_intr(uhci_softc_t *sc, uhci_intr_info_t *ii) 1417 { 1418 uhci_soft_td_t *std, *lstd; 1419 u_int32_t status; 1420 1421 DPRINTFN(15, ("uhci_check_intr: ii=%p\n", ii)); 1422 #ifdef DIAGNOSTIC 1423 if (ii == NULL) { 1424 printf("uhci_check_intr: no ii? %p\n", ii); 1425 return; 1426 } 1427 #endif 1428 if (ii->xfer->status == USBD_CANCELLED || 1429 ii->xfer->status == USBD_TIMEOUT) { 1430 DPRINTF(("uhci_check_intr: aborted xfer=%p\n", ii->xfer)); 1431 return; 1432 } 1433 1434 if (ii->stdstart == NULL) 1435 return; 1436 lstd = ii->stdend; 1437 #ifdef DIAGNOSTIC 1438 if (lstd == NULL) { 1439 printf("uhci_check_intr: std==0\n"); 1440 return; 1441 } 1442 #endif 1443 /* 1444 * If the last TD is still active we need to check whether there 1445 * is an error somewhere in the middle, or whether there was a 1446 * short packet (SPD and not ACTIVE). 1447 */ 1448 usb_syncmem(&lstd->dma, 1449 lstd->offs + offsetof(uhci_td_t, td_status), 1450 sizeof(lstd->td.td_status), 1451 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1452 if (le32toh(lstd->td.td_status) & UHCI_TD_ACTIVE) { 1453 DPRINTFN(12, ("uhci_check_intr: active ii=%p\n", ii)); 1454 for (std = ii->stdstart; std != lstd; std = std->link.std) { 1455 usb_syncmem(&std->dma, 1456 std->offs + offsetof(uhci_td_t, td_status), 1457 sizeof(std->td.td_status), 1458 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1459 status = le32toh(std->td.td_status); 1460 usb_syncmem(&std->dma, 1461 std->offs + offsetof(uhci_td_t, td_status), 1462 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1463 /* If there's an active TD the xfer isn't done. */ 1464 if (status & UHCI_TD_ACTIVE) 1465 break; 1466 /* Any kind of error makes the xfer done. */ 1467 if (status & UHCI_TD_STALLED) 1468 goto done; 1469 /* We want short packets, and it is short: it's done */ 1470 usb_syncmem(&std->dma, 1471 std->offs + offsetof(uhci_td_t, td_token), 1472 sizeof(std->td.td_token), 1473 BUS_DMASYNC_POSTWRITE); 1474 if ((status & UHCI_TD_SPD) && 1475 UHCI_TD_GET_ACTLEN(status) < 1476 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) 1477 goto done; 1478 } 1479 DPRINTFN(12, ("uhci_check_intr: ii=%p std=%p still active\n", 1480 ii, ii->stdstart)); 1481 usb_syncmem(&lstd->dma, 1482 lstd->offs + offsetof(uhci_td_t, td_status), 1483 sizeof(lstd->td.td_status), 1484 BUS_DMASYNC_PREREAD); 1485 return; 1486 } 1487 done: 1488 DPRINTFN(12, ("uhci_check_intr: ii=%p done\n", ii)); 1489 callout_stop(&ii->xfer->timeout_handle); 1490 uhci_idone(ii); 1491 } 1492 1493 /* Called with USB lock held. */ 1494 void 1495 uhci_idone(uhci_intr_info_t *ii) 1496 { 1497 usbd_xfer_handle xfer = ii->xfer; 1498 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 1499 #ifdef DIAGNOSTIC 1500 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 1501 #endif 1502 uhci_soft_td_t *std; 1503 u_int32_t status = 0, nstatus; 1504 int actlen; 1505 1506 KASSERT(mutex_owned(&sc->sc_lock)); 1507 1508 DPRINTFN(12, ("uhci_idone: ii=%p\n", ii)); 1509 #ifdef DIAGNOSTIC 1510 { 1511 /* XXX SMP? */ 1512 int s = splhigh(); 1513 if (ii->isdone) { 1514 splx(s); 1515 #ifdef UHCI_DEBUG 1516 printf("uhci_idone: ii is done!\n "); 1517 uhci_dump_ii(ii); 1518 #else 1519 printf("uhci_idone: ii=%p is done!\n", ii); 1520 #endif 1521 return; 1522 } 1523 ii->isdone = 1; 1524 splx(s); 1525 } 1526 #endif 1527 1528 if (xfer->nframes != 0) { 1529 /* Isoc transfer, do things differently. */ 1530 uhci_soft_td_t **stds = upipe->u.iso.stds; 1531 int i, n, nframes, len; 1532 1533 DPRINTFN(5,("uhci_idone: ii=%p isoc ready\n", ii)); 1534 1535 nframes = xfer->nframes; 1536 actlen = 0; 1537 n = UXFER(xfer)->curframe; 1538 for (i = 0; i < nframes; i++) { 1539 std = stds[n]; 1540 #ifdef UHCI_DEBUG 1541 if (uhcidebug > 5) { 1542 DPRINTFN(-1,("uhci_idone: isoc TD %d\n", i)); 1543 uhci_dump_td(std); 1544 } 1545 #endif 1546 if (++n >= UHCI_VFRAMELIST_COUNT) 1547 n = 0; 1548 usb_syncmem(&std->dma, 1549 std->offs + offsetof(uhci_td_t, td_status), 1550 sizeof(std->td.td_status), 1551 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1552 status = le32toh(std->td.td_status); 1553 len = UHCI_TD_GET_ACTLEN(status); 1554 xfer->frlengths[i] = len; 1555 actlen += len; 1556 } 1557 upipe->u.iso.inuse -= nframes; 1558 xfer->actlen = actlen; 1559 xfer->status = USBD_NORMAL_COMPLETION; 1560 goto end; 1561 } 1562 1563 #ifdef UHCI_DEBUG 1564 DPRINTFN(10, ("uhci_idone: ii=%p, xfer=%p, pipe=%p ready\n", 1565 ii, xfer, upipe)); 1566 if (uhcidebug > 10) 1567 uhci_dump_tds(ii->stdstart); 1568 #endif 1569 1570 /* The transfer is done, compute actual length and status. */ 1571 actlen = 0; 1572 for (std = ii->stdstart; std != NULL; std = std->link.std) { 1573 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1574 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1575 nstatus = le32toh(std->td.td_status); 1576 if (nstatus & UHCI_TD_ACTIVE) 1577 break; 1578 1579 status = nstatus; 1580 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1581 UHCI_TD_PID_SETUP) 1582 actlen += UHCI_TD_GET_ACTLEN(status); 1583 else { 1584 /* 1585 * UHCI will report CRCTO in addition to a STALL or NAK 1586 * for a SETUP transaction. See section 3.2.2, "TD 1587 * CONTROL AND STATUS". 1588 */ 1589 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1590 status &= ~UHCI_TD_CRCTO; 1591 } 1592 } 1593 /* If there are left over TDs we need to update the toggle. */ 1594 if (std != NULL) 1595 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1596 1597 status &= UHCI_TD_ERROR; 1598 DPRINTFN(10, ("uhci_idone: actlen=%d, status=0x%x\n", 1599 actlen, status)); 1600 xfer->actlen = actlen; 1601 if (status != 0) { 1602 #ifdef UHCI_DEBUG 1603 char sbuf[128]; 1604 1605 snprintb(sbuf, sizeof(sbuf), 1606 "\20\22BITSTUFF\23CRCTO\24NAK\25" 1607 "BABBLE\26DBUFFER\27STALLED\30ACTIVE",(u_int32_t)status); 1608 1609 DPRINTFN((status == UHCI_TD_STALLED)*10, 1610 ("uhci_idone: error, addr=%d, endpt=0x%02x, " 1611 "status 0x%s\n", 1612 xfer->pipe->device->address, 1613 xfer->pipe->endpoint->edesc->bEndpointAddress, 1614 sbuf)); 1615 #endif 1616 1617 if (status == UHCI_TD_STALLED) 1618 xfer->status = USBD_STALLED; 1619 else 1620 xfer->status = USBD_IOERROR; /* more info XXX */ 1621 } else { 1622 xfer->status = USBD_NORMAL_COMPLETION; 1623 } 1624 1625 end: 1626 usb_transfer_complete(xfer); 1627 KASSERT(mutex_owned(&sc->sc_lock)); 1628 DPRINTFN(12, ("uhci_idone: ii=%p done\n", ii)); 1629 } 1630 1631 /* 1632 * Called when a request does not complete. 1633 */ 1634 void 1635 uhci_timeout(void *addr) 1636 { 1637 uhci_intr_info_t *ii = addr; 1638 struct uhci_xfer *uxfer = UXFER(ii->xfer); 1639 struct uhci_pipe *upipe = (struct uhci_pipe *)uxfer->xfer.pipe; 1640 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 1641 1642 DPRINTF(("uhci_timeout: uxfer=%p\n", uxfer)); 1643 1644 if (sc->sc_dying) { 1645 mutex_enter(&sc->sc_lock); 1646 uhci_abort_xfer(&uxfer->xfer, USBD_TIMEOUT); 1647 mutex_exit(&sc->sc_lock); 1648 return; 1649 } 1650 1651 /* Execute the abort in a process context. */ 1652 usb_init_task(&uxfer->abort_task, uhci_timeout_task, ii->xfer, 1653 USB_TASKQ_MPSAFE); 1654 usb_add_task(uxfer->xfer.pipe->device, &uxfer->abort_task, 1655 USB_TASKQ_HC); 1656 } 1657 1658 void 1659 uhci_timeout_task(void *addr) 1660 { 1661 usbd_xfer_handle xfer = addr; 1662 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1663 1664 DPRINTF(("uhci_timeout_task: xfer=%p\n", xfer)); 1665 1666 mutex_enter(&sc->sc_lock); 1667 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1668 mutex_exit(&sc->sc_lock); 1669 } 1670 1671 /* 1672 * Wait here until controller claims to have an interrupt. 1673 * Then call uhci_intr and return. Use timeout to avoid waiting 1674 * too long. 1675 * Only used during boot when interrupts are not enabled yet. 1676 */ 1677 void 1678 uhci_waitintr(uhci_softc_t *sc, usbd_xfer_handle xfer) 1679 { 1680 int timo = xfer->timeout; 1681 uhci_intr_info_t *ii; 1682 1683 mutex_enter(&sc->sc_lock); 1684 1685 DPRINTFN(10,("uhci_waitintr: timeout = %dms\n", timo)); 1686 1687 xfer->status = USBD_IN_PROGRESS; 1688 for (; timo >= 0; timo--) { 1689 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_lock); 1690 DPRINTFN(20,("uhci_waitintr: 0x%04x\n", UREAD2(sc, UHCI_STS))); 1691 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1692 mutex_spin_enter(&sc->sc_intr_lock); 1693 uhci_intr1(sc); 1694 mutex_spin_exit(&sc->sc_intr_lock); 1695 if (xfer->status != USBD_IN_PROGRESS) 1696 goto done; 1697 } 1698 } 1699 1700 /* Timeout */ 1701 DPRINTF(("uhci_waitintr: timeout\n")); 1702 for (ii = LIST_FIRST(&sc->sc_intrhead); 1703 ii != NULL && ii->xfer != xfer; 1704 ii = LIST_NEXT(ii, list)) 1705 ; 1706 #ifdef DIAGNOSTIC 1707 if (ii == NULL) 1708 panic("uhci_waitintr: lost intr_info"); 1709 #endif 1710 uhci_idone(ii); 1711 1712 done: 1713 mutex_exit(&sc->sc_lock); 1714 } 1715 1716 void 1717 uhci_poll(struct usbd_bus *bus) 1718 { 1719 uhci_softc_t *sc = bus->hci_private; 1720 1721 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1722 mutex_spin_enter(&sc->sc_intr_lock); 1723 uhci_intr1(sc); 1724 mutex_spin_exit(&sc->sc_intr_lock); 1725 } 1726 } 1727 1728 void 1729 uhci_reset(uhci_softc_t *sc) 1730 { 1731 int n; 1732 1733 UHCICMD(sc, UHCI_CMD_HCRESET); 1734 /* The reset bit goes low when the controller is done. */ 1735 for (n = 0; n < UHCI_RESET_TIMEOUT && 1736 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1737 usb_delay_ms(&sc->sc_bus, 1); 1738 if (n >= UHCI_RESET_TIMEOUT) 1739 printf("%s: controller did not reset\n", 1740 device_xname(sc->sc_dev)); 1741 } 1742 1743 usbd_status 1744 uhci_run(uhci_softc_t *sc, int run, int locked) 1745 { 1746 int n, running; 1747 u_int16_t cmd; 1748 1749 run = run != 0; 1750 if (!locked) 1751 mutex_spin_enter(&sc->sc_intr_lock); 1752 DPRINTF(("uhci_run: setting run=%d\n", run)); 1753 cmd = UREAD2(sc, UHCI_CMD); 1754 if (run) 1755 cmd |= UHCI_CMD_RS; 1756 else 1757 cmd &= ~UHCI_CMD_RS; 1758 UHCICMD(sc, cmd); 1759 for(n = 0; n < 10; n++) { 1760 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1761 /* return when we've entered the state we want */ 1762 if (run == running) { 1763 if (!locked) 1764 mutex_spin_exit(&sc->sc_intr_lock); 1765 DPRINTF(("uhci_run: done cmd=0x%x sts=0x%x\n", 1766 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS))); 1767 return (USBD_NORMAL_COMPLETION); 1768 } 1769 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock); 1770 } 1771 if (!locked) 1772 mutex_spin_exit(&sc->sc_intr_lock); 1773 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1774 run ? "start" : "stop"); 1775 return (USBD_IOERROR); 1776 } 1777 1778 /* 1779 * Memory management routines. 1780 * uhci_alloc_std allocates TDs 1781 * uhci_alloc_sqh allocates QHs 1782 * These two routines do their own free list management, 1783 * partly for speed, partly because allocating DMAable memory 1784 * has page size granularaity so much memory would be wasted if 1785 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1786 */ 1787 1788 uhci_soft_td_t * 1789 uhci_alloc_std(uhci_softc_t *sc) 1790 { 1791 uhci_soft_td_t *std; 1792 usbd_status err; 1793 int i, offs; 1794 usb_dma_t dma; 1795 1796 if (sc->sc_freetds == NULL) { 1797 DPRINTFN(2,("uhci_alloc_std: allocating chunk\n")); 1798 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1799 UHCI_TD_ALIGN, &dma); 1800 if (err) 1801 return (0); 1802 for (i = 0; i < UHCI_STD_CHUNK; i++) { 1803 offs = i * UHCI_STD_SIZE; 1804 std = KERNADDR(&dma, offs); 1805 std->physaddr = DMAADDR(&dma, offs); 1806 std->dma = dma; 1807 std->offs = offs; 1808 std->link.std = sc->sc_freetds; 1809 sc->sc_freetds = std; 1810 } 1811 } 1812 std = sc->sc_freetds; 1813 sc->sc_freetds = std->link.std; 1814 memset(&std->td, 0, sizeof(uhci_td_t)); 1815 return std; 1816 } 1817 1818 void 1819 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1820 { 1821 #ifdef DIAGNOSTIC 1822 #define TD_IS_FREE 0x12345678 1823 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1824 printf("uhci_free_std: freeing free TD %p\n", std); 1825 return; 1826 } 1827 std->td.td_token = htole32(TD_IS_FREE); 1828 #endif 1829 std->link.std = sc->sc_freetds; 1830 sc->sc_freetds = std; 1831 } 1832 1833 uhci_soft_qh_t * 1834 uhci_alloc_sqh(uhci_softc_t *sc) 1835 { 1836 uhci_soft_qh_t *sqh; 1837 usbd_status err; 1838 int i, offs; 1839 usb_dma_t dma; 1840 1841 if (sc->sc_freeqhs == NULL) { 1842 DPRINTFN(2, ("uhci_alloc_sqh: allocating chunk\n")); 1843 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1844 UHCI_QH_ALIGN, &dma); 1845 if (err) 1846 return (0); 1847 for(i = 0; i < UHCI_SQH_CHUNK; i++) { 1848 offs = i * UHCI_SQH_SIZE; 1849 sqh = KERNADDR(&dma, offs); 1850 sqh->physaddr = DMAADDR(&dma, offs); 1851 sqh->dma = dma; 1852 sqh->offs = offs; 1853 sqh->hlink = sc->sc_freeqhs; 1854 sc->sc_freeqhs = sqh; 1855 } 1856 } 1857 sqh = sc->sc_freeqhs; 1858 sc->sc_freeqhs = sqh->hlink; 1859 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1860 return (sqh); 1861 } 1862 1863 void 1864 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1865 { 1866 sqh->hlink = sc->sc_freeqhs; 1867 sc->sc_freeqhs = sqh; 1868 } 1869 1870 void 1871 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1872 uhci_soft_td_t *stdend) 1873 { 1874 uhci_soft_td_t *p; 1875 1876 /* 1877 * to avoid race condition with the controller which may be looking 1878 * at this chain, we need to first invalidate all links, and 1879 * then wait for the controller to move to another queue 1880 */ 1881 for (p = std; p != stdend; p = p->link.std) { 1882 usb_syncmem(&p->dma, 1883 p->offs + offsetof(uhci_td_t, td_link), 1884 sizeof(p->td.td_link), 1885 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1886 if ((p->td.td_link & UHCI_PTR_T) == 0) { 1887 p->td.td_link = UHCI_PTR_T; 1888 usb_syncmem(&p->dma, 1889 p->offs + offsetof(uhci_td_t, td_link), 1890 sizeof(p->td.td_link), 1891 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1892 } 1893 } 1894 delay(UHCI_QH_REMOVE_DELAY); 1895 1896 for (; std != stdend; std = p) { 1897 p = std->link.std; 1898 uhci_free_std(sc, std); 1899 } 1900 } 1901 1902 usbd_status 1903 uhci_alloc_std_chain(struct uhci_pipe *upipe, uhci_softc_t *sc, int len, 1904 int rd, u_int16_t flags, usb_dma_t *dma, 1905 uhci_soft_td_t **sp, uhci_soft_td_t **ep) 1906 { 1907 uhci_soft_td_t *p, *lastp; 1908 uhci_physaddr_t lastlink; 1909 int i, ntd, l, tog, maxp; 1910 u_int32_t status; 1911 int addr = upipe->pipe.device->address; 1912 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 1913 1914 DPRINTFN(8, ("uhci_alloc_std_chain: addr=%d endpt=%d len=%d speed=%d " 1915 "flags=0x%x\n", addr, UE_GET_ADDR(endpt), len, 1916 upipe->pipe.device->speed, flags)); 1917 1918 KASSERT(mutex_owned(&sc->sc_lock)); 1919 1920 maxp = UGETW(upipe->pipe.endpoint->edesc->wMaxPacketSize); 1921 if (maxp == 0) { 1922 printf("uhci_alloc_std_chain: maxp=0\n"); 1923 return (USBD_INVAL); 1924 } 1925 ntd = (len + maxp - 1) / maxp; 1926 if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0) 1927 ntd++; 1928 DPRINTFN(10, ("uhci_alloc_std_chain: maxp=%d ntd=%d\n", maxp, ntd)); 1929 if (ntd == 0) { 1930 *sp = *ep = 0; 1931 DPRINTFN(-1,("uhci_alloc_std_chain: ntd=0\n")); 1932 return (USBD_NORMAL_COMPLETION); 1933 } 1934 tog = upipe->nexttoggle; 1935 if (ntd % 2 == 0) 1936 tog ^= 1; 1937 upipe->nexttoggle = tog ^ 1; 1938 lastp = NULL; 1939 lastlink = UHCI_PTR_T; 1940 ntd--; 1941 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 1942 if (upipe->pipe.device->speed == USB_SPEED_LOW) 1943 status |= UHCI_TD_LS; 1944 if (flags & USBD_SHORT_XFER_OK) 1945 status |= UHCI_TD_SPD; 1946 usb_syncmem(dma, 0, len, 1947 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1948 for (i = ntd; i >= 0; i--) { 1949 p = uhci_alloc_std(sc); 1950 if (p == NULL) { 1951 KASSERT(lastp != NULL); 1952 uhci_free_std_chain(sc, lastp, NULL); 1953 return (USBD_NOMEM); 1954 } 1955 p->link.std = lastp; 1956 p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD); 1957 lastp = p; 1958 lastlink = p->physaddr; 1959 p->td.td_status = htole32(status); 1960 if (i == ntd) { 1961 /* last TD */ 1962 l = len % maxp; 1963 if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER)) 1964 l = maxp; 1965 *ep = p; 1966 } else 1967 l = maxp; 1968 p->td.td_token = 1969 htole32(rd ? UHCI_TD_IN (l, endpt, addr, tog) : 1970 UHCI_TD_OUT(l, endpt, addr, tog)); 1971 p->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 1972 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 1973 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1974 tog ^= 1; 1975 } 1976 *sp = lastp; 1977 DPRINTFN(10, ("uhci_alloc_std_chain: nexttog=%d\n", 1978 upipe->nexttoggle)); 1979 return (USBD_NORMAL_COMPLETION); 1980 } 1981 1982 void 1983 uhci_device_clear_toggle(usbd_pipe_handle pipe) 1984 { 1985 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 1986 upipe->nexttoggle = 0; 1987 } 1988 1989 void 1990 uhci_noop(usbd_pipe_handle pipe) 1991 { 1992 } 1993 1994 usbd_status 1995 uhci_device_bulk_transfer(usbd_xfer_handle xfer) 1996 { 1997 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1998 usbd_status err; 1999 2000 /* Insert last in queue. */ 2001 mutex_enter(&sc->sc_lock); 2002 err = usb_insert_transfer(xfer); 2003 mutex_exit(&sc->sc_lock); 2004 if (err) 2005 return (err); 2006 2007 /* 2008 * Pipe isn't running (otherwise err would be USBD_INPROG), 2009 * so start it first. 2010 */ 2011 return (uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2012 } 2013 2014 usbd_status 2015 uhci_device_bulk_start(usbd_xfer_handle xfer) 2016 { 2017 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2018 usbd_device_handle dev = upipe->pipe.device; 2019 uhci_softc_t *sc = dev->bus->hci_private; 2020 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2021 uhci_soft_td_t *data, *dataend; 2022 uhci_soft_qh_t *sqh; 2023 usbd_status err; 2024 int len, isread, endpt; 2025 2026 DPRINTFN(3, ("uhci_device_bulk_start: xfer=%p len=%d flags=%d ii=%p\n", 2027 xfer, xfer->length, xfer->flags, ii)); 2028 2029 if (sc->sc_dying) 2030 return (USBD_IOERROR); 2031 2032 #ifdef DIAGNOSTIC 2033 if (xfer->rqflags & URQ_REQUEST) 2034 panic("uhci_device_bulk_transfer: a request"); 2035 #endif 2036 2037 mutex_enter(&sc->sc_lock); 2038 2039 len = xfer->length; 2040 endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2041 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2042 sqh = upipe->u.bulk.sqh; 2043 2044 upipe->u.bulk.isread = isread; 2045 upipe->u.bulk.length = len; 2046 2047 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->flags, 2048 &xfer->dmabuf, &data, &dataend); 2049 if (err) { 2050 mutex_exit(&sc->sc_lock); 2051 return (err); 2052 } 2053 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2054 usb_syncmem(&dataend->dma, 2055 dataend->offs + offsetof(uhci_td_t, td_status), 2056 sizeof(dataend->td.td_status), 2057 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2058 2059 2060 #ifdef UHCI_DEBUG 2061 if (uhcidebug > 8) { 2062 DPRINTF(("uhci_device_bulk_transfer: data(1)\n")); 2063 uhci_dump_tds(data); 2064 } 2065 #endif 2066 2067 /* Set up interrupt info. */ 2068 ii->xfer = xfer; 2069 ii->stdstart = data; 2070 ii->stdend = dataend; 2071 #ifdef DIAGNOSTIC 2072 if (!ii->isdone) { 2073 printf("uhci_device_bulk_transfer: not done, ii=%p\n", ii); 2074 } 2075 ii->isdone = 0; 2076 #endif 2077 2078 sqh->elink = data; 2079 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2080 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2081 2082 uhci_add_bulk(sc, sqh); 2083 uhci_add_intr_info(sc, ii); 2084 2085 if (xfer->timeout && !sc->sc_bus.use_polling) { 2086 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 2087 uhci_timeout, ii); 2088 } 2089 xfer->status = USBD_IN_PROGRESS; 2090 2091 #ifdef UHCI_DEBUG 2092 if (uhcidebug > 10) { 2093 DPRINTF(("uhci_device_bulk_transfer: data(2)\n")); 2094 uhci_dump_tds(data); 2095 } 2096 #endif 2097 2098 if (sc->sc_bus.use_polling) 2099 uhci_waitintr(sc, xfer); 2100 2101 mutex_exit(&sc->sc_lock); 2102 return (USBD_IN_PROGRESS); 2103 } 2104 2105 /* Abort a device bulk request. */ 2106 void 2107 uhci_device_bulk_abort(usbd_xfer_handle xfer) 2108 { 2109 #ifdef DIAGNOSTIC 2110 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2111 #endif 2112 2113 KASSERT(mutex_owned(&sc->sc_lock)); 2114 2115 DPRINTF(("uhci_device_bulk_abort:\n")); 2116 uhci_abort_xfer(xfer, USBD_CANCELLED); 2117 } 2118 2119 /* 2120 * Abort a device request. 2121 * If this routine is called at splusb() it guarantees that the request 2122 * will be removed from the hardware scheduling and that the callback 2123 * for it will be called with USBD_CANCELLED status. 2124 * It's impossible to guarantee that the requested transfer will not 2125 * have happened since the hardware runs concurrently. 2126 * If the transaction has already happened we rely on the ordinary 2127 * interrupt processing to process it. 2128 * XXX This is most probably wrong. 2129 * XXXMRG this doesn't make sense anymore. 2130 */ 2131 void 2132 uhci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2133 { 2134 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2135 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2136 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 2137 uhci_soft_td_t *std; 2138 int wake; 2139 2140 DPRINTFN(1,("uhci_abort_xfer: xfer=%p, status=%d\n", xfer, status)); 2141 2142 KASSERT(mutex_owned(&sc->sc_lock)); 2143 2144 if (sc->sc_dying) { 2145 /* If we're dying, just do the software part. */ 2146 xfer->status = status; /* make software ignore it */ 2147 callout_stop(&xfer->timeout_handle); 2148 usb_transfer_complete(xfer); 2149 return; 2150 } 2151 2152 if (cpu_intr_p() || cpu_softintr_p()) 2153 panic("uhci_abort_xfer: not in process context"); 2154 2155 /* 2156 * If an abort is already in progress then just wait for it to 2157 * complete and return. 2158 */ 2159 if (xfer->hcflags & UXFER_ABORTING) { 2160 DPRINTFN(2, ("uhci_abort_xfer: already aborting\n")); 2161 #ifdef DIAGNOSTIC 2162 if (status == USBD_TIMEOUT) 2163 printf("uhci_abort_xfer: TIMEOUT while aborting\n"); 2164 #endif 2165 /* Override the status which might be USBD_TIMEOUT. */ 2166 xfer->status = status; 2167 DPRINTFN(2, ("uhci_abort_xfer: waiting for abort to finish\n")); 2168 xfer->hcflags |= UXFER_ABORTWAIT; 2169 while (xfer->hcflags & UXFER_ABORTING) 2170 cv_wait(&xfer->hccv, &sc->sc_lock); 2171 goto done; 2172 } 2173 xfer->hcflags |= UXFER_ABORTING; 2174 2175 /* 2176 * Step 1: Make interrupt routine and hardware ignore xfer. 2177 */ 2178 xfer->status = status; /* make software ignore it */ 2179 callout_stop(&xfer->timeout_handle); 2180 DPRINTFN(1,("uhci_abort_xfer: stop ii=%p\n", ii)); 2181 for (std = ii->stdstart; std != NULL; std = std->link.std) { 2182 usb_syncmem(&std->dma, 2183 std->offs + offsetof(uhci_td_t, td_status), 2184 sizeof(std->td.td_status), 2185 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2186 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2187 usb_syncmem(&std->dma, 2188 std->offs + offsetof(uhci_td_t, td_status), 2189 sizeof(std->td.td_status), 2190 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2191 } 2192 2193 /* 2194 * Step 2: Wait until we know hardware has finished any possible 2195 * use of the xfer. Also make sure the soft interrupt routine 2196 * has run. 2197 */ 2198 /* Hardware finishes in 1ms */ 2199 usb_delay_ms_locked(upipe->pipe.device->bus, 2, &sc->sc_lock); 2200 sc->sc_softwake = 1; 2201 usb_schedsoftintr(&sc->sc_bus); 2202 DPRINTFN(1,("uhci_abort_xfer: cv_wait\n")); 2203 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2204 2205 /* 2206 * Step 3: Execute callback. 2207 */ 2208 DPRINTFN(1,("uhci_abort_xfer: callback\n")); 2209 #ifdef DIAGNOSTIC 2210 ii->isdone = 1; 2211 #endif 2212 wake = xfer->hcflags & UXFER_ABORTWAIT; 2213 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2214 usb_transfer_complete(xfer); 2215 if (wake) 2216 cv_broadcast(&xfer->hccv); 2217 done: 2218 KASSERT(mutex_owned(&sc->sc_lock)); 2219 } 2220 2221 /* Close a device bulk pipe. */ 2222 void 2223 uhci_device_bulk_close(usbd_pipe_handle pipe) 2224 { 2225 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2226 usbd_device_handle dev = upipe->pipe.device; 2227 uhci_softc_t *sc = dev->bus->hci_private; 2228 2229 KASSERT(mutex_owned(&sc->sc_lock)); 2230 2231 uhci_free_sqh(sc, upipe->u.bulk.sqh); 2232 2233 pipe->endpoint->datatoggle = upipe->nexttoggle; 2234 } 2235 2236 usbd_status 2237 uhci_device_ctrl_transfer(usbd_xfer_handle xfer) 2238 { 2239 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2240 usbd_status err; 2241 2242 /* Insert last in queue. */ 2243 mutex_enter(&sc->sc_lock); 2244 err = usb_insert_transfer(xfer); 2245 mutex_exit(&sc->sc_lock); 2246 if (err) 2247 return (err); 2248 2249 /* 2250 * Pipe isn't running (otherwise err would be USBD_INPROG), 2251 * so start it first. 2252 */ 2253 return (uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2254 } 2255 2256 usbd_status 2257 uhci_device_ctrl_start(usbd_xfer_handle xfer) 2258 { 2259 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2260 usbd_status err; 2261 2262 if (sc->sc_dying) 2263 return (USBD_IOERROR); 2264 2265 #ifdef DIAGNOSTIC 2266 if (!(xfer->rqflags & URQ_REQUEST)) 2267 panic("uhci_device_ctrl_transfer: not a request"); 2268 #endif 2269 2270 mutex_enter(&sc->sc_lock); 2271 err = uhci_device_request(xfer); 2272 mutex_exit(&sc->sc_lock); 2273 if (err) 2274 return (err); 2275 2276 if (sc->sc_bus.use_polling) 2277 uhci_waitintr(sc, xfer); 2278 return (USBD_IN_PROGRESS); 2279 } 2280 2281 usbd_status 2282 uhci_device_intr_transfer(usbd_xfer_handle xfer) 2283 { 2284 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2285 usbd_status err; 2286 2287 /* Insert last in queue. */ 2288 mutex_enter(&sc->sc_lock); 2289 err = usb_insert_transfer(xfer); 2290 mutex_exit(&sc->sc_lock); 2291 if (err) 2292 return (err); 2293 2294 /* 2295 * Pipe isn't running (otherwise err would be USBD_INPROG), 2296 * so start it first. 2297 */ 2298 return (uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2299 } 2300 2301 usbd_status 2302 uhci_device_intr_start(usbd_xfer_handle xfer) 2303 { 2304 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2305 usbd_device_handle dev = upipe->pipe.device; 2306 uhci_softc_t *sc = dev->bus->hci_private; 2307 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2308 uhci_soft_td_t *data, *dataend; 2309 uhci_soft_qh_t *sqh; 2310 usbd_status err; 2311 int isread, endpt; 2312 int i; 2313 2314 if (sc->sc_dying) 2315 return (USBD_IOERROR); 2316 2317 DPRINTFN(3,("uhci_device_intr_transfer: xfer=%p len=%d flags=%d\n", 2318 xfer, xfer->length, xfer->flags)); 2319 2320 #ifdef DIAGNOSTIC 2321 if (xfer->rqflags & URQ_REQUEST) 2322 panic("uhci_device_intr_transfer: a request"); 2323 #endif 2324 2325 mutex_enter(&sc->sc_lock); 2326 2327 endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2328 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2329 2330 upipe->u.intr.isread = isread; 2331 2332 err = uhci_alloc_std_chain(upipe, sc, xfer->length, isread, 2333 xfer->flags, &xfer->dmabuf, &data, 2334 &dataend); 2335 if (err) { 2336 mutex_exit(&sc->sc_lock); 2337 return (err); 2338 } 2339 2340 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2341 usb_syncmem(&dataend->dma, 2342 dataend->offs + offsetof(uhci_td_t, td_status), 2343 sizeof(dataend->td.td_status), 2344 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2345 2346 #ifdef UHCI_DEBUG 2347 if (uhcidebug > 10) { 2348 DPRINTF(("uhci_device_intr_transfer: data(1)\n")); 2349 uhci_dump_tds(data); 2350 uhci_dump_qh(upipe->u.intr.qhs[0]); 2351 } 2352 #endif 2353 2354 /* Set up interrupt info. */ 2355 ii->xfer = xfer; 2356 ii->stdstart = data; 2357 ii->stdend = dataend; 2358 #ifdef DIAGNOSTIC 2359 if (!ii->isdone) { 2360 printf("uhci_device_intr_transfer: not done, ii=%p\n", ii); 2361 } 2362 ii->isdone = 0; 2363 #endif 2364 2365 DPRINTFN(10,("uhci_device_intr_transfer: qhs[0]=%p\n", 2366 upipe->u.intr.qhs[0])); 2367 for (i = 0; i < upipe->u.intr.npoll; i++) { 2368 sqh = upipe->u.intr.qhs[i]; 2369 sqh->elink = data; 2370 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2371 usb_syncmem(&sqh->dma, 2372 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2373 sizeof(sqh->qh.qh_elink), 2374 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2375 } 2376 uhci_add_intr_info(sc, ii); 2377 xfer->status = USBD_IN_PROGRESS; 2378 mutex_exit(&sc->sc_lock); 2379 2380 #ifdef UHCI_DEBUG 2381 if (uhcidebug > 10) { 2382 DPRINTF(("uhci_device_intr_transfer: data(2)\n")); 2383 uhci_dump_tds(data); 2384 uhci_dump_qh(upipe->u.intr.qhs[0]); 2385 } 2386 #endif 2387 2388 return (USBD_IN_PROGRESS); 2389 } 2390 2391 /* Abort a device control request. */ 2392 void 2393 uhci_device_ctrl_abort(usbd_xfer_handle xfer) 2394 { 2395 #ifdef DIAGNOSTIC 2396 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2397 #endif 2398 2399 KASSERT(mutex_owned(&sc->sc_lock)); 2400 2401 DPRINTF(("uhci_device_ctrl_abort:\n")); 2402 uhci_abort_xfer(xfer, USBD_CANCELLED); 2403 } 2404 2405 /* Close a device control pipe. */ 2406 void 2407 uhci_device_ctrl_close(usbd_pipe_handle pipe) 2408 { 2409 } 2410 2411 /* Abort a device interrupt request. */ 2412 void 2413 uhci_device_intr_abort(usbd_xfer_handle xfer) 2414 { 2415 #ifdef DIAGNOSTIC 2416 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2417 #endif 2418 2419 KASSERT(mutex_owned(&sc->sc_lock)); 2420 2421 DPRINTFN(1,("uhci_device_intr_abort: xfer=%p\n", xfer)); 2422 if (xfer->pipe->intrxfer == xfer) { 2423 DPRINTFN(1,("uhci_device_intr_abort: remove\n")); 2424 xfer->pipe->intrxfer = NULL; 2425 } 2426 uhci_abort_xfer(xfer, USBD_CANCELLED); 2427 } 2428 2429 /* Close a device interrupt pipe. */ 2430 void 2431 uhci_device_intr_close(usbd_pipe_handle pipe) 2432 { 2433 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2434 uhci_softc_t *sc = pipe->device->bus->hci_private; 2435 int i, npoll; 2436 2437 KASSERT(mutex_owned(&sc->sc_lock)); 2438 2439 /* Unlink descriptors from controller data structures. */ 2440 npoll = upipe->u.intr.npoll; 2441 for (i = 0; i < npoll; i++) 2442 uhci_remove_intr(sc, upipe->u.intr.qhs[i]); 2443 2444 /* 2445 * We now have to wait for any activity on the physical 2446 * descriptors to stop. 2447 */ 2448 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2449 2450 for(i = 0; i < npoll; i++) 2451 uhci_free_sqh(sc, upipe->u.intr.qhs[i]); 2452 kmem_free(upipe->u.intr.qhs, npoll * sizeof(uhci_soft_qh_t *)); 2453 2454 /* XXX free other resources */ 2455 } 2456 2457 usbd_status 2458 uhci_device_request(usbd_xfer_handle xfer) 2459 { 2460 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2461 usb_device_request_t *req = &xfer->request; 2462 usbd_device_handle dev = upipe->pipe.device; 2463 uhci_softc_t *sc = dev->bus->hci_private; 2464 int addr = dev->address; 2465 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2466 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2467 uhci_soft_td_t *setup, *data, *stat, *next, *dataend; 2468 uhci_soft_qh_t *sqh; 2469 int len; 2470 u_int32_t ls; 2471 usbd_status err; 2472 int isread; 2473 2474 KASSERT(mutex_owned(&sc->sc_lock)); 2475 2476 DPRINTFN(3,("uhci_device_control type=0x%02x, request=0x%02x, " 2477 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 2478 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2479 UGETW(req->wIndex), UGETW(req->wLength), 2480 addr, endpt)); 2481 2482 ls = dev->speed == USB_SPEED_LOW ? UHCI_TD_LS : 0; 2483 isread = req->bmRequestType & UT_READ; 2484 len = UGETW(req->wLength); 2485 2486 setup = upipe->u.ctl.setup; 2487 stat = upipe->u.ctl.stat; 2488 sqh = upipe->u.ctl.sqh; 2489 2490 /* Set up data transaction */ 2491 if (len != 0) { 2492 upipe->nexttoggle = 1; 2493 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->flags, 2494 &xfer->dmabuf, &data, &dataend); 2495 if (err) 2496 return (err); 2497 next = data; 2498 dataend->link.std = stat; 2499 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_VF | UHCI_PTR_TD); 2500 usb_syncmem(&dataend->dma, 2501 dataend->offs + offsetof(uhci_td_t, td_link), 2502 sizeof(dataend->td.td_link), 2503 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2504 } else { 2505 next = stat; 2506 } 2507 upipe->u.ctl.length = len; 2508 2509 memcpy(KERNADDR(&upipe->u.ctl.reqdma, 0), req, sizeof *req); 2510 usb_syncmem(&upipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 2511 2512 setup->link.std = next; 2513 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_VF | UHCI_PTR_TD); 2514 setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2515 UHCI_TD_ACTIVE); 2516 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof *req, endpt, addr)); 2517 setup->td.td_buffer = htole32(DMAADDR(&upipe->u.ctl.reqdma, 0)); 2518 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2519 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2520 2521 stat->link.std = NULL; 2522 stat->td.td_link = htole32(UHCI_PTR_T); 2523 stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2524 UHCI_TD_ACTIVE | UHCI_TD_IOC); 2525 stat->td.td_token = 2526 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2527 UHCI_TD_IN (0, endpt, addr, 1)); 2528 stat->td.td_buffer = htole32(0); 2529 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2530 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2531 2532 #ifdef UHCI_DEBUG 2533 if (uhcidebug > 10) { 2534 DPRINTF(("uhci_device_request: before transfer\n")); 2535 uhci_dump_tds(setup); 2536 } 2537 #endif 2538 2539 /* Set up interrupt info. */ 2540 ii->xfer = xfer; 2541 ii->stdstart = setup; 2542 ii->stdend = stat; 2543 #ifdef DIAGNOSTIC 2544 if (!ii->isdone) { 2545 printf("uhci_device_request: not done, ii=%p\n", ii); 2546 } 2547 ii->isdone = 0; 2548 #endif 2549 2550 sqh->elink = setup; 2551 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2552 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2553 2554 if (dev->speed == USB_SPEED_LOW) 2555 uhci_add_ls_ctrl(sc, sqh); 2556 else 2557 uhci_add_hs_ctrl(sc, sqh); 2558 uhci_add_intr_info(sc, ii); 2559 #ifdef UHCI_DEBUG 2560 if (uhcidebug > 12) { 2561 uhci_soft_td_t *std; 2562 uhci_soft_qh_t *xqh; 2563 uhci_soft_qh_t *sxqh; 2564 int maxqh = 0; 2565 uhci_physaddr_t link; 2566 DPRINTF(("uhci_enter_ctl_q: follow from [0]\n")); 2567 for (std = sc->sc_vframes[0].htd, link = 0; 2568 (link & UHCI_PTR_QH) == 0; 2569 std = std->link.std) { 2570 link = le32toh(std->td.td_link); 2571 uhci_dump_td(std); 2572 } 2573 sxqh = (uhci_soft_qh_t *)std; 2574 uhci_dump_qh(sxqh); 2575 for (xqh = sxqh; 2576 xqh != NULL; 2577 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2578 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2579 uhci_dump_qh(xqh); 2580 } 2581 DPRINTF(("Enqueued QH:\n")); 2582 uhci_dump_qh(sqh); 2583 uhci_dump_tds(sqh->elink); 2584 } 2585 #endif 2586 if (xfer->timeout && !sc->sc_bus.use_polling) { 2587 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 2588 uhci_timeout, ii); 2589 } 2590 xfer->status = USBD_IN_PROGRESS; 2591 2592 return (USBD_NORMAL_COMPLETION); 2593 } 2594 2595 usbd_status 2596 uhci_device_isoc_transfer(usbd_xfer_handle xfer) 2597 { 2598 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2599 usbd_status err; 2600 2601 DPRINTFN(5,("uhci_device_isoc_transfer: xfer=%p\n", xfer)); 2602 2603 /* Put it on our queue, */ 2604 mutex_enter(&sc->sc_lock); 2605 err = usb_insert_transfer(xfer); 2606 mutex_exit(&sc->sc_lock); 2607 2608 /* bail out on error, */ 2609 if (err && err != USBD_IN_PROGRESS) 2610 return (err); 2611 2612 /* XXX should check inuse here */ 2613 2614 /* insert into schedule, */ 2615 uhci_device_isoc_enter(xfer); 2616 2617 /* and start if the pipe wasn't running */ 2618 if (!err) 2619 uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 2620 2621 return (err); 2622 } 2623 2624 void 2625 uhci_device_isoc_enter(usbd_xfer_handle xfer) 2626 { 2627 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2628 usbd_device_handle dev = upipe->pipe.device; 2629 uhci_softc_t *sc = dev->bus->hci_private; 2630 struct iso *iso = &upipe->u.iso; 2631 uhci_soft_td_t *std; 2632 u_int32_t buf, len, status, offs; 2633 int i, next, nframes; 2634 int rd = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2635 2636 DPRINTFN(5,("uhci_device_isoc_enter: used=%d next=%d xfer=%p " 2637 "nframes=%d\n", 2638 iso->inuse, iso->next, xfer, xfer->nframes)); 2639 2640 if (sc->sc_dying) 2641 return; 2642 2643 if (xfer->status == USBD_IN_PROGRESS) { 2644 /* This request has already been entered into the frame list */ 2645 printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer); 2646 /* XXX */ 2647 } 2648 2649 #ifdef DIAGNOSTIC 2650 if (iso->inuse >= UHCI_VFRAMELIST_COUNT) 2651 printf("uhci_device_isoc_enter: overflow!\n"); 2652 #endif 2653 2654 next = iso->next; 2655 if (next == -1) { 2656 /* Not in use yet, schedule it a few frames ahead. */ 2657 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 2658 DPRINTFN(2,("uhci_device_isoc_enter: start next=%d\n", next)); 2659 } 2660 2661 xfer->status = USBD_IN_PROGRESS; 2662 UXFER(xfer)->curframe = next; 2663 2664 buf = DMAADDR(&xfer->dmabuf, 0); 2665 offs = 0; 2666 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 2667 UHCI_TD_ACTIVE | 2668 UHCI_TD_IOS); 2669 nframes = xfer->nframes; 2670 mutex_enter(&sc->sc_lock); 2671 for (i = 0; i < nframes; i++) { 2672 std = iso->stds[next]; 2673 if (++next >= UHCI_VFRAMELIST_COUNT) 2674 next = 0; 2675 len = xfer->frlengths[i]; 2676 std->td.td_buffer = htole32(buf); 2677 usb_syncmem(&xfer->dmabuf, offs, len, 2678 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2679 if (i == nframes - 1) 2680 status |= UHCI_TD_IOC; 2681 std->td.td_status = htole32(status); 2682 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2683 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 2684 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2685 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2686 #ifdef UHCI_DEBUG 2687 if (uhcidebug > 5) { 2688 DPRINTFN(5,("uhci_device_isoc_enter: TD %d\n", i)); 2689 uhci_dump_td(std); 2690 } 2691 #endif 2692 buf += len; 2693 offs += len; 2694 } 2695 iso->next = next; 2696 iso->inuse += xfer->nframes; 2697 2698 mutex_exit(&sc->sc_lock); 2699 } 2700 2701 usbd_status 2702 uhci_device_isoc_start(usbd_xfer_handle xfer) 2703 { 2704 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2705 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 2706 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2707 uhci_soft_td_t *end; 2708 int i; 2709 2710 DPRINTFN(5,("uhci_device_isoc_start: xfer=%p\n", xfer)); 2711 2712 mutex_enter(&sc->sc_lock); 2713 2714 if (sc->sc_dying) { 2715 mutex_exit(&sc->sc_lock); 2716 return (USBD_IOERROR); 2717 } 2718 2719 #ifdef DIAGNOSTIC 2720 if (xfer->status != USBD_IN_PROGRESS) 2721 printf("uhci_device_isoc_start: not in progress %p\n", xfer); 2722 #endif 2723 2724 /* Find the last TD */ 2725 i = UXFER(xfer)->curframe + xfer->nframes; 2726 if (i >= UHCI_VFRAMELIST_COUNT) 2727 i -= UHCI_VFRAMELIST_COUNT; 2728 end = upipe->u.iso.stds[i]; 2729 2730 #ifdef DIAGNOSTIC 2731 if (end == NULL) { 2732 printf("uhci_device_isoc_start: end == NULL\n"); 2733 return (USBD_INVAL); 2734 } 2735 #endif 2736 2737 /* Set up interrupt info. */ 2738 ii->xfer = xfer; 2739 ii->stdstart = end; 2740 ii->stdend = end; 2741 #ifdef DIAGNOSTIC 2742 if (!ii->isdone) 2743 printf("uhci_device_isoc_start: not done, ii=%p\n", ii); 2744 ii->isdone = 0; 2745 #endif 2746 uhci_add_intr_info(sc, ii); 2747 2748 mutex_exit(&sc->sc_lock); 2749 2750 return (USBD_IN_PROGRESS); 2751 } 2752 2753 void 2754 uhci_device_isoc_abort(usbd_xfer_handle xfer) 2755 { 2756 #ifdef DIAGNOSTIC 2757 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2758 #endif 2759 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2760 uhci_soft_td_t **stds = upipe->u.iso.stds; 2761 uhci_soft_td_t *std; 2762 int i, n, nframes, maxlen, len; 2763 2764 KASSERT(mutex_owned(&sc->sc_lock)); 2765 2766 /* Transfer is already done. */ 2767 if (xfer->status != USBD_NOT_STARTED && 2768 xfer->status != USBD_IN_PROGRESS) { 2769 return; 2770 } 2771 2772 /* Give xfer the requested abort code. */ 2773 xfer->status = USBD_CANCELLED; 2774 2775 /* make hardware ignore it, */ 2776 nframes = xfer->nframes; 2777 n = UXFER(xfer)->curframe; 2778 maxlen = 0; 2779 for (i = 0; i < nframes; i++) { 2780 std = stds[n]; 2781 usb_syncmem(&std->dma, 2782 std->offs + offsetof(uhci_td_t, td_status), 2783 sizeof(std->td.td_status), 2784 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2785 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2786 usb_syncmem(&std->dma, 2787 std->offs + offsetof(uhci_td_t, td_status), 2788 sizeof(std->td.td_status), 2789 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2790 usb_syncmem(&std->dma, 2791 std->offs + offsetof(uhci_td_t, td_token), 2792 sizeof(std->td.td_token), 2793 BUS_DMASYNC_POSTWRITE); 2794 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 2795 if (len > maxlen) 2796 maxlen = len; 2797 if (++n >= UHCI_VFRAMELIST_COUNT) 2798 n = 0; 2799 } 2800 2801 /* and wait until we are sure the hardware has finished. */ 2802 delay(maxlen); 2803 2804 #ifdef DIAGNOSTIC 2805 UXFER(xfer)->iinfo.isdone = 1; 2806 #endif 2807 /* Run callback and remove from interrupt list. */ 2808 usb_transfer_complete(xfer); 2809 2810 KASSERT(mutex_owned(&sc->sc_lock)); 2811 } 2812 2813 void 2814 uhci_device_isoc_close(usbd_pipe_handle pipe) 2815 { 2816 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2817 usbd_device_handle dev = upipe->pipe.device; 2818 uhci_softc_t *sc = dev->bus->hci_private; 2819 uhci_soft_td_t *std, *vstd; 2820 struct iso *iso; 2821 int i; 2822 2823 KASSERT(mutex_owned(&sc->sc_lock)); 2824 2825 /* 2826 * Make sure all TDs are marked as inactive. 2827 * Wait for completion. 2828 * Unschedule. 2829 * Deallocate. 2830 */ 2831 iso = &upipe->u.iso; 2832 2833 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2834 std = iso->stds[i]; 2835 usb_syncmem(&std->dma, 2836 std->offs + offsetof(uhci_td_t, td_status), 2837 sizeof(std->td.td_status), 2838 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2839 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 2840 usb_syncmem(&std->dma, 2841 std->offs + offsetof(uhci_td_t, td_status), 2842 sizeof(std->td.td_status), 2843 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2844 } 2845 /* wait for completion */ 2846 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2847 2848 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2849 std = iso->stds[i]; 2850 for (vstd = sc->sc_vframes[i].htd; 2851 vstd != NULL && vstd->link.std != std; 2852 vstd = vstd->link.std) 2853 ; 2854 if (vstd == NULL) { 2855 /*panic*/ 2856 printf("uhci_device_isoc_close: %p not found\n", std); 2857 mutex_exit(&sc->sc_lock); 2858 return; 2859 } 2860 vstd->link = std->link; 2861 usb_syncmem(&std->dma, 2862 std->offs + offsetof(uhci_td_t, td_link), 2863 sizeof(std->td.td_link), 2864 BUS_DMASYNC_POSTWRITE); 2865 vstd->td.td_link = std->td.td_link; 2866 usb_syncmem(&vstd->dma, 2867 vstd->offs + offsetof(uhci_td_t, td_link), 2868 sizeof(vstd->td.td_link), 2869 BUS_DMASYNC_PREWRITE); 2870 uhci_free_std(sc, std); 2871 } 2872 2873 kmem_free(iso->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *)); 2874 } 2875 2876 usbd_status 2877 uhci_setup_isoc(usbd_pipe_handle pipe) 2878 { 2879 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2880 usbd_device_handle dev = upipe->pipe.device; 2881 uhci_softc_t *sc = dev->bus->hci_private; 2882 int addr = upipe->pipe.device->address; 2883 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2884 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 2885 uhci_soft_td_t *std, *vstd; 2886 u_int32_t token; 2887 struct iso *iso; 2888 int i; 2889 2890 iso = &upipe->u.iso; 2891 iso->stds = kmem_alloc(UHCI_VFRAMELIST_COUNT * 2892 sizeof (uhci_soft_td_t *), 2893 KM_SLEEP); 2894 if (iso->stds == NULL) 2895 return USBD_NOMEM; 2896 2897 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 2898 UHCI_TD_OUT(0, endpt, addr, 0); 2899 2900 mutex_enter(&sc->sc_lock); 2901 2902 /* Allocate the TDs and mark as inactive; */ 2903 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2904 std = uhci_alloc_std(sc); 2905 if (std == 0) 2906 goto bad; 2907 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 2908 std->td.td_token = htole32(token); 2909 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2910 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2911 iso->stds[i] = std; 2912 } 2913 2914 /* Insert TDs into schedule. */ 2915 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2916 std = iso->stds[i]; 2917 vstd = sc->sc_vframes[i].htd; 2918 usb_syncmem(&vstd->dma, 2919 vstd->offs + offsetof(uhci_td_t, td_link), 2920 sizeof(vstd->td.td_link), 2921 BUS_DMASYNC_POSTWRITE); 2922 std->link = vstd->link; 2923 std->td.td_link = vstd->td.td_link; 2924 usb_syncmem(&std->dma, 2925 std->offs + offsetof(uhci_td_t, td_link), 2926 sizeof(std->td.td_link), 2927 BUS_DMASYNC_PREWRITE); 2928 vstd->link.std = std; 2929 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 2930 usb_syncmem(&vstd->dma, 2931 vstd->offs + offsetof(uhci_td_t, td_link), 2932 sizeof(vstd->td.td_link), 2933 BUS_DMASYNC_PREWRITE); 2934 } 2935 mutex_exit(&sc->sc_lock); 2936 2937 iso->next = -1; 2938 iso->inuse = 0; 2939 2940 return (USBD_NORMAL_COMPLETION); 2941 2942 bad: 2943 while (--i >= 0) 2944 uhci_free_std(sc, iso->stds[i]); 2945 mutex_exit(&sc->sc_lock); 2946 kmem_free(iso->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *)); 2947 return (USBD_NOMEM); 2948 } 2949 2950 void 2951 uhci_device_isoc_done(usbd_xfer_handle xfer) 2952 { 2953 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2954 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2955 int i, offs; 2956 int rd = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2957 2958 2959 DPRINTFN(4, ("uhci_isoc_done: length=%d, busy_free=0x%08x\n", 2960 xfer->actlen, xfer->busy_free)); 2961 2962 if (ii->xfer != xfer) 2963 /* Not on interrupt list, ignore it. */ 2964 return; 2965 2966 if (!uhci_active_intr_info(ii)) 2967 return; 2968 2969 #ifdef DIAGNOSTIC 2970 if (ii->stdend == NULL) { 2971 printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer); 2972 #ifdef UHCI_DEBUG 2973 uhci_dump_ii(ii); 2974 #endif 2975 return; 2976 } 2977 #endif 2978 2979 /* Turn off the interrupt since it is active even if the TD is not. */ 2980 usb_syncmem(&ii->stdend->dma, 2981 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2982 sizeof(ii->stdend->td.td_status), 2983 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2984 ii->stdend->td.td_status &= htole32(~UHCI_TD_IOC); 2985 usb_syncmem(&ii->stdend->dma, 2986 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2987 sizeof(ii->stdend->td.td_status), 2988 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2989 2990 uhci_del_intr_info(ii); /* remove from active list */ 2991 2992 offs = 0; 2993 for (i = 0; i < xfer->nframes; i++) { 2994 usb_syncmem(&xfer->dmabuf, offs, xfer->frlengths[i], 2995 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2996 offs += xfer->frlengths[i]; 2997 } 2998 } 2999 3000 void 3001 uhci_device_intr_done(usbd_xfer_handle xfer) 3002 { 3003 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3004 uhci_softc_t *sc = ii->sc; 3005 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 3006 uhci_soft_qh_t *sqh; 3007 int i, npoll, isread; 3008 3009 DPRINTFN(5, ("uhci_device_intr_done: length=%d\n", xfer->actlen)); 3010 3011 KASSERT(mutex_owned(&sc->sc_lock)); 3012 3013 npoll = upipe->u.intr.npoll; 3014 for(i = 0; i < npoll; i++) { 3015 sqh = upipe->u.intr.qhs[i]; 3016 sqh->elink = NULL; 3017 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3018 usb_syncmem(&sqh->dma, 3019 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3020 sizeof(sqh->qh.qh_elink), 3021 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3022 } 3023 uhci_free_std_chain(sc, ii->stdstart, NULL); 3024 3025 isread = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 3026 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3027 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3028 3029 /* XXX Wasteful. */ 3030 if (xfer->pipe->repeat) { 3031 uhci_soft_td_t *data, *dataend; 3032 3033 DPRINTFN(5,("uhci_device_intr_done: requeing\n")); 3034 3035 /* This alloc cannot fail since we freed the chain above. */ 3036 uhci_alloc_std_chain(upipe, sc, xfer->length, 3037 upipe->u.intr.isread, xfer->flags, 3038 &xfer->dmabuf, &data, &dataend); 3039 dataend->td.td_status |= htole32(UHCI_TD_IOC); 3040 usb_syncmem(&dataend->dma, 3041 dataend->offs + offsetof(uhci_td_t, td_status), 3042 sizeof(dataend->td.td_status), 3043 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3044 3045 #ifdef UHCI_DEBUG 3046 if (uhcidebug > 10) { 3047 DPRINTF(("uhci_device_intr_done: data(1)\n")); 3048 uhci_dump_tds(data); 3049 uhci_dump_qh(upipe->u.intr.qhs[0]); 3050 } 3051 #endif 3052 3053 ii->stdstart = data; 3054 ii->stdend = dataend; 3055 #ifdef DIAGNOSTIC 3056 if (!ii->isdone) { 3057 printf("uhci_device_intr_done: not done, ii=%p\n", ii); 3058 } 3059 ii->isdone = 0; 3060 #endif 3061 for (i = 0; i < npoll; i++) { 3062 sqh = upipe->u.intr.qhs[i]; 3063 sqh->elink = data; 3064 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 3065 usb_syncmem(&sqh->dma, 3066 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3067 sizeof(sqh->qh.qh_elink), 3068 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3069 } 3070 xfer->status = USBD_IN_PROGRESS; 3071 /* The ii is already on the examined list, just leave it. */ 3072 } else { 3073 DPRINTFN(5,("uhci_device_intr_done: removing\n")); 3074 if (uhci_active_intr_info(ii)) 3075 uhci_del_intr_info(ii); 3076 } 3077 } 3078 3079 /* Deallocate request data structures */ 3080 void 3081 uhci_device_ctrl_done(usbd_xfer_handle xfer) 3082 { 3083 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3084 uhci_softc_t *sc = ii->sc; 3085 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 3086 int len = UGETW(xfer->request.wLength); 3087 int isread = (xfer->request.bmRequestType & UT_READ); 3088 3089 KASSERT(mutex_owned(&sc->sc_lock)); 3090 3091 #ifdef DIAGNOSTIC 3092 if (!(xfer->rqflags & URQ_REQUEST)) 3093 panic("uhci_device_ctrl_done: not a request"); 3094 #endif 3095 3096 if (!uhci_active_intr_info(ii)) 3097 return; 3098 3099 uhci_del_intr_info(ii); /* remove from active list */ 3100 3101 if (upipe->pipe.device->speed == USB_SPEED_LOW) 3102 uhci_remove_ls_ctrl(sc, upipe->u.ctl.sqh); 3103 else 3104 uhci_remove_hs_ctrl(sc, upipe->u.ctl.sqh); 3105 3106 if (upipe->u.ctl.length != 0) 3107 uhci_free_std_chain(sc, ii->stdstart->link.std, ii->stdend); 3108 3109 if (len) { 3110 usb_syncmem(&xfer->dmabuf, 0, len, 3111 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3112 } 3113 usb_syncmem(&upipe->u.ctl.reqdma, 0, 3114 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3115 3116 DPRINTFN(5, ("uhci_device_ctrl_done: length=%d\n", xfer->actlen)); 3117 } 3118 3119 /* Deallocate request data structures */ 3120 void 3121 uhci_device_bulk_done(usbd_xfer_handle xfer) 3122 { 3123 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3124 uhci_softc_t *sc = ii->sc; 3125 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 3126 3127 DPRINTFN(5,("uhci_device_bulk_done: xfer=%p ii=%p sc=%p upipe=%p\n", 3128 xfer, ii, sc, upipe)); 3129 3130 KASSERT(mutex_owned(&sc->sc_lock)); 3131 3132 if (!uhci_active_intr_info(ii)) 3133 return; 3134 3135 uhci_del_intr_info(ii); /* remove from active list */ 3136 3137 uhci_remove_bulk(sc, upipe->u.bulk.sqh); 3138 3139 uhci_free_std_chain(sc, ii->stdstart, NULL); 3140 3141 DPRINTFN(5, ("uhci_device_bulk_done: length=%d\n", xfer->actlen)); 3142 } 3143 3144 /* Add interrupt QH, called with vflock. */ 3145 void 3146 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3147 { 3148 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3149 uhci_soft_qh_t *eqh; 3150 3151 DPRINTFN(4, ("uhci_add_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3152 3153 eqh = vf->eqh; 3154 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3155 sizeof(eqh->qh.qh_hlink), 3156 BUS_DMASYNC_POSTWRITE); 3157 sqh->hlink = eqh->hlink; 3158 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3159 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3160 sizeof(sqh->qh.qh_hlink), 3161 BUS_DMASYNC_PREWRITE); 3162 eqh->hlink = sqh; 3163 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3164 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3165 sizeof(eqh->qh.qh_hlink), 3166 BUS_DMASYNC_PREWRITE); 3167 vf->eqh = sqh; 3168 vf->bandwidth++; 3169 } 3170 3171 /* Remove interrupt QH. */ 3172 void 3173 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3174 { 3175 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3176 uhci_soft_qh_t *pqh; 3177 3178 DPRINTFN(4, ("uhci_remove_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3179 3180 /* See comment in uhci_remove_ctrl() */ 3181 3182 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3183 sizeof(sqh->qh.qh_elink), 3184 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3185 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3186 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3187 usb_syncmem(&sqh->dma, 3188 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3189 sizeof(sqh->qh.qh_elink), 3190 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3191 delay(UHCI_QH_REMOVE_DELAY); 3192 } 3193 3194 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3195 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3196 sizeof(sqh->qh.qh_hlink), 3197 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3198 pqh->hlink = sqh->hlink; 3199 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3200 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3201 sizeof(pqh->qh.qh_hlink), 3202 BUS_DMASYNC_PREWRITE); 3203 delay(UHCI_QH_REMOVE_DELAY); 3204 if (vf->eqh == sqh) 3205 vf->eqh = pqh; 3206 vf->bandwidth--; 3207 } 3208 3209 usbd_status 3210 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3211 { 3212 uhci_soft_qh_t *sqh; 3213 int i, npoll; 3214 u_int bestbw, bw, bestoffs, offs; 3215 3216 DPRINTFN(2, ("uhci_device_setintr: pipe=%p\n", upipe)); 3217 if (ival == 0) { 3218 printf("uhci_device_setintr: 0 interval\n"); 3219 return (USBD_INVAL); 3220 } 3221 3222 if (ival > UHCI_VFRAMELIST_COUNT) 3223 ival = UHCI_VFRAMELIST_COUNT; 3224 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3225 DPRINTFN(2, ("uhci_device_setintr: ival=%d npoll=%d\n", ival, npoll)); 3226 3227 upipe->u.intr.npoll = npoll; 3228 upipe->u.intr.qhs = 3229 kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP); 3230 if (upipe->u.intr.qhs == NULL) 3231 return USBD_NOMEM; 3232 3233 /* 3234 * Figure out which offset in the schedule that has most 3235 * bandwidth left over. 3236 */ 3237 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3238 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3239 for (bw = i = 0; i < npoll; i++) 3240 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3241 if (bw < bestbw) { 3242 bestbw = bw; 3243 bestoffs = offs; 3244 } 3245 } 3246 DPRINTFN(1, ("uhci_device_setintr: bw=%d offs=%d\n", bestbw, bestoffs)); 3247 3248 mutex_enter(&sc->sc_lock); 3249 for(i = 0; i < npoll; i++) { 3250 upipe->u.intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3251 sqh->elink = NULL; 3252 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3253 usb_syncmem(&sqh->dma, 3254 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3255 sizeof(sqh->qh.qh_elink), 3256 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3257 sqh->pos = MOD(i * ival + bestoffs); 3258 } 3259 #undef MOD 3260 3261 /* Enter QHs into the controller data structures. */ 3262 for(i = 0; i < npoll; i++) 3263 uhci_add_intr(sc, upipe->u.intr.qhs[i]); 3264 mutex_exit(&sc->sc_lock); 3265 3266 DPRINTFN(5, ("uhci_device_setintr: returns %p\n", upipe)); 3267 return (USBD_NORMAL_COMPLETION); 3268 } 3269 3270 /* Open a new pipe. */ 3271 usbd_status 3272 uhci_open(usbd_pipe_handle pipe) 3273 { 3274 uhci_softc_t *sc = pipe->device->bus->hci_private; 3275 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 3276 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 3277 usbd_status err = USBD_NOMEM; 3278 int ival; 3279 3280 DPRINTFN(1, ("uhci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 3281 pipe, pipe->device->address, 3282 ed->bEndpointAddress, sc->sc_addr)); 3283 3284 if (sc->sc_dying) 3285 return USBD_IOERROR; 3286 3287 upipe->aborting = 0; 3288 /* toggle state needed for bulk endpoints */ 3289 upipe->nexttoggle = pipe->endpoint->datatoggle; 3290 3291 if (pipe->device->address == sc->sc_addr) { 3292 switch (ed->bEndpointAddress) { 3293 case USB_CONTROL_ENDPOINT: 3294 pipe->methods = &uhci_root_ctrl_methods; 3295 break; 3296 case UE_DIR_IN | UHCI_INTR_ENDPT: 3297 pipe->methods = &uhci_root_intr_methods; 3298 break; 3299 default: 3300 return (USBD_INVAL); 3301 } 3302 } else { 3303 switch (ed->bmAttributes & UE_XFERTYPE) { 3304 case UE_CONTROL: 3305 pipe->methods = &uhci_device_ctrl_methods; 3306 upipe->u.ctl.sqh = uhci_alloc_sqh(sc); 3307 if (upipe->u.ctl.sqh == NULL) 3308 goto bad; 3309 upipe->u.ctl.setup = uhci_alloc_std(sc); 3310 if (upipe->u.ctl.setup == NULL) { 3311 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3312 goto bad; 3313 } 3314 upipe->u.ctl.stat = uhci_alloc_std(sc); 3315 if (upipe->u.ctl.stat == NULL) { 3316 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3317 uhci_free_std(sc, upipe->u.ctl.setup); 3318 goto bad; 3319 } 3320 err = usb_allocmem(&sc->sc_bus, 3321 sizeof(usb_device_request_t), 3322 0, &upipe->u.ctl.reqdma); 3323 if (err) { 3324 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3325 uhci_free_std(sc, upipe->u.ctl.setup); 3326 uhci_free_std(sc, upipe->u.ctl.stat); 3327 goto bad; 3328 } 3329 break; 3330 case UE_INTERRUPT: 3331 pipe->methods = &uhci_device_intr_methods; 3332 ival = pipe->interval; 3333 if (ival == USBD_DEFAULT_INTERVAL) 3334 ival = ed->bInterval; 3335 return (uhci_device_setintr(sc, upipe, ival)); 3336 case UE_ISOCHRONOUS: 3337 pipe->methods = &uhci_device_isoc_methods; 3338 return (uhci_setup_isoc(pipe)); 3339 case UE_BULK: 3340 pipe->methods = &uhci_device_bulk_methods; 3341 upipe->u.bulk.sqh = uhci_alloc_sqh(sc); 3342 if (upipe->u.bulk.sqh == NULL) 3343 goto bad; 3344 break; 3345 } 3346 } 3347 return (USBD_NORMAL_COMPLETION); 3348 3349 bad: 3350 return USBD_NOMEM; 3351 } 3352 3353 /* 3354 * Data structures and routines to emulate the root hub. 3355 */ 3356 usb_device_descriptor_t uhci_devd = { 3357 USB_DEVICE_DESCRIPTOR_SIZE, 3358 UDESC_DEVICE, /* type */ 3359 {0x00, 0x01}, /* USB version */ 3360 UDCLASS_HUB, /* class */ 3361 UDSUBCLASS_HUB, /* subclass */ 3362 UDPROTO_FSHUB, /* protocol */ 3363 64, /* max packet */ 3364 {0},{0},{0x00,0x01}, /* device id */ 3365 1,2,0, /* string indicies */ 3366 1 /* # of configurations */ 3367 }; 3368 3369 const usb_config_descriptor_t uhci_confd = { 3370 USB_CONFIG_DESCRIPTOR_SIZE, 3371 UDESC_CONFIG, 3372 {USB_CONFIG_DESCRIPTOR_SIZE + 3373 USB_INTERFACE_DESCRIPTOR_SIZE + 3374 USB_ENDPOINT_DESCRIPTOR_SIZE}, 3375 1, 3376 1, 3377 0, 3378 UC_ATTR_MBO | UC_SELF_POWERED, 3379 0 /* max power */ 3380 }; 3381 3382 const usb_interface_descriptor_t uhci_ifcd = { 3383 USB_INTERFACE_DESCRIPTOR_SIZE, 3384 UDESC_INTERFACE, 3385 0, 3386 0, 3387 1, 3388 UICLASS_HUB, 3389 UISUBCLASS_HUB, 3390 UIPROTO_FSHUB, 3391 0 3392 }; 3393 3394 const usb_endpoint_descriptor_t uhci_endpd = { 3395 USB_ENDPOINT_DESCRIPTOR_SIZE, 3396 UDESC_ENDPOINT, 3397 UE_DIR_IN | UHCI_INTR_ENDPT, 3398 UE_INTERRUPT, 3399 {8}, 3400 255 3401 }; 3402 3403 const usb_hub_descriptor_t uhci_hubd_piix = { 3404 USB_HUB_DESCRIPTOR_SIZE, 3405 UDESC_HUB, 3406 2, 3407 { UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0 }, 3408 50, /* power on to power good */ 3409 0, 3410 { 0x00 }, /* both ports are removable */ 3411 { 0 }, 3412 }; 3413 3414 /* 3415 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3416 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3417 * should not be used by the USB subsystem. As we cannot issue a 3418 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3419 * will be enabled as part of the reset. 3420 * 3421 * On the VT83C572, the port cannot be successfully enabled until the 3422 * outstanding "port enable change" and "connection status change" 3423 * events have been reset. 3424 */ 3425 Static usbd_status 3426 uhci_portreset(uhci_softc_t *sc, int index) 3427 { 3428 int lim, port, x; 3429 3430 if (index == 1) 3431 port = UHCI_PORTSC1; 3432 else if (index == 2) 3433 port = UHCI_PORTSC2; 3434 else 3435 return (USBD_IOERROR); 3436 3437 x = URWMASK(UREAD2(sc, port)); 3438 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3439 3440 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3441 3442 DPRINTFN(3,("uhci port %d reset, status0 = 0x%04x\n", 3443 index, UREAD2(sc, port))); 3444 3445 x = URWMASK(UREAD2(sc, port)); 3446 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3447 3448 delay(100); 3449 3450 DPRINTFN(3,("uhci port %d reset, status1 = 0x%04x\n", 3451 index, UREAD2(sc, port))); 3452 3453 x = URWMASK(UREAD2(sc, port)); 3454 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3455 3456 for (lim = 10; --lim > 0;) { 3457 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3458 3459 x = UREAD2(sc, port); 3460 3461 DPRINTFN(3,("uhci port %d iteration %u, status = 0x%04x\n", 3462 index, lim, x)); 3463 3464 if (!(x & UHCI_PORTSC_CCS)) { 3465 /* 3466 * No device is connected (or was disconnected 3467 * during reset). Consider the port reset. 3468 * The delay must be long enough to ensure on 3469 * the initial iteration that the device 3470 * connection will have been registered. 50ms 3471 * appears to be sufficient, but 20ms is not. 3472 */ 3473 DPRINTFN(3,("uhci port %d loop %u, device detached\n", 3474 index, lim)); 3475 break; 3476 } 3477 3478 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3479 /* 3480 * Port enabled changed and/or connection 3481 * status changed were set. Reset either or 3482 * both raised flags (by writing a 1 to that 3483 * bit), and wait again for state to settle. 3484 */ 3485 UWRITE2(sc, port, URWMASK(x) | 3486 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3487 continue; 3488 } 3489 3490 if (x & UHCI_PORTSC_PE) 3491 /* Port is enabled */ 3492 break; 3493 3494 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3495 } 3496 3497 DPRINTFN(3,("uhci port %d reset, status2 = 0x%04x\n", 3498 index, UREAD2(sc, port))); 3499 3500 if (lim <= 0) { 3501 DPRINTFN(1,("uhci port %d reset timed out\n", index)); 3502 return (USBD_TIMEOUT); 3503 } 3504 3505 sc->sc_isreset = 1; 3506 return (USBD_NORMAL_COMPLETION); 3507 } 3508 3509 /* 3510 * Simulate a hardware hub by handling all the necessary requests. 3511 */ 3512 usbd_status 3513 uhci_root_ctrl_transfer(usbd_xfer_handle xfer) 3514 { 3515 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3516 usbd_status err; 3517 3518 /* Insert last in queue. */ 3519 mutex_enter(&sc->sc_lock); 3520 err = usb_insert_transfer(xfer); 3521 mutex_exit(&sc->sc_lock); 3522 if (err) 3523 return (err); 3524 3525 /* 3526 * Pipe isn't running (otherwise err would be USBD_INPROG), 3527 * so start it first. 3528 */ 3529 return (uhci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3530 } 3531 3532 usbd_status 3533 uhci_root_ctrl_start(usbd_xfer_handle xfer) 3534 { 3535 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3536 usb_device_request_t *req; 3537 void *buf = NULL; 3538 int port, x; 3539 int len, value, index, status, change, l, totlen = 0; 3540 usb_port_status_t ps; 3541 usbd_status err; 3542 3543 if (sc->sc_dying) 3544 return (USBD_IOERROR); 3545 3546 #ifdef DIAGNOSTIC 3547 if (!(xfer->rqflags & URQ_REQUEST)) 3548 panic("uhci_root_ctrl_start: not a request"); 3549 #endif 3550 req = &xfer->request; 3551 3552 DPRINTFN(2,("uhci_root_ctrl_control type=0x%02x request=%02x\n", 3553 req->bmRequestType, req->bRequest)); 3554 3555 len = UGETW(req->wLength); 3556 value = UGETW(req->wValue); 3557 index = UGETW(req->wIndex); 3558 3559 if (len != 0) 3560 buf = KERNADDR(&xfer->dmabuf, 0); 3561 3562 #define C(x,y) ((x) | ((y) << 8)) 3563 switch(C(req->bRequest, req->bmRequestType)) { 3564 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3565 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3566 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3567 /* 3568 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3569 * for the integrated root hub. 3570 */ 3571 break; 3572 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3573 if (len > 0) { 3574 *(u_int8_t *)buf = sc->sc_conf; 3575 totlen = 1; 3576 } 3577 break; 3578 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3579 DPRINTFN(2,("uhci_root_ctrl_control wValue=0x%04x\n", value)); 3580 if (len == 0) 3581 break; 3582 switch(value >> 8) { 3583 case UDESC_DEVICE: 3584 if ((value & 0xff) != 0) { 3585 err = USBD_IOERROR; 3586 goto ret; 3587 } 3588 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 3589 USETW(uhci_devd.idVendor, sc->sc_id_vendor); 3590 memcpy(buf, &uhci_devd, l); 3591 break; 3592 case UDESC_CONFIG: 3593 if ((value & 0xff) != 0) { 3594 err = USBD_IOERROR; 3595 goto ret; 3596 } 3597 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 3598 memcpy(buf, &uhci_confd, l); 3599 buf = (char *)buf + l; 3600 len -= l; 3601 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 3602 totlen += l; 3603 memcpy(buf, &uhci_ifcd, l); 3604 buf = (char *)buf + l; 3605 len -= l; 3606 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 3607 totlen += l; 3608 memcpy(buf, &uhci_endpd, l); 3609 break; 3610 case UDESC_STRING: 3611 #define sd ((usb_string_descriptor_t *)buf) 3612 switch (value & 0xff) { 3613 case 0: /* Language table */ 3614 totlen = usb_makelangtbl(sd, len); 3615 break; 3616 case 1: /* Vendor */ 3617 totlen = usb_makestrdesc(sd, len, 3618 sc->sc_vendor); 3619 break; 3620 case 2: /* Product */ 3621 totlen = usb_makestrdesc(sd, len, 3622 "UHCI root hub"); 3623 break; 3624 } 3625 #undef sd 3626 break; 3627 default: 3628 err = USBD_IOERROR; 3629 goto ret; 3630 } 3631 break; 3632 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3633 if (len > 0) { 3634 *(u_int8_t *)buf = 0; 3635 totlen = 1; 3636 } 3637 break; 3638 case C(UR_GET_STATUS, UT_READ_DEVICE): 3639 if (len > 1) { 3640 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 3641 totlen = 2; 3642 } 3643 break; 3644 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3645 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3646 if (len > 1) { 3647 USETW(((usb_status_t *)buf)->wStatus, 0); 3648 totlen = 2; 3649 } 3650 break; 3651 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3652 if (value >= USB_MAX_DEVICES) { 3653 err = USBD_IOERROR; 3654 goto ret; 3655 } 3656 sc->sc_addr = value; 3657 break; 3658 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3659 if (value != 0 && value != 1) { 3660 err = USBD_IOERROR; 3661 goto ret; 3662 } 3663 sc->sc_conf = value; 3664 break; 3665 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3666 break; 3667 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3668 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3669 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3670 err = USBD_IOERROR; 3671 goto ret; 3672 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3673 break; 3674 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3675 break; 3676 /* Hub requests */ 3677 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3678 break; 3679 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3680 DPRINTFN(3, ("uhci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 3681 "port=%d feature=%d\n", 3682 index, value)); 3683 if (index == 1) 3684 port = UHCI_PORTSC1; 3685 else if (index == 2) 3686 port = UHCI_PORTSC2; 3687 else { 3688 err = USBD_IOERROR; 3689 goto ret; 3690 } 3691 switch(value) { 3692 case UHF_PORT_ENABLE: 3693 x = URWMASK(UREAD2(sc, port)); 3694 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3695 break; 3696 case UHF_PORT_SUSPEND: 3697 x = URWMASK(UREAD2(sc, port)); 3698 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3699 break; 3700 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3701 /* see USB2 spec ch. 7.1.7.7 */ 3702 usb_delay_ms(&sc->sc_bus, 20); 3703 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3704 /* 10ms resume delay must be provided by caller */ 3705 break; 3706 case UHF_PORT_RESET: 3707 x = URWMASK(UREAD2(sc, port)); 3708 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3709 break; 3710 case UHF_C_PORT_CONNECTION: 3711 x = URWMASK(UREAD2(sc, port)); 3712 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3713 break; 3714 case UHF_C_PORT_ENABLE: 3715 x = URWMASK(UREAD2(sc, port)); 3716 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3717 break; 3718 case UHF_C_PORT_OVER_CURRENT: 3719 x = URWMASK(UREAD2(sc, port)); 3720 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3721 break; 3722 case UHF_C_PORT_RESET: 3723 sc->sc_isreset = 0; 3724 err = USBD_NORMAL_COMPLETION; 3725 goto ret; 3726 case UHF_PORT_CONNECTION: 3727 case UHF_PORT_OVER_CURRENT: 3728 case UHF_PORT_POWER: 3729 case UHF_PORT_LOW_SPEED: 3730 case UHF_C_PORT_SUSPEND: 3731 default: 3732 err = USBD_IOERROR; 3733 goto ret; 3734 } 3735 break; 3736 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3737 if (index == 1) 3738 port = UHCI_PORTSC1; 3739 else if (index == 2) 3740 port = UHCI_PORTSC2; 3741 else { 3742 err = USBD_IOERROR; 3743 goto ret; 3744 } 3745 if (len > 0) { 3746 *(u_int8_t *)buf = 3747 (UREAD2(sc, port) & UHCI_PORTSC_LS) >> 3748 UHCI_PORTSC_LS_SHIFT; 3749 totlen = 1; 3750 } 3751 break; 3752 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3753 if (len == 0) 3754 break; 3755 if ((value & 0xff) != 0) { 3756 err = USBD_IOERROR; 3757 goto ret; 3758 } 3759 l = min(len, USB_HUB_DESCRIPTOR_SIZE); 3760 totlen = l; 3761 memcpy(buf, &uhci_hubd_piix, l); 3762 break; 3763 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3764 if (len != 4) { 3765 err = USBD_IOERROR; 3766 goto ret; 3767 } 3768 memset(buf, 0, len); 3769 totlen = len; 3770 break; 3771 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3772 if (index == 1) 3773 port = UHCI_PORTSC1; 3774 else if (index == 2) 3775 port = UHCI_PORTSC2; 3776 else { 3777 err = USBD_IOERROR; 3778 goto ret; 3779 } 3780 if (len != 4) { 3781 err = USBD_IOERROR; 3782 goto ret; 3783 } 3784 x = UREAD2(sc, port); 3785 status = change = 0; 3786 if (x & UHCI_PORTSC_CCS) 3787 status |= UPS_CURRENT_CONNECT_STATUS; 3788 if (x & UHCI_PORTSC_CSC) 3789 change |= UPS_C_CONNECT_STATUS; 3790 if (x & UHCI_PORTSC_PE) 3791 status |= UPS_PORT_ENABLED; 3792 if (x & UHCI_PORTSC_POEDC) 3793 change |= UPS_C_PORT_ENABLED; 3794 if (x & UHCI_PORTSC_OCI) 3795 status |= UPS_OVERCURRENT_INDICATOR; 3796 if (x & UHCI_PORTSC_OCIC) 3797 change |= UPS_C_OVERCURRENT_INDICATOR; 3798 if (x & UHCI_PORTSC_SUSP) 3799 status |= UPS_SUSPEND; 3800 if (x & UHCI_PORTSC_LSDA) 3801 status |= UPS_LOW_SPEED; 3802 status |= UPS_PORT_POWER; 3803 if (sc->sc_isreset) 3804 change |= UPS_C_PORT_RESET; 3805 USETW(ps.wPortStatus, status); 3806 USETW(ps.wPortChange, change); 3807 l = min(len, sizeof ps); 3808 memcpy(buf, &ps, l); 3809 totlen = l; 3810 break; 3811 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3812 err = USBD_IOERROR; 3813 goto ret; 3814 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3815 break; 3816 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3817 if (index == 1) 3818 port = UHCI_PORTSC1; 3819 else if (index == 2) 3820 port = UHCI_PORTSC2; 3821 else { 3822 err = USBD_IOERROR; 3823 goto ret; 3824 } 3825 switch(value) { 3826 case UHF_PORT_ENABLE: 3827 x = URWMASK(UREAD2(sc, port)); 3828 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3829 break; 3830 case UHF_PORT_SUSPEND: 3831 x = URWMASK(UREAD2(sc, port)); 3832 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 3833 break; 3834 case UHF_PORT_RESET: 3835 err = uhci_portreset(sc, index); 3836 goto ret; 3837 case UHF_PORT_POWER: 3838 /* Pretend we turned on power */ 3839 err = USBD_NORMAL_COMPLETION; 3840 goto ret; 3841 case UHF_C_PORT_CONNECTION: 3842 case UHF_C_PORT_ENABLE: 3843 case UHF_C_PORT_OVER_CURRENT: 3844 case UHF_PORT_CONNECTION: 3845 case UHF_PORT_OVER_CURRENT: 3846 case UHF_PORT_LOW_SPEED: 3847 case UHF_C_PORT_SUSPEND: 3848 case UHF_C_PORT_RESET: 3849 default: 3850 err = USBD_IOERROR; 3851 goto ret; 3852 } 3853 break; 3854 default: 3855 err = USBD_IOERROR; 3856 goto ret; 3857 } 3858 xfer->actlen = totlen; 3859 err = USBD_NORMAL_COMPLETION; 3860 ret: 3861 xfer->status = err; 3862 mutex_enter(&sc->sc_lock); 3863 usb_transfer_complete(xfer); 3864 mutex_exit(&sc->sc_lock); 3865 return (USBD_IN_PROGRESS); 3866 } 3867 3868 /* Abort a root control request. */ 3869 void 3870 uhci_root_ctrl_abort(usbd_xfer_handle xfer) 3871 { 3872 /* Nothing to do, all transfers are synchronous. */ 3873 } 3874 3875 /* Close the root pipe. */ 3876 void 3877 uhci_root_ctrl_close(usbd_pipe_handle pipe) 3878 { 3879 DPRINTF(("uhci_root_ctrl_close\n")); 3880 } 3881 3882 /* Abort a root interrupt request. */ 3883 void 3884 uhci_root_intr_abort(usbd_xfer_handle xfer) 3885 { 3886 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3887 3888 KASSERT(mutex_owned(&sc->sc_lock)); 3889 3890 callout_stop(&sc->sc_poll_handle); 3891 sc->sc_intr_xfer = NULL; 3892 3893 if (xfer->pipe->intrxfer == xfer) { 3894 DPRINTF(("uhci_root_intr_abort: remove\n")); 3895 xfer->pipe->intrxfer = 0; 3896 } 3897 xfer->status = USBD_CANCELLED; 3898 #ifdef DIAGNOSTIC 3899 UXFER(xfer)->iinfo.isdone = 1; 3900 #endif 3901 usb_transfer_complete(xfer); 3902 } 3903 3904 usbd_status 3905 uhci_root_intr_transfer(usbd_xfer_handle xfer) 3906 { 3907 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3908 usbd_status err; 3909 3910 /* Insert last in queue. */ 3911 mutex_enter(&sc->sc_lock); 3912 err = usb_insert_transfer(xfer); 3913 mutex_exit(&sc->sc_lock); 3914 if (err) 3915 return (err); 3916 3917 /* 3918 * Pipe isn't running (otherwise err would be USBD_INPROG), 3919 * start first 3920 */ 3921 return (uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3922 } 3923 3924 /* Start a transfer on the root interrupt pipe */ 3925 usbd_status 3926 uhci_root_intr_start(usbd_xfer_handle xfer) 3927 { 3928 usbd_pipe_handle pipe = xfer->pipe; 3929 uhci_softc_t *sc = pipe->device->bus->hci_private; 3930 unsigned int ival; 3931 3932 DPRINTFN(3, ("uhci_root_intr_start: xfer=%p len=%d flags=%d\n", 3933 xfer, xfer->length, xfer->flags)); 3934 3935 if (sc->sc_dying) 3936 return (USBD_IOERROR); 3937 3938 /* XXX temporary variable needed to avoid gcc3 warning */ 3939 ival = xfer->pipe->endpoint->edesc->bInterval; 3940 sc->sc_ival = mstohz(ival); 3941 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 3942 sc->sc_intr_xfer = xfer; 3943 return (USBD_IN_PROGRESS); 3944 } 3945 3946 /* Close the root interrupt pipe. */ 3947 void 3948 uhci_root_intr_close(usbd_pipe_handle pipe) 3949 { 3950 uhci_softc_t *sc = pipe->device->bus->hci_private; 3951 3952 KASSERT(mutex_owned(&sc->sc_lock)); 3953 3954 callout_stop(&sc->sc_poll_handle); 3955 sc->sc_intr_xfer = NULL; 3956 DPRINTF(("uhci_root_intr_close\n")); 3957 } 3958
Indexes created Tue Sep 30 20:09:53 GMT 2025