uhci.c revision 1.240.6.10
1 /* $NetBSD: uhci.c,v 1.240.6.10 2012/02/20 06:50:21 mrg Exp $ */ 2 /* $FreeBSD: src/sys/dev/usb/uhci.c,v 1.33 1999/11/17 22:33:41 n_hibma Exp $ */ 3 4 /* 5 * Copyright (c) 1998, 2004, 2011 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Lennart Augustsson (lennart (at) augustsson.net) at 10 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 11 * and Matthew R. Green. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * USB Universal Host Controller driver. 37 * Handles e.g. PIIX3 and PIIX4. 38 * 39 * UHCI spec: http://www.intel.com/technology/usb/spec.htm 40 * USB spec: http://www.usb.org/developers/docs/ 41 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 42 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.240.6.10 2012/02/20 06:50:21 mrg Exp $"); 47 48 #include "opt_usb.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/kmem.h> 54 #include <sys/device.h> 55 #include <sys/select.h> 56 #include <sys/extent.h> 57 #include <sys/proc.h> 58 #include <sys/queue.h> 59 #include <sys/bus.h> 60 61 #include <machine/endian.h> 62 63 #include <dev/usb/usb.h> 64 #include <dev/usb/usbdi.h> 65 #include <dev/usb/usbdivar.h> 66 #include <dev/usb/usb_mem.h> 67 #include <dev/usb/usb_quirks.h> 68 69 #include <dev/usb/uhcireg.h> 70 #include <dev/usb/uhcivar.h> 71 #include <dev/usb/usbroothub_subr.h> 72 73 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 74 /*#define UHCI_CTL_LOOP */ 75 76 77 78 #ifdef UHCI_DEBUG 79 uhci_softc_t *thesc; 80 #define DPRINTF(x) if (uhcidebug) printf x 81 #define DPRINTFN(n,x) if (uhcidebug>(n)) printf x 82 int uhcidebug = 0; 83 int uhcinoloop = 0; 84 #else 85 #define DPRINTF(x) 86 #define DPRINTFN(n,x) 87 #endif 88 89 /* 90 * The UHCI controller is little endian, so on big endian machines 91 * the data stored in memory needs to be swapped. 92 */ 93 94 struct uhci_pipe { 95 struct usbd_pipe pipe; 96 int nexttoggle; 97 98 u_char aborting; 99 usbd_xfer_handle abortstart, abortend; 100 101 /* Info needed for different pipe kinds. */ 102 union { 103 /* Control pipe */ 104 struct { 105 uhci_soft_qh_t *sqh; 106 usb_dma_t reqdma; 107 uhci_soft_td_t *setup, *stat; 108 u_int length; 109 } ctl; 110 /* Interrupt pipe */ 111 struct { 112 int npoll; 113 int isread; 114 uhci_soft_qh_t **qhs; 115 } intr; 116 /* Bulk pipe */ 117 struct { 118 uhci_soft_qh_t *sqh; 119 u_int length; 120 int isread; 121 } bulk; 122 /* Iso pipe */ 123 struct iso { 124 uhci_soft_td_t **stds; 125 int next, inuse; 126 } iso; 127 } u; 128 }; 129 130 Static void uhci_globalreset(uhci_softc_t *); 131 Static usbd_status uhci_portreset(uhci_softc_t*, int); 132 Static void uhci_reset(uhci_softc_t *); 133 Static usbd_status uhci_run(uhci_softc_t *, int run); 134 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 135 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 136 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 137 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 138 #if 0 139 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 140 uhci_intr_info_t *); 141 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 142 #endif 143 144 Static void uhci_free_std_chain(uhci_softc_t *, 145 uhci_soft_td_t *, uhci_soft_td_t *); 146 Static usbd_status uhci_alloc_std_chain(struct uhci_pipe *, 147 uhci_softc_t *, int, int, u_int16_t, usb_dma_t *, 148 uhci_soft_td_t **, uhci_soft_td_t **); 149 Static void uhci_poll_hub(void *); 150 Static void uhci_waitintr(uhci_softc_t *, usbd_xfer_handle); 151 Static void uhci_check_intr(uhci_softc_t *, uhci_intr_info_t *); 152 Static void uhci_idone(uhci_intr_info_t *); 153 154 Static void uhci_abort_xfer(usbd_xfer_handle, usbd_status status); 155 156 Static void uhci_timeout(void *); 157 Static void uhci_timeout_task(void *); 158 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 159 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 160 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 161 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 162 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 163 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 164 Static void uhci_add_loop(uhci_softc_t *sc); 165 Static void uhci_rem_loop(uhci_softc_t *sc); 166 167 Static usbd_status uhci_setup_isoc(usbd_pipe_handle pipe); 168 Static void uhci_device_isoc_enter(usbd_xfer_handle); 169 170 Static usbd_status uhci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 171 Static void uhci_freem(struct usbd_bus *, usb_dma_t *); 172 173 Static usbd_xfer_handle uhci_allocx(struct usbd_bus *); 174 Static void uhci_freex(struct usbd_bus *, usbd_xfer_handle); 175 Static void uhci_get_lock(struct usbd_bus *, kmutex_t **); 176 177 Static usbd_status uhci_device_ctrl_transfer(usbd_xfer_handle); 178 Static usbd_status uhci_device_ctrl_start(usbd_xfer_handle); 179 Static void uhci_device_ctrl_abort(usbd_xfer_handle); 180 Static void uhci_device_ctrl_close(usbd_pipe_handle); 181 Static void uhci_device_ctrl_done(usbd_xfer_handle); 182 183 Static usbd_status uhci_device_intr_transfer(usbd_xfer_handle); 184 Static usbd_status uhci_device_intr_start(usbd_xfer_handle); 185 Static void uhci_device_intr_abort(usbd_xfer_handle); 186 Static void uhci_device_intr_close(usbd_pipe_handle); 187 Static void uhci_device_intr_done(usbd_xfer_handle); 188 189 Static usbd_status uhci_device_bulk_transfer(usbd_xfer_handle); 190 Static usbd_status uhci_device_bulk_start(usbd_xfer_handle); 191 Static void uhci_device_bulk_abort(usbd_xfer_handle); 192 Static void uhci_device_bulk_close(usbd_pipe_handle); 193 Static void uhci_device_bulk_done(usbd_xfer_handle); 194 195 Static usbd_status uhci_device_isoc_transfer(usbd_xfer_handle); 196 Static usbd_status uhci_device_isoc_start(usbd_xfer_handle); 197 Static void uhci_device_isoc_abort(usbd_xfer_handle); 198 Static void uhci_device_isoc_close(usbd_pipe_handle); 199 Static void uhci_device_isoc_done(usbd_xfer_handle); 200 201 Static usbd_status uhci_root_ctrl_transfer(usbd_xfer_handle); 202 Static usbd_status uhci_root_ctrl_start(usbd_xfer_handle); 203 Static void uhci_root_ctrl_abort(usbd_xfer_handle); 204 Static void uhci_root_ctrl_close(usbd_pipe_handle); 205 Static void uhci_root_ctrl_done(usbd_xfer_handle); 206 207 Static usbd_status uhci_root_intr_transfer(usbd_xfer_handle); 208 Static usbd_status uhci_root_intr_start(usbd_xfer_handle); 209 Static void uhci_root_intr_abort(usbd_xfer_handle); 210 Static void uhci_root_intr_close(usbd_pipe_handle); 211 Static void uhci_root_intr_done(usbd_xfer_handle); 212 213 Static usbd_status uhci_open(usbd_pipe_handle); 214 Static void uhci_poll(struct usbd_bus *); 215 Static void uhci_softintr(void *); 216 217 Static usbd_status uhci_device_request(usbd_xfer_handle xfer); 218 219 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 220 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 221 Static usbd_status uhci_device_setintr(uhci_softc_t *sc, 222 struct uhci_pipe *pipe, int ival); 223 224 Static void uhci_device_clear_toggle(usbd_pipe_handle pipe); 225 Static void uhci_noop(usbd_pipe_handle pipe); 226 227 static inline uhci_soft_qh_t *uhci_find_prev_qh(uhci_soft_qh_t *, 228 uhci_soft_qh_t *); 229 230 #ifdef UHCI_DEBUG 231 Static void uhci_dump_all(uhci_softc_t *); 232 Static void uhci_dumpregs(uhci_softc_t *); 233 Static void uhci_dump_qhs(uhci_soft_qh_t *); 234 Static void uhci_dump_qh(uhci_soft_qh_t *); 235 Static void uhci_dump_tds(uhci_soft_td_t *); 236 Static void uhci_dump_td(uhci_soft_td_t *); 237 Static void uhci_dump_ii(uhci_intr_info_t *ii); 238 void uhci_dump(void); 239 #endif 240 241 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 242 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 243 #define UWRITE1(sc, r, x) \ 244 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 245 } while (/*CONSTCOND*/0) 246 #define UWRITE2(sc, r, x) \ 247 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 248 } while (/*CONSTCOND*/0) 249 #define UWRITE4(sc, r, x) \ 250 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 251 } while (/*CONSTCOND*/0) 252 static __inline uint8_t 253 UREAD1(uhci_softc_t *sc, bus_size_t r) 254 { 255 256 UBARR(sc); 257 return bus_space_read_1(sc->iot, sc->ioh, r); 258 } 259 260 static __inline uint16_t 261 UREAD2(uhci_softc_t *sc, bus_size_t r) 262 { 263 264 UBARR(sc); 265 return bus_space_read_2(sc->iot, sc->ioh, r); 266 } 267 268 static __inline uint32_t 269 UREAD4(uhci_softc_t *sc, bus_size_t r) 270 { 271 272 UBARR(sc); 273 return bus_space_read_4(sc->iot, sc->ioh, r); 274 } 275 276 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 277 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 278 279 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 280 281 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 282 283 #define UHCI_INTR_ENDPT 1 284 285 const struct usbd_bus_methods uhci_bus_methods = { 286 .open_pipe = uhci_open, 287 .soft_intr = uhci_softintr, 288 .do_poll = uhci_poll, 289 .allocm = uhci_allocm, 290 .freem = uhci_freem, 291 .allocx = uhci_allocx, 292 .freex = uhci_freex, 293 .get_lock = uhci_get_lock, 294 }; 295 296 const struct usbd_pipe_methods uhci_root_ctrl_methods = { 297 .transfer = uhci_root_ctrl_transfer, 298 .start = uhci_root_ctrl_start, 299 .abort = uhci_root_ctrl_abort, 300 .close = uhci_root_ctrl_close, 301 .cleartoggle = uhci_noop, 302 .done = uhci_root_ctrl_done, 303 }; 304 305 const struct usbd_pipe_methods uhci_root_intr_methods = { 306 .transfer = uhci_root_intr_transfer, 307 .start = uhci_root_intr_start, 308 .abort = uhci_root_intr_abort, 309 .close = uhci_root_intr_close, 310 .cleartoggle = uhci_noop, 311 .done = uhci_root_intr_done, 312 }; 313 314 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 315 .transfer = uhci_device_ctrl_transfer, 316 .start = uhci_device_ctrl_start, 317 .abort = uhci_device_ctrl_abort, 318 .close = uhci_device_ctrl_close, 319 .cleartoggle = uhci_noop, 320 .done = uhci_device_ctrl_done, 321 }; 322 323 const struct usbd_pipe_methods uhci_device_intr_methods = { 324 .transfer = uhci_device_intr_transfer, 325 .start = uhci_device_intr_start, 326 .abort = uhci_device_intr_abort, 327 .close = uhci_device_intr_close, 328 .cleartoggle = uhci_device_clear_toggle, 329 .done = uhci_device_intr_done, 330 }; 331 332 const struct usbd_pipe_methods uhci_device_bulk_methods = { 333 .transfer = uhci_device_bulk_transfer, 334 .start = uhci_device_bulk_start, 335 .abort = uhci_device_bulk_abort, 336 .close = uhci_device_bulk_close, 337 .cleartoggle = uhci_device_clear_toggle, 338 .done = uhci_device_bulk_done, 339 }; 340 341 const struct usbd_pipe_methods uhci_device_isoc_methods = { 342 .transfer = uhci_device_isoc_transfer, 343 .start = uhci_device_isoc_start, 344 .abort = uhci_device_isoc_abort, 345 .close = uhci_device_isoc_close, 346 .cleartoggle = uhci_noop, 347 .done = uhci_device_isoc_done, 348 }; 349 350 #define uhci_add_intr_info(sc, ii) \ 351 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ii), list) 352 #define uhci_del_intr_info(ii) \ 353 do { \ 354 LIST_REMOVE((ii), list); \ 355 (ii)->list.le_prev = NULL; \ 356 } while (0) 357 #define uhci_active_intr_info(ii) ((ii)->list.le_prev != NULL) 358 359 static inline uhci_soft_qh_t * 360 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 361 { 362 DPRINTFN(15,("uhci_find_prev_qh: pqh=%p sqh=%p\n", pqh, sqh)); 363 364 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 365 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 366 usb_syncmem(&pqh->dma, 367 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 368 sizeof(pqh->qh.qh_hlink), 369 BUS_DMASYNC_POSTWRITE); 370 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 371 printf("uhci_find_prev_qh: QH not found\n"); 372 return (NULL); 373 } 374 #endif 375 } 376 return (pqh); 377 } 378 379 void 380 uhci_globalreset(uhci_softc_t *sc) 381 { 382 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 383 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 384 UHCICMD(sc, 0); /* do nothing */ 385 } 386 387 usbd_status 388 uhci_init(uhci_softc_t *sc) 389 { 390 usbd_status err; 391 int i, j; 392 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 393 uhci_soft_td_t *std; 394 395 DPRINTFN(1,("uhci_init: start\n")); 396 397 #ifdef UHCI_DEBUG 398 thesc = sc; 399 400 if (uhcidebug > 2) 401 uhci_dumpregs(sc); 402 #endif 403 404 sc->sc_suspend = PWR_RESUME; 405 406 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 407 uhci_globalreset(sc); /* reset the controller */ 408 uhci_reset(sc); 409 410 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 411 USB_MEM_RESERVE); 412 413 /* Allocate and initialize real frame array. */ 414 err = usb_allocmem(&sc->sc_bus, 415 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 416 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 417 if (err) 418 return (err); 419 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 420 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 421 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 422 423 /* 424 * Allocate a TD, inactive, that hangs from the last QH. 425 * This is to avoid a bug in the PIIX that makes it run berserk 426 * otherwise. 427 */ 428 std = uhci_alloc_std(sc); 429 if (std == NULL) 430 return (USBD_NOMEM); 431 std->link.std = NULL; 432 std->td.td_link = htole32(UHCI_PTR_T); 433 std->td.td_status = htole32(0); /* inactive */ 434 std->td.td_token = htole32(0); 435 std->td.td_buffer = htole32(0); 436 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 437 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 438 439 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 440 lsqh = uhci_alloc_sqh(sc); 441 if (lsqh == NULL) 442 return (USBD_NOMEM); 443 lsqh->hlink = NULL; 444 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 445 lsqh->elink = std; 446 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 447 sc->sc_last_qh = lsqh; 448 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 449 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 450 451 /* Allocate the dummy QH where bulk traffic will be queued. */ 452 bsqh = uhci_alloc_sqh(sc); 453 if (bsqh == NULL) 454 return (USBD_NOMEM); 455 bsqh->hlink = lsqh; 456 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 457 bsqh->elink = NULL; 458 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 459 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 460 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 461 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 462 463 /* Allocate dummy QH where high speed control traffic will be queued. */ 464 chsqh = uhci_alloc_sqh(sc); 465 if (chsqh == NULL) 466 return (USBD_NOMEM); 467 chsqh->hlink = bsqh; 468 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 469 chsqh->elink = NULL; 470 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 471 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 472 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 473 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 474 475 /* Allocate dummy QH where control traffic will be queued. */ 476 clsqh = uhci_alloc_sqh(sc); 477 if (clsqh == NULL) 478 return (USBD_NOMEM); 479 clsqh->hlink = chsqh; 480 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 481 clsqh->elink = NULL; 482 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 483 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 484 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 485 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 486 487 /* 488 * Make all (virtual) frame list pointers point to the interrupt 489 * queue heads and the interrupt queue heads at the control 490 * queue head and point the physical frame list to the virtual. 491 */ 492 for(i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 493 std = uhci_alloc_std(sc); 494 sqh = uhci_alloc_sqh(sc); 495 if (std == NULL || sqh == NULL) 496 return (USBD_NOMEM); 497 std->link.sqh = sqh; 498 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 499 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 500 std->td.td_token = htole32(0); 501 std->td.td_buffer = htole32(0); 502 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 503 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 504 sqh->hlink = clsqh; 505 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 506 sqh->elink = NULL; 507 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 508 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 509 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 510 sc->sc_vframes[i].htd = std; 511 sc->sc_vframes[i].etd = std; 512 sc->sc_vframes[i].hqh = sqh; 513 sc->sc_vframes[i].eqh = sqh; 514 for (j = i; 515 j < UHCI_FRAMELIST_COUNT; 516 j += UHCI_VFRAMELIST_COUNT) 517 sc->sc_pframes[j] = htole32(std->physaddr); 518 } 519 usb_syncmem(&sc->sc_dma, 0, 520 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 521 BUS_DMASYNC_PREWRITE); 522 523 524 LIST_INIT(&sc->sc_intrhead); 525 526 SIMPLEQ_INIT(&sc->sc_free_xfers); 527 528 callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE); 529 530 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 531 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 532 cv_init(&sc->sc_softwake_cv, "uhciab"); 533 534 /* Set up the bus struct. */ 535 sc->sc_bus.methods = &uhci_bus_methods; 536 sc->sc_bus.pipe_size = sizeof(struct uhci_pipe); 537 538 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 539 540 DPRINTFN(1,("uhci_init: enabling\n")); 541 542 err = uhci_run(sc, 1); /* and here we go... */ 543 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 544 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 545 return err; 546 } 547 548 int 549 uhci_activate(device_t self, enum devact act) 550 { 551 struct uhci_softc *sc = device_private(self); 552 553 switch (act) { 554 case DVACT_DEACTIVATE: 555 sc->sc_dying = 1; 556 return 0; 557 default: 558 return EOPNOTSUPP; 559 } 560 } 561 562 void 563 uhci_childdet(device_t self, device_t child) 564 { 565 struct uhci_softc *sc = device_private(self); 566 567 KASSERT(sc->sc_child == child); 568 sc->sc_child = NULL; 569 } 570 571 int 572 uhci_detach(struct uhci_softc *sc, int flags) 573 { 574 usbd_xfer_handle xfer; 575 int rv = 0; 576 577 if (sc->sc_child != NULL) 578 rv = config_detach(sc->sc_child, flags); 579 580 if (rv != 0) 581 return (rv); 582 583 /* Free all xfers associated with this HC. */ 584 for (;;) { 585 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 586 if (xfer == NULL) 587 break; 588 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 589 kmem_free(xfer, sizeof(struct uhci_xfer)); 590 } 591 592 callout_halt(&sc->sc_poll_handle, NULL); 593 callout_destroy(&sc->sc_poll_handle); 594 595 cv_destroy(&sc->sc_softwake_cv); 596 597 mutex_destroy(&sc->sc_lock); 598 mutex_destroy(&sc->sc_intr_lock); 599 600 /* XXX free other data structures XXX */ 601 602 return (rv); 603 } 604 605 usbd_status 606 uhci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 607 { 608 struct uhci_softc *sc = bus->hci_private; 609 usbd_status status; 610 u_int32_t n; 611 612 /* 613 * XXX 614 * Since we are allocating a buffer we can assume that we will 615 * need TDs for it. Since we don't want to allocate those from 616 * an interrupt context, we allocate them here and free them again. 617 * This is no guarantee that we'll get the TDs next time... 618 */ 619 n = size / 8; 620 if (n > 16) { 621 u_int32_t i; 622 uhci_soft_td_t **stds; 623 624 DPRINTF(("uhci_allocm: get %d TDs\n", n)); 625 stds = kmem_alloc(sizeof(uhci_soft_td_t *) * n, KM_SLEEP); 626 if (!stds) 627 return USBD_NOMEM; 628 for(i = 0; i < n; i++) 629 stds[i] = uhci_alloc_std(sc); 630 for(i = 0; i < n; i++) 631 if (stds[i] != NULL) 632 uhci_free_std(sc, stds[i]); 633 kmem_free(stds, sizeof(uhci_soft_td_t *) * n); 634 } 635 636 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 637 if (status == USBD_NOMEM) 638 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 639 return status; 640 } 641 642 void 643 uhci_freem(struct usbd_bus *bus, usb_dma_t *dma) 644 { 645 if (dma->block->flags & USB_DMA_RESERVE) { 646 usb_reserve_freem(&((struct uhci_softc *)bus)->sc_dma_reserve, 647 dma); 648 return; 649 } 650 usb_freemem(&((struct uhci_softc *)bus)->sc_bus, dma); 651 } 652 653 usbd_xfer_handle 654 uhci_allocx(struct usbd_bus *bus) 655 { 656 struct uhci_softc *sc = bus->hci_private; 657 usbd_xfer_handle xfer; 658 659 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 660 if (xfer != NULL) { 661 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 662 #ifdef DIAGNOSTIC 663 if (xfer->busy_free != XFER_FREE) { 664 printf("uhci_allocx: xfer=%p not free, 0x%08x\n", xfer, 665 xfer->busy_free); 666 } 667 #endif 668 } else { 669 xfer = kmem_alloc(sizeof(struct uhci_xfer), KM_SLEEP); 670 } 671 if (xfer != NULL) { 672 memset(xfer, 0, sizeof (struct uhci_xfer)); 673 UXFER(xfer)->iinfo.sc = sc; 674 #ifdef DIAGNOSTIC 675 UXFER(xfer)->iinfo.isdone = 1; 676 xfer->busy_free = XFER_BUSY; 677 #endif 678 } 679 return (xfer); 680 } 681 682 void 683 uhci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 684 { 685 struct uhci_softc *sc = bus->hci_private; 686 687 #ifdef DIAGNOSTIC 688 if (xfer->busy_free != XFER_BUSY) { 689 printf("uhci_freex: xfer=%p not busy, 0x%08x\n", xfer, 690 xfer->busy_free); 691 } 692 xfer->busy_free = XFER_FREE; 693 if (!UXFER(xfer)->iinfo.isdone) { 694 printf("uhci_freex: !isdone\n"); 695 } 696 #endif 697 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 698 } 699 700 Static void 701 uhci_get_lock(struct usbd_bus *bus, kmutex_t **thread) 702 { 703 struct uhci_softc *sc = bus->hci_private; 704 705 *thread = &sc->sc_lock; 706 } 707 708 709 /* 710 * Handle suspend/resume. 711 * 712 * We need to switch to polling mode here, because this routine is 713 * called from an interrupt context. This is all right since we 714 * are almost suspended anyway. 715 */ 716 bool 717 uhci_resume(device_t dv, const pmf_qual_t *qual) 718 { 719 uhci_softc_t *sc = device_private(dv); 720 int cmd; 721 722 mutex_spin_enter(&sc->sc_intr_lock); 723 724 cmd = UREAD2(sc, UHCI_CMD); 725 sc->sc_bus.use_polling++; 726 UWRITE2(sc, UHCI_INTR, 0); 727 uhci_globalreset(sc); 728 uhci_reset(sc); 729 if (cmd & UHCI_CMD_RS) 730 uhci_run(sc, 0); 731 732 /* restore saved state */ 733 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 734 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 735 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 736 737 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 738 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 739 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 740 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 741 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 742 UHCICMD(sc, UHCI_CMD_MAXP); 743 uhci_run(sc, 1); /* and start traffic again */ 744 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 745 sc->sc_bus.use_polling--; 746 if (sc->sc_intr_xfer != NULL) 747 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, 748 sc->sc_intr_xfer); 749 #ifdef UHCI_DEBUG 750 if (uhcidebug > 2) 751 uhci_dumpregs(sc); 752 #endif 753 754 sc->sc_suspend = PWR_RESUME; 755 mutex_spin_exit(&sc->sc_intr_lock); 756 757 return true; 758 } 759 760 bool 761 uhci_suspend(device_t dv, const pmf_qual_t *qual) 762 { 763 uhci_softc_t *sc = device_private(dv); 764 int cmd; 765 766 mutex_spin_enter(&sc->sc_intr_lock); 767 768 cmd = UREAD2(sc, UHCI_CMD); 769 770 #ifdef UHCI_DEBUG 771 if (uhcidebug > 2) 772 uhci_dumpregs(sc); 773 #endif 774 if (sc->sc_intr_xfer != NULL) 775 callout_stop(&sc->sc_poll_handle); 776 sc->sc_suspend = PWR_SUSPEND; 777 sc->sc_bus.use_polling++; 778 779 uhci_run(sc, 0); /* stop the controller */ 780 cmd &= ~UHCI_CMD_RS; 781 782 /* save some state if BIOS doesn't */ 783 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 784 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 785 786 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 787 788 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 789 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 790 sc->sc_bus.use_polling--; 791 792 mutex_spin_exit(&sc->sc_intr_lock); 793 794 return true; 795 } 796 797 #ifdef UHCI_DEBUG 798 Static void 799 uhci_dumpregs(uhci_softc_t *sc) 800 { 801 DPRINTFN(-1,("%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, " 802 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 803 device_xname(sc->sc_dev), 804 UREAD2(sc, UHCI_CMD), 805 UREAD2(sc, UHCI_STS), 806 UREAD2(sc, UHCI_INTR), 807 UREAD2(sc, UHCI_FRNUM), 808 UREAD4(sc, UHCI_FLBASEADDR), 809 UREAD1(sc, UHCI_SOF), 810 UREAD2(sc, UHCI_PORTSC1), 811 UREAD2(sc, UHCI_PORTSC2))); 812 } 813 814 void 815 uhci_dump_td(uhci_soft_td_t *p) 816 { 817 char sbuf[128], sbuf2[128]; 818 819 820 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 821 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 822 DPRINTFN(-1,("TD(%p) at %08lx = link=0x%08lx status=0x%08lx " 823 "token=0x%08lx buffer=0x%08lx\n", 824 p, (long)p->physaddr, 825 (long)le32toh(p->td.td_link), 826 (long)le32toh(p->td.td_status), 827 (long)le32toh(p->td.td_token), 828 (long)le32toh(p->td.td_buffer))); 829 830 snprintb(sbuf, sizeof(sbuf), "\20\1T\2Q\3VF", 831 (u_int32_t)le32toh(p->td.td_link)); 832 snprintb(sbuf2, sizeof(sbuf2), 833 "\20\22BITSTUFF\23CRCTO\24NAK\25BABBLE\26DBUFFER\27" 834 "STALLED\30ACTIVE\31IOC\32ISO\33LS\36SPD", 835 (u_int32_t)le32toh(p->td.td_status)); 836 837 DPRINTFN(-1,(" %s %s,errcnt=%d,actlen=%d pid=%02x,addr=%d,endpt=%d," 838 "D=%d,maxlen=%d\n", sbuf, sbuf2, 839 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 840 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 841 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 842 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 843 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 844 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 845 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token)))); 846 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 847 BUS_DMASYNC_PREREAD); 848 } 849 850 void 851 uhci_dump_qh(uhci_soft_qh_t *sqh) 852 { 853 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 854 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 855 DPRINTFN(-1,("QH(%p) at %08x: hlink=%08x elink=%08x\n", sqh, 856 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 857 le32toh(sqh->qh.qh_elink))); 858 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 859 } 860 861 862 #if 1 863 void 864 uhci_dump(void) 865 { 866 uhci_dump_all(thesc); 867 } 868 #endif 869 870 void 871 uhci_dump_all(uhci_softc_t *sc) 872 { 873 uhci_dumpregs(sc); 874 printf("intrs=%d\n", sc->sc_bus.no_intrs); 875 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 876 uhci_dump_qh(sc->sc_lctl_start); 877 } 878 879 880 void 881 uhci_dump_qhs(uhci_soft_qh_t *sqh) 882 { 883 uhci_dump_qh(sqh); 884 885 /* uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 886 * Traverses sideways first, then down. 887 * 888 * QH1 889 * QH2 890 * No QH 891 * TD2.1 892 * TD2.2 893 * TD1.1 894 * etc. 895 * 896 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 897 */ 898 899 900 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 901 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 902 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 903 uhci_dump_qhs(sqh->hlink); 904 else 905 DPRINTF(("No QH\n")); 906 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 907 908 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 909 uhci_dump_tds(sqh->elink); 910 else 911 DPRINTF(("No TD\n")); 912 } 913 914 void 915 uhci_dump_tds(uhci_soft_td_t *std) 916 { 917 uhci_soft_td_t *td; 918 int stop; 919 920 for(td = std; td != NULL; td = td->link.std) { 921 uhci_dump_td(td); 922 923 /* Check whether the link pointer in this TD marks 924 * the link pointer as end of queue. This avoids 925 * printing the free list in case the queue/TD has 926 * already been moved there (seatbelt). 927 */ 928 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 929 sizeof(td->td.td_link), 930 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 931 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 932 le32toh(td->td.td_link) == 0); 933 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 934 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 935 if (stop) 936 break; 937 } 938 } 939 940 Static void 941 uhci_dump_ii(uhci_intr_info_t *ii) 942 { 943 usbd_pipe_handle pipe; 944 usb_endpoint_descriptor_t *ed; 945 usbd_device_handle dev; 946 947 #ifdef DIAGNOSTIC 948 #define DONE ii->isdone 949 #else 950 #define DONE 0 951 #endif 952 if (ii == NULL) { 953 printf("ii NULL\n"); 954 return; 955 } 956 if (ii->xfer == NULL) { 957 printf("ii %p: done=%d xfer=NULL\n", 958 ii, DONE); 959 return; 960 } 961 pipe = ii->xfer->pipe; 962 if (pipe == NULL) { 963 printf("ii %p: done=%d xfer=%p pipe=NULL\n", 964 ii, DONE, ii->xfer); 965 return; 966 } 967 if (pipe->endpoint == NULL) { 968 printf("ii %p: done=%d xfer=%p pipe=%p pipe->endpoint=NULL\n", 969 ii, DONE, ii->xfer, pipe); 970 return; 971 } 972 if (pipe->device == NULL) { 973 printf("ii %p: done=%d xfer=%p pipe=%p pipe->device=NULL\n", 974 ii, DONE, ii->xfer, pipe); 975 return; 976 } 977 ed = pipe->endpoint->edesc; 978 dev = pipe->device; 979 printf("ii %p: done=%d xfer=%p dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 980 ii, DONE, ii->xfer, dev, 981 UGETW(dev->ddesc.idVendor), 982 UGETW(dev->ddesc.idProduct), 983 dev->address, pipe, 984 ed->bEndpointAddress, ed->bmAttributes); 985 #undef DONE 986 } 987 988 void uhci_dump_iis(struct uhci_softc *sc); 989 void 990 uhci_dump_iis(struct uhci_softc *sc) 991 { 992 uhci_intr_info_t *ii; 993 994 printf("intr_info list:\n"); 995 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = LIST_NEXT(ii, list)) 996 uhci_dump_ii(ii); 997 } 998 999 void iidump(void); 1000 void iidump(void) { uhci_dump_iis(thesc); } 1001 1002 #endif 1003 1004 /* 1005 * This routine is executed periodically and simulates interrupts 1006 * from the root controller interrupt pipe for port status change. 1007 */ 1008 void 1009 uhci_poll_hub(void *addr) 1010 { 1011 usbd_xfer_handle xfer = addr; 1012 usbd_pipe_handle pipe = xfer->pipe; 1013 uhci_softc_t *sc; 1014 u_char *p; 1015 1016 DPRINTFN(20, ("uhci_poll_hub\n")); 1017 1018 if (__predict_false(pipe->device == NULL || pipe->device->bus == NULL)) 1019 return; /* device has detached */ 1020 sc = pipe->device->bus->hci_private; 1021 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 1022 1023 p = KERNADDR(&xfer->dmabuf, 0); 1024 p[0] = 0; 1025 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1026 p[0] |= 1<<1; 1027 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1028 p[0] |= 1<<2; 1029 if (p[0] == 0) 1030 /* No change, try again in a while */ 1031 return; 1032 1033 xfer->actlen = 1; 1034 xfer->status = USBD_NORMAL_COMPLETION; 1035 mutex_enter(&sc->sc_lock); 1036 xfer->device->bus->intr_context++; 1037 usb_transfer_complete(xfer); 1038 xfer->device->bus->intr_context--; 1039 mutex_exit(&sc->sc_lock); 1040 } 1041 1042 void 1043 uhci_root_intr_done(usbd_xfer_handle xfer) 1044 { 1045 } 1046 1047 void 1048 uhci_root_ctrl_done(usbd_xfer_handle xfer) 1049 { 1050 } 1051 1052 /* 1053 * Let the last QH loop back to the high speed control transfer QH. 1054 * This is what intel calls "bandwidth reclamation" and improves 1055 * USB performance a lot for some devices. 1056 * If we are already looping, just count it. 1057 */ 1058 void 1059 uhci_add_loop(uhci_softc_t *sc) { 1060 #ifdef UHCI_DEBUG 1061 if (uhcinoloop) 1062 return; 1063 #endif 1064 if (++sc->sc_loops == 1) { 1065 DPRINTFN(5,("uhci_start_loop: add\n")); 1066 /* Note, we don't loop back the soft pointer. */ 1067 sc->sc_last_qh->qh.qh_hlink = 1068 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 1069 usb_syncmem(&sc->sc_last_qh->dma, 1070 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1071 sizeof(sc->sc_last_qh->qh.qh_hlink), 1072 BUS_DMASYNC_PREWRITE); 1073 } 1074 } 1075 1076 void 1077 uhci_rem_loop(uhci_softc_t *sc) { 1078 #ifdef UHCI_DEBUG 1079 if (uhcinoloop) 1080 return; 1081 #endif 1082 if (--sc->sc_loops == 0) { 1083 DPRINTFN(5,("uhci_end_loop: remove\n")); 1084 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 1085 usb_syncmem(&sc->sc_last_qh->dma, 1086 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1087 sizeof(sc->sc_last_qh->qh.qh_hlink), 1088 BUS_DMASYNC_PREWRITE); 1089 } 1090 } 1091 1092 /* Add high speed control QH, called with thread lock held. */ 1093 void 1094 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1095 { 1096 uhci_soft_qh_t *eqh; 1097 1098 KASSERT(mutex_owned(&sc->sc_lock)); 1099 1100 DPRINTFN(10, ("uhci_add_ctrl: sqh=%p\n", sqh)); 1101 eqh = sc->sc_hctl_end; 1102 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1103 sizeof(eqh->qh.qh_hlink), 1104 BUS_DMASYNC_POSTWRITE); 1105 sqh->hlink = eqh->hlink; 1106 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1107 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1108 BUS_DMASYNC_PREWRITE); 1109 eqh->hlink = sqh; 1110 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1111 sc->sc_hctl_end = sqh; 1112 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1113 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1114 #ifdef UHCI_CTL_LOOP 1115 uhci_add_loop(sc); 1116 #endif 1117 } 1118 1119 /* Remove high speed control QH, called with thread lock held. */ 1120 void 1121 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1122 { 1123 uhci_soft_qh_t *pqh; 1124 1125 KASSERT(mutex_owned(&sc->sc_lock)); 1126 1127 DPRINTFN(10, ("uhci_remove_hs_ctrl: sqh=%p\n", sqh)); 1128 #ifdef UHCI_CTL_LOOP 1129 uhci_rem_loop(sc); 1130 #endif 1131 /* 1132 * The T bit should be set in the elink of the QH so that the HC 1133 * doesn't follow the pointer. This condition may fail if the 1134 * the transferred packet was short so that the QH still points 1135 * at the last used TD. 1136 * In this case we set the T bit and wait a little for the HC 1137 * to stop looking at the TD. 1138 * Note that if the TD chain is large enough, the controller 1139 * may still be looking at the chain at the end of this function. 1140 * uhci_free_std_chain() will make sure the controller stops 1141 * looking at it quickly, but until then we should not change 1142 * sqh->hlink. 1143 */ 1144 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1145 sizeof(sqh->qh.qh_elink), 1146 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1147 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1148 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1149 usb_syncmem(&sqh->dma, 1150 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1151 sizeof(sqh->qh.qh_elink), 1152 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1153 delay(UHCI_QH_REMOVE_DELAY); 1154 } 1155 1156 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1157 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1158 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1159 pqh->hlink = sqh->hlink; 1160 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1161 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1162 sizeof(pqh->qh.qh_hlink), 1163 BUS_DMASYNC_PREWRITE); 1164 delay(UHCI_QH_REMOVE_DELAY); 1165 if (sc->sc_hctl_end == sqh) 1166 sc->sc_hctl_end = pqh; 1167 } 1168 1169 /* Add low speed control QH, called with thread lock held. */ 1170 void 1171 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1172 { 1173 uhci_soft_qh_t *eqh; 1174 1175 KASSERT(mutex_owned(&sc->sc_lock)); 1176 1177 DPRINTFN(10, ("uhci_add_ls_ctrl: sqh=%p\n", sqh)); 1178 eqh = sc->sc_lctl_end; 1179 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1180 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1181 sqh->hlink = eqh->hlink; 1182 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1183 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1184 BUS_DMASYNC_PREWRITE); 1185 eqh->hlink = sqh; 1186 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1187 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1188 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1189 sc->sc_lctl_end = sqh; 1190 } 1191 1192 /* Remove low speed control QH, called with thread lock held. */ 1193 void 1194 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1195 { 1196 uhci_soft_qh_t *pqh; 1197 1198 KASSERT(mutex_owned(&sc->sc_lock)); 1199 1200 DPRINTFN(10, ("uhci_remove_ls_ctrl: sqh=%p\n", sqh)); 1201 /* See comment in uhci_remove_hs_ctrl() */ 1202 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1203 sizeof(sqh->qh.qh_elink), 1204 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1205 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1206 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1207 usb_syncmem(&sqh->dma, 1208 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1209 sizeof(sqh->qh.qh_elink), 1210 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1211 delay(UHCI_QH_REMOVE_DELAY); 1212 } 1213 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1214 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1215 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1216 pqh->hlink = sqh->hlink; 1217 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1218 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1219 sizeof(pqh->qh.qh_hlink), 1220 BUS_DMASYNC_PREWRITE); 1221 delay(UHCI_QH_REMOVE_DELAY); 1222 if (sc->sc_lctl_end == sqh) 1223 sc->sc_lctl_end = pqh; 1224 } 1225 1226 /* Add bulk QH, called with thread lock held. */ 1227 void 1228 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1229 { 1230 uhci_soft_qh_t *eqh; 1231 1232 KASSERT(mutex_owned(&sc->sc_lock)); 1233 1234 DPRINTFN(10, ("uhci_add_bulk: sqh=%p\n", sqh)); 1235 eqh = sc->sc_bulk_end; 1236 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1237 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1238 sqh->hlink = eqh->hlink; 1239 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1240 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1241 BUS_DMASYNC_PREWRITE); 1242 eqh->hlink = sqh; 1243 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1244 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1245 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1246 sc->sc_bulk_end = sqh; 1247 uhci_add_loop(sc); 1248 } 1249 1250 /* Remove bulk QH, called with thread lock held. */ 1251 void 1252 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1253 { 1254 uhci_soft_qh_t *pqh; 1255 1256 KASSERT(mutex_owned(&sc->sc_lock)); 1257 1258 DPRINTFN(10, ("uhci_remove_bulk: sqh=%p\n", sqh)); 1259 uhci_rem_loop(sc); 1260 /* See comment in uhci_remove_hs_ctrl() */ 1261 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1262 sizeof(sqh->qh.qh_elink), 1263 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1264 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1265 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1266 usb_syncmem(&sqh->dma, 1267 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1268 sizeof(sqh->qh.qh_elink), 1269 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1270 delay(UHCI_QH_REMOVE_DELAY); 1271 } 1272 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1273 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1274 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1275 pqh->hlink = sqh->hlink; 1276 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1277 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1278 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1279 delay(UHCI_QH_REMOVE_DELAY); 1280 if (sc->sc_bulk_end == sqh) 1281 sc->sc_bulk_end = pqh; 1282 } 1283 1284 Static int uhci_intr1(uhci_softc_t *); 1285 1286 int 1287 uhci_intr(void *arg) 1288 { 1289 uhci_softc_t *sc = arg; 1290 int ret = 0; 1291 1292 mutex_spin_enter(&sc->sc_intr_lock); 1293 1294 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1295 goto done; 1296 1297 if (sc->sc_bus.use_polling || UREAD2(sc, UHCI_INTR) == 0) { 1298 #ifdef DIAGNOSTIC 1299 DPRINTFN(16, ("uhci_intr: ignored interrupt while polling\n")); 1300 #endif 1301 goto done; 1302 } 1303 1304 ret = uhci_intr1(sc); 1305 1306 done: 1307 mutex_spin_exit(&sc->sc_intr_lock); 1308 return ret; 1309 } 1310 1311 int 1312 uhci_intr1(uhci_softc_t *sc) 1313 { 1314 int status; 1315 int ack; 1316 1317 #ifdef UHCI_DEBUG 1318 if (uhcidebug > 15) { 1319 DPRINTF(("%s: uhci_intr1\n", device_xname(sc->sc_dev))); 1320 uhci_dumpregs(sc); 1321 } 1322 #endif 1323 1324 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1325 1326 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1327 if (status == 0) /* The interrupt was not for us. */ 1328 return (0); 1329 1330 if (sc->sc_suspend != PWR_RESUME) { 1331 #ifdef DIAGNOSTIC 1332 printf("%s: interrupt while not operating ignored\n", 1333 device_xname(sc->sc_dev)); 1334 #endif 1335 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1336 return (0); 1337 } 1338 1339 ack = 0; 1340 if (status & UHCI_STS_USBINT) 1341 ack |= UHCI_STS_USBINT; 1342 if (status & UHCI_STS_USBEI) 1343 ack |= UHCI_STS_USBEI; 1344 if (status & UHCI_STS_RD) { 1345 ack |= UHCI_STS_RD; 1346 #ifdef UHCI_DEBUG 1347 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1348 #endif 1349 } 1350 if (status & UHCI_STS_HSE) { 1351 ack |= UHCI_STS_HSE; 1352 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1353 } 1354 if (status & UHCI_STS_HCPE) { 1355 ack |= UHCI_STS_HCPE; 1356 printf("%s: host controller process error\n", 1357 device_xname(sc->sc_dev)); 1358 } 1359 1360 /* When HCHalted=1 and Run/Stop=0 , it is normal */ 1361 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 1362 /* no acknowledge needed */ 1363 if (!sc->sc_dying) { 1364 printf("%s: host controller halted\n", 1365 device_xname(sc->sc_dev)); 1366 #ifdef UHCI_DEBUG 1367 uhci_dump_all(sc); 1368 #endif 1369 } 1370 sc->sc_dying = 1; 1371 } 1372 1373 if (!ack) 1374 return (0); /* nothing to acknowledge */ 1375 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1376 1377 sc->sc_bus.no_intrs++; 1378 usb_schedsoftintr(&sc->sc_bus); 1379 1380 DPRINTFN(15, ("%s: uhci_intr: exit\n", device_xname(sc->sc_dev))); 1381 1382 return (1); 1383 } 1384 1385 void 1386 uhci_softintr(void *v) 1387 { 1388 struct usbd_bus *bus = v; 1389 uhci_softc_t *sc = bus->hci_private; 1390 uhci_intr_info_t *ii, *nextii; 1391 1392 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1393 1394 DPRINTFN(10,("%s: uhci_softintr (%d)\n", device_xname(sc->sc_dev), 1395 sc->sc_bus.intr_context)); 1396 1397 sc->sc_bus.intr_context++; 1398 1399 /* 1400 * Interrupts on UHCI really suck. When the host controller 1401 * interrupts because a transfer is completed there is no 1402 * way of knowing which transfer it was. You can scan down 1403 * the TDs and QHs of the previous frame to limit the search, 1404 * but that assumes that the interrupt was not delayed by more 1405 * than 1 ms, which may not always be true (e.g. after debug 1406 * output on a slow console). 1407 * We scan all interrupt descriptors to see if any have 1408 * completed. 1409 */ 1410 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = nextii) { 1411 nextii = LIST_NEXT(ii, list); 1412 uhci_check_intr(sc, ii); 1413 } 1414 1415 if (sc->sc_softwake) { 1416 sc->sc_softwake = 0; 1417 cv_broadcast(&sc->sc_softwake_cv); 1418 } 1419 1420 sc->sc_bus.intr_context--; 1421 } 1422 1423 /* Check for an interrupt. */ 1424 void 1425 uhci_check_intr(uhci_softc_t *sc, uhci_intr_info_t *ii) 1426 { 1427 uhci_soft_td_t *std, *lstd; 1428 u_int32_t status; 1429 1430 DPRINTFN(15, ("uhci_check_intr: ii=%p\n", ii)); 1431 #ifdef DIAGNOSTIC 1432 if (ii == NULL) { 1433 printf("uhci_check_intr: no ii? %p\n", ii); 1434 return; 1435 } 1436 #endif 1437 if (ii->xfer->status == USBD_CANCELLED || 1438 ii->xfer->status == USBD_TIMEOUT) { 1439 DPRINTF(("uhci_check_intr: aborted xfer=%p\n", ii->xfer)); 1440 return; 1441 } 1442 1443 if (ii->stdstart == NULL) 1444 return; 1445 lstd = ii->stdend; 1446 #ifdef DIAGNOSTIC 1447 if (lstd == NULL) { 1448 printf("uhci_check_intr: std==0\n"); 1449 return; 1450 } 1451 #endif 1452 /* 1453 * If the last TD is still active we need to check whether there 1454 * is an error somewhere in the middle, or whether there was a 1455 * short packet (SPD and not ACTIVE). 1456 */ 1457 usb_syncmem(&lstd->dma, 1458 lstd->offs + offsetof(uhci_td_t, td_status), 1459 sizeof(lstd->td.td_status), 1460 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1461 if (le32toh(lstd->td.td_status) & UHCI_TD_ACTIVE) { 1462 DPRINTFN(12, ("uhci_check_intr: active ii=%p\n", ii)); 1463 for (std = ii->stdstart; std != lstd; std = std->link.std) { 1464 usb_syncmem(&std->dma, 1465 std->offs + offsetof(uhci_td_t, td_status), 1466 sizeof(std->td.td_status), 1467 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1468 status = le32toh(std->td.td_status); 1469 usb_syncmem(&std->dma, 1470 std->offs + offsetof(uhci_td_t, td_status), 1471 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1472 /* If there's an active TD the xfer isn't done. */ 1473 if (status & UHCI_TD_ACTIVE) 1474 break; 1475 /* Any kind of error makes the xfer done. */ 1476 if (status & UHCI_TD_STALLED) 1477 goto done; 1478 /* We want short packets, and it is short: it's done */ 1479 usb_syncmem(&std->dma, 1480 std->offs + offsetof(uhci_td_t, td_token), 1481 sizeof(std->td.td_token), 1482 BUS_DMASYNC_POSTWRITE); 1483 if ((status & UHCI_TD_SPD) && 1484 UHCI_TD_GET_ACTLEN(status) < 1485 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) 1486 goto done; 1487 } 1488 DPRINTFN(12, ("uhci_check_intr: ii=%p std=%p still active\n", 1489 ii, ii->stdstart)); 1490 usb_syncmem(&lstd->dma, 1491 lstd->offs + offsetof(uhci_td_t, td_status), 1492 sizeof(lstd->td.td_status), 1493 BUS_DMASYNC_PREREAD); 1494 return; 1495 } 1496 done: 1497 DPRINTFN(12, ("uhci_check_intr: ii=%p done\n", ii)); 1498 callout_stop(&ii->xfer->timeout_handle); 1499 uhci_idone(ii); 1500 } 1501 1502 /* Called with USB thread lock held. */ 1503 void 1504 uhci_idone(uhci_intr_info_t *ii) 1505 { 1506 usbd_xfer_handle xfer = ii->xfer; 1507 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 1508 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 1509 uhci_soft_td_t *std; 1510 u_int32_t status = 0, nstatus; 1511 int actlen; 1512 1513 KASSERT(mutex_owned(&sc->sc_lock)); 1514 1515 DPRINTFN(12, ("uhci_idone: ii=%p\n", ii)); 1516 #ifdef DIAGNOSTIC 1517 { 1518 /* XXX SMP? */ 1519 int s = splhigh(); 1520 if (ii->isdone) { 1521 splx(s); 1522 #ifdef UHCI_DEBUG 1523 printf("uhci_idone: ii is done!\n "); 1524 uhci_dump_ii(ii); 1525 #else 1526 printf("uhci_idone: ii=%p is done!\n", ii); 1527 #endif 1528 return; 1529 } 1530 ii->isdone = 1; 1531 splx(s); 1532 } 1533 #endif 1534 1535 if (xfer->nframes != 0) { 1536 /* Isoc transfer, do things differently. */ 1537 uhci_soft_td_t **stds = upipe->u.iso.stds; 1538 int i, n, nframes, len; 1539 1540 DPRINTFN(5,("uhci_idone: ii=%p isoc ready\n", ii)); 1541 1542 nframes = xfer->nframes; 1543 actlen = 0; 1544 n = UXFER(xfer)->curframe; 1545 for (i = 0; i < nframes; i++) { 1546 std = stds[n]; 1547 #ifdef UHCI_DEBUG 1548 if (uhcidebug > 5) { 1549 DPRINTFN(-1,("uhci_idone: isoc TD %d\n", i)); 1550 uhci_dump_td(std); 1551 } 1552 #endif 1553 if (++n >= UHCI_VFRAMELIST_COUNT) 1554 n = 0; 1555 usb_syncmem(&std->dma, 1556 std->offs + offsetof(uhci_td_t, td_status), 1557 sizeof(std->td.td_status), 1558 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1559 status = le32toh(std->td.td_status); 1560 len = UHCI_TD_GET_ACTLEN(status); 1561 xfer->frlengths[i] = len; 1562 actlen += len; 1563 } 1564 upipe->u.iso.inuse -= nframes; 1565 xfer->actlen = actlen; 1566 xfer->status = USBD_NORMAL_COMPLETION; 1567 goto end; 1568 } 1569 1570 #ifdef UHCI_DEBUG 1571 DPRINTFN(10, ("uhci_idone: ii=%p, xfer=%p, pipe=%p ready\n", 1572 ii, xfer, upipe)); 1573 if (uhcidebug > 10) 1574 uhci_dump_tds(ii->stdstart); 1575 #endif 1576 1577 /* The transfer is done, compute actual length and status. */ 1578 actlen = 0; 1579 for (std = ii->stdstart; std != NULL; std = std->link.std) { 1580 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1581 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1582 nstatus = le32toh(std->td.td_status); 1583 if (nstatus & UHCI_TD_ACTIVE) 1584 break; 1585 1586 status = nstatus; 1587 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1588 UHCI_TD_PID_SETUP) 1589 actlen += UHCI_TD_GET_ACTLEN(status); 1590 else { 1591 /* 1592 * UHCI will report CRCTO in addition to a STALL or NAK 1593 * for a SETUP transaction. See section 3.2.2, "TD 1594 * CONTROL AND STATUS". 1595 */ 1596 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1597 status &= ~UHCI_TD_CRCTO; 1598 } 1599 } 1600 /* If there are left over TDs we need to update the toggle. */ 1601 if (std != NULL) 1602 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1603 1604 status &= UHCI_TD_ERROR; 1605 DPRINTFN(10, ("uhci_idone: actlen=%d, status=0x%x\n", 1606 actlen, status)); 1607 xfer->actlen = actlen; 1608 if (status != 0) { 1609 #ifdef UHCI_DEBUG 1610 char sbuf[128]; 1611 1612 snprintb(sbuf, sizeof(sbuf), 1613 "\20\22BITSTUFF\23CRCTO\24NAK\25" 1614 "BABBLE\26DBUFFER\27STALLED\30ACTIVE",(u_int32_t)status); 1615 1616 DPRINTFN((status == UHCI_TD_STALLED)*10, 1617 ("uhci_idone: error, addr=%d, endpt=0x%02x, " 1618 "status 0x%s\n", 1619 xfer->pipe->device->address, 1620 xfer->pipe->endpoint->edesc->bEndpointAddress, 1621 sbuf)); 1622 #endif 1623 1624 if (status == UHCI_TD_STALLED) 1625 xfer->status = USBD_STALLED; 1626 else 1627 xfer->status = USBD_IOERROR; /* more info XXX */ 1628 } else { 1629 xfer->status = USBD_NORMAL_COMPLETION; 1630 } 1631 1632 end: 1633 usb_transfer_complete(xfer); 1634 KASSERT(mutex_owned(&sc->sc_lock)); 1635 DPRINTFN(12, ("uhci_idone: ii=%p done\n", ii)); 1636 } 1637 1638 /* 1639 * Called when a request does not complete. 1640 */ 1641 void 1642 uhci_timeout(void *addr) 1643 { 1644 uhci_intr_info_t *ii = addr; 1645 struct uhci_xfer *uxfer = UXFER(ii->xfer); 1646 struct uhci_pipe *upipe = (struct uhci_pipe *)uxfer->xfer.pipe; 1647 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 1648 1649 DPRINTF(("uhci_timeout: uxfer=%p\n", uxfer)); 1650 1651 if (sc->sc_dying) { 1652 mutex_enter(&sc->sc_lock); 1653 uhci_abort_xfer(&uxfer->xfer, USBD_TIMEOUT); 1654 mutex_exit(&sc->sc_lock); 1655 return; 1656 } 1657 1658 /* Execute the abort in a process context. */ 1659 usb_init_task(&uxfer->abort_task, uhci_timeout_task, ii->xfer); 1660 usb_add_task(uxfer->xfer.pipe->device, &uxfer->abort_task, 1661 USB_TASKQ_HC); 1662 } 1663 1664 void 1665 uhci_timeout_task(void *addr) 1666 { 1667 usbd_xfer_handle xfer = addr; 1668 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1669 1670 DPRINTF(("uhci_timeout_task: xfer=%p\n", xfer)); 1671 1672 mutex_enter(&sc->sc_lock); 1673 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1674 mutex_exit(&sc->sc_lock); 1675 } 1676 1677 /* 1678 * Wait here until controller claims to have an interrupt. 1679 * Then call uhci_intr and return. Use timeout to avoid waiting 1680 * too long. 1681 * Only used during boot when interrupts are not enabled yet. 1682 */ 1683 void 1684 uhci_waitintr(uhci_softc_t *sc, usbd_xfer_handle xfer) 1685 { 1686 int timo = xfer->timeout; 1687 uhci_intr_info_t *ii; 1688 1689 mutex_enter(&sc->sc_lock); 1690 1691 DPRINTFN(10,("uhci_waitintr: timeout = %dms\n", timo)); 1692 1693 xfer->status = USBD_IN_PROGRESS; 1694 for (; timo >= 0; timo--) { 1695 usb_delay_ms(&sc->sc_bus, 1); 1696 DPRINTFN(20,("uhci_waitintr: 0x%04x\n", UREAD2(sc, UHCI_STS))); 1697 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1698 mutex_spin_enter(&sc->sc_intr_lock); 1699 uhci_intr1(sc); 1700 mutex_spin_exit(&sc->sc_intr_lock); 1701 if (xfer->status != USBD_IN_PROGRESS) 1702 goto done; 1703 } 1704 } 1705 1706 /* Timeout */ 1707 DPRINTF(("uhci_waitintr: timeout\n")); 1708 for (ii = LIST_FIRST(&sc->sc_intrhead); 1709 ii != NULL && ii->xfer != xfer; 1710 ii = LIST_NEXT(ii, list)) 1711 ; 1712 #ifdef DIAGNOSTIC 1713 if (ii == NULL) 1714 panic("uhci_waitintr: lost intr_info"); 1715 #endif 1716 uhci_idone(ii); 1717 1718 done: 1719 mutex_exit(&sc->sc_lock); 1720 } 1721 1722 void 1723 uhci_poll(struct usbd_bus *bus) 1724 { 1725 uhci_softc_t *sc = bus->hci_private; 1726 1727 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1728 mutex_spin_enter(&sc->sc_intr_lock); 1729 uhci_intr1(sc); 1730 mutex_spin_exit(&sc->sc_intr_lock); 1731 } 1732 } 1733 1734 void 1735 uhci_reset(uhci_softc_t *sc) 1736 { 1737 int n; 1738 1739 UHCICMD(sc, UHCI_CMD_HCRESET); 1740 /* The reset bit goes low when the controller is done. */ 1741 for (n = 0; n < UHCI_RESET_TIMEOUT && 1742 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1743 usb_delay_ms(&sc->sc_bus, 1); 1744 if (n >= UHCI_RESET_TIMEOUT) 1745 printf("%s: controller did not reset\n", 1746 device_xname(sc->sc_dev)); 1747 } 1748 1749 usbd_status 1750 uhci_run(uhci_softc_t *sc, int run) 1751 { 1752 int n, running; 1753 u_int16_t cmd; 1754 1755 run = run != 0; 1756 mutex_spin_enter(&sc->sc_intr_lock); 1757 DPRINTF(("uhci_run: setting run=%d\n", run)); 1758 cmd = UREAD2(sc, UHCI_CMD); 1759 if (run) 1760 cmd |= UHCI_CMD_RS; 1761 else 1762 cmd &= ~UHCI_CMD_RS; 1763 UHCICMD(sc, cmd); 1764 for(n = 0; n < 10; n++) { 1765 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1766 /* return when we've entered the state we want */ 1767 if (run == running) { 1768 mutex_spin_exit(&sc->sc_intr_lock); 1769 DPRINTF(("uhci_run: done cmd=0x%x sts=0x%x\n", 1770 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS))); 1771 return (USBD_NORMAL_COMPLETION); 1772 } 1773 usb_delay_ms(&sc->sc_bus, 1); 1774 } 1775 mutex_spin_exit(&sc->sc_intr_lock); 1776 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1777 run ? "start" : "stop"); 1778 return (USBD_IOERROR); 1779 } 1780 1781 /* 1782 * Memory management routines. 1783 * uhci_alloc_std allocates TDs 1784 * uhci_alloc_sqh allocates QHs 1785 * These two routines do their own free list management, 1786 * partly for speed, partly because allocating DMAable memory 1787 * has page size granularaity so much memory would be wasted if 1788 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1789 */ 1790 1791 uhci_soft_td_t * 1792 uhci_alloc_std(uhci_softc_t *sc) 1793 { 1794 uhci_soft_td_t *std; 1795 usbd_status err; 1796 int i, offs; 1797 usb_dma_t dma; 1798 1799 if (sc->sc_freetds == NULL) { 1800 DPRINTFN(2,("uhci_alloc_std: allocating chunk\n")); 1801 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1802 UHCI_TD_ALIGN, &dma); 1803 if (err) 1804 return (0); 1805 for (i = 0; i < UHCI_STD_CHUNK; i++) { 1806 offs = i * UHCI_STD_SIZE; 1807 std = KERNADDR(&dma, offs); 1808 std->physaddr = DMAADDR(&dma, offs); 1809 std->dma = dma; 1810 std->offs = offs; 1811 std->link.std = sc->sc_freetds; 1812 sc->sc_freetds = std; 1813 } 1814 } 1815 std = sc->sc_freetds; 1816 sc->sc_freetds = std->link.std; 1817 memset(&std->td, 0, sizeof(uhci_td_t)); 1818 return std; 1819 } 1820 1821 void 1822 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1823 { 1824 #ifdef DIAGNOSTIC 1825 #define TD_IS_FREE 0x12345678 1826 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1827 printf("uhci_free_std: freeing free TD %p\n", std); 1828 return; 1829 } 1830 std->td.td_token = htole32(TD_IS_FREE); 1831 #endif 1832 std->link.std = sc->sc_freetds; 1833 sc->sc_freetds = std; 1834 } 1835 1836 uhci_soft_qh_t * 1837 uhci_alloc_sqh(uhci_softc_t *sc) 1838 { 1839 uhci_soft_qh_t *sqh; 1840 usbd_status err; 1841 int i, offs; 1842 usb_dma_t dma; 1843 1844 if (sc->sc_freeqhs == NULL) { 1845 DPRINTFN(2, ("uhci_alloc_sqh: allocating chunk\n")); 1846 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1847 UHCI_QH_ALIGN, &dma); 1848 if (err) 1849 return (0); 1850 for(i = 0; i < UHCI_SQH_CHUNK; i++) { 1851 offs = i * UHCI_SQH_SIZE; 1852 sqh = KERNADDR(&dma, offs); 1853 sqh->physaddr = DMAADDR(&dma, offs); 1854 sqh->dma = dma; 1855 sqh->offs = offs; 1856 sqh->hlink = sc->sc_freeqhs; 1857 sc->sc_freeqhs = sqh; 1858 } 1859 } 1860 sqh = sc->sc_freeqhs; 1861 sc->sc_freeqhs = sqh->hlink; 1862 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1863 return (sqh); 1864 } 1865 1866 void 1867 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1868 { 1869 sqh->hlink = sc->sc_freeqhs; 1870 sc->sc_freeqhs = sqh; 1871 } 1872 1873 void 1874 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1875 uhci_soft_td_t *stdend) 1876 { 1877 uhci_soft_td_t *p; 1878 1879 /* 1880 * to avoid race condition with the controller which may be looking 1881 * at this chain, we need to first invalidate all links, and 1882 * then wait for the controller to move to another queue 1883 */ 1884 for (p = std; p != stdend; p = p->link.std) { 1885 usb_syncmem(&p->dma, 1886 p->offs + offsetof(uhci_td_t, td_link), 1887 sizeof(p->td.td_link), 1888 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1889 if ((p->td.td_link & UHCI_PTR_T) == 0) { 1890 p->td.td_link = UHCI_PTR_T; 1891 usb_syncmem(&p->dma, 1892 p->offs + offsetof(uhci_td_t, td_link), 1893 sizeof(p->td.td_link), 1894 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1895 } 1896 } 1897 delay(UHCI_QH_REMOVE_DELAY); 1898 1899 for (; std != stdend; std = p) { 1900 p = std->link.std; 1901 uhci_free_std(sc, std); 1902 } 1903 } 1904 1905 usbd_status 1906 uhci_alloc_std_chain(struct uhci_pipe *upipe, uhci_softc_t *sc, int len, 1907 int rd, u_int16_t flags, usb_dma_t *dma, 1908 uhci_soft_td_t **sp, uhci_soft_td_t **ep) 1909 { 1910 uhci_soft_td_t *p, *lastp; 1911 uhci_physaddr_t lastlink; 1912 int i, ntd, l, tog, maxp; 1913 u_int32_t status; 1914 int addr = upipe->pipe.device->address; 1915 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 1916 1917 DPRINTFN(8, ("uhci_alloc_std_chain: addr=%d endpt=%d len=%d speed=%d " 1918 "flags=0x%x\n", addr, UE_GET_ADDR(endpt), len, 1919 upipe->pipe.device->speed, flags)); 1920 1921 KASSERT(mutex_owned(&sc->sc_lock)); 1922 1923 maxp = UGETW(upipe->pipe.endpoint->edesc->wMaxPacketSize); 1924 if (maxp == 0) { 1925 printf("uhci_alloc_std_chain: maxp=0\n"); 1926 return (USBD_INVAL); 1927 } 1928 ntd = (len + maxp - 1) / maxp; 1929 if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0) 1930 ntd++; 1931 DPRINTFN(10, ("uhci_alloc_std_chain: maxp=%d ntd=%d\n", maxp, ntd)); 1932 if (ntd == 0) { 1933 *sp = *ep = 0; 1934 DPRINTFN(-1,("uhci_alloc_std_chain: ntd=0\n")); 1935 return (USBD_NORMAL_COMPLETION); 1936 } 1937 tog = upipe->nexttoggle; 1938 if (ntd % 2 == 0) 1939 tog ^= 1; 1940 upipe->nexttoggle = tog ^ 1; 1941 lastp = NULL; 1942 lastlink = UHCI_PTR_T; 1943 ntd--; 1944 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 1945 if (upipe->pipe.device->speed == USB_SPEED_LOW) 1946 status |= UHCI_TD_LS; 1947 if (flags & USBD_SHORT_XFER_OK) 1948 status |= UHCI_TD_SPD; 1949 usb_syncmem(dma, 0, len, 1950 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1951 for (i = ntd; i >= 0; i--) { 1952 p = uhci_alloc_std(sc); 1953 if (p == NULL) { 1954 KASSERT(lastp != NULL); 1955 uhci_free_std_chain(sc, lastp, NULL); 1956 return (USBD_NOMEM); 1957 } 1958 p->link.std = lastp; 1959 p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD); 1960 lastp = p; 1961 lastlink = p->physaddr; 1962 p->td.td_status = htole32(status); 1963 if (i == ntd) { 1964 /* last TD */ 1965 l = len % maxp; 1966 if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER)) 1967 l = maxp; 1968 *ep = p; 1969 } else 1970 l = maxp; 1971 p->td.td_token = 1972 htole32(rd ? UHCI_TD_IN (l, endpt, addr, tog) : 1973 UHCI_TD_OUT(l, endpt, addr, tog)); 1974 p->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 1975 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 1976 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1977 tog ^= 1; 1978 } 1979 *sp = lastp; 1980 DPRINTFN(10, ("uhci_alloc_std_chain: nexttog=%d\n", 1981 upipe->nexttoggle)); 1982 return (USBD_NORMAL_COMPLETION); 1983 } 1984 1985 void 1986 uhci_device_clear_toggle(usbd_pipe_handle pipe) 1987 { 1988 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 1989 upipe->nexttoggle = 0; 1990 } 1991 1992 void 1993 uhci_noop(usbd_pipe_handle pipe) 1994 { 1995 } 1996 1997 usbd_status 1998 uhci_device_bulk_transfer(usbd_xfer_handle xfer) 1999 { 2000 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2001 usbd_status err; 2002 2003 /* Insert last in queue. */ 2004 mutex_enter(&sc->sc_lock); 2005 err = usb_insert_transfer(xfer); 2006 mutex_exit(&sc->sc_lock); 2007 if (err) 2008 return (err); 2009 2010 /* 2011 * Pipe isn't running (otherwise err would be USBD_INPROG), 2012 * so start it first. 2013 */ 2014 return (uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2015 } 2016 2017 usbd_status 2018 uhci_device_bulk_start(usbd_xfer_handle xfer) 2019 { 2020 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2021 usbd_device_handle dev = upipe->pipe.device; 2022 uhci_softc_t *sc = dev->bus->hci_private; 2023 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2024 uhci_soft_td_t *data, *dataend; 2025 uhci_soft_qh_t *sqh; 2026 usbd_status err; 2027 int len, isread, endpt; 2028 2029 DPRINTFN(3, ("uhci_device_bulk_start: xfer=%p len=%d flags=%d ii=%p\n", 2030 xfer, xfer->length, xfer->flags, ii)); 2031 2032 if (sc->sc_dying) 2033 return (USBD_IOERROR); 2034 2035 #ifdef DIAGNOSTIC 2036 if (xfer->rqflags & URQ_REQUEST) 2037 panic("uhci_device_bulk_transfer: a request"); 2038 #endif 2039 2040 mutex_enter(&sc->sc_lock); 2041 2042 len = xfer->length; 2043 endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2044 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2045 sqh = upipe->u.bulk.sqh; 2046 2047 upipe->u.bulk.isread = isread; 2048 upipe->u.bulk.length = len; 2049 2050 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->flags, 2051 &xfer->dmabuf, &data, &dataend); 2052 if (err) { 2053 mutex_exit(&sc->sc_lock); 2054 return (err); 2055 } 2056 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2057 usb_syncmem(&dataend->dma, 2058 dataend->offs + offsetof(uhci_td_t, td_status), 2059 sizeof(dataend->td.td_status), 2060 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2061 2062 2063 #ifdef UHCI_DEBUG 2064 if (uhcidebug > 8) { 2065 DPRINTF(("uhci_device_bulk_transfer: data(1)\n")); 2066 uhci_dump_tds(data); 2067 } 2068 #endif 2069 2070 /* Set up interrupt info. */ 2071 ii->xfer = xfer; 2072 ii->stdstart = data; 2073 ii->stdend = dataend; 2074 #ifdef DIAGNOSTIC 2075 if (!ii->isdone) { 2076 printf("uhci_device_bulk_transfer: not done, ii=%p\n", ii); 2077 } 2078 ii->isdone = 0; 2079 #endif 2080 2081 sqh->elink = data; 2082 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2083 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2084 2085 uhci_add_bulk(sc, sqh); 2086 uhci_add_intr_info(sc, ii); 2087 2088 if (xfer->timeout && !sc->sc_bus.use_polling) { 2089 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 2090 uhci_timeout, ii); 2091 } 2092 xfer->status = USBD_IN_PROGRESS; 2093 2094 #ifdef UHCI_DEBUG 2095 if (uhcidebug > 10) { 2096 DPRINTF(("uhci_device_bulk_transfer: data(2)\n")); 2097 uhci_dump_tds(data); 2098 } 2099 #endif 2100 2101 if (sc->sc_bus.use_polling) 2102 uhci_waitintr(sc, xfer); 2103 2104 mutex_exit(&sc->sc_lock); 2105 return (USBD_IN_PROGRESS); 2106 } 2107 2108 /* Abort a device bulk request. */ 2109 void 2110 uhci_device_bulk_abort(usbd_xfer_handle xfer) 2111 { 2112 #ifdef DIAGNOSTIC 2113 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2114 #endif 2115 2116 KASSERT(mutex_owned(&sc->sc_lock)); 2117 2118 DPRINTF(("uhci_device_bulk_abort:\n")); 2119 uhci_abort_xfer(xfer, USBD_CANCELLED); 2120 } 2121 2122 /* 2123 * Abort a device request. 2124 * If this routine is called at splusb() it guarantees that the request 2125 * will be removed from the hardware scheduling and that the callback 2126 * for it will be called with USBD_CANCELLED status. 2127 * It's impossible to guarantee that the requested transfer will not 2128 * have happened since the hardware runs concurrently. 2129 * If the transaction has already happened we rely on the ordinary 2130 * interrupt processing to process it. 2131 * XXX This is most probably wrong. 2132 * XXXMRG this doesn't make sense anymore. 2133 */ 2134 void 2135 uhci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2136 { 2137 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2138 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2139 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 2140 uhci_soft_td_t *std; 2141 int wake; 2142 2143 DPRINTFN(1,("uhci_abort_xfer: xfer=%p, status=%d\n", xfer, status)); 2144 2145 KASSERT(mutex_owned(&sc->sc_lock)); 2146 2147 if (sc->sc_dying) { 2148 /* If we're dying, just do the software part. */ 2149 xfer->status = status; /* make software ignore it */ 2150 callout_stop(&xfer->timeout_handle); 2151 usb_transfer_complete(xfer); 2152 return; 2153 } 2154 2155 if (xfer->device->bus->intr_context || !curproc) 2156 panic("uhci_abort_xfer: not in process context"); 2157 2158 /* 2159 * If an abort is already in progress then just wait for it to 2160 * complete and return. 2161 */ 2162 if (xfer->hcflags & UXFER_ABORTING) { 2163 DPRINTFN(2, ("uhci_abort_xfer: already aborting\n")); 2164 #ifdef DIAGNOSTIC 2165 if (status == USBD_TIMEOUT) 2166 printf("uhci_abort_xfer: TIMEOUT while aborting\n"); 2167 #endif 2168 /* Override the status which might be USBD_TIMEOUT. */ 2169 xfer->status = status; 2170 DPRINTFN(2, ("uhci_abort_xfer: waiting for abort to finish\n")); 2171 xfer->hcflags |= UXFER_ABORTWAIT; 2172 while (xfer->hcflags & UXFER_ABORTING) 2173 cv_wait(&xfer->hccv, &sc->sc_lock); 2174 goto done; 2175 } 2176 xfer->hcflags |= UXFER_ABORTING; 2177 2178 /* 2179 * Step 1: Make interrupt routine and hardware ignore xfer. 2180 */ 2181 xfer->status = status; /* make software ignore it */ 2182 callout_stop(&xfer->timeout_handle); 2183 DPRINTFN(1,("uhci_abort_xfer: stop ii=%p\n", ii)); 2184 for (std = ii->stdstart; std != NULL; std = std->link.std) { 2185 usb_syncmem(&std->dma, 2186 std->offs + offsetof(uhci_td_t, td_status), 2187 sizeof(std->td.td_status), 2188 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2189 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2190 usb_syncmem(&std->dma, 2191 std->offs + offsetof(uhci_td_t, td_status), 2192 sizeof(std->td.td_status), 2193 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2194 } 2195 2196 /* 2197 * Step 2: Wait until we know hardware has finished any possible 2198 * use of the xfer. Also make sure the soft interrupt routine 2199 * has run. 2200 */ 2201 usb_delay_ms(upipe->pipe.device->bus, 2); /* Hardware finishes in 1ms */ 2202 sc->sc_softwake = 1; 2203 usb_schedsoftintr(&sc->sc_bus); 2204 DPRINTFN(1,("uhci_abort_xfer: cv_wait\n")); 2205 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2206 2207 /* 2208 * Step 3: Execute callback. 2209 */ 2210 DPRINTFN(1,("uhci_abort_xfer: callback\n")); 2211 #ifdef DIAGNOSTIC 2212 ii->isdone = 1; 2213 #endif 2214 wake = xfer->hcflags & UXFER_ABORTWAIT; 2215 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2216 usb_transfer_complete(xfer); 2217 if (wake) 2218 cv_broadcast(&xfer->hccv); 2219 done: 2220 KASSERT(mutex_owned(&sc->sc_lock)); 2221 } 2222 2223 /* Close a device bulk pipe. */ 2224 void 2225 uhci_device_bulk_close(usbd_pipe_handle pipe) 2226 { 2227 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2228 usbd_device_handle dev = upipe->pipe.device; 2229 uhci_softc_t *sc = dev->bus->hci_private; 2230 2231 KASSERT(mutex_owned(&sc->sc_lock)); 2232 2233 uhci_free_sqh(sc, upipe->u.bulk.sqh); 2234 2235 pipe->endpoint->datatoggle = upipe->nexttoggle; 2236 } 2237 2238 usbd_status 2239 uhci_device_ctrl_transfer(usbd_xfer_handle xfer) 2240 { 2241 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2242 usbd_status err; 2243 2244 /* Insert last in queue. */ 2245 mutex_enter(&sc->sc_lock); 2246 err = usb_insert_transfer(xfer); 2247 mutex_exit(&sc->sc_lock); 2248 if (err) 2249 return (err); 2250 2251 /* 2252 * Pipe isn't running (otherwise err would be USBD_INPROG), 2253 * so start it first. 2254 */ 2255 return (uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2256 } 2257 2258 usbd_status 2259 uhci_device_ctrl_start(usbd_xfer_handle xfer) 2260 { 2261 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2262 usbd_status err; 2263 2264 if (sc->sc_dying) 2265 return (USBD_IOERROR); 2266 2267 #ifdef DIAGNOSTIC 2268 if (!(xfer->rqflags & URQ_REQUEST)) 2269 panic("uhci_device_ctrl_transfer: not a request"); 2270 #endif 2271 2272 mutex_enter(&sc->sc_lock); 2273 err = uhci_device_request(xfer); 2274 mutex_exit(&sc->sc_lock); 2275 if (err) 2276 return (err); 2277 2278 if (sc->sc_bus.use_polling) 2279 uhci_waitintr(sc, xfer); 2280 return (USBD_IN_PROGRESS); 2281 } 2282 2283 usbd_status 2284 uhci_device_intr_transfer(usbd_xfer_handle xfer) 2285 { 2286 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2287 usbd_status err; 2288 2289 /* Insert last in queue. */ 2290 mutex_enter(&sc->sc_lock); 2291 err = usb_insert_transfer(xfer); 2292 mutex_exit(&sc->sc_lock); 2293 if (err) 2294 return (err); 2295 2296 /* 2297 * Pipe isn't running (otherwise err would be USBD_INPROG), 2298 * so start it first. 2299 */ 2300 return (uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2301 } 2302 2303 usbd_status 2304 uhci_device_intr_start(usbd_xfer_handle xfer) 2305 { 2306 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2307 usbd_device_handle dev = upipe->pipe.device; 2308 uhci_softc_t *sc = dev->bus->hci_private; 2309 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2310 uhci_soft_td_t *data, *dataend; 2311 uhci_soft_qh_t *sqh; 2312 usbd_status err; 2313 int isread, endpt; 2314 int i; 2315 2316 if (sc->sc_dying) 2317 return (USBD_IOERROR); 2318 2319 DPRINTFN(3,("uhci_device_intr_transfer: xfer=%p len=%d flags=%d\n", 2320 xfer, xfer->length, xfer->flags)); 2321 2322 #ifdef DIAGNOSTIC 2323 if (xfer->rqflags & URQ_REQUEST) 2324 panic("uhci_device_intr_transfer: a request"); 2325 #endif 2326 2327 endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2328 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2329 2330 upipe->u.intr.isread = isread; 2331 2332 err = uhci_alloc_std_chain(upipe, sc, xfer->length, isread, 2333 xfer->flags, &xfer->dmabuf, &data, 2334 &dataend); 2335 if (err) 2336 return (err); 2337 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2338 usb_syncmem(&dataend->dma, 2339 dataend->offs + offsetof(uhci_td_t, td_status), 2340 sizeof(dataend->td.td_status), 2341 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2342 2343 #ifdef UHCI_DEBUG 2344 if (uhcidebug > 10) { 2345 DPRINTF(("uhci_device_intr_transfer: data(1)\n")); 2346 uhci_dump_tds(data); 2347 uhci_dump_qh(upipe->u.intr.qhs[0]); 2348 } 2349 #endif 2350 2351 mutex_enter(&sc->sc_lock); 2352 /* Set up interrupt info. */ 2353 ii->xfer = xfer; 2354 ii->stdstart = data; 2355 ii->stdend = dataend; 2356 #ifdef DIAGNOSTIC 2357 if (!ii->isdone) { 2358 printf("uhci_device_intr_transfer: not done, ii=%p\n", ii); 2359 } 2360 ii->isdone = 0; 2361 #endif 2362 2363 DPRINTFN(10,("uhci_device_intr_transfer: qhs[0]=%p\n", 2364 upipe->u.intr.qhs[0])); 2365 for (i = 0; i < upipe->u.intr.npoll; i++) { 2366 sqh = upipe->u.intr.qhs[i]; 2367 sqh->elink = data; 2368 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2369 usb_syncmem(&sqh->dma, 2370 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2371 sizeof(sqh->qh.qh_elink), 2372 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2373 } 2374 uhci_add_intr_info(sc, ii); 2375 xfer->status = USBD_IN_PROGRESS; 2376 mutex_exit(&sc->sc_lock); 2377 2378 #ifdef UHCI_DEBUG 2379 if (uhcidebug > 10) { 2380 DPRINTF(("uhci_device_intr_transfer: data(2)\n")); 2381 uhci_dump_tds(data); 2382 uhci_dump_qh(upipe->u.intr.qhs[0]); 2383 } 2384 #endif 2385 2386 return (USBD_IN_PROGRESS); 2387 } 2388 2389 /* Abort a device control request. */ 2390 void 2391 uhci_device_ctrl_abort(usbd_xfer_handle xfer) 2392 { 2393 #ifdef DIAGNOSTIC 2394 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2395 #endif 2396 2397 KASSERT(mutex_owned(&sc->sc_lock)); 2398 2399 DPRINTF(("uhci_device_ctrl_abort:\n")); 2400 uhci_abort_xfer(xfer, USBD_CANCELLED); 2401 } 2402 2403 /* Close a device control pipe. */ 2404 void 2405 uhci_device_ctrl_close(usbd_pipe_handle pipe) 2406 { 2407 } 2408 2409 /* Abort a device interrupt request. */ 2410 void 2411 uhci_device_intr_abort(usbd_xfer_handle xfer) 2412 { 2413 #ifdef DIAGNOSTIC 2414 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2415 #endif 2416 2417 KASSERT(mutex_owned(&sc->sc_lock)); 2418 2419 DPRINTFN(1,("uhci_device_intr_abort: xfer=%p\n", xfer)); 2420 if (xfer->pipe->intrxfer == xfer) { 2421 DPRINTFN(1,("uhci_device_intr_abort: remove\n")); 2422 xfer->pipe->intrxfer = NULL; 2423 } 2424 uhci_abort_xfer(xfer, USBD_CANCELLED); 2425 } 2426 2427 /* Close a device interrupt pipe. */ 2428 void 2429 uhci_device_intr_close(usbd_pipe_handle pipe) 2430 { 2431 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2432 uhci_softc_t *sc = pipe->device->bus->hci_private; 2433 int i, npoll; 2434 2435 KASSERT(mutex_owned(&sc->sc_lock)); 2436 2437 /* Unlink descriptors from controller data structures. */ 2438 npoll = upipe->u.intr.npoll; 2439 for (i = 0; i < npoll; i++) 2440 uhci_remove_intr(sc, upipe->u.intr.qhs[i]); 2441 2442 /* 2443 * We now have to wait for any activity on the physical 2444 * descriptors to stop. 2445 */ 2446 usb_delay_ms(&sc->sc_bus, 2); 2447 2448 for(i = 0; i < npoll; i++) 2449 uhci_free_sqh(sc, upipe->u.intr.qhs[i]); 2450 kmem_free(upipe->u.intr.qhs, npoll * sizeof(uhci_soft_qh_t *)); 2451 2452 /* XXX free other resources */ 2453 } 2454 2455 usbd_status 2456 uhci_device_request(usbd_xfer_handle xfer) 2457 { 2458 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2459 usb_device_request_t *req = &xfer->request; 2460 usbd_device_handle dev = upipe->pipe.device; 2461 uhci_softc_t *sc = dev->bus->hci_private; 2462 int addr = dev->address; 2463 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2464 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2465 uhci_soft_td_t *setup, *data, *stat, *next, *dataend; 2466 uhci_soft_qh_t *sqh; 2467 int len; 2468 u_int32_t ls; 2469 usbd_status err; 2470 int isread; 2471 2472 KASSERT(mutex_owned(&sc->sc_lock)); 2473 2474 DPRINTFN(3,("uhci_device_control type=0x%02x, request=0x%02x, " 2475 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 2476 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2477 UGETW(req->wIndex), UGETW(req->wLength), 2478 addr, endpt)); 2479 2480 ls = dev->speed == USB_SPEED_LOW ? UHCI_TD_LS : 0; 2481 isread = req->bmRequestType & UT_READ; 2482 len = UGETW(req->wLength); 2483 2484 setup = upipe->u.ctl.setup; 2485 stat = upipe->u.ctl.stat; 2486 sqh = upipe->u.ctl.sqh; 2487 2488 /* Set up data transaction */ 2489 if (len != 0) { 2490 upipe->nexttoggle = 1; 2491 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->flags, 2492 &xfer->dmabuf, &data, &dataend); 2493 if (err) 2494 return (err); 2495 next = data; 2496 dataend->link.std = stat; 2497 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_VF | UHCI_PTR_TD); 2498 usb_syncmem(&dataend->dma, 2499 dataend->offs + offsetof(uhci_td_t, td_link), 2500 sizeof(dataend->td.td_link), 2501 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2502 } else { 2503 next = stat; 2504 } 2505 upipe->u.ctl.length = len; 2506 2507 memcpy(KERNADDR(&upipe->u.ctl.reqdma, 0), req, sizeof *req); 2508 usb_syncmem(&upipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 2509 2510 setup->link.std = next; 2511 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_VF | UHCI_PTR_TD); 2512 setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2513 UHCI_TD_ACTIVE); 2514 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof *req, endpt, addr)); 2515 setup->td.td_buffer = htole32(DMAADDR(&upipe->u.ctl.reqdma, 0)); 2516 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2517 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2518 2519 stat->link.std = NULL; 2520 stat->td.td_link = htole32(UHCI_PTR_T); 2521 stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2522 UHCI_TD_ACTIVE | UHCI_TD_IOC); 2523 stat->td.td_token = 2524 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2525 UHCI_TD_IN (0, endpt, addr, 1)); 2526 stat->td.td_buffer = htole32(0); 2527 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2528 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2529 2530 #ifdef UHCI_DEBUG 2531 if (uhcidebug > 10) { 2532 DPRINTF(("uhci_device_request: before transfer\n")); 2533 uhci_dump_tds(setup); 2534 } 2535 #endif 2536 2537 /* Set up interrupt info. */ 2538 ii->xfer = xfer; 2539 ii->stdstart = setup; 2540 ii->stdend = stat; 2541 #ifdef DIAGNOSTIC 2542 if (!ii->isdone) { 2543 printf("uhci_device_request: not done, ii=%p\n", ii); 2544 } 2545 ii->isdone = 0; 2546 #endif 2547 2548 sqh->elink = setup; 2549 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2550 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2551 2552 if (dev->speed == USB_SPEED_LOW) 2553 uhci_add_ls_ctrl(sc, sqh); 2554 else 2555 uhci_add_hs_ctrl(sc, sqh); 2556 uhci_add_intr_info(sc, ii); 2557 #ifdef UHCI_DEBUG 2558 if (uhcidebug > 12) { 2559 uhci_soft_td_t *std; 2560 uhci_soft_qh_t *xqh; 2561 uhci_soft_qh_t *sxqh; 2562 int maxqh = 0; 2563 uhci_physaddr_t link; 2564 DPRINTF(("uhci_enter_ctl_q: follow from [0]\n")); 2565 for (std = sc->sc_vframes[0].htd, link = 0; 2566 (link & UHCI_PTR_QH) == 0; 2567 std = std->link.std) { 2568 link = le32toh(std->td.td_link); 2569 uhci_dump_td(std); 2570 } 2571 sxqh = (uhci_soft_qh_t *)std; 2572 uhci_dump_qh(sxqh); 2573 for (xqh = sxqh; 2574 xqh != NULL; 2575 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2576 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2577 uhci_dump_qh(xqh); 2578 } 2579 DPRINTF(("Enqueued QH:\n")); 2580 uhci_dump_qh(sqh); 2581 uhci_dump_tds(sqh->elink); 2582 } 2583 #endif 2584 if (xfer->timeout && !sc->sc_bus.use_polling) { 2585 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 2586 uhci_timeout, ii); 2587 } 2588 xfer->status = USBD_IN_PROGRESS; 2589 2590 return (USBD_NORMAL_COMPLETION); 2591 } 2592 2593 usbd_status 2594 uhci_device_isoc_transfer(usbd_xfer_handle xfer) 2595 { 2596 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2597 usbd_status err; 2598 2599 DPRINTFN(5,("uhci_device_isoc_transfer: xfer=%p\n", xfer)); 2600 2601 /* Put it on our queue, */ 2602 mutex_enter(&sc->sc_lock); 2603 err = usb_insert_transfer(xfer); 2604 mutex_exit(&sc->sc_lock); 2605 2606 /* bail out on error, */ 2607 if (err && err != USBD_IN_PROGRESS) 2608 return (err); 2609 2610 /* XXX should check inuse here */ 2611 2612 /* insert into schedule, */ 2613 uhci_device_isoc_enter(xfer); 2614 2615 /* and start if the pipe wasn't running */ 2616 if (!err) 2617 uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 2618 2619 return (err); 2620 } 2621 2622 void 2623 uhci_device_isoc_enter(usbd_xfer_handle xfer) 2624 { 2625 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2626 usbd_device_handle dev = upipe->pipe.device; 2627 uhci_softc_t *sc = dev->bus->hci_private; 2628 struct iso *iso = &upipe->u.iso; 2629 uhci_soft_td_t *std; 2630 u_int32_t buf, len, status, offs; 2631 int i, next, nframes; 2632 int rd = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2633 2634 DPRINTFN(5,("uhci_device_isoc_enter: used=%d next=%d xfer=%p " 2635 "nframes=%d\n", 2636 iso->inuse, iso->next, xfer, xfer->nframes)); 2637 2638 if (sc->sc_dying) 2639 return; 2640 2641 if (xfer->status == USBD_IN_PROGRESS) { 2642 /* This request has already been entered into the frame list */ 2643 printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer); 2644 /* XXX */ 2645 } 2646 2647 #ifdef DIAGNOSTIC 2648 if (iso->inuse >= UHCI_VFRAMELIST_COUNT) 2649 printf("uhci_device_isoc_enter: overflow!\n"); 2650 #endif 2651 2652 next = iso->next; 2653 if (next == -1) { 2654 /* Not in use yet, schedule it a few frames ahead. */ 2655 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 2656 DPRINTFN(2,("uhci_device_isoc_enter: start next=%d\n", next)); 2657 } 2658 2659 xfer->status = USBD_IN_PROGRESS; 2660 UXFER(xfer)->curframe = next; 2661 2662 buf = DMAADDR(&xfer->dmabuf, 0); 2663 offs = 0; 2664 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 2665 UHCI_TD_ACTIVE | 2666 UHCI_TD_IOS); 2667 nframes = xfer->nframes; 2668 mutex_enter(&sc->sc_lock); 2669 for (i = 0; i < nframes; i++) { 2670 std = iso->stds[next]; 2671 if (++next >= UHCI_VFRAMELIST_COUNT) 2672 next = 0; 2673 len = xfer->frlengths[i]; 2674 std->td.td_buffer = htole32(buf); 2675 usb_syncmem(&xfer->dmabuf, offs, len, 2676 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2677 if (i == nframes - 1) 2678 status |= UHCI_TD_IOC; 2679 std->td.td_status = htole32(status); 2680 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2681 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 2682 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2683 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2684 #ifdef UHCI_DEBUG 2685 if (uhcidebug > 5) { 2686 DPRINTFN(5,("uhci_device_isoc_enter: TD %d\n", i)); 2687 uhci_dump_td(std); 2688 } 2689 #endif 2690 buf += len; 2691 offs += len; 2692 } 2693 iso->next = next; 2694 iso->inuse += xfer->nframes; 2695 2696 mutex_exit(&sc->sc_lock); 2697 } 2698 2699 usbd_status 2700 uhci_device_isoc_start(usbd_xfer_handle xfer) 2701 { 2702 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2703 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 2704 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2705 uhci_soft_td_t *end; 2706 int i; 2707 2708 DPRINTFN(5,("uhci_device_isoc_start: xfer=%p\n", xfer)); 2709 2710 mutex_enter(&sc->sc_lock); 2711 2712 if (sc->sc_dying) { 2713 mutex_exit(&sc->sc_lock); 2714 return (USBD_IOERROR); 2715 } 2716 2717 #ifdef DIAGNOSTIC 2718 if (xfer->status != USBD_IN_PROGRESS) 2719 printf("uhci_device_isoc_start: not in progress %p\n", xfer); 2720 #endif 2721 2722 /* Find the last TD */ 2723 i = UXFER(xfer)->curframe + xfer->nframes; 2724 if (i >= UHCI_VFRAMELIST_COUNT) 2725 i -= UHCI_VFRAMELIST_COUNT; 2726 end = upipe->u.iso.stds[i]; 2727 2728 #ifdef DIAGNOSTIC 2729 if (end == NULL) { 2730 printf("uhci_device_isoc_start: end == NULL\n"); 2731 return (USBD_INVAL); 2732 } 2733 #endif 2734 2735 /* Set up interrupt info. */ 2736 ii->xfer = xfer; 2737 ii->stdstart = end; 2738 ii->stdend = end; 2739 #ifdef DIAGNOSTIC 2740 if (!ii->isdone) 2741 printf("uhci_device_isoc_start: not done, ii=%p\n", ii); 2742 ii->isdone = 0; 2743 #endif 2744 uhci_add_intr_info(sc, ii); 2745 2746 mutex_exit(&sc->sc_lock); 2747 2748 return (USBD_IN_PROGRESS); 2749 } 2750 2751 void 2752 uhci_device_isoc_abort(usbd_xfer_handle xfer) 2753 { 2754 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2755 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2756 uhci_soft_td_t **stds = upipe->u.iso.stds; 2757 uhci_soft_td_t *std; 2758 int i, n, nframes, maxlen, len; 2759 2760 KASSERT(mutex_owned(&sc->sc_lock)); 2761 2762 /* Transfer is already done. */ 2763 if (xfer->status != USBD_NOT_STARTED && 2764 xfer->status != USBD_IN_PROGRESS) { 2765 return; 2766 } 2767 2768 /* Give xfer the requested abort code. */ 2769 xfer->status = USBD_CANCELLED; 2770 2771 /* make hardware ignore it, */ 2772 nframes = xfer->nframes; 2773 n = UXFER(xfer)->curframe; 2774 maxlen = 0; 2775 for (i = 0; i < nframes; i++) { 2776 std = stds[n]; 2777 usb_syncmem(&std->dma, 2778 std->offs + offsetof(uhci_td_t, td_status), 2779 sizeof(std->td.td_status), 2780 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2781 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2782 usb_syncmem(&std->dma, 2783 std->offs + offsetof(uhci_td_t, td_status), 2784 sizeof(std->td.td_status), 2785 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2786 usb_syncmem(&std->dma, 2787 std->offs + offsetof(uhci_td_t, td_token), 2788 sizeof(std->td.td_token), 2789 BUS_DMASYNC_POSTWRITE); 2790 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 2791 if (len > maxlen) 2792 maxlen = len; 2793 if (++n >= UHCI_VFRAMELIST_COUNT) 2794 n = 0; 2795 } 2796 2797 /* and wait until we are sure the hardware has finished. */ 2798 delay(maxlen); 2799 2800 #ifdef DIAGNOSTIC 2801 UXFER(xfer)->iinfo.isdone = 1; 2802 #endif 2803 /* Run callback and remove from interrupt list. */ 2804 usb_transfer_complete(xfer); 2805 2806 KASSERT(mutex_owned(&sc->sc_lock)); 2807 } 2808 2809 void 2810 uhci_device_isoc_close(usbd_pipe_handle pipe) 2811 { 2812 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2813 usbd_device_handle dev = upipe->pipe.device; 2814 uhci_softc_t *sc = dev->bus->hci_private; 2815 uhci_soft_td_t *std, *vstd; 2816 struct iso *iso; 2817 int i; 2818 2819 KASSERT(mutex_owned(&sc->sc_lock)); 2820 2821 /* 2822 * Make sure all TDs are marked as inactive. 2823 * Wait for completion. 2824 * Unschedule. 2825 * Deallocate. 2826 */ 2827 iso = &upipe->u.iso; 2828 2829 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2830 std = iso->stds[i]; 2831 usb_syncmem(&std->dma, 2832 std->offs + offsetof(uhci_td_t, td_status), 2833 sizeof(std->td.td_status), 2834 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2835 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 2836 usb_syncmem(&std->dma, 2837 std->offs + offsetof(uhci_td_t, td_status), 2838 sizeof(std->td.td_status), 2839 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2840 } 2841 usb_delay_ms(&sc->sc_bus, 2); /* wait for completion */ 2842 2843 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2844 std = iso->stds[i]; 2845 for (vstd = sc->sc_vframes[i].htd; 2846 vstd != NULL && vstd->link.std != std; 2847 vstd = vstd->link.std) 2848 ; 2849 if (vstd == NULL) { 2850 /*panic*/ 2851 printf("uhci_device_isoc_close: %p not found\n", std); 2852 mutex_exit(&sc->sc_lock); 2853 return; 2854 } 2855 vstd->link = std->link; 2856 usb_syncmem(&std->dma, 2857 std->offs + offsetof(uhci_td_t, td_link), 2858 sizeof(std->td.td_link), 2859 BUS_DMASYNC_POSTWRITE); 2860 vstd->td.td_link = std->td.td_link; 2861 usb_syncmem(&vstd->dma, 2862 vstd->offs + offsetof(uhci_td_t, td_link), 2863 sizeof(vstd->td.td_link), 2864 BUS_DMASYNC_PREWRITE); 2865 uhci_free_std(sc, std); 2866 } 2867 2868 kmem_free(iso->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *)); 2869 } 2870 2871 usbd_status 2872 uhci_setup_isoc(usbd_pipe_handle pipe) 2873 { 2874 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2875 usbd_device_handle dev = upipe->pipe.device; 2876 uhci_softc_t *sc = dev->bus->hci_private; 2877 int addr = upipe->pipe.device->address; 2878 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2879 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 2880 uhci_soft_td_t *std, *vstd; 2881 u_int32_t token; 2882 struct iso *iso; 2883 int i; 2884 2885 iso = &upipe->u.iso; 2886 iso->stds = kmem_alloc(UHCI_VFRAMELIST_COUNT * 2887 sizeof (uhci_soft_td_t *), 2888 KM_SLEEP); 2889 if (iso->stds == NULL) 2890 return USBD_NOMEM; 2891 2892 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 2893 UHCI_TD_OUT(0, endpt, addr, 0); 2894 2895 mutex_enter(&sc->sc_lock); 2896 2897 /* Allocate the TDs and mark as inactive; */ 2898 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2899 std = uhci_alloc_std(sc); 2900 if (std == 0) 2901 goto bad; 2902 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 2903 std->td.td_token = htole32(token); 2904 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2905 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2906 iso->stds[i] = std; 2907 } 2908 2909 /* Insert TDs into schedule. */ 2910 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2911 std = iso->stds[i]; 2912 vstd = sc->sc_vframes[i].htd; 2913 usb_syncmem(&vstd->dma, 2914 vstd->offs + offsetof(uhci_td_t, td_link), 2915 sizeof(vstd->td.td_link), 2916 BUS_DMASYNC_POSTWRITE); 2917 std->link = vstd->link; 2918 std->td.td_link = vstd->td.td_link; 2919 usb_syncmem(&std->dma, 2920 std->offs + offsetof(uhci_td_t, td_link), 2921 sizeof(std->td.td_link), 2922 BUS_DMASYNC_PREWRITE); 2923 vstd->link.std = std; 2924 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 2925 usb_syncmem(&vstd->dma, 2926 vstd->offs + offsetof(uhci_td_t, td_link), 2927 sizeof(vstd->td.td_link), 2928 BUS_DMASYNC_PREWRITE); 2929 } 2930 mutex_exit(&sc->sc_lock); 2931 2932 iso->next = -1; 2933 iso->inuse = 0; 2934 2935 return (USBD_NORMAL_COMPLETION); 2936 2937 bad: 2938 while (--i >= 0) 2939 uhci_free_std(sc, iso->stds[i]); 2940 mutex_exit(&sc->sc_lock); 2941 kmem_free(iso->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *)); 2942 return (USBD_NOMEM); 2943 } 2944 2945 void 2946 uhci_device_isoc_done(usbd_xfer_handle xfer) 2947 { 2948 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2949 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2950 int i, offs; 2951 int rd = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2952 2953 2954 DPRINTFN(4, ("uhci_isoc_done: length=%d, busy_free=0x%08x\n", 2955 xfer->actlen, xfer->busy_free)); 2956 2957 if (ii->xfer != xfer) 2958 /* Not on interrupt list, ignore it. */ 2959 return; 2960 2961 if (!uhci_active_intr_info(ii)) 2962 return; 2963 2964 #ifdef DIAGNOSTIC 2965 if (ii->stdend == NULL) { 2966 printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer); 2967 #ifdef UHCI_DEBUG 2968 uhci_dump_ii(ii); 2969 #endif 2970 return; 2971 } 2972 #endif 2973 2974 /* Turn off the interrupt since it is active even if the TD is not. */ 2975 usb_syncmem(&ii->stdend->dma, 2976 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2977 sizeof(ii->stdend->td.td_status), 2978 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2979 ii->stdend->td.td_status &= htole32(~UHCI_TD_IOC); 2980 usb_syncmem(&ii->stdend->dma, 2981 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2982 sizeof(ii->stdend->td.td_status), 2983 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2984 2985 uhci_del_intr_info(ii); /* remove from active list */ 2986 2987 offs = 0; 2988 for (i = 0; i < xfer->nframes; i++) { 2989 usb_syncmem(&xfer->dmabuf, offs, xfer->frlengths[i], 2990 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2991 offs += xfer->frlengths[i]; 2992 } 2993 } 2994 2995 void 2996 uhci_device_intr_done(usbd_xfer_handle xfer) 2997 { 2998 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2999 uhci_softc_t *sc = ii->sc; 3000 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 3001 uhci_soft_qh_t *sqh; 3002 int i, npoll, isread; 3003 3004 DPRINTFN(5, ("uhci_device_intr_done: length=%d\n", xfer->actlen)); 3005 3006 KASSERT(mutex_owned(&sc->sc_lock)); 3007 3008 npoll = upipe->u.intr.npoll; 3009 for(i = 0; i < npoll; i++) { 3010 sqh = upipe->u.intr.qhs[i]; 3011 sqh->elink = NULL; 3012 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3013 usb_syncmem(&sqh->dma, 3014 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3015 sizeof(sqh->qh.qh_elink), 3016 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3017 } 3018 uhci_free_std_chain(sc, ii->stdstart, NULL); 3019 3020 isread = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 3021 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3022 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3023 3024 /* XXX Wasteful. */ 3025 if (xfer->pipe->repeat) { 3026 uhci_soft_td_t *data, *dataend; 3027 3028 DPRINTFN(5,("uhci_device_intr_done: requeing\n")); 3029 3030 /* This alloc cannot fail since we freed the chain above. */ 3031 uhci_alloc_std_chain(upipe, sc, xfer->length, 3032 upipe->u.intr.isread, xfer->flags, 3033 &xfer->dmabuf, &data, &dataend); 3034 dataend->td.td_status |= htole32(UHCI_TD_IOC); 3035 usb_syncmem(&dataend->dma, 3036 dataend->offs + offsetof(uhci_td_t, td_status), 3037 sizeof(dataend->td.td_status), 3038 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3039 3040 #ifdef UHCI_DEBUG 3041 if (uhcidebug > 10) { 3042 DPRINTF(("uhci_device_intr_done: data(1)\n")); 3043 uhci_dump_tds(data); 3044 uhci_dump_qh(upipe->u.intr.qhs[0]); 3045 } 3046 #endif 3047 3048 ii->stdstart = data; 3049 ii->stdend = dataend; 3050 #ifdef DIAGNOSTIC 3051 if (!ii->isdone) { 3052 printf("uhci_device_intr_done: not done, ii=%p\n", ii); 3053 } 3054 ii->isdone = 0; 3055 #endif 3056 for (i = 0; i < npoll; i++) { 3057 sqh = upipe->u.intr.qhs[i]; 3058 sqh->elink = data; 3059 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 3060 usb_syncmem(&sqh->dma, 3061 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3062 sizeof(sqh->qh.qh_elink), 3063 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3064 } 3065 xfer->status = USBD_IN_PROGRESS; 3066 /* The ii is already on the examined list, just leave it. */ 3067 } else { 3068 DPRINTFN(5,("uhci_device_intr_done: removing\n")); 3069 if (uhci_active_intr_info(ii)) 3070 uhci_del_intr_info(ii); 3071 } 3072 } 3073 3074 /* Deallocate request data structures */ 3075 void 3076 uhci_device_ctrl_done(usbd_xfer_handle xfer) 3077 { 3078 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3079 uhci_softc_t *sc = ii->sc; 3080 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 3081 int len = UGETW(xfer->request.wLength); 3082 int isread = (xfer->request.bmRequestType & UT_READ); 3083 3084 KASSERT(mutex_owned(&sc->sc_lock)); 3085 3086 #ifdef DIAGNOSTIC 3087 if (!(xfer->rqflags & URQ_REQUEST)) 3088 panic("uhci_device_ctrl_done: not a request"); 3089 #endif 3090 3091 if (!uhci_active_intr_info(ii)) 3092 return; 3093 3094 uhci_del_intr_info(ii); /* remove from active list */ 3095 3096 if (upipe->pipe.device->speed == USB_SPEED_LOW) 3097 uhci_remove_ls_ctrl(sc, upipe->u.ctl.sqh); 3098 else 3099 uhci_remove_hs_ctrl(sc, upipe->u.ctl.sqh); 3100 3101 if (upipe->u.ctl.length != 0) 3102 uhci_free_std_chain(sc, ii->stdstart->link.std, ii->stdend); 3103 3104 if (len) { 3105 usb_syncmem(&xfer->dmabuf, 0, len, 3106 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3107 } 3108 usb_syncmem(&upipe->u.ctl.reqdma, 0, 3109 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3110 3111 DPRINTFN(5, ("uhci_device_ctrl_done: length=%d\n", xfer->actlen)); 3112 } 3113 3114 /* Deallocate request data structures */ 3115 void 3116 uhci_device_bulk_done(usbd_xfer_handle xfer) 3117 { 3118 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3119 uhci_softc_t *sc = ii->sc; 3120 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 3121 3122 DPRINTFN(5,("uhci_device_bulk_done: xfer=%p ii=%p sc=%p upipe=%p\n", 3123 xfer, ii, sc, upipe)); 3124 3125 KASSERT(mutex_owned(&sc->sc_lock)); 3126 3127 if (!uhci_active_intr_info(ii)) 3128 return; 3129 3130 uhci_del_intr_info(ii); /* remove from active list */ 3131 3132 uhci_remove_bulk(sc, upipe->u.bulk.sqh); 3133 3134 uhci_free_std_chain(sc, ii->stdstart, NULL); 3135 3136 DPRINTFN(5, ("uhci_device_bulk_done: length=%d\n", xfer->actlen)); 3137 } 3138 3139 /* Add interrupt QH, called with vflock. */ 3140 void 3141 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3142 { 3143 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3144 uhci_soft_qh_t *eqh; 3145 3146 DPRINTFN(4, ("uhci_add_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3147 3148 eqh = vf->eqh; 3149 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3150 sizeof(eqh->qh.qh_hlink), 3151 BUS_DMASYNC_POSTWRITE); 3152 sqh->hlink = eqh->hlink; 3153 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3154 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3155 sizeof(sqh->qh.qh_hlink), 3156 BUS_DMASYNC_PREWRITE); 3157 eqh->hlink = sqh; 3158 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3159 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3160 sizeof(eqh->qh.qh_hlink), 3161 BUS_DMASYNC_PREWRITE); 3162 vf->eqh = sqh; 3163 vf->bandwidth++; 3164 } 3165 3166 /* Remove interrupt QH. */ 3167 void 3168 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3169 { 3170 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3171 uhci_soft_qh_t *pqh; 3172 3173 DPRINTFN(4, ("uhci_remove_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3174 3175 /* See comment in uhci_remove_ctrl() */ 3176 3177 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3178 sizeof(sqh->qh.qh_elink), 3179 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3180 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3181 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3182 usb_syncmem(&sqh->dma, 3183 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3184 sizeof(sqh->qh.qh_elink), 3185 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3186 delay(UHCI_QH_REMOVE_DELAY); 3187 } 3188 3189 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3190 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3191 sizeof(sqh->qh.qh_hlink), 3192 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3193 pqh->hlink = sqh->hlink; 3194 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3195 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3196 sizeof(pqh->qh.qh_hlink), 3197 BUS_DMASYNC_PREWRITE); 3198 delay(UHCI_QH_REMOVE_DELAY); 3199 if (vf->eqh == sqh) 3200 vf->eqh = pqh; 3201 vf->bandwidth--; 3202 } 3203 3204 usbd_status 3205 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3206 { 3207 uhci_soft_qh_t *sqh; 3208 int i, npoll; 3209 u_int bestbw, bw, bestoffs, offs; 3210 3211 DPRINTFN(2, ("uhci_device_setintr: pipe=%p\n", upipe)); 3212 if (ival == 0) { 3213 printf("uhci_device_setintr: 0 interval\n"); 3214 return (USBD_INVAL); 3215 } 3216 3217 if (ival > UHCI_VFRAMELIST_COUNT) 3218 ival = UHCI_VFRAMELIST_COUNT; 3219 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3220 DPRINTFN(2, ("uhci_device_setintr: ival=%d npoll=%d\n", ival, npoll)); 3221 3222 upipe->u.intr.npoll = npoll; 3223 upipe->u.intr.qhs = 3224 kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP); 3225 if (upipe->u.intr.qhs == NULL) 3226 return USBD_NOMEM; 3227 3228 /* 3229 * Figure out which offset in the schedule that has most 3230 * bandwidth left over. 3231 */ 3232 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3233 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3234 for (bw = i = 0; i < npoll; i++) 3235 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3236 if (bw < bestbw) { 3237 bestbw = bw; 3238 bestoffs = offs; 3239 } 3240 } 3241 DPRINTFN(1, ("uhci_device_setintr: bw=%d offs=%d\n", bestbw, bestoffs)); 3242 3243 mutex_enter(&sc->sc_lock); 3244 for(i = 0; i < npoll; i++) { 3245 upipe->u.intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3246 sqh->elink = NULL; 3247 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3248 usb_syncmem(&sqh->dma, 3249 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3250 sizeof(sqh->qh.qh_elink), 3251 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3252 sqh->pos = MOD(i * ival + bestoffs); 3253 } 3254 #undef MOD 3255 3256 /* Enter QHs into the controller data structures. */ 3257 for(i = 0; i < npoll; i++) 3258 uhci_add_intr(sc, upipe->u.intr.qhs[i]); 3259 mutex_exit(&sc->sc_lock); 3260 3261 DPRINTFN(5, ("uhci_device_setintr: returns %p\n", upipe)); 3262 return (USBD_NORMAL_COMPLETION); 3263 } 3264 3265 /* Open a new pipe. */ 3266 usbd_status 3267 uhci_open(usbd_pipe_handle pipe) 3268 { 3269 uhci_softc_t *sc = pipe->device->bus->hci_private; 3270 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 3271 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 3272 usbd_status err = USBD_NOMEM; 3273 int ival; 3274 3275 DPRINTFN(1, ("uhci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 3276 pipe, pipe->device->address, 3277 ed->bEndpointAddress, sc->sc_addr)); 3278 3279 if (sc->sc_dying) 3280 return USBD_IOERROR; 3281 3282 upipe->aborting = 0; 3283 /* toggle state needed for bulk endpoints */ 3284 upipe->nexttoggle = pipe->endpoint->datatoggle; 3285 3286 if (pipe->device->address == sc->sc_addr) { 3287 switch (ed->bEndpointAddress) { 3288 case USB_CONTROL_ENDPOINT: 3289 pipe->methods = &uhci_root_ctrl_methods; 3290 break; 3291 case UE_DIR_IN | UHCI_INTR_ENDPT: 3292 pipe->methods = &uhci_root_intr_methods; 3293 break; 3294 default: 3295 return (USBD_INVAL); 3296 } 3297 } else { 3298 switch (ed->bmAttributes & UE_XFERTYPE) { 3299 case UE_CONTROL: 3300 pipe->methods = &uhci_device_ctrl_methods; 3301 upipe->u.ctl.sqh = uhci_alloc_sqh(sc); 3302 if (upipe->u.ctl.sqh == NULL) 3303 goto bad; 3304 upipe->u.ctl.setup = uhci_alloc_std(sc); 3305 if (upipe->u.ctl.setup == NULL) { 3306 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3307 goto bad; 3308 } 3309 upipe->u.ctl.stat = uhci_alloc_std(sc); 3310 if (upipe->u.ctl.stat == NULL) { 3311 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3312 uhci_free_std(sc, upipe->u.ctl.setup); 3313 goto bad; 3314 } 3315 err = usb_allocmem(&sc->sc_bus, 3316 sizeof(usb_device_request_t), 3317 0, &upipe->u.ctl.reqdma); 3318 if (err) { 3319 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3320 uhci_free_std(sc, upipe->u.ctl.setup); 3321 uhci_free_std(sc, upipe->u.ctl.stat); 3322 goto bad; 3323 } 3324 break; 3325 case UE_INTERRUPT: 3326 pipe->methods = &uhci_device_intr_methods; 3327 ival = pipe->interval; 3328 if (ival == USBD_DEFAULT_INTERVAL) 3329 ival = ed->bInterval; 3330 return (uhci_device_setintr(sc, upipe, ival)); 3331 case UE_ISOCHRONOUS: 3332 pipe->methods = &uhci_device_isoc_methods; 3333 return (uhci_setup_isoc(pipe)); 3334 case UE_BULK: 3335 pipe->methods = &uhci_device_bulk_methods; 3336 upipe->u.bulk.sqh = uhci_alloc_sqh(sc); 3337 if (upipe->u.bulk.sqh == NULL) 3338 goto bad; 3339 break; 3340 } 3341 } 3342 return (USBD_NORMAL_COMPLETION); 3343 3344 bad: 3345 return USBD_NOMEM; 3346 } 3347 3348 /* 3349 * Data structures and routines to emulate the root hub. 3350 */ 3351 usb_device_descriptor_t uhci_devd = { 3352 USB_DEVICE_DESCRIPTOR_SIZE, 3353 UDESC_DEVICE, /* type */ 3354 {0x00, 0x01}, /* USB version */ 3355 UDCLASS_HUB, /* class */ 3356 UDSUBCLASS_HUB, /* subclass */ 3357 UDPROTO_FSHUB, /* protocol */ 3358 64, /* max packet */ 3359 {0},{0},{0x00,0x01}, /* device id */ 3360 1,2,0, /* string indicies */ 3361 1 /* # of configurations */ 3362 }; 3363 3364 const usb_config_descriptor_t uhci_confd = { 3365 USB_CONFIG_DESCRIPTOR_SIZE, 3366 UDESC_CONFIG, 3367 {USB_CONFIG_DESCRIPTOR_SIZE + 3368 USB_INTERFACE_DESCRIPTOR_SIZE + 3369 USB_ENDPOINT_DESCRIPTOR_SIZE}, 3370 1, 3371 1, 3372 0, 3373 UC_ATTR_MBO | UC_SELF_POWERED, 3374 0 /* max power */ 3375 }; 3376 3377 const usb_interface_descriptor_t uhci_ifcd = { 3378 USB_INTERFACE_DESCRIPTOR_SIZE, 3379 UDESC_INTERFACE, 3380 0, 3381 0, 3382 1, 3383 UICLASS_HUB, 3384 UISUBCLASS_HUB, 3385 UIPROTO_FSHUB, 3386 0 3387 }; 3388 3389 const usb_endpoint_descriptor_t uhci_endpd = { 3390 USB_ENDPOINT_DESCRIPTOR_SIZE, 3391 UDESC_ENDPOINT, 3392 UE_DIR_IN | UHCI_INTR_ENDPT, 3393 UE_INTERRUPT, 3394 {8}, 3395 255 3396 }; 3397 3398 const usb_hub_descriptor_t uhci_hubd_piix = { 3399 USB_HUB_DESCRIPTOR_SIZE, 3400 UDESC_HUB, 3401 2, 3402 { UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0 }, 3403 50, /* power on to power good */ 3404 0, 3405 { 0x00 }, /* both ports are removable */ 3406 { 0 }, 3407 }; 3408 3409 /* 3410 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3411 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3412 * should not be used by the USB subsystem. As we cannot issue a 3413 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3414 * will be enabled as part of the reset. 3415 * 3416 * On the VT83C572, the port cannot be successfully enabled until the 3417 * outstanding "port enable change" and "connection status change" 3418 * events have been reset. 3419 */ 3420 Static usbd_status 3421 uhci_portreset(uhci_softc_t *sc, int index) 3422 { 3423 int lim, port, x; 3424 3425 if (index == 1) 3426 port = UHCI_PORTSC1; 3427 else if (index == 2) 3428 port = UHCI_PORTSC2; 3429 else 3430 return (USBD_IOERROR); 3431 3432 x = URWMASK(UREAD2(sc, port)); 3433 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3434 3435 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3436 3437 DPRINTFN(3,("uhci port %d reset, status0 = 0x%04x\n", 3438 index, UREAD2(sc, port))); 3439 3440 x = URWMASK(UREAD2(sc, port)); 3441 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3442 3443 delay(100); 3444 3445 DPRINTFN(3,("uhci port %d reset, status1 = 0x%04x\n", 3446 index, UREAD2(sc, port))); 3447 3448 x = URWMASK(UREAD2(sc, port)); 3449 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3450 3451 for (lim = 10; --lim > 0;) { 3452 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3453 3454 x = UREAD2(sc, port); 3455 3456 DPRINTFN(3,("uhci port %d iteration %u, status = 0x%04x\n", 3457 index, lim, x)); 3458 3459 if (!(x & UHCI_PORTSC_CCS)) { 3460 /* 3461 * No device is connected (or was disconnected 3462 * during reset). Consider the port reset. 3463 * The delay must be long enough to ensure on 3464 * the initial iteration that the device 3465 * connection will have been registered. 50ms 3466 * appears to be sufficient, but 20ms is not. 3467 */ 3468 DPRINTFN(3,("uhci port %d loop %u, device detached\n", 3469 index, lim)); 3470 break; 3471 } 3472 3473 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3474 /* 3475 * Port enabled changed and/or connection 3476 * status changed were set. Reset either or 3477 * both raised flags (by writing a 1 to that 3478 * bit), and wait again for state to settle. 3479 */ 3480 UWRITE2(sc, port, URWMASK(x) | 3481 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3482 continue; 3483 } 3484 3485 if (x & UHCI_PORTSC_PE) 3486 /* Port is enabled */ 3487 break; 3488 3489 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3490 } 3491 3492 DPRINTFN(3,("uhci port %d reset, status2 = 0x%04x\n", 3493 index, UREAD2(sc, port))); 3494 3495 if (lim <= 0) { 3496 DPRINTFN(1,("uhci port %d reset timed out\n", index)); 3497 return (USBD_TIMEOUT); 3498 } 3499 3500 sc->sc_isreset = 1; 3501 return (USBD_NORMAL_COMPLETION); 3502 } 3503 3504 /* 3505 * Simulate a hardware hub by handling all the necessary requests. 3506 */ 3507 usbd_status 3508 uhci_root_ctrl_transfer(usbd_xfer_handle xfer) 3509 { 3510 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3511 usbd_status err; 3512 3513 /* Insert last in queue. */ 3514 mutex_enter(&sc->sc_lock); 3515 err = usb_insert_transfer(xfer); 3516 mutex_exit(&sc->sc_lock); 3517 if (err) 3518 return (err); 3519 3520 /* 3521 * Pipe isn't running (otherwise err would be USBD_INPROG), 3522 * so start it first. 3523 */ 3524 return (uhci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3525 } 3526 3527 usbd_status 3528 uhci_root_ctrl_start(usbd_xfer_handle xfer) 3529 { 3530 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3531 usb_device_request_t *req; 3532 void *buf = NULL; 3533 int port, x; 3534 int len, value, index, status, change, l, totlen = 0; 3535 usb_port_status_t ps; 3536 usbd_status err; 3537 3538 if (sc->sc_dying) 3539 return (USBD_IOERROR); 3540 3541 #ifdef DIAGNOSTIC 3542 if (!(xfer->rqflags & URQ_REQUEST)) 3543 panic("uhci_root_ctrl_start: not a request"); 3544 #endif 3545 req = &xfer->request; 3546 3547 DPRINTFN(2,("uhci_root_ctrl_control type=0x%02x request=%02x\n", 3548 req->bmRequestType, req->bRequest)); 3549 3550 len = UGETW(req->wLength); 3551 value = UGETW(req->wValue); 3552 index = UGETW(req->wIndex); 3553 3554 if (len != 0) 3555 buf = KERNADDR(&xfer->dmabuf, 0); 3556 3557 #define C(x,y) ((x) | ((y) << 8)) 3558 switch(C(req->bRequest, req->bmRequestType)) { 3559 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3560 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3561 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3562 /* 3563 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3564 * for the integrated root hub. 3565 */ 3566 break; 3567 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3568 if (len > 0) { 3569 *(u_int8_t *)buf = sc->sc_conf; 3570 totlen = 1; 3571 } 3572 break; 3573 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3574 DPRINTFN(2,("uhci_root_ctrl_control wValue=0x%04x\n", value)); 3575 if (len == 0) 3576 break; 3577 switch(value >> 8) { 3578 case UDESC_DEVICE: 3579 if ((value & 0xff) != 0) { 3580 err = USBD_IOERROR; 3581 goto ret; 3582 } 3583 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 3584 USETW(uhci_devd.idVendor, sc->sc_id_vendor); 3585 memcpy(buf, &uhci_devd, l); 3586 break; 3587 case UDESC_CONFIG: 3588 if ((value & 0xff) != 0) { 3589 err = USBD_IOERROR; 3590 goto ret; 3591 } 3592 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 3593 memcpy(buf, &uhci_confd, l); 3594 buf = (char *)buf + l; 3595 len -= l; 3596 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 3597 totlen += l; 3598 memcpy(buf, &uhci_ifcd, l); 3599 buf = (char *)buf + l; 3600 len -= l; 3601 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 3602 totlen += l; 3603 memcpy(buf, &uhci_endpd, l); 3604 break; 3605 case UDESC_STRING: 3606 #define sd ((usb_string_descriptor_t *)buf) 3607 switch (value & 0xff) { 3608 case 0: /* Language table */ 3609 totlen = usb_makelangtbl(sd, len); 3610 break; 3611 case 1: /* Vendor */ 3612 totlen = usb_makestrdesc(sd, len, 3613 sc->sc_vendor); 3614 break; 3615 case 2: /* Product */ 3616 totlen = usb_makestrdesc(sd, len, 3617 "UHCI root hub"); 3618 break; 3619 } 3620 #undef sd 3621 break; 3622 default: 3623 err = USBD_IOERROR; 3624 goto ret; 3625 } 3626 break; 3627 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3628 if (len > 0) { 3629 *(u_int8_t *)buf = 0; 3630 totlen = 1; 3631 } 3632 break; 3633 case C(UR_GET_STATUS, UT_READ_DEVICE): 3634 if (len > 1) { 3635 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 3636 totlen = 2; 3637 } 3638 break; 3639 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3640 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3641 if (len > 1) { 3642 USETW(((usb_status_t *)buf)->wStatus, 0); 3643 totlen = 2; 3644 } 3645 break; 3646 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3647 if (value >= USB_MAX_DEVICES) { 3648 err = USBD_IOERROR; 3649 goto ret; 3650 } 3651 sc->sc_addr = value; 3652 break; 3653 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3654 if (value != 0 && value != 1) { 3655 err = USBD_IOERROR; 3656 goto ret; 3657 } 3658 sc->sc_conf = value; 3659 break; 3660 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3661 break; 3662 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3663 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3664 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3665 err = USBD_IOERROR; 3666 goto ret; 3667 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3668 break; 3669 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3670 break; 3671 /* Hub requests */ 3672 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3673 break; 3674 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3675 DPRINTFN(3, ("uhci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 3676 "port=%d feature=%d\n", 3677 index, value)); 3678 if (index == 1) 3679 port = UHCI_PORTSC1; 3680 else if (index == 2) 3681 port = UHCI_PORTSC2; 3682 else { 3683 err = USBD_IOERROR; 3684 goto ret; 3685 } 3686 switch(value) { 3687 case UHF_PORT_ENABLE: 3688 x = URWMASK(UREAD2(sc, port)); 3689 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3690 break; 3691 case UHF_PORT_SUSPEND: 3692 x = URWMASK(UREAD2(sc, port)); 3693 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3694 break; 3695 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3696 /* see USB2 spec ch. 7.1.7.7 */ 3697 usb_delay_ms(&sc->sc_bus, 20); 3698 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3699 /* 10ms resume delay must be provided by caller */ 3700 break; 3701 case UHF_PORT_RESET: 3702 x = URWMASK(UREAD2(sc, port)); 3703 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3704 break; 3705 case UHF_C_PORT_CONNECTION: 3706 x = URWMASK(UREAD2(sc, port)); 3707 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3708 break; 3709 case UHF_C_PORT_ENABLE: 3710 x = URWMASK(UREAD2(sc, port)); 3711 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3712 break; 3713 case UHF_C_PORT_OVER_CURRENT: 3714 x = URWMASK(UREAD2(sc, port)); 3715 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3716 break; 3717 case UHF_C_PORT_RESET: 3718 sc->sc_isreset = 0; 3719 err = USBD_NORMAL_COMPLETION; 3720 goto ret; 3721 case UHF_PORT_CONNECTION: 3722 case UHF_PORT_OVER_CURRENT: 3723 case UHF_PORT_POWER: 3724 case UHF_PORT_LOW_SPEED: 3725 case UHF_C_PORT_SUSPEND: 3726 default: 3727 err = USBD_IOERROR; 3728 goto ret; 3729 } 3730 break; 3731 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3732 if (index == 1) 3733 port = UHCI_PORTSC1; 3734 else if (index == 2) 3735 port = UHCI_PORTSC2; 3736 else { 3737 err = USBD_IOERROR; 3738 goto ret; 3739 } 3740 if (len > 0) { 3741 *(u_int8_t *)buf = 3742 (UREAD2(sc, port) & UHCI_PORTSC_LS) >> 3743 UHCI_PORTSC_LS_SHIFT; 3744 totlen = 1; 3745 } 3746 break; 3747 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3748 if (len == 0) 3749 break; 3750 if ((value & 0xff) != 0) { 3751 err = USBD_IOERROR; 3752 goto ret; 3753 } 3754 l = min(len, USB_HUB_DESCRIPTOR_SIZE); 3755 totlen = l; 3756 memcpy(buf, &uhci_hubd_piix, l); 3757 break; 3758 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3759 if (len != 4) { 3760 err = USBD_IOERROR; 3761 goto ret; 3762 } 3763 memset(buf, 0, len); 3764 totlen = len; 3765 break; 3766 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3767 if (index == 1) 3768 port = UHCI_PORTSC1; 3769 else if (index == 2) 3770 port = UHCI_PORTSC2; 3771 else { 3772 err = USBD_IOERROR; 3773 goto ret; 3774 } 3775 if (len != 4) { 3776 err = USBD_IOERROR; 3777 goto ret; 3778 } 3779 x = UREAD2(sc, port); 3780 status = change = 0; 3781 if (x & UHCI_PORTSC_CCS) 3782 status |= UPS_CURRENT_CONNECT_STATUS; 3783 if (x & UHCI_PORTSC_CSC) 3784 change |= UPS_C_CONNECT_STATUS; 3785 if (x & UHCI_PORTSC_PE) 3786 status |= UPS_PORT_ENABLED; 3787 if (x & UHCI_PORTSC_POEDC) 3788 change |= UPS_C_PORT_ENABLED; 3789 if (x & UHCI_PORTSC_OCI) 3790 status |= UPS_OVERCURRENT_INDICATOR; 3791 if (x & UHCI_PORTSC_OCIC) 3792 change |= UPS_C_OVERCURRENT_INDICATOR; 3793 if (x & UHCI_PORTSC_SUSP) 3794 status |= UPS_SUSPEND; 3795 if (x & UHCI_PORTSC_LSDA) 3796 status |= UPS_LOW_SPEED; 3797 status |= UPS_PORT_POWER; 3798 if (sc->sc_isreset) 3799 change |= UPS_C_PORT_RESET; 3800 USETW(ps.wPortStatus, status); 3801 USETW(ps.wPortChange, change); 3802 l = min(len, sizeof ps); 3803 memcpy(buf, &ps, l); 3804 totlen = l; 3805 break; 3806 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3807 err = USBD_IOERROR; 3808 goto ret; 3809 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3810 break; 3811 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3812 if (index == 1) 3813 port = UHCI_PORTSC1; 3814 else if (index == 2) 3815 port = UHCI_PORTSC2; 3816 else { 3817 err = USBD_IOERROR; 3818 goto ret; 3819 } 3820 switch(value) { 3821 case UHF_PORT_ENABLE: 3822 x = URWMASK(UREAD2(sc, port)); 3823 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3824 break; 3825 case UHF_PORT_SUSPEND: 3826 x = URWMASK(UREAD2(sc, port)); 3827 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 3828 break; 3829 case UHF_PORT_RESET: 3830 err = uhci_portreset(sc, index); 3831 goto ret; 3832 case UHF_PORT_POWER: 3833 /* Pretend we turned on power */ 3834 err = USBD_NORMAL_COMPLETION; 3835 goto ret; 3836 case UHF_C_PORT_CONNECTION: 3837 case UHF_C_PORT_ENABLE: 3838 case UHF_C_PORT_OVER_CURRENT: 3839 case UHF_PORT_CONNECTION: 3840 case UHF_PORT_OVER_CURRENT: 3841 case UHF_PORT_LOW_SPEED: 3842 case UHF_C_PORT_SUSPEND: 3843 case UHF_C_PORT_RESET: 3844 default: 3845 err = USBD_IOERROR; 3846 goto ret; 3847 } 3848 break; 3849 default: 3850 err = USBD_IOERROR; 3851 goto ret; 3852 } 3853 xfer->actlen = totlen; 3854 err = USBD_NORMAL_COMPLETION; 3855 ret: 3856 xfer->status = err; 3857 mutex_enter(&sc->sc_lock); 3858 usb_transfer_complete(xfer); 3859 mutex_exit(&sc->sc_lock); 3860 return (USBD_IN_PROGRESS); 3861 } 3862 3863 /* Abort a root control request. */ 3864 void 3865 uhci_root_ctrl_abort(usbd_xfer_handle xfer) 3866 { 3867 /* Nothing to do, all transfers are synchronous. */ 3868 } 3869 3870 /* Close the root pipe. */ 3871 void 3872 uhci_root_ctrl_close(usbd_pipe_handle pipe) 3873 { 3874 DPRINTF(("uhci_root_ctrl_close\n")); 3875 } 3876 3877 /* Abort a root interrupt request. */ 3878 void 3879 uhci_root_intr_abort(usbd_xfer_handle xfer) 3880 { 3881 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3882 3883 KASSERT(mutex_owned(&sc->sc_lock)); 3884 3885 callout_stop(&sc->sc_poll_handle); 3886 sc->sc_intr_xfer = NULL; 3887 3888 if (xfer->pipe->intrxfer == xfer) { 3889 DPRINTF(("uhci_root_intr_abort: remove\n")); 3890 xfer->pipe->intrxfer = 0; 3891 } 3892 xfer->status = USBD_CANCELLED; 3893 #ifdef DIAGNOSTIC 3894 UXFER(xfer)->iinfo.isdone = 1; 3895 #endif 3896 usb_transfer_complete(xfer); 3897 } 3898 3899 usbd_status 3900 uhci_root_intr_transfer(usbd_xfer_handle xfer) 3901 { 3902 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3903 usbd_status err; 3904 3905 /* Insert last in queue. */ 3906 mutex_enter(&sc->sc_lock); 3907 err = usb_insert_transfer(xfer); 3908 mutex_exit(&sc->sc_lock); 3909 if (err) 3910 return (err); 3911 3912 /* 3913 * Pipe isn't running (otherwise err would be USBD_INPROG), 3914 * start first 3915 */ 3916 return (uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3917 } 3918 3919 /* Start a transfer on the root interrupt pipe */ 3920 usbd_status 3921 uhci_root_intr_start(usbd_xfer_handle xfer) 3922 { 3923 usbd_pipe_handle pipe = xfer->pipe; 3924 uhci_softc_t *sc = pipe->device->bus->hci_private; 3925 unsigned int ival; 3926 3927 DPRINTFN(3, ("uhci_root_intr_start: xfer=%p len=%d flags=%d\n", 3928 xfer, xfer->length, xfer->flags)); 3929 3930 if (sc->sc_dying) 3931 return (USBD_IOERROR); 3932 3933 /* XXX temporary variable needed to avoid gcc3 warning */ 3934 ival = xfer->pipe->endpoint->edesc->bInterval; 3935 sc->sc_ival = mstohz(ival); 3936 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 3937 sc->sc_intr_xfer = xfer; 3938 return (USBD_IN_PROGRESS); 3939 } 3940 3941 /* Close the root interrupt pipe. */ 3942 void 3943 uhci_root_intr_close(usbd_pipe_handle pipe) 3944 { 3945 uhci_softc_t *sc = pipe->device->bus->hci_private; 3946 3947 KASSERT(mutex_owned(&sc->sc_lock)); 3948 3949 callout_stop(&sc->sc_poll_handle); 3950 sc->sc_intr_xfer = NULL; 3951 DPRINTF(("uhci_root_intr_close\n")); 3952 } 3953
Indexes created Tue Sep 30 17:09:57 GMT 2025