uhci.c revision 1.240.6.16
1 /* $NetBSD: uhci.c,v 1.240.6.16 2012/03/03 02:29:34 mrg Exp $ */ 2 /* $FreeBSD: src/sys/dev/usb/uhci.c,v 1.33 1999/11/17 22:33:41 n_hibma Exp $ */ 3 4 /* 5 * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Lennart Augustsson (lennart (at) augustsson.net) at 10 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 11 * and Matthew R. Green (mrg (at) eterna.com.au). 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * USB Universal Host Controller driver. 37 * Handles e.g. PIIX3 and PIIX4. 38 * 39 * UHCI spec: http://www.intel.com/technology/usb/spec.htm 40 * USB spec: http://www.usb.org/developers/docs/ 41 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 42 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.240.6.16 2012/03/03 02:29:34 mrg Exp $"); 47 48 #include "opt_usb.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/kmem.h> 54 #include <sys/device.h> 55 #include <sys/select.h> 56 #include <sys/extent.h> 57 #include <sys/proc.h> 58 #include <sys/queue.h> 59 #include <sys/bus.h> 60 #include <sys/cpu.h> 61 62 #include <machine/endian.h> 63 64 #include <dev/usb/usb.h> 65 #include <dev/usb/usbdi.h> 66 #include <dev/usb/usbdivar.h> 67 #include <dev/usb/usb_mem.h> 68 #include <dev/usb/usb_quirks.h> 69 70 #include <dev/usb/uhcireg.h> 71 #include <dev/usb/uhcivar.h> 72 #include <dev/usb/usbroothub_subr.h> 73 74 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 75 /*#define UHCI_CTL_LOOP */ 76 77 78 79 #ifdef UHCI_DEBUG 80 uhci_softc_t *thesc; 81 #define DPRINTF(x) if (uhcidebug) printf x 82 #define DPRINTFN(n,x) if (uhcidebug>(n)) printf x 83 int uhcidebug = 0; 84 int uhcinoloop = 0; 85 #else 86 #define DPRINTF(x) 87 #define DPRINTFN(n,x) 88 #endif 89 90 /* 91 * The UHCI controller is little endian, so on big endian machines 92 * the data stored in memory needs to be swapped. 93 */ 94 95 struct uhci_pipe { 96 struct usbd_pipe pipe; 97 int nexttoggle; 98 99 u_char aborting; 100 usbd_xfer_handle abortstart, abortend; 101 102 /* Info needed for different pipe kinds. */ 103 union { 104 /* Control pipe */ 105 struct { 106 uhci_soft_qh_t *sqh; 107 usb_dma_t reqdma; 108 uhci_soft_td_t *setup, *stat; 109 u_int length; 110 } ctl; 111 /* Interrupt pipe */ 112 struct { 113 int npoll; 114 int isread; 115 uhci_soft_qh_t **qhs; 116 } intr; 117 /* Bulk pipe */ 118 struct { 119 uhci_soft_qh_t *sqh; 120 u_int length; 121 int isread; 122 } bulk; 123 /* Iso pipe */ 124 struct iso { 125 uhci_soft_td_t **stds; 126 int next, inuse; 127 } iso; 128 } u; 129 }; 130 131 Static void uhci_globalreset(uhci_softc_t *); 132 Static usbd_status uhci_portreset(uhci_softc_t*, int); 133 Static void uhci_reset(uhci_softc_t *); 134 Static usbd_status uhci_run(uhci_softc_t *, int run); 135 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 136 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 137 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 138 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 139 #if 0 140 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 141 uhci_intr_info_t *); 142 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 143 #endif 144 145 Static void uhci_free_std_chain(uhci_softc_t *, 146 uhci_soft_td_t *, uhci_soft_td_t *); 147 Static usbd_status uhci_alloc_std_chain(struct uhci_pipe *, 148 uhci_softc_t *, int, int, u_int16_t, usb_dma_t *, 149 uhci_soft_td_t **, uhci_soft_td_t **); 150 Static void uhci_poll_hub(void *); 151 Static void uhci_waitintr(uhci_softc_t *, usbd_xfer_handle); 152 Static void uhci_check_intr(uhci_softc_t *, uhci_intr_info_t *); 153 Static void uhci_idone(uhci_intr_info_t *); 154 155 Static void uhci_abort_xfer(usbd_xfer_handle, usbd_status status); 156 157 Static void uhci_timeout(void *); 158 Static void uhci_timeout_task(void *); 159 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 160 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 161 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 162 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 163 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 164 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 165 Static void uhci_add_loop(uhci_softc_t *sc); 166 Static void uhci_rem_loop(uhci_softc_t *sc); 167 168 Static usbd_status uhci_setup_isoc(usbd_pipe_handle pipe); 169 Static void uhci_device_isoc_enter(usbd_xfer_handle); 170 171 Static usbd_status uhci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 172 Static void uhci_freem(struct usbd_bus *, usb_dma_t *); 173 174 Static usbd_xfer_handle uhci_allocx(struct usbd_bus *); 175 Static void uhci_freex(struct usbd_bus *, usbd_xfer_handle); 176 Static void uhci_get_lock(struct usbd_bus *, kmutex_t **); 177 178 Static usbd_status uhci_device_ctrl_transfer(usbd_xfer_handle); 179 Static usbd_status uhci_device_ctrl_start(usbd_xfer_handle); 180 Static void uhci_device_ctrl_abort(usbd_xfer_handle); 181 Static void uhci_device_ctrl_close(usbd_pipe_handle); 182 Static void uhci_device_ctrl_done(usbd_xfer_handle); 183 184 Static usbd_status uhci_device_intr_transfer(usbd_xfer_handle); 185 Static usbd_status uhci_device_intr_start(usbd_xfer_handle); 186 Static void uhci_device_intr_abort(usbd_xfer_handle); 187 Static void uhci_device_intr_close(usbd_pipe_handle); 188 Static void uhci_device_intr_done(usbd_xfer_handle); 189 190 Static usbd_status uhci_device_bulk_transfer(usbd_xfer_handle); 191 Static usbd_status uhci_device_bulk_start(usbd_xfer_handle); 192 Static void uhci_device_bulk_abort(usbd_xfer_handle); 193 Static void uhci_device_bulk_close(usbd_pipe_handle); 194 Static void uhci_device_bulk_done(usbd_xfer_handle); 195 196 Static usbd_status uhci_device_isoc_transfer(usbd_xfer_handle); 197 Static usbd_status uhci_device_isoc_start(usbd_xfer_handle); 198 Static void uhci_device_isoc_abort(usbd_xfer_handle); 199 Static void uhci_device_isoc_close(usbd_pipe_handle); 200 Static void uhci_device_isoc_done(usbd_xfer_handle); 201 202 Static usbd_status uhci_root_ctrl_transfer(usbd_xfer_handle); 203 Static usbd_status uhci_root_ctrl_start(usbd_xfer_handle); 204 Static void uhci_root_ctrl_abort(usbd_xfer_handle); 205 Static void uhci_root_ctrl_close(usbd_pipe_handle); 206 Static void uhci_root_ctrl_done(usbd_xfer_handle); 207 208 Static usbd_status uhci_root_intr_transfer(usbd_xfer_handle); 209 Static usbd_status uhci_root_intr_start(usbd_xfer_handle); 210 Static void uhci_root_intr_abort(usbd_xfer_handle); 211 Static void uhci_root_intr_close(usbd_pipe_handle); 212 Static void uhci_root_intr_done(usbd_xfer_handle); 213 214 Static usbd_status uhci_open(usbd_pipe_handle); 215 Static void uhci_poll(struct usbd_bus *); 216 Static void uhci_softintr(void *); 217 218 Static usbd_status uhci_device_request(usbd_xfer_handle xfer); 219 220 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 221 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 222 Static usbd_status uhci_device_setintr(uhci_softc_t *sc, 223 struct uhci_pipe *pipe, int ival); 224 225 Static void uhci_device_clear_toggle(usbd_pipe_handle pipe); 226 Static void uhci_noop(usbd_pipe_handle pipe); 227 228 static inline uhci_soft_qh_t *uhci_find_prev_qh(uhci_soft_qh_t *, 229 uhci_soft_qh_t *); 230 231 #ifdef UHCI_DEBUG 232 Static void uhci_dump_all(uhci_softc_t *); 233 Static void uhci_dumpregs(uhci_softc_t *); 234 Static void uhci_dump_qhs(uhci_soft_qh_t *); 235 Static void uhci_dump_qh(uhci_soft_qh_t *); 236 Static void uhci_dump_tds(uhci_soft_td_t *); 237 Static void uhci_dump_td(uhci_soft_td_t *); 238 Static void uhci_dump_ii(uhci_intr_info_t *ii); 239 void uhci_dump(void); 240 #endif 241 242 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 243 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 244 #define UWRITE1(sc, r, x) \ 245 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 246 } while (/*CONSTCOND*/0) 247 #define UWRITE2(sc, r, x) \ 248 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 249 } while (/*CONSTCOND*/0) 250 #define UWRITE4(sc, r, x) \ 251 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 252 } while (/*CONSTCOND*/0) 253 static __inline uint8_t 254 UREAD1(uhci_softc_t *sc, bus_size_t r) 255 { 256 257 UBARR(sc); 258 return bus_space_read_1(sc->iot, sc->ioh, r); 259 } 260 261 static __inline uint16_t 262 UREAD2(uhci_softc_t *sc, bus_size_t r) 263 { 264 265 UBARR(sc); 266 return bus_space_read_2(sc->iot, sc->ioh, r); 267 } 268 269 static __inline uint32_t 270 UREAD4(uhci_softc_t *sc, bus_size_t r) 271 { 272 273 UBARR(sc); 274 return bus_space_read_4(sc->iot, sc->ioh, r); 275 } 276 277 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 278 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 279 280 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 281 282 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 283 284 #define UHCI_INTR_ENDPT 1 285 286 const struct usbd_bus_methods uhci_bus_methods = { 287 .open_pipe = uhci_open, 288 .soft_intr = uhci_softintr, 289 .do_poll = uhci_poll, 290 .allocm = uhci_allocm, 291 .freem = uhci_freem, 292 .allocx = uhci_allocx, 293 .freex = uhci_freex, 294 .get_lock = uhci_get_lock, 295 }; 296 297 const struct usbd_pipe_methods uhci_root_ctrl_methods = { 298 .transfer = uhci_root_ctrl_transfer, 299 .start = uhci_root_ctrl_start, 300 .abort = uhci_root_ctrl_abort, 301 .close = uhci_root_ctrl_close, 302 .cleartoggle = uhci_noop, 303 .done = uhci_root_ctrl_done, 304 }; 305 306 const struct usbd_pipe_methods uhci_root_intr_methods = { 307 .transfer = uhci_root_intr_transfer, 308 .start = uhci_root_intr_start, 309 .abort = uhci_root_intr_abort, 310 .close = uhci_root_intr_close, 311 .cleartoggle = uhci_noop, 312 .done = uhci_root_intr_done, 313 }; 314 315 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 316 .transfer = uhci_device_ctrl_transfer, 317 .start = uhci_device_ctrl_start, 318 .abort = uhci_device_ctrl_abort, 319 .close = uhci_device_ctrl_close, 320 .cleartoggle = uhci_noop, 321 .done = uhci_device_ctrl_done, 322 }; 323 324 const struct usbd_pipe_methods uhci_device_intr_methods = { 325 .transfer = uhci_device_intr_transfer, 326 .start = uhci_device_intr_start, 327 .abort = uhci_device_intr_abort, 328 .close = uhci_device_intr_close, 329 .cleartoggle = uhci_device_clear_toggle, 330 .done = uhci_device_intr_done, 331 }; 332 333 const struct usbd_pipe_methods uhci_device_bulk_methods = { 334 .transfer = uhci_device_bulk_transfer, 335 .start = uhci_device_bulk_start, 336 .abort = uhci_device_bulk_abort, 337 .close = uhci_device_bulk_close, 338 .cleartoggle = uhci_device_clear_toggle, 339 .done = uhci_device_bulk_done, 340 }; 341 342 const struct usbd_pipe_methods uhci_device_isoc_methods = { 343 .transfer = uhci_device_isoc_transfer, 344 .start = uhci_device_isoc_start, 345 .abort = uhci_device_isoc_abort, 346 .close = uhci_device_isoc_close, 347 .cleartoggle = uhci_noop, 348 .done = uhci_device_isoc_done, 349 }; 350 351 #define uhci_add_intr_info(sc, ii) \ 352 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ii), list) 353 #define uhci_del_intr_info(ii) \ 354 do { \ 355 LIST_REMOVE((ii), list); \ 356 (ii)->list.le_prev = NULL; \ 357 } while (0) 358 #define uhci_active_intr_info(ii) ((ii)->list.le_prev != NULL) 359 360 static inline uhci_soft_qh_t * 361 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 362 { 363 DPRINTFN(15,("uhci_find_prev_qh: pqh=%p sqh=%p\n", pqh, sqh)); 364 365 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 366 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 367 usb_syncmem(&pqh->dma, 368 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 369 sizeof(pqh->qh.qh_hlink), 370 BUS_DMASYNC_POSTWRITE); 371 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 372 printf("uhci_find_prev_qh: QH not found\n"); 373 return (NULL); 374 } 375 #endif 376 } 377 return (pqh); 378 } 379 380 void 381 uhci_globalreset(uhci_softc_t *sc) 382 { 383 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 384 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 385 UHCICMD(sc, 0); /* do nothing */ 386 } 387 388 usbd_status 389 uhci_init(uhci_softc_t *sc) 390 { 391 usbd_status err; 392 int i, j; 393 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 394 uhci_soft_td_t *std; 395 396 DPRINTFN(1,("uhci_init: start\n")); 397 398 #ifdef UHCI_DEBUG 399 thesc = sc; 400 401 if (uhcidebug > 2) 402 uhci_dumpregs(sc); 403 #endif 404 405 sc->sc_suspend = PWR_RESUME; 406 407 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 408 uhci_globalreset(sc); /* reset the controller */ 409 uhci_reset(sc); 410 411 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 412 USB_MEM_RESERVE); 413 414 /* Allocate and initialize real frame array. */ 415 err = usb_allocmem(&sc->sc_bus, 416 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 417 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 418 if (err) 419 return (err); 420 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 421 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 422 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 423 424 /* 425 * Allocate a TD, inactive, that hangs from the last QH. 426 * This is to avoid a bug in the PIIX that makes it run berserk 427 * otherwise. 428 */ 429 std = uhci_alloc_std(sc); 430 if (std == NULL) 431 return (USBD_NOMEM); 432 std->link.std = NULL; 433 std->td.td_link = htole32(UHCI_PTR_T); 434 std->td.td_status = htole32(0); /* inactive */ 435 std->td.td_token = htole32(0); 436 std->td.td_buffer = htole32(0); 437 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 438 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 439 440 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 441 lsqh = uhci_alloc_sqh(sc); 442 if (lsqh == NULL) 443 return (USBD_NOMEM); 444 lsqh->hlink = NULL; 445 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 446 lsqh->elink = std; 447 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 448 sc->sc_last_qh = lsqh; 449 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 450 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 451 452 /* Allocate the dummy QH where bulk traffic will be queued. */ 453 bsqh = uhci_alloc_sqh(sc); 454 if (bsqh == NULL) 455 return (USBD_NOMEM); 456 bsqh->hlink = lsqh; 457 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 458 bsqh->elink = NULL; 459 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 460 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 461 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 462 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 463 464 /* Allocate dummy QH where high speed control traffic will be queued. */ 465 chsqh = uhci_alloc_sqh(sc); 466 if (chsqh == NULL) 467 return (USBD_NOMEM); 468 chsqh->hlink = bsqh; 469 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 470 chsqh->elink = NULL; 471 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 472 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 473 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 474 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 475 476 /* Allocate dummy QH where control traffic will be queued. */ 477 clsqh = uhci_alloc_sqh(sc); 478 if (clsqh == NULL) 479 return (USBD_NOMEM); 480 clsqh->hlink = chsqh; 481 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 482 clsqh->elink = NULL; 483 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 484 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 485 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 486 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 487 488 /* 489 * Make all (virtual) frame list pointers point to the interrupt 490 * queue heads and the interrupt queue heads at the control 491 * queue head and point the physical frame list to the virtual. 492 */ 493 for(i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 494 std = uhci_alloc_std(sc); 495 sqh = uhci_alloc_sqh(sc); 496 if (std == NULL || sqh == NULL) 497 return (USBD_NOMEM); 498 std->link.sqh = sqh; 499 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 500 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 501 std->td.td_token = htole32(0); 502 std->td.td_buffer = htole32(0); 503 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 504 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 505 sqh->hlink = clsqh; 506 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 507 sqh->elink = NULL; 508 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 509 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 510 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 511 sc->sc_vframes[i].htd = std; 512 sc->sc_vframes[i].etd = std; 513 sc->sc_vframes[i].hqh = sqh; 514 sc->sc_vframes[i].eqh = sqh; 515 for (j = i; 516 j < UHCI_FRAMELIST_COUNT; 517 j += UHCI_VFRAMELIST_COUNT) 518 sc->sc_pframes[j] = htole32(std->physaddr); 519 } 520 usb_syncmem(&sc->sc_dma, 0, 521 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 522 BUS_DMASYNC_PREWRITE); 523 524 525 LIST_INIT(&sc->sc_intrhead); 526 527 SIMPLEQ_INIT(&sc->sc_free_xfers); 528 529 callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE); 530 531 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 532 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 533 cv_init(&sc->sc_softwake_cv, "uhciab"); 534 535 /* Set up the bus struct. */ 536 sc->sc_bus.methods = &uhci_bus_methods; 537 sc->sc_bus.pipe_size = sizeof(struct uhci_pipe); 538 539 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 540 541 DPRINTFN(1,("uhci_init: enabling\n")); 542 543 err = uhci_run(sc, 1); /* and here we go... */ 544 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 545 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 546 return err; 547 } 548 549 int 550 uhci_activate(device_t self, enum devact act) 551 { 552 struct uhci_softc *sc = device_private(self); 553 554 switch (act) { 555 case DVACT_DEACTIVATE: 556 sc->sc_dying = 1; 557 return 0; 558 default: 559 return EOPNOTSUPP; 560 } 561 } 562 563 void 564 uhci_childdet(device_t self, device_t child) 565 { 566 struct uhci_softc *sc = device_private(self); 567 568 KASSERT(sc->sc_child == child); 569 sc->sc_child = NULL; 570 } 571 572 int 573 uhci_detach(struct uhci_softc *sc, int flags) 574 { 575 usbd_xfer_handle xfer; 576 int rv = 0; 577 578 if (sc->sc_child != NULL) 579 rv = config_detach(sc->sc_child, flags); 580 581 if (rv != 0) 582 return (rv); 583 584 /* Free all xfers associated with this HC. */ 585 for (;;) { 586 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 587 if (xfer == NULL) 588 break; 589 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 590 kmem_free(xfer, sizeof(struct uhci_xfer)); 591 } 592 593 callout_halt(&sc->sc_poll_handle, NULL); 594 callout_destroy(&sc->sc_poll_handle); 595 596 cv_destroy(&sc->sc_softwake_cv); 597 598 mutex_destroy(&sc->sc_lock); 599 mutex_destroy(&sc->sc_intr_lock); 600 601 /* XXX free other data structures XXX */ 602 603 return (rv); 604 } 605 606 usbd_status 607 uhci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 608 { 609 struct uhci_softc *sc = bus->hci_private; 610 usbd_status status; 611 u_int32_t n; 612 613 /* 614 * XXX 615 * Since we are allocating a buffer we can assume that we will 616 * need TDs for it. Since we don't want to allocate those from 617 * an interrupt context, we allocate them here and free them again. 618 * This is no guarantee that we'll get the TDs next time... 619 */ 620 n = size / 8; 621 if (n > 16) { 622 u_int32_t i; 623 uhci_soft_td_t **stds; 624 625 DPRINTF(("uhci_allocm: get %d TDs\n", n)); 626 stds = kmem_alloc(sizeof(uhci_soft_td_t *) * n, KM_SLEEP); 627 if (!stds) 628 return USBD_NOMEM; 629 for(i = 0; i < n; i++) 630 stds[i] = uhci_alloc_std(sc); 631 for(i = 0; i < n; i++) 632 if (stds[i] != NULL) 633 uhci_free_std(sc, stds[i]); 634 kmem_free(stds, sizeof(uhci_soft_td_t *) * n); 635 } 636 637 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 638 if (status == USBD_NOMEM) 639 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 640 return status; 641 } 642 643 void 644 uhci_freem(struct usbd_bus *bus, usb_dma_t *dma) 645 { 646 if (dma->block->flags & USB_DMA_RESERVE) { 647 usb_reserve_freem(&((struct uhci_softc *)bus)->sc_dma_reserve, 648 dma); 649 return; 650 } 651 usb_freemem(&((struct uhci_softc *)bus)->sc_bus, dma); 652 } 653 654 usbd_xfer_handle 655 uhci_allocx(struct usbd_bus *bus) 656 { 657 struct uhci_softc *sc = bus->hci_private; 658 usbd_xfer_handle xfer; 659 660 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 661 if (xfer != NULL) { 662 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 663 #ifdef DIAGNOSTIC 664 if (xfer->busy_free != XFER_FREE) { 665 printf("uhci_allocx: xfer=%p not free, 0x%08x\n", xfer, 666 xfer->busy_free); 667 } 668 #endif 669 } else { 670 xfer = kmem_alloc(sizeof(struct uhci_xfer), KM_SLEEP); 671 } 672 if (xfer != NULL) { 673 memset(xfer, 0, sizeof (struct uhci_xfer)); 674 UXFER(xfer)->iinfo.sc = sc; 675 #ifdef DIAGNOSTIC 676 UXFER(xfer)->iinfo.isdone = 1; 677 xfer->busy_free = XFER_BUSY; 678 #endif 679 } 680 return (xfer); 681 } 682 683 void 684 uhci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 685 { 686 struct uhci_softc *sc = bus->hci_private; 687 688 #ifdef DIAGNOSTIC 689 if (xfer->busy_free != XFER_BUSY) { 690 printf("uhci_freex: xfer=%p not busy, 0x%08x\n", xfer, 691 xfer->busy_free); 692 } 693 xfer->busy_free = XFER_FREE; 694 if (!UXFER(xfer)->iinfo.isdone) { 695 printf("uhci_freex: !isdone\n"); 696 } 697 #endif 698 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 699 } 700 701 Static void 702 uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 703 { 704 struct uhci_softc *sc = bus->hci_private; 705 706 *lock = &sc->sc_lock; 707 } 708 709 710 /* 711 * Handle suspend/resume. 712 * 713 * We need to switch to polling mode here, because this routine is 714 * called from an interrupt context. This is all right since we 715 * are almost suspended anyway. 716 */ 717 bool 718 uhci_resume(device_t dv, const pmf_qual_t *qual) 719 { 720 uhci_softc_t *sc = device_private(dv); 721 int cmd; 722 723 mutex_spin_enter(&sc->sc_intr_lock); 724 725 cmd = UREAD2(sc, UHCI_CMD); 726 sc->sc_bus.use_polling++; 727 UWRITE2(sc, UHCI_INTR, 0); 728 uhci_globalreset(sc); 729 uhci_reset(sc); 730 if (cmd & UHCI_CMD_RS) 731 uhci_run(sc, 0); 732 733 /* restore saved state */ 734 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 735 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 736 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 737 738 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 739 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock); 740 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 741 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 742 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 743 UHCICMD(sc, UHCI_CMD_MAXP); 744 uhci_run(sc, 1); /* and start traffic again */ 745 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock); 746 sc->sc_bus.use_polling--; 747 if (sc->sc_intr_xfer != NULL) 748 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, 749 sc->sc_intr_xfer); 750 #ifdef UHCI_DEBUG 751 if (uhcidebug > 2) 752 uhci_dumpregs(sc); 753 #endif 754 755 sc->sc_suspend = PWR_RESUME; 756 mutex_spin_exit(&sc->sc_intr_lock); 757 758 return true; 759 } 760 761 bool 762 uhci_suspend(device_t dv, const pmf_qual_t *qual) 763 { 764 uhci_softc_t *sc = device_private(dv); 765 int cmd; 766 767 mutex_spin_enter(&sc->sc_intr_lock); 768 769 cmd = UREAD2(sc, UHCI_CMD); 770 771 #ifdef UHCI_DEBUG 772 if (uhcidebug > 2) 773 uhci_dumpregs(sc); 774 #endif 775 if (sc->sc_intr_xfer != NULL) 776 callout_stop(&sc->sc_poll_handle); 777 sc->sc_suspend = PWR_SUSPEND; 778 sc->sc_bus.use_polling++; 779 780 uhci_run(sc, 0); /* stop the controller */ 781 cmd &= ~UHCI_CMD_RS; 782 783 /* save some state if BIOS doesn't */ 784 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 785 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 786 787 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 788 789 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 790 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock); 791 sc->sc_bus.use_polling--; 792 793 mutex_spin_exit(&sc->sc_intr_lock); 794 795 return true; 796 } 797 798 #ifdef UHCI_DEBUG 799 Static void 800 uhci_dumpregs(uhci_softc_t *sc) 801 { 802 DPRINTFN(-1,("%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, " 803 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 804 device_xname(sc->sc_dev), 805 UREAD2(sc, UHCI_CMD), 806 UREAD2(sc, UHCI_STS), 807 UREAD2(sc, UHCI_INTR), 808 UREAD2(sc, UHCI_FRNUM), 809 UREAD4(sc, UHCI_FLBASEADDR), 810 UREAD1(sc, UHCI_SOF), 811 UREAD2(sc, UHCI_PORTSC1), 812 UREAD2(sc, UHCI_PORTSC2))); 813 } 814 815 void 816 uhci_dump_td(uhci_soft_td_t *p) 817 { 818 char sbuf[128], sbuf2[128]; 819 820 821 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 822 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 823 DPRINTFN(-1,("TD(%p) at %08lx = link=0x%08lx status=0x%08lx " 824 "token=0x%08lx buffer=0x%08lx\n", 825 p, (long)p->physaddr, 826 (long)le32toh(p->td.td_link), 827 (long)le32toh(p->td.td_status), 828 (long)le32toh(p->td.td_token), 829 (long)le32toh(p->td.td_buffer))); 830 831 snprintb(sbuf, sizeof(sbuf), "\20\1T\2Q\3VF", 832 (u_int32_t)le32toh(p->td.td_link)); 833 snprintb(sbuf2, sizeof(sbuf2), 834 "\20\22BITSTUFF\23CRCTO\24NAK\25BABBLE\26DBUFFER\27" 835 "STALLED\30ACTIVE\31IOC\32ISO\33LS\36SPD", 836 (u_int32_t)le32toh(p->td.td_status)); 837 838 DPRINTFN(-1,(" %s %s,errcnt=%d,actlen=%d pid=%02x,addr=%d,endpt=%d," 839 "D=%d,maxlen=%d\n", sbuf, sbuf2, 840 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 841 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 842 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 843 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 844 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 845 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 846 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token)))); 847 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 848 BUS_DMASYNC_PREREAD); 849 } 850 851 void 852 uhci_dump_qh(uhci_soft_qh_t *sqh) 853 { 854 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 855 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 856 DPRINTFN(-1,("QH(%p) at %08x: hlink=%08x elink=%08x\n", sqh, 857 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 858 le32toh(sqh->qh.qh_elink))); 859 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 860 } 861 862 863 #if 1 864 void 865 uhci_dump(void) 866 { 867 uhci_dump_all(thesc); 868 } 869 #endif 870 871 void 872 uhci_dump_all(uhci_softc_t *sc) 873 { 874 uhci_dumpregs(sc); 875 printf("intrs=%d\n", sc->sc_bus.no_intrs); 876 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 877 uhci_dump_qh(sc->sc_lctl_start); 878 } 879 880 881 void 882 uhci_dump_qhs(uhci_soft_qh_t *sqh) 883 { 884 uhci_dump_qh(sqh); 885 886 /* uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 887 * Traverses sideways first, then down. 888 * 889 * QH1 890 * QH2 891 * No QH 892 * TD2.1 893 * TD2.2 894 * TD1.1 895 * etc. 896 * 897 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 898 */ 899 900 901 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 902 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 903 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 904 uhci_dump_qhs(sqh->hlink); 905 else 906 DPRINTF(("No QH\n")); 907 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 908 909 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 910 uhci_dump_tds(sqh->elink); 911 else 912 DPRINTF(("No TD\n")); 913 } 914 915 void 916 uhci_dump_tds(uhci_soft_td_t *std) 917 { 918 uhci_soft_td_t *td; 919 int stop; 920 921 for(td = std; td != NULL; td = td->link.std) { 922 uhci_dump_td(td); 923 924 /* Check whether the link pointer in this TD marks 925 * the link pointer as end of queue. This avoids 926 * printing the free list in case the queue/TD has 927 * already been moved there (seatbelt). 928 */ 929 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 930 sizeof(td->td.td_link), 931 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 932 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 933 le32toh(td->td.td_link) == 0); 934 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 935 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 936 if (stop) 937 break; 938 } 939 } 940 941 Static void 942 uhci_dump_ii(uhci_intr_info_t *ii) 943 { 944 usbd_pipe_handle pipe; 945 usb_endpoint_descriptor_t *ed; 946 usbd_device_handle dev; 947 948 #ifdef DIAGNOSTIC 949 #define DONE ii->isdone 950 #else 951 #define DONE 0 952 #endif 953 if (ii == NULL) { 954 printf("ii NULL\n"); 955 return; 956 } 957 if (ii->xfer == NULL) { 958 printf("ii %p: done=%d xfer=NULL\n", 959 ii, DONE); 960 return; 961 } 962 pipe = ii->xfer->pipe; 963 if (pipe == NULL) { 964 printf("ii %p: done=%d xfer=%p pipe=NULL\n", 965 ii, DONE, ii->xfer); 966 return; 967 } 968 if (pipe->endpoint == NULL) { 969 printf("ii %p: done=%d xfer=%p pipe=%p pipe->endpoint=NULL\n", 970 ii, DONE, ii->xfer, pipe); 971 return; 972 } 973 if (pipe->device == NULL) { 974 printf("ii %p: done=%d xfer=%p pipe=%p pipe->device=NULL\n", 975 ii, DONE, ii->xfer, pipe); 976 return; 977 } 978 ed = pipe->endpoint->edesc; 979 dev = pipe->device; 980 printf("ii %p: done=%d xfer=%p dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 981 ii, DONE, ii->xfer, dev, 982 UGETW(dev->ddesc.idVendor), 983 UGETW(dev->ddesc.idProduct), 984 dev->address, pipe, 985 ed->bEndpointAddress, ed->bmAttributes); 986 #undef DONE 987 } 988 989 void uhci_dump_iis(struct uhci_softc *sc); 990 void 991 uhci_dump_iis(struct uhci_softc *sc) 992 { 993 uhci_intr_info_t *ii; 994 995 printf("intr_info list:\n"); 996 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = LIST_NEXT(ii, list)) 997 uhci_dump_ii(ii); 998 } 999 1000 void iidump(void); 1001 void iidump(void) { uhci_dump_iis(thesc); } 1002 1003 #endif 1004 1005 /* 1006 * This routine is executed periodically and simulates interrupts 1007 * from the root controller interrupt pipe for port status change. 1008 */ 1009 void 1010 uhci_poll_hub(void *addr) 1011 { 1012 usbd_xfer_handle xfer = addr; 1013 usbd_pipe_handle pipe = xfer->pipe; 1014 uhci_softc_t *sc; 1015 u_char *p; 1016 1017 DPRINTFN(20, ("uhci_poll_hub\n")); 1018 1019 if (__predict_false(pipe->device == NULL || pipe->device->bus == NULL)) 1020 return; /* device has detached */ 1021 sc = pipe->device->bus->hci_private; 1022 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 1023 1024 p = KERNADDR(&xfer->dmabuf, 0); 1025 p[0] = 0; 1026 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1027 p[0] |= 1<<1; 1028 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1029 p[0] |= 1<<2; 1030 if (p[0] == 0) 1031 /* No change, try again in a while */ 1032 return; 1033 1034 xfer->actlen = 1; 1035 xfer->status = USBD_NORMAL_COMPLETION; 1036 mutex_enter(&sc->sc_lock); 1037 usb_transfer_complete(xfer); 1038 mutex_exit(&sc->sc_lock); 1039 } 1040 1041 void 1042 uhci_root_intr_done(usbd_xfer_handle xfer) 1043 { 1044 } 1045 1046 void 1047 uhci_root_ctrl_done(usbd_xfer_handle xfer) 1048 { 1049 } 1050 1051 /* 1052 * Let the last QH loop back to the high speed control transfer QH. 1053 * This is what intel calls "bandwidth reclamation" and improves 1054 * USB performance a lot for some devices. 1055 * If we are already looping, just count it. 1056 */ 1057 void 1058 uhci_add_loop(uhci_softc_t *sc) { 1059 #ifdef UHCI_DEBUG 1060 if (uhcinoloop) 1061 return; 1062 #endif 1063 if (++sc->sc_loops == 1) { 1064 DPRINTFN(5,("uhci_start_loop: add\n")); 1065 /* Note, we don't loop back the soft pointer. */ 1066 sc->sc_last_qh->qh.qh_hlink = 1067 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 1068 usb_syncmem(&sc->sc_last_qh->dma, 1069 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1070 sizeof(sc->sc_last_qh->qh.qh_hlink), 1071 BUS_DMASYNC_PREWRITE); 1072 } 1073 } 1074 1075 void 1076 uhci_rem_loop(uhci_softc_t *sc) { 1077 #ifdef UHCI_DEBUG 1078 if (uhcinoloop) 1079 return; 1080 #endif 1081 if (--sc->sc_loops == 0) { 1082 DPRINTFN(5,("uhci_end_loop: remove\n")); 1083 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 1084 usb_syncmem(&sc->sc_last_qh->dma, 1085 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1086 sizeof(sc->sc_last_qh->qh.qh_hlink), 1087 BUS_DMASYNC_PREWRITE); 1088 } 1089 } 1090 1091 /* Add high speed control QH, called with lock held. */ 1092 void 1093 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1094 { 1095 uhci_soft_qh_t *eqh; 1096 1097 KASSERT(mutex_owned(&sc->sc_lock)); 1098 1099 DPRINTFN(10, ("uhci_add_ctrl: sqh=%p\n", sqh)); 1100 eqh = sc->sc_hctl_end; 1101 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1102 sizeof(eqh->qh.qh_hlink), 1103 BUS_DMASYNC_POSTWRITE); 1104 sqh->hlink = eqh->hlink; 1105 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1106 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1107 BUS_DMASYNC_PREWRITE); 1108 eqh->hlink = sqh; 1109 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1110 sc->sc_hctl_end = sqh; 1111 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1112 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1113 #ifdef UHCI_CTL_LOOP 1114 uhci_add_loop(sc); 1115 #endif 1116 } 1117 1118 /* Remove high speed control QH, called with lock held. */ 1119 void 1120 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1121 { 1122 uhci_soft_qh_t *pqh; 1123 1124 KASSERT(mutex_owned(&sc->sc_lock)); 1125 1126 DPRINTFN(10, ("uhci_remove_hs_ctrl: sqh=%p\n", sqh)); 1127 #ifdef UHCI_CTL_LOOP 1128 uhci_rem_loop(sc); 1129 #endif 1130 /* 1131 * The T bit should be set in the elink of the QH so that the HC 1132 * doesn't follow the pointer. This condition may fail if the 1133 * the transferred packet was short so that the QH still points 1134 * at the last used TD. 1135 * In this case we set the T bit and wait a little for the HC 1136 * to stop looking at the TD. 1137 * Note that if the TD chain is large enough, the controller 1138 * may still be looking at the chain at the end of this function. 1139 * uhci_free_std_chain() will make sure the controller stops 1140 * looking at it quickly, but until then we should not change 1141 * sqh->hlink. 1142 */ 1143 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1144 sizeof(sqh->qh.qh_elink), 1145 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1146 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1147 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1148 usb_syncmem(&sqh->dma, 1149 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1150 sizeof(sqh->qh.qh_elink), 1151 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1152 delay(UHCI_QH_REMOVE_DELAY); 1153 } 1154 1155 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1156 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1157 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1158 pqh->hlink = sqh->hlink; 1159 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1160 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1161 sizeof(pqh->qh.qh_hlink), 1162 BUS_DMASYNC_PREWRITE); 1163 delay(UHCI_QH_REMOVE_DELAY); 1164 if (sc->sc_hctl_end == sqh) 1165 sc->sc_hctl_end = pqh; 1166 } 1167 1168 /* Add low speed control QH, called with lock held. */ 1169 void 1170 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1171 { 1172 uhci_soft_qh_t *eqh; 1173 1174 KASSERT(mutex_owned(&sc->sc_lock)); 1175 1176 DPRINTFN(10, ("uhci_add_ls_ctrl: sqh=%p\n", sqh)); 1177 eqh = sc->sc_lctl_end; 1178 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1179 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1180 sqh->hlink = eqh->hlink; 1181 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1182 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1183 BUS_DMASYNC_PREWRITE); 1184 eqh->hlink = sqh; 1185 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1186 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1187 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1188 sc->sc_lctl_end = sqh; 1189 } 1190 1191 /* Remove low speed control QH, called with lock held. */ 1192 void 1193 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1194 { 1195 uhci_soft_qh_t *pqh; 1196 1197 KASSERT(mutex_owned(&sc->sc_lock)); 1198 1199 DPRINTFN(10, ("uhci_remove_ls_ctrl: sqh=%p\n", sqh)); 1200 /* See comment in uhci_remove_hs_ctrl() */ 1201 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1202 sizeof(sqh->qh.qh_elink), 1203 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1204 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1205 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1206 usb_syncmem(&sqh->dma, 1207 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1208 sizeof(sqh->qh.qh_elink), 1209 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1210 delay(UHCI_QH_REMOVE_DELAY); 1211 } 1212 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1213 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1214 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1215 pqh->hlink = sqh->hlink; 1216 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1217 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1218 sizeof(pqh->qh.qh_hlink), 1219 BUS_DMASYNC_PREWRITE); 1220 delay(UHCI_QH_REMOVE_DELAY); 1221 if (sc->sc_lctl_end == sqh) 1222 sc->sc_lctl_end = pqh; 1223 } 1224 1225 /* Add bulk QH, called with lock held. */ 1226 void 1227 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1228 { 1229 uhci_soft_qh_t *eqh; 1230 1231 KASSERT(mutex_owned(&sc->sc_lock)); 1232 1233 DPRINTFN(10, ("uhci_add_bulk: sqh=%p\n", sqh)); 1234 eqh = sc->sc_bulk_end; 1235 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1236 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1237 sqh->hlink = eqh->hlink; 1238 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1239 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1240 BUS_DMASYNC_PREWRITE); 1241 eqh->hlink = sqh; 1242 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1243 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1244 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1245 sc->sc_bulk_end = sqh; 1246 uhci_add_loop(sc); 1247 } 1248 1249 /* Remove bulk QH, called with lock held. */ 1250 void 1251 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1252 { 1253 uhci_soft_qh_t *pqh; 1254 1255 KASSERT(mutex_owned(&sc->sc_lock)); 1256 1257 DPRINTFN(10, ("uhci_remove_bulk: sqh=%p\n", sqh)); 1258 uhci_rem_loop(sc); 1259 /* See comment in uhci_remove_hs_ctrl() */ 1260 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1261 sizeof(sqh->qh.qh_elink), 1262 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1263 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1264 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1265 usb_syncmem(&sqh->dma, 1266 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1267 sizeof(sqh->qh.qh_elink), 1268 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1269 delay(UHCI_QH_REMOVE_DELAY); 1270 } 1271 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1272 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1273 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1274 pqh->hlink = sqh->hlink; 1275 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1276 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1277 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1278 delay(UHCI_QH_REMOVE_DELAY); 1279 if (sc->sc_bulk_end == sqh) 1280 sc->sc_bulk_end = pqh; 1281 } 1282 1283 Static int uhci_intr1(uhci_softc_t *); 1284 1285 int 1286 uhci_intr(void *arg) 1287 { 1288 uhci_softc_t *sc = arg; 1289 int ret = 0; 1290 1291 mutex_spin_enter(&sc->sc_intr_lock); 1292 1293 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1294 goto done; 1295 1296 if (sc->sc_bus.use_polling || UREAD2(sc, UHCI_INTR) == 0) { 1297 #ifdef DIAGNOSTIC 1298 DPRINTFN(16, ("uhci_intr: ignored interrupt while polling\n")); 1299 #endif 1300 goto done; 1301 } 1302 1303 ret = uhci_intr1(sc); 1304 1305 done: 1306 mutex_spin_exit(&sc->sc_intr_lock); 1307 return ret; 1308 } 1309 1310 int 1311 uhci_intr1(uhci_softc_t *sc) 1312 { 1313 int status; 1314 int ack; 1315 1316 #ifdef UHCI_DEBUG 1317 if (uhcidebug > 15) { 1318 DPRINTF(("%s: uhci_intr1\n", device_xname(sc->sc_dev))); 1319 uhci_dumpregs(sc); 1320 } 1321 #endif 1322 1323 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1324 1325 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1326 if (status == 0) /* The interrupt was not for us. */ 1327 return (0); 1328 1329 if (sc->sc_suspend != PWR_RESUME) { 1330 #ifdef DIAGNOSTIC 1331 printf("%s: interrupt while not operating ignored\n", 1332 device_xname(sc->sc_dev)); 1333 #endif 1334 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1335 return (0); 1336 } 1337 1338 ack = 0; 1339 if (status & UHCI_STS_USBINT) 1340 ack |= UHCI_STS_USBINT; 1341 if (status & UHCI_STS_USBEI) 1342 ack |= UHCI_STS_USBEI; 1343 if (status & UHCI_STS_RD) { 1344 ack |= UHCI_STS_RD; 1345 #ifdef UHCI_DEBUG 1346 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1347 #endif 1348 } 1349 if (status & UHCI_STS_HSE) { 1350 ack |= UHCI_STS_HSE; 1351 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1352 } 1353 if (status & UHCI_STS_HCPE) { 1354 ack |= UHCI_STS_HCPE; 1355 printf("%s: host controller process error\n", 1356 device_xname(sc->sc_dev)); 1357 } 1358 1359 /* When HCHalted=1 and Run/Stop=0 , it is normal */ 1360 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 1361 /* no acknowledge needed */ 1362 if (!sc->sc_dying) { 1363 printf("%s: host controller halted\n", 1364 device_xname(sc->sc_dev)); 1365 #ifdef UHCI_DEBUG 1366 uhci_dump_all(sc); 1367 #endif 1368 } 1369 sc->sc_dying = 1; 1370 } 1371 1372 if (!ack) 1373 return (0); /* nothing to acknowledge */ 1374 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1375 1376 sc->sc_bus.no_intrs++; 1377 usb_schedsoftintr(&sc->sc_bus); 1378 1379 DPRINTFN(15, ("%s: uhci_intr: exit\n", device_xname(sc->sc_dev))); 1380 1381 return (1); 1382 } 1383 1384 void 1385 uhci_softintr(void *v) 1386 { 1387 struct usbd_bus *bus = v; 1388 uhci_softc_t *sc = bus->hci_private; 1389 uhci_intr_info_t *ii, *nextii; 1390 1391 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1392 1393 DPRINTFN(10,("%s: uhci_softintr\n", device_xname(sc->sc_dev))); 1394 1395 /* 1396 * Interrupts on UHCI really suck. When the host controller 1397 * interrupts because a transfer is completed there is no 1398 * way of knowing which transfer it was. You can scan down 1399 * the TDs and QHs of the previous frame to limit the search, 1400 * but that assumes that the interrupt was not delayed by more 1401 * than 1 ms, which may not always be true (e.g. after debug 1402 * output on a slow console). 1403 * We scan all interrupt descriptors to see if any have 1404 * completed. 1405 */ 1406 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = nextii) { 1407 nextii = LIST_NEXT(ii, list); 1408 uhci_check_intr(sc, ii); 1409 } 1410 1411 if (sc->sc_softwake) { 1412 sc->sc_softwake = 0; 1413 cv_broadcast(&sc->sc_softwake_cv); 1414 } 1415 } 1416 1417 /* Check for an interrupt. */ 1418 void 1419 uhci_check_intr(uhci_softc_t *sc, uhci_intr_info_t *ii) 1420 { 1421 uhci_soft_td_t *std, *lstd; 1422 u_int32_t status; 1423 1424 DPRINTFN(15, ("uhci_check_intr: ii=%p\n", ii)); 1425 #ifdef DIAGNOSTIC 1426 if (ii == NULL) { 1427 printf("uhci_check_intr: no ii? %p\n", ii); 1428 return; 1429 } 1430 #endif 1431 if (ii->xfer->status == USBD_CANCELLED || 1432 ii->xfer->status == USBD_TIMEOUT) { 1433 DPRINTF(("uhci_check_intr: aborted xfer=%p\n", ii->xfer)); 1434 return; 1435 } 1436 1437 if (ii->stdstart == NULL) 1438 return; 1439 lstd = ii->stdend; 1440 #ifdef DIAGNOSTIC 1441 if (lstd == NULL) { 1442 printf("uhci_check_intr: std==0\n"); 1443 return; 1444 } 1445 #endif 1446 /* 1447 * If the last TD is still active we need to check whether there 1448 * is an error somewhere in the middle, or whether there was a 1449 * short packet (SPD and not ACTIVE). 1450 */ 1451 usb_syncmem(&lstd->dma, 1452 lstd->offs + offsetof(uhci_td_t, td_status), 1453 sizeof(lstd->td.td_status), 1454 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1455 if (le32toh(lstd->td.td_status) & UHCI_TD_ACTIVE) { 1456 DPRINTFN(12, ("uhci_check_intr: active ii=%p\n", ii)); 1457 for (std = ii->stdstart; std != lstd; std = std->link.std) { 1458 usb_syncmem(&std->dma, 1459 std->offs + offsetof(uhci_td_t, td_status), 1460 sizeof(std->td.td_status), 1461 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1462 status = le32toh(std->td.td_status); 1463 usb_syncmem(&std->dma, 1464 std->offs + offsetof(uhci_td_t, td_status), 1465 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1466 /* If there's an active TD the xfer isn't done. */ 1467 if (status & UHCI_TD_ACTIVE) 1468 break; 1469 /* Any kind of error makes the xfer done. */ 1470 if (status & UHCI_TD_STALLED) 1471 goto done; 1472 /* We want short packets, and it is short: it's done */ 1473 usb_syncmem(&std->dma, 1474 std->offs + offsetof(uhci_td_t, td_token), 1475 sizeof(std->td.td_token), 1476 BUS_DMASYNC_POSTWRITE); 1477 if ((status & UHCI_TD_SPD) && 1478 UHCI_TD_GET_ACTLEN(status) < 1479 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) 1480 goto done; 1481 } 1482 DPRINTFN(12, ("uhci_check_intr: ii=%p std=%p still active\n", 1483 ii, ii->stdstart)); 1484 usb_syncmem(&lstd->dma, 1485 lstd->offs + offsetof(uhci_td_t, td_status), 1486 sizeof(lstd->td.td_status), 1487 BUS_DMASYNC_PREREAD); 1488 return; 1489 } 1490 done: 1491 DPRINTFN(12, ("uhci_check_intr: ii=%p done\n", ii)); 1492 callout_stop(&ii->xfer->timeout_handle); 1493 uhci_idone(ii); 1494 } 1495 1496 /* Called with USB lock held. */ 1497 void 1498 uhci_idone(uhci_intr_info_t *ii) 1499 { 1500 usbd_xfer_handle xfer = ii->xfer; 1501 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 1502 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 1503 uhci_soft_td_t *std; 1504 u_int32_t status = 0, nstatus; 1505 int actlen; 1506 1507 KASSERT(mutex_owned(&sc->sc_lock)); 1508 1509 DPRINTFN(12, ("uhci_idone: ii=%p\n", ii)); 1510 #ifdef DIAGNOSTIC 1511 { 1512 /* XXX SMP? */ 1513 int s = splhigh(); 1514 if (ii->isdone) { 1515 splx(s); 1516 #ifdef UHCI_DEBUG 1517 printf("uhci_idone: ii is done!\n "); 1518 uhci_dump_ii(ii); 1519 #else 1520 printf("uhci_idone: ii=%p is done!\n", ii); 1521 #endif 1522 return; 1523 } 1524 ii->isdone = 1; 1525 splx(s); 1526 } 1527 #endif 1528 1529 if (xfer->nframes != 0) { 1530 /* Isoc transfer, do things differently. */ 1531 uhci_soft_td_t **stds = upipe->u.iso.stds; 1532 int i, n, nframes, len; 1533 1534 DPRINTFN(5,("uhci_idone: ii=%p isoc ready\n", ii)); 1535 1536 nframes = xfer->nframes; 1537 actlen = 0; 1538 n = UXFER(xfer)->curframe; 1539 for (i = 0; i < nframes; i++) { 1540 std = stds[n]; 1541 #ifdef UHCI_DEBUG 1542 if (uhcidebug > 5) { 1543 DPRINTFN(-1,("uhci_idone: isoc TD %d\n", i)); 1544 uhci_dump_td(std); 1545 } 1546 #endif 1547 if (++n >= UHCI_VFRAMELIST_COUNT) 1548 n = 0; 1549 usb_syncmem(&std->dma, 1550 std->offs + offsetof(uhci_td_t, td_status), 1551 sizeof(std->td.td_status), 1552 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1553 status = le32toh(std->td.td_status); 1554 len = UHCI_TD_GET_ACTLEN(status); 1555 xfer->frlengths[i] = len; 1556 actlen += len; 1557 } 1558 upipe->u.iso.inuse -= nframes; 1559 xfer->actlen = actlen; 1560 xfer->status = USBD_NORMAL_COMPLETION; 1561 goto end; 1562 } 1563 1564 #ifdef UHCI_DEBUG 1565 DPRINTFN(10, ("uhci_idone: ii=%p, xfer=%p, pipe=%p ready\n", 1566 ii, xfer, upipe)); 1567 if (uhcidebug > 10) 1568 uhci_dump_tds(ii->stdstart); 1569 #endif 1570 1571 /* The transfer is done, compute actual length and status. */ 1572 actlen = 0; 1573 for (std = ii->stdstart; std != NULL; std = std->link.std) { 1574 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1575 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1576 nstatus = le32toh(std->td.td_status); 1577 if (nstatus & UHCI_TD_ACTIVE) 1578 break; 1579 1580 status = nstatus; 1581 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1582 UHCI_TD_PID_SETUP) 1583 actlen += UHCI_TD_GET_ACTLEN(status); 1584 else { 1585 /* 1586 * UHCI will report CRCTO in addition to a STALL or NAK 1587 * for a SETUP transaction. See section 3.2.2, "TD 1588 * CONTROL AND STATUS". 1589 */ 1590 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1591 status &= ~UHCI_TD_CRCTO; 1592 } 1593 } 1594 /* If there are left over TDs we need to update the toggle. */ 1595 if (std != NULL) 1596 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1597 1598 status &= UHCI_TD_ERROR; 1599 DPRINTFN(10, ("uhci_idone: actlen=%d, status=0x%x\n", 1600 actlen, status)); 1601 xfer->actlen = actlen; 1602 if (status != 0) { 1603 #ifdef UHCI_DEBUG 1604 char sbuf[128]; 1605 1606 snprintb(sbuf, sizeof(sbuf), 1607 "\20\22BITSTUFF\23CRCTO\24NAK\25" 1608 "BABBLE\26DBUFFER\27STALLED\30ACTIVE",(u_int32_t)status); 1609 1610 DPRINTFN((status == UHCI_TD_STALLED)*10, 1611 ("uhci_idone: error, addr=%d, endpt=0x%02x, " 1612 "status 0x%s\n", 1613 xfer->pipe->device->address, 1614 xfer->pipe->endpoint->edesc->bEndpointAddress, 1615 sbuf)); 1616 #endif 1617 1618 if (status == UHCI_TD_STALLED) 1619 xfer->status = USBD_STALLED; 1620 else 1621 xfer->status = USBD_IOERROR; /* more info XXX */ 1622 } else { 1623 xfer->status = USBD_NORMAL_COMPLETION; 1624 } 1625 1626 end: 1627 usb_transfer_complete(xfer); 1628 KASSERT(mutex_owned(&sc->sc_lock)); 1629 DPRINTFN(12, ("uhci_idone: ii=%p done\n", ii)); 1630 } 1631 1632 /* 1633 * Called when a request does not complete. 1634 */ 1635 void 1636 uhci_timeout(void *addr) 1637 { 1638 uhci_intr_info_t *ii = addr; 1639 struct uhci_xfer *uxfer = UXFER(ii->xfer); 1640 struct uhci_pipe *upipe = (struct uhci_pipe *)uxfer->xfer.pipe; 1641 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 1642 1643 DPRINTF(("uhci_timeout: uxfer=%p\n", uxfer)); 1644 1645 if (sc->sc_dying) { 1646 mutex_enter(&sc->sc_lock); 1647 uhci_abort_xfer(&uxfer->xfer, USBD_TIMEOUT); 1648 mutex_exit(&sc->sc_lock); 1649 return; 1650 } 1651 1652 /* Execute the abort in a process context. */ 1653 usb_init_task(&uxfer->abort_task, uhci_timeout_task, ii->xfer); 1654 usb_add_task(uxfer->xfer.pipe->device, &uxfer->abort_task, 1655 USB_TASKQ_HC); 1656 } 1657 1658 void 1659 uhci_timeout_task(void *addr) 1660 { 1661 usbd_xfer_handle xfer = addr; 1662 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1663 1664 DPRINTF(("uhci_timeout_task: xfer=%p\n", xfer)); 1665 1666 mutex_enter(&sc->sc_lock); 1667 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1668 mutex_exit(&sc->sc_lock); 1669 } 1670 1671 /* 1672 * Wait here until controller claims to have an interrupt. 1673 * Then call uhci_intr and return. Use timeout to avoid waiting 1674 * too long. 1675 * Only used during boot when interrupts are not enabled yet. 1676 */ 1677 void 1678 uhci_waitintr(uhci_softc_t *sc, usbd_xfer_handle xfer) 1679 { 1680 int timo = xfer->timeout; 1681 uhci_intr_info_t *ii; 1682 1683 mutex_enter(&sc->sc_lock); 1684 1685 DPRINTFN(10,("uhci_waitintr: timeout = %dms\n", timo)); 1686 1687 xfer->status = USBD_IN_PROGRESS; 1688 for (; timo >= 0; timo--) { 1689 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_lock); 1690 DPRINTFN(20,("uhci_waitintr: 0x%04x\n", UREAD2(sc, UHCI_STS))); 1691 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1692 mutex_spin_enter(&sc->sc_intr_lock); 1693 uhci_intr1(sc); 1694 mutex_spin_exit(&sc->sc_intr_lock); 1695 if (xfer->status != USBD_IN_PROGRESS) 1696 goto done; 1697 } 1698 } 1699 1700 /* Timeout */ 1701 DPRINTF(("uhci_waitintr: timeout\n")); 1702 for (ii = LIST_FIRST(&sc->sc_intrhead); 1703 ii != NULL && ii->xfer != xfer; 1704 ii = LIST_NEXT(ii, list)) 1705 ; 1706 #ifdef DIAGNOSTIC 1707 if (ii == NULL) 1708 panic("uhci_waitintr: lost intr_info"); 1709 #endif 1710 uhci_idone(ii); 1711 1712 done: 1713 mutex_exit(&sc->sc_lock); 1714 } 1715 1716 void 1717 uhci_poll(struct usbd_bus *bus) 1718 { 1719 uhci_softc_t *sc = bus->hci_private; 1720 1721 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1722 mutex_spin_enter(&sc->sc_intr_lock); 1723 uhci_intr1(sc); 1724 mutex_spin_exit(&sc->sc_intr_lock); 1725 } 1726 } 1727 1728 void 1729 uhci_reset(uhci_softc_t *sc) 1730 { 1731 int n; 1732 1733 UHCICMD(sc, UHCI_CMD_HCRESET); 1734 /* The reset bit goes low when the controller is done. */ 1735 for (n = 0; n < UHCI_RESET_TIMEOUT && 1736 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1737 usb_delay_ms(&sc->sc_bus, 1); 1738 if (n >= UHCI_RESET_TIMEOUT) 1739 printf("%s: controller did not reset\n", 1740 device_xname(sc->sc_dev)); 1741 } 1742 1743 usbd_status 1744 uhci_run(uhci_softc_t *sc, int run) 1745 { 1746 int n, running; 1747 u_int16_t cmd; 1748 1749 run = run != 0; 1750 mutex_spin_enter(&sc->sc_intr_lock); 1751 DPRINTF(("uhci_run: setting run=%d\n", run)); 1752 cmd = UREAD2(sc, UHCI_CMD); 1753 if (run) 1754 cmd |= UHCI_CMD_RS; 1755 else 1756 cmd &= ~UHCI_CMD_RS; 1757 UHCICMD(sc, cmd); 1758 for(n = 0; n < 10; n++) { 1759 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1760 /* return when we've entered the state we want */ 1761 if (run == running) { 1762 mutex_spin_exit(&sc->sc_intr_lock); 1763 DPRINTF(("uhci_run: done cmd=0x%x sts=0x%x\n", 1764 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS))); 1765 return (USBD_NORMAL_COMPLETION); 1766 } 1767 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock); 1768 } 1769 mutex_spin_exit(&sc->sc_intr_lock); 1770 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1771 run ? "start" : "stop"); 1772 return (USBD_IOERROR); 1773 } 1774 1775 /* 1776 * Memory management routines. 1777 * uhci_alloc_std allocates TDs 1778 * uhci_alloc_sqh allocates QHs 1779 * These two routines do their own free list management, 1780 * partly for speed, partly because allocating DMAable memory 1781 * has page size granularaity so much memory would be wasted if 1782 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1783 */ 1784 1785 uhci_soft_td_t * 1786 uhci_alloc_std(uhci_softc_t *sc) 1787 { 1788 uhci_soft_td_t *std; 1789 usbd_status err; 1790 int i, offs; 1791 usb_dma_t dma; 1792 1793 if (sc->sc_freetds == NULL) { 1794 DPRINTFN(2,("uhci_alloc_std: allocating chunk\n")); 1795 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1796 UHCI_TD_ALIGN, &dma); 1797 if (err) 1798 return (0); 1799 for (i = 0; i < UHCI_STD_CHUNK; i++) { 1800 offs = i * UHCI_STD_SIZE; 1801 std = KERNADDR(&dma, offs); 1802 std->physaddr = DMAADDR(&dma, offs); 1803 std->dma = dma; 1804 std->offs = offs; 1805 std->link.std = sc->sc_freetds; 1806 sc->sc_freetds = std; 1807 } 1808 } 1809 std = sc->sc_freetds; 1810 sc->sc_freetds = std->link.std; 1811 memset(&std->td, 0, sizeof(uhci_td_t)); 1812 return std; 1813 } 1814 1815 void 1816 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1817 { 1818 #ifdef DIAGNOSTIC 1819 #define TD_IS_FREE 0x12345678 1820 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1821 printf("uhci_free_std: freeing free TD %p\n", std); 1822 return; 1823 } 1824 std->td.td_token = htole32(TD_IS_FREE); 1825 #endif 1826 std->link.std = sc->sc_freetds; 1827 sc->sc_freetds = std; 1828 } 1829 1830 uhci_soft_qh_t * 1831 uhci_alloc_sqh(uhci_softc_t *sc) 1832 { 1833 uhci_soft_qh_t *sqh; 1834 usbd_status err; 1835 int i, offs; 1836 usb_dma_t dma; 1837 1838 if (sc->sc_freeqhs == NULL) { 1839 DPRINTFN(2, ("uhci_alloc_sqh: allocating chunk\n")); 1840 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1841 UHCI_QH_ALIGN, &dma); 1842 if (err) 1843 return (0); 1844 for(i = 0; i < UHCI_SQH_CHUNK; i++) { 1845 offs = i * UHCI_SQH_SIZE; 1846 sqh = KERNADDR(&dma, offs); 1847 sqh->physaddr = DMAADDR(&dma, offs); 1848 sqh->dma = dma; 1849 sqh->offs = offs; 1850 sqh->hlink = sc->sc_freeqhs; 1851 sc->sc_freeqhs = sqh; 1852 } 1853 } 1854 sqh = sc->sc_freeqhs; 1855 sc->sc_freeqhs = sqh->hlink; 1856 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1857 return (sqh); 1858 } 1859 1860 void 1861 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1862 { 1863 sqh->hlink = sc->sc_freeqhs; 1864 sc->sc_freeqhs = sqh; 1865 } 1866 1867 void 1868 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1869 uhci_soft_td_t *stdend) 1870 { 1871 uhci_soft_td_t *p; 1872 1873 /* 1874 * to avoid race condition with the controller which may be looking 1875 * at this chain, we need to first invalidate all links, and 1876 * then wait for the controller to move to another queue 1877 */ 1878 for (p = std; p != stdend; p = p->link.std) { 1879 usb_syncmem(&p->dma, 1880 p->offs + offsetof(uhci_td_t, td_link), 1881 sizeof(p->td.td_link), 1882 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1883 if ((p->td.td_link & UHCI_PTR_T) == 0) { 1884 p->td.td_link = UHCI_PTR_T; 1885 usb_syncmem(&p->dma, 1886 p->offs + offsetof(uhci_td_t, td_link), 1887 sizeof(p->td.td_link), 1888 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1889 } 1890 } 1891 delay(UHCI_QH_REMOVE_DELAY); 1892 1893 for (; std != stdend; std = p) { 1894 p = std->link.std; 1895 uhci_free_std(sc, std); 1896 } 1897 } 1898 1899 usbd_status 1900 uhci_alloc_std_chain(struct uhci_pipe *upipe, uhci_softc_t *sc, int len, 1901 int rd, u_int16_t flags, usb_dma_t *dma, 1902 uhci_soft_td_t **sp, uhci_soft_td_t **ep) 1903 { 1904 uhci_soft_td_t *p, *lastp; 1905 uhci_physaddr_t lastlink; 1906 int i, ntd, l, tog, maxp; 1907 u_int32_t status; 1908 int addr = upipe->pipe.device->address; 1909 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 1910 1911 DPRINTFN(8, ("uhci_alloc_std_chain: addr=%d endpt=%d len=%d speed=%d " 1912 "flags=0x%x\n", addr, UE_GET_ADDR(endpt), len, 1913 upipe->pipe.device->speed, flags)); 1914 1915 KASSERT(mutex_owned(&sc->sc_lock)); 1916 1917 maxp = UGETW(upipe->pipe.endpoint->edesc->wMaxPacketSize); 1918 if (maxp == 0) { 1919 printf("uhci_alloc_std_chain: maxp=0\n"); 1920 return (USBD_INVAL); 1921 } 1922 ntd = (len + maxp - 1) / maxp; 1923 if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0) 1924 ntd++; 1925 DPRINTFN(10, ("uhci_alloc_std_chain: maxp=%d ntd=%d\n", maxp, ntd)); 1926 if (ntd == 0) { 1927 *sp = *ep = 0; 1928 DPRINTFN(-1,("uhci_alloc_std_chain: ntd=0\n")); 1929 return (USBD_NORMAL_COMPLETION); 1930 } 1931 tog = upipe->nexttoggle; 1932 if (ntd % 2 == 0) 1933 tog ^= 1; 1934 upipe->nexttoggle = tog ^ 1; 1935 lastp = NULL; 1936 lastlink = UHCI_PTR_T; 1937 ntd--; 1938 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 1939 if (upipe->pipe.device->speed == USB_SPEED_LOW) 1940 status |= UHCI_TD_LS; 1941 if (flags & USBD_SHORT_XFER_OK) 1942 status |= UHCI_TD_SPD; 1943 usb_syncmem(dma, 0, len, 1944 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1945 for (i = ntd; i >= 0; i--) { 1946 p = uhci_alloc_std(sc); 1947 if (p == NULL) { 1948 KASSERT(lastp != NULL); 1949 uhci_free_std_chain(sc, lastp, NULL); 1950 return (USBD_NOMEM); 1951 } 1952 p->link.std = lastp; 1953 p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD); 1954 lastp = p; 1955 lastlink = p->physaddr; 1956 p->td.td_status = htole32(status); 1957 if (i == ntd) { 1958 /* last TD */ 1959 l = len % maxp; 1960 if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER)) 1961 l = maxp; 1962 *ep = p; 1963 } else 1964 l = maxp; 1965 p->td.td_token = 1966 htole32(rd ? UHCI_TD_IN (l, endpt, addr, tog) : 1967 UHCI_TD_OUT(l, endpt, addr, tog)); 1968 p->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 1969 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 1970 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1971 tog ^= 1; 1972 } 1973 *sp = lastp; 1974 DPRINTFN(10, ("uhci_alloc_std_chain: nexttog=%d\n", 1975 upipe->nexttoggle)); 1976 return (USBD_NORMAL_COMPLETION); 1977 } 1978 1979 void 1980 uhci_device_clear_toggle(usbd_pipe_handle pipe) 1981 { 1982 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 1983 upipe->nexttoggle = 0; 1984 } 1985 1986 void 1987 uhci_noop(usbd_pipe_handle pipe) 1988 { 1989 } 1990 1991 usbd_status 1992 uhci_device_bulk_transfer(usbd_xfer_handle xfer) 1993 { 1994 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1995 usbd_status err; 1996 1997 /* Insert last in queue. */ 1998 mutex_enter(&sc->sc_lock); 1999 err = usb_insert_transfer(xfer); 2000 mutex_exit(&sc->sc_lock); 2001 if (err) 2002 return (err); 2003 2004 /* 2005 * Pipe isn't running (otherwise err would be USBD_INPROG), 2006 * so start it first. 2007 */ 2008 return (uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2009 } 2010 2011 usbd_status 2012 uhci_device_bulk_start(usbd_xfer_handle xfer) 2013 { 2014 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2015 usbd_device_handle dev = upipe->pipe.device; 2016 uhci_softc_t *sc = dev->bus->hci_private; 2017 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2018 uhci_soft_td_t *data, *dataend; 2019 uhci_soft_qh_t *sqh; 2020 usbd_status err; 2021 int len, isread, endpt; 2022 2023 DPRINTFN(3, ("uhci_device_bulk_start: xfer=%p len=%d flags=%d ii=%p\n", 2024 xfer, xfer->length, xfer->flags, ii)); 2025 2026 if (sc->sc_dying) 2027 return (USBD_IOERROR); 2028 2029 #ifdef DIAGNOSTIC 2030 if (xfer->rqflags & URQ_REQUEST) 2031 panic("uhci_device_bulk_transfer: a request"); 2032 #endif 2033 2034 mutex_enter(&sc->sc_lock); 2035 2036 len = xfer->length; 2037 endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2038 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2039 sqh = upipe->u.bulk.sqh; 2040 2041 upipe->u.bulk.isread = isread; 2042 upipe->u.bulk.length = len; 2043 2044 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->flags, 2045 &xfer->dmabuf, &data, &dataend); 2046 if (err) { 2047 mutex_exit(&sc->sc_lock); 2048 return (err); 2049 } 2050 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2051 usb_syncmem(&dataend->dma, 2052 dataend->offs + offsetof(uhci_td_t, td_status), 2053 sizeof(dataend->td.td_status), 2054 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2055 2056 2057 #ifdef UHCI_DEBUG 2058 if (uhcidebug > 8) { 2059 DPRINTF(("uhci_device_bulk_transfer: data(1)\n")); 2060 uhci_dump_tds(data); 2061 } 2062 #endif 2063 2064 /* Set up interrupt info. */ 2065 ii->xfer = xfer; 2066 ii->stdstart = data; 2067 ii->stdend = dataend; 2068 #ifdef DIAGNOSTIC 2069 if (!ii->isdone) { 2070 printf("uhci_device_bulk_transfer: not done, ii=%p\n", ii); 2071 } 2072 ii->isdone = 0; 2073 #endif 2074 2075 sqh->elink = data; 2076 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2077 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2078 2079 uhci_add_bulk(sc, sqh); 2080 uhci_add_intr_info(sc, ii); 2081 2082 if (xfer->timeout && !sc->sc_bus.use_polling) { 2083 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 2084 uhci_timeout, ii); 2085 } 2086 xfer->status = USBD_IN_PROGRESS; 2087 2088 #ifdef UHCI_DEBUG 2089 if (uhcidebug > 10) { 2090 DPRINTF(("uhci_device_bulk_transfer: data(2)\n")); 2091 uhci_dump_tds(data); 2092 } 2093 #endif 2094 2095 if (sc->sc_bus.use_polling) 2096 uhci_waitintr(sc, xfer); 2097 2098 mutex_exit(&sc->sc_lock); 2099 return (USBD_IN_PROGRESS); 2100 } 2101 2102 /* Abort a device bulk request. */ 2103 void 2104 uhci_device_bulk_abort(usbd_xfer_handle xfer) 2105 { 2106 #ifdef DIAGNOSTIC 2107 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2108 #endif 2109 2110 KASSERT(mutex_owned(&sc->sc_lock)); 2111 2112 DPRINTF(("uhci_device_bulk_abort:\n")); 2113 uhci_abort_xfer(xfer, USBD_CANCELLED); 2114 } 2115 2116 /* 2117 * Abort a device request. 2118 * If this routine is called at splusb() it guarantees that the request 2119 * will be removed from the hardware scheduling and that the callback 2120 * for it will be called with USBD_CANCELLED status. 2121 * It's impossible to guarantee that the requested transfer will not 2122 * have happened since the hardware runs concurrently. 2123 * If the transaction has already happened we rely on the ordinary 2124 * interrupt processing to process it. 2125 * XXX This is most probably wrong. 2126 * XXXMRG this doesn't make sense anymore. 2127 */ 2128 void 2129 uhci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2130 { 2131 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2132 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2133 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 2134 uhci_soft_td_t *std; 2135 int wake; 2136 2137 DPRINTFN(1,("uhci_abort_xfer: xfer=%p, status=%d\n", xfer, status)); 2138 2139 KASSERT(mutex_owned(&sc->sc_lock)); 2140 2141 if (sc->sc_dying) { 2142 /* If we're dying, just do the software part. */ 2143 xfer->status = status; /* make software ignore it */ 2144 callout_stop(&xfer->timeout_handle); 2145 usb_transfer_complete(xfer); 2146 return; 2147 } 2148 2149 if (cpu_intr_p() || cpu_softintr_p()) 2150 panic("uhci_abort_xfer: not in process context"); 2151 2152 /* 2153 * If an abort is already in progress then just wait for it to 2154 * complete and return. 2155 */ 2156 if (xfer->hcflags & UXFER_ABORTING) { 2157 DPRINTFN(2, ("uhci_abort_xfer: already aborting\n")); 2158 #ifdef DIAGNOSTIC 2159 if (status == USBD_TIMEOUT) 2160 printf("uhci_abort_xfer: TIMEOUT while aborting\n"); 2161 #endif 2162 /* Override the status which might be USBD_TIMEOUT. */ 2163 xfer->status = status; 2164 DPRINTFN(2, ("uhci_abort_xfer: waiting for abort to finish\n")); 2165 xfer->hcflags |= UXFER_ABORTWAIT; 2166 while (xfer->hcflags & UXFER_ABORTING) 2167 cv_wait(&xfer->hccv, &sc->sc_lock); 2168 goto done; 2169 } 2170 xfer->hcflags |= UXFER_ABORTING; 2171 2172 /* 2173 * Step 1: Make interrupt routine and hardware ignore xfer. 2174 */ 2175 xfer->status = status; /* make software ignore it */ 2176 callout_stop(&xfer->timeout_handle); 2177 DPRINTFN(1,("uhci_abort_xfer: stop ii=%p\n", ii)); 2178 for (std = ii->stdstart; std != NULL; std = std->link.std) { 2179 usb_syncmem(&std->dma, 2180 std->offs + offsetof(uhci_td_t, td_status), 2181 sizeof(std->td.td_status), 2182 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2183 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2184 usb_syncmem(&std->dma, 2185 std->offs + offsetof(uhci_td_t, td_status), 2186 sizeof(std->td.td_status), 2187 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2188 } 2189 2190 /* 2191 * Step 2: Wait until we know hardware has finished any possible 2192 * use of the xfer. Also make sure the soft interrupt routine 2193 * has run. 2194 */ 2195 /* Hardware finishes in 1ms */ 2196 usb_delay_ms_locked(upipe->pipe.device->bus, 2, &sc->sc_lock); 2197 sc->sc_softwake = 1; 2198 usb_schedsoftintr(&sc->sc_bus); 2199 DPRINTFN(1,("uhci_abort_xfer: cv_wait\n")); 2200 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2201 2202 /* 2203 * Step 3: Execute callback. 2204 */ 2205 DPRINTFN(1,("uhci_abort_xfer: callback\n")); 2206 #ifdef DIAGNOSTIC 2207 ii->isdone = 1; 2208 #endif 2209 wake = xfer->hcflags & UXFER_ABORTWAIT; 2210 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2211 usb_transfer_complete(xfer); 2212 if (wake) 2213 cv_broadcast(&xfer->hccv); 2214 done: 2215 KASSERT(mutex_owned(&sc->sc_lock)); 2216 } 2217 2218 /* Close a device bulk pipe. */ 2219 void 2220 uhci_device_bulk_close(usbd_pipe_handle pipe) 2221 { 2222 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2223 usbd_device_handle dev = upipe->pipe.device; 2224 uhci_softc_t *sc = dev->bus->hci_private; 2225 2226 KASSERT(mutex_owned(&sc->sc_lock)); 2227 2228 uhci_free_sqh(sc, upipe->u.bulk.sqh); 2229 2230 pipe->endpoint->datatoggle = upipe->nexttoggle; 2231 } 2232 2233 usbd_status 2234 uhci_device_ctrl_transfer(usbd_xfer_handle xfer) 2235 { 2236 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2237 usbd_status err; 2238 2239 /* Insert last in queue. */ 2240 mutex_enter(&sc->sc_lock); 2241 err = usb_insert_transfer(xfer); 2242 mutex_exit(&sc->sc_lock); 2243 if (err) 2244 return (err); 2245 2246 /* 2247 * Pipe isn't running (otherwise err would be USBD_INPROG), 2248 * so start it first. 2249 */ 2250 return (uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2251 } 2252 2253 usbd_status 2254 uhci_device_ctrl_start(usbd_xfer_handle xfer) 2255 { 2256 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2257 usbd_status err; 2258 2259 if (sc->sc_dying) 2260 return (USBD_IOERROR); 2261 2262 #ifdef DIAGNOSTIC 2263 if (!(xfer->rqflags & URQ_REQUEST)) 2264 panic("uhci_device_ctrl_transfer: not a request"); 2265 #endif 2266 2267 mutex_enter(&sc->sc_lock); 2268 err = uhci_device_request(xfer); 2269 mutex_exit(&sc->sc_lock); 2270 if (err) 2271 return (err); 2272 2273 if (sc->sc_bus.use_polling) 2274 uhci_waitintr(sc, xfer); 2275 return (USBD_IN_PROGRESS); 2276 } 2277 2278 usbd_status 2279 uhci_device_intr_transfer(usbd_xfer_handle xfer) 2280 { 2281 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2282 usbd_status err; 2283 2284 /* Insert last in queue. */ 2285 mutex_enter(&sc->sc_lock); 2286 err = usb_insert_transfer(xfer); 2287 mutex_exit(&sc->sc_lock); 2288 if (err) 2289 return (err); 2290 2291 /* 2292 * Pipe isn't running (otherwise err would be USBD_INPROG), 2293 * so start it first. 2294 */ 2295 return (uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2296 } 2297 2298 usbd_status 2299 uhci_device_intr_start(usbd_xfer_handle xfer) 2300 { 2301 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2302 usbd_device_handle dev = upipe->pipe.device; 2303 uhci_softc_t *sc = dev->bus->hci_private; 2304 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2305 uhci_soft_td_t *data, *dataend; 2306 uhci_soft_qh_t *sqh; 2307 usbd_status err; 2308 int isread, endpt; 2309 int i; 2310 2311 if (sc->sc_dying) 2312 return (USBD_IOERROR); 2313 2314 DPRINTFN(3,("uhci_device_intr_transfer: xfer=%p len=%d flags=%d\n", 2315 xfer, xfer->length, xfer->flags)); 2316 2317 #ifdef DIAGNOSTIC 2318 if (xfer->rqflags & URQ_REQUEST) 2319 panic("uhci_device_intr_transfer: a request"); 2320 #endif 2321 2322 endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2323 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2324 2325 upipe->u.intr.isread = isread; 2326 2327 err = uhci_alloc_std_chain(upipe, sc, xfer->length, isread, 2328 xfer->flags, &xfer->dmabuf, &data, 2329 &dataend); 2330 if (err) 2331 return (err); 2332 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2333 usb_syncmem(&dataend->dma, 2334 dataend->offs + offsetof(uhci_td_t, td_status), 2335 sizeof(dataend->td.td_status), 2336 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2337 2338 #ifdef UHCI_DEBUG 2339 if (uhcidebug > 10) { 2340 DPRINTF(("uhci_device_intr_transfer: data(1)\n")); 2341 uhci_dump_tds(data); 2342 uhci_dump_qh(upipe->u.intr.qhs[0]); 2343 } 2344 #endif 2345 2346 mutex_enter(&sc->sc_lock); 2347 /* Set up interrupt info. */ 2348 ii->xfer = xfer; 2349 ii->stdstart = data; 2350 ii->stdend = dataend; 2351 #ifdef DIAGNOSTIC 2352 if (!ii->isdone) { 2353 printf("uhci_device_intr_transfer: not done, ii=%p\n", ii); 2354 } 2355 ii->isdone = 0; 2356 #endif 2357 2358 DPRINTFN(10,("uhci_device_intr_transfer: qhs[0]=%p\n", 2359 upipe->u.intr.qhs[0])); 2360 for (i = 0; i < upipe->u.intr.npoll; i++) { 2361 sqh = upipe->u.intr.qhs[i]; 2362 sqh->elink = data; 2363 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2364 usb_syncmem(&sqh->dma, 2365 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2366 sizeof(sqh->qh.qh_elink), 2367 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2368 } 2369 uhci_add_intr_info(sc, ii); 2370 xfer->status = USBD_IN_PROGRESS; 2371 mutex_exit(&sc->sc_lock); 2372 2373 #ifdef UHCI_DEBUG 2374 if (uhcidebug > 10) { 2375 DPRINTF(("uhci_device_intr_transfer: data(2)\n")); 2376 uhci_dump_tds(data); 2377 uhci_dump_qh(upipe->u.intr.qhs[0]); 2378 } 2379 #endif 2380 2381 return (USBD_IN_PROGRESS); 2382 } 2383 2384 /* Abort a device control request. */ 2385 void 2386 uhci_device_ctrl_abort(usbd_xfer_handle xfer) 2387 { 2388 #ifdef DIAGNOSTIC 2389 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2390 #endif 2391 2392 KASSERT(mutex_owned(&sc->sc_lock)); 2393 2394 DPRINTF(("uhci_device_ctrl_abort:\n")); 2395 uhci_abort_xfer(xfer, USBD_CANCELLED); 2396 } 2397 2398 /* Close a device control pipe. */ 2399 void 2400 uhci_device_ctrl_close(usbd_pipe_handle pipe) 2401 { 2402 } 2403 2404 /* Abort a device interrupt request. */ 2405 void 2406 uhci_device_intr_abort(usbd_xfer_handle xfer) 2407 { 2408 #ifdef DIAGNOSTIC 2409 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2410 #endif 2411 2412 KASSERT(mutex_owned(&sc->sc_lock)); 2413 2414 DPRINTFN(1,("uhci_device_intr_abort: xfer=%p\n", xfer)); 2415 if (xfer->pipe->intrxfer == xfer) { 2416 DPRINTFN(1,("uhci_device_intr_abort: remove\n")); 2417 xfer->pipe->intrxfer = NULL; 2418 } 2419 uhci_abort_xfer(xfer, USBD_CANCELLED); 2420 } 2421 2422 /* Close a device interrupt pipe. */ 2423 void 2424 uhci_device_intr_close(usbd_pipe_handle pipe) 2425 { 2426 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2427 uhci_softc_t *sc = pipe->device->bus->hci_private; 2428 int i, npoll; 2429 2430 KASSERT(mutex_owned(&sc->sc_lock)); 2431 2432 /* Unlink descriptors from controller data structures. */ 2433 npoll = upipe->u.intr.npoll; 2434 for (i = 0; i < npoll; i++) 2435 uhci_remove_intr(sc, upipe->u.intr.qhs[i]); 2436 2437 /* 2438 * We now have to wait for any activity on the physical 2439 * descriptors to stop. 2440 */ 2441 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2442 2443 for(i = 0; i < npoll; i++) 2444 uhci_free_sqh(sc, upipe->u.intr.qhs[i]); 2445 kmem_free(upipe->u.intr.qhs, npoll * sizeof(uhci_soft_qh_t *)); 2446 2447 /* XXX free other resources */ 2448 } 2449 2450 usbd_status 2451 uhci_device_request(usbd_xfer_handle xfer) 2452 { 2453 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2454 usb_device_request_t *req = &xfer->request; 2455 usbd_device_handle dev = upipe->pipe.device; 2456 uhci_softc_t *sc = dev->bus->hci_private; 2457 int addr = dev->address; 2458 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2459 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2460 uhci_soft_td_t *setup, *data, *stat, *next, *dataend; 2461 uhci_soft_qh_t *sqh; 2462 int len; 2463 u_int32_t ls; 2464 usbd_status err; 2465 int isread; 2466 2467 KASSERT(mutex_owned(&sc->sc_lock)); 2468 2469 DPRINTFN(3,("uhci_device_control type=0x%02x, request=0x%02x, " 2470 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 2471 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2472 UGETW(req->wIndex), UGETW(req->wLength), 2473 addr, endpt)); 2474 2475 ls = dev->speed == USB_SPEED_LOW ? UHCI_TD_LS : 0; 2476 isread = req->bmRequestType & UT_READ; 2477 len = UGETW(req->wLength); 2478 2479 setup = upipe->u.ctl.setup; 2480 stat = upipe->u.ctl.stat; 2481 sqh = upipe->u.ctl.sqh; 2482 2483 /* Set up data transaction */ 2484 if (len != 0) { 2485 upipe->nexttoggle = 1; 2486 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->flags, 2487 &xfer->dmabuf, &data, &dataend); 2488 if (err) 2489 return (err); 2490 next = data; 2491 dataend->link.std = stat; 2492 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_VF | UHCI_PTR_TD); 2493 usb_syncmem(&dataend->dma, 2494 dataend->offs + offsetof(uhci_td_t, td_link), 2495 sizeof(dataend->td.td_link), 2496 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2497 } else { 2498 next = stat; 2499 } 2500 upipe->u.ctl.length = len; 2501 2502 memcpy(KERNADDR(&upipe->u.ctl.reqdma, 0), req, sizeof *req); 2503 usb_syncmem(&upipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 2504 2505 setup->link.std = next; 2506 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_VF | UHCI_PTR_TD); 2507 setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2508 UHCI_TD_ACTIVE); 2509 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof *req, endpt, addr)); 2510 setup->td.td_buffer = htole32(DMAADDR(&upipe->u.ctl.reqdma, 0)); 2511 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2512 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2513 2514 stat->link.std = NULL; 2515 stat->td.td_link = htole32(UHCI_PTR_T); 2516 stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2517 UHCI_TD_ACTIVE | UHCI_TD_IOC); 2518 stat->td.td_token = 2519 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2520 UHCI_TD_IN (0, endpt, addr, 1)); 2521 stat->td.td_buffer = htole32(0); 2522 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2523 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2524 2525 #ifdef UHCI_DEBUG 2526 if (uhcidebug > 10) { 2527 DPRINTF(("uhci_device_request: before transfer\n")); 2528 uhci_dump_tds(setup); 2529 } 2530 #endif 2531 2532 /* Set up interrupt info. */ 2533 ii->xfer = xfer; 2534 ii->stdstart = setup; 2535 ii->stdend = stat; 2536 #ifdef DIAGNOSTIC 2537 if (!ii->isdone) { 2538 printf("uhci_device_request: not done, ii=%p\n", ii); 2539 } 2540 ii->isdone = 0; 2541 #endif 2542 2543 sqh->elink = setup; 2544 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2545 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2546 2547 if (dev->speed == USB_SPEED_LOW) 2548 uhci_add_ls_ctrl(sc, sqh); 2549 else 2550 uhci_add_hs_ctrl(sc, sqh); 2551 uhci_add_intr_info(sc, ii); 2552 #ifdef UHCI_DEBUG 2553 if (uhcidebug > 12) { 2554 uhci_soft_td_t *std; 2555 uhci_soft_qh_t *xqh; 2556 uhci_soft_qh_t *sxqh; 2557 int maxqh = 0; 2558 uhci_physaddr_t link; 2559 DPRINTF(("uhci_enter_ctl_q: follow from [0]\n")); 2560 for (std = sc->sc_vframes[0].htd, link = 0; 2561 (link & UHCI_PTR_QH) == 0; 2562 std = std->link.std) { 2563 link = le32toh(std->td.td_link); 2564 uhci_dump_td(std); 2565 } 2566 sxqh = (uhci_soft_qh_t *)std; 2567 uhci_dump_qh(sxqh); 2568 for (xqh = sxqh; 2569 xqh != NULL; 2570 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2571 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2572 uhci_dump_qh(xqh); 2573 } 2574 DPRINTF(("Enqueued QH:\n")); 2575 uhci_dump_qh(sqh); 2576 uhci_dump_tds(sqh->elink); 2577 } 2578 #endif 2579 if (xfer->timeout && !sc->sc_bus.use_polling) { 2580 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 2581 uhci_timeout, ii); 2582 } 2583 xfer->status = USBD_IN_PROGRESS; 2584 2585 return (USBD_NORMAL_COMPLETION); 2586 } 2587 2588 usbd_status 2589 uhci_device_isoc_transfer(usbd_xfer_handle xfer) 2590 { 2591 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2592 usbd_status err; 2593 2594 DPRINTFN(5,("uhci_device_isoc_transfer: xfer=%p\n", xfer)); 2595 2596 /* Put it on our queue, */ 2597 mutex_enter(&sc->sc_lock); 2598 err = usb_insert_transfer(xfer); 2599 mutex_exit(&sc->sc_lock); 2600 2601 /* bail out on error, */ 2602 if (err && err != USBD_IN_PROGRESS) 2603 return (err); 2604 2605 /* XXX should check inuse here */ 2606 2607 /* insert into schedule, */ 2608 uhci_device_isoc_enter(xfer); 2609 2610 /* and start if the pipe wasn't running */ 2611 if (!err) 2612 uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 2613 2614 return (err); 2615 } 2616 2617 void 2618 uhci_device_isoc_enter(usbd_xfer_handle xfer) 2619 { 2620 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2621 usbd_device_handle dev = upipe->pipe.device; 2622 uhci_softc_t *sc = dev->bus->hci_private; 2623 struct iso *iso = &upipe->u.iso; 2624 uhci_soft_td_t *std; 2625 u_int32_t buf, len, status, offs; 2626 int i, next, nframes; 2627 int rd = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2628 2629 DPRINTFN(5,("uhci_device_isoc_enter: used=%d next=%d xfer=%p " 2630 "nframes=%d\n", 2631 iso->inuse, iso->next, xfer, xfer->nframes)); 2632 2633 if (sc->sc_dying) 2634 return; 2635 2636 if (xfer->status == USBD_IN_PROGRESS) { 2637 /* This request has already been entered into the frame list */ 2638 printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer); 2639 /* XXX */ 2640 } 2641 2642 #ifdef DIAGNOSTIC 2643 if (iso->inuse >= UHCI_VFRAMELIST_COUNT) 2644 printf("uhci_device_isoc_enter: overflow!\n"); 2645 #endif 2646 2647 next = iso->next; 2648 if (next == -1) { 2649 /* Not in use yet, schedule it a few frames ahead. */ 2650 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 2651 DPRINTFN(2,("uhci_device_isoc_enter: start next=%d\n", next)); 2652 } 2653 2654 xfer->status = USBD_IN_PROGRESS; 2655 UXFER(xfer)->curframe = next; 2656 2657 buf = DMAADDR(&xfer->dmabuf, 0); 2658 offs = 0; 2659 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 2660 UHCI_TD_ACTIVE | 2661 UHCI_TD_IOS); 2662 nframes = xfer->nframes; 2663 mutex_enter(&sc->sc_lock); 2664 for (i = 0; i < nframes; i++) { 2665 std = iso->stds[next]; 2666 if (++next >= UHCI_VFRAMELIST_COUNT) 2667 next = 0; 2668 len = xfer->frlengths[i]; 2669 std->td.td_buffer = htole32(buf); 2670 usb_syncmem(&xfer->dmabuf, offs, len, 2671 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2672 if (i == nframes - 1) 2673 status |= UHCI_TD_IOC; 2674 std->td.td_status = htole32(status); 2675 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2676 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 2677 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2678 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2679 #ifdef UHCI_DEBUG 2680 if (uhcidebug > 5) { 2681 DPRINTFN(5,("uhci_device_isoc_enter: TD %d\n", i)); 2682 uhci_dump_td(std); 2683 } 2684 #endif 2685 buf += len; 2686 offs += len; 2687 } 2688 iso->next = next; 2689 iso->inuse += xfer->nframes; 2690 2691 mutex_exit(&sc->sc_lock); 2692 } 2693 2694 usbd_status 2695 uhci_device_isoc_start(usbd_xfer_handle xfer) 2696 { 2697 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2698 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 2699 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2700 uhci_soft_td_t *end; 2701 int i; 2702 2703 DPRINTFN(5,("uhci_device_isoc_start: xfer=%p\n", xfer)); 2704 2705 mutex_enter(&sc->sc_lock); 2706 2707 if (sc->sc_dying) { 2708 mutex_exit(&sc->sc_lock); 2709 return (USBD_IOERROR); 2710 } 2711 2712 #ifdef DIAGNOSTIC 2713 if (xfer->status != USBD_IN_PROGRESS) 2714 printf("uhci_device_isoc_start: not in progress %p\n", xfer); 2715 #endif 2716 2717 /* Find the last TD */ 2718 i = UXFER(xfer)->curframe + xfer->nframes; 2719 if (i >= UHCI_VFRAMELIST_COUNT) 2720 i -= UHCI_VFRAMELIST_COUNT; 2721 end = upipe->u.iso.stds[i]; 2722 2723 #ifdef DIAGNOSTIC 2724 if (end == NULL) { 2725 printf("uhci_device_isoc_start: end == NULL\n"); 2726 return (USBD_INVAL); 2727 } 2728 #endif 2729 2730 /* Set up interrupt info. */ 2731 ii->xfer = xfer; 2732 ii->stdstart = end; 2733 ii->stdend = end; 2734 #ifdef DIAGNOSTIC 2735 if (!ii->isdone) 2736 printf("uhci_device_isoc_start: not done, ii=%p\n", ii); 2737 ii->isdone = 0; 2738 #endif 2739 uhci_add_intr_info(sc, ii); 2740 2741 mutex_exit(&sc->sc_lock); 2742 2743 return (USBD_IN_PROGRESS); 2744 } 2745 2746 void 2747 uhci_device_isoc_abort(usbd_xfer_handle xfer) 2748 { 2749 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2750 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2751 uhci_soft_td_t **stds = upipe->u.iso.stds; 2752 uhci_soft_td_t *std; 2753 int i, n, nframes, maxlen, len; 2754 2755 KASSERT(mutex_owned(&sc->sc_lock)); 2756 2757 /* Transfer is already done. */ 2758 if (xfer->status != USBD_NOT_STARTED && 2759 xfer->status != USBD_IN_PROGRESS) { 2760 return; 2761 } 2762 2763 /* Give xfer the requested abort code. */ 2764 xfer->status = USBD_CANCELLED; 2765 2766 /* make hardware ignore it, */ 2767 nframes = xfer->nframes; 2768 n = UXFER(xfer)->curframe; 2769 maxlen = 0; 2770 for (i = 0; i < nframes; i++) { 2771 std = stds[n]; 2772 usb_syncmem(&std->dma, 2773 std->offs + offsetof(uhci_td_t, td_status), 2774 sizeof(std->td.td_status), 2775 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2776 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2777 usb_syncmem(&std->dma, 2778 std->offs + offsetof(uhci_td_t, td_status), 2779 sizeof(std->td.td_status), 2780 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2781 usb_syncmem(&std->dma, 2782 std->offs + offsetof(uhci_td_t, td_token), 2783 sizeof(std->td.td_token), 2784 BUS_DMASYNC_POSTWRITE); 2785 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 2786 if (len > maxlen) 2787 maxlen = len; 2788 if (++n >= UHCI_VFRAMELIST_COUNT) 2789 n = 0; 2790 } 2791 2792 /* and wait until we are sure the hardware has finished. */ 2793 delay(maxlen); 2794 2795 #ifdef DIAGNOSTIC 2796 UXFER(xfer)->iinfo.isdone = 1; 2797 #endif 2798 /* Run callback and remove from interrupt list. */ 2799 usb_transfer_complete(xfer); 2800 2801 KASSERT(mutex_owned(&sc->sc_lock)); 2802 } 2803 2804 void 2805 uhci_device_isoc_close(usbd_pipe_handle pipe) 2806 { 2807 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2808 usbd_device_handle dev = upipe->pipe.device; 2809 uhci_softc_t *sc = dev->bus->hci_private; 2810 uhci_soft_td_t *std, *vstd; 2811 struct iso *iso; 2812 int i; 2813 2814 KASSERT(mutex_owned(&sc->sc_lock)); 2815 2816 /* 2817 * Make sure all TDs are marked as inactive. 2818 * Wait for completion. 2819 * Unschedule. 2820 * Deallocate. 2821 */ 2822 iso = &upipe->u.iso; 2823 2824 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2825 std = iso->stds[i]; 2826 usb_syncmem(&std->dma, 2827 std->offs + offsetof(uhci_td_t, td_status), 2828 sizeof(std->td.td_status), 2829 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2830 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 2831 usb_syncmem(&std->dma, 2832 std->offs + offsetof(uhci_td_t, td_status), 2833 sizeof(std->td.td_status), 2834 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2835 } 2836 /* wait for completion */ 2837 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2838 2839 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2840 std = iso->stds[i]; 2841 for (vstd = sc->sc_vframes[i].htd; 2842 vstd != NULL && vstd->link.std != std; 2843 vstd = vstd->link.std) 2844 ; 2845 if (vstd == NULL) { 2846 /*panic*/ 2847 printf("uhci_device_isoc_close: %p not found\n", std); 2848 mutex_exit(&sc->sc_lock); 2849 return; 2850 } 2851 vstd->link = std->link; 2852 usb_syncmem(&std->dma, 2853 std->offs + offsetof(uhci_td_t, td_link), 2854 sizeof(std->td.td_link), 2855 BUS_DMASYNC_POSTWRITE); 2856 vstd->td.td_link = std->td.td_link; 2857 usb_syncmem(&vstd->dma, 2858 vstd->offs + offsetof(uhci_td_t, td_link), 2859 sizeof(vstd->td.td_link), 2860 BUS_DMASYNC_PREWRITE); 2861 uhci_free_std(sc, std); 2862 } 2863 2864 kmem_free(iso->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *)); 2865 } 2866 2867 usbd_status 2868 uhci_setup_isoc(usbd_pipe_handle pipe) 2869 { 2870 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2871 usbd_device_handle dev = upipe->pipe.device; 2872 uhci_softc_t *sc = dev->bus->hci_private; 2873 int addr = upipe->pipe.device->address; 2874 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2875 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 2876 uhci_soft_td_t *std, *vstd; 2877 u_int32_t token; 2878 struct iso *iso; 2879 int i; 2880 2881 iso = &upipe->u.iso; 2882 iso->stds = kmem_alloc(UHCI_VFRAMELIST_COUNT * 2883 sizeof (uhci_soft_td_t *), 2884 KM_SLEEP); 2885 if (iso->stds == NULL) 2886 return USBD_NOMEM; 2887 2888 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 2889 UHCI_TD_OUT(0, endpt, addr, 0); 2890 2891 mutex_enter(&sc->sc_lock); 2892 2893 /* Allocate the TDs and mark as inactive; */ 2894 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2895 std = uhci_alloc_std(sc); 2896 if (std == 0) 2897 goto bad; 2898 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 2899 std->td.td_token = htole32(token); 2900 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2901 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2902 iso->stds[i] = std; 2903 } 2904 2905 /* Insert TDs into schedule. */ 2906 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2907 std = iso->stds[i]; 2908 vstd = sc->sc_vframes[i].htd; 2909 usb_syncmem(&vstd->dma, 2910 vstd->offs + offsetof(uhci_td_t, td_link), 2911 sizeof(vstd->td.td_link), 2912 BUS_DMASYNC_POSTWRITE); 2913 std->link = vstd->link; 2914 std->td.td_link = vstd->td.td_link; 2915 usb_syncmem(&std->dma, 2916 std->offs + offsetof(uhci_td_t, td_link), 2917 sizeof(std->td.td_link), 2918 BUS_DMASYNC_PREWRITE); 2919 vstd->link.std = std; 2920 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 2921 usb_syncmem(&vstd->dma, 2922 vstd->offs + offsetof(uhci_td_t, td_link), 2923 sizeof(vstd->td.td_link), 2924 BUS_DMASYNC_PREWRITE); 2925 } 2926 mutex_exit(&sc->sc_lock); 2927 2928 iso->next = -1; 2929 iso->inuse = 0; 2930 2931 return (USBD_NORMAL_COMPLETION); 2932 2933 bad: 2934 while (--i >= 0) 2935 uhci_free_std(sc, iso->stds[i]); 2936 mutex_exit(&sc->sc_lock); 2937 kmem_free(iso->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *)); 2938 return (USBD_NOMEM); 2939 } 2940 2941 void 2942 uhci_device_isoc_done(usbd_xfer_handle xfer) 2943 { 2944 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2945 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2946 int i, offs; 2947 int rd = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2948 2949 2950 DPRINTFN(4, ("uhci_isoc_done: length=%d, busy_free=0x%08x\n", 2951 xfer->actlen, xfer->busy_free)); 2952 2953 if (ii->xfer != xfer) 2954 /* Not on interrupt list, ignore it. */ 2955 return; 2956 2957 if (!uhci_active_intr_info(ii)) 2958 return; 2959 2960 #ifdef DIAGNOSTIC 2961 if (ii->stdend == NULL) { 2962 printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer); 2963 #ifdef UHCI_DEBUG 2964 uhci_dump_ii(ii); 2965 #endif 2966 return; 2967 } 2968 #endif 2969 2970 /* Turn off the interrupt since it is active even if the TD is not. */ 2971 usb_syncmem(&ii->stdend->dma, 2972 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2973 sizeof(ii->stdend->td.td_status), 2974 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2975 ii->stdend->td.td_status &= htole32(~UHCI_TD_IOC); 2976 usb_syncmem(&ii->stdend->dma, 2977 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2978 sizeof(ii->stdend->td.td_status), 2979 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2980 2981 uhci_del_intr_info(ii); /* remove from active list */ 2982 2983 offs = 0; 2984 for (i = 0; i < xfer->nframes; i++) { 2985 usb_syncmem(&xfer->dmabuf, offs, xfer->frlengths[i], 2986 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2987 offs += xfer->frlengths[i]; 2988 } 2989 } 2990 2991 void 2992 uhci_device_intr_done(usbd_xfer_handle xfer) 2993 { 2994 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2995 uhci_softc_t *sc = ii->sc; 2996 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2997 uhci_soft_qh_t *sqh; 2998 int i, npoll, isread; 2999 3000 DPRINTFN(5, ("uhci_device_intr_done: length=%d\n", xfer->actlen)); 3001 3002 KASSERT(mutex_owned(&sc->sc_lock)); 3003 3004 npoll = upipe->u.intr.npoll; 3005 for(i = 0; i < npoll; i++) { 3006 sqh = upipe->u.intr.qhs[i]; 3007 sqh->elink = NULL; 3008 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3009 usb_syncmem(&sqh->dma, 3010 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3011 sizeof(sqh->qh.qh_elink), 3012 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3013 } 3014 uhci_free_std_chain(sc, ii->stdstart, NULL); 3015 3016 isread = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 3017 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3018 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3019 3020 /* XXX Wasteful. */ 3021 if (xfer->pipe->repeat) { 3022 uhci_soft_td_t *data, *dataend; 3023 3024 DPRINTFN(5,("uhci_device_intr_done: requeing\n")); 3025 3026 /* This alloc cannot fail since we freed the chain above. */ 3027 uhci_alloc_std_chain(upipe, sc, xfer->length, 3028 upipe->u.intr.isread, xfer->flags, 3029 &xfer->dmabuf, &data, &dataend); 3030 dataend->td.td_status |= htole32(UHCI_TD_IOC); 3031 usb_syncmem(&dataend->dma, 3032 dataend->offs + offsetof(uhci_td_t, td_status), 3033 sizeof(dataend->td.td_status), 3034 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3035 3036 #ifdef UHCI_DEBUG 3037 if (uhcidebug > 10) { 3038 DPRINTF(("uhci_device_intr_done: data(1)\n")); 3039 uhci_dump_tds(data); 3040 uhci_dump_qh(upipe->u.intr.qhs[0]); 3041 } 3042 #endif 3043 3044 ii->stdstart = data; 3045 ii->stdend = dataend; 3046 #ifdef DIAGNOSTIC 3047 if (!ii->isdone) { 3048 printf("uhci_device_intr_done: not done, ii=%p\n", ii); 3049 } 3050 ii->isdone = 0; 3051 #endif 3052 for (i = 0; i < npoll; i++) { 3053 sqh = upipe->u.intr.qhs[i]; 3054 sqh->elink = data; 3055 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 3056 usb_syncmem(&sqh->dma, 3057 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3058 sizeof(sqh->qh.qh_elink), 3059 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3060 } 3061 xfer->status = USBD_IN_PROGRESS; 3062 /* The ii is already on the examined list, just leave it. */ 3063 } else { 3064 DPRINTFN(5,("uhci_device_intr_done: removing\n")); 3065 if (uhci_active_intr_info(ii)) 3066 uhci_del_intr_info(ii); 3067 } 3068 } 3069 3070 /* Deallocate request data structures */ 3071 void 3072 uhci_device_ctrl_done(usbd_xfer_handle xfer) 3073 { 3074 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3075 uhci_softc_t *sc = ii->sc; 3076 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 3077 int len = UGETW(xfer->request.wLength); 3078 int isread = (xfer->request.bmRequestType & UT_READ); 3079 3080 KASSERT(mutex_owned(&sc->sc_lock)); 3081 3082 #ifdef DIAGNOSTIC 3083 if (!(xfer->rqflags & URQ_REQUEST)) 3084 panic("uhci_device_ctrl_done: not a request"); 3085 #endif 3086 3087 if (!uhci_active_intr_info(ii)) 3088 return; 3089 3090 uhci_del_intr_info(ii); /* remove from active list */ 3091 3092 if (upipe->pipe.device->speed == USB_SPEED_LOW) 3093 uhci_remove_ls_ctrl(sc, upipe->u.ctl.sqh); 3094 else 3095 uhci_remove_hs_ctrl(sc, upipe->u.ctl.sqh); 3096 3097 if (upipe->u.ctl.length != 0) 3098 uhci_free_std_chain(sc, ii->stdstart->link.std, ii->stdend); 3099 3100 if (len) { 3101 usb_syncmem(&xfer->dmabuf, 0, len, 3102 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3103 } 3104 usb_syncmem(&upipe->u.ctl.reqdma, 0, 3105 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3106 3107 DPRINTFN(5, ("uhci_device_ctrl_done: length=%d\n", xfer->actlen)); 3108 } 3109 3110 /* Deallocate request data structures */ 3111 void 3112 uhci_device_bulk_done(usbd_xfer_handle xfer) 3113 { 3114 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3115 uhci_softc_t *sc = ii->sc; 3116 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 3117 3118 DPRINTFN(5,("uhci_device_bulk_done: xfer=%p ii=%p sc=%p upipe=%p\n", 3119 xfer, ii, sc, upipe)); 3120 3121 KASSERT(mutex_owned(&sc->sc_lock)); 3122 3123 if (!uhci_active_intr_info(ii)) 3124 return; 3125 3126 uhci_del_intr_info(ii); /* remove from active list */ 3127 3128 uhci_remove_bulk(sc, upipe->u.bulk.sqh); 3129 3130 uhci_free_std_chain(sc, ii->stdstart, NULL); 3131 3132 DPRINTFN(5, ("uhci_device_bulk_done: length=%d\n", xfer->actlen)); 3133 } 3134 3135 /* Add interrupt QH, called with vflock. */ 3136 void 3137 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3138 { 3139 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3140 uhci_soft_qh_t *eqh; 3141 3142 DPRINTFN(4, ("uhci_add_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3143 3144 eqh = vf->eqh; 3145 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3146 sizeof(eqh->qh.qh_hlink), 3147 BUS_DMASYNC_POSTWRITE); 3148 sqh->hlink = eqh->hlink; 3149 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3150 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3151 sizeof(sqh->qh.qh_hlink), 3152 BUS_DMASYNC_PREWRITE); 3153 eqh->hlink = sqh; 3154 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3155 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3156 sizeof(eqh->qh.qh_hlink), 3157 BUS_DMASYNC_PREWRITE); 3158 vf->eqh = sqh; 3159 vf->bandwidth++; 3160 } 3161 3162 /* Remove interrupt QH. */ 3163 void 3164 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3165 { 3166 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3167 uhci_soft_qh_t *pqh; 3168 3169 DPRINTFN(4, ("uhci_remove_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3170 3171 /* See comment in uhci_remove_ctrl() */ 3172 3173 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3174 sizeof(sqh->qh.qh_elink), 3175 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3176 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3177 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3178 usb_syncmem(&sqh->dma, 3179 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3180 sizeof(sqh->qh.qh_elink), 3181 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3182 delay(UHCI_QH_REMOVE_DELAY); 3183 } 3184 3185 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3186 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3187 sizeof(sqh->qh.qh_hlink), 3188 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3189 pqh->hlink = sqh->hlink; 3190 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3191 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3192 sizeof(pqh->qh.qh_hlink), 3193 BUS_DMASYNC_PREWRITE); 3194 delay(UHCI_QH_REMOVE_DELAY); 3195 if (vf->eqh == sqh) 3196 vf->eqh = pqh; 3197 vf->bandwidth--; 3198 } 3199 3200 usbd_status 3201 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3202 { 3203 uhci_soft_qh_t *sqh; 3204 int i, npoll; 3205 u_int bestbw, bw, bestoffs, offs; 3206 3207 DPRINTFN(2, ("uhci_device_setintr: pipe=%p\n", upipe)); 3208 if (ival == 0) { 3209 printf("uhci_device_setintr: 0 interval\n"); 3210 return (USBD_INVAL); 3211 } 3212 3213 if (ival > UHCI_VFRAMELIST_COUNT) 3214 ival = UHCI_VFRAMELIST_COUNT; 3215 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3216 DPRINTFN(2, ("uhci_device_setintr: ival=%d npoll=%d\n", ival, npoll)); 3217 3218 upipe->u.intr.npoll = npoll; 3219 upipe->u.intr.qhs = 3220 kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP); 3221 if (upipe->u.intr.qhs == NULL) 3222 return USBD_NOMEM; 3223 3224 /* 3225 * Figure out which offset in the schedule that has most 3226 * bandwidth left over. 3227 */ 3228 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3229 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3230 for (bw = i = 0; i < npoll; i++) 3231 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3232 if (bw < bestbw) { 3233 bestbw = bw; 3234 bestoffs = offs; 3235 } 3236 } 3237 DPRINTFN(1, ("uhci_device_setintr: bw=%d offs=%d\n", bestbw, bestoffs)); 3238 3239 mutex_enter(&sc->sc_lock); 3240 for(i = 0; i < npoll; i++) { 3241 upipe->u.intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3242 sqh->elink = NULL; 3243 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3244 usb_syncmem(&sqh->dma, 3245 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3246 sizeof(sqh->qh.qh_elink), 3247 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3248 sqh->pos = MOD(i * ival + bestoffs); 3249 } 3250 #undef MOD 3251 3252 /* Enter QHs into the controller data structures. */ 3253 for(i = 0; i < npoll; i++) 3254 uhci_add_intr(sc, upipe->u.intr.qhs[i]); 3255 mutex_exit(&sc->sc_lock); 3256 3257 DPRINTFN(5, ("uhci_device_setintr: returns %p\n", upipe)); 3258 return (USBD_NORMAL_COMPLETION); 3259 } 3260 3261 /* Open a new pipe. */ 3262 usbd_status 3263 uhci_open(usbd_pipe_handle pipe) 3264 { 3265 uhci_softc_t *sc = pipe->device->bus->hci_private; 3266 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 3267 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 3268 usbd_status err = USBD_NOMEM; 3269 int ival; 3270 3271 DPRINTFN(1, ("uhci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 3272 pipe, pipe->device->address, 3273 ed->bEndpointAddress, sc->sc_addr)); 3274 3275 if (sc->sc_dying) 3276 return USBD_IOERROR; 3277 3278 upipe->aborting = 0; 3279 /* toggle state needed for bulk endpoints */ 3280 upipe->nexttoggle = pipe->endpoint->datatoggle; 3281 3282 if (pipe->device->address == sc->sc_addr) { 3283 switch (ed->bEndpointAddress) { 3284 case USB_CONTROL_ENDPOINT: 3285 pipe->methods = &uhci_root_ctrl_methods; 3286 break; 3287 case UE_DIR_IN | UHCI_INTR_ENDPT: 3288 pipe->methods = &uhci_root_intr_methods; 3289 break; 3290 default: 3291 return (USBD_INVAL); 3292 } 3293 } else { 3294 switch (ed->bmAttributes & UE_XFERTYPE) { 3295 case UE_CONTROL: 3296 pipe->methods = &uhci_device_ctrl_methods; 3297 upipe->u.ctl.sqh = uhci_alloc_sqh(sc); 3298 if (upipe->u.ctl.sqh == NULL) 3299 goto bad; 3300 upipe->u.ctl.setup = uhci_alloc_std(sc); 3301 if (upipe->u.ctl.setup == NULL) { 3302 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3303 goto bad; 3304 } 3305 upipe->u.ctl.stat = uhci_alloc_std(sc); 3306 if (upipe->u.ctl.stat == NULL) { 3307 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3308 uhci_free_std(sc, upipe->u.ctl.setup); 3309 goto bad; 3310 } 3311 err = usb_allocmem(&sc->sc_bus, 3312 sizeof(usb_device_request_t), 3313 0, &upipe->u.ctl.reqdma); 3314 if (err) { 3315 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3316 uhci_free_std(sc, upipe->u.ctl.setup); 3317 uhci_free_std(sc, upipe->u.ctl.stat); 3318 goto bad; 3319 } 3320 break; 3321 case UE_INTERRUPT: 3322 pipe->methods = &uhci_device_intr_methods; 3323 ival = pipe->interval; 3324 if (ival == USBD_DEFAULT_INTERVAL) 3325 ival = ed->bInterval; 3326 return (uhci_device_setintr(sc, upipe, ival)); 3327 case UE_ISOCHRONOUS: 3328 pipe->methods = &uhci_device_isoc_methods; 3329 return (uhci_setup_isoc(pipe)); 3330 case UE_BULK: 3331 pipe->methods = &uhci_device_bulk_methods; 3332 upipe->u.bulk.sqh = uhci_alloc_sqh(sc); 3333 if (upipe->u.bulk.sqh == NULL) 3334 goto bad; 3335 break; 3336 } 3337 } 3338 return (USBD_NORMAL_COMPLETION); 3339 3340 bad: 3341 return USBD_NOMEM; 3342 } 3343 3344 /* 3345 * Data structures and routines to emulate the root hub. 3346 */ 3347 usb_device_descriptor_t uhci_devd = { 3348 USB_DEVICE_DESCRIPTOR_SIZE, 3349 UDESC_DEVICE, /* type */ 3350 {0x00, 0x01}, /* USB version */ 3351 UDCLASS_HUB, /* class */ 3352 UDSUBCLASS_HUB, /* subclass */ 3353 UDPROTO_FSHUB, /* protocol */ 3354 64, /* max packet */ 3355 {0},{0},{0x00,0x01}, /* device id */ 3356 1,2,0, /* string indicies */ 3357 1 /* # of configurations */ 3358 }; 3359 3360 const usb_config_descriptor_t uhci_confd = { 3361 USB_CONFIG_DESCRIPTOR_SIZE, 3362 UDESC_CONFIG, 3363 {USB_CONFIG_DESCRIPTOR_SIZE + 3364 USB_INTERFACE_DESCRIPTOR_SIZE + 3365 USB_ENDPOINT_DESCRIPTOR_SIZE}, 3366 1, 3367 1, 3368 0, 3369 UC_ATTR_MBO | UC_SELF_POWERED, 3370 0 /* max power */ 3371 }; 3372 3373 const usb_interface_descriptor_t uhci_ifcd = { 3374 USB_INTERFACE_DESCRIPTOR_SIZE, 3375 UDESC_INTERFACE, 3376 0, 3377 0, 3378 1, 3379 UICLASS_HUB, 3380 UISUBCLASS_HUB, 3381 UIPROTO_FSHUB, 3382 0 3383 }; 3384 3385 const usb_endpoint_descriptor_t uhci_endpd = { 3386 USB_ENDPOINT_DESCRIPTOR_SIZE, 3387 UDESC_ENDPOINT, 3388 UE_DIR_IN | UHCI_INTR_ENDPT, 3389 UE_INTERRUPT, 3390 {8}, 3391 255 3392 }; 3393 3394 const usb_hub_descriptor_t uhci_hubd_piix = { 3395 USB_HUB_DESCRIPTOR_SIZE, 3396 UDESC_HUB, 3397 2, 3398 { UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0 }, 3399 50, /* power on to power good */ 3400 0, 3401 { 0x00 }, /* both ports are removable */ 3402 { 0 }, 3403 }; 3404 3405 /* 3406 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3407 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3408 * should not be used by the USB subsystem. As we cannot issue a 3409 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3410 * will be enabled as part of the reset. 3411 * 3412 * On the VT83C572, the port cannot be successfully enabled until the 3413 * outstanding "port enable change" and "connection status change" 3414 * events have been reset. 3415 */ 3416 Static usbd_status 3417 uhci_portreset(uhci_softc_t *sc, int index) 3418 { 3419 int lim, port, x; 3420 3421 if (index == 1) 3422 port = UHCI_PORTSC1; 3423 else if (index == 2) 3424 port = UHCI_PORTSC2; 3425 else 3426 return (USBD_IOERROR); 3427 3428 x = URWMASK(UREAD2(sc, port)); 3429 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3430 3431 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3432 3433 DPRINTFN(3,("uhci port %d reset, status0 = 0x%04x\n", 3434 index, UREAD2(sc, port))); 3435 3436 x = URWMASK(UREAD2(sc, port)); 3437 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3438 3439 delay(100); 3440 3441 DPRINTFN(3,("uhci port %d reset, status1 = 0x%04x\n", 3442 index, UREAD2(sc, port))); 3443 3444 x = URWMASK(UREAD2(sc, port)); 3445 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3446 3447 for (lim = 10; --lim > 0;) { 3448 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3449 3450 x = UREAD2(sc, port); 3451 3452 DPRINTFN(3,("uhci port %d iteration %u, status = 0x%04x\n", 3453 index, lim, x)); 3454 3455 if (!(x & UHCI_PORTSC_CCS)) { 3456 /* 3457 * No device is connected (or was disconnected 3458 * during reset). Consider the port reset. 3459 * The delay must be long enough to ensure on 3460 * the initial iteration that the device 3461 * connection will have been registered. 50ms 3462 * appears to be sufficient, but 20ms is not. 3463 */ 3464 DPRINTFN(3,("uhci port %d loop %u, device detached\n", 3465 index, lim)); 3466 break; 3467 } 3468 3469 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3470 /* 3471 * Port enabled changed and/or connection 3472 * status changed were set. Reset either or 3473 * both raised flags (by writing a 1 to that 3474 * bit), and wait again for state to settle. 3475 */ 3476 UWRITE2(sc, port, URWMASK(x) | 3477 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3478 continue; 3479 } 3480 3481 if (x & UHCI_PORTSC_PE) 3482 /* Port is enabled */ 3483 break; 3484 3485 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3486 } 3487 3488 DPRINTFN(3,("uhci port %d reset, status2 = 0x%04x\n", 3489 index, UREAD2(sc, port))); 3490 3491 if (lim <= 0) { 3492 DPRINTFN(1,("uhci port %d reset timed out\n", index)); 3493 return (USBD_TIMEOUT); 3494 } 3495 3496 sc->sc_isreset = 1; 3497 return (USBD_NORMAL_COMPLETION); 3498 } 3499 3500 /* 3501 * Simulate a hardware hub by handling all the necessary requests. 3502 */ 3503 usbd_status 3504 uhci_root_ctrl_transfer(usbd_xfer_handle xfer) 3505 { 3506 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3507 usbd_status err; 3508 3509 /* Insert last in queue. */ 3510 mutex_enter(&sc->sc_lock); 3511 err = usb_insert_transfer(xfer); 3512 mutex_exit(&sc->sc_lock); 3513 if (err) 3514 return (err); 3515 3516 /* 3517 * Pipe isn't running (otherwise err would be USBD_INPROG), 3518 * so start it first. 3519 */ 3520 return (uhci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3521 } 3522 3523 usbd_status 3524 uhci_root_ctrl_start(usbd_xfer_handle xfer) 3525 { 3526 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3527 usb_device_request_t *req; 3528 void *buf = NULL; 3529 int port, x; 3530 int len, value, index, status, change, l, totlen = 0; 3531 usb_port_status_t ps; 3532 usbd_status err; 3533 3534 if (sc->sc_dying) 3535 return (USBD_IOERROR); 3536 3537 #ifdef DIAGNOSTIC 3538 if (!(xfer->rqflags & URQ_REQUEST)) 3539 panic("uhci_root_ctrl_start: not a request"); 3540 #endif 3541 req = &xfer->request; 3542 3543 DPRINTFN(2,("uhci_root_ctrl_control type=0x%02x request=%02x\n", 3544 req->bmRequestType, req->bRequest)); 3545 3546 len = UGETW(req->wLength); 3547 value = UGETW(req->wValue); 3548 index = UGETW(req->wIndex); 3549 3550 if (len != 0) 3551 buf = KERNADDR(&xfer->dmabuf, 0); 3552 3553 #define C(x,y) ((x) | ((y) << 8)) 3554 switch(C(req->bRequest, req->bmRequestType)) { 3555 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3556 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3557 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3558 /* 3559 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3560 * for the integrated root hub. 3561 */ 3562 break; 3563 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3564 if (len > 0) { 3565 *(u_int8_t *)buf = sc->sc_conf; 3566 totlen = 1; 3567 } 3568 break; 3569 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3570 DPRINTFN(2,("uhci_root_ctrl_control wValue=0x%04x\n", value)); 3571 if (len == 0) 3572 break; 3573 switch(value >> 8) { 3574 case UDESC_DEVICE: 3575 if ((value & 0xff) != 0) { 3576 err = USBD_IOERROR; 3577 goto ret; 3578 } 3579 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 3580 USETW(uhci_devd.idVendor, sc->sc_id_vendor); 3581 memcpy(buf, &uhci_devd, l); 3582 break; 3583 case UDESC_CONFIG: 3584 if ((value & 0xff) != 0) { 3585 err = USBD_IOERROR; 3586 goto ret; 3587 } 3588 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 3589 memcpy(buf, &uhci_confd, l); 3590 buf = (char *)buf + l; 3591 len -= l; 3592 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 3593 totlen += l; 3594 memcpy(buf, &uhci_ifcd, l); 3595 buf = (char *)buf + l; 3596 len -= l; 3597 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 3598 totlen += l; 3599 memcpy(buf, &uhci_endpd, l); 3600 break; 3601 case UDESC_STRING: 3602 #define sd ((usb_string_descriptor_t *)buf) 3603 switch (value & 0xff) { 3604 case 0: /* Language table */ 3605 totlen = usb_makelangtbl(sd, len); 3606 break; 3607 case 1: /* Vendor */ 3608 totlen = usb_makestrdesc(sd, len, 3609 sc->sc_vendor); 3610 break; 3611 case 2: /* Product */ 3612 totlen = usb_makestrdesc(sd, len, 3613 "UHCI root hub"); 3614 break; 3615 } 3616 #undef sd 3617 break; 3618 default: 3619 err = USBD_IOERROR; 3620 goto ret; 3621 } 3622 break; 3623 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3624 if (len > 0) { 3625 *(u_int8_t *)buf = 0; 3626 totlen = 1; 3627 } 3628 break; 3629 case C(UR_GET_STATUS, UT_READ_DEVICE): 3630 if (len > 1) { 3631 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 3632 totlen = 2; 3633 } 3634 break; 3635 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3636 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3637 if (len > 1) { 3638 USETW(((usb_status_t *)buf)->wStatus, 0); 3639 totlen = 2; 3640 } 3641 break; 3642 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3643 if (value >= USB_MAX_DEVICES) { 3644 err = USBD_IOERROR; 3645 goto ret; 3646 } 3647 sc->sc_addr = value; 3648 break; 3649 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3650 if (value != 0 && value != 1) { 3651 err = USBD_IOERROR; 3652 goto ret; 3653 } 3654 sc->sc_conf = value; 3655 break; 3656 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3657 break; 3658 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3659 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3660 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3661 err = USBD_IOERROR; 3662 goto ret; 3663 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3664 break; 3665 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3666 break; 3667 /* Hub requests */ 3668 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3669 break; 3670 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3671 DPRINTFN(3, ("uhci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 3672 "port=%d feature=%d\n", 3673 index, value)); 3674 if (index == 1) 3675 port = UHCI_PORTSC1; 3676 else if (index == 2) 3677 port = UHCI_PORTSC2; 3678 else { 3679 err = USBD_IOERROR; 3680 goto ret; 3681 } 3682 switch(value) { 3683 case UHF_PORT_ENABLE: 3684 x = URWMASK(UREAD2(sc, port)); 3685 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3686 break; 3687 case UHF_PORT_SUSPEND: 3688 x = URWMASK(UREAD2(sc, port)); 3689 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3690 break; 3691 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3692 /* see USB2 spec ch. 7.1.7.7 */ 3693 usb_delay_ms(&sc->sc_bus, 20); 3694 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3695 /* 10ms resume delay must be provided by caller */ 3696 break; 3697 case UHF_PORT_RESET: 3698 x = URWMASK(UREAD2(sc, port)); 3699 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3700 break; 3701 case UHF_C_PORT_CONNECTION: 3702 x = URWMASK(UREAD2(sc, port)); 3703 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3704 break; 3705 case UHF_C_PORT_ENABLE: 3706 x = URWMASK(UREAD2(sc, port)); 3707 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3708 break; 3709 case UHF_C_PORT_OVER_CURRENT: 3710 x = URWMASK(UREAD2(sc, port)); 3711 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3712 break; 3713 case UHF_C_PORT_RESET: 3714 sc->sc_isreset = 0; 3715 err = USBD_NORMAL_COMPLETION; 3716 goto ret; 3717 case UHF_PORT_CONNECTION: 3718 case UHF_PORT_OVER_CURRENT: 3719 case UHF_PORT_POWER: 3720 case UHF_PORT_LOW_SPEED: 3721 case UHF_C_PORT_SUSPEND: 3722 default: 3723 err = USBD_IOERROR; 3724 goto ret; 3725 } 3726 break; 3727 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3728 if (index == 1) 3729 port = UHCI_PORTSC1; 3730 else if (index == 2) 3731 port = UHCI_PORTSC2; 3732 else { 3733 err = USBD_IOERROR; 3734 goto ret; 3735 } 3736 if (len > 0) { 3737 *(u_int8_t *)buf = 3738 (UREAD2(sc, port) & UHCI_PORTSC_LS) >> 3739 UHCI_PORTSC_LS_SHIFT; 3740 totlen = 1; 3741 } 3742 break; 3743 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3744 if (len == 0) 3745 break; 3746 if ((value & 0xff) != 0) { 3747 err = USBD_IOERROR; 3748 goto ret; 3749 } 3750 l = min(len, USB_HUB_DESCRIPTOR_SIZE); 3751 totlen = l; 3752 memcpy(buf, &uhci_hubd_piix, l); 3753 break; 3754 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3755 if (len != 4) { 3756 err = USBD_IOERROR; 3757 goto ret; 3758 } 3759 memset(buf, 0, len); 3760 totlen = len; 3761 break; 3762 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3763 if (index == 1) 3764 port = UHCI_PORTSC1; 3765 else if (index == 2) 3766 port = UHCI_PORTSC2; 3767 else { 3768 err = USBD_IOERROR; 3769 goto ret; 3770 } 3771 if (len != 4) { 3772 err = USBD_IOERROR; 3773 goto ret; 3774 } 3775 x = UREAD2(sc, port); 3776 status = change = 0; 3777 if (x & UHCI_PORTSC_CCS) 3778 status |= UPS_CURRENT_CONNECT_STATUS; 3779 if (x & UHCI_PORTSC_CSC) 3780 change |= UPS_C_CONNECT_STATUS; 3781 if (x & UHCI_PORTSC_PE) 3782 status |= UPS_PORT_ENABLED; 3783 if (x & UHCI_PORTSC_POEDC) 3784 change |= UPS_C_PORT_ENABLED; 3785 if (x & UHCI_PORTSC_OCI) 3786 status |= UPS_OVERCURRENT_INDICATOR; 3787 if (x & UHCI_PORTSC_OCIC) 3788 change |= UPS_C_OVERCURRENT_INDICATOR; 3789 if (x & UHCI_PORTSC_SUSP) 3790 status |= UPS_SUSPEND; 3791 if (x & UHCI_PORTSC_LSDA) 3792 status |= UPS_LOW_SPEED; 3793 status |= UPS_PORT_POWER; 3794 if (sc->sc_isreset) 3795 change |= UPS_C_PORT_RESET; 3796 USETW(ps.wPortStatus, status); 3797 USETW(ps.wPortChange, change); 3798 l = min(len, sizeof ps); 3799 memcpy(buf, &ps, l); 3800 totlen = l; 3801 break; 3802 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3803 err = USBD_IOERROR; 3804 goto ret; 3805 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3806 break; 3807 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3808 if (index == 1) 3809 port = UHCI_PORTSC1; 3810 else if (index == 2) 3811 port = UHCI_PORTSC2; 3812 else { 3813 err = USBD_IOERROR; 3814 goto ret; 3815 } 3816 switch(value) { 3817 case UHF_PORT_ENABLE: 3818 x = URWMASK(UREAD2(sc, port)); 3819 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3820 break; 3821 case UHF_PORT_SUSPEND: 3822 x = URWMASK(UREAD2(sc, port)); 3823 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 3824 break; 3825 case UHF_PORT_RESET: 3826 err = uhci_portreset(sc, index); 3827 goto ret; 3828 case UHF_PORT_POWER: 3829 /* Pretend we turned on power */ 3830 err = USBD_NORMAL_COMPLETION; 3831 goto ret; 3832 case UHF_C_PORT_CONNECTION: 3833 case UHF_C_PORT_ENABLE: 3834 case UHF_C_PORT_OVER_CURRENT: 3835 case UHF_PORT_CONNECTION: 3836 case UHF_PORT_OVER_CURRENT: 3837 case UHF_PORT_LOW_SPEED: 3838 case UHF_C_PORT_SUSPEND: 3839 case UHF_C_PORT_RESET: 3840 default: 3841 err = USBD_IOERROR; 3842 goto ret; 3843 } 3844 break; 3845 default: 3846 err = USBD_IOERROR; 3847 goto ret; 3848 } 3849 xfer->actlen = totlen; 3850 err = USBD_NORMAL_COMPLETION; 3851 ret: 3852 xfer->status = err; 3853 mutex_enter(&sc->sc_lock); 3854 usb_transfer_complete(xfer); 3855 mutex_exit(&sc->sc_lock); 3856 return (USBD_IN_PROGRESS); 3857 } 3858 3859 /* Abort a root control request. */ 3860 void 3861 uhci_root_ctrl_abort(usbd_xfer_handle xfer) 3862 { 3863 /* Nothing to do, all transfers are synchronous. */ 3864 } 3865 3866 /* Close the root pipe. */ 3867 void 3868 uhci_root_ctrl_close(usbd_pipe_handle pipe) 3869 { 3870 DPRINTF(("uhci_root_ctrl_close\n")); 3871 } 3872 3873 /* Abort a root interrupt request. */ 3874 void 3875 uhci_root_intr_abort(usbd_xfer_handle xfer) 3876 { 3877 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3878 3879 KASSERT(mutex_owned(&sc->sc_lock)); 3880 3881 callout_stop(&sc->sc_poll_handle); 3882 sc->sc_intr_xfer = NULL; 3883 3884 if (xfer->pipe->intrxfer == xfer) { 3885 DPRINTF(("uhci_root_intr_abort: remove\n")); 3886 xfer->pipe->intrxfer = 0; 3887 } 3888 xfer->status = USBD_CANCELLED; 3889 #ifdef DIAGNOSTIC 3890 UXFER(xfer)->iinfo.isdone = 1; 3891 #endif 3892 usb_transfer_complete(xfer); 3893 } 3894 3895 usbd_status 3896 uhci_root_intr_transfer(usbd_xfer_handle xfer) 3897 { 3898 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3899 usbd_status err; 3900 3901 /* Insert last in queue. */ 3902 mutex_enter(&sc->sc_lock); 3903 err = usb_insert_transfer(xfer); 3904 mutex_exit(&sc->sc_lock); 3905 if (err) 3906 return (err); 3907 3908 /* 3909 * Pipe isn't running (otherwise err would be USBD_INPROG), 3910 * start first 3911 */ 3912 return (uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3913 } 3914 3915 /* Start a transfer on the root interrupt pipe */ 3916 usbd_status 3917 uhci_root_intr_start(usbd_xfer_handle xfer) 3918 { 3919 usbd_pipe_handle pipe = xfer->pipe; 3920 uhci_softc_t *sc = pipe->device->bus->hci_private; 3921 unsigned int ival; 3922 3923 DPRINTFN(3, ("uhci_root_intr_start: xfer=%p len=%d flags=%d\n", 3924 xfer, xfer->length, xfer->flags)); 3925 3926 if (sc->sc_dying) 3927 return (USBD_IOERROR); 3928 3929 /* XXX temporary variable needed to avoid gcc3 warning */ 3930 ival = xfer->pipe->endpoint->edesc->bInterval; 3931 sc->sc_ival = mstohz(ival); 3932 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 3933 sc->sc_intr_xfer = xfer; 3934 return (USBD_IN_PROGRESS); 3935 } 3936 3937 /* Close the root interrupt pipe. */ 3938 void 3939 uhci_root_intr_close(usbd_pipe_handle pipe) 3940 { 3941 uhci_softc_t *sc = pipe->device->bus->hci_private; 3942 3943 KASSERT(mutex_owned(&sc->sc_lock)); 3944 3945 callout_stop(&sc->sc_poll_handle); 3946 sc->sc_intr_xfer = NULL; 3947 DPRINTF(("uhci_root_intr_close\n")); 3948 } 3949
Indexes created Tue Sep 30 17:09:57 GMT 2025